1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2014, Joyent, Inc. All rights reserved.
26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved.
28 */
29
30 /*
31 * Copyright (c) 2000 to 2010, LSI Corporation.
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms of all code within
35 * this file that is exclusively owned by LSI, with or without
36 * modification, is permitted provided that, in addition to the CDDL 1.0
37 * License requirements, the following conditions are met:
38 *
39 * Neither the name of the author nor the names of its contributors may be
40 * used to endorse or promote products derived from this software without
41 * specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 */
56
57 /*
58 * mptsas3 - This is a driver based on LSI Logic's MPT2.0/2.5 interface.
59 *
60 */
61
62 #if defined(lint) || defined(DEBUG)
63 #define MPTSAS_DEBUG
64 #endif
65
66 /*
67 * standard header files.
68 */
69 #include <sys/note.h>
70 #include <sys/scsi/scsi.h>
71 #include <sys/pci.h>
72 #include <sys/file.h>
73 #include <sys/policy.h>
74 #include <sys/model.h>
75 #include <sys/sysevent.h>
76 #include <sys/sysevent/eventdefs.h>
77 #include <sys/sysevent/dr.h>
78 #include <sys/sata/sata_defs.h>
79 #include <sys/scsi/generic/sas.h>
80 #include <sys/scsi/impl/scsi_sas.h>
81
82 #pragma pack(1)
83 #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_type.h>
84 #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2.h>
85 #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_cnfg.h>
86 #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_init.h>
87 #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_ioc.h>
88 #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_sas.h>
89 #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_tool.h>
90 #include <sys/scsi/adapters/mpt_sas3/mpi/mpi2_raid.h>
91 #pragma pack()
92
93 /*
94 * private header files.
95 *
96 */
97 #include <sys/scsi/impl/scsi_reset_notify.h>
98 #include <sys/scsi/adapters/mpt_sas3/mptsas3_var.h>
99 #include <sys/scsi/adapters/mpt_sas3/mptsas3_ioctl.h>
100 #include <sys/scsi/adapters/mpt_sas3/mptsas3_smhba.h>
101 #include <sys/scsi/adapters/mpt_sas3/mptsas3_hash.h>
102 #include <sys/raidioctl.h>
103
104 #include <sys/fs/dv_node.h> /* devfs_clean */
105
106 /*
107 * FMA header files
108 */
109 #include <sys/ddifm.h>
110 #include <sys/fm/protocol.h>
111 #include <sys/fm/util.h>
112 #include <sys/fm/io/ddi.h>
113
114 /*
115 * autoconfiguration data and routines.
116 */
117 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
118 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
119 static int mptsas_power(dev_info_t *dip, int component, int level);
120
121 /*
122 * cb_ops function
123 */
124 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
125 cred_t *credp, int *rval);
126 #ifdef __sparc
127 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
128 #else /* __sparc */
129 static int mptsas_quiesce(dev_info_t *devi);
130 #endif /* __sparc */
131
132 /*
133 * Resource initilaization for hardware
134 */
135 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
136 static void mptsas_disable_bus_master(mptsas_t *mpt);
137 static void mptsas_hba_fini(mptsas_t *mpt);
138 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
139 static int mptsas_hba_setup(mptsas_t *mpt);
140 static void mptsas_hba_teardown(mptsas_t *mpt);
141 static int mptsas_config_space_init(mptsas_t *mpt);
142 static void mptsas_config_space_fini(mptsas_t *mpt);
143 static void mptsas_iport_register(mptsas_t *mpt);
144 static int mptsas_smp_setup(mptsas_t *mpt);
145 static void mptsas_smp_teardown(mptsas_t *mpt);
146 static int mptsas_cache_create(mptsas_t *mpt);
147 static void mptsas_cache_destroy(mptsas_t *mpt);
148 static int mptsas_alloc_request_frames(mptsas_t *mpt);
149 static int mptsas_alloc_sense_bufs(mptsas_t *mpt);
150 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
151 static int mptsas_alloc_free_queue(mptsas_t *mpt);
152 static int mptsas_alloc_post_queue(mptsas_t *mpt);
153 static void mptsas_free_post_queue(mptsas_t *mpt);
154 static void mptsas_alloc_reply_args(mptsas_t *mpt);
155 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
156 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
157 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
158
159 /*
160 * SCSA function prototypes
161 */
162 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
163 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
164 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
165 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
166 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
167 int tgtonly);
168 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
169 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
170 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
171 int tgtlen, int flags, int (*callback)(), caddr_t arg);
172 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
173 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
174 struct scsi_pkt *pkt);
175 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
176 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
177 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
178 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
179 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
180 void (*callback)(caddr_t), caddr_t arg);
181 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
182 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
183 static int mptsas_scsi_quiesce(dev_info_t *dip);
184 static int mptsas_scsi_unquiesce(dev_info_t *dip);
185 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
186 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
187
188 /*
189 * SMP functions
190 */
191 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
192
193 /*
194 * internal function prototypes.
195 */
196 static void mptsas_list_add(mptsas_t *mpt);
197 static void mptsas_list_del(mptsas_t *mpt);
198
199 static int mptsas_quiesce_bus(mptsas_t *mpt);
200 static int mptsas_unquiesce_bus(mptsas_t *mpt);
201
202 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
203 static void mptsas_free_handshake_msg(mptsas_t *mpt);
204
205 static void mptsas_ncmds_checkdrain(void *arg);
206
207 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
208 static void mptsas_retry_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
209 static int mptsas_save_cmd_to_slot(mptsas_t *mpt, mptsas_cmd_t *cmd);
210 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp,
211 int *tran_rval);
212 static void mptsas_accept_tx_waitqs(mptsas_t *mpt);
213 static void mptsas_unblock_tx_waitqs(mptsas_t *mpt);
214 static void mptsas_drain_tx_waitq(mptsas_t *mpt, mptsas_tx_waitqueue_t *txwq);
215 static int mptsas_check_targ_intxtion(mptsas_target_t *ptgt, int cmd_pkt_flags);
216
217 static int mptsas_do_detach(dev_info_t *dev);
218 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
219 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
220 struct scsi_pkt *pkt);
221 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
222
223 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
224 static void mptsas_handle_event(void *args);
225 static int mptsas_handle_event_sync(void *args);
226 static void mptsas_handle_dr(void *args);
227 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
228 dev_info_t *pdip);
229
230 static void mptsas_restart_cmd(void *);
231
232 static void mptsas_flush_hba(mptsas_t *mpt);
233 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
234 uint8_t tasktype);
235 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
236 uchar_t reason, uint_t stat);
237
238 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
239 static void mptsas_process_intr(mptsas_t *mpt, mptsas_reply_pqueue_t *rpqp,
240 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
241 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
242 mptsas_reply_pqueue_t *rpqp, pMpi2ReplyDescriptorsUnion_t reply_desc);
243 static void mptsas_handle_address_reply(mptsas_t *mpt,
244 pMpi2ReplyDescriptorsUnion_t reply_desc);
245 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
246 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
247 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
248
249 static void mptsas_watch(void *arg);
250 static void mptsas_watchsubr(mptsas_t *mpt);
251 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt);
252
253 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
254 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
255 uint8_t *data, uint32_t request_size, uint32_t reply_size,
256 uint32_t data_size, uint8_t direction, uint8_t *dataout,
257 uint32_t dataout_size, short timeout, int mode);
258 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
259
260 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
261 uint32_t unique_id);
262 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
263 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
264 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
265 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
266 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
267 uint32_t diag_type);
268 static int mptsas_diag_register(mptsas_t *mpt,
269 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
270 static int mptsas_diag_unregister(mptsas_t *mpt,
271 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
272 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
273 uint32_t *return_code);
274 static int mptsas_diag_read_buffer(mptsas_t *mpt,
275 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
276 uint32_t *return_code, int ioctl_mode);
277 static int mptsas_diag_release(mptsas_t *mpt,
278 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
279 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
280 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
281 int ioctl_mode);
282 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
283 int mode);
284
285 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
286 int cmdlen, int tgtlen, int statuslen, int kf);
287 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
288
289 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
290 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
291
292 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
293 int kmflags);
294 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
295
296 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
297 mptsas_cmd_t *cmd);
298 static void mptsas_check_task_mgt(mptsas_t *mpt,
299 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
300 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
301 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
302 int *resid);
303
304 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
305 static void mptsas_free_active_slots(mptsas_t *mpt);
306 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
307
308 static void mptsas_restart_hba(mptsas_t *mpt);
309 static void mptsas_restart_waitq(mptsas_t *mpt);
310
311 static void mptsas_deliver_doneq_thread(mptsas_t *mpt,
312 mptsas_done_list_t *dlist);
313 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
314 static void mptsas_rpdoneq_add(mptsas_t *mpt, mptsas_reply_pqueue_t *rpqp,
315 mptsas_cmd_t *cmd);
316 static void mptsas_doneq_mv(mptsas_done_list_t *from,
317 mptsas_doneq_thread_list_t *item);
318
319 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
320 static void mptsas_doneq_empty(mptsas_t *mpt);
321 static void mptsas_rpdoneq_empty(mptsas_reply_pqueue_t *rpqp);
322 static void mptsas_doneq_thread(mptsas_thread_arg_t *arg);
323 static void mptsas_tx_waitq_thread(mptsas_thread_arg_t *arg);
324
325 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
326 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
327
328 static void mptsas_start_watch_reset_delay();
329 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
330 static void mptsas_watch_reset_delay(void *arg);
331 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
332 static void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt,
333 int what);
334 static void mptsas_set_throttle_mtx(struct mptsas *mpt, mptsas_target_t *ptgt,
335 int what);
336 static void mptsas_remove_cmd_nomtx(mptsas_t *mpt, mptsas_cmd_t *cmd);
337
338 /*
339 * helper functions
340 */
341 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
342
343 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
344 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
345 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
346 int lun);
347 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
348 int lun);
349 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
350 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
351
352 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
353 int *lun);
354 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
355
356 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt,
357 mptsas_phymask_t phymask, uint8_t phy);
358 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt,
359 mptsas_phymask_t phymask, uint64_t wwid);
360 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt,
361 mptsas_phymask_t phymask, uint64_t wwid);
362
363 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
364 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
365
366 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
367 uint16_t *handle, mptsas_target_t **pptgt);
368 static void mptsas_update_phymask(mptsas_t *mpt);
369
370 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
371 uint32_t *status, uint8_t cmd);
372 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
373 mptsas_phymask_t *phymask);
374 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
375 mptsas_phymask_t phymask);
376 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt);
377
378
379 /*
380 * Enumeration / DR functions
381 */
382 static void mptsas_config_all(dev_info_t *pdip);
383 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
384 dev_info_t **lundip);
385 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
386 dev_info_t **lundip);
387
388 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
389 static int mptsas_offline_targetdev(dev_info_t *pdip, char *name);
390 static void mptsas_offline_target(mptsas_t *mpt, mptsas_target_t *ptgt,
391 uint8_t topo_flags, dev_info_t *parent);
392
393 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
394 dev_info_t **dip);
395
396 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
397 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
398 dev_info_t **dip, mptsas_target_t *ptgt);
399
400 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
401 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
402
403 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
404 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
405 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
406 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
407 int lun);
408
409 static void mptsas_offline_missed_luns(dev_info_t *pdip,
410 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
411 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
412 mdi_pathinfo_t *rpip, uint_t flags);
413
414 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
415 dev_info_t **smp_dip);
416 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
417 uint_t flags);
418
419 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
420 int mode, int *rval);
421 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
422 int mode, int *rval);
423 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
424 int mode, int *rval);
425 static void mptsas_record_event(void *args);
426 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
427 int mode);
428
429 mptsas_target_t *mptsas_tgt_alloc(mptsas_t *, uint16_t, uint64_t,
430 uint32_t, mptsas_phymask_t, uint8_t);
431 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *);
432 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
433 dev_info_t **smp_dip);
434
435 /*
436 * Power management functions
437 */
438 static int mptsas_get_pci_cap(mptsas_t *mpt);
439 static int mptsas_init_pm(mptsas_t *mpt);
440
441 /*
442 * MPT MSI tunable:
443 *
444 * By default MSI is enabled on all supported platforms.
445 */
446 boolean_t mptsas_enable_msi = B_TRUE;
447 boolean_t mptsas_enable_msix = B_TRUE;
448 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
449
450 /*
451 * Global switch for use of MPI2.5 FAST PATH.
452 */
453 boolean_t mptsas3_use_fastpath = B_TRUE;
454
455 static int mptsas_register_intrs(mptsas_t *);
456 static void mptsas_unregister_intrs(mptsas_t *);
457 static int mptsas_add_intrs(mptsas_t *, int);
458 static void mptsas_rem_intrs(mptsas_t *);
459
460 /*
461 * FMA Prototypes
462 */
463 static void mptsas_fm_init(mptsas_t *mpt);
464 static void mptsas_fm_fini(mptsas_t *mpt);
465 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
466
467 extern pri_t minclsyspri, maxclsyspri;
468 /*
469 * NCPUS is used to determine some optimal configurations for number
470 * of threads created to perform specific jobs. If we are invoked because
471 * a disk is part of the root file system ncpus may still be 1 so check
472 * boot_ncpus as well.
473 */
474 extern int ncpus, boot_ncpus;
475 #define NCPUS max(ncpus, boot_ncpus)
476
477 /*
478 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
479 * under this device that the paths to a physical device are created when
480 * MPxIO is used.
481 */
482 extern dev_info_t *scsi_vhci_dip;
483
484 /*
485 * Tunable timeout value for Inquiry VPD page 0x83
486 * By default the value is 30 seconds.
487 */
488 int mptsas_inq83_retry_timeout = 30;
489
490 /*
491 * Tunable for default SCSI pkt timeout. Defaults to 5 seconds, which should
492 * be plenty for INQUIRY and REPORT_LUNS, which are the only commands currently
493 * issued by mptsas directly.
494 */
495 int mptsas_scsi_pkt_time = 5;
496
497 /*
498 * This is used to allocate memory for message frame storage, not for
499 * data I/O DMA. All message frames must be stored in the first 4G of
500 * physical memory.
501 */
502 ddi_dma_attr_t mptsas_dma_attrs = {
503 DMA_ATTR_V0, /* attribute layout version */
504 0x0ull, /* address low - should be 0 (longlong) */
505 0xffffffffull, /* address high - 32-bit max range */
506 0x00ffffffull, /* count max - max DMA object size */
507 4, /* allocation alignment requirements */
508 0x78, /* burstsizes - binary encoded values */
509 1, /* minxfer - gran. of DMA engine */
510 0x00ffffffull, /* maxxfer - gran. of DMA engine */
511 0xffffffffull, /* max segment size (DMA boundary) */
512 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
513 512, /* granularity - device transfer size */
514 0 /* flags, set to 0 */
515 };
516
517 /*
518 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
519 * physical addresses are supported.)
520 */
521 ddi_dma_attr_t mptsas_dma_attrs64 = {
522 DMA_ATTR_V0, /* attribute layout version */
523 0x0ull, /* address low - should be 0 (longlong) */
524 0xffffffffffffffffull, /* address high - 64-bit max */
525 0x00ffffffull, /* count max - max DMA object size */
526 4, /* allocation alignment requirements */
527 0x78, /* burstsizes - binary encoded values */
528 1, /* minxfer - gran. of DMA engine */
529 0x00ffffffull, /* maxxfer - gran. of DMA engine */
530 0xffffffffull, /* max segment size (DMA boundary) */
531 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
532 512, /* granularity - device transfer size */
533 0 /* flags, set to 0 */
534 };
535
536 ddi_device_acc_attr_t mptsas_dev_attr = {
537 DDI_DEVICE_ATTR_V1,
538 DDI_STRUCTURE_LE_ACC,
539 DDI_STRICTORDER_ACC,
540 DDI_DEFAULT_ACC
541 };
542
543 static struct cb_ops mptsas_cb_ops = {
544 scsi_hba_open, /* open */
545 scsi_hba_close, /* close */
546 nodev, /* strategy */
547 nodev, /* print */
548 nodev, /* dump */
549 nodev, /* read */
550 nodev, /* write */
551 mptsas_ioctl, /* ioctl */
552 nodev, /* devmap */
553 nodev, /* mmap */
554 nodev, /* segmap */
555 nochpoll, /* chpoll */
556 ddi_prop_op, /* cb_prop_op */
557 NULL, /* streamtab */
558 D_MP, /* cb_flag */
559 CB_REV, /* rev */
560 nodev, /* aread */
561 nodev /* awrite */
562 };
563
564 static struct dev_ops mptsas_ops = {
565 DEVO_REV, /* devo_rev, */
566 0, /* refcnt */
567 ddi_no_info, /* info */
568 nulldev, /* identify */
569 nulldev, /* probe */
570 mptsas_attach, /* attach */
571 mptsas_detach, /* detach */
572 #ifdef __sparc
573 mptsas_reset,
574 #else
575 nodev, /* reset */
576 #endif /* __sparc */
577 &mptsas_cb_ops, /* driver operations */
578 NULL, /* bus operations */
579 mptsas_power, /* power management */
580 #ifdef __sparc
581 ddi_quiesce_not_needed
582 #else
583 mptsas_quiesce /* quiesce */
584 #endif /* __sparc */
585 };
586
587
588 #define MPTSAS_MOD_STRING "MPTSAS3 HBA Driver 00.00.01"
589
590 static struct modldrv modldrv = {
591 &mod_driverops, /* Type of module. This one is a driver */
592 MPTSAS_MOD_STRING, /* Name of the module. */
593 &mptsas_ops, /* driver ops */
594 };
595
596 static struct modlinkage modlinkage = {
597 MODREV_1, &modldrv, NULL
598 };
599 #define TARGET_PROP "target"
600 #define LUN_PROP "lun"
601 #define LUN64_PROP "lun64"
602 #define SAS_PROP "sas-mpt"
603 #define MDI_GUID "wwn"
604 #define NDI_GUID "guid"
605 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
606
607 /*
608 * Local static data
609 */
610 #if defined(MPTSAS_DEBUG)
611 uint32_t mptsas_debug_flags = 0x0;
612 /*
613 * Flags to ignore these messages in local debug ring buffer.
614 * Default is to ignore the watchsubr() output which normally happens
615 * every second.
616 */
617 uint32_t mptsas_dbglog_imask = 0x40000000;
618 uint32_t mptsas_test_timeout = 0;
619 #endif /* defined(MPTSAS_DEBUG) */
620 uint32_t mptsas_debug_resets = 0;
621
622 static kmutex_t mptsas_global_mutex;
623 static void *mptsas3_state; /* soft state ptr */
624 static krwlock_t mptsas_global_rwlock;
625
626 static kmutex_t mptsas_log_mutex;
627 static char mptsas_log_buf[256];
628 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
629
630 static mptsas_t *mptsas_head, *mptsas_tail;
631 static clock_t mptsas_scsi_watchdog_tick;
632 static clock_t mptsas_tick;
633 static timeout_id_t mptsas_reset_watch;
634 static timeout_id_t mptsas_timeout_id;
635 static int mptsas_timeouts_enabled = 0;
636
637 /*
638 * Maximum number of MSI-X interrupts any instance of mptsas3 can use.
639 * Note that if you want to increase this you may have to also bump the
640 * value of ddi_msix_alloc_limit which defaults to 8.
641 * Set to zero to fall back to other interrupt types.
642 */
643 int mptsas3_max_msix_intrs = 8;
644
645 /*
646 * Default length for extended auto request sense buffers.
647 * All sense buffers need to be under the same alloc because there
648 * is only one common top 32bits (of 64bits) address register.
649 * Most requests only require 32 bytes, but some request >256.
650 * We use rmalloc()/rmfree() on this additional memory to manage the
651 * "extended" requests.
652 */
653 int mptsas_extreq_sense_bufsize = 256*64;
654
655 /*
656 * Believe that all software resrictions of having to run with DMA
657 * attributes to limit allocation to the first 4G are removed.
658 * However, this flag remains to enable quick switchback should suspicious
659 * problems emerge.
660 * Note that scsi_alloc_consistent_buf() does still adhering to allocating
661 * 32 bit addressable memory, but we can cope if that is changed now.
662 */
663 int mptsas_use_64bit_msgaddr = 1;
664
665 /*
666 * warlock directives
667 */
668 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
669 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
670 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
671 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
672 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
673 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
674
675 /*
676 * SM - HBA statics
677 */
678 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
679
680 #ifdef MPTSAS_DEBUG
681 void debug_enter(char *);
682 #endif
683
684 /*
685 * Notes:
686 * - scsi_hba_init(9F) initializes SCSI HBA modules
687 * - must call scsi_hba_fini(9F) if modload() fails
688 */
689 int
690 _init(void)
691 {
692 int status;
693 /* CONSTCOND */
694 ASSERT(NO_COMPETING_THREADS);
695
696 NDBG0(("_init"));
697
698 status = ddi_soft_state_init(&mptsas3_state, MPTSAS_SIZE,
699 MPTSAS_INITIAL_SOFT_SPACE);
700 if (status != 0) {
701 return (status);
702 }
703
704 if ((status = scsi_hba_init(&modlinkage)) != 0) {
705 ddi_soft_state_fini(&mptsas3_state);
706 return (status);
707 }
708
709 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
710 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
711 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
712
713 if ((status = mod_install(&modlinkage)) != 0) {
714 mutex_destroy(&mptsas_log_mutex);
715 rw_destroy(&mptsas_global_rwlock);
716 mutex_destroy(&mptsas_global_mutex);
717 ddi_soft_state_fini(&mptsas3_state);
718 scsi_hba_fini(&modlinkage);
719 }
720
721 return (status);
722 }
723
724 /*
725 * Notes:
726 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
727 */
728 int
729 _fini(void)
730 {
731 int status;
732 /* CONSTCOND */
733 ASSERT(NO_COMPETING_THREADS);
734
735 NDBG0(("_fini"));
736
737 if ((status = mod_remove(&modlinkage)) == 0) {
738 ddi_soft_state_fini(&mptsas3_state);
739 scsi_hba_fini(&modlinkage);
740 mutex_destroy(&mptsas_global_mutex);
741 rw_destroy(&mptsas_global_rwlock);
742 mutex_destroy(&mptsas_log_mutex);
743 }
744 return (status);
745 }
746
747 /*
748 * The loadable-module _info(9E) entry point
749 */
750 int
751 _info(struct modinfo *modinfop)
752 {
753 /* CONSTCOND */
754 ASSERT(NO_COMPETING_THREADS);
755 NDBG0(("mptsas _info"));
756
757 return (mod_info(&modlinkage, modinfop));
758 }
759
760 static int
761 mptsas_target_eval_devhdl(const void *op, void *arg)
762 {
763 uint16_t dh = *(uint16_t *)arg;
764 const mptsas_target_t *tp = op;
765
766 return ((int)tp->m_devhdl - (int)dh);
767 }
768
769 static int
770 mptsas_target_eval_slot(const void *op, void *arg)
771 {
772 mptsas_led_control_t *lcp = arg;
773 const mptsas_target_t *tp = op;
774
775 if (tp->m_enclosure != lcp->Enclosure)
776 return ((int)tp->m_enclosure - (int)lcp->Enclosure);
777
778 return ((int)tp->m_slot_num - (int)lcp->Slot);
779 }
780
781 static int
782 mptsas_target_eval_nowwn(const void *op, void *arg)
783 {
784 uint8_t phy = *(uint8_t *)arg;
785 const mptsas_target_t *tp = op;
786
787 if (tp->m_addr.mta_wwn != 0)
788 return (-1);
789
790 return ((int)tp->m_phynum - (int)phy);
791 }
792
793 static int
794 mptsas_smp_eval_devhdl(const void *op, void *arg)
795 {
796 uint16_t dh = *(uint16_t *)arg;
797 const mptsas_smp_t *sp = op;
798
799 return ((int)sp->m_devhdl - (int)dh);
800 }
801
802 static uint64_t
803 mptsas_target_addr_hash(const void *tp)
804 {
805 const mptsas_target_addr_t *tap = tp;
806
807 return ((tap->mta_wwn & 0xffffffffffffULL) |
808 ((uint64_t)tap->mta_phymask << 48));
809 }
810
811 static int
812 mptsas_target_addr_cmp(const void *a, const void *b)
813 {
814 const mptsas_target_addr_t *aap = a;
815 const mptsas_target_addr_t *bap = b;
816
817 if (aap->mta_wwn < bap->mta_wwn)
818 return (-1);
819 if (aap->mta_wwn > bap->mta_wwn)
820 return (1);
821 return ((int)bap->mta_phymask - (int)aap->mta_phymask);
822 }
823
824 static void
825 mptsas_target_free(void *op)
826 {
827 kmem_free(op, sizeof (mptsas_target_t));
828 }
829
830 static void
831 mptsas_smp_free(void *op)
832 {
833 kmem_free(op, sizeof (mptsas_smp_t));
834 }
835
836 static void
837 mptsas_destroy_hashes(mptsas_t *mpt)
838 {
839 mptsas_target_t *tp;
840 mptsas_smp_t *sp;
841
842 for (tp = refhash_first(mpt->m_targets); tp != NULL;
843 tp = refhash_next(mpt->m_targets, tp)) {
844 mutex_destroy(&tp->m_t_mutex);
845 refhash_remove(mpt->m_targets, tp);
846 }
847 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
848 sp = refhash_next(mpt->m_smp_targets, sp)) {
849 refhash_remove(mpt->m_smp_targets, sp);
850 }
851 refhash_destroy(mpt->m_targets);
852 refhash_destroy(mpt->m_smp_targets);
853 mpt->m_targets = NULL;
854 mpt->m_smp_targets = NULL;
855 }
856
857 static int
858 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
859 {
860 dev_info_t *pdip;
861 mptsas_t *mpt;
862 scsi_hba_tran_t *hba_tran;
863 char *iport = NULL;
864 char phymask[MPTSAS_MAX_PHYS];
865 mptsas_phymask_t phy_mask = 0;
866 int dynamic_port = 0;
867 uint32_t page_address;
868 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
869 int rval = DDI_FAILURE;
870 int i = 0;
871 uint8_t numphys = 0;
872 uint8_t phy_id;
873 uint8_t phy_port = 0;
874 uint16_t attached_devhdl = 0;
875 uint32_t dev_info;
876 uint64_t attached_sas_wwn;
877 uint16_t dev_hdl;
878 uint16_t pdev_hdl;
879 uint16_t bay_num, enclosure, io_flags;
880 char attached_wwnstr[MPTSAS_WWN_STRLEN];
881
882 /* CONSTCOND */
883 ASSERT(NO_COMPETING_THREADS);
884
885 switch (cmd) {
886 case DDI_ATTACH:
887 break;
888
889 case DDI_RESUME:
890 /*
891 * If this a scsi-iport node, nothing to do here.
892 */
893 return (DDI_SUCCESS);
894
895 default:
896 return (DDI_FAILURE);
897 }
898
899 pdip = ddi_get_parent(dip);
900
901 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
902 NULL) {
903 cmn_err(CE_WARN, "Failed attach iport because fail to "
904 "get tran vector for the HBA node");
905 return (DDI_FAILURE);
906 }
907
908 mpt = TRAN2MPT(hba_tran);
909 ASSERT(mpt != NULL);
910 if (mpt == NULL)
911 return (DDI_FAILURE);
912
913 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
914 NULL) {
915 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
916 "get tran vector for the iport node");
917 return (DDI_FAILURE);
918 }
919
920 /*
921 * Overwrite parent's tran_hba_private to iport's tran vector
922 */
923 hba_tran->tran_hba_private = mpt;
924
925 ddi_report_dev(dip);
926
927 /*
928 * Get SAS address for initiator port according dev_handle
929 */
930 iport = ddi_get_name_addr(dip);
931 if (iport && strncmp(iport, "v0", 2) == 0) {
932 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
933 MPTSAS_VIRTUAL_PORT, 1) !=
934 DDI_PROP_SUCCESS) {
935 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
936 MPTSAS_VIRTUAL_PORT);
937 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
938 "prop update failed");
939 return (DDI_FAILURE);
940 }
941 return (DDI_SUCCESS);
942 }
943
944 mutex_enter(&mpt->m_mutex);
945 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
946 bzero(phymask, sizeof (phymask));
947 (void) sprintf(phymask,
948 "%x", mpt->m_phy_info[i].phy_mask);
949 if (strcmp(phymask, iport) == 0) {
950 break;
951 }
952 }
953
954 if (i == MPTSAS_MAX_PHYS) {
955 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
956 "seems not exist", iport);
957 mutex_exit(&mpt->m_mutex);
958 return (DDI_FAILURE);
959 }
960
961 phy_mask = mpt->m_phy_info[i].phy_mask;
962
963 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
964 dynamic_port = 1;
965 else
966 dynamic_port = 0;
967
968 /*
969 * Update PHY info for smhba
970 */
971 if (mptsas_smhba_phy_init(mpt)) {
972 mutex_exit(&mpt->m_mutex);
973 mptsas_log(mpt, CE_WARN, "mptsas phy update "
974 "failed");
975 return (DDI_FAILURE);
976 }
977
978 mutex_exit(&mpt->m_mutex);
979
980 numphys = 0;
981 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
982 if ((phy_mask >> i) & 0x01) {
983 numphys++;
984 }
985 }
986
987 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
988 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
989 mpt->un.m_base_wwid);
990
991 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
992 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
993 DDI_PROP_SUCCESS) {
994 (void) ddi_prop_remove(DDI_DEV_T_NONE,
995 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
996 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
997 "prop update failed");
998 return (DDI_FAILURE);
999 }
1000 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
1001 MPTSAS_NUM_PHYS, numphys) !=
1002 DDI_PROP_SUCCESS) {
1003 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
1004 return (DDI_FAILURE);
1005 }
1006
1007 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
1008 "phymask", phy_mask) !=
1009 DDI_PROP_SUCCESS) {
1010 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
1011 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
1012 "prop update failed");
1013 return (DDI_FAILURE);
1014 }
1015
1016 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
1017 "dynamic-port", dynamic_port) !=
1018 DDI_PROP_SUCCESS) {
1019 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
1020 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
1021 "prop update failed");
1022 return (DDI_FAILURE);
1023 }
1024 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
1025 MPTSAS_VIRTUAL_PORT, 0) !=
1026 DDI_PROP_SUCCESS) {
1027 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
1028 MPTSAS_VIRTUAL_PORT);
1029 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
1030 "prop update failed");
1031 return (DDI_FAILURE);
1032 }
1033 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask,
1034 &attached_devhdl);
1035
1036 mutex_enter(&mpt->m_mutex);
1037 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
1038 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
1039 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
1040 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
1041 &pdev_hdl, &bay_num, &enclosure, &io_flags);
1042 if (rval != DDI_SUCCESS) {
1043 mptsas_log(mpt, CE_WARN,
1044 "Failed to get device page0 for handle:%d",
1045 attached_devhdl);
1046 mutex_exit(&mpt->m_mutex);
1047 return (DDI_FAILURE);
1048 }
1049
1050 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1051 bzero(phymask, sizeof (phymask));
1052 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
1053 if (strcmp(phymask, iport) == 0) {
1054 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
1055 "%x",
1056 mpt->m_phy_info[i].phy_mask);
1057 }
1058 }
1059 mutex_exit(&mpt->m_mutex);
1060
1061 bzero(attached_wwnstr, sizeof (attached_wwnstr));
1062 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
1063 attached_sas_wwn);
1064 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
1065 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
1066 DDI_PROP_SUCCESS) {
1067 (void) ddi_prop_remove(DDI_DEV_T_NONE,
1068 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
1069 return (DDI_FAILURE);
1070 }
1071
1072 /* Create kstats for each phy on this iport */
1073
1074 mptsas_create_phy_stats(mpt, iport, dip);
1075
1076 /*
1077 * register sas hba iport with mdi (MPxIO/vhci)
1078 */
1079 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
1080 dip, 0) == MDI_SUCCESS) {
1081 mpt->m_mpxio_enable = TRUE;
1082 }
1083 return (DDI_SUCCESS);
1084 }
1085
1086 /*
1087 * Notes:
1088 * Set up all device state and allocate data structures,
1089 * mutexes, condition variables, etc. for device operation.
1090 * Add interrupts needed.
1091 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
1092 */
1093 static int
1094 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
1095 {
1096 mptsas_t *mpt = NULL;
1097 int instance, i, j;
1098 int q_thread_num;
1099 char map_setup = 0;
1100 char config_setup = 0;
1101 char hba_attach_setup = 0;
1102 char smp_attach_setup = 0;
1103 char mutex_init_done = 0;
1104 char event_taskq_create = 0;
1105 char dr_taskq_create = 0;
1106 char doneq_thread_create = 0;
1107 char txwq_thread_create = 0;
1108 char added_watchdog = 0;
1109 scsi_hba_tran_t *hba_tran;
1110 uint_t mem_bar = MEM_SPACE;
1111 int rval = DDI_FAILURE;
1112
1113 /* CONSTCOND */
1114 ASSERT(NO_COMPETING_THREADS);
1115
1116 if (scsi_hba_iport_unit_address(dip)) {
1117 return (mptsas_iport_attach(dip, cmd));
1118 }
1119
1120 switch (cmd) {
1121 case DDI_ATTACH:
1122 break;
1123
1124 case DDI_RESUME:
1125 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
1126 return (DDI_FAILURE);
1127
1128 mpt = TRAN2MPT(hba_tran);
1129
1130 if (!mpt) {
1131 return (DDI_FAILURE);
1132 }
1133
1134 /*
1135 * Reset hardware and softc to "no outstanding commands"
1136 * Note that a check condition can result on first command
1137 * to a target.
1138 */
1139 mutex_enter(&mpt->m_mutex);
1140
1141 /*
1142 * raise power.
1143 */
1144 if (mpt->m_options & MPTSAS_OPT_PM) {
1145 mutex_exit(&mpt->m_mutex);
1146 (void) pm_busy_component(dip, 0);
1147 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
1148 if (rval == DDI_SUCCESS) {
1149 mutex_enter(&mpt->m_mutex);
1150 } else {
1151 /*
1152 * The pm_raise_power() call above failed,
1153 * and that can only occur if we were unable
1154 * to reset the hardware. This is probably
1155 * due to unhealty hardware, and because
1156 * important filesystems(such as the root
1157 * filesystem) could be on the attached disks,
1158 * it would not be a good idea to continue,
1159 * as we won't be entirely certain we are
1160 * writing correct data. So we panic() here
1161 * to not only prevent possible data corruption,
1162 * but to give developers or end users a hope
1163 * of identifying and correcting any problems.
1164 */
1165 fm_panic("mptsas could not reset hardware "
1166 "during resume");
1167 }
1168 }
1169
1170 mpt->m_suspended = 0;
1171
1172 /*
1173 * Reinitialize ioc
1174 */
1175 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1176 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1177 mutex_exit(&mpt->m_mutex);
1178 if (mpt->m_options & MPTSAS_OPT_PM) {
1179 (void) pm_idle_component(dip, 0);
1180 }
1181 fm_panic("mptsas init chip fail during resume");
1182 }
1183 /*
1184 * mptsas_update_driver_data needs interrupts so enable them
1185 * first.
1186 */
1187 MPTSAS_ENABLE_INTR(mpt);
1188 mptsas_update_driver_data(mpt);
1189
1190 /* start requests, if possible */
1191 mptsas_restart_hba(mpt);
1192
1193 mutex_exit(&mpt->m_mutex);
1194
1195 /*
1196 * Restart watch thread
1197 */
1198 mutex_enter(&mptsas_global_mutex);
1199 if (mptsas_timeout_id == 0) {
1200 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1201 mptsas_tick);
1202 mptsas_timeouts_enabled = 1;
1203 }
1204 mutex_exit(&mptsas_global_mutex);
1205
1206 /* report idle status to pm framework */
1207 if (mpt->m_options & MPTSAS_OPT_PM) {
1208 (void) pm_idle_component(dip, 0);
1209 }
1210
1211 return (DDI_SUCCESS);
1212
1213 default:
1214 return (DDI_FAILURE);
1215
1216 }
1217
1218 instance = ddi_get_instance(dip);
1219
1220 /*
1221 * Allocate softc information.
1222 */
1223 if (ddi_soft_state_zalloc(mptsas3_state, instance) != DDI_SUCCESS) {
1224 mptsas_log(NULL, CE_WARN,
1225 "mptsas%d: cannot allocate soft state", instance);
1226 goto fail;
1227 }
1228
1229 mpt = ddi_get_soft_state(mptsas3_state, instance);
1230
1231 if (mpt == NULL) {
1232 mptsas_log(NULL, CE_WARN,
1233 "mptsas%d: cannot get soft state", instance);
1234 goto fail;
1235 }
1236
1237 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1238 scsi_size_clean(dip);
1239
1240 mpt->m_dip = dip;
1241 mpt->m_instance = instance;
1242
1243 /* Make a per-instance copy of the structures */
1244 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1245 if (mptsas_use_64bit_msgaddr) {
1246 mpt->m_msg_dma_attr = mptsas_dma_attrs64;
1247 } else {
1248 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1249 }
1250 mpt->m_reg_acc_attr = mptsas_dev_attr;
1251 mpt->m_dev_acc_attr = mptsas_dev_attr;
1252
1253 /*
1254 * Round down the arq sense buffer size to nearest 16 bytes.
1255 */
1256 mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE;
1257
1258 /*
1259 * Initialize FMA
1260 */
1261 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1262 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1263 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1264 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1265
1266 mptsas_fm_init(mpt);
1267
1268 if (mptsas_alloc_handshake_msg(mpt,
1269 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1270 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1271 goto fail;
1272 }
1273
1274 /*
1275 * Setup configuration space
1276 */
1277 if (mptsas_config_space_init(mpt) == FALSE) {
1278 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1279 goto fail;
1280 }
1281 config_setup++;
1282
1283 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1284 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1285 mptsas_log(mpt, CE_WARN, "map setup failed");
1286 goto fail;
1287 }
1288 map_setup++;
1289
1290 /*
1291 * A taskq is created for dealing with the event handler
1292 */
1293 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1294 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1295 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1296 goto fail;
1297 }
1298 event_taskq_create++;
1299
1300 /*
1301 * A taskq is created for dealing with dr events
1302 */
1303 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1304 "mptsas_dr_taskq",
1305 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1306 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1307 "failed");
1308 goto fail;
1309 }
1310 dr_taskq_create++;
1311
1312 cv_init(&mpt->m_qthread_cv, NULL, CV_DRIVER, NULL);
1313 mutex_init(&mpt->m_qthread_mutex, NULL, MUTEX_DRIVER, NULL);
1314
1315 i = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1316 0, "mptsas_enable_txwq_prop", NCPUS > 1);
1317 if (i) {
1318 mpt->m_txwq_thread_n = NUM_TX_WAITQ;
1319 mpt->m_txwq_enabled = FALSE;
1320 if (ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1321 0, "mptsas_allow_txwq_jumping", 0)) {
1322 mpt->m_txwq_allow_q_jumping = TRUE;
1323 }
1324 i = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1325 0, "mptsas_txwq_threashold_prop", 80000);
1326 mpt->m_txwq_thread_threshold = (uint16_t)i;
1327 } else {
1328 mpt->m_txwq_thread_n = 0;
1329 mpt->m_txwq_enabled = FALSE;
1330 }
1331
1332 if (mpt->m_txwq_thread_n) {
1333 mutex_enter(&mpt->m_qthread_mutex);
1334 for (j = 0; j < NUM_TX_WAITQ; j++) {
1335 mutex_init(&mpt->m_tx_waitq[j].txwq_mutex, NULL,
1336 MUTEX_DRIVER,
1337 NULL);
1338 cv_init(&mpt->m_tx_waitq[j].txwq_cv, NULL, CV_DRIVER,
1339 NULL);
1340 cv_init(&mpt->m_tx_waitq[j].txwq_drain_cv, NULL,
1341 CV_DRIVER, NULL);
1342 mpt->m_tx_waitq[j].txwq_active = TRUE;
1343 mpt->m_tx_waitq[j].txwq_draining = FALSE;
1344 mpt->m_tx_waitq[j].txwq_cmdq = NULL;
1345 mpt->m_tx_waitq[j].txwq_qtail =
1346 &mpt->m_tx_waitq[j].txwq_cmdq;
1347 mutex_enter(&mpt->m_tx_waitq[j].txwq_mutex);
1348 mpt->m_tx_waitq[j].arg.mpt = mpt;
1349 mpt->m_tx_waitq[j].arg.t = j;
1350 mpt->m_tx_waitq[j].txwq_threadp =
1351 thread_create(NULL, 0, mptsas_tx_waitq_thread,
1352 &mpt->m_tx_waitq[j].arg,
1353 0, &p0, TS_RUN, maxclsyspri - 10);
1354 mutex_exit(&mpt->m_tx_waitq[j].txwq_mutex);
1355 }
1356 mutex_exit(&mpt->m_qthread_mutex);
1357 txwq_thread_create++;
1358 }
1359
1360 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1361 0, "mptsas_doneq_thread_threshold_prop", 10);
1362 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1363 0, "mptsas_doneq_length_threshold_prop", 8);
1364 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1365 0, "mptsas_doneq_thread_n_prop", min(NCPUS, 8));
1366
1367 if (mpt->m_doneq_thread_n) {
1368 mutex_enter(&mpt->m_qthread_mutex);
1369 mpt->m_doneq_thread_id =
1370 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1371 * mpt->m_doneq_thread_n, KM_SLEEP);
1372
1373 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1374 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1375 CV_DRIVER, NULL);
1376 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1377 MUTEX_DRIVER, NULL);
1378 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1379 mpt->m_doneq_thread_id[j].flag |=
1380 MPTSAS_DONEQ_THREAD_ACTIVE;
1381 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1382 mpt->m_doneq_thread_id[j].arg.t = j;
1383 mpt->m_doneq_thread_id[j].threadp =
1384 thread_create(NULL, 0, mptsas_doneq_thread,
1385 &mpt->m_doneq_thread_id[j].arg,
1386 0, &p0, TS_RUN, maxclsyspri - 10);
1387 mpt->m_doneq_thread_id[j].dlist.dl_tail =
1388 &mpt->m_doneq_thread_id[j].dlist.dl_q;
1389 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1390 }
1391 mutex_exit(&mpt->m_qthread_mutex);
1392 doneq_thread_create++;
1393 }
1394
1395 /*
1396 * Disable hardware interrupt since we're not ready to
1397 * handle it yet.
1398 */
1399 MPTSAS_DISABLE_INTR(mpt);
1400
1401 /*
1402 * Initialize mutex used in interrupt handler.
1403 * We don't support hi-level so the mutex's are all adaptive
1404 * and we don't want to register the interrupts until we get
1405 * the chip type information from _init_chip() below.
1406 * Otherwise we would use DDI_INTR_PRI(mpt->m_intr_pri)
1407 * rather than NULL in the mutex_init() calls.
1408 */
1409 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, NULL);
1410 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1411 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1412 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1413 NULL, MUTEX_DRIVER, NULL);
1414 }
1415
1416 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1417 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1418 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1419 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1420 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1421 mutex_init_done++;
1422
1423 mutex_enter(&mpt->m_mutex);
1424 /*
1425 * Initialize power management component
1426 */
1427 if (mpt->m_options & MPTSAS_OPT_PM) {
1428 if (mptsas_init_pm(mpt)) {
1429 mutex_exit(&mpt->m_mutex);
1430 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1431 "failed");
1432 goto fail;
1433 }
1434 }
1435
1436 /*
1437 * Initialize chip using Message Unit Reset, if allowed
1438 */
1439 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1440 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1441 mutex_exit(&mpt->m_mutex);
1442 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1443 goto fail;
1444 }
1445
1446 /*
1447 * Fill in the phy_info structure and get the base WWID
1448 */
1449 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1450 mptsas_log(mpt, CE_WARN,
1451 "mptsas_get_manufacture_page5 failed!");
1452 goto fail;
1453 }
1454
1455 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1456 mptsas_log(mpt, CE_WARN,
1457 "mptsas_get_sas_io_unit_page_hndshk failed!");
1458 goto fail;
1459 }
1460
1461 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1462 mptsas_log(mpt, CE_WARN,
1463 "mptsas_get_manufacture_page0 failed!");
1464 goto fail;
1465 }
1466
1467 /*
1468 * If we only have one interrupt the default for doneq_thread_threshold
1469 * should be 0 so that all completion processing goes to the threads.
1470 * Only change it if it wasn't set from .conf file.
1471 */
1472 if (mpt->m_doneq_thread_n != 0 &&
1473 ddi_prop_exists(DDI_DEV_T_ANY, dip,
1474 0, "mptsas_doneq_length_threshold_prop") == 0 &&
1475 mpt->m_intr_cnt == 1) {
1476 mpt->m_doneq_length_threshold = 0;
1477 }
1478
1479
1480 mutex_exit(&mpt->m_mutex);
1481
1482 /*
1483 * Register the iport for multiple port HBA
1484 */
1485 mptsas_iport_register(mpt);
1486
1487 /*
1488 * initialize SCSI HBA transport structure
1489 */
1490 if (mptsas_hba_setup(mpt) == FALSE)
1491 goto fail;
1492 hba_attach_setup++;
1493
1494 if (mptsas_smp_setup(mpt) == FALSE)
1495 goto fail;
1496 smp_attach_setup++;
1497
1498 if (mptsas_cache_create(mpt) == FALSE)
1499 goto fail;
1500
1501 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1502 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1503 if (mpt->m_scsi_reset_delay == 0) {
1504 mptsas_log(mpt, CE_NOTE,
1505 "scsi_reset_delay of 0 is not recommended,"
1506 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1507 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1508 }
1509
1510 /*
1511 * Initialize the wait and done FIFO queue
1512 */
1513 mpt->m_dlist.dl_tail = &mpt->m_dlist.dl_q;
1514 mpt->m_waitqtail = &mpt->m_waitq;
1515
1516 /*
1517 * ioc cmd queue initialize
1518 */
1519 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1520 mpt->m_dev_handle = 0xFFFF;
1521
1522 MPTSAS_ENABLE_INTR(mpt);
1523
1524 /*
1525 * enable event notification
1526 */
1527 mutex_enter(&mpt->m_mutex);
1528 if (mptsas_ioc_enable_event_notification(mpt)) {
1529 mutex_exit(&mpt->m_mutex);
1530 goto fail;
1531 }
1532 mutex_exit(&mpt->m_mutex);
1533
1534 /*
1535 * used for mptsas_watch
1536 */
1537 mptsas_list_add(mpt);
1538
1539 mutex_enter(&mptsas_global_mutex);
1540 if (mptsas_timeouts_enabled == 0) {
1541 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1542 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1543
1544 mptsas_tick = mptsas_scsi_watchdog_tick *
1545 drv_usectohz((clock_t)1000000);
1546
1547 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1548 mptsas_timeouts_enabled = 1;
1549 }
1550 mutex_exit(&mptsas_global_mutex);
1551 added_watchdog++;
1552
1553 /*
1554 * Initialize PHY info for smhba.
1555 * This requires watchdog to be enabled otherwise if interrupts
1556 * don't work the system will hang.
1557 */
1558 if (mptsas_smhba_setup(mpt)) {
1559 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1560 "failed");
1561 goto fail;
1562 }
1563
1564 /* Check all dma handles allocated in attach */
1565 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1566 != DDI_SUCCESS) ||
1567 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl)
1568 != DDI_SUCCESS) ||
1569 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1570 != DDI_SUCCESS) ||
1571 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1572 != DDI_SUCCESS) ||
1573 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1574 != DDI_SUCCESS) ||
1575 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1576 != DDI_SUCCESS)) {
1577 goto fail;
1578 }
1579
1580 /* Check all acc handles allocated in attach */
1581 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1582 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1583 != DDI_SUCCESS) ||
1584 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl)
1585 != DDI_SUCCESS) ||
1586 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1587 != DDI_SUCCESS) ||
1588 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1589 != DDI_SUCCESS) ||
1590 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1591 != DDI_SUCCESS) ||
1592 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1593 != DDI_SUCCESS) ||
1594 (mptsas_check_acc_handle(mpt->m_config_handle)
1595 != DDI_SUCCESS)) {
1596 goto fail;
1597 }
1598
1599 /*
1600 * After this point, we are not going to fail the attach.
1601 */
1602
1603 /* Print message of HBA present */
1604 ddi_report_dev(dip);
1605
1606 /* report idle status to pm framework */
1607 if (mpt->m_options & MPTSAS_OPT_PM) {
1608 (void) pm_idle_component(dip, 0);
1609 }
1610
1611 return (DDI_SUCCESS);
1612
1613 fail:
1614 mptsas_log(mpt, CE_WARN, "attach failed");
1615 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1616 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1617 if (mpt) {
1618 /* deallocate in reverse order */
1619 if (added_watchdog) {
1620 mptsas_list_del(mpt);
1621 mutex_enter(&mptsas_global_mutex);
1622
1623 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1624 timeout_id_t tid = mptsas_timeout_id;
1625 mptsas_timeouts_enabled = 0;
1626 mptsas_timeout_id = 0;
1627 mutex_exit(&mptsas_global_mutex);
1628 (void) untimeout(tid);
1629 mutex_enter(&mptsas_global_mutex);
1630 }
1631 mutex_exit(&mptsas_global_mutex);
1632 }
1633
1634 mptsas_cache_destroy(mpt);
1635
1636 if (smp_attach_setup) {
1637 mptsas_smp_teardown(mpt);
1638 }
1639 if (hba_attach_setup) {
1640 mptsas_hba_teardown(mpt);
1641 }
1642
1643 if (mpt->m_targets)
1644 refhash_destroy(mpt->m_targets);
1645 if (mpt->m_smp_targets)
1646 refhash_destroy(mpt->m_smp_targets);
1647
1648 if (mpt->m_active) {
1649 mptsas_free_active_slots(mpt);
1650 }
1651 if (mpt->m_intr_cnt) {
1652 mptsas_unregister_intrs(mpt);
1653 }
1654
1655 if (doneq_thread_create) {
1656 mutex_enter(&mpt->m_qthread_mutex);
1657 q_thread_num = mpt->m_doneq_thread_n;
1658 for (j = 0; j < q_thread_num; j++) {
1659 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1660 mpt->m_doneq_thread_id[j].flag &=
1661 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1662 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1663 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1664 }
1665 while (mpt->m_doneq_thread_n) {
1666 cv_wait(&mpt->m_qthread_cv,
1667 &mpt->m_qthread_mutex);
1668 }
1669 for (j = 0; j < q_thread_num; j++) {
1670 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1671 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1672 }
1673 kmem_free(mpt->m_doneq_thread_id,
1674 sizeof (mptsas_doneq_thread_list_t)
1675 * q_thread_num);
1676 mutex_exit(&mpt->m_qthread_mutex);
1677 }
1678 if (txwq_thread_create) {
1679 mutex_enter(&mpt->m_qthread_mutex);
1680 q_thread_num = mpt->m_txwq_thread_n;
1681 for (j = 0; j < q_thread_num; j++) {
1682 mutex_enter(&mpt->m_tx_waitq[j].txwq_mutex);
1683 mpt->m_tx_waitq[j].txwq_active = FALSE;
1684 cv_signal(&mpt->m_tx_waitq[j].txwq_cv);
1685 mutex_exit(&mpt->m_tx_waitq[j].txwq_mutex);
1686 }
1687 while (mpt->m_txwq_thread_n) {
1688 cv_wait(&mpt->m_qthread_cv,
1689 &mpt->m_qthread_mutex);
1690 }
1691 for (j = 0; j < q_thread_num; j++) {
1692 cv_destroy(&mpt->m_tx_waitq[j].txwq_cv);
1693 cv_destroy(&mpt->m_tx_waitq[j].txwq_drain_cv);
1694 mutex_destroy(&mpt->m_tx_waitq[j].txwq_mutex);
1695 }
1696 }
1697 if (event_taskq_create) {
1698 ddi_taskq_destroy(mpt->m_event_taskq);
1699 }
1700 if (dr_taskq_create) {
1701 ddi_taskq_destroy(mpt->m_dr_taskq);
1702 }
1703 if (mutex_init_done) {
1704 mutex_destroy(&mpt->m_qthread_mutex);
1705 mutex_destroy(&mpt->m_passthru_mutex);
1706 mutex_destroy(&mpt->m_mutex);
1707 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1708 mutex_destroy(
1709 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1710 }
1711 cv_destroy(&mpt->m_qthread_cv);
1712 cv_destroy(&mpt->m_cv);
1713 cv_destroy(&mpt->m_passthru_cv);
1714 cv_destroy(&mpt->m_fw_cv);
1715 cv_destroy(&mpt->m_config_cv);
1716 cv_destroy(&mpt->m_fw_diag_cv);
1717 }
1718
1719 if (map_setup) {
1720 mptsas_cfg_fini(mpt);
1721 }
1722 if (config_setup) {
1723 mptsas_config_space_fini(mpt);
1724 }
1725 mptsas_free_handshake_msg(mpt);
1726 mptsas_hba_fini(mpt);
1727
1728 mptsas_fm_fini(mpt);
1729 ddi_soft_state_free(mptsas3_state, instance);
1730 ddi_prop_remove_all(dip);
1731 }
1732 return (DDI_FAILURE);
1733 }
1734
1735 static int
1736 mptsas_suspend(dev_info_t *devi)
1737 {
1738 mptsas_t *mpt, *g;
1739 scsi_hba_tran_t *tran;
1740
1741 if (scsi_hba_iport_unit_address(devi)) {
1742 return (DDI_SUCCESS);
1743 }
1744
1745 if ((tran = ddi_get_driver_private(devi)) == NULL)
1746 return (DDI_SUCCESS);
1747
1748 mpt = TRAN2MPT(tran);
1749 if (!mpt) {
1750 return (DDI_SUCCESS);
1751 }
1752
1753 mutex_enter(&mpt->m_mutex);
1754
1755 if (mpt->m_suspended++) {
1756 mutex_exit(&mpt->m_mutex);
1757 return (DDI_SUCCESS);
1758 }
1759
1760 /*
1761 * Cancel timeout threads for this mpt
1762 */
1763 if (mpt->m_quiesce_timeid) {
1764 timeout_id_t tid = mpt->m_quiesce_timeid;
1765 mpt->m_quiesce_timeid = 0;
1766 mutex_exit(&mpt->m_mutex);
1767 (void) untimeout(tid);
1768 mutex_enter(&mpt->m_mutex);
1769 }
1770
1771 if (mpt->m_restart_cmd_timeid) {
1772 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1773 mpt->m_restart_cmd_timeid = 0;
1774 mutex_exit(&mpt->m_mutex);
1775 (void) untimeout(tid);
1776 mutex_enter(&mpt->m_mutex);
1777 }
1778
1779 mutex_exit(&mpt->m_mutex);
1780
1781 (void) pm_idle_component(mpt->m_dip, 0);
1782
1783 /*
1784 * Cancel watch threads if all mpts suspended
1785 */
1786 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1787 for (g = mptsas_head; g != NULL; g = g->m_next) {
1788 if (!g->m_suspended)
1789 break;
1790 }
1791 rw_exit(&mptsas_global_rwlock);
1792
1793 mutex_enter(&mptsas_global_mutex);
1794 if (g == NULL) {
1795 timeout_id_t tid;
1796
1797 mptsas_timeouts_enabled = 0;
1798 if (mptsas_timeout_id) {
1799 tid = mptsas_timeout_id;
1800 mptsas_timeout_id = 0;
1801 mutex_exit(&mptsas_global_mutex);
1802 (void) untimeout(tid);
1803 mutex_enter(&mptsas_global_mutex);
1804 }
1805 if (mptsas_reset_watch) {
1806 tid = mptsas_reset_watch;
1807 mptsas_reset_watch = 0;
1808 mutex_exit(&mptsas_global_mutex);
1809 (void) untimeout(tid);
1810 mutex_enter(&mptsas_global_mutex);
1811 }
1812 }
1813 mutex_exit(&mptsas_global_mutex);
1814
1815 mutex_enter(&mpt->m_mutex);
1816
1817 /*
1818 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1819 */
1820 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1821 (mpt->m_power_level != PM_LEVEL_D0)) {
1822 mutex_exit(&mpt->m_mutex);
1823 return (DDI_SUCCESS);
1824 }
1825
1826 /* Disable HBA interrupts in hardware */
1827 MPTSAS_DISABLE_INTR(mpt);
1828 /*
1829 * Send RAID action system shutdown to sync IR
1830 */
1831 mptsas_raid_action_system_shutdown(mpt);
1832
1833 mutex_exit(&mpt->m_mutex);
1834
1835 /* drain the taskq */
1836 ddi_taskq_wait(mpt->m_event_taskq);
1837 ddi_taskq_wait(mpt->m_dr_taskq);
1838
1839 return (DDI_SUCCESS);
1840 }
1841
1842 #ifdef __sparc
1843 /*ARGSUSED*/
1844 static int
1845 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1846 {
1847 mptsas_t *mpt;
1848 scsi_hba_tran_t *tran;
1849
1850 /*
1851 * If this call is for iport, just return.
1852 */
1853 if (scsi_hba_iport_unit_address(devi))
1854 return (DDI_SUCCESS);
1855
1856 if ((tran = ddi_get_driver_private(devi)) == NULL)
1857 return (DDI_SUCCESS);
1858
1859 if ((mpt = TRAN2MPT(tran)) == NULL)
1860 return (DDI_SUCCESS);
1861
1862 /*
1863 * Send RAID action system shutdown to sync IR. Disable HBA
1864 * interrupts in hardware first.
1865 */
1866 MPTSAS_DISABLE_INTR(mpt);
1867 mptsas_raid_action_system_shutdown(mpt);
1868
1869 return (DDI_SUCCESS);
1870 }
1871 #else /* __sparc */
1872 /*
1873 * quiesce(9E) entry point.
1874 *
1875 * This function is called when the system is single-threaded at high
1876 * PIL with preemption disabled. Therefore, this function must not be
1877 * blocked.
1878 *
1879 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1880 * DDI_FAILURE indicates an error condition and should almost never happen.
1881 */
1882 static int
1883 mptsas_quiesce(dev_info_t *devi)
1884 {
1885 mptsas_t *mpt;
1886 scsi_hba_tran_t *tran;
1887
1888 /*
1889 * If this call is for iport, just return.
1890 */
1891 if (scsi_hba_iport_unit_address(devi))
1892 return (DDI_SUCCESS);
1893
1894 if ((tran = ddi_get_driver_private(devi)) == NULL)
1895 return (DDI_SUCCESS);
1896
1897 if ((mpt = TRAN2MPT(tran)) == NULL)
1898 return (DDI_SUCCESS);
1899
1900 /* Disable HBA interrupts in hardware */
1901 MPTSAS_DISABLE_INTR(mpt);
1902 /* Send RAID action system shutdonw to sync IR */
1903 mptsas_raid_action_system_shutdown(mpt);
1904
1905 return (DDI_SUCCESS);
1906 }
1907 #endif /* __sparc */
1908
1909 /*
1910 * detach(9E). Remove all device allocations and system resources;
1911 * disable device interrupts.
1912 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1913 */
1914 static int
1915 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1916 {
1917 /* CONSTCOND */
1918 ASSERT(NO_COMPETING_THREADS);
1919 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1920
1921 switch (cmd) {
1922 case DDI_DETACH:
1923 return (mptsas_do_detach(devi));
1924
1925 case DDI_SUSPEND:
1926 return (mptsas_suspend(devi));
1927
1928 default:
1929 return (DDI_FAILURE);
1930 }
1931 /* NOTREACHED */
1932 }
1933
1934 static int
1935 mptsas_do_detach(dev_info_t *dip)
1936 {
1937 mptsas_t *mpt;
1938 scsi_hba_tran_t *tran;
1939 int circ = 0;
1940 int circ1 = 0;
1941 mdi_pathinfo_t *pip = NULL;
1942 int i;
1943 int q_thread_num = 0;
1944
1945 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1946
1947 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1948 return (DDI_FAILURE);
1949
1950 mpt = TRAN2MPT(tran);
1951 if (!mpt) {
1952 return (DDI_FAILURE);
1953 }
1954 /*
1955 * Still have pathinfo child, should not detach mpt driver
1956 */
1957 if (scsi_hba_iport_unit_address(dip)) {
1958 if (mpt->m_mpxio_enable) {
1959 /*
1960 * MPxIO enabled for the iport
1961 */
1962 ndi_devi_enter(scsi_vhci_dip, &circ1);
1963 ndi_devi_enter(dip, &circ);
1964 while (pip = mdi_get_next_client_path(dip, NULL)) {
1965 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1966 continue;
1967 }
1968 ndi_devi_exit(dip, circ);
1969 ndi_devi_exit(scsi_vhci_dip, circ1);
1970 NDBG12(("detach failed because of "
1971 "outstanding path info"));
1972 return (DDI_FAILURE);
1973 }
1974 ndi_devi_exit(dip, circ);
1975 ndi_devi_exit(scsi_vhci_dip, circ1);
1976 (void) mdi_phci_unregister(dip, 0);
1977 }
1978
1979 ddi_prop_remove_all(dip);
1980
1981 return (DDI_SUCCESS);
1982 }
1983
1984 /* Make sure power level is D0 before accessing registers */
1985 if (mpt->m_options & MPTSAS_OPT_PM) {
1986 (void) pm_busy_component(dip, 0);
1987 if (mpt->m_power_level != PM_LEVEL_D0) {
1988 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1989 DDI_SUCCESS) {
1990 mptsas_log(mpt, CE_WARN,
1991 "mptsas3%d: Raise power request failed.",
1992 mpt->m_instance);
1993 (void) pm_idle_component(dip, 0);
1994 return (DDI_FAILURE);
1995 }
1996 }
1997 }
1998
1999 /*
2000 * Send RAID action system shutdown to sync IR. After action, send a
2001 * Message Unit Reset. Since after that DMA resource will be freed,
2002 * set ioc to READY state will avoid HBA initiated DMA operation.
2003 */
2004 mutex_enter(&mpt->m_mutex);
2005 MPTSAS_DISABLE_INTR(mpt);
2006 mptsas_raid_action_system_shutdown(mpt);
2007 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
2008 (void) mptsas_ioc_reset(mpt, FALSE);
2009 mutex_exit(&mpt->m_mutex);
2010 mptsas_rem_intrs(mpt);
2011 ddi_taskq_destroy(mpt->m_event_taskq);
2012 ddi_taskq_destroy(mpt->m_dr_taskq);
2013
2014 if (mpt->m_doneq_thread_n) {
2015 mutex_enter(&mpt->m_qthread_mutex);
2016 q_thread_num = mpt->m_doneq_thread_n;
2017 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
2018 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
2019 mpt->m_doneq_thread_id[i].flag &=
2020 (~MPTSAS_DONEQ_THREAD_ACTIVE);
2021 cv_signal(&mpt->m_doneq_thread_id[i].cv);
2022 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
2023 }
2024 while (mpt->m_doneq_thread_n) {
2025 cv_wait(&mpt->m_qthread_cv,
2026 &mpt->m_qthread_mutex);
2027 }
2028 for (i = 0; i < q_thread_num; i++) {
2029 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
2030 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
2031 }
2032 kmem_free(mpt->m_doneq_thread_id,
2033 sizeof (mptsas_doneq_thread_list_t)
2034 * q_thread_num);
2035 mutex_exit(&mpt->m_qthread_mutex);
2036 }
2037 if (mpt->m_txwq_thread_n) {
2038 mutex_enter(&mpt->m_qthread_mutex);
2039 q_thread_num = mpt->m_txwq_thread_n;
2040 for (i = 0; i < q_thread_num; i++) {
2041 mutex_enter(&mpt->m_tx_waitq[i].txwq_mutex);
2042 mpt->m_tx_waitq[i].txwq_active = FALSE;
2043 cv_signal(&mpt->m_tx_waitq[i].txwq_cv);
2044 mutex_exit(&mpt->m_tx_waitq[i].txwq_mutex);
2045 }
2046 while (mpt->m_txwq_thread_n) {
2047 cv_wait(&mpt->m_qthread_cv,
2048 &mpt->m_qthread_mutex);
2049 }
2050 for (i = 0; i < q_thread_num; i++) {
2051 cv_destroy(&mpt->m_tx_waitq[i].txwq_cv);
2052 cv_destroy(&mpt->m_tx_waitq[i].txwq_drain_cv);
2053 mutex_destroy(&mpt->m_tx_waitq[i].txwq_mutex);
2054 }
2055 }
2056
2057 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
2058
2059 mptsas_list_del(mpt);
2060
2061 /*
2062 * Cancel timeout threads for this mpt
2063 */
2064 mutex_enter(&mpt->m_mutex);
2065 if (mpt->m_quiesce_timeid) {
2066 timeout_id_t tid = mpt->m_quiesce_timeid;
2067 mpt->m_quiesce_timeid = 0;
2068 mutex_exit(&mpt->m_mutex);
2069 (void) untimeout(tid);
2070 mutex_enter(&mpt->m_mutex);
2071 }
2072
2073 if (mpt->m_restart_cmd_timeid) {
2074 timeout_id_t tid = mpt->m_restart_cmd_timeid;
2075 mpt->m_restart_cmd_timeid = 0;
2076 mutex_exit(&mpt->m_mutex);
2077 (void) untimeout(tid);
2078 mutex_enter(&mpt->m_mutex);
2079 }
2080
2081 mutex_exit(&mpt->m_mutex);
2082
2083 /*
2084 * last mpt? ... if active, CANCEL watch threads.
2085 */
2086 mutex_enter(&mptsas_global_mutex);
2087 if (mptsas_head == NULL) {
2088 timeout_id_t tid;
2089 /*
2090 * Clear mptsas_timeouts_enable so that the watch thread
2091 * gets restarted on DDI_ATTACH
2092 */
2093 mptsas_timeouts_enabled = 0;
2094 if (mptsas_timeout_id) {
2095 tid = mptsas_timeout_id;
2096 mptsas_timeout_id = 0;
2097 mutex_exit(&mptsas_global_mutex);
2098 (void) untimeout(tid);
2099 mutex_enter(&mptsas_global_mutex);
2100 }
2101 if (mptsas_reset_watch) {
2102 tid = mptsas_reset_watch;
2103 mptsas_reset_watch = 0;
2104 mutex_exit(&mptsas_global_mutex);
2105 (void) untimeout(tid);
2106 mutex_enter(&mptsas_global_mutex);
2107 }
2108 }
2109 mutex_exit(&mptsas_global_mutex);
2110
2111 /*
2112 * Delete Phy stats
2113 */
2114 mptsas_destroy_phy_stats(mpt);
2115
2116 mptsas_destroy_hashes(mpt);
2117
2118 /*
2119 * Delete nt_active.
2120 */
2121 mutex_enter(&mpt->m_mutex);
2122 mptsas_free_active_slots(mpt);
2123 mutex_exit(&mpt->m_mutex);
2124
2125 /* deallocate everything that was allocated in mptsas_attach */
2126 mptsas_cache_destroy(mpt);
2127
2128 mptsas_hba_fini(mpt);
2129 mptsas_cfg_fini(mpt);
2130
2131 /* Lower the power informing PM Framework */
2132 if (mpt->m_options & MPTSAS_OPT_PM) {
2133 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
2134 mptsas_log(mpt, CE_WARN,
2135 "!mptsas3%d: Lower power request failed "
2136 "during detach, ignoring.",
2137 mpt->m_instance);
2138 }
2139
2140 mutex_destroy(&mpt->m_qthread_mutex);
2141 mutex_destroy(&mpt->m_passthru_mutex);
2142 mutex_destroy(&mpt->m_mutex);
2143 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
2144 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
2145 }
2146 cv_destroy(&mpt->m_qthread_cv);
2147 cv_destroy(&mpt->m_cv);
2148 cv_destroy(&mpt->m_passthru_cv);
2149 cv_destroy(&mpt->m_fw_cv);
2150 cv_destroy(&mpt->m_config_cv);
2151 cv_destroy(&mpt->m_fw_diag_cv);
2152
2153
2154 mptsas_smp_teardown(mpt);
2155 mptsas_hba_teardown(mpt);
2156
2157 mptsas_config_space_fini(mpt);
2158
2159 mptsas_free_handshake_msg(mpt);
2160
2161 mptsas_fm_fini(mpt);
2162 ddi_soft_state_free(mptsas3_state, ddi_get_instance(dip));
2163 ddi_prop_remove_all(dip);
2164
2165 return (DDI_SUCCESS);
2166 }
2167
2168 static void
2169 mptsas_list_add(mptsas_t *mpt)
2170 {
2171 rw_enter(&mptsas_global_rwlock, RW_WRITER);
2172
2173 if (mptsas_head == NULL) {
2174 mptsas_head = mpt;
2175 } else {
2176 mptsas_tail->m_next = mpt;
2177 }
2178 mptsas_tail = mpt;
2179 rw_exit(&mptsas_global_rwlock);
2180 }
2181
2182 static void
2183 mptsas_list_del(mptsas_t *mpt)
2184 {
2185 mptsas_t *m;
2186 /*
2187 * Remove device instance from the global linked list
2188 */
2189 rw_enter(&mptsas_global_rwlock, RW_WRITER);
2190 if (mptsas_head == mpt) {
2191 m = mptsas_head = mpt->m_next;
2192 } else {
2193 for (m = mptsas_head; m != NULL; m = m->m_next) {
2194 if (m->m_next == mpt) {
2195 m->m_next = mpt->m_next;
2196 break;
2197 }
2198 }
2199 if (m == NULL) {
2200 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
2201 }
2202 }
2203
2204 if (mptsas_tail == mpt) {
2205 mptsas_tail = m;
2206 }
2207 rw_exit(&mptsas_global_rwlock);
2208 }
2209
2210 static int
2211 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
2212 {
2213 ddi_dma_attr_t task_dma_attrs;
2214
2215 mpt->m_hshk_dma_size = 0;
2216 task_dma_attrs = mpt->m_msg_dma_attr;
2217 task_dma_attrs.dma_attr_sgllen = 1;
2218 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
2219
2220 /* allocate Task Management ddi_dma resources */
2221 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
2222 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
2223 alloc_size, NULL) == FALSE) {
2224 return (DDI_FAILURE);
2225 }
2226 mpt->m_hshk_dma_size = alloc_size;
2227
2228 return (DDI_SUCCESS);
2229 }
2230
2231 static void
2232 mptsas_free_handshake_msg(mptsas_t *mpt)
2233 {
2234 if (mpt->m_hshk_dma_size == 0)
2235 return;
2236 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
2237 mpt->m_hshk_dma_size = 0;
2238 }
2239
2240 static int
2241 mptsas_hba_setup(mptsas_t *mpt)
2242 {
2243 scsi_hba_tran_t *hba_tran;
2244 int tran_flags;
2245
2246 /* Allocate a transport structure */
2247 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
2248 SCSI_HBA_CANSLEEP);
2249 ASSERT(mpt->m_tran != NULL);
2250
2251 hba_tran->tran_hba_private = mpt;
2252 hba_tran->tran_tgt_private = NULL;
2253
2254 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
2255 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
2256
2257 hba_tran->tran_start = mptsas_scsi_start;
2258 hba_tran->tran_reset = mptsas_scsi_reset;
2259 hba_tran->tran_abort = mptsas_scsi_abort;
2260 hba_tran->tran_getcap = mptsas_scsi_getcap;
2261 hba_tran->tran_setcap = mptsas_scsi_setcap;
2262 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
2263 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
2264
2265 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
2266 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
2267 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
2268
2269 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
2270 hba_tran->tran_get_name = mptsas_get_name;
2271
2272 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
2273 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
2274 hba_tran->tran_bus_reset = NULL;
2275
2276 hba_tran->tran_add_eventcall = NULL;
2277 hba_tran->tran_get_eventcookie = NULL;
2278 hba_tran->tran_post_event = NULL;
2279 hba_tran->tran_remove_eventcall = NULL;
2280
2281 hba_tran->tran_bus_config = mptsas_bus_config;
2282
2283 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2284
2285 /*
2286 * All children of the HBA are iports. We need tran was cloned.
2287 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2288 * inherited to iport's tran vector.
2289 */
2290 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2291
2292 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2293 hba_tran, tran_flags) != DDI_SUCCESS) {
2294 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2295 scsi_hba_tran_free(hba_tran);
2296 mpt->m_tran = NULL;
2297 return (FALSE);
2298 }
2299 return (TRUE);
2300 }
2301
2302 static void
2303 mptsas_hba_teardown(mptsas_t *mpt)
2304 {
2305 (void) scsi_hba_detach(mpt->m_dip);
2306 if (mpt->m_tran != NULL) {
2307 scsi_hba_tran_free(mpt->m_tran);
2308 mpt->m_tran = NULL;
2309 }
2310 }
2311
2312 static void
2313 mptsas_iport_register(mptsas_t *mpt)
2314 {
2315 int i, j;
2316 mptsas_phymask_t mask = 0x0;
2317 /*
2318 * initial value of mask is 0
2319 */
2320 mutex_enter(&mpt->m_mutex);
2321 for (i = 0; i < mpt->m_num_phys; i++) {
2322 mptsas_phymask_t phy_mask = 0x0;
2323 char phy_mask_name[MPTSAS_MAX_PHYS];
2324 uint8_t current_port;
2325
2326 if (mpt->m_phy_info[i].attached_devhdl == 0)
2327 continue;
2328
2329 bzero(phy_mask_name, sizeof (phy_mask_name));
2330
2331 current_port = mpt->m_phy_info[i].port_num;
2332
2333 if ((mask & (1 << i)) != 0)
2334 continue;
2335
2336 for (j = 0; j < mpt->m_num_phys; j++) {
2337 if (mpt->m_phy_info[j].attached_devhdl &&
2338 (mpt->m_phy_info[j].port_num == current_port)) {
2339 phy_mask |= (1 << j);
2340 }
2341 }
2342 mask = mask | phy_mask;
2343
2344 for (j = 0; j < mpt->m_num_phys; j++) {
2345 if ((phy_mask >> j) & 0x01) {
2346 mpt->m_phy_info[j].phy_mask = phy_mask;
2347 }
2348 }
2349
2350 (void) sprintf(phy_mask_name, "%x", phy_mask);
2351
2352 mutex_exit(&mpt->m_mutex);
2353 /*
2354 * register a iport
2355 */
2356 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2357 mutex_enter(&mpt->m_mutex);
2358 }
2359 mutex_exit(&mpt->m_mutex);
2360 /*
2361 * register a virtual port for RAID volume always
2362 */
2363 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2364
2365 }
2366
2367 static int
2368 mptsas_smp_setup(mptsas_t *mpt)
2369 {
2370 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2371 ASSERT(mpt->m_smptran != NULL);
2372 mpt->m_smptran->smp_tran_hba_private = mpt;
2373 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2374 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2375 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2376 smp_hba_tran_free(mpt->m_smptran);
2377 mpt->m_smptran = NULL;
2378 return (FALSE);
2379 }
2380 /*
2381 * Initialize smp hash table
2382 */
2383 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT,
2384 mptsas_target_addr_hash, mptsas_target_addr_cmp,
2385 mptsas_smp_free, sizeof (mptsas_smp_t),
2386 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr),
2387 KM_SLEEP);
2388 mpt->m_smp_devhdl = 0xFFFF;
2389
2390 return (TRUE);
2391 }
2392
2393 static void
2394 mptsas_smp_teardown(mptsas_t *mpt)
2395 {
2396 (void) smp_hba_detach(mpt->m_dip);
2397 if (mpt->m_smptran != NULL) {
2398 smp_hba_tran_free(mpt->m_smptran);
2399 mpt->m_smptran = NULL;
2400 }
2401 mpt->m_smp_devhdl = 0;
2402 }
2403
2404 static int
2405 mptsas_cache_create(mptsas_t *mpt)
2406 {
2407 int instance = mpt->m_instance;
2408 char buf[64];
2409
2410 /*
2411 * create kmem cache for packets
2412 */
2413 (void) sprintf(buf, "mptsas3%d_cache", instance);
2414 mpt->m_kmem_cache = kmem_cache_create(buf,
2415 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 16,
2416 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2417 NULL, (void *)mpt, NULL, 0);
2418
2419 if (mpt->m_kmem_cache == NULL) {
2420 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2421 return (FALSE);
2422 }
2423
2424 /*
2425 * create kmem cache for extra SGL frames if SGL cannot
2426 * be accomodated into main request frame.
2427 */
2428 (void) sprintf(buf, "mptsas3%d_cache_frames", instance);
2429 mpt->m_cache_frames = kmem_cache_create(buf,
2430 sizeof (mptsas_cache_frames_t), 16,
2431 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2432 NULL, (void *)mpt, NULL, 0);
2433
2434 if (mpt->m_cache_frames == NULL) {
2435 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2436 return (FALSE);
2437 }
2438
2439 return (TRUE);
2440 }
2441
2442 static void
2443 mptsas_cache_destroy(mptsas_t *mpt)
2444 {
2445 /* deallocate in reverse order */
2446 if (mpt->m_cache_frames) {
2447 kmem_cache_destroy(mpt->m_cache_frames);
2448 mpt->m_cache_frames = NULL;
2449 }
2450 if (mpt->m_kmem_cache) {
2451 kmem_cache_destroy(mpt->m_kmem_cache);
2452 mpt->m_kmem_cache = NULL;
2453 }
2454 }
2455
2456 static int
2457 mptsas_power(dev_info_t *dip, int component, int level)
2458 {
2459 #ifndef __lock_lint
2460 _NOTE(ARGUNUSED(component))
2461 #endif
2462 mptsas_t *mpt;
2463 int rval = DDI_SUCCESS;
2464 int polls = 0;
2465 uint32_t ioc_status;
2466
2467 if (scsi_hba_iport_unit_address(dip) != 0)
2468 return (DDI_SUCCESS);
2469
2470 mpt = ddi_get_soft_state(mptsas3_state, ddi_get_instance(dip));
2471 if (mpt == NULL) {
2472 return (DDI_FAILURE);
2473 }
2474
2475 mutex_enter(&mpt->m_mutex);
2476
2477 /*
2478 * If the device is busy, don't lower its power level
2479 */
2480 if (mpt->m_busy && (mpt->m_power_level > level)) {
2481 mutex_exit(&mpt->m_mutex);
2482 return (DDI_FAILURE);
2483 }
2484 switch (level) {
2485 case PM_LEVEL_D0:
2486 NDBG11(("mptsas3%d: turning power ON.", mpt->m_instance));
2487 MPTSAS_POWER_ON(mpt);
2488 /*
2489 * Wait up to 30 seconds for IOC to come out of reset.
2490 */
2491 while (((ioc_status = ddi_get32(mpt->m_datap,
2492 &mpt->m_reg->Doorbell)) &
2493 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2494 if (polls++ > 3000) {
2495 break;
2496 }
2497 delay(drv_usectohz(10000));
2498 }
2499 /*
2500 * If IOC is not in operational state, try to hard reset it.
2501 */
2502 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2503 MPI2_IOC_STATE_OPERATIONAL) {
2504 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2505 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2506 mptsas_log(mpt, CE_WARN,
2507 "mptsas_power: hard reset failed");
2508 mutex_exit(&mpt->m_mutex);
2509 return (DDI_FAILURE);
2510 }
2511 }
2512 mpt->m_power_level = PM_LEVEL_D0;
2513 break;
2514 case PM_LEVEL_D3:
2515 NDBG11(("mptsas3%d: turning power OFF.", mpt->m_instance));
2516 MPTSAS_POWER_OFF(mpt);
2517 break;
2518 default:
2519 mptsas_log(mpt, CE_WARN, "mptsas3%d: unknown power level <%x>.",
2520 mpt->m_instance, level);
2521 rval = DDI_FAILURE;
2522 break;
2523 }
2524 mutex_exit(&mpt->m_mutex);
2525 return (rval);
2526 }
2527
2528 /*
2529 * Initialize configuration space and figure out which
2530 * chip and revison of the chip the mpt driver is using.
2531 */
2532 static int
2533 mptsas_config_space_init(mptsas_t *mpt)
2534 {
2535 NDBG0(("mptsas_config_space_init"));
2536
2537 if (mpt->m_config_handle != NULL)
2538 return (TRUE);
2539
2540 if (pci_config_setup(mpt->m_dip,
2541 &mpt->m_config_handle) != DDI_SUCCESS) {
2542 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2543 return (FALSE);
2544 }
2545
2546 /*
2547 * This is a workaround for a XMITS ASIC bug which does not
2548 * drive the CBE upper bits.
2549 */
2550 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2551 PCI_STAT_PERROR) {
2552 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2553 PCI_STAT_PERROR);
2554 }
2555
2556 mptsas_setup_cmd_reg(mpt);
2557
2558 /*
2559 * Get the chip device id:
2560 */
2561 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2562
2563 /*
2564 * Save the revision.
2565 */
2566 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2567
2568 /*
2569 * Save the SubSystem Vendor and Device IDs
2570 */
2571 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2572 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2573
2574 /*
2575 * Set the latency timer to 0x40 as specified by the upa -> pci
2576 * bridge chip design team. This may be done by the sparc pci
2577 * bus nexus driver, but the driver should make sure the latency
2578 * timer is correct for performance reasons.
2579 */
2580 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2581 MPTSAS_LATENCY_TIMER);
2582
2583 (void) mptsas_get_pci_cap(mpt);
2584 return (TRUE);
2585 }
2586
2587 static void
2588 mptsas_config_space_fini(mptsas_t *mpt)
2589 {
2590 if (mpt->m_config_handle != NULL) {
2591 mptsas_disable_bus_master(mpt);
2592 pci_config_teardown(&mpt->m_config_handle);
2593 mpt->m_config_handle = NULL;
2594 }
2595 }
2596
2597 static void
2598 mptsas_setup_cmd_reg(mptsas_t *mpt)
2599 {
2600 ushort_t cmdreg;
2601
2602 /*
2603 * Set the command register to the needed values.
2604 */
2605 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2606 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2607 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2608 cmdreg &= ~PCI_COMM_IO;
2609 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2610 }
2611
2612 static void
2613 mptsas_disable_bus_master(mptsas_t *mpt)
2614 {
2615 ushort_t cmdreg;
2616
2617 /*
2618 * Clear the master enable bit in the PCI command register.
2619 * This prevents any bus mastering activity like DMA.
2620 */
2621 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2622 cmdreg &= ~PCI_COMM_ME;
2623 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2624 }
2625
2626 int
2627 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2628 {
2629 ddi_dma_attr_t attrs;
2630
2631 attrs = mpt->m_io_dma_attr;
2632 attrs.dma_attr_sgllen = 1;
2633
2634 ASSERT(dma_statep != NULL);
2635
2636 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2637 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2638 &dma_statep->cookie) == FALSE) {
2639 return (DDI_FAILURE);
2640 }
2641
2642 return (DDI_SUCCESS);
2643 }
2644
2645 void
2646 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2647 {
2648 ASSERT(dma_statep != NULL);
2649 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2650 dma_statep->size = 0;
2651 }
2652
2653 int
2654 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2655 {
2656 ddi_dma_attr_t attrs;
2657 ddi_dma_handle_t dma_handle;
2658 caddr_t memp;
2659 ddi_acc_handle_t accessp;
2660 int rval;
2661
2662 ASSERT(mutex_owned(&mpt->m_mutex));
2663
2664 attrs = mpt->m_msg_dma_attr;
2665 attrs.dma_attr_sgllen = 1;
2666 attrs.dma_attr_granular = size;
2667
2668 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2669 &accessp, &memp, size, NULL) == FALSE) {
2670 return (DDI_FAILURE);
2671 }
2672
2673 rval = (*callback) (mpt, memp, var, accessp);
2674
2675 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2676 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2677 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2678 rval = DDI_FAILURE;
2679 }
2680
2681 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2682 return (rval);
2683
2684 }
2685
2686 static int
2687 mptsas_alloc_request_frames(mptsas_t *mpt)
2688 {
2689 ddi_dma_attr_t frame_dma_attrs;
2690 caddr_t memp;
2691 ddi_dma_cookie_t cookie;
2692 size_t mem_size;
2693
2694 /*
2695 * re-alloc when it has already alloced
2696 */
2697 if (mpt->m_dma_flags & MPTSAS_REQ_FRAME) {
2698 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2699 &mpt->m_acc_req_frame_hdl);
2700 mpt->m_dma_flags &= ~MPTSAS_REQ_FRAME;
2701 }
2702
2703 /*
2704 * The size of the request frame pool is:
2705 * Number of Request Frames * Request Frame Size
2706 */
2707 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2708
2709 /*
2710 * set the DMA attributes. System Request Message Frames must be
2711 * aligned on a 16-byte boundry.
2712 */
2713 frame_dma_attrs = mpt->m_msg_dma_attr;
2714 frame_dma_attrs.dma_attr_align = 16;
2715 frame_dma_attrs.dma_attr_sgllen = 1;
2716
2717 /*
2718 * allocate the request frame pool.
2719 */
2720 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2721 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2722 mem_size, &cookie) == FALSE) {
2723 return (DDI_FAILURE);
2724 }
2725
2726 /*
2727 * Store the request frame memory address. This chip uses this
2728 * address to dma to and from the driver's frame. The second
2729 * address is the address mpt uses to fill in the frame.
2730 */
2731 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2732 mpt->m_req_frame = memp;
2733
2734 /*
2735 * Clear the request frame pool.
2736 */
2737 bzero(mpt->m_req_frame, mem_size);
2738
2739 mpt->m_dma_flags |= MPTSAS_REQ_FRAME;
2740 return (DDI_SUCCESS);
2741 }
2742
2743 static int
2744 mptsas_alloc_sense_bufs(mptsas_t *mpt)
2745 {
2746 ddi_dma_attr_t sense_dma_attrs;
2747 caddr_t memp;
2748 ddi_dma_cookie_t cookie;
2749 size_t mem_size;
2750 int num_extrqsense_bufs;
2751
2752 /*
2753 * re-alloc when it has already alloced
2754 */
2755 if (mpt->m_dma_flags & MPTSAS_REQ_SENSE) {
2756 rmfreemap(mpt->m_erqsense_map);
2757 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2758 &mpt->m_acc_req_sense_hdl);
2759 mpt->m_dma_flags &= ~MPTSAS_REQ_SENSE;
2760 }
2761
2762 /*
2763 * The size of the request sense pool is:
2764 * (Number of Request Frames - 2 ) * Request Sense Size +
2765 * extra memory for extended sense requests.
2766 */
2767 mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) +
2768 mptsas_extreq_sense_bufsize;
2769
2770 /*
2771 * set the DMA attributes. ARQ buffers
2772 * aligned on a 16-byte boundry.
2773 */
2774 sense_dma_attrs = mpt->m_msg_dma_attr;
2775 sense_dma_attrs.dma_attr_align = 16;
2776 sense_dma_attrs.dma_attr_sgllen = 1;
2777
2778 /*
2779 * allocate the request sense buffer pool.
2780 */
2781 if (mptsas_dma_addr_create(mpt, sense_dma_attrs,
2782 &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp,
2783 mem_size, &cookie) == FALSE) {
2784 return (DDI_FAILURE);
2785 }
2786
2787 /*
2788 * Store the request sense base memory address. This chip uses this
2789 * address to dma the request sense data. The second
2790 * address is the address mpt uses to access the data.
2791 * The third is the base for the extended rqsense buffers.
2792 */
2793 mpt->m_req_sense_dma_addr = cookie.dmac_laddress;
2794 mpt->m_req_sense = memp;
2795 memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size;
2796 mpt->m_extreq_sense = memp;
2797
2798 /*
2799 * The extra memory is divided up into multiples of the base
2800 * buffer size in order to allocate via rmalloc().
2801 * Note that the rmallocmap cannot start at zero!
2802 */
2803 num_extrqsense_bufs = mptsas_extreq_sense_bufsize /
2804 mpt->m_req_sense_size;
2805 mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs);
2806 rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1);
2807
2808 /*
2809 * Clear the pool.
2810 */
2811 bzero(mpt->m_req_sense, mem_size);
2812
2813 mpt->m_dma_flags |= MPTSAS_REQ_SENSE;
2814 return (DDI_SUCCESS);
2815 }
2816
2817 static int
2818 mptsas_alloc_reply_frames(mptsas_t *mpt)
2819 {
2820 ddi_dma_attr_t frame_dma_attrs;
2821 caddr_t memp;
2822 ddi_dma_cookie_t cookie;
2823 size_t mem_size;
2824
2825 /*
2826 * re-alloc when it has already alloced
2827 */
2828 if (mpt->m_dma_flags & MPTSAS_REPLY_FRAME) {
2829 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2830 &mpt->m_acc_reply_frame_hdl);
2831 mpt->m_dma_flags &= ~MPTSAS_REPLY_FRAME;
2832 }
2833
2834 /*
2835 * The size of the reply frame pool is:
2836 * Number of Reply Frames * Reply Frame Size
2837 */
2838 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2839
2840 /*
2841 * set the DMA attributes. System Reply Message Frames must be
2842 * aligned on a 4-byte boundry. This is the default.
2843 */
2844 frame_dma_attrs = mpt->m_msg_dma_attr;
2845 frame_dma_attrs.dma_attr_sgllen = 1;
2846
2847 /*
2848 * allocate the reply frame pool
2849 */
2850 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2851 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2852 mem_size, &cookie) == FALSE) {
2853 return (DDI_FAILURE);
2854 }
2855
2856 /*
2857 * Store the reply frame memory address. This chip uses this
2858 * address to dma to and from the driver's frame. The second
2859 * address is the address mpt uses to process the frame.
2860 */
2861 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2862 mpt->m_reply_frame = memp;
2863
2864 /*
2865 * Clear the reply frame pool.
2866 */
2867 bzero(mpt->m_reply_frame, mem_size);
2868
2869 mpt->m_dma_flags |= MPTSAS_REPLY_FRAME;
2870 return (DDI_SUCCESS);
2871 }
2872
2873 static int
2874 mptsas_alloc_free_queue(mptsas_t *mpt)
2875 {
2876 ddi_dma_attr_t frame_dma_attrs;
2877 caddr_t memp;
2878 ddi_dma_cookie_t cookie;
2879 size_t mem_size;
2880
2881 /*
2882 * re-alloc when it has already alloced
2883 */
2884 if (mpt->m_dma_flags & MPTSAS_FREE_QUEUE) {
2885 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2886 &mpt->m_acc_free_queue_hdl);
2887 mpt->m_dma_flags &= ~MPTSAS_FREE_QUEUE;
2888 }
2889
2890 /*
2891 * The reply free queue size is:
2892 * Reply Free Queue Depth * 4
2893 * The "4" is the size of one 32 bit address (low part of 64-bit
2894 * address)
2895 */
2896 mem_size = mpt->m_free_queue_depth * 4;
2897
2898 /*
2899 * set the DMA attributes The Reply Free Queue must be aligned on a
2900 * 16-byte boundry.
2901 */
2902 frame_dma_attrs = mpt->m_msg_dma_attr;
2903 frame_dma_attrs.dma_attr_align = 16;
2904 frame_dma_attrs.dma_attr_sgllen = 1;
2905
2906 /*
2907 * allocate the reply free queue
2908 */
2909 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2910 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2911 mem_size, &cookie) == FALSE) {
2912 return (DDI_FAILURE);
2913 }
2914
2915 /*
2916 * Store the reply free queue memory address. This chip uses this
2917 * address to read from the reply free queue. The second address
2918 * is the address mpt uses to manage the queue.
2919 */
2920 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2921 mpt->m_free_queue = memp;
2922
2923 /*
2924 * Clear the reply free queue memory.
2925 */
2926 bzero(mpt->m_free_queue, mem_size);
2927
2928 mpt->m_dma_flags |= MPTSAS_FREE_QUEUE;
2929 return (DDI_SUCCESS);
2930 }
2931
2932 static void
2933 mptsas_free_post_queue(mptsas_t *mpt)
2934 {
2935 mptsas_reply_pqueue_t *rpqp;
2936 int i;
2937
2938 if (mpt->m_dma_flags & MPTSAS_POST_QUEUE) {
2939 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2940 &mpt->m_acc_post_queue_hdl);
2941 rpqp = mpt->m_rep_post_queues;
2942 for (i = 0; i < mpt->m_post_reply_qcount; i++) {
2943 mutex_destroy(&rpqp->rpq_mutex);
2944 rpqp++;
2945 }
2946 kmem_free(mpt->m_rep_post_queues,
2947 sizeof (mptsas_reply_pqueue_t) *
2948 mpt->m_post_reply_qcount);
2949 mpt->m_dma_flags &= ~MPTSAS_POST_QUEUE;
2950 }
2951 }
2952
2953 static int
2954 mptsas_alloc_post_queue(mptsas_t *mpt)
2955 {
2956 ddi_dma_attr_t frame_dma_attrs;
2957 caddr_t memp;
2958 ddi_dma_cookie_t cookie;
2959 size_t mem_size;
2960 mptsas_reply_pqueue_t *rpqp;
2961 int i;
2962
2963 /*
2964 * re-alloc when it has already alloced
2965 */
2966 mptsas_free_post_queue(mpt);
2967
2968 /*
2969 * The reply descriptor post queue size is:
2970 * Reply Descriptor Post Queue Depth * 8
2971 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2972 */
2973 mpt->m_post_reply_qcount = mpt->m_intr_cnt;
2974 mem_size = mpt->m_post_queue_depth * 8 * mpt->m_post_reply_qcount;
2975
2976 /*
2977 * set the DMA attributes. The Reply Descriptor Post Queue must be
2978 * aligned on a 16-byte boundry.
2979 */
2980 frame_dma_attrs = mpt->m_msg_dma_attr;
2981 frame_dma_attrs.dma_attr_align = 16;
2982 frame_dma_attrs.dma_attr_sgllen = 1;
2983
2984 /*
2985 * Allocate the reply post queue(s).
2986 * MPI2.5 introduces a method to allocate multiple queues
2987 * using a redirect table. For now stick to one contiguous
2988 * chunck. This can get as big as 1Mbyte for 16 queues.
2989 * The spec gives no indication that the queue size can be
2990 * reduced if you have many of them.
2991 */
2992 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2993 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2994 mem_size, &cookie) == FALSE) {
2995 return (DDI_FAILURE);
2996 }
2997
2998 /*
2999 * Store the reply descriptor post queue memory address. This chip
3000 * uses this address to write to the reply descriptor post queue. The
3001 * second address is the address mpt uses to manage the queue.
3002 */
3003 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
3004 mpt->m_post_queue = memp;
3005
3006 mpt->m_rep_post_queues = kmem_zalloc(sizeof (mptsas_reply_pqueue_t) *
3007 mpt->m_post_reply_qcount, KM_SLEEP);
3008 rpqp = mpt->m_rep_post_queues;
3009 for (i = 0; i < mpt->m_post_reply_qcount; i++) {
3010 rpqp->rpq_queue = memp;
3011 mutex_init(&rpqp->rpq_mutex, NULL, MUTEX_DRIVER, NULL);
3012 rpqp->rpq_dlist.dl_tail = &rpqp->rpq_dlist.dl_q;
3013 rpqp->rpq_num = (uint8_t)i;
3014 memp += (mpt->m_post_queue_depth * 8);
3015 rpqp++;
3016 }
3017
3018 /*
3019 * Clear the reply post queue memory.
3020 */
3021 bzero(mpt->m_post_queue, mem_size);
3022
3023 mpt->m_dma_flags |= MPTSAS_POST_QUEUE;
3024 return (DDI_SUCCESS);
3025 }
3026
3027 static void
3028 mptsas_alloc_reply_args(mptsas_t *mpt)
3029 {
3030 if (mpt->m_replyh_args == NULL) {
3031 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
3032 mpt->m_max_replies, KM_SLEEP);
3033 } else {
3034 bzero(mpt->m_replyh_args, sizeof (m_replyh_arg_t) *
3035 mpt->m_max_replies);
3036 }
3037 }
3038
3039 static int
3040 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
3041 {
3042 mptsas_cache_frames_t *frames = NULL;
3043 if (cmd->cmd_extra_frames == NULL) {
3044 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
3045 if (frames == NULL) {
3046 return (DDI_FAILURE);
3047 }
3048 cmd->cmd_extra_frames = frames;
3049 }
3050 return (DDI_SUCCESS);
3051 }
3052
3053 static void
3054 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
3055 {
3056 if (cmd->cmd_extra_frames) {
3057 kmem_cache_free(mpt->m_cache_frames,
3058 (void *)cmd->cmd_extra_frames);
3059 cmd->cmd_extra_frames = NULL;
3060 }
3061 }
3062
3063 static void
3064 mptsas_cfg_fini(mptsas_t *mpt)
3065 {
3066 NDBG0(("mptsas_cfg_fini"));
3067 ddi_regs_map_free(&mpt->m_datap);
3068 }
3069
3070 static void
3071 mptsas_hba_fini(mptsas_t *mpt)
3072 {
3073 NDBG0(("mptsas_hba_fini"));
3074
3075 /*
3076 * Free up any allocated memory
3077 */
3078 if (mpt->m_dma_flags & MPTSAS_REQ_FRAME) {
3079 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
3080 &mpt->m_acc_req_frame_hdl);
3081 }
3082
3083 if (mpt->m_dma_flags & MPTSAS_REQ_SENSE) {
3084 rmfreemap(mpt->m_erqsense_map);
3085 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
3086 &mpt->m_acc_req_sense_hdl);
3087 }
3088
3089 if (mpt->m_dma_flags & MPTSAS_REPLY_FRAME) {
3090 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
3091 &mpt->m_acc_reply_frame_hdl);
3092 }
3093
3094 if (mpt->m_dma_flags & MPTSAS_FREE_QUEUE) {
3095 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
3096 &mpt->m_acc_free_queue_hdl);
3097 }
3098
3099 mptsas_free_post_queue(mpt);
3100
3101 if (mpt->m_replyh_args != NULL) {
3102 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
3103 * mpt->m_max_replies);
3104 }
3105 }
3106
3107 static int
3108 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
3109 {
3110 int lun = 0;
3111 char *sas_wwn = NULL;
3112 int phynum = -1;
3113 int reallen = 0;
3114
3115 /* Get the target num */
3116 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
3117 LUN_PROP, 0);
3118
3119 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
3120 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
3121 /*
3122 * Stick in the address of form "pPHY,LUN"
3123 */
3124 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
3125 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
3126 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
3127 == DDI_PROP_SUCCESS) {
3128 /*
3129 * Stick in the address of the form "wWWN,LUN"
3130 */
3131 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
3132 ddi_prop_free(sas_wwn);
3133 } else {
3134 return (DDI_FAILURE);
3135 }
3136
3137 ASSERT(reallen < len);
3138 if (reallen >= len) {
3139 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
3140 "length too small, it needs to be %d bytes", reallen + 1);
3141 }
3142 return (DDI_SUCCESS);
3143 }
3144
3145 /*
3146 * tran_tgt_init(9E) - target device instance initialization
3147 */
3148 static int
3149 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3150 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3151 {
3152 #ifndef __lock_lint
3153 _NOTE(ARGUNUSED(hba_tran))
3154 #endif
3155
3156 /*
3157 * At this point, the scsi_device structure already exists
3158 * and has been initialized.
3159 *
3160 * Use this function to allocate target-private data structures,
3161 * if needed by this HBA. Add revised flow-control and queue
3162 * properties for child here, if desired and if you can tell they
3163 * support tagged queueing by now.
3164 */
3165 mptsas_t *mpt;
3166 int lun = sd->sd_address.a_lun;
3167 mdi_pathinfo_t *pip = NULL;
3168 mptsas_tgt_private_t *tgt_private = NULL;
3169 mptsas_target_t *ptgt = NULL;
3170 char *psas_wwn = NULL;
3171 mptsas_phymask_t phymask = 0;
3172 uint64_t sas_wwn = 0;
3173 mptsas_target_addr_t addr;
3174 mpt = SDEV2MPT(sd);
3175
3176 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
3177
3178 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
3179 (void *)hba_dip, (void *)tgt_dip, lun));
3180
3181 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
3182 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
3183 ddi_set_name_addr(tgt_dip, NULL);
3184 return (DDI_FAILURE);
3185 }
3186 /*
3187 * phymask is 0 means the virtual port for RAID
3188 */
3189 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
3190 "phymask", 0);
3191 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3192 if ((pip = (void *)(sd->sd_private)) == NULL) {
3193 /*
3194 * Very bad news if this occurs. Somehow scsi_vhci has
3195 * lost the pathinfo node for this target.
3196 */
3197 return (DDI_NOT_WELL_FORMED);
3198 }
3199
3200 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
3201 DDI_PROP_SUCCESS) {
3202 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
3203 return (DDI_FAILURE);
3204 }
3205
3206 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
3207 &psas_wwn) == MDI_SUCCESS) {
3208 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3209 sas_wwn = 0;
3210 }
3211 (void) mdi_prop_free(psas_wwn);
3212 }
3213 } else {
3214 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
3215 DDI_PROP_DONTPASS, LUN_PROP, 0);
3216 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
3217 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
3218 DDI_PROP_SUCCESS) {
3219 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3220 sas_wwn = 0;
3221 }
3222 ddi_prop_free(psas_wwn);
3223 } else {
3224 sas_wwn = 0;
3225 }
3226 }
3227
3228 ASSERT((sas_wwn != 0) || (phymask != 0));
3229 addr.mta_wwn = sas_wwn;
3230 addr.mta_phymask = phymask;
3231 mutex_enter(&mpt->m_mutex);
3232 ptgt = refhash_lookup(mpt->m_targets, &addr);
3233 mutex_exit(&mpt->m_mutex);
3234 if (ptgt == NULL) {
3235 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
3236 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
3237 sas_wwn);
3238 return (DDI_FAILURE);
3239 }
3240 if (hba_tran->tran_tgt_private == NULL) {
3241 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
3242 KM_SLEEP);
3243 tgt_private->t_lun = lun;
3244 tgt_private->t_private = ptgt;
3245 hba_tran->tran_tgt_private = tgt_private;
3246 }
3247
3248 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3249 return (DDI_SUCCESS);
3250 }
3251 mutex_enter(&mpt->m_mutex);
3252
3253 if (ptgt->m_deviceinfo &
3254 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
3255 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
3256 uchar_t *inq89 = NULL;
3257 int inq89_len = 0x238;
3258 int reallen = 0;
3259 int rval = 0;
3260 struct sata_id *sid = NULL;
3261 char model[SATA_ID_MODEL_LEN + 1];
3262 char fw[SATA_ID_FW_LEN + 1];
3263 char *vid, *pid;
3264 int i;
3265
3266 mutex_exit(&mpt->m_mutex);
3267 /*
3268 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
3269 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
3270 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
3271 */
3272 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
3273 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
3274 inq89, inq89_len, &reallen, 1);
3275
3276 if (rval != 0) {
3277 if (inq89 != NULL) {
3278 kmem_free(inq89, inq89_len);
3279 }
3280
3281 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
3282 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
3283 return (DDI_SUCCESS);
3284 }
3285 sid = (void *)(&inq89[60]);
3286
3287 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
3288 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
3289
3290 model[SATA_ID_MODEL_LEN] = 0;
3291 fw[SATA_ID_FW_LEN] = 0;
3292
3293 /*
3294 * split model into into vid/pid
3295 */
3296 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++)
3297 if ((*pid == ' ') || (*pid == '\t'))
3298 break;
3299 if (i < SATA_ID_MODEL_LEN) {
3300 vid = model;
3301 /*
3302 * terminate vid, establish pid
3303 */
3304 *pid++ = 0;
3305 } else {
3306 /*
3307 * vid will stay "ATA ", the rule is same
3308 * as sata framework implementation.
3309 */
3310 vid = NULL;
3311 /*
3312 * model is all pid
3313 */
3314 pid = model;
3315 }
3316
3317 /*
3318 * override SCSA "inquiry-*" properties
3319 */
3320 if (vid)
3321 (void) scsi_device_prop_update_inqstring(sd,
3322 INQUIRY_VENDOR_ID, vid, strlen(vid));
3323 if (pid)
3324 (void) scsi_device_prop_update_inqstring(sd,
3325 INQUIRY_PRODUCT_ID, pid, strlen(pid));
3326 (void) scsi_device_prop_update_inqstring(sd,
3327 INQUIRY_REVISION_ID, fw, strlen(fw));
3328
3329 if (inq89 != NULL) {
3330 kmem_free(inq89, inq89_len);
3331 }
3332 } else {
3333 mutex_exit(&mpt->m_mutex);
3334 }
3335
3336 return (DDI_SUCCESS);
3337 }
3338 /*
3339 * tran_tgt_free(9E) - target device instance deallocation
3340 */
3341 static void
3342 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3343 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3344 {
3345 #ifndef __lock_lint
3346 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
3347 #endif
3348
3349 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
3350
3351 if (tgt_private != NULL) {
3352 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
3353 hba_tran->tran_tgt_private = NULL;
3354 }
3355 }
3356
3357 /*
3358 * scsi_pkt handling
3359 *
3360 * Visible to the external world via the transport structure.
3361 */
3362
3363 /*
3364 * Notes:
3365 * - transport the command to the addressed SCSI target/lun device
3366 * - normal operation is to schedule the command to be transported,
3367 * and return TRAN_ACCEPT if this is successful.
3368 * - if NO_INTR, tran_start must poll device for command completion
3369 */
3370 static int
3371 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
3372 {
3373 #ifndef __lock_lint
3374 _NOTE(ARGUNUSED(ap))
3375 #endif
3376 mptsas_t *mpt = PKT2MPT(pkt);
3377 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3378 int rval, start;
3379 uint8_t pref;
3380 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3381 mptsas_tx_waitqueue_t *txwq;
3382
3383 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
3384 ASSERT(ptgt);
3385 if (ptgt == NULL)
3386 return (TRAN_FATAL_ERROR);
3387
3388 /*
3389 * prepare the pkt before taking mutex.
3390 */
3391 rval = mptsas_prepare_pkt(cmd);
3392 if (rval != TRAN_ACCEPT) {
3393 return (rval);
3394 }
3395
3396 /*
3397 * Send the command to target/lun, however your HBA requires it.
3398 * If busy, return TRAN_BUSY; if there's some other formatting error
3399 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
3400 * return of TRAN_ACCEPT.
3401 *
3402 * Remember that access to shared resources, including the mptsas_t
3403 * data structure and the HBA hardware registers, must be protected
3404 * with mutexes, here and everywhere.
3405 *
3406 * Also remember that at interrupt time, you'll get an argument
3407 * to the interrupt handler which is a pointer to your mptsas_t
3408 * structure; you'll have to remember which commands are outstanding
3409 * and which scsi_pkt is the currently-running command so the
3410 * interrupt handler can refer to the pkt to set completion
3411 * status, call the target driver back through pkt_comp, etc.
3412 *
3413 * If the instance lock is held by other thread, don't spin to wait
3414 * for it. Instead, queue the cmd and next time when the instance lock
3415 * is not held, accept all the queued cmd. A extra tx_waitq is
3416 * introduced to protect the queue.
3417 *
3418 * The polled cmd will not be queud and accepted as usual.
3419 *
3420 * Under the tx_waitq mutex, record whether a thread is draining
3421 * the tx_waitq. An IO requesting thread that finds the instance
3422 * mutex contended appends to the tx_waitq and while holding the
3423 * tx_wait mutex, if the draining flag is not set, sets it and then
3424 * proceeds to spin for the instance mutex. This scheme ensures that
3425 * the last cmd in a burst be processed.
3426 *
3427 * we enable this feature only when the helper threads are enabled,
3428 * at which we think the loads are heavy.
3429 *
3430 * per instance, per queue mutex m_tx_waitq[i].txwq_mutex is
3431 * introduced to protect the txwq_qtail, txwq_cmdq, txwq_len
3432 */
3433
3434 if (mpt->m_txwq_enabled == TRUE) {
3435 int gotmtx = 0;
3436
3437 if (mpt->m_txwq_allow_q_jumping) {
3438 gotmtx = mutex_tryenter(&mpt->m_mutex);
3439 }
3440 if (gotmtx == 0) {
3441 /* We didn't get the mutex or didn't try */
3442 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3443 mutex_enter(&mpt->m_mutex);
3444 /* Polled commands queue jump */
3445 mptsas_accept_tx_waitqs(mpt);
3446 } else {
3447 rval = mptsas_check_targ_intxtion(
3448 cmd->cmd_tgt_addr,
3449 cmd->cmd_pkt_flags);
3450 if (rval != TRAN_ACCEPT) {
3451 return (rval);
3452 }
3453
3454 cmd->cmd_flags |= CFLAG_TXQ;
3455 pref = mpt->m_pref_tx_waitq;
3456 txwq = &mpt->m_tx_waitq[pref];
3457
3458 if (mutex_tryenter(&txwq->txwq_mutex) == 0) {
3459 txwq = &mpt->m_tx_waitq[pref^1];
3460 mutex_enter(&txwq->txwq_mutex);
3461 } else {
3462 pref ^= 1;
3463 mpt->m_pref_tx_waitq = pref;
3464 }
3465
3466 *txwq->txwq_qtail = cmd;
3467 txwq->txwq_qtail = &cmd->cmd_linkp;
3468 txwq->txwq_len++;
3469 if (!txwq->txwq_draining) {
3470 cv_signal(&txwq->txwq_cv);
3471 }
3472 mutex_exit(&txwq->txwq_mutex);
3473 return (rval);
3474 }
3475 }
3476 } else {
3477 mutex_enter(&mpt->m_mutex);
3478 }
3479 rval = mptsas_check_targ_intxtion(cmd->cmd_tgt_addr,
3480 cmd->cmd_pkt_flags);
3481 if (rval != TRAN_ACCEPT) {
3482 mutex_exit(&mpt->m_mutex);
3483 return (rval);
3484 }
3485
3486 start = mptsas_accept_pkt(mpt, cmd, &rval);
3487 mutex_exit(&mpt->m_mutex);
3488 if (start) {
3489 (void) mptsas_start_cmd(mpt, cmd);
3490 }
3491
3492 return (rval);
3493 }
3494
3495 static int
3496 mptsas_check_targ_intxtion(mptsas_target_t *ptgt, int cmd_pkt_flags)
3497 {
3498 /*
3499 * ptgt->m_dr_flag is a variable that is only ever changed by
3500 * direct write under the main m_mutex.
3501 * It doesn't need a mutex hold to protect this read.
3502 */
3503
3504 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3505 if (cmd_pkt_flags & FLAG_NOQUEUE) {
3506 /*
3507 * The command should be allowed to retry by returning
3508 * TRAN_BUSY to stall the I/O's which come from
3509 * scsi_vhci since the device/path is in unstable state
3510 * now.
3511 */
3512 return (TRAN_BUSY);
3513 } else {
3514 /*
3515 * The device is offline, just fail the command by
3516 * return TRAN_FATAL_ERROR.
3517 */
3518 return (TRAN_FATAL_ERROR);
3519 }
3520 }
3521 return (TRAN_ACCEPT);
3522 }
3523
3524 #if 0
3525 /*
3526 * Note that this function has a side effect of releasing the
3527 * per target mutex.
3528 */
3529 static void
3530 mptsas_offline_target_direct(mptsas_t *mpt, mptsas_target_t *ptgt)
3531 {
3532 char phy_mask_name[MPTSAS_MAX_PHYS];
3533 mptsas_phymask_t phymask = ptgt->m_addr.mta_phymask;
3534 dev_info_t *parent;
3535
3536 ASSERT(mutex_owned(&mpt->m_mutex));
3537
3538 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
3539 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
3540 (void) sprintf(phy_mask_name, "%x", phymask);
3541 parent = scsi_hba_iport_find(mpt->m_dip, phy_mask_name);
3542
3543 if (parent != NULL) {
3544 mptsas_offline_target(mpt, ptgt,
3545 ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED ?
3546 MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE :
3547 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE,
3548 parent);
3549 } else {
3550 mptsas_log(mpt, CE_WARN, "Failed to find an "
3551 "iport for \"%s\", should not happen!",
3552 phy_mask_name);
3553 }
3554 }
3555 #endif
3556
3557 /*
3558 * In order to be efficient with the m_mutex (which can be dropped before
3559 * calling mptsas_start_cmd()) indicate if start_cmd should be called via the
3560 * returned value (FALSE or TRUE). Caller is then responsible for doing the
3561 * right thing with the m_mutex.
3562 */
3563 static int
3564 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd, int *tran_rval)
3565 {
3566 int rval = TRAN_ACCEPT;
3567 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3568
3569 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3570
3571 ASSERT(mutex_owned(&mpt->m_mutex));
3572
3573 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3574 rval = mptsas_prepare_pkt(cmd);
3575 if (rval != TRAN_ACCEPT) {
3576 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3577 goto set_tranrval;
3578 }
3579 }
3580
3581 /*
3582 * If the command came from the tx wait q it may have slipped
3583 * by the check for dr_flag before being added to the queue.
3584 * Fail here with abort status.
3585 */
3586 if (cmd->cmd_flags & CFLAG_TXQ) {
3587 rval = mptsas_check_targ_intxtion(cmd->cmd_tgt_addr,
3588 cmd->cmd_pkt_flags);
3589 if (rval != TRAN_ACCEPT) {
3590 mptsas_set_pkt_reason(mpt, cmd, CMD_ABORTED,
3591 STAT_ABORTED);
3592 mptsas_doneq_add(mpt, cmd);
3593 mptsas_doneq_empty(mpt);
3594 goto set_tranrval;
3595 }
3596 }
3597 /*
3598 * If HBA is being reset, the DevHandles are being re-initialized,
3599 * which means that they could be invalid even if the target is still
3600 * attached. Check if being reset and if DevHandle is being
3601 * re-initialized. If this is the case, return BUSY so the I/O can be
3602 * retried later.
3603 */
3604 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3605 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3606 if (cmd->cmd_flags & CFLAG_TXQ) {
3607 mptsas_doneq_add(mpt, cmd);
3608 mptsas_doneq_empty(mpt);
3609 } else {
3610 rval = TRAN_BUSY;
3611 }
3612 goto set_tranrval;
3613 }
3614
3615 mutex_enter(&ptgt->m_t_mutex);
3616 /*
3617 * reset the throttle if we were draining
3618 */
3619 if ((ptgt->m_t_ncmds == 0) &&
3620 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3621 NDBG23(("reset throttle"));
3622 ASSERT(ptgt->m_reset_delay == 0);
3623 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3624 }
3625
3626 /*
3627 * If device handle has already been invalidated, just
3628 * fail the command. In theory, for a command from scsi_vhci
3629 * client it's impossible to receive a command with an invalid
3630 * devhdl since devhdl is set after path offline, target
3631 * driver is not supposed to select an offlined path.
3632 */
3633 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3634 NDBG3(("rejecting command, it might because invalid devhdl "
3635 "request."));
3636 mutex_exit(&ptgt->m_t_mutex);
3637 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3638 if (cmd->cmd_flags & CFLAG_TXQ) {
3639 mptsas_doneq_add(mpt, cmd);
3640 mptsas_doneq_empty(mpt);
3641 } else {
3642 rval = TRAN_FATAL_ERROR;
3643 }
3644 goto set_tranrval;
3645 }
3646 /*
3647 * The first case is the normal case. mpt gets a command from the
3648 * target driver and starts it.
3649 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3650 * commands is m_max_requests - 2.
3651 */
3652 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3653 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3654 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3655 (ptgt->m_reset_delay == 0) && (mpt->m_polled_intr == 0) &&
3656 (ptgt->m_t_nwait == 0) &&
3657 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3658 ASSERT((cmd->cmd_flags & CFLAG_CMDIOC) == 0);
3659 if (mptsas_save_cmd_to_slot(mpt, cmd) == TRUE) {
3660 ptgt->m_t_ncmds++;
3661 mutex_exit(&ptgt->m_t_mutex);
3662 cmd->cmd_active_expiration = 0;
3663 *tran_rval = rval;
3664 return (TRUE);
3665 } else {
3666 mutex_exit(&ptgt->m_t_mutex);
3667 mptsas_waitq_add(mpt, cmd);
3668 }
3669 } else {
3670 mutex_exit(&ptgt->m_t_mutex);
3671 /*
3672 * Add this pkt to the work queue
3673 */
3674 mptsas_waitq_add(mpt, cmd);
3675
3676 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3677 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3678
3679 /*
3680 * Only flush the doneq if this is not a TM
3681 * cmd. For TM cmds the flushing of the
3682 * doneq will be done in those routines.
3683 */
3684 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3685 mptsas_doneq_empty(mpt);
3686 }
3687 }
3688 }
3689 set_tranrval:
3690 *tran_rval = rval;
3691 return (FALSE);
3692 }
3693
3694 static void
3695 mptsas_retry_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3696 {
3697 int rval;
3698
3699 cmd->cmd_pkt_flags |= FLAG_HEAD;
3700 cmd->cmd_flags |= CFLAG_RETRY;
3701 cmd->cmd_flags &= ~CFLAG_TXQ;
3702 if (mptsas_accept_pkt(mpt, cmd, &rval)) {
3703 (void) mptsas_start_cmd(mpt, cmd);
3704 }
3705
3706 /*
3707 * If there was a problem clear the retry flag so that the
3708 * command will be completed with error rather than get lost!
3709 */
3710 if (rval != TRAN_ACCEPT)
3711 cmd->cmd_flags &= ~CFLAG_RETRY;
3712 }
3713
3714 static int
3715 mptsas_save_cmd_to_slot(mptsas_t *mpt, mptsas_cmd_t *cmd)
3716 {
3717 mptsas_slots_t *slots = mpt->m_active;
3718 uint_t slot, start_rotor, rotor, n_normal;
3719
3720 /*
3721 * Account for reserved TM request slot and reserved SMID of 0.
3722 */
3723 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2));
3724
3725 /*
3726 * Find the next available slot, beginning at m_rotor. If no slot is
3727 * available, we'll return FALSE to indicate that. This mechanism
3728 * considers only the normal slots, not the reserved slot 0 nor the
3729 * task management slot m_n_normal + 1. The rotor is left to point to
3730 * the normal slot after the one we select, unless we select the last
3731 * normal slot in which case it returns to slot 1.
3732 */
3733 start_rotor = rotor = slots->m_rotor;
3734 n_normal = slots->m_n_normal;
3735 do {
3736 slot = rotor++;
3737 if (rotor > n_normal)
3738 rotor = 1;
3739
3740 if (rotor == start_rotor)
3741 break;
3742 } while (slots->m_slot[slot] != NULL);
3743 slots->m_rotor = rotor;
3744
3745 if (slots->m_slot[slot] != NULL)
3746 return (FALSE);
3747
3748 ASSERT(slot != 0 && slot <= slots->m_n_normal);
3749
3750 cmd->cmd_slot = slot;
3751 slots->m_slot[slot] = cmd;
3752 atomic_inc_32(&mpt->m_ncmds);
3753
3754 /*
3755 * Distribute the commands amongst the reply queues (Interrupt vectors).
3756 * Stick to 0 for polled.
3757 */
3758 if (!(cmd->cmd_pkt_flags & FLAG_NOINTR) &&
3759 !(cmd->cmd_flags & (CFLAG_PASSTHRU|CFLAG_CONFIG|CFLAG_FW_DIAG)) &&
3760 (mpt->m_post_reply_qcount > 1)) {
3761 cmd->cmd_rpqidx = slot % mpt->m_post_reply_qcount;
3762 }
3763 atomic_inc_32(&mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds);
3764 return (TRUE);
3765 }
3766
3767 int
3768 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3769 {
3770 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3771
3772 ASSERT(MUTEX_HELD(&mpt->m_mutex));
3773
3774 if (!mptsas_save_cmd_to_slot(mpt, cmd)) {
3775 return (FALSE);
3776 }
3777
3778 /*
3779 * only increment per target ncmds if this is not a
3780 * command that has no target associated with it (i.e. a
3781 * event acknoledgement)
3782 */
3783 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3784 /*
3785 * Expiration time is set in mptsas_start_cmd
3786 */
3787 mutex_enter(&ptgt->m_t_mutex);
3788 ptgt->m_t_ncmds++;
3789 mutex_exit(&ptgt->m_t_mutex);
3790 cmd->cmd_active_expiration = 0;
3791 } else {
3792 /*
3793 * Initialize expiration time for passthrough commands,
3794 */
3795 cmd->cmd_active_expiration = gethrtime() +
3796 (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC;
3797 }
3798 return (TRUE);
3799 }
3800
3801 /*
3802 * prepare the pkt:
3803 * the pkt may have been resubmitted or just reused so
3804 * initialize some fields and do some checks.
3805 */
3806 static int
3807 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3808 {
3809 struct scsi_pkt *pkt = CMD2PKT(cmd);
3810
3811 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3812
3813 /*
3814 * Reinitialize some fields that need it; the packet may
3815 * have been resubmitted
3816 */
3817 pkt->pkt_reason = CMD_CMPLT;
3818 pkt->pkt_state = 0;
3819 pkt->pkt_statistics = 0;
3820 pkt->pkt_resid = 0;
3821 cmd->cmd_age = 0;
3822 cmd->cmd_pkt_flags = pkt->pkt_flags;
3823
3824 /*
3825 * zero status byte.
3826 */
3827 *(pkt->pkt_scbp) = 0;
3828
3829 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3830 pkt->pkt_resid = cmd->cmd_dmacount;
3831
3832 /*
3833 * consistent packets need to be sync'ed first
3834 * (only for data going out)
3835 */
3836 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3837 (cmd->cmd_flags & CFLAG_DMASEND)) {
3838 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3839 DDI_DMA_SYNC_FORDEV);
3840 }
3841 }
3842
3843 cmd->cmd_flags =
3844 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3845 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3846
3847 return (TRAN_ACCEPT);
3848 }
3849
3850 /*
3851 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3852 *
3853 * One of three possibilities:
3854 * - allocate scsi_pkt
3855 * - allocate scsi_pkt and DMA resources
3856 * - allocate DMA resources to an already-allocated pkt
3857 */
3858 static struct scsi_pkt *
3859 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3860 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3861 int (*callback)(), caddr_t arg)
3862 {
3863 mptsas_cmd_t *cmd, *new_cmd;
3864 mptsas_t *mpt = ADDR2MPT(ap);
3865 int failure = 1;
3866 uint_t oldcookiec;
3867 mptsas_target_t *ptgt = NULL;
3868 int rval;
3869 mptsas_tgt_private_t *tgt_private;
3870 int kf;
3871
3872 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3873
3874 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3875 tran_tgt_private;
3876 ASSERT(tgt_private != NULL);
3877 if (tgt_private == NULL) {
3878 return (NULL);
3879 }
3880 ptgt = tgt_private->t_private;
3881 ASSERT(ptgt != NULL);
3882 if (ptgt == NULL)
3883 return (NULL);
3884 ap->a_target = ptgt->m_devhdl;
3885 ap->a_lun = tgt_private->t_lun;
3886
3887 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3888 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3889 statuslen *= 100; tgtlen *= 4;
3890 #endif
3891 NDBG3(("mptsas_scsi_init_pkt:\n"
3892 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3893 ap->a_target, (void *)pkt, (void *)bp,
3894 cmdlen, statuslen, tgtlen, flags));
3895
3896 /*
3897 * Allocate the new packet.
3898 */
3899 if (pkt == NULL) {
3900 ddi_dma_handle_t save_dma_handle;
3901
3902 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3903
3904 if (cmd) {
3905 save_dma_handle = cmd->cmd_dmahandle;
3906 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3907 cmd->cmd_dmahandle = save_dma_handle;
3908
3909 pkt = (void *)((uchar_t *)cmd +
3910 sizeof (struct mptsas_cmd));
3911 pkt->pkt_ha_private = (opaque_t)cmd;
3912 pkt->pkt_address = *ap;
3913 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3914 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3915 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3916 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3917 cmd->cmd_cdblen = (uchar_t)cmdlen;
3918 cmd->cmd_scblen = statuslen;
3919 cmd->cmd_rqslen = SENSE_LENGTH;
3920 cmd->cmd_tgt_addr = ptgt;
3921 failure = 0;
3922 }
3923
3924 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) ||
3925 (tgtlen > PKT_PRIV_LEN) ||
3926 (statuslen > EXTCMDS_STATUS_SIZE)) {
3927 if (failure == 0) {
3928 /*
3929 * if extern alloc fails, all will be
3930 * deallocated, including cmd
3931 */
3932 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3933 cmdlen, tgtlen, statuslen, kf);
3934 }
3935 if (failure) {
3936 /*
3937 * if extern allocation fails, it will
3938 * deallocate the new pkt as well
3939 */
3940 return (NULL);
3941 }
3942 }
3943 new_cmd = cmd;
3944
3945 } else {
3946 cmd = PKT2CMD(pkt);
3947 new_cmd = NULL;
3948 }
3949
3950
3951 /* grab cmd->cmd_cookiec here as oldcookiec */
3952
3953 oldcookiec = cmd->cmd_cookiec;
3954
3955 /*
3956 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3957 * greater than 0 and we'll need to grab the next dma window
3958 */
3959 /*
3960 * SLM-not doing extra command frame right now; may add later
3961 */
3962
3963 if (cmd->cmd_nwin > 0) {
3964
3965 /*
3966 * Make sure we havn't gone past the the total number
3967 * of windows
3968 */
3969 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3970 return (NULL);
3971 }
3972 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3973 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3974 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3975 return (NULL);
3976 }
3977 goto get_dma_cookies;
3978 }
3979
3980
3981 if (flags & PKT_XARQ) {
3982 cmd->cmd_flags |= CFLAG_XARQ;
3983 }
3984
3985 /*
3986 * DMA resource allocation. This version assumes your
3987 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3988 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3989 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3990 */
3991 if (bp && (bp->b_bcount != 0) &&
3992 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3993
3994 int cnt, dma_flags;
3995 mptti_t *dmap; /* ptr to the S/G list */
3996
3997 /*
3998 * Set up DMA memory and position to the next DMA segment.
3999 */
4000 ASSERT(cmd->cmd_dmahandle != NULL);
4001
4002 if (bp->b_flags & B_READ) {
4003 dma_flags = DDI_DMA_READ;
4004 cmd->cmd_flags &= ~CFLAG_DMASEND;
4005 } else {
4006 dma_flags = DDI_DMA_WRITE;
4007 cmd->cmd_flags |= CFLAG_DMASEND;
4008 }
4009 if (flags & PKT_CONSISTENT) {
4010 cmd->cmd_flags |= CFLAG_CMDIOPB;
4011 dma_flags |= DDI_DMA_CONSISTENT;
4012 }
4013
4014 if (flags & PKT_DMA_PARTIAL) {
4015 dma_flags |= DDI_DMA_PARTIAL;
4016 }
4017
4018 /*
4019 * workaround for byte hole issue on psycho and
4020 * schizo pre 2.1
4021 */
4022 if ((bp->b_flags & B_READ) && ((bp->b_flags &
4023 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
4024 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
4025 dma_flags |= DDI_DMA_CONSISTENT;
4026 }
4027
4028 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
4029 dma_flags, callback, arg,
4030 &cmd->cmd_cookie, &cmd->cmd_cookiec);
4031 if (rval == DDI_DMA_PARTIAL_MAP) {
4032 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
4033 &cmd->cmd_nwin);
4034 cmd->cmd_winindex = 0;
4035 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
4036 cmd->cmd_winindex, &cmd->cmd_dma_offset,
4037 &cmd->cmd_dma_len, &cmd->cmd_cookie,
4038 &cmd->cmd_cookiec);
4039 } else if (rval && (rval != DDI_DMA_MAPPED)) {
4040 switch (rval) {
4041 case DDI_DMA_NORESOURCES:
4042 bioerror(bp, 0);
4043 break;
4044 case DDI_DMA_BADATTR:
4045 case DDI_DMA_NOMAPPING:
4046 bioerror(bp, EFAULT);
4047 break;
4048 case DDI_DMA_TOOBIG:
4049 default:
4050 bioerror(bp, EINVAL);
4051 break;
4052 }
4053 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4054 if (new_cmd) {
4055 mptsas_scsi_destroy_pkt(ap, pkt);
4056 }
4057 return ((struct scsi_pkt *)NULL);
4058 }
4059
4060 get_dma_cookies:
4061 cmd->cmd_flags |= CFLAG_DMAVALID;
4062 ASSERT(cmd->cmd_cookiec > 0);
4063
4064 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
4065 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
4066 cmd->cmd_cookiec);
4067 bioerror(bp, EINVAL);
4068 if (new_cmd) {
4069 mptsas_scsi_destroy_pkt(ap, pkt);
4070 }
4071 return ((struct scsi_pkt *)NULL);
4072 }
4073
4074 /*
4075 * Allocate extra SGL buffer if needed.
4076 */
4077 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
4078 (cmd->cmd_extra_frames == NULL)) {
4079 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
4080 DDI_FAILURE) {
4081 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
4082 "failed");
4083 bioerror(bp, ENOMEM);
4084 if (new_cmd) {
4085 mptsas_scsi_destroy_pkt(ap, pkt);
4086 }
4087 return ((struct scsi_pkt *)NULL);
4088 }
4089 }
4090
4091 /*
4092 * Always use scatter-gather transfer
4093 * Use the loop below to store physical addresses of
4094 * DMA segments, from the DMA cookies, into your HBA's
4095 * scatter-gather list.
4096 * We need to ensure we have enough kmem alloc'd
4097 * for the sg entries since we are no longer using an
4098 * array inside mptsas_cmd_t.
4099 *
4100 * We check cmd->cmd_cookiec against oldcookiec so
4101 * the scatter-gather list is correctly allocated
4102 */
4103
4104 if (oldcookiec != cmd->cmd_cookiec) {
4105 if (cmd->cmd_sg != (mptti_t *)NULL) {
4106 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
4107 oldcookiec);
4108 cmd->cmd_sg = NULL;
4109 }
4110 }
4111
4112 if (cmd->cmd_sg == (mptti_t *)NULL) {
4113 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
4114 cmd->cmd_cookiec), kf);
4115
4116 if (cmd->cmd_sg == (mptti_t *)NULL) {
4117 mptsas_log(mpt, CE_WARN,
4118 "unable to kmem_alloc enough memory "
4119 "for scatter/gather list");
4120 /*
4121 * if we have an ENOMEM condition we need to behave
4122 * the same way as the rest of this routine
4123 */
4124
4125 bioerror(bp, ENOMEM);
4126 if (new_cmd) {
4127 mptsas_scsi_destroy_pkt(ap, pkt);
4128 }
4129 return ((struct scsi_pkt *)NULL);
4130 }
4131 }
4132
4133 dmap = cmd->cmd_sg;
4134
4135 ASSERT(cmd->cmd_cookie.dmac_size != 0);
4136
4137 /*
4138 * store the first segment into the S/G list
4139 */
4140 dmap->count = cmd->cmd_cookie.dmac_size;
4141 dmap->addr.address64.Low = (uint32_t)
4142 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
4143 dmap->addr.address64.High = (uint32_t)
4144 (cmd->cmd_cookie.dmac_laddress >> 32);
4145
4146 /*
4147 * dmacount counts the size of the dma for this window
4148 * (if partial dma is being used). totaldmacount
4149 * keeps track of the total amount of dma we have
4150 * transferred for all the windows (needed to calculate
4151 * the resid value below).
4152 */
4153 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
4154 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
4155
4156 /*
4157 * We already stored the first DMA scatter gather segment,
4158 * start at 1 if we need to store more.
4159 */
4160 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
4161 /*
4162 * Get next DMA cookie
4163 */
4164 ddi_dma_nextcookie(cmd->cmd_dmahandle,
4165 &cmd->cmd_cookie);
4166 dmap++;
4167
4168 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
4169 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
4170
4171 /*
4172 * store the segment parms into the S/G list
4173 */
4174 dmap->count = cmd->cmd_cookie.dmac_size;
4175 dmap->addr.address64.Low = (uint32_t)
4176 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
4177 dmap->addr.address64.High = (uint32_t)
4178 (cmd->cmd_cookie.dmac_laddress >> 32);
4179 }
4180
4181 /*
4182 * If this was partially allocated we set the resid
4183 * the amount of data NOT transferred in this window
4184 * If there is only one window, the resid will be 0
4185 */
4186 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
4187 NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.",
4188 cmd->cmd_dmacount));
4189 }
4190 return (pkt);
4191 }
4192
4193 /*
4194 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
4195 *
4196 * Notes:
4197 * - also frees DMA resources if allocated
4198 * - implicit DMA synchonization
4199 */
4200 static void
4201 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4202 {
4203 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4204 mptsas_t *mpt = ADDR2MPT(ap);
4205
4206 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
4207 ap->a_target, (void *)pkt));
4208
4209 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4210 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4211 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4212 }
4213
4214 if (cmd->cmd_sg) {
4215 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
4216 cmd->cmd_sg = NULL;
4217 }
4218
4219 mptsas_free_extra_sgl_frame(mpt, cmd);
4220
4221 if ((cmd->cmd_flags &
4222 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
4223 CFLAG_SCBEXTERN)) == 0) {
4224 cmd->cmd_flags = CFLAG_FREE;
4225 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4226 } else {
4227 mptsas_pkt_destroy_extern(mpt, cmd);
4228 }
4229 }
4230
4231 /*
4232 * kmem cache constructor and destructor:
4233 * When constructing, we bzero the cmd and allocate the dma handle
4234 * When destructing, just free the dma handle
4235 */
4236 static int
4237 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
4238 {
4239 mptsas_cmd_t *cmd = buf;
4240 mptsas_t *mpt = cdrarg;
4241 int (*callback)(caddr_t);
4242
4243 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4244
4245 NDBG4(("mptsas_kmem_cache_constructor"));
4246
4247 /*
4248 * allocate a dma handle
4249 */
4250 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
4251 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
4252 cmd->cmd_dmahandle = NULL;
4253 return (-1);
4254 }
4255 return (0);
4256 }
4257
4258 static void
4259 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
4260 {
4261 #ifndef __lock_lint
4262 _NOTE(ARGUNUSED(cdrarg))
4263 #endif
4264 mptsas_cmd_t *cmd = buf;
4265
4266 NDBG4(("mptsas_kmem_cache_destructor"));
4267
4268 if (cmd->cmd_dmahandle) {
4269 ddi_dma_free_handle(&cmd->cmd_dmahandle);
4270 cmd->cmd_dmahandle = NULL;
4271 }
4272 }
4273
4274 static int
4275 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
4276 {
4277 mptsas_cache_frames_t *p = buf;
4278 mptsas_t *mpt = cdrarg;
4279 ddi_dma_attr_t frame_dma_attr;
4280 size_t mem_size, alloc_len;
4281 ddi_dma_cookie_t cookie;
4282 uint_t ncookie;
4283 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
4284 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4285
4286 frame_dma_attr = mpt->m_msg_dma_attr;
4287 frame_dma_attr.dma_attr_align = 0x10;
4288 frame_dma_attr.dma_attr_sgllen = 1;
4289
4290 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
4291 &p->m_dma_hdl) != DDI_SUCCESS) {
4292 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
4293 " extra SGL.");
4294 return (DDI_FAILURE);
4295 }
4296
4297 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
4298
4299 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
4300 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
4301 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
4302 ddi_dma_free_handle(&p->m_dma_hdl);
4303 p->m_dma_hdl = NULL;
4304 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
4305 " extra SGL.");
4306 return (DDI_FAILURE);
4307 }
4308
4309 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
4310 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
4311 &cookie, &ncookie) != DDI_DMA_MAPPED) {
4312 (void) ddi_dma_mem_free(&p->m_acc_hdl);
4313 ddi_dma_free_handle(&p->m_dma_hdl);
4314 p->m_dma_hdl = NULL;
4315 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
4316 " extra SGL");
4317 return (DDI_FAILURE);
4318 }
4319
4320 /*
4321 * Store the SGL memory address. This chip uses this
4322 * address to dma to and from the driver. The second
4323 * address is the address mpt uses to fill in the SGL.
4324 */
4325 p->m_phys_addr = cookie.dmac_laddress;
4326
4327 return (DDI_SUCCESS);
4328 }
4329
4330 static void
4331 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
4332 {
4333 #ifndef __lock_lint
4334 _NOTE(ARGUNUSED(cdrarg))
4335 #endif
4336 mptsas_cache_frames_t *p = buf;
4337 if (p->m_dma_hdl != NULL) {
4338 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
4339 (void) ddi_dma_mem_free(&p->m_acc_hdl);
4340 ddi_dma_free_handle(&p->m_dma_hdl);
4341 p->m_phys_addr = NULL;
4342 p->m_frames_addr = NULL;
4343 p->m_dma_hdl = NULL;
4344 p->m_acc_hdl = NULL;
4345 }
4346
4347 }
4348
4349 /*
4350 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
4351 * for non-standard length cdb, pkt_private, status areas
4352 * if allocation fails, then deallocate all external space and the pkt
4353 */
4354 /* ARGSUSED */
4355 static int
4356 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
4357 int cmdlen, int tgtlen, int statuslen, int kf)
4358 {
4359 caddr_t cdbp, scbp, tgt;
4360 size_t senselength;
4361
4362 NDBG3(("mptsas_pkt_alloc_extern: "
4363 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
4364 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
4365
4366 tgt = cdbp = scbp = NULL;
4367 cmd->cmd_scblen = statuslen;
4368 cmd->cmd_privlen = (uchar_t)tgtlen;
4369
4370 if (cmdlen > sizeof (cmd->cmd_cdb)) {
4371 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
4372 goto fail;
4373 }
4374 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
4375 cmd->cmd_flags |= CFLAG_CDBEXTERN;
4376 }
4377 if (tgtlen > PKT_PRIV_LEN) {
4378 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
4379 goto fail;
4380 }
4381 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
4382 cmd->cmd_pkt->pkt_private = tgt;
4383 }
4384 if (statuslen > EXTCMDS_STATUS_SIZE) {
4385 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
4386 goto fail;
4387 }
4388 cmd->cmd_flags |= CFLAG_SCBEXTERN;
4389 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
4390
4391 /* allocate sense data buf for DMA */
4392
4393 senselength = statuslen - MPTSAS_GET_ITEM_OFF(
4394 struct scsi_arq_status, sts_sensedata);
4395 if (senselength > mpt->m_req_sense_size) {
4396 unsigned long i;
4397 cmd->cmd_extrqslen = (uint16_t)senselength;
4398 cmd->cmd_extrqschunks = (senselength +
4399 (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size;
4400 i = rmalloc_wait(mpt->m_erqsense_map,
4401 cmd->cmd_extrqschunks);
4402 ASSERT(i != 0);
4403 cmd->cmd_extrqsidx = i - 1;
4404 cmd->cmd_arq_buf = mpt->m_extreq_sense +
4405 (cmd->cmd_extrqsidx * mpt->m_req_sense_size);
4406 } else {
4407 cmd->cmd_rqslen = (uchar_t)senselength;
4408 }
4409 }
4410 return (0);
4411 fail:
4412 mptsas_pkt_destroy_extern(mpt, cmd);
4413 return (1);
4414 }
4415
4416 /*
4417 * deallocate external pkt space and deallocate the pkt
4418 */
4419 static void
4420 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4421 {
4422 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4423
4424 if (cmd->cmd_flags & CFLAG_FREE) {
4425 mptsas_log(mpt, CE_PANIC,
4426 "mptsas_pkt_destroy_extern: freeing free packet");
4427 _NOTE(NOT_REACHED)
4428 /* NOTREACHED */
4429 }
4430 if (cmd->cmd_extrqslen != 0) {
4431 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
4432 cmd->cmd_extrqsidx + 1);
4433 }
4434 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4435 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4436 }
4437 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4438 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4439 }
4440 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4441 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4442 }
4443 cmd->cmd_flags = CFLAG_FREE;
4444 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4445 }
4446
4447 /*
4448 * tran_sync_pkt(9E) - explicit DMA synchronization
4449 */
4450 /*ARGSUSED*/
4451 static void
4452 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4453 {
4454 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4455
4456 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4457 ap->a_target, (void *)pkt));
4458
4459 if (cmd->cmd_dmahandle) {
4460 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4461 (cmd->cmd_flags & CFLAG_DMASEND) ?
4462 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4463 }
4464 }
4465
4466 /*
4467 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4468 */
4469 /*ARGSUSED*/
4470 static void
4471 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4472 {
4473 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4474 mptsas_t *mpt = ADDR2MPT(ap);
4475
4476 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4477 ap->a_target, (void *)pkt));
4478
4479 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4480 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4481 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4482 }
4483
4484 mptsas_free_extra_sgl_frame(mpt, cmd);
4485 }
4486
4487 static void
4488 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4489 {
4490 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4491 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4492 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4493 DDI_DMA_SYNC_FORCPU);
4494 }
4495 (*pkt->pkt_comp)(pkt);
4496 }
4497
4498 static void
4499 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4500 ddi_acc_handle_t acc_hdl, uint_t cookiec,
4501 uint32_t end_flags)
4502 {
4503 pMpi2SGESimple64_t sge;
4504 mptti_t *dmap;
4505 uint32_t flags;
4506
4507 dmap = cmd->cmd_sg;
4508
4509 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4510 while (cookiec--) {
4511 ddi_put32(acc_hdl, &sge->Address.Low,
4512 dmap->addr.address64.Low);
4513 ddi_put32(acc_hdl, &sge->Address.High,
4514 dmap->addr.address64.High);
4515 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count);
4516 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4517 flags |= ((uint32_t)
4518 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4519 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4520 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4521 MPI2_SGE_FLAGS_SHIFT);
4522
4523 /*
4524 * If this is the last cookie, we set the flags
4525 * to indicate so
4526 */
4527 if (cookiec == 0) {
4528 flags |= end_flags;
4529 }
4530 if (cmd->cmd_flags & CFLAG_DMASEND) {
4531 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4532 MPI2_SGE_FLAGS_SHIFT);
4533 } else {
4534 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4535 MPI2_SGE_FLAGS_SHIFT);
4536 }
4537 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4538 dmap++;
4539 sge++;
4540 }
4541 }
4542
4543 static void
4544 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4545 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4546 {
4547 pMpi2SGESimple64_t sge;
4548 pMpi2SGEChain64_t sgechain;
4549 uint64_t nframe_phys_addr;
4550 uint_t cookiec;
4551 mptti_t *dmap;
4552 uint32_t flags;
4553 int i, j, k, l, frames, sgemax;
4554 int temp, maxframe_sges;
4555 uint8_t chainflags;
4556 uint16_t chainlength;
4557 mptsas_cache_frames_t *p;
4558
4559 cookiec = cmd->cmd_cookiec;
4560
4561 /*
4562 * Hereby we start to deal with multiple frames.
4563 * The process is as follows:
4564 * 1. Determine how many frames are needed for SGL element
4565 * storage; Note that all frames are stored in contiguous
4566 * memory space and in 64-bit DMA mode each element is
4567 * 3 double-words (12 bytes) long.
4568 * 2. Fill up the main frame. We need to do this separately
4569 * since it contains the SCSI IO request header and needs
4570 * dedicated processing. Note that the last 4 double-words
4571 * of the SCSI IO header is for SGL element storage
4572 * (MPI2_SGE_IO_UNION).
4573 * 3. Fill the chain element in the main frame, so the DMA
4574 * engine can use the following frames.
4575 * 4. Enter a loop to fill the remaining frames. Note that the
4576 * last frame contains no chain element. The remaining
4577 * frames go into the mpt SGL buffer allocated on the fly,
4578 * not immediately following the main message frame, as in
4579 * Gen1.
4580 * Some restrictions:
4581 * 1. For 64-bit DMA, the simple element and chain element
4582 * are both of 3 double-words (12 bytes) in size, even
4583 * though all frames are stored in the first 4G of mem
4584 * range and the higher 32-bits of the address are always 0.
4585 * 2. On some controllers (like the 1064/1068), a frame can
4586 * hold SGL elements with the last 1 or 2 double-words
4587 * (4 or 8 bytes) un-used. On these controllers, we should
4588 * recognize that there's not enough room for another SGL
4589 * element and move the sge pointer to the next frame.
4590 */
4591
4592 /*
4593 * Sgemax is the number of SGE's that will fit
4594 * each extra frame and frames is total
4595 * number of frames we'll need. 1 sge entry per
4596 * frame is reseverd for the chain element thus the -1 below.
4597 */
4598 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) - 1);
4599 maxframe_sges = MPTSAS_MAX_FRAME_SGES64(mpt);
4600 temp = (cookiec - (maxframe_sges - 1)) / sgemax;
4601
4602 /*
4603 * A little check to see if we need to round up the number
4604 * of frames we need
4605 */
4606 if ((cookiec - (maxframe_sges - 1)) - (temp * sgemax) > 1) {
4607 frames = (temp + 1);
4608 } else {
4609 frames = temp;
4610 }
4611 dmap = cmd->cmd_sg;
4612 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4613
4614 /*
4615 * First fill in the main frame
4616 */
4617 j = maxframe_sges - 1;
4618 mptsas_sge_mainframe(cmd, frame, acc_hdl, j,
4619 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4620 MPI2_SGE_FLAGS_SHIFT));
4621 dmap += j;
4622 sge += j;
4623 j++;
4624
4625 /*
4626 * Fill in the chain element in the main frame.
4627 * About calculation on ChainOffset:
4628 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4629 * in the end reserved for SGL element storage
4630 * (MPI2_SGE_IO_UNION); we should count it in our
4631 * calculation. See its definition in the header file.
4632 * 2. Constant j is the counter of the current SGL element
4633 * that will be processed, and (j - 1) is the number of
4634 * SGL elements that have been processed (stored in the
4635 * main frame).
4636 * 3. ChainOffset value should be in units of double-words (4
4637 * bytes) so the last value should be divided by 4.
4638 */
4639 ddi_put8(acc_hdl, &frame->ChainOffset,
4640 (sizeof (MPI2_SCSI_IO_REQUEST) -
4641 sizeof (MPI2_SGE_IO_UNION) +
4642 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4643 sgechain = (pMpi2SGEChain64_t)sge;
4644 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4645 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4646 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4647 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4648
4649 /*
4650 * The size of the next frame is the accurate size of space
4651 * (in bytes) used to store the SGL elements. j is the counter
4652 * of SGL elements. (j - 1) is the number of SGL elements that
4653 * have been processed (stored in frames).
4654 */
4655 if (frames >= 2) {
4656 chainlength = mpt->m_req_frame_size /
4657 sizeof (MPI2_SGE_SIMPLE64) *
4658 sizeof (MPI2_SGE_SIMPLE64);
4659 } else {
4660 chainlength = ((cookiec - (j - 1)) *
4661 sizeof (MPI2_SGE_SIMPLE64));
4662 }
4663
4664 p = cmd->cmd_extra_frames;
4665
4666 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4667 ddi_put32(acc_hdl, &sgechain->Address.Low,
4668 (p->m_phys_addr&0xffffffffull));
4669 ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr>>32);
4670
4671 /*
4672 * If there are more than 2 frames left we have to
4673 * fill in the next chain offset to the location of
4674 * the chain element in the next frame.
4675 * sgemax is the number of simple elements in an extra
4676 * frame. Note that the value NextChainOffset should be
4677 * in double-words (4 bytes).
4678 */
4679 if (frames >= 2) {
4680 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4681 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4682 } else {
4683 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4684 }
4685
4686 /*
4687 * Jump to next frame;
4688 * Starting here, chain buffers go into the per command SGL.
4689 * This buffer is allocated when chain buffers are needed.
4690 */
4691 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4692 i = cookiec;
4693
4694 /*
4695 * Start filling in frames with SGE's. If we
4696 * reach the end of frame and still have SGE's
4697 * to fill we need to add a chain element and
4698 * use another frame. j will be our counter
4699 * for what cookie we are at and i will be
4700 * the total cookiec. k is the current frame
4701 */
4702 for (k = 1; k <= frames; k++) {
4703 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4704
4705 /*
4706 * If we have reached the end of frame
4707 * and we have more SGE's to fill in
4708 * we have to fill the final entry
4709 * with a chain element and then
4710 * continue to the next frame
4711 */
4712 if ((l == (sgemax + 1)) && (k != frames)) {
4713 sgechain = (pMpi2SGEChain64_t)sge;
4714 j--;
4715 chainflags = (
4716 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4717 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4718 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4719 ddi_put8(p->m_acc_hdl,
4720 &sgechain->Flags, chainflags);
4721 /*
4722 * k is the frame counter and (k + 1)
4723 * is the number of the next frame.
4724 * Note that frames are in contiguous
4725 * memory space.
4726 */
4727 nframe_phys_addr = p->m_phys_addr +
4728 (mpt->m_req_frame_size * k);
4729 ddi_put32(p->m_acc_hdl,
4730 &sgechain->Address.Low,
4731 nframe_phys_addr&0xffffffffull);
4732 ddi_put32(p->m_acc_hdl,
4733 &sgechain->Address.High,
4734 nframe_phys_addr>>32);
4735
4736 /*
4737 * If there are more than 2 frames left
4738 * we have to next chain offset to
4739 * the location of the chain element
4740 * in the next frame and fill in the
4741 * length of the next chain
4742 */
4743 if ((frames - k) >= 2) {
4744 ddi_put8(p->m_acc_hdl,
4745 &sgechain->NextChainOffset,
4746 (sgemax *
4747 sizeof (MPI2_SGE_SIMPLE64))
4748 >> 2);
4749 ddi_put16(p->m_acc_hdl,
4750 &sgechain->Length,
4751 mpt->m_req_frame_size /
4752 sizeof (MPI2_SGE_SIMPLE64) *
4753 sizeof (MPI2_SGE_SIMPLE64));
4754 } else {
4755 /*
4756 * This is the last frame. Set
4757 * the NextChainOffset to 0 and
4758 * Length is the total size of
4759 * all remaining simple elements
4760 */
4761 ddi_put8(p->m_acc_hdl,
4762 &sgechain->NextChainOffset,
4763 0);
4764 ddi_put16(p->m_acc_hdl,
4765 &sgechain->Length,
4766 (cookiec - j) *
4767 sizeof (MPI2_SGE_SIMPLE64));
4768 }
4769
4770 /* Jump to the next frame */
4771 sge = (pMpi2SGESimple64_t)
4772 ((char *)p->m_frames_addr +
4773 (int)mpt->m_req_frame_size * k);
4774
4775 continue;
4776 }
4777
4778 ddi_put32(p->m_acc_hdl,
4779 &sge->Address.Low,
4780 dmap->addr.address64.Low);
4781 ddi_put32(p->m_acc_hdl,
4782 &sge->Address.High,
4783 dmap->addr.address64.High);
4784 ddi_put32(p->m_acc_hdl,
4785 &sge->FlagsLength, dmap->count);
4786 flags = ddi_get32(p->m_acc_hdl,
4787 &sge->FlagsLength);
4788 flags |= ((uint32_t)(
4789 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4790 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4791 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4792 MPI2_SGE_FLAGS_SHIFT);
4793
4794 /*
4795 * If we are at the end of the frame and
4796 * there is another frame to fill in
4797 * we set the last simple element as last
4798 * element
4799 */
4800 if ((l == sgemax) && (k != frames)) {
4801 flags |= ((uint32_t)
4802 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4803 MPI2_SGE_FLAGS_SHIFT);
4804 }
4805
4806 /*
4807 * If this is the final cookie we
4808 * indicate it by setting the flags
4809 */
4810 if (j == i) {
4811 flags |= ((uint32_t)
4812 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4813 MPI2_SGE_FLAGS_END_OF_BUFFER |
4814 MPI2_SGE_FLAGS_END_OF_LIST) <<
4815 MPI2_SGE_FLAGS_SHIFT);
4816 }
4817 if (cmd->cmd_flags & CFLAG_DMASEND) {
4818 flags |=
4819 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4820 MPI2_SGE_FLAGS_SHIFT);
4821 } else {
4822 flags |=
4823 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4824 MPI2_SGE_FLAGS_SHIFT);
4825 }
4826 ddi_put32(p->m_acc_hdl,
4827 &sge->FlagsLength, flags);
4828 dmap++;
4829 sge++;
4830 }
4831 }
4832
4833 /*
4834 * Sync DMA with the chain buffers that were just created
4835 */
4836 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4837 }
4838
4839 static void
4840 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4841 ddi_acc_handle_t acc_hdl, uint_t cookiec,
4842 uint8_t end_flag)
4843 {
4844 pMpi2IeeeSgeSimple64_t ieeesge;
4845 mptti_t *dmap;
4846 uint8_t flags;
4847
4848 dmap = cmd->cmd_sg;
4849
4850 NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec,
4851 cmd->cmd_flags & CFLAG_DMASEND?"Out":"In"));
4852
4853 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4854 while (cookiec--) {
4855 ddi_put32(acc_hdl, &ieeesge->Address.Low,
4856 dmap->addr.address64.Low);
4857 ddi_put32(acc_hdl, &ieeesge->Address.High,
4858 dmap->addr.address64.High);
4859 ddi_put32(acc_hdl, &ieeesge->Length, dmap->count);
4860 NDBG1(("mptsas_ieee_sge_mainframe: len=%d, high=0x%x",
4861 dmap->count, dmap->addr.address64.High));
4862 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
4863 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4864
4865 /*
4866 * If this is the last cookie, we set the flags
4867 * to indicate so
4868 */
4869 if (cookiec == 0) {
4870 flags |= end_flag;
4871 }
4872
4873 /*
4874 * XXX: Hmmm, what about the direction based on
4875 * cmd->cmd_flags & CFLAG_DMASEND?
4876 */
4877 ddi_put8(acc_hdl, &ieeesge->Flags, flags);
4878 dmap++;
4879 ieeesge++;
4880 }
4881 }
4882
4883 static void
4884 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4885 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4886 {
4887 pMpi2IeeeSgeSimple64_t ieeesge;
4888 pMpi25IeeeSgeChain64_t ieeesgechain;
4889 uint64_t nframe_phys_addr;
4890 uint_t cookiec;
4891 mptti_t *dmap;
4892 uint8_t flags;
4893 int i, j, k, l, frames, sgemax;
4894 int temp, maxframe_sges;
4895 uint8_t chainflags;
4896 uint32_t chainlength;
4897 mptsas_cache_frames_t *p;
4898
4899 cookiec = cmd->cmd_cookiec;
4900
4901 NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec));
4902
4903 /*
4904 * Hereby we start to deal with multiple frames.
4905 * The process is as follows:
4906 * 1. Determine how many frames are needed for SGL element
4907 * storage; Note that all frames are stored in contiguous
4908 * memory space and in 64-bit DMA mode each element is
4909 * 4 double-words (16 bytes) long.
4910 * 2. Fill up the main frame. We need to do this separately
4911 * since it contains the SCSI IO request header and needs
4912 * dedicated processing. Note that the last 4 double-words
4913 * of the SCSI IO header is for SGL element storage
4914 * (MPI2_SGE_IO_UNION).
4915 * 3. Fill the chain element in the main frame, so the DMA
4916 * engine can use the following frames.
4917 * 4. Enter a loop to fill the remaining frames. Note that the
4918 * last frame contains no chain element. The remaining
4919 * frames go into the mpt SGL buffer allocated on the fly,
4920 * not immediately following the main message frame, as in
4921 * Gen1.
4922 * Some restrictions:
4923 * 1. For 64-bit DMA, the simple element and chain element
4924 * are both of 4 double-words (16 bytes) in size, even
4925 * though all frames are stored in the first 4G of mem
4926 * range and the higher 32-bits of the address are always 0.
4927 * 2. On some controllers (like the 1064/1068), a frame can
4928 * hold SGL elements with the last 1 or 2 double-words
4929 * (4 or 8 bytes) un-used. On these controllers, we should
4930 * recognize that there's not enough room for another SGL
4931 * element and move the sge pointer to the next frame.
4932 */
4933
4934 /*
4935 * Sgemax is the number of SGE's that will fit
4936 * each extra frame and frames is total
4937 * number of frames we'll need. 1 sge entry per
4938 * frame is reseverd for the chain element thus the -1 below.
4939 */
4940 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64))
4941 - 1);
4942 maxframe_sges = MPTSAS_MAX_FRAME_SGES64(mpt);
4943 temp = (cookiec - (maxframe_sges - 1)) / sgemax;
4944
4945 /*
4946 * A little check to see if we need to round up the number
4947 * of frames we need
4948 */
4949 if ((cookiec - (maxframe_sges - 1)) - (temp * sgemax) > 1) {
4950 frames = (temp + 1);
4951 } else {
4952 frames = temp;
4953 }
4954 NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames));
4955 dmap = cmd->cmd_sg;
4956 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4957
4958 /*
4959 * First fill in the main frame
4960 */
4961 j = maxframe_sges - 1;
4962 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0);
4963 dmap += j;
4964 ieeesge += j;
4965 j++;
4966
4967 /*
4968 * Fill in the chain element in the main frame.
4969 * About calculation on ChainOffset:
4970 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4971 * in the end reserved for SGL element storage
4972 * (MPI2_SGE_IO_UNION); we should count it in our
4973 * calculation. See its definition in the header file.
4974 * 2. Constant j is the counter of the current SGL element
4975 * that will be processed, and (j - 1) is the number of
4976 * SGL elements that have been processed (stored in the
4977 * main frame).
4978 * 3. ChainOffset value should be in units of quad-words (16
4979 * bytes) so the last value should be divided by 16.
4980 */
4981 ddi_put8(acc_hdl, &frame->ChainOffset,
4982 (sizeof (MPI2_SCSI_IO_REQUEST) -
4983 sizeof (MPI2_SGE_IO_UNION) +
4984 (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4985 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4986 chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4987 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4988 ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags);
4989
4990 /*
4991 * The size of the next frame is the accurate size of space
4992 * (in bytes) used to store the SGL elements. j is the counter
4993 * of SGL elements. (j - 1) is the number of SGL elements that
4994 * have been processed (stored in frames).
4995 */
4996 if (frames >= 2) {
4997 chainlength = mpt->m_req_frame_size /
4998 sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4999 sizeof (MPI2_IEEE_SGE_SIMPLE64);
5000 } else {
5001 chainlength = ((cookiec - (j - 1)) *
5002 sizeof (MPI2_IEEE_SGE_SIMPLE64));
5003 }
5004
5005 p = cmd->cmd_extra_frames;
5006
5007 ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength);
5008 ddi_put32(acc_hdl, &ieeesgechain->Address.Low,
5009 p->m_phys_addr&0xffffffffull);
5010 ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr>>32);
5011
5012 /*
5013 * If there are more than 2 frames left we have to
5014 * fill in the next chain offset to the location of
5015 * the chain element in the next frame.
5016 * sgemax is the number of simple elements in an extra
5017 * frame. Note that the value NextChainOffset should be
5018 * in double-words (4 bytes).
5019 */
5020 if (frames >= 2) {
5021 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset,
5022 (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
5023 } else {
5024 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0);
5025 }
5026
5027 /*
5028 * Jump to next frame;
5029 * Starting here, chain buffers go into the per command SGL.
5030 * This buffer is allocated when chain buffers are needed.
5031 */
5032 ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr;
5033 i = cookiec;
5034
5035 /*
5036 * Start filling in frames with SGE's. If we
5037 * reach the end of frame and still have SGE's
5038 * to fill we need to add a chain element and
5039 * use another frame. j will be our counter
5040 * for what cookie we are at and i will be
5041 * the total cookiec. k is the current frame
5042 */
5043 for (k = 1; k <= frames; k++) {
5044 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
5045
5046 /*
5047 * If we have reached the end of frame
5048 * and we have more SGE's to fill in
5049 * we have to fill the final entry
5050 * with a chain element and then
5051 * continue to the next frame
5052 */
5053 if ((l == (sgemax + 1)) && (k != frames)) {
5054 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
5055 j--;
5056 chainflags =
5057 MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
5058 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
5059 ddi_put8(p->m_acc_hdl,
5060 &ieeesgechain->Flags, chainflags);
5061 /*
5062 * k is the frame counter and (k + 1)
5063 * is the number of the next frame.
5064 * Note that frames are in contiguous
5065 * memory space.
5066 */
5067 nframe_phys_addr = p->m_phys_addr +
5068 (mpt->m_req_frame_size * k);
5069 ddi_put32(p->m_acc_hdl,
5070 &ieeesgechain->Address.Low,
5071 nframe_phys_addr&0xffffffffull);
5072 ddi_put32(p->m_acc_hdl,
5073 &ieeesgechain->Address.High,
5074 nframe_phys_addr>>32);
5075
5076 /*
5077 * If there are more than 2 frames left
5078 * we have to next chain offset to
5079 * the location of the chain element
5080 * in the next frame and fill in the
5081 * length of the next chain
5082 */
5083 if ((frames - k) >= 2) {
5084 ddi_put8(p->m_acc_hdl,
5085 &ieeesgechain->NextChainOffset,
5086 (sgemax *
5087 sizeof (MPI2_IEEE_SGE_SIMPLE64))
5088 >> 4);
5089 ddi_put32(p->m_acc_hdl,
5090 &ieeesgechain->Length,
5091 mpt->m_req_frame_size /
5092 sizeof (MPI2_IEEE_SGE_SIMPLE64) *
5093 sizeof (MPI2_IEEE_SGE_SIMPLE64));
5094 } else {
5095 /*
5096 * This is the last frame. Set
5097 * the NextChainOffset to 0 and
5098 * Length is the total size of
5099 * all remaining simple elements
5100 */
5101 ddi_put8(p->m_acc_hdl,
5102 &ieeesgechain->NextChainOffset,
5103 0);
5104 ddi_put32(p->m_acc_hdl,
5105 &ieeesgechain->Length,
5106 (cookiec - j) *
5107 sizeof (MPI2_IEEE_SGE_SIMPLE64));
5108 }
5109
5110 /* Jump to the next frame */
5111 ieeesge = (pMpi2IeeeSgeSimple64_t)
5112 ((char *)p->m_frames_addr +
5113 (int)mpt->m_req_frame_size * k);
5114
5115 continue;
5116 }
5117
5118 ddi_put32(p->m_acc_hdl,
5119 &ieeesge->Address.Low,
5120 dmap->addr.address64.Low);
5121 ddi_put32(p->m_acc_hdl,
5122 &ieeesge->Address.High,
5123 dmap->addr.address64.High);
5124 ddi_put32(p->m_acc_hdl,
5125 &ieeesge->Length, dmap->count);
5126 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
5127 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
5128
5129 /*
5130 * If we are at the end of the frame and
5131 * there is another frame to fill in
5132 * do we need to do anything?
5133 * if ((l == sgemax) && (k != frames)) {
5134 * }
5135 */
5136
5137 /*
5138 * If this is the final cookie set end of list.
5139 */
5140 if (j == i) {
5141 flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
5142 }
5143
5144 ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags);
5145 dmap++;
5146 ieeesge++;
5147 }
5148 }
5149
5150 /*
5151 * Sync DMA with the chain buffers that were just created
5152 */
5153 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
5154 }
5155
5156 static void
5157 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
5158 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
5159 {
5160 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
5161
5162 NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec));
5163
5164 /*
5165 * Set read/write bit in control.
5166 */
5167 if (cmd->cmd_flags & CFLAG_DMASEND) {
5168 *control |= MPI2_SCSIIO_CONTROL_WRITE;
5169 } else {
5170 *control |= MPI2_SCSIIO_CONTROL_READ;
5171 }
5172
5173 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
5174
5175 /*
5176 * We have 4 cases here. First where we can fit all the
5177 * SG elements into the main frame, and the case
5178 * where we can't. The SG element is also different when using
5179 * MPI2.5 interface.
5180 * If we have more cookies than we can attach to a frame
5181 * we will need to use a chain element to point
5182 * a location of memory where the rest of the S/G
5183 * elements reside.
5184 */
5185 if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
5186 if (mpt->m_MPI25) {
5187 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl,
5188 cmd->cmd_cookiec,
5189 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
5190 } else {
5191 mptsas_sge_mainframe(cmd, frame, acc_hdl,
5192 cmd->cmd_cookiec,
5193 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
5194 | MPI2_SGE_FLAGS_END_OF_BUFFER
5195 | MPI2_SGE_FLAGS_END_OF_LIST) <<
5196 MPI2_SGE_FLAGS_SHIFT));
5197 }
5198 } else {
5199 if (mpt->m_MPI25) {
5200 mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl);
5201 } else {
5202 mptsas_sge_chain(mpt, cmd, frame, acc_hdl);
5203 }
5204 }
5205 }
5206
5207 /*
5208 * Interrupt handling
5209 * Utility routine. Poll for status of a command sent to HBA
5210 * without interrupts (a FLAG_NOINTR command).
5211 */
5212 int
5213 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
5214 {
5215 int rval = TRUE;
5216 uint32_t int_mask;
5217
5218 NDBG5(("mptsas_poll: cmd=0x%p, flags 0x%x", (void *)poll_cmd,
5219 poll_cmd->cmd_flags));
5220
5221 /*
5222 * Get the current interrupt mask and disable interrupts. When
5223 * re-enabling ints, set mask to saved value.
5224 */
5225 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
5226 MPTSAS_DISABLE_INTR(mpt);
5227
5228 mpt->m_polled_intr = 1;
5229
5230 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
5231 mptsas_restart_hba(mpt);
5232 }
5233
5234 /*
5235 * Wait, using drv_usecwait(), long enough for the command to
5236 * reasonably return from the target if the target isn't
5237 * "dead". A polled command may well be sent from scsi_poll, and
5238 * there are retries built in to scsi_poll if the transport
5239 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
5240 * and retries the transport up to scsi_poll_busycnt times
5241 * (currently 60) if
5242 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
5243 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
5244 *
5245 * limit the waiting to avoid a hang in the event that the
5246 * cmd never gets started but we are still receiving interrupts
5247 */
5248 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
5249 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
5250 NDBG5(("mptsas_poll: command incomplete"));
5251 rval = FALSE;
5252 break;
5253 }
5254 }
5255
5256 if (rval == FALSE) {
5257
5258 /*
5259 * this isn't supposed to happen, the hba must be wedged
5260 * Mark this cmd as a timeout.
5261 */
5262 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
5263 (STAT_TIMEOUT|STAT_ABORTED));
5264
5265 if (poll_cmd->cmd_queued == FALSE) {
5266
5267 NDBG5(("mptsas_poll: not on waitq"));
5268
5269 poll_cmd->cmd_pkt->pkt_state |=
5270 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
5271 } else {
5272
5273 /* find and remove it from the waitq */
5274 NDBG5(("mptsas_poll: delete from waitq"));
5275 mptsas_waitq_delete(mpt, poll_cmd);
5276 }
5277
5278 }
5279 mptsas_fma_check(mpt, poll_cmd);
5280
5281 /*
5282 * Clear polling flag, re-enable interrupts.
5283 */
5284 mpt->m_polled_intr = 0;
5285 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
5286
5287 /*
5288 * If there are queued cmd, start them now.
5289 */
5290 if (mpt->m_waitq != NULL) {
5291 mptsas_restart_waitq(mpt);
5292 }
5293
5294 NDBG5(("mptsas_poll: done"));
5295 return (rval);
5296 }
5297
5298 /*
5299 * Used for polling cmds and TM function
5300 */
5301 static int
5302 mptsas_wait_intr(mptsas_t *mpt, int polltime)
5303 {
5304 int cnt, rval = FALSE;
5305 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5306 mptsas_reply_pqueue_t *rpqp;
5307
5308 NDBG5(("mptsas_wait_intr"));
5309 ASSERT(mutex_owned(&mpt->m_mutex));
5310
5311 /*
5312 * Keep polling for at least (polltime * 1000) seconds
5313 */
5314 rpqp = mpt->m_rep_post_queues;
5315
5316 /*
5317 * Drop the main mutex and grab the mutex for reply queue 0
5318 */
5319 mutex_exit(&mpt->m_mutex);
5320 mutex_enter(&rpqp->rpq_mutex);
5321 for (cnt = 0; cnt < polltime; cnt++) {
5322 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5323 DDI_DMA_SYNC_FORCPU);
5324
5325 /*
5326 * Polled requests should only come back through
5327 * the first interrupt.
5328 */
5329 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5330 MPTSAS_GET_NEXT_REPLY(rpqp, rpqp->rpq_index);
5331
5332 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5333 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5334 ddi_get32(mpt->m_acc_post_queue_hdl,
5335 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5336 drv_usecwait(1000);
5337 continue;
5338 }
5339
5340 /*
5341 * The reply is valid, process it according to its
5342 * type.
5343 */
5344 mptsas_process_intr(mpt, rpqp, reply_desc_union);
5345
5346 /*
5347 * Clear the reply descriptor for re-use.
5348 */
5349 ddi_put64(mpt->m_acc_post_queue_hdl,
5350 &((uint64_t *)(void *)rpqp->rpq_queue)[rpqp->rpq_index],
5351 0xFFFFFFFFFFFFFFFF);
5352 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5353 DDI_DMA_SYNC_FORDEV);
5354
5355 if (++rpqp->rpq_index == mpt->m_post_queue_depth) {
5356 rpqp->rpq_index = 0;
5357 }
5358
5359 /*
5360 * Update the reply index
5361 */
5362 ddi_put32(mpt->m_datap,
5363 &mpt->m_reg->ReplyPostHostIndex, rpqp->rpq_index);
5364 rval = TRUE;
5365 break;
5366 }
5367
5368 mutex_exit(&rpqp->rpq_mutex);
5369 mutex_enter(&mpt->m_mutex);
5370
5371 return (rval);
5372 }
5373
5374 static void
5375 mptsas_handle_scsi_io_success(mptsas_t *mpt,
5376 mptsas_reply_pqueue_t *rpqp,
5377 pMpi2ReplyDescriptorsUnion_t reply_desc)
5378 {
5379 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
5380 uint16_t SMID;
5381 mptsas_slots_t *slots = mpt->m_active;
5382 mptsas_cmd_t *cmd = NULL;
5383 struct scsi_pkt *pkt;
5384
5385 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
5386 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
5387
5388 /*
5389 * This is a success reply so just complete the IO. First, do a sanity
5390 * check on the SMID. The final slot is used for TM requests, which
5391 * would not come into this reply handler.
5392 */
5393 if ((SMID == 0) || (SMID > slots->m_n_normal)) {
5394 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
5395 SMID);
5396 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5397 return;
5398 }
5399
5400 cmd = slots->m_slot[SMID];
5401
5402 /*
5403 * print warning and return if the slot is empty
5404 */
5405 if (cmd == NULL) {
5406 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
5407 "in slot %d", SMID);
5408 return;
5409 }
5410 ASSERT(cmd->cmd_rpqidx == rpqp->rpq_num);
5411
5412 pkt = CMD2PKT(cmd);
5413 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
5414 STATE_GOT_STATUS);
5415 if (cmd->cmd_flags & CFLAG_DMAVALID) {
5416 pkt->pkt_state |= STATE_XFERRED_DATA;
5417 }
5418 pkt->pkt_resid = 0;
5419
5420 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
5421 cmd->cmd_flags |= CFLAG_FINISHED;
5422 cv_broadcast(&mpt->m_passthru_cv);
5423 return;
5424 }
5425 if (!(cmd->cmd_flags & CFLAG_TM_CMD)) {
5426 if (cmd->cmd_flags & CFLAG_CMDIOC) {
5427 mutex_enter(&mpt->m_mutex);
5428 mptsas_remove_cmd(mpt, cmd);
5429 mutex_exit(&mpt->m_mutex);
5430 } else {
5431 #ifdef MPTSAS_DEBUG
5432 /*
5433 * In order to test timeout for a command set
5434 * mptsas_test_timeout via mdb to avoid completion
5435 * processing here.
5436 */
5437 if (mptsas_test_timeout) {
5438 mptsas_test_timeout = 0;
5439 return;
5440 }
5441 #endif
5442 /*
5443 * This is the normal path, avoid grabbing
5444 * the m_mutex.
5445 */
5446 mptsas_remove_cmd_nomtx(mpt, cmd);
5447 }
5448 }
5449
5450 if (cmd->cmd_flags & CFLAG_RETRY) {
5451 /*
5452 * The target returned QFULL or busy, do not add tihs
5453 * pkt to the doneq since the hba will retry
5454 * this cmd.
5455 *
5456 * The pkt has already been resubmitted in
5457 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5458 * Remove this cmd_flag here.
5459 */
5460 cmd->cmd_flags &= ~CFLAG_RETRY;
5461 } else {
5462 mptsas_rpdoneq_add(mpt, rpqp, cmd);
5463 }
5464 }
5465
5466 static void
5467 mptsas_handle_address_reply(mptsas_t *mpt,
5468 pMpi2ReplyDescriptorsUnion_t reply_desc)
5469 {
5470 pMpi2AddressReplyDescriptor_t address_reply;
5471 pMPI2DefaultReply_t reply;
5472 mptsas_fw_diagnostic_buffer_t *pBuffer;
5473 uint32_t reply_addr, reply_frame_dma_baseaddr;
5474 uint16_t SMID, iocstatus;
5475 mptsas_slots_t *slots = mpt->m_active;
5476 mptsas_cmd_t *cmd = NULL;
5477 uint8_t function, buffer_type;
5478 m_replyh_arg_t *args;
5479 int reply_frame_no;
5480
5481 ASSERT(mutex_owned(&mpt->m_mutex));
5482
5483 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
5484 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
5485 &address_reply->ReplyFrameAddress);
5486 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
5487
5488 /*
5489 * If reply frame is not in the proper range we should ignore this
5490 * message and exit the interrupt handler.
5491 */
5492 reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xfffffffful;
5493 if ((reply_addr < reply_frame_dma_baseaddr) ||
5494 (reply_addr >= (reply_frame_dma_baseaddr +
5495 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
5496 ((reply_addr - reply_frame_dma_baseaddr) %
5497 mpt->m_reply_frame_size != 0)) {
5498 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
5499 "address 0x%x\n", reply_addr);
5500 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5501 return;
5502 }
5503
5504 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
5505 DDI_DMA_SYNC_FORCPU);
5506 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
5507 reply_frame_dma_baseaddr));
5508 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
5509
5510 NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x",
5511 function, reply_addr));
5512
5513 /*
5514 * don't get slot information and command for events since these values
5515 * don't exist
5516 */
5517 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
5518 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
5519 /*
5520 * This could be a TM reply, which use the last allocated SMID,
5521 * so allow for that.
5522 */
5523 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) {
5524 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
5525 "%d\n", SMID);
5526 ddi_fm_service_impact(mpt->m_dip,
5527 DDI_SERVICE_UNAFFECTED);
5528 return;
5529 }
5530
5531 cmd = slots->m_slot[SMID];
5532
5533 /*
5534 * print warning and return if the slot is empty
5535 */
5536 if (cmd == NULL) {
5537 mptsas_log(mpt, CE_WARN, "?NULL command for address "
5538 "reply in slot %d", SMID);
5539 return;
5540 }
5541 if ((cmd->cmd_flags &
5542 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
5543 cmd->cmd_rfm = reply_addr;
5544 cmd->cmd_flags |= CFLAG_FINISHED;
5545 cv_broadcast(&mpt->m_passthru_cv);
5546 cv_broadcast(&mpt->m_config_cv);
5547 cv_broadcast(&mpt->m_fw_diag_cv);
5548 return;
5549 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
5550 mptsas_remove_cmd(mpt, cmd);
5551 }
5552 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
5553 }
5554 /*
5555 * Depending on the function, we need to handle
5556 * the reply frame (and cmd) differently.
5557 */
5558 switch (function) {
5559 case MPI2_FUNCTION_SCSI_IO_REQUEST:
5560 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
5561 break;
5562 case MPI2_FUNCTION_SCSI_TASK_MGMT:
5563 cmd->cmd_rfm = reply_addr;
5564 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
5565 cmd);
5566 break;
5567 case MPI2_FUNCTION_FW_DOWNLOAD:
5568 cmd->cmd_flags |= CFLAG_FINISHED;
5569 cv_signal(&mpt->m_fw_cv);
5570 break;
5571 case MPI2_FUNCTION_EVENT_NOTIFICATION:
5572 reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) /
5573 mpt->m_reply_frame_size;
5574 args = &mpt->m_replyh_args[reply_frame_no];
5575 args->mpt = (void *)mpt;
5576 args->rfm = reply_addr;
5577
5578 /*
5579 * Record the event if its type is enabled in
5580 * this mpt instance by ioctl.
5581 */
5582 mptsas_record_event(args);
5583
5584 /*
5585 * Handle time critical events
5586 * NOT_RESPONDING/ADDED only now
5587 */
5588 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
5589 /*
5590 * Would not return main process,
5591 * just let taskq resolve ack action
5592 * and ack would be sent in taskq thread
5593 */
5594 NDBG20(("send mptsas_handle_event_sync success"));
5595 }
5596
5597 if (mpt->m_in_reset) {
5598 NDBG20(("dropping event received during reset"));
5599 return;
5600 }
5601
5602 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
5603 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
5604 mptsas_log(mpt, CE_WARN, "No memory available"
5605 "for dispatch taskq");
5606 /*
5607 * Return the reply frame to the free queue.
5608 */
5609 ddi_put32(mpt->m_acc_free_queue_hdl,
5610 &((uint32_t *)(void *)
5611 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
5612 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5613 DDI_DMA_SYNC_FORDEV);
5614 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5615 mpt->m_free_index = 0;
5616 }
5617
5618 ddi_put32(mpt->m_datap,
5619 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
5620 }
5621 return;
5622 case MPI2_FUNCTION_DIAG_BUFFER_POST:
5623 /*
5624 * If SMID is 0, this implies that the reply is due to a
5625 * release function with a status that the buffer has been
5626 * released. Set the buffer flags accordingly.
5627 */
5628 if (SMID == 0) {
5629 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
5630 &reply->IOCStatus);
5631 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
5632 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
5633 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
5634 pBuffer =
5635 &mpt->m_fw_diag_buffer_list[buffer_type];
5636 pBuffer->valid_data = TRUE;
5637 pBuffer->owned_by_firmware = FALSE;
5638 pBuffer->immediate = FALSE;
5639 }
5640 } else {
5641 /*
5642 * Normal handling of diag post reply with SMID.
5643 */
5644 cmd = slots->m_slot[SMID];
5645
5646 /*
5647 * print warning and return if the slot is empty
5648 */
5649 if (cmd == NULL) {
5650 mptsas_log(mpt, CE_WARN, "?NULL command for "
5651 "address reply in slot %d", SMID);
5652 return;
5653 }
5654 cmd->cmd_rfm = reply_addr;
5655 cmd->cmd_flags |= CFLAG_FINISHED;
5656 cv_broadcast(&mpt->m_fw_diag_cv);
5657 }
5658 return;
5659 default:
5660 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
5661 break;
5662 }
5663
5664 /*
5665 * Return the reply frame to the free queue.
5666 */
5667 ddi_put32(mpt->m_acc_free_queue_hdl,
5668 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
5669 reply_addr);
5670 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5671 DDI_DMA_SYNC_FORDEV);
5672 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5673 mpt->m_free_index = 0;
5674 }
5675 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
5676 mpt->m_free_index);
5677
5678 if (cmd->cmd_flags & CFLAG_FW_CMD)
5679 return;
5680
5681 if (cmd->cmd_flags & CFLAG_RETRY) {
5682 /*
5683 * The target returned QFULL or busy, do not add this
5684 * pkt to the doneq since the hba will retry
5685 * this cmd.
5686 *
5687 * The pkt has already been resubmitted in
5688 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5689 * Remove this cmd_flag here.
5690 */
5691 cmd->cmd_flags &= ~CFLAG_RETRY;
5692 } else {
5693 mptsas_doneq_add(mpt, cmd);
5694 }
5695 }
5696
5697 #ifdef MPTSAS_DEBUG
5698 static uint8_t mptsas_last_sense[256];
5699 #endif
5700
5701 static void
5702 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
5703 mptsas_cmd_t *cmd)
5704 {
5705 uint8_t scsi_status, scsi_state;
5706 uint16_t ioc_status, cmd_rqs_len;
5707 uint32_t xferred, sensecount, responsedata, loginfo = 0;
5708 struct scsi_pkt *pkt;
5709 struct scsi_arq_status *arqstat;
5710 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5711 uint8_t *sensedata = NULL;
5712 uint64_t sas_wwn;
5713 uint8_t phy;
5714 char wwn_str[MPTSAS_WWN_STRLEN];
5715
5716 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
5717 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5718 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
5719 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
5720 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
5721 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
5722 &reply->ResponseInfo);
5723
5724 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
5725 sas_wwn = ptgt->m_addr.mta_wwn;
5726 phy = ptgt->m_phynum;
5727 if (sas_wwn == 0) {
5728 (void) sprintf(wwn_str, "p%x", phy);
5729 } else {
5730 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
5731 }
5732 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
5733 &reply->IOCLogInfo);
5734 mptsas_log(mpt, CE_NOTE,
5735 "?Log info 0x%x received for target %d %s.\n"
5736 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5737 loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status,
5738 scsi_state);
5739 }
5740
5741 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5742 scsi_status, ioc_status, scsi_state));
5743
5744 pkt = CMD2PKT(cmd);
5745 *(pkt->pkt_scbp) = scsi_status;
5746
5747 if (loginfo == 0x31170000) {
5748 /*
5749 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
5750 * 0x31170000 comes, that means the device missing delay
5751 * is in progressing, the command need retry later.
5752 */
5753 *(pkt->pkt_scbp) = STATUS_BUSY;
5754 return;
5755 }
5756
5757 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
5758 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
5759 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
5760 pkt->pkt_reason = CMD_INCOMPLETE;
5761 pkt->pkt_state |= STATE_GOT_BUS;
5762 mutex_enter(&ptgt->m_t_mutex);
5763 if (ptgt->m_reset_delay == 0) {
5764 mptsas_set_throttle(mpt, ptgt,
5765 DRAIN_THROTTLE);
5766 }
5767 mutex_exit(&ptgt->m_t_mutex);
5768 return;
5769 }
5770
5771 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
5772 responsedata &= 0x000000FF;
5773 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5774 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5775 pkt->pkt_reason = CMD_TLR_OFF;
5776 return;
5777 }
5778 }
5779
5780
5781 switch (scsi_status) {
5782 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5783 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
5784 DDI_DMA_SYNC_FORCPU);
5785 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5786 arqstat = (void*)(pkt->pkt_scbp);
5787 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5788 (pkt->pkt_scbp));
5789 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5790 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5791 if (cmd->cmd_flags & CFLAG_XARQ) {
5792 pkt->pkt_state |= STATE_XARQ_DONE;
5793 }
5794 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5795 pkt->pkt_state |= STATE_XFERRED_DATA;
5796 }
5797 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5798 arqstat->sts_rqpkt_state = pkt->pkt_state;
5799 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5800 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5801 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5802 #ifdef MPTSAS_DEBUG
5803 bcopy((uchar_t *)cmd->cmd_arq_buf, mptsas_last_sense,
5804 cmd->cmd_rqslen);
5805 #endif
5806 if (cmd->cmd_extrqslen != 0) {
5807 cmd_rqs_len = cmd->cmd_extrqslen;
5808 } else {
5809 cmd_rqs_len = cmd->cmd_rqslen;
5810 }
5811 bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata,
5812 ((cmd->cmd_rqslen >= sensecount) ? sensecount :
5813 cmd_rqs_len));
5814 arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount);
5815 cmd->cmd_flags |= CFLAG_CMDARQ;
5816 /*
5817 * Set proper status for pkt if autosense was valid
5818 */
5819 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5820 struct scsi_status zero_status = { 0 };
5821 arqstat->sts_rqpkt_status = zero_status;
5822 }
5823
5824 /*
5825 * ASC=0x47 is parity error
5826 * ASC=0x48 is initiator detected error received
5827 */
5828 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5829 ((scsi_sense_asc(sensedata) == 0x47) ||
5830 (scsi_sense_asc(sensedata) == 0x48))) {
5831 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5832 }
5833
5834 /*
5835 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5836 * ASC/ASCQ=0x25/0x00 means invalid lun
5837 */
5838 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5839 (scsi_sense_asc(sensedata) == 0x3F) &&
5840 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5841 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5842 (scsi_sense_asc(sensedata) == 0x25) &&
5843 (scsi_sense_ascq(sensedata) == 0x00))) {
5844 mptsas_topo_change_list_t *topo_node = NULL;
5845
5846 topo_node = kmem_zalloc(
5847 sizeof (mptsas_topo_change_list_t),
5848 KM_NOSLEEP);
5849 if (topo_node == NULL) {
5850 mptsas_log(mpt, CE_NOTE, "No memory"
5851 "resource for handle SAS dynamic"
5852 "reconfigure.\n");
5853 break;
5854 }
5855 topo_node->mpt = mpt;
5856 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5857 topo_node->un.phymask = ptgt->m_addr.mta_phymask;
5858 topo_node->devhdl = ptgt->m_devhdl;
5859 topo_node->object = (void *)ptgt;
5860 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5861
5862 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5863 mptsas_handle_dr,
5864 (void *)topo_node,
5865 DDI_NOSLEEP)) != DDI_SUCCESS) {
5866 kmem_free(topo_node,
5867 sizeof (mptsas_topo_change_list_t));
5868 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5869 "for handle SAS dynamic reconfigure"
5870 "failed. \n");
5871 }
5872 }
5873 break;
5874 case MPI2_SCSI_STATUS_GOOD:
5875 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5876 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5877 pkt->pkt_reason = CMD_DEV_GONE;
5878 pkt->pkt_state |= STATE_GOT_BUS;
5879 mutex_enter(&ptgt->m_t_mutex);
5880 if (ptgt->m_reset_delay == 0) {
5881 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5882 }
5883 mutex_exit(&ptgt->m_t_mutex);
5884 NDBG31(("lost disk for target%d, command:%x",
5885 Tgt(cmd), pkt->pkt_cdbp[0]));
5886 break;
5887 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5888 NDBG31(("data overrun: xferred=%d", xferred));
5889 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5890 pkt->pkt_reason = CMD_DATA_OVR;
5891 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5892 | STATE_SENT_CMD | STATE_GOT_STATUS
5893 | STATE_XFERRED_DATA);
5894 pkt->pkt_resid = 0;
5895 break;
5896 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5897 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5898 NDBG31(("data underrun: xferred=%d", xferred));
5899 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5900 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5901 | STATE_SENT_CMD | STATE_GOT_STATUS);
5902 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5903 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5904 pkt->pkt_state |= STATE_XFERRED_DATA;
5905 }
5906 break;
5907 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5908 if (cmd->cmd_active_expiration <= gethrtime()) {
5909 /*
5910 * When timeout requested, propagate
5911 * proper reason and statistics to
5912 * target drivers.
5913 */
5914 mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT,
5915 STAT_BUS_RESET | STAT_TIMEOUT);
5916 } else {
5917 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
5918 STAT_BUS_RESET);
5919 }
5920 break;
5921 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5922 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5923 mptsas_set_pkt_reason(mpt,
5924 cmd, CMD_RESET, STAT_DEV_RESET);
5925 break;
5926 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5927 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5928 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5929 mptsas_set_pkt_reason(mpt,
5930 cmd, CMD_TERMINATED, STAT_TERMINATED);
5931 break;
5932 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5933 case MPI2_IOCSTATUS_BUSY:
5934 /*
5935 * set throttles to drain
5936 */
5937 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
5938 ptgt = refhash_next(mpt->m_targets, ptgt)) {
5939 mptsas_set_throttle_mtx(mpt, ptgt,
5940 DRAIN_THROTTLE);
5941 }
5942
5943 /*
5944 * retry command
5945 */
5946 mptsas_retry_pkt(mpt, cmd);
5947 break;
5948 default:
5949 mptsas_log(mpt, CE_WARN,
5950 "unknown ioc_status = %x\n", ioc_status);
5951 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5952 "count = %x, scsi_status = %x", scsi_state,
5953 xferred, scsi_status);
5954 break;
5955 }
5956 break;
5957 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5958 mptsas_handle_qfull(mpt, cmd);
5959 break;
5960 case MPI2_SCSI_STATUS_BUSY:
5961 NDBG31(("scsi_status busy received"));
5962 break;
5963 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5964 NDBG31(("scsi_status reservation conflict received"));
5965 break;
5966 default:
5967 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5968 scsi_status, ioc_status);
5969 mptsas_log(mpt, CE_WARN,
5970 "mptsas_process_intr: invalid scsi status\n");
5971 break;
5972 }
5973 }
5974
5975 static void
5976 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5977 mptsas_cmd_t *cmd)
5978 {
5979 uint8_t task_type;
5980 uint16_t ioc_status;
5981 uint32_t log_info;
5982 uint16_t dev_handle;
5983 struct scsi_pkt *pkt = CMD2PKT(cmd);
5984
5985 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5986 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5987 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5988 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5989
5990 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5991 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5992 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5993 task_type, ioc_status, log_info, dev_handle);
5994 pkt->pkt_reason = CMD_INCOMPLETE;
5995 return;
5996 }
5997
5998 switch (task_type) {
5999 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
6000 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
6001 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
6002 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
6003 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
6004 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
6005 break;
6006 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
6007 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
6008 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
6009 /*
6010 * Check for invalid DevHandle of 0 in case application
6011 * sends bad command. DevHandle of 0 could cause problems.
6012 */
6013 if (dev_handle == 0) {
6014 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
6015 " DevHandle of 0.");
6016 } else {
6017 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
6018 task_type);
6019 }
6020 break;
6021 default:
6022 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
6023 task_type);
6024 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
6025 break;
6026 }
6027 }
6028
6029 static void
6030 mptsas_doneq_thread(mptsas_thread_arg_t *arg)
6031 {
6032 mptsas_t *mpt = arg->mpt;
6033 uint32_t t = arg->t;
6034 mptsas_cmd_t *cmd;
6035 struct scsi_pkt *pkt;
6036 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
6037
6038 mutex_enter(&item->mutex);
6039 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
6040 if (!item->dlist.dl_q) {
6041 cv_wait(&item->cv, &item->mutex);
6042 }
6043 pkt = NULL;
6044 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
6045 cmd->cmd_flags |= CFLAG_COMPLETED;
6046 pkt = CMD2PKT(cmd);
6047 }
6048 mutex_exit(&item->mutex);
6049 if (pkt) {
6050 mptsas_pkt_comp(pkt, cmd);
6051 }
6052 mutex_enter(&item->mutex);
6053 }
6054 mutex_exit(&item->mutex);
6055 mutex_enter(&mpt->m_qthread_mutex);
6056 mpt->m_doneq_thread_n--;
6057 cv_broadcast(&mpt->m_qthread_cv);
6058 mutex_exit(&mpt->m_qthread_mutex);
6059 }
6060
6061
6062 /*
6063 * mpt interrupt handler.
6064 */
6065 static uint_t
6066 mptsas_intr(caddr_t arg1, caddr_t arg2)
6067 {
6068 mptsas_t *mpt = (void *)arg1;
6069 mptsas_reply_pqueue_t *rpqp;
6070 int reply_q = (int)(uintptr_t)arg2;
6071 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
6072 int found = 0, i, rpqidx;
6073 size_t dma_sync_len;
6074 off_t dma_sync_offset;
6075 uint32_t istat;
6076
6077 NDBG18(("mptsas_intr: arg1 0x%p reply_q 0x%d", (void *)arg1, reply_q));
6078
6079 rpqp = &mpt->m_rep_post_queues[reply_q];
6080
6081 /*
6082 * If interrupts are shared by two channels then check whether this
6083 * interrupt is genuinely for this channel by making sure first the
6084 * chip is in high power state.
6085 */
6086 if ((mpt->m_options & MPTSAS_OPT_PM) &&
6087 (mpt->m_power_level != PM_LEVEL_D0)) {
6088 mpt->m_unclaimed_pm_interrupt_count++;
6089 return (DDI_INTR_UNCLAIMED);
6090 }
6091
6092 istat = MPTSAS_GET_ISTAT(mpt);
6093 if (!(istat & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)) {
6094 NDBG18(("Interrupt bit not set, istat 0x%x", istat));
6095 mpt->m_unclaimed_no_interrupt_count++;
6096 /*
6097 * Really need a good definition of when this is valid.
6098 * It appears not to be if you have multiple reply post
6099 * queues, there may be a better way - need LSI info.
6100 * For now just count them.
6101 */
6102 #if 0
6103 return (DDI_INTR_UNCLAIMED);
6104 #endif
6105 }
6106
6107 /*
6108 * If polling, interrupt was triggered by some shared interrupt because
6109 * IOC interrupts are disabled during polling, so polling routine will
6110 * handle any replies. Considering this, if polling is happening,
6111 * return with interrupt unclaimed.
6112 */
6113 if (mpt->m_polled_intr) {
6114 mptsas_log(mpt, CE_WARN,
6115 "Unclaimed interrupt, rpq %d (Polling), istat 0x%x",
6116 reply_q, istat);
6117 mpt->m_unclaimed_polled_interrupt_count++;
6118 return (DDI_INTR_UNCLAIMED);
6119 }
6120
6121 /*
6122 * At the moment this is the only place the mutex is grabbed.
6123 * So it should never fail!
6124 */
6125 if (mutex_tryenter(&rpqp->rpq_mutex) == 0) {
6126 mutex_enter(&rpqp->rpq_mutex);
6127 rpqp->rpq_intr_mutexbusy++;
6128 }
6129
6130 dma_sync_len = mpt->m_post_queue_depth * 8;
6131 dma_sync_offset = dma_sync_len * reply_q;
6132 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl,
6133 dma_sync_offset, dma_sync_len, DDI_DMA_SYNC_FORCPU);
6134
6135 /*
6136 * Go around the reply queue and process each descriptor until
6137 * we get to the next unused one.
6138 * It seems to be an occupational hazard that we get interrupts
6139 * with nothing to do. These are counted below.
6140 */
6141 rpqidx = rpqp->rpq_index;
6142 #ifndef __lock_lint
6143 _NOTE(CONSTCOND)
6144 #endif
6145 while (TRUE) {
6146 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
6147 MPTSAS_GET_NEXT_REPLY(rpqp, rpqidx);
6148
6149 if (ddi_get32(mpt->m_acc_post_queue_hdl,
6150 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
6151 ddi_get32(mpt->m_acc_post_queue_hdl,
6152 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
6153 break;
6154 }
6155
6156 found++;
6157
6158 ASSERT(ddi_get8(mpt->m_acc_post_queue_hdl,
6159 &reply_desc_union->Default.MSIxIndex) == reply_q);
6160
6161 /*
6162 * Process it according to its type.
6163 */
6164 mptsas_process_intr(mpt, rpqp, reply_desc_union);
6165
6166 /*
6167 * Clear the reply descriptor for re-use.
6168 */
6169 ddi_put64(mpt->m_acc_post_queue_hdl,
6170 &((uint64_t *)(void *)rpqp->rpq_queue)[rpqidx],
6171 0xFFFFFFFFFFFFFFFF);
6172
6173 /*
6174 * Increment post index and roll over if needed.
6175 */
6176 if (++rpqidx == mpt->m_post_queue_depth) {
6177 rpqidx = 0;
6178 }
6179 }
6180
6181 if (found == 0) {
6182 rpqp->rpq_intr_unclaimed++;
6183 mutex_exit(&rpqp->rpq_mutex);
6184 mpt->m_unclaimed_nocmd_interrupt_count++;
6185 return (DDI_INTR_UNCLAIMED);
6186 }
6187 rpqp->rpq_index = rpqidx;
6188
6189 rpqp->rpq_intr_count++;
6190 NDBG18(("mptsas_intr complete(%d), did %d loops", reply_q, found));
6191
6192 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl,
6193 dma_sync_offset, dma_sync_len, DDI_DMA_SYNC_FORDEV);
6194
6195 mpt->m_interrupt_count++;
6196
6197 /*
6198 * Update the reply index if at least one reply was processed.
6199 * For more than 8 reply queues on SAS3 controllers we have to do
6200 * things a little different. See Chapter 20 in the MPI 2.5 spec.
6201 */
6202 if (mpt->m_post_reply_qcount > 8) {
6203 /*
6204 * The offsets from the base are multiples of 0x10.
6205 * We are indexing into 32 bit quantities so calculate
6206 * the index for that.
6207 */
6208 i = (reply_q&~0x7) >> 1;
6209 ddi_put32(mpt->m_datap,
6210 &mpt->m_reg->SuppReplyPostHostIndex[i],
6211 rpqp->rpq_index |
6212 ((reply_q&0x7)<<MPI2_RPHI_MSIX_INDEX_SHIFT));
6213 (void) ddi_get32(mpt->m_datap,
6214 &mpt->m_reg->SuppReplyPostHostIndex[i]);
6215 } else {
6216 ddi_put32(mpt->m_datap,
6217 &mpt->m_reg->ReplyPostHostIndex,
6218 rpqp->rpq_index | (reply_q<<MPI2_RPHI_MSIX_INDEX_SHIFT));
6219 (void) ddi_get32(mpt->m_datap,
6220 &mpt->m_reg->ReplyPostHostIndex);
6221 }
6222
6223 /*
6224 * If no helper threads are created, process the doneq in ISR. If
6225 * helpers are created, use the doneq length as a metric to measure the
6226 * load on the interrupt CPU. If it is long enough, which indicates the
6227 * load is heavy, then we deliver the IO completions to the helpers.
6228 * This measurement has some limitations, although it is simple and
6229 * straightforward and works well for most of the cases at present.
6230 * To always use the threads set mptsas_doneq_length_threshold_prop
6231 * to zero in the mpt_sas3.conf file.
6232 *
6233 * Check the current reply queue done queue.
6234 */
6235 if (rpqp->rpq_dlist.dl_len) {
6236 if (!mpt->m_doneq_thread_n ||
6237 (rpqp->rpq_dlist.dl_len <= mpt->m_doneq_length_threshold)) {
6238 mptsas_rpdoneq_empty(rpqp);
6239 } else {
6240 mptsas_deliver_doneq_thread(mpt, &rpqp->rpq_dlist);
6241 }
6242 }
6243
6244 mutex_exit(&rpqp->rpq_mutex);
6245
6246 /*
6247 * Check the main done queue. If we find something
6248 * grab the mutex and check again before processing.
6249 */
6250 if (mpt->m_dlist.dl_len) {
6251 mutex_enter(&mpt->m_mutex);
6252 if (mpt->m_dlist.dl_len) {
6253 if (!mpt->m_doneq_thread_n ||
6254 (mpt->m_dlist.dl_len <=
6255 mpt->m_doneq_length_threshold)) {
6256 mptsas_doneq_empty(mpt);
6257 } else {
6258 mptsas_deliver_doneq_thread(mpt, &mpt->m_dlist);
6259 }
6260 }
6261 mutex_exit(&mpt->m_mutex);
6262 }
6263
6264 /*
6265 * If there are queued cmd, start them now.
6266 */
6267 if (mpt->m_waitq != NULL) {
6268 mutex_enter(&mpt->m_mutex);
6269 if (mpt->m_waitq != NULL && mpt->m_polled_intr == 0) {
6270 mptsas_restart_waitq(mpt);
6271 }
6272 mutex_exit(&mpt->m_mutex);
6273 }
6274 return (DDI_INTR_CLAIMED);
6275 }
6276
6277 static void
6278 mptsas_process_intr(mptsas_t *mpt, mptsas_reply_pqueue_t *rpqp,
6279 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
6280 {
6281 uint8_t reply_type;
6282
6283 /*
6284 * Should get here with the reply queue mutex held, but not
6285 * the main mpt mutex. Want to avoid grabbing that during
6286 * normal operations if possible.
6287 */
6288 ASSERT(mutex_owned(&rpqp->rpq_mutex));
6289
6290 /*
6291 * The reply is valid, process it according to its
6292 * type. Also, set a flag for updated the reply index
6293 * after they've all been processed.
6294 */
6295 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
6296 &reply_desc_union->Default.ReplyFlags);
6297 NDBG18(("mptsas_process_intr(rpq %d) reply_type 0x%x", rpqp->rpq_num,
6298 reply_type));
6299 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
6300 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
6301 reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) {
6302 mptsas_handle_scsi_io_success(mpt, rpqp, reply_desc_union);
6303 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
6304 mutex_enter(&mpt->m_mutex);
6305 mptsas_handle_address_reply(mpt, reply_desc_union);
6306 mutex_exit(&mpt->m_mutex);
6307 } else {
6308 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
6309 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
6310 }
6311 }
6312
6313 /*
6314 * handle qfull condition
6315 */
6316 static void
6317 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
6318 {
6319 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
6320
6321 mutex_enter(&ptgt->m_t_mutex);
6322 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
6323 (ptgt->m_qfull_retries == 0)) {
6324 /*
6325 * We have exhausted the retries on QFULL, or,
6326 * the target driver has indicated that it
6327 * wants to handle QFULL itself by setting
6328 * qfull-retries capability to 0. In either case
6329 * we want the target driver's QFULL handling
6330 * to kick in. We do this by having pkt_reason
6331 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
6332 */
6333 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
6334 } else {
6335 if (ptgt->m_reset_delay == 0) {
6336 ptgt->m_t_throttle =
6337 max((ptgt->m_t_ncmds - 2), 0);
6338 }
6339 mutex_exit(&ptgt->m_t_mutex);
6340
6341 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
6342
6343 mptsas_retry_pkt(mpt, cmd);
6344
6345 mutex_enter(&ptgt->m_t_mutex);
6346 /*
6347 * when target gives queue full status with no commands
6348 * outstanding (m_t_ncmds == 0), throttle is set to 0
6349 * (HOLD_THROTTLE), and the queue full handling start
6350 * (see psarc/1994/313); if there are commands outstanding,
6351 * throttle is set to (m_t_ncmds - 2)
6352 */
6353 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
6354 /*
6355 * By setting throttle to QFULL_THROTTLE, we
6356 * avoid submitting new commands and in
6357 * mptsas_restart_cmd find out slots which need
6358 * their throttles to be cleared.
6359 */
6360 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
6361 if (mpt->m_restart_cmd_timeid == 0) {
6362 mpt->m_restart_cmd_timeid =
6363 timeout(mptsas_restart_cmd, mpt,
6364 ptgt->m_qfull_retry_interval);
6365 }
6366 }
6367 }
6368 mutex_exit(&ptgt->m_t_mutex);
6369 }
6370
6371 mptsas_phymask_t
6372 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
6373 {
6374 mptsas_phymask_t phy_mask = 0;
6375 uint8_t i = 0;
6376
6377 NDBG20(("mptsas3%d physport_to_phymask enter", mpt->m_instance));
6378
6379 ASSERT(mutex_owned(&mpt->m_mutex));
6380
6381 /*
6382 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
6383 */
6384 if (physport == 0xFF) {
6385 return (0);
6386 }
6387
6388 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
6389 if (mpt->m_phy_info[i].attached_devhdl &&
6390 (mpt->m_phy_info[i].phy_mask != 0) &&
6391 (mpt->m_phy_info[i].port_num == physport)) {
6392 phy_mask = mpt->m_phy_info[i].phy_mask;
6393 break;
6394 }
6395 }
6396 NDBG20(("mptsas3%d physport_to_phymask:physport :%x phymask :%x, ",
6397 mpt->m_instance, physport, phy_mask));
6398 return (phy_mask);
6399 }
6400
6401 /*
6402 * mpt free device handle after device gone, by use of passthrough
6403 */
6404 static int
6405 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
6406 {
6407 Mpi2SasIoUnitControlRequest_t req;
6408 Mpi2SasIoUnitControlReply_t rep;
6409 int ret;
6410
6411 ASSERT(mutex_owned(&mpt->m_mutex));
6412
6413 /*
6414 * Need to compose a SAS IO Unit Control request message
6415 * and call mptsas_do_passthru() function
6416 */
6417 bzero(&req, sizeof (req));
6418 bzero(&rep, sizeof (rep));
6419
6420 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
6421 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
6422 req.DevHandle = LE_16(devhdl);
6423
6424 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
6425 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
6426 if (ret != 0) {
6427 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6428 "Control error %d", ret);
6429 return (DDI_FAILURE);
6430 }
6431
6432 /* do passthrough success, check the ioc status */
6433 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
6434 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6435 "Control IOCStatus %d", LE_16(rep.IOCStatus));
6436 return (DDI_FAILURE);
6437 }
6438
6439 return (DDI_SUCCESS);
6440 }
6441
6442 static void
6443 mptsas_update_phymask(mptsas_t *mpt)
6444 {
6445 mptsas_phymask_t mask = 0, phy_mask;
6446 char *phy_mask_name;
6447 uint8_t current_port;
6448 int i, j;
6449
6450 NDBG20(("mptsas3%d update phymask ", mpt->m_instance));
6451
6452 ASSERT(mutex_owned(&mpt->m_mutex));
6453
6454 (void) mptsas_get_sas_io_unit_page(mpt);
6455
6456 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6457
6458 for (i = 0; i < mpt->m_num_phys; i++) {
6459 phy_mask = 0x00;
6460
6461 if (mpt->m_phy_info[i].attached_devhdl == 0)
6462 continue;
6463
6464 bzero(phy_mask_name, sizeof (phy_mask_name));
6465
6466 current_port = mpt->m_phy_info[i].port_num;
6467
6468 if ((mask & (1 << i)) != 0)
6469 continue;
6470
6471 for (j = 0; j < mpt->m_num_phys; j++) {
6472 if (mpt->m_phy_info[j].attached_devhdl &&
6473 (mpt->m_phy_info[j].port_num == current_port)) {
6474 phy_mask |= (1 << j);
6475 }
6476 }
6477 mask = mask | phy_mask;
6478
6479 for (j = 0; j < mpt->m_num_phys; j++) {
6480 if ((phy_mask >> j) & 0x01) {
6481 mpt->m_phy_info[j].phy_mask = phy_mask;
6482 }
6483 }
6484
6485 (void) sprintf(phy_mask_name, "%x", phy_mask);
6486
6487 mutex_exit(&mpt->m_mutex);
6488 /*
6489 * register a iport, if the port has already been existed
6490 * SCSA will do nothing and just return.
6491 */
6492 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
6493 mutex_enter(&mpt->m_mutex);
6494 }
6495 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6496 NDBG20(("mptsas3%d update phymask return", mpt->m_instance));
6497 }
6498
6499 /*
6500 * mptsas_handle_dr is a task handler for DR, the DR action includes:
6501 * 1. Directly attched Device Added/Removed.
6502 * 2. Expander Device Added/Removed.
6503 * 3. Indirectly Attached Device Added/Expander.
6504 * 4. LUNs of a existing device status change.
6505 * 5. RAID volume created/deleted.
6506 * 6. Member of RAID volume is released because of RAID deletion.
6507 * 7. Physical disks are removed because of RAID creation.
6508 */
6509 static void
6510 mptsas_handle_dr(void *args) {
6511 mptsas_topo_change_list_t *topo_node = NULL;
6512 mptsas_topo_change_list_t *save_node = NULL;
6513 mptsas_t *mpt;
6514 dev_info_t *parent = NULL;
6515 mptsas_phymask_t phymask = 0;
6516 char phy_mask_name[MPTSAS_MAX_PHYS];
6517 uint8_t flags = 0, physport = 0xff;
6518 uint8_t port_update = 0;
6519 uint_t event;
6520
6521 topo_node = (mptsas_topo_change_list_t *)args;
6522
6523 mpt = topo_node->mpt;
6524 event = topo_node->event;
6525 flags = topo_node->flags;
6526
6527 NDBG20(("mptsas3%d handle_dr enter", mpt->m_instance));
6528
6529 switch (event) {
6530 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6531 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6532 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
6533 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6534 /*
6535 * Direct attached or expander attached device added
6536 * into system or a Phys Disk that is being unhidden.
6537 */
6538 port_update = 1;
6539 }
6540 break;
6541 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6542 /*
6543 * New expander added into system, it must be the head
6544 * of topo_change_list_t
6545 */
6546 port_update = 1;
6547 break;
6548 default:
6549 port_update = 0;
6550 break;
6551 }
6552 /*
6553 * All cases port_update == 1 may cause initiator port form change
6554 */
6555 mutex_enter(&mpt->m_mutex);
6556 if (mpt->m_port_chng && port_update) {
6557 /*
6558 * mpt->m_port_chng flag indicates some PHYs of initiator
6559 * port have changed to online. So when expander added or
6560 * directly attached device online event come, we force to
6561 * update port information by issueing SAS IO Unit Page and
6562 * update PHYMASKs.
6563 */
6564 (void) mptsas_update_phymask(mpt);
6565 mpt->m_port_chng = 0;
6566
6567 }
6568 mutex_exit(&mpt->m_mutex);
6569
6570 while (topo_node) {
6571 phymask = 0;
6572 flags = topo_node->flags;
6573 event = topo_node->event;
6574 if (event == MPTSAS_DR_EVENT_REMOVE_HANDLE) {
6575 goto handle_topo_change;
6576 }
6577 if ((event == MPTSAS_DR_EVENT_RECONFIG_TARGET) &&
6578 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6579 /*
6580 * There is no any field in IR_CONFIG_CHANGE
6581 * event indicate physport/phynum, let's get
6582 * parent after SAS Device Page0 request.
6583 */
6584 goto handle_topo_change;
6585 }
6586
6587 if (parent == NULL) {
6588 physport = topo_node->un.physport;
6589 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
6590 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
6591 /*
6592 * For all offline events, phymask is known
6593 */
6594 phymask = topo_node->un.phymask;
6595 goto find_parent;
6596 }
6597 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
6598 phymask = topo_node->un.phymask;
6599 goto find_parent;
6600 }
6601
6602 mutex_enter(&mpt->m_mutex);
6603 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6604 /*
6605 * If the direct attached device added or a
6606 * phys disk is being unhidden, argument
6607 * physport actually is PHY#, so we have to get
6608 * phymask according PHY#.
6609 */
6610 physport = mpt->m_phy_info[physport].port_num;
6611 }
6612
6613 /*
6614 * Translate physport to phymask so that we can search
6615 * parent dip.
6616 */
6617 phymask = mptsas_physport_to_phymask(mpt, physport);
6618 mutex_exit(&mpt->m_mutex);
6619
6620 find_parent:
6621 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
6622 /*
6623 * For RAID topology change node, write the iport name
6624 * as v0.
6625 */
6626 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6627 (void) sprintf(phy_mask_name, "v0");
6628 } else {
6629 /*
6630 * phymask can be 0 if the drive has been
6631 * pulled by the time an add event is
6632 * processed. If phymask is 0, just skip this
6633 * event and continue.
6634 */
6635 if (phymask == 0) {
6636 save_node = topo_node;
6637 topo_node = topo_node->next;
6638 ASSERT(save_node);
6639 kmem_free(save_node,
6640 sizeof (mptsas_topo_change_list_t));
6641 parent = NULL;
6642 continue;
6643 }
6644 (void) sprintf(phy_mask_name, "%x", phymask);
6645 }
6646 parent = scsi_hba_iport_find(mpt->m_dip,
6647 phy_mask_name);
6648 if (parent == NULL) {
6649 mptsas_log(mpt, CE_WARN, "Failed to find an "
6650 "iport for \"%s\", should not happen!",
6651 phy_mask_name);
6652 save_node = topo_node;
6653 topo_node = topo_node->next;
6654 ASSERT(save_node);
6655 kmem_free(save_node,
6656 sizeof (mptsas_topo_change_list_t));
6657 continue;
6658 }
6659
6660 }
6661 ASSERT(parent);
6662 handle_topo_change:
6663
6664 mutex_enter(&mpt->m_mutex);
6665 /*
6666 * If HBA is being reset, don't perform operations depending
6667 * on the IOC. We must free the topo list, however.
6668 */
6669 if (!mpt->m_in_reset)
6670 mptsas_handle_topo_change(topo_node, parent);
6671 else
6672 NDBG20(("skipping topo change received during reset"));
6673 mutex_exit(&mpt->m_mutex);
6674 save_node = topo_node;
6675 topo_node = topo_node->next;
6676 ASSERT(save_node);
6677 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
6678
6679 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6680 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
6681 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
6682 /*
6683 * If direct attached device associated, make sure
6684 * reset the parent before start the next one. But
6685 * all devices associated with expander shares the
6686 * parent. Also, reset parent if this is for RAID.
6687 */
6688 parent = NULL;
6689 }
6690 }
6691 }
6692
6693 static void
6694 mptsas_offline_target(mptsas_t *mpt, mptsas_target_t *ptgt,
6695 uint8_t topo_flags, dev_info_t *parent)
6696 {
6697 uint64_t sas_wwn = 0;
6698 uint8_t phy;
6699 char wwn_str[MPTSAS_WWN_STRLEN];
6700 uint16_t devhdl;
6701 int circ = 0, circ1 = 0;
6702 int rval = 0;
6703
6704 sas_wwn = ptgt->m_addr.mta_wwn;
6705 phy = ptgt->m_phynum;
6706 devhdl = ptgt->m_devhdl;
6707
6708 if (sas_wwn) {
6709 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
6710 } else {
6711 (void) sprintf(wwn_str, "p%x", phy);
6712 }
6713
6714 /*
6715 * Abort all outstanding command on the device
6716 */
6717 rval = mptsas_do_scsi_reset(mpt, devhdl);
6718 if (rval) {
6719 NDBG20(("mptsas3%d: mptsas_offline_target: reset target "
6720 "before offline devhdl:%x, phymask:%x, rval:%x",
6721 mpt->m_instance, ptgt->m_devhdl,
6722 ptgt->m_addr.mta_phymask, rval));
6723 }
6724
6725 mutex_exit(&mpt->m_mutex);
6726
6727 ndi_devi_enter(scsi_vhci_dip, &circ);
6728 ndi_devi_enter(parent, &circ1);
6729 rval = mptsas_offline_targetdev(parent, wwn_str);
6730 ndi_devi_exit(parent, circ1);
6731 ndi_devi_exit(scsi_vhci_dip, circ);
6732 NDBG20(("mptsas3%d: mptsas_offline_target %s devhdl:%x, "
6733 "phymask:%x, rval:%x", mpt->m_instance, wwn_str,
6734 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval));
6735
6736 /*
6737 * Clear parent's props for SMHBA support
6738 */
6739 if (topo_flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6740 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6741 SCSI_ADDR_PROP_ATTACHED_PORT, "") !=
6742 DDI_PROP_SUCCESS) {
6743 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6744 SCSI_ADDR_PROP_ATTACHED_PORT);
6745 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6746 "prop update failed");
6747 }
6748 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6749 MPTSAS_NUM_PHYS, 0) != DDI_PROP_SUCCESS) {
6750 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6751 MPTSAS_NUM_PHYS);
6752 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6753 "prop update failed");
6754 }
6755 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6756 MPTSAS_VIRTUAL_PORT, 1) != DDI_PROP_SUCCESS) {
6757 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6758 MPTSAS_VIRTUAL_PORT);
6759 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6760 "prop update failed");
6761 }
6762 }
6763
6764 mutex_enter(&mpt->m_mutex);
6765 ptgt->m_led_status = 0;
6766 (void) mptsas_flush_led_status(mpt, ptgt);
6767 if (rval == DDI_SUCCESS) {
6768 mutex_destroy(&ptgt->m_t_mutex);
6769 refhash_remove(mpt->m_targets, ptgt);
6770 ptgt = NULL;
6771 } else {
6772 /*
6773 * clean DR_INTRANSITION flag to allow I/O down to
6774 * PHCI driver since failover finished.
6775 * Invalidate the devhdl
6776 */
6777 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6778 ptgt->m_tgt_unconfigured = 0;
6779 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6780 }
6781 }
6782
6783 static void
6784 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
6785 dev_info_t *parent)
6786 {
6787 mptsas_target_t *ptgt = NULL;
6788 mptsas_smp_t *psmp = NULL;
6789 mptsas_t *mpt = (void *)topo_node->mpt;
6790 uint16_t devhdl;
6791 uint16_t attached_devhdl;
6792 int rval = 0;
6793 uint32_t page_address;
6794 uint8_t flags;
6795 dev_info_t *lundip;
6796 int circ = 0, circ1 = 0;
6797 char attached_wwnstr[MPTSAS_WWN_STRLEN];
6798
6799 NDBG20(("mptsas3%d handle_topo_change enter, devhdl 0x%x,"
6800 "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl,
6801 topo_node->event, topo_node->flags));
6802
6803 ASSERT(mutex_owned(&mpt->m_mutex));
6804
6805 switch (topo_node->event) {
6806 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6807 {
6808 char *phy_mask_name;
6809 mptsas_phymask_t phymask = 0;
6810
6811 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6812 /*
6813 * Get latest RAID info.
6814 */
6815 (void) mptsas_get_raid_info(mpt);
6816 ptgt = refhash_linear_search(mpt->m_targets,
6817 mptsas_target_eval_devhdl, &topo_node->devhdl);
6818 if (ptgt == NULL)
6819 break;
6820 } else {
6821 ptgt = (void *)topo_node->object;
6822 }
6823
6824 if (ptgt == NULL) {
6825 /*
6826 * If a Phys Disk was deleted, RAID info needs to be
6827 * updated to reflect the new topology.
6828 */
6829 (void) mptsas_get_raid_info(mpt);
6830
6831 /*
6832 * Get sas device page 0 by DevHandle to make sure if
6833 * SSP/SATA end device exist.
6834 */
6835 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6836 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
6837 topo_node->devhdl;
6838
6839 rval = mptsas_get_target_device_info(mpt, page_address,
6840 &devhdl, &ptgt);
6841 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
6842 mptsas_log(mpt, CE_NOTE,
6843 "mptsas_handle_topo_change: target %d is "
6844 "not a SAS/SATA device. \n",
6845 topo_node->devhdl);
6846 } else if (rval == DEV_INFO_FAIL_ALLOC) {
6847 mptsas_log(mpt, CE_NOTE,
6848 "mptsas_handle_topo_change: could not "
6849 "allocate memory. \n");
6850 }
6851 /*
6852 * If rval is DEV_INFO_PHYS_DISK than there is nothing
6853 * else to do, just leave.
6854 */
6855 if (rval != DEV_INFO_SUCCESS) {
6856 return;
6857 }
6858 }
6859
6860 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
6861
6862 mutex_exit(&mpt->m_mutex);
6863 flags = topo_node->flags;
6864
6865 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
6866 phymask = ptgt->m_addr.mta_phymask;
6867 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6868 (void) sprintf(phy_mask_name, "%x", phymask);
6869 parent = scsi_hba_iport_find(mpt->m_dip,
6870 phy_mask_name);
6871 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6872 if (parent == NULL) {
6873 mptsas_log(mpt, CE_WARN, "Failed to find a "
6874 "iport for PD, should not happen!");
6875 mutex_enter(&mpt->m_mutex);
6876 break;
6877 }
6878 }
6879
6880 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6881 ndi_devi_enter(parent, &circ1);
6882 (void) mptsas_config_raid(parent, topo_node->devhdl,
6883 &lundip);
6884 ndi_devi_exit(parent, circ1);
6885 } else {
6886 /*
6887 * hold nexus for bus configure
6888 */
6889 ndi_devi_enter(scsi_vhci_dip, &circ);
6890 ndi_devi_enter(parent, &circ1);
6891 rval = mptsas_config_target(parent, ptgt);
6892 /*
6893 * release nexus for bus configure
6894 */
6895 ndi_devi_exit(parent, circ1);
6896 ndi_devi_exit(scsi_vhci_dip, circ);
6897
6898 /*
6899 * Add parent's props for SMHBA support
6900 */
6901 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6902 bzero(attached_wwnstr,
6903 sizeof (attached_wwnstr));
6904 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
6905 ptgt->m_addr.mta_wwn);
6906 if (ddi_prop_update_string(DDI_DEV_T_NONE,
6907 parent,
6908 SCSI_ADDR_PROP_ATTACHED_PORT,
6909 attached_wwnstr)
6910 != DDI_PROP_SUCCESS) {
6911 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6912 parent,
6913 SCSI_ADDR_PROP_ATTACHED_PORT);
6914 mptsas_log(mpt, CE_WARN, "Failed to"
6915 "attached-port props");
6916 return;
6917 }
6918 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6919 MPTSAS_NUM_PHYS, 1) !=
6920 DDI_PROP_SUCCESS) {
6921 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6922 parent, MPTSAS_NUM_PHYS);
6923 mptsas_log(mpt, CE_WARN, "Failed to"
6924 " create num-phys props");
6925 return;
6926 }
6927
6928 /*
6929 * Update PHY info for smhba
6930 */
6931 mutex_enter(&mpt->m_mutex);
6932 if (mptsas_smhba_phy_init(mpt)) {
6933 mutex_exit(&mpt->m_mutex);
6934 mptsas_log(mpt, CE_WARN, "mptsas phy"
6935 " update failed");
6936 return;
6937 }
6938 mutex_exit(&mpt->m_mutex);
6939
6940 /*
6941 * topo_node->un.physport is really the PHY#
6942 * for direct attached devices
6943 */
6944 mptsas_smhba_set_one_phy_props(mpt, parent,
6945 topo_node->un.physport, &attached_devhdl);
6946
6947 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6948 MPTSAS_VIRTUAL_PORT, 0) !=
6949 DDI_PROP_SUCCESS) {
6950 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6951 parent, MPTSAS_VIRTUAL_PORT);
6952 mptsas_log(mpt, CE_WARN,
6953 "mptsas virtual-port"
6954 "port prop update failed");
6955 return;
6956 }
6957 }
6958 }
6959 mutex_enter(&mpt->m_mutex);
6960
6961 NDBG20(("mptsas3%d handle_topo_change to online devhdl:%x, "
6962 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
6963 ptgt->m_addr.mta_phymask));
6964 break;
6965 }
6966 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
6967 {
6968 devhdl = topo_node->devhdl;
6969 ptgt = refhash_linear_search(mpt->m_targets,
6970 mptsas_target_eval_devhdl, &devhdl);
6971 if (ptgt == NULL)
6972 break;
6973
6974 ASSERT(ptgt->m_devhdl == devhdl);
6975
6976 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6977 (topo_node->flags ==
6978 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6979 /*
6980 * Get latest RAID info if RAID volume status changes
6981 * or Phys Disk status changes
6982 */
6983 (void) mptsas_get_raid_info(mpt);
6984 }
6985
6986 mptsas_offline_target(mpt, ptgt, topo_node->flags, parent);
6987
6988 /*
6989 * Send SAS IO Unit Control to free the dev handle
6990 */
6991 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6992 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6993 rval = mptsas_free_devhdl(mpt, devhdl);
6994
6995 NDBG20(("mptsas3%d handle_topo_change to remove "
6996 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6997 rval));
6998 }
6999
7000 break;
7001 }
7002 case MPTSAS_DR_EVENT_REMOVE_HANDLE:
7003 {
7004 devhdl = topo_node->devhdl;
7005
7006 /*
7007 * Do a reset first.
7008 */
7009 rval = mptsas_do_scsi_reset(mpt, devhdl);
7010 NDBG20(("mpt%d reset target before remove "
7011 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, rval));
7012
7013 /*
7014 * Send SAS IO Unit Control to free the dev handle
7015 */
7016 rval = mptsas_free_devhdl(mpt, devhdl);
7017 NDBG20(("mptsas3%d handle_topo_change to remove "
7018 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
7019 rval));
7020 break;
7021 }
7022 case MPTSAS_DR_EVENT_RECONFIG_SMP:
7023 {
7024 mptsas_smp_t smp;
7025 dev_info_t *smpdip;
7026
7027 devhdl = topo_node->devhdl;
7028
7029 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
7030 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
7031 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
7032 if (rval != DDI_SUCCESS) {
7033 mptsas_log(mpt, CE_WARN, "failed to online smp, "
7034 "handle %x", devhdl);
7035 return;
7036 }
7037
7038 psmp = mptsas_smp_alloc(mpt, &smp);
7039 if (psmp == NULL) {
7040 return;
7041 }
7042
7043 mutex_exit(&mpt->m_mutex);
7044 ndi_devi_enter(parent, &circ1);
7045 (void) mptsas_online_smp(parent, psmp, &smpdip);
7046 ndi_devi_exit(parent, circ1);
7047
7048 mutex_enter(&mpt->m_mutex);
7049 break;
7050 }
7051 case MPTSAS_DR_EVENT_OFFLINE_SMP:
7052 {
7053 devhdl = topo_node->devhdl;
7054 uint32_t dev_info;
7055
7056 psmp = refhash_linear_search(mpt->m_smp_targets,
7057 mptsas_smp_eval_devhdl, &devhdl);
7058 if (psmp == NULL)
7059 break;
7060 /*
7061 * The mptsas_smp_t data is released only if the dip is offlined
7062 * successfully.
7063 */
7064 mutex_exit(&mpt->m_mutex);
7065
7066 ndi_devi_enter(parent, &circ1);
7067 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
7068 ndi_devi_exit(parent, circ1);
7069
7070 dev_info = psmp->m_deviceinfo;
7071 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
7072 DEVINFO_DIRECT_ATTACHED) {
7073 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
7074 MPTSAS_VIRTUAL_PORT, 1) !=
7075 DDI_PROP_SUCCESS) {
7076 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
7077 MPTSAS_VIRTUAL_PORT);
7078 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
7079 "prop update failed");
7080 return;
7081 }
7082 /*
7083 * Check whether the smp connected to the iport,
7084 */
7085 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
7086 MPTSAS_NUM_PHYS, 0) !=
7087 DDI_PROP_SUCCESS) {
7088 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
7089 MPTSAS_NUM_PHYS);
7090 mptsas_log(mpt, CE_WARN, "mptsas num phys"
7091 "prop update failed");
7092 return;
7093 }
7094 /*
7095 * Clear parent's attached-port props
7096 */
7097 bzero(attached_wwnstr, sizeof (attached_wwnstr));
7098 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
7099 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
7100 DDI_PROP_SUCCESS) {
7101 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
7102 SCSI_ADDR_PROP_ATTACHED_PORT);
7103 mptsas_log(mpt, CE_WARN, "mptsas attached port "
7104 "prop update failed");
7105 return;
7106 }
7107 }
7108
7109 mutex_enter(&mpt->m_mutex);
7110 NDBG20(("mptsas3%d handle_topo_change to remove devhdl:%x, "
7111 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
7112 if (rval == DDI_SUCCESS) {
7113 refhash_remove(mpt->m_smp_targets, psmp);
7114 } else {
7115 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
7116 }
7117
7118 bzero(attached_wwnstr, sizeof (attached_wwnstr));
7119
7120 break;
7121 }
7122 default:
7123 return;
7124 }
7125 }
7126
7127 /*
7128 * Record the event if its type is enabled in mpt instance by ioctl.
7129 */
7130 static void
7131 mptsas_record_event(void *args)
7132 {
7133 m_replyh_arg_t *replyh_arg;
7134 pMpi2EventNotificationReply_t eventreply;
7135 uint32_t event, rfm;
7136 mptsas_t *mpt;
7137 int i, j;
7138 uint16_t event_data_len;
7139 boolean_t sendAEN = FALSE;
7140
7141 replyh_arg = (m_replyh_arg_t *)args;
7142 rfm = replyh_arg->rfm;
7143 mpt = replyh_arg->mpt;
7144
7145 eventreply = (pMpi2EventNotificationReply_t)
7146 (mpt->m_reply_frame + (rfm -
7147 (mpt->m_reply_frame_dma_addr&0xfffffffful)));
7148 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7149
7150
7151 /*
7152 * Generate a system event to let anyone who cares know that a
7153 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
7154 * event mask is set to.
7155 */
7156 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
7157 sendAEN = TRUE;
7158 }
7159
7160 /*
7161 * Record the event only if it is not masked. Determine which dword
7162 * and bit of event mask to test.
7163 */
7164 i = (uint8_t)(event / 32);
7165 j = (uint8_t)(event % 32);
7166 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
7167 i = mpt->m_event_index;
7168 mpt->m_events[i].Type = event;
7169 mpt->m_events[i].Number = ++mpt->m_event_number;
7170 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
7171 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
7172 &eventreply->EventDataLength);
7173
7174 if (event_data_len > 0) {
7175 /*
7176 * Limit data to size in m_event entry
7177 */
7178 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
7179 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
7180 }
7181 for (j = 0; j < event_data_len; j++) {
7182 mpt->m_events[i].Data[j] =
7183 ddi_get32(mpt->m_acc_reply_frame_hdl,
7184 &(eventreply->EventData[j]));
7185 }
7186
7187 /*
7188 * check for index wrap-around
7189 */
7190 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
7191 i = 0;
7192 }
7193 mpt->m_event_index = (uint8_t)i;
7194
7195 /*
7196 * Set flag to send the event.
7197 */
7198 sendAEN = TRUE;
7199 }
7200 }
7201
7202 /*
7203 * Generate a system event if flag is set to let anyone who cares know
7204 * that an event has occurred.
7205 */
7206 if (sendAEN) {
7207 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
7208 "SAS", NULL, NULL, DDI_NOSLEEP);
7209 }
7210 }
7211
7212 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
7213 /*
7214 * handle sync events from ioc in interrupt
7215 * return value:
7216 * DDI_SUCCESS: The event is handled by this func
7217 * DDI_FAILURE: Event is not handled
7218 */
7219 static int
7220 mptsas_handle_event_sync(void *args)
7221 {
7222 m_replyh_arg_t *replyh_arg;
7223 pMpi2EventNotificationReply_t eventreply;
7224 uint32_t event, rfm;
7225 mptsas_t *mpt;
7226 uint_t iocstatus;
7227
7228 replyh_arg = (m_replyh_arg_t *)args;
7229 rfm = replyh_arg->rfm;
7230 mpt = replyh_arg->mpt;
7231
7232 ASSERT(mutex_owned(&mpt->m_mutex));
7233
7234 eventreply = (pMpi2EventNotificationReply_t)
7235 (mpt->m_reply_frame + (rfm -
7236 (mpt->m_reply_frame_dma_addr&0xfffffffful)));
7237 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7238
7239 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7240 &eventreply->IOCStatus)) {
7241 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7242 mptsas_log(mpt, CE_WARN,
7243 "!mptsas_handle_event_sync: event 0x%x, "
7244 "IOCStatus=0x%x, "
7245 "IOCLogInfo=0x%x", event, iocstatus,
7246 ddi_get32(mpt->m_acc_reply_frame_hdl,
7247 &eventreply->IOCLogInfo));
7248 } else {
7249 mptsas_log(mpt, CE_WARN,
7250 "mptsas_handle_event_sync: event 0x%x, "
7251 "IOCStatus=0x%x, "
7252 "(IOCLogInfo=0x%x)", event, iocstatus,
7253 ddi_get32(mpt->m_acc_reply_frame_hdl,
7254 &eventreply->IOCLogInfo));
7255 }
7256 }
7257
7258 /*
7259 * figure out what kind of event we got and handle accordingly
7260 */
7261 switch (event) {
7262 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7263 {
7264 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
7265 uint8_t num_entries, expstatus, phy;
7266 uint8_t phystatus, physport, state, i;
7267 uint8_t start_phy_num, link_rate;
7268 uint16_t dev_handle, reason_code;
7269 uint16_t enc_handle, expd_handle;
7270 char string[80], curr[80], prev[80];
7271 mptsas_topo_change_list_t *topo_head = NULL;
7272 mptsas_topo_change_list_t *topo_tail = NULL;
7273 mptsas_topo_change_list_t *topo_node = NULL;
7274 mptsas_target_t *ptgt;
7275 mptsas_smp_t *psmp;
7276 uint8_t flags = 0, exp_flag;
7277 smhba_info_t *pSmhba = NULL;
7278
7279 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
7280
7281 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
7282 eventreply->EventData;
7283
7284 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7285 &sas_topo_change_list->EnclosureHandle);
7286 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7287 &sas_topo_change_list->ExpanderDevHandle);
7288 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7289 &sas_topo_change_list->NumEntries);
7290 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7291 &sas_topo_change_list->StartPhyNum);
7292 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
7293 &sas_topo_change_list->ExpStatus);
7294 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
7295 &sas_topo_change_list->PhysicalPort);
7296
7297 string[0] = 0;
7298 if (expd_handle) {
7299 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
7300 switch (expstatus) {
7301 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
7302 (void) sprintf(string, " added");
7303 /*
7304 * New expander device added
7305 */
7306 mpt->m_port_chng = 1;
7307 topo_node = kmem_zalloc(
7308 sizeof (mptsas_topo_change_list_t),
7309 KM_SLEEP);
7310 topo_node->mpt = mpt;
7311 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
7312 topo_node->un.physport = physport;
7313 topo_node->devhdl = expd_handle;
7314 topo_node->flags = flags;
7315 topo_node->object = NULL;
7316 if (topo_head == NULL) {
7317 topo_head = topo_tail = topo_node;
7318 } else {
7319 topo_tail->next = topo_node;
7320 topo_tail = topo_node;
7321 }
7322 break;
7323 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
7324 (void) sprintf(string, " not responding, "
7325 "removed");
7326 psmp = refhash_linear_search(mpt->m_smp_targets,
7327 mptsas_smp_eval_devhdl, &expd_handle);
7328 if (psmp == NULL)
7329 break;
7330
7331 topo_node = kmem_zalloc(
7332 sizeof (mptsas_topo_change_list_t),
7333 KM_SLEEP);
7334 topo_node->mpt = mpt;
7335 topo_node->un.phymask =
7336 psmp->m_addr.mta_phymask;
7337 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
7338 topo_node->devhdl = expd_handle;
7339 topo_node->flags = flags;
7340 topo_node->object = NULL;
7341 if (topo_head == NULL) {
7342 topo_head = topo_tail = topo_node;
7343 } else {
7344 topo_tail->next = topo_node;
7345 topo_tail = topo_node;
7346 }
7347 break;
7348 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
7349 break;
7350 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
7351 (void) sprintf(string, " not responding, "
7352 "delaying removal");
7353 break;
7354 default:
7355 break;
7356 }
7357 } else {
7358 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
7359 }
7360
7361 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
7362 enc_handle, expd_handle, string));
7363 for (i = 0; i < num_entries; i++) {
7364 phy = i + start_phy_num;
7365 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
7366 &sas_topo_change_list->PHY[i].PhyStatus);
7367 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7368 &sas_topo_change_list->PHY[i].AttachedDevHandle);
7369 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
7370 /*
7371 * Filter out processing of Phy Vacant Status unless
7372 * the reason code is "Not Responding". Process all
7373 * other combinations of Phy Status and Reason Codes.
7374 */
7375 if ((phystatus &
7376 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
7377 (reason_code !=
7378 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
7379 continue;
7380 }
7381 curr[0] = 0;
7382 prev[0] = 0;
7383 string[0] = 0;
7384 switch (reason_code) {
7385 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
7386 {
7387 NDBG20(("mptsas3%d phy %d physical_port %d "
7388 "dev_handle %d added", mpt->m_instance, phy,
7389 physport, dev_handle));
7390 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7391 &sas_topo_change_list->PHY[i].LinkRate);
7392 state = (link_rate &
7393 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7394 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7395 switch (state) {
7396 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7397 (void) sprintf(curr, "is disabled");
7398 break;
7399 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7400 (void) sprintf(curr, "is offline, "
7401 "failed speed negotiation");
7402 break;
7403 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7404 (void) sprintf(curr, "SATA OOB "
7405 "complete");
7406 break;
7407 case SMP_RESET_IN_PROGRESS:
7408 (void) sprintf(curr, "SMP reset in "
7409 "progress");
7410 break;
7411 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7412 (void) sprintf(curr, "is online at "
7413 "1.5 Gbps");
7414 break;
7415 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7416 (void) sprintf(curr, "is online at 3.0 "
7417 "Gbps");
7418 break;
7419 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7420 (void) sprintf(curr, "is online at 6.0 "
7421 "Gbps");
7422 break;
7423 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7424 (void) sprintf(curr,
7425 "is online at 12.0 Gbps");
7426 break;
7427 default:
7428 (void) sprintf(curr, "state is "
7429 "unknown");
7430 break;
7431 }
7432 /*
7433 * New target device added into the system.
7434 * Set association flag according to if an
7435 * expander is used or not.
7436 */
7437 exp_flag =
7438 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7439 if (flags ==
7440 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7441 flags = exp_flag;
7442 }
7443 topo_node = kmem_zalloc(
7444 sizeof (mptsas_topo_change_list_t),
7445 KM_SLEEP);
7446 topo_node->mpt = mpt;
7447 topo_node->event =
7448 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7449 if (expd_handle == 0) {
7450 /*
7451 * Per MPI 2, if expander dev handle
7452 * is 0, it's a directly attached
7453 * device. So driver use PHY to decide
7454 * which iport is associated
7455 */
7456 physport = phy;
7457 mpt->m_port_chng = 1;
7458 }
7459 topo_node->un.physport = physport;
7460 topo_node->devhdl = dev_handle;
7461 topo_node->flags = flags;
7462 topo_node->object = NULL;
7463 if (topo_head == NULL) {
7464 topo_head = topo_tail = topo_node;
7465 } else {
7466 topo_tail->next = topo_node;
7467 topo_tail = topo_node;
7468 }
7469 break;
7470 }
7471 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
7472 {
7473 NDBG20(("mptsas3%d phy %d physical_port %d "
7474 "dev_handle %d removed", mpt->m_instance,
7475 phy, physport, dev_handle));
7476 /*
7477 * Set association flag according to if an
7478 * expander is used or not.
7479 */
7480 exp_flag =
7481 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7482 if (flags ==
7483 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7484 flags = exp_flag;
7485 }
7486 /*
7487 * Target device is removed from the system
7488 * Before the device is really offline from
7489 * from system.
7490 */
7491 ptgt = refhash_linear_search(mpt->m_targets,
7492 mptsas_target_eval_devhdl, &dev_handle);
7493 /*
7494 * If ptgt is NULL here, it means that the
7495 * DevHandle is not in the hash table. This is
7496 * reasonable sometimes. For example, if a
7497 * disk was pulled, then added, then pulled
7498 * again, the disk will not have been put into
7499 * the hash table because the add event will
7500 * have an invalid phymask. BUT, this does not
7501 * mean that the DevHandle is invalid. The
7502 * controller will still have a valid DevHandle
7503 * that must be removed. To do this, use the
7504 * MPTSAS_DR_EVENT_REMOVE_HANDLE event.
7505 */
7506 if (ptgt == NULL) {
7507 topo_node = kmem_zalloc(
7508 sizeof (mptsas_topo_change_list_t),
7509 KM_SLEEP);
7510 topo_node->mpt = mpt;
7511 topo_node->un.phymask = 0;
7512 topo_node->event =
7513 MPTSAS_DR_EVENT_REMOVE_HANDLE;
7514 topo_node->devhdl = dev_handle;
7515 topo_node->flags = flags;
7516 topo_node->object = NULL;
7517 if (topo_head == NULL) {
7518 topo_head = topo_tail =
7519 topo_node;
7520 } else {
7521 topo_tail->next = topo_node;
7522 topo_tail = topo_node;
7523 }
7524 break;
7525 }
7526
7527 /*
7528 * Update DR flag immediately avoid I/O failure
7529 * before failover finish. We won't add
7530 * any following commands into waitq, instead,
7531 * we need return TRAN_BUSY in the tran_start
7532 * context.
7533 */
7534 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7535
7536 topo_node = kmem_zalloc(
7537 sizeof (mptsas_topo_change_list_t),
7538 KM_SLEEP);
7539 topo_node->mpt = mpt;
7540 topo_node->un.phymask =
7541 ptgt->m_addr.mta_phymask;
7542 topo_node->event =
7543 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7544 topo_node->devhdl = dev_handle;
7545 topo_node->flags = flags;
7546 topo_node->object = NULL;
7547 if (topo_head == NULL) {
7548 topo_head = topo_tail = topo_node;
7549 } else {
7550 topo_tail->next = topo_node;
7551 topo_tail = topo_node;
7552 }
7553 break;
7554 }
7555 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
7556 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7557 &sas_topo_change_list->PHY[i].LinkRate);
7558 state = (link_rate &
7559 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7560 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7561 pSmhba = &mpt->m_phy_info[i].smhba_info;
7562 pSmhba->negotiated_link_rate = state;
7563 switch (state) {
7564 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7565 (void) sprintf(curr, "is disabled");
7566 mptsas_smhba_log_sysevent(mpt,
7567 ESC_SAS_PHY_EVENT,
7568 SAS_PHY_REMOVE,
7569 &mpt->m_phy_info[i].smhba_info);
7570 mpt->m_phy_info[i].smhba_info.
7571 negotiated_link_rate
7572 = 0x1;
7573 break;
7574 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7575 (void) sprintf(curr, "is offline, "
7576 "failed speed negotiation");
7577 mptsas_smhba_log_sysevent(mpt,
7578 ESC_SAS_PHY_EVENT,
7579 SAS_PHY_OFFLINE,
7580 &mpt->m_phy_info[i].smhba_info);
7581 break;
7582 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7583 (void) sprintf(curr, "SATA OOB "
7584 "complete");
7585 break;
7586 case SMP_RESET_IN_PROGRESS:
7587 (void) sprintf(curr, "SMP reset in "
7588 "progress");
7589 break;
7590 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7591 (void) sprintf(curr, "is online at "
7592 "1.5 Gbps");
7593 if ((expd_handle == 0) &&
7594 (enc_handle == 1)) {
7595 mpt->m_port_chng = 1;
7596 }
7597 mptsas_smhba_log_sysevent(mpt,
7598 ESC_SAS_PHY_EVENT,
7599 SAS_PHY_ONLINE,
7600 &mpt->m_phy_info[i].smhba_info);
7601 break;
7602 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7603 (void) sprintf(curr, "is online at 3.0 "
7604 "Gbps");
7605 if ((expd_handle == 0) &&
7606 (enc_handle == 1)) {
7607 mpt->m_port_chng = 1;
7608 }
7609 mptsas_smhba_log_sysevent(mpt,
7610 ESC_SAS_PHY_EVENT,
7611 SAS_PHY_ONLINE,
7612 &mpt->m_phy_info[i].smhba_info);
7613 break;
7614 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7615 (void) sprintf(curr, "is online at "
7616 "6.0 Gbps");
7617 if ((expd_handle == 0) &&
7618 (enc_handle == 1)) {
7619 mpt->m_port_chng = 1;
7620 }
7621 mptsas_smhba_log_sysevent(mpt,
7622 ESC_SAS_PHY_EVENT,
7623 SAS_PHY_ONLINE,
7624 &mpt->m_phy_info[i].smhba_info);
7625 break;
7626 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7627 (void) sprintf(curr, "is online at "
7628 "12.0 Gbps");
7629 if ((expd_handle == 0) &&
7630 (enc_handle == 1)) {
7631 mpt->m_port_chng = 1;
7632 }
7633 mptsas_smhba_log_sysevent(mpt,
7634 ESC_SAS_PHY_EVENT,
7635 SAS_PHY_ONLINE,
7636 &mpt->m_phy_info[i].smhba_info);
7637 break;
7638 default:
7639 (void) sprintf(curr, "state is "
7640 "unknown");
7641 break;
7642 }
7643
7644 state = (link_rate &
7645 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
7646 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
7647 switch (state) {
7648 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7649 (void) sprintf(prev, ", was disabled");
7650 break;
7651 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7652 (void) sprintf(prev, ", was offline, "
7653 "failed speed negotiation");
7654 break;
7655 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7656 (void) sprintf(prev, ", was SATA OOB "
7657 "complete");
7658 break;
7659 case SMP_RESET_IN_PROGRESS:
7660 (void) sprintf(prev, ", was SMP reset "
7661 "in progress");
7662 break;
7663 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7664 (void) sprintf(prev, ", was online at "
7665 "1.5 Gbps");
7666 break;
7667 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7668 (void) sprintf(prev, ", was online at "
7669 "3.0 Gbps");
7670 break;
7671 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7672 (void) sprintf(prev, ", was online at "
7673 "6.0 Gbps");
7674 break;
7675 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7676 (void) sprintf(prev, ", was online at "
7677 "12.0 Gbps");
7678 break;
7679 default:
7680 break;
7681 }
7682 (void) sprintf(&string[strlen(string)], "link "
7683 "changed, ");
7684 break;
7685 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
7686 continue;
7687 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
7688 (void) sprintf(&string[strlen(string)],
7689 "target not responding, delaying "
7690 "removal");
7691 break;
7692 }
7693 NDBG20(("mptsas3%d phy %d DevHandle %x, %s%s%s\n",
7694 mpt->m_instance, phy, dev_handle, string, curr,
7695 prev));
7696 }
7697 if (topo_head != NULL) {
7698 /*
7699 * Launch DR taskq to handle topology change
7700 */
7701 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7702 mptsas_handle_dr, (void *)topo_head,
7703 DDI_NOSLEEP)) != DDI_SUCCESS) {
7704 while (topo_head != NULL) {
7705 topo_node = topo_head;
7706 topo_head = topo_head->next;
7707 kmem_free(topo_node,
7708 sizeof (mptsas_topo_change_list_t));
7709 }
7710 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7711 "for handle SAS DR event failed. \n");
7712 }
7713 }
7714 break;
7715 }
7716 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7717 {
7718 Mpi2EventDataIrConfigChangeList_t *irChangeList;
7719 mptsas_topo_change_list_t *topo_head = NULL;
7720 mptsas_topo_change_list_t *topo_tail = NULL;
7721 mptsas_topo_change_list_t *topo_node = NULL;
7722 mptsas_target_t *ptgt;
7723 uint8_t num_entries, i, reason;
7724 uint16_t volhandle, diskhandle;
7725
7726 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
7727 eventreply->EventData;
7728 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7729 &irChangeList->NumElements);
7730
7731 NDBG20(("mptsas3%d IR_CONFIGURATION_CHANGE_LIST event received",
7732 mpt->m_instance));
7733
7734 for (i = 0; i < num_entries; i++) {
7735 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7736 &irChangeList->ConfigElement[i].ReasonCode);
7737 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7738 &irChangeList->ConfigElement[i].VolDevHandle);
7739 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7740 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
7741
7742 switch (reason) {
7743 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
7744 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
7745 {
7746 NDBG20(("mptsas %d volume added\n",
7747 mpt->m_instance));
7748
7749 topo_node = kmem_zalloc(
7750 sizeof (mptsas_topo_change_list_t),
7751 KM_SLEEP);
7752
7753 topo_node->mpt = mpt;
7754 topo_node->event =
7755 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7756 topo_node->un.physport = 0xff;
7757 topo_node->devhdl = volhandle;
7758 topo_node->flags =
7759 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7760 topo_node->object = NULL;
7761 if (topo_head == NULL) {
7762 topo_head = topo_tail = topo_node;
7763 } else {
7764 topo_tail->next = topo_node;
7765 topo_tail = topo_node;
7766 }
7767 break;
7768 }
7769 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
7770 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
7771 {
7772 NDBG20(("mptsas %d volume deleted\n",
7773 mpt->m_instance));
7774 ptgt = refhash_linear_search(mpt->m_targets,
7775 mptsas_target_eval_devhdl, &volhandle);
7776 if (ptgt == NULL)
7777 break;
7778
7779 /*
7780 * Clear any flags related to volume
7781 */
7782 (void) mptsas_delete_volume(mpt, volhandle);
7783
7784 /*
7785 * Update DR flag immediately avoid I/O failure
7786 */
7787 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7788
7789 topo_node = kmem_zalloc(
7790 sizeof (mptsas_topo_change_list_t),
7791 KM_SLEEP);
7792 topo_node->mpt = mpt;
7793 topo_node->un.phymask =
7794 ptgt->m_addr.mta_phymask;
7795 topo_node->event =
7796 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7797 topo_node->devhdl = volhandle;
7798 topo_node->flags =
7799 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7800 topo_node->object = (void *)ptgt;
7801 if (topo_head == NULL) {
7802 topo_head = topo_tail = topo_node;
7803 } else {
7804 topo_tail->next = topo_node;
7805 topo_tail = topo_node;
7806 }
7807 break;
7808 }
7809 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
7810 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
7811 {
7812 ptgt = refhash_linear_search(mpt->m_targets,
7813 mptsas_target_eval_devhdl, &diskhandle);
7814 if (ptgt == NULL)
7815 break;
7816
7817 /*
7818 * Update DR flag immediately avoid I/O failure
7819 */
7820 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7821
7822 topo_node = kmem_zalloc(
7823 sizeof (mptsas_topo_change_list_t),
7824 KM_SLEEP);
7825 topo_node->mpt = mpt;
7826 topo_node->un.phymask =
7827 ptgt->m_addr.mta_phymask;
7828 topo_node->event =
7829 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7830 topo_node->devhdl = diskhandle;
7831 topo_node->flags =
7832 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7833 topo_node->object = (void *)ptgt;
7834 if (topo_head == NULL) {
7835 topo_head = topo_tail = topo_node;
7836 } else {
7837 topo_tail->next = topo_node;
7838 topo_tail = topo_node;
7839 }
7840 break;
7841 }
7842 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
7843 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
7844 {
7845 /*
7846 * The physical drive is released by a IR
7847 * volume. But we cannot get the the physport
7848 * or phynum from the event data, so we only
7849 * can get the physport/phynum after SAS
7850 * Device Page0 request for the devhdl.
7851 */
7852 topo_node = kmem_zalloc(
7853 sizeof (mptsas_topo_change_list_t),
7854 KM_SLEEP);
7855 topo_node->mpt = mpt;
7856 topo_node->un.phymask = 0;
7857 topo_node->event =
7858 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7859 topo_node->devhdl = diskhandle;
7860 topo_node->flags =
7861 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7862 topo_node->object = NULL;
7863 mpt->m_port_chng = 1;
7864 if (topo_head == NULL) {
7865 topo_head = topo_tail = topo_node;
7866 } else {
7867 topo_tail->next = topo_node;
7868 topo_tail = topo_node;
7869 }
7870 break;
7871 }
7872 default:
7873 break;
7874 }
7875 }
7876
7877 if (topo_head != NULL) {
7878 /*
7879 * Launch DR taskq to handle topology change
7880 */
7881 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7882 mptsas_handle_dr, (void *)topo_head,
7883 DDI_NOSLEEP)) != DDI_SUCCESS) {
7884 while (topo_head != NULL) {
7885 topo_node = topo_head;
7886 topo_head = topo_head->next;
7887 kmem_free(topo_node,
7888 sizeof (mptsas_topo_change_list_t));
7889 }
7890 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7891 "for handle SAS DR event failed. \n");
7892 }
7893 }
7894 break;
7895 }
7896 default:
7897 return (DDI_FAILURE);
7898 }
7899
7900 return (DDI_SUCCESS);
7901 }
7902
7903 /*
7904 * handle events from ioc
7905 */
7906 static void
7907 mptsas_handle_event(void *args)
7908 {
7909 m_replyh_arg_t *replyh_arg;
7910 pMpi2EventNotificationReply_t eventreply;
7911 uint32_t event, iocloginfo, rfm;
7912 uint32_t status;
7913 uint8_t port;
7914 mptsas_t *mpt;
7915 uint_t iocstatus;
7916
7917 replyh_arg = (m_replyh_arg_t *)args;
7918 rfm = replyh_arg->rfm;
7919 mpt = replyh_arg->mpt;
7920
7921 mutex_enter(&mpt->m_mutex);
7922 /*
7923 * If HBA is being reset, drop incoming event.
7924 */
7925 if (mpt->m_in_reset) {
7926 NDBG20(("dropping event received prior to reset"));
7927 mutex_exit(&mpt->m_mutex);
7928 return;
7929 }
7930
7931 eventreply = (pMpi2EventNotificationReply_t)
7932 (mpt->m_reply_frame + (rfm -
7933 (mpt->m_reply_frame_dma_addr&0xfffffffful)));
7934 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7935
7936 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7937 &eventreply->IOCStatus)) {
7938 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7939 mptsas_log(mpt, CE_WARN,
7940 "!mptsas_handle_event: IOCStatus=0x%x, "
7941 "IOCLogInfo=0x%x", iocstatus,
7942 ddi_get32(mpt->m_acc_reply_frame_hdl,
7943 &eventreply->IOCLogInfo));
7944 } else {
7945 mptsas_log(mpt, CE_WARN,
7946 "mptsas_handle_event: IOCStatus=0x%x, "
7947 "IOCLogInfo=0x%x", iocstatus,
7948 ddi_get32(mpt->m_acc_reply_frame_hdl,
7949 &eventreply->IOCLogInfo));
7950 }
7951 }
7952
7953 /*
7954 * figure out what kind of event we got and handle accordingly
7955 */
7956 switch (event) {
7957 case MPI2_EVENT_LOG_ENTRY_ADDED:
7958 break;
7959 case MPI2_EVENT_LOG_DATA:
7960 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7961 &eventreply->IOCLogInfo);
7962 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7963 iocloginfo));
7964 break;
7965 case MPI2_EVENT_STATE_CHANGE:
7966 NDBG20(("mptsas3%d state change.", mpt->m_instance));
7967 break;
7968 case MPI2_EVENT_HARD_RESET_RECEIVED:
7969 NDBG20(("mptsas3%d event change.", mpt->m_instance));
7970 break;
7971 case MPI2_EVENT_SAS_DISCOVERY:
7972 {
7973 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7974 char string[80];
7975 uint8_t rc;
7976
7977 sasdiscovery =
7978 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7979
7980 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7981 &sasdiscovery->ReasonCode);
7982 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7983 &sasdiscovery->PhysicalPort);
7984 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7985 &sasdiscovery->DiscoveryStatus);
7986
7987 string[0] = 0;
7988 switch (rc) {
7989 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7990 (void) sprintf(string, "STARTING");
7991 break;
7992 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7993 (void) sprintf(string, "COMPLETED");
7994 break;
7995 default:
7996 (void) sprintf(string, "UNKNOWN");
7997 break;
7998 }
7999
8000 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
8001 port, status));
8002
8003 break;
8004 }
8005 case MPI2_EVENT_EVENT_CHANGE:
8006 NDBG20(("mptsas3%d event change.", mpt->m_instance));
8007 break;
8008 case MPI2_EVENT_TASK_SET_FULL:
8009 {
8010 pMpi2EventDataTaskSetFull_t taskfull;
8011
8012 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
8013
8014 NDBG20(("TASK_SET_FULL received for mptsas3%d, depth %d\n",
8015 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
8016 &taskfull->CurrentDepth)));
8017 break;
8018 }
8019 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
8020 {
8021 /*
8022 * SAS TOPOLOGY CHANGE LIST Event has already been handled
8023 * in mptsas_handle_event_sync() of interrupt context
8024 */
8025 break;
8026 }
8027 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
8028 {
8029 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
8030 uint8_t rc;
8031 char string[80];
8032
8033 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
8034 eventreply->EventData;
8035
8036 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
8037 &encstatus->ReasonCode);
8038 switch (rc) {
8039 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
8040 (void) sprintf(string, "added");
8041 break;
8042 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
8043 (void) sprintf(string, ", not responding");
8044 break;
8045 default:
8046 break;
8047 }
8048 NDBG20(("mptsas3%d ENCLOSURE STATUS CHANGE for enclosure "
8049 "%x%s\n", mpt->m_instance,
8050 ddi_get16(mpt->m_acc_reply_frame_hdl,
8051 &encstatus->EnclosureHandle), string));
8052 break;
8053 }
8054
8055 /*
8056 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
8057 * mptsas_handle_event_sync,in here just send ack message.
8058 */
8059 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
8060 {
8061 pMpi2EventDataSasDeviceStatusChange_t statuschange;
8062 uint8_t rc;
8063 uint16_t devhdl;
8064 uint64_t wwn = 0;
8065 uint32_t wwn_lo, wwn_hi;
8066
8067 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
8068 eventreply->EventData;
8069 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
8070 &statuschange->ReasonCode);
8071 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
8072 (uint32_t *)(void *)&statuschange->SASAddress);
8073 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
8074 (uint32_t *)(void *)&statuschange->SASAddress + 1);
8075 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
8076 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
8077 &statuschange->DevHandle);
8078
8079 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
8080 wwn));
8081
8082 switch (rc) {
8083 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
8084 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
8085 ddi_get8(mpt->m_acc_reply_frame_hdl,
8086 &statuschange->ASC),
8087 ddi_get8(mpt->m_acc_reply_frame_hdl,
8088 &statuschange->ASCQ)));
8089 break;
8090
8091 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
8092 NDBG20(("Device not supported"));
8093 break;
8094
8095 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
8096 NDBG20(("IOC internally generated the Target Reset "
8097 "for devhdl:%x", devhdl));
8098 break;
8099
8100 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
8101 NDBG20(("IOC's internally generated Target Reset "
8102 "completed for devhdl:%x", devhdl));
8103 break;
8104
8105 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
8106 NDBG20(("IOC internally generated Abort Task"));
8107 break;
8108
8109 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
8110 NDBG20(("IOC's internally generated Abort Task "
8111 "completed"));
8112 break;
8113
8114 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
8115 NDBG20(("IOC internally generated Abort Task Set"));
8116 break;
8117
8118 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
8119 NDBG20(("IOC internally generated Clear Task Set"));
8120 break;
8121
8122 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
8123 NDBG20(("IOC internally generated Query Task"));
8124 break;
8125
8126 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
8127 NDBG20(("Device sent an Asynchronous Notification"));
8128 break;
8129
8130 default:
8131 break;
8132 }
8133 break;
8134 }
8135 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
8136 {
8137 /*
8138 * IR TOPOLOGY CHANGE LIST Event has already been handled
8139 * in mpt_handle_event_sync() of interrupt context
8140 */
8141 break;
8142 }
8143 case MPI2_EVENT_IR_OPERATION_STATUS:
8144 {
8145 Mpi2EventDataIrOperationStatus_t *irOpStatus;
8146 char reason_str[80];
8147 uint8_t rc, percent;
8148 uint16_t handle;
8149
8150 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
8151 eventreply->EventData;
8152 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
8153 &irOpStatus->RAIDOperation);
8154 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
8155 &irOpStatus->PercentComplete);
8156 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8157 &irOpStatus->VolDevHandle);
8158
8159 switch (rc) {
8160 case MPI2_EVENT_IR_RAIDOP_RESYNC:
8161 (void) sprintf(reason_str, "resync");
8162 break;
8163 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
8164 (void) sprintf(reason_str, "online capacity "
8165 "expansion");
8166 break;
8167 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
8168 (void) sprintf(reason_str, "consistency check");
8169 break;
8170 default:
8171 (void) sprintf(reason_str, "unknown reason %x",
8172 rc);
8173 }
8174
8175 NDBG20(("mptsas3%d raid operational status: (%s)"
8176 "\thandle(0x%04x), percent complete(%d)\n",
8177 mpt->m_instance, reason_str, handle, percent));
8178 break;
8179 }
8180 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
8181 {
8182 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
8183 uint8_t phy_num;
8184 uint8_t primitive;
8185
8186 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
8187 eventreply->EventData;
8188
8189 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
8190 &sas_broadcast->PhyNum);
8191 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
8192 &sas_broadcast->Primitive);
8193
8194 switch (primitive) {
8195 case MPI2_EVENT_PRIMITIVE_CHANGE:
8196 mptsas_smhba_log_sysevent(mpt,
8197 ESC_SAS_HBA_PORT_BROADCAST,
8198 SAS_PORT_BROADCAST_CHANGE,
8199 &mpt->m_phy_info[phy_num].smhba_info);
8200 break;
8201 case MPI2_EVENT_PRIMITIVE_SES:
8202 mptsas_smhba_log_sysevent(mpt,
8203 ESC_SAS_HBA_PORT_BROADCAST,
8204 SAS_PORT_BROADCAST_SES,
8205 &mpt->m_phy_info[phy_num].smhba_info);
8206 break;
8207 case MPI2_EVENT_PRIMITIVE_EXPANDER:
8208 mptsas_smhba_log_sysevent(mpt,
8209 ESC_SAS_HBA_PORT_BROADCAST,
8210 SAS_PORT_BROADCAST_D01_4,
8211 &mpt->m_phy_info[phy_num].smhba_info);
8212 break;
8213 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
8214 mptsas_smhba_log_sysevent(mpt,
8215 ESC_SAS_HBA_PORT_BROADCAST,
8216 SAS_PORT_BROADCAST_D04_7,
8217 &mpt->m_phy_info[phy_num].smhba_info);
8218 break;
8219 case MPI2_EVENT_PRIMITIVE_RESERVED3:
8220 mptsas_smhba_log_sysevent(mpt,
8221 ESC_SAS_HBA_PORT_BROADCAST,
8222 SAS_PORT_BROADCAST_D16_7,
8223 &mpt->m_phy_info[phy_num].smhba_info);
8224 break;
8225 case MPI2_EVENT_PRIMITIVE_RESERVED4:
8226 mptsas_smhba_log_sysevent(mpt,
8227 ESC_SAS_HBA_PORT_BROADCAST,
8228 SAS_PORT_BROADCAST_D29_7,
8229 &mpt->m_phy_info[phy_num].smhba_info);
8230 break;
8231 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
8232 mptsas_smhba_log_sysevent(mpt,
8233 ESC_SAS_HBA_PORT_BROADCAST,
8234 SAS_PORT_BROADCAST_D24_0,
8235 &mpt->m_phy_info[phy_num].smhba_info);
8236 break;
8237 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
8238 mptsas_smhba_log_sysevent(mpt,
8239 ESC_SAS_HBA_PORT_BROADCAST,
8240 SAS_PORT_BROADCAST_D27_4,
8241 &mpt->m_phy_info[phy_num].smhba_info);
8242 break;
8243 default:
8244 NDBG16(("mptsas3%d: unknown BROADCAST PRIMITIVE"
8245 " %x received",
8246 mpt->m_instance, primitive));
8247 break;
8248 }
8249 NDBG16(("mptsas3%d sas broadcast primitive: "
8250 "\tprimitive(0x%04x), phy(%d) complete\n",
8251 mpt->m_instance, primitive, phy_num));
8252 break;
8253 }
8254 case MPI2_EVENT_IR_VOLUME:
8255 {
8256 Mpi2EventDataIrVolume_t *irVolume;
8257 uint16_t devhandle;
8258 uint32_t state;
8259 int config, vol;
8260 uint8_t found = FALSE;
8261
8262 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
8263 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
8264 &irVolume->NewValue);
8265 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8266 &irVolume->VolDevHandle);
8267
8268 NDBG20(("EVENT_IR_VOLUME event is received"));
8269
8270 /*
8271 * Get latest RAID info and then find the DevHandle for this
8272 * event in the configuration. If the DevHandle is not found
8273 * just exit the event.
8274 */
8275 (void) mptsas_get_raid_info(mpt);
8276 for (config = 0; (config < mpt->m_num_raid_configs) &&
8277 (!found); config++) {
8278 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
8279 if (mpt->m_raidconfig[config].m_raidvol[vol].
8280 m_raidhandle == devhandle) {
8281 found = TRUE;
8282 break;
8283 }
8284 }
8285 }
8286 if (!found) {
8287 break;
8288 }
8289
8290 switch (irVolume->ReasonCode) {
8291 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
8292 {
8293 uint32_t i;
8294 mpt->m_raidconfig[config].m_raidvol[vol].m_settings =
8295 state;
8296
8297 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
8298 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
8299 ", auto-config of hot-swap drives is %s"
8300 ", write caching is %s"
8301 ", hot-spare pool mask is %02x\n",
8302 vol, state &
8303 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
8304 ? "disabled" : "enabled",
8305 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
8306 ? "controlled by member disks" :
8307 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
8308 ? "disabled" :
8309 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
8310 ? "enabled" :
8311 "incorrectly set",
8312 (state >> 16) & 0xff);
8313 break;
8314 }
8315 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
8316 {
8317 mpt->m_raidconfig[config].m_raidvol[vol].m_state =
8318 (uint8_t)state;
8319
8320 mptsas_log(mpt, CE_NOTE,
8321 "Volume %d is now %s\n", vol,
8322 state == MPI2_RAID_VOL_STATE_OPTIMAL
8323 ? "optimal" :
8324 state == MPI2_RAID_VOL_STATE_DEGRADED
8325 ? "degraded" :
8326 state == MPI2_RAID_VOL_STATE_ONLINE
8327 ? "online" :
8328 state == MPI2_RAID_VOL_STATE_INITIALIZING
8329 ? "initializing" :
8330 state == MPI2_RAID_VOL_STATE_FAILED
8331 ? "failed" :
8332 state == MPI2_RAID_VOL_STATE_MISSING
8333 ? "missing" :
8334 "state unknown");
8335 break;
8336 }
8337 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
8338 {
8339 mpt->m_raidconfig[config].m_raidvol[vol].
8340 m_statusflags = state;
8341
8342 mptsas_log(mpt, CE_NOTE,
8343 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
8344 vol,
8345 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
8346 ? ", enabled" : ", disabled",
8347 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
8348 ? ", quiesced" : "",
8349 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
8350 ? ", inactive" : ", active",
8351 state &
8352 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
8353 ? ", bad block table is full" : "",
8354 state &
8355 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
8356 ? ", resync in progress" : "",
8357 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
8358 ? ", background initialization in progress" : "",
8359 state &
8360 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
8361 ? ", capacity expansion in progress" : "",
8362 state &
8363 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
8364 ? ", consistency check in progress" : "",
8365 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
8366 ? ", data scrub in progress" : "");
8367 break;
8368 }
8369 default:
8370 break;
8371 }
8372 break;
8373 }
8374 case MPI2_EVENT_IR_PHYSICAL_DISK:
8375 {
8376 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
8377 uint16_t devhandle, enchandle, slot;
8378 uint32_t status, state;
8379 uint8_t physdisknum, reason;
8380
8381 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
8382 eventreply->EventData;
8383 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
8384 &irPhysDisk->PhysDiskNum);
8385 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8386 &irPhysDisk->PhysDiskDevHandle);
8387 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8388 &irPhysDisk->EnclosureHandle);
8389 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
8390 &irPhysDisk->Slot);
8391 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
8392 &irPhysDisk->NewValue);
8393 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
8394 &irPhysDisk->ReasonCode);
8395
8396 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
8397
8398 switch (reason) {
8399 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
8400 mptsas_log(mpt, CE_NOTE,
8401 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8402 "for enclosure with handle 0x%x is now in hot "
8403 "spare pool %d",
8404 physdisknum, devhandle, slot, enchandle,
8405 (state >> 16) & 0xff);
8406 break;
8407
8408 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
8409 status = state;
8410 mptsas_log(mpt, CE_NOTE,
8411 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8412 "for enclosure with handle 0x%x is now "
8413 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
8414 enchandle,
8415 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
8416 ? ", inactive" : ", active",
8417 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
8418 ? ", out of sync" : "",
8419 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
8420 ? ", quiesced" : "",
8421 status &
8422 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
8423 ? ", write cache enabled" : "",
8424 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
8425 ? ", capacity expansion target" : "");
8426 break;
8427
8428 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
8429 mptsas_log(mpt, CE_NOTE,
8430 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8431 "for enclosure with handle 0x%x is now %s\n",
8432 physdisknum, devhandle, slot, enchandle,
8433 state == MPI2_RAID_PD_STATE_OPTIMAL
8434 ? "optimal" :
8435 state == MPI2_RAID_PD_STATE_REBUILDING
8436 ? "rebuilding" :
8437 state == MPI2_RAID_PD_STATE_DEGRADED
8438 ? "degraded" :
8439 state == MPI2_RAID_PD_STATE_HOT_SPARE
8440 ? "a hot spare" :
8441 state == MPI2_RAID_PD_STATE_ONLINE
8442 ? "online" :
8443 state == MPI2_RAID_PD_STATE_OFFLINE
8444 ? "offline" :
8445 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
8446 ? "not compatible" :
8447 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
8448 ? "not configured" :
8449 "state unknown");
8450 break;
8451 }
8452 break;
8453 }
8454 default:
8455 NDBG20(("mptsas3%d: unknown event %x received",
8456 mpt->m_instance, event));
8457 break;
8458 }
8459
8460 /*
8461 * Return the reply frame to the free queue.
8462 */
8463 ddi_put32(mpt->m_acc_free_queue_hdl,
8464 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
8465 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
8466 DDI_DMA_SYNC_FORDEV);
8467 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
8468 mpt->m_free_index = 0;
8469 }
8470 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
8471 mpt->m_free_index);
8472 mutex_exit(&mpt->m_mutex);
8473 }
8474
8475 /*
8476 * invoked from timeout() to restart qfull cmds with throttle == 0
8477 */
8478 static void
8479 mptsas_restart_cmd(void *arg)
8480 {
8481 mptsas_t *mpt = arg;
8482 mptsas_target_t *ptgt = NULL;
8483
8484 mutex_enter(&mpt->m_mutex);
8485
8486 mpt->m_restart_cmd_timeid = 0;
8487
8488 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
8489 ptgt = refhash_next(mpt->m_targets, ptgt)) {
8490 mutex_enter(&ptgt->m_t_mutex);
8491 if (ptgt->m_reset_delay == 0) {
8492 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
8493 mptsas_set_throttle(mpt, ptgt,
8494 MAX_THROTTLE);
8495 }
8496 }
8497 mutex_exit(&ptgt->m_t_mutex);
8498 }
8499 mptsas_restart_hba(mpt);
8500 mutex_exit(&mpt->m_mutex);
8501 }
8502
8503 /*
8504 * Assume some checks have been done prior to calling this
8505 * function so we don't need to consider taking the m_mutex.
8506 */
8507 static void
8508 mptsas_remove_cmd_nomtx(mptsas_t *mpt, mptsas_cmd_t *cmd)
8509 {
8510 int slot;
8511 mptsas_slots_t *slots = mpt->m_active;
8512 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8513
8514 ASSERT(cmd != NULL);
8515 ASSERT(cmd->cmd_queued == FALSE);
8516 ASSERT((cmd->cmd_flags & CFLAG_CMDIOC) == 0);
8517
8518 slot = cmd->cmd_slot;
8519
8520 /*
8521 * remove the cmd.
8522 */
8523 if (cmd == slots->m_slot[slot]) {
8524 NDBG31(("mptsas_remove_cmd_nomtx: removing cmd=0x%p, flags "
8525 "0x%x", (void *)cmd, cmd->cmd_flags));
8526 slots->m_slot[slot] = NULL;
8527 ASSERT(mpt->m_ncmds != 0);
8528 atomic_dec_32(&mpt->m_ncmds);
8529 ASSERT(mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds != 0);
8530 atomic_dec_32(
8531 &mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds);
8532
8533 /*
8534 * Decrement per target ncmds, we know this is not an
8535 * IOC cmd and it therefore has a target associated with it.
8536 */
8537 mutex_enter(&ptgt->m_t_mutex);
8538 ASSERT(ptgt->m_t_ncmds != 0);
8539 ptgt->m_t_ncmds--;
8540
8541 /*
8542 * reset throttle if we just ran an untagged command
8543 * to a tagged target
8544 */
8545 if ((ptgt->m_t_ncmds == 0) &&
8546 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8547 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8548 }
8549
8550 /*
8551 * Remove this command from the active queue.
8552 */
8553 if (cmd->cmd_active_expiration != 0) {
8554 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd,
8555 cmd_active_link);
8556 cmd->cmd_active_expiration = 0;
8557 }
8558 mutex_exit(&ptgt->m_t_mutex);
8559 }
8560
8561 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8562 }
8563
8564 void
8565 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8566 {
8567 int slot;
8568 mptsas_slots_t *slots = mpt->m_active;
8569 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8570
8571 ASSERT(cmd != NULL);
8572 ASSERT(cmd->cmd_queued == FALSE);
8573
8574 /*
8575 * Task Management cmds are removed in their own routines. Also,
8576 * we don't want to modify timeout based on TM cmds.
8577 */
8578 if (cmd->cmd_flags & CFLAG_TM_CMD) {
8579 return;
8580 }
8581
8582 slot = cmd->cmd_slot;
8583
8584 /*
8585 * remove the cmd.
8586 */
8587 if (cmd == slots->m_slot[slot]) {
8588 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags 0x%x",
8589 (void *)cmd, cmd->cmd_flags));
8590 slots->m_slot[slot] = NULL;
8591 ASSERT(mpt->m_ncmds != 0);
8592 atomic_dec_32(&mpt->m_ncmds);
8593 ASSERT(mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds != 0);
8594 atomic_dec_32(
8595 &mpt->m_rep_post_queues[cmd->cmd_rpqidx].rpq_ncmds);
8596
8597 /*
8598 * only decrement per target ncmds if command
8599 * has a target associated with it.
8600 */
8601 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
8602 mutex_enter(&ptgt->m_t_mutex);
8603 ASSERT(ptgt->m_t_ncmds != 0);
8604 ptgt->m_t_ncmds--;
8605
8606 /*
8607 * reset throttle if we just ran an untagged command
8608 * to a tagged target
8609 */
8610 if ((ptgt->m_t_ncmds == 0) &&
8611 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8612 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8613 }
8614
8615 /*
8616 * Remove this command from the active queue.
8617 */
8618 if (cmd->cmd_active_expiration != 0) {
8619 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd,
8620 cmd_active_link);
8621 cmd->cmd_active_expiration = 0;
8622 }
8623 mutex_exit(&ptgt->m_t_mutex);
8624 }
8625
8626 }
8627
8628 /*
8629 * This is all we need to do for ioc commands.
8630 */
8631 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8632 mptsas_return_to_pool(mpt, cmd);
8633 return;
8634 }
8635
8636 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8637 }
8638
8639 /*
8640 * accept all cmds on the tx_waitq if any and then
8641 * start a fresh request from the top of the device queue.
8642 *
8643 * since there are always cmds queued on the tx_waitq, and rare cmds on
8644 * the instance waitq, so this function should not be invoked in the ISR,
8645 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
8646 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
8647 */
8648 static void
8649 mptsas_restart_hba(mptsas_t *mpt)
8650 {
8651 ASSERT(mutex_owned(&mpt->m_mutex));
8652
8653 mptsas_accept_tx_waitqs(mpt);
8654 mptsas_restart_waitq(mpt);
8655 }
8656
8657 /*
8658 * start a fresh request from the top of the device queue
8659 */
8660 static void
8661 mptsas_restart_waitq(mptsas_t *mpt)
8662 {
8663 mptsas_cmd_t *cmd, *next_cmd;
8664 mptsas_target_t *ptgt = NULL;
8665
8666 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
8667
8668 ASSERT(mutex_owned(&mpt->m_mutex));
8669
8670 /*
8671 * If there is a reset delay, don't start any cmds. Otherwise, start
8672 * as many cmds as possible.
8673 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
8674 * commands is m_max_requests - 2.
8675 */
8676 cmd = mpt->m_waitq;
8677
8678 while (cmd != NULL) {
8679 next_cmd = cmd->cmd_linkp;
8680 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
8681 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8682 /*
8683 * passthru command get slot need
8684 * set CFLAG_PREPARED.
8685 */
8686 cmd->cmd_flags |= CFLAG_PREPARED;
8687 mptsas_waitq_delete(mpt, cmd);
8688 mptsas_start_passthru(mpt, cmd);
8689 }
8690 cmd = next_cmd;
8691 continue;
8692 }
8693 if (cmd->cmd_flags & CFLAG_CONFIG) {
8694 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8695 /*
8696 * Send the config page request and delete it
8697 * from the waitq.
8698 */
8699 cmd->cmd_flags |= CFLAG_PREPARED;
8700 mptsas_waitq_delete(mpt, cmd);
8701 mptsas_start_config_page_access(mpt, cmd);
8702 }
8703 cmd = next_cmd;
8704 continue;
8705 }
8706 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
8707 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8708 /*
8709 * Send the FW Diag request and delete if from
8710 * the waitq.
8711 */
8712 cmd->cmd_flags |= CFLAG_PREPARED;
8713 mptsas_waitq_delete(mpt, cmd);
8714 mptsas_start_diag(mpt, cmd);
8715 }
8716 cmd = next_cmd;
8717 continue;
8718 }
8719
8720 ptgt = cmd->cmd_tgt_addr;
8721 if (ptgt) {
8722 mutex_enter(&ptgt->m_t_mutex);
8723 if ((ptgt->m_t_throttle == DRAIN_THROTTLE) &&
8724 (ptgt->m_t_ncmds == 0)) {
8725 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8726 }
8727 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
8728 (ptgt->m_reset_delay == 0) &&
8729 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
8730 mutex_exit(&ptgt->m_t_mutex);
8731
8732 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8733 mptsas_waitq_delete(mpt, cmd);
8734 mutex_exit(&mpt->m_mutex);
8735 (void) mptsas_start_cmd(mpt, cmd);
8736 mutex_enter(&mpt->m_mutex);
8737 cmd = mpt->m_waitq;
8738 continue;
8739 }
8740 } else {
8741 mutex_exit(&ptgt->m_t_mutex);
8742 }
8743 }
8744 cmd = next_cmd;
8745 }
8746 }
8747
8748 /*
8749 * Cmds are queued if scsi_start() doesn't get the m_mutex lock(no wait)
8750 * or if the decision has been made to always do that. Setting
8751 * mptsas_allow_txq_jumping to zero will allow higher performance on
8752 * a heavily loaded system as there is less disruption to the flow here.
8753 * There are 2 threads that handle one queue each. The idea is that
8754 * they take it in turn to grab the m_mutex to run the mptsas_accept_pkt()
8755 * function and then drop it while the cmd is started in mptsas_start_cmd().
8756 */
8757 static void
8758 mptsas_tx_waitq_thread(mptsas_thread_arg_t *arg)
8759 {
8760 mptsas_t *mpt = arg->mpt;
8761 mptsas_tx_waitqueue_t *txwq = &mpt->m_tx_waitq[arg->t];
8762
8763 mutex_enter(&txwq->txwq_mutex);
8764 while (txwq->txwq_active) {
8765 mptsas_drain_tx_waitq(mpt, txwq);
8766 if (txwq->txwq_wdrain) {
8767 cv_signal(&txwq->txwq_drain_cv);
8768 }
8769 cv_wait(&txwq->txwq_cv, &txwq->txwq_mutex);
8770 }
8771 mutex_exit(&txwq->txwq_mutex);
8772 mutex_enter(&mpt->m_qthread_mutex);
8773 mpt->m_txwq_thread_n--;
8774 cv_broadcast(&mpt->m_qthread_cv);
8775 mutex_exit(&mpt->m_qthread_mutex);
8776 }
8777
8778 /*
8779 * Set the draining flag, disconnect the list and process one at a time
8780 * so that the cmds are sent in order.
8781 */
8782 static void
8783 mptsas_drain_tx_waitq(mptsas_t *mpt, mptsas_tx_waitqueue_t *txwq)
8784 {
8785 mptsas_cmd_t *cmd, *ncmd;
8786 int rval, start;
8787 #ifdef MPTSAS_DEBUG
8788 uint32_t qlen;
8789 #endif
8790
8791 txwq->txwq_draining = TRUE;
8792 #ifndef __lock_lint
8793 _NOTE(CONSTCOND)
8794 #endif
8795 while (TRUE) {
8796
8797 /*
8798 * A Bus Reset could occur at any time but it will have to
8799 * wait for the main mutex before flushing the tx_waitq.
8800 * Pull all commands at once, then follow the list in order to
8801 * reduce txwq_mutex hold time. If there is a Bus Reset at
8802 * some point the commands will get to the waitq and then be
8803 * flushed.
8804 */
8805 cmd = txwq->txwq_cmdq;
8806
8807 if (cmd == NULL) {
8808 txwq->txwq_draining = FALSE;
8809 return;
8810 }
8811 txwq->txwq_cmdq = NULL;
8812 txwq->txwq_qtail = &txwq->txwq_cmdq;
8813 #ifdef MPTSAS_DEBUG
8814 qlen = txwq->txwq_len;
8815 #endif
8816 txwq->txwq_len = 0;
8817 mutex_exit(&txwq->txwq_mutex);
8818
8819 while (cmd) {
8820 ncmd = cmd->cmd_linkp;
8821 cmd->cmd_linkp = NULL;
8822 mutex_enter(&mpt->m_mutex);
8823 start = mptsas_accept_pkt(mpt, cmd, &rval);
8824 mutex_exit(&mpt->m_mutex);
8825 if (start) {
8826 (void) mptsas_start_cmd(mpt, cmd);
8827 }
8828 if (rval != TRAN_ACCEPT)
8829 cmn_err(CE_WARN,
8830 "mpt: mptsas_drain_tx_waitq: failed "
8831 "(rval=0x%x) to accept cmd 0x%p on queue\n",
8832 rval, (void *)cmd);
8833 cmd = ncmd;
8834 #ifdef MPTSAS_DEBUG
8835 qlen--;
8836 #endif
8837 }
8838 ASSERT(qlen == 0);
8839 mutex_enter(&txwq->txwq_mutex);
8840 }
8841 }
8842
8843 /*
8844 * Stop the drain threads from picking up a new list.
8845 * Optionally wait for the current list being processed to drain through.
8846 * Add to and processing the tx waitq is now on hold until unblock is called.
8847 */
8848 static void
8849 mptsas_block_tx_waitqs(mptsas_t *mpt, int wait)
8850 {
8851 int i;
8852 uint8_t wdrain = 0;
8853 mptsas_tx_waitqueue_t *txwq;
8854
8855 ASSERT(mutex_owned(&mpt->m_mutex));
8856
8857 if (mpt->m_txwq_thread_n == 0) {
8858 return;
8859 }
8860
8861 /*
8862 * Turn off the use of the tx wait queues by scsi_start().
8863 * This is just a dynamic flag no need for a mutex.
8864 */
8865 mpt->m_txwq_enabled = BLOCKED;
8866
8867 for (i = 0; i < NUM_TX_WAITQ; i++) {
8868 txwq = &mpt->m_tx_waitq[i];
8869 mutex_enter(&txwq->txwq_mutex);
8870 txwq->txwq_wdrain = TRUE;
8871 if (txwq->txwq_draining && wait)
8872 wdrain |= (1<<i);
8873 mutex_exit(&txwq->txwq_mutex);
8874 }
8875
8876 if (wdrain) {
8877 /*
8878 * Because the threads disconnect the entire queue each time
8879 * round in order to drain to completely drain we have to
8880 * drop the main mutex otherwise the drain threads get stuck.
8881 */
8882 mutex_exit(&mpt->m_mutex);
8883 for (i = 0; i < NUM_TX_WAITQ; i++) {
8884 if (wdrain & (1<<i)) {
8885 txwq = &mpt->m_tx_waitq[i];
8886 mutex_enter(&txwq->txwq_mutex);
8887 while (txwq->txwq_draining) {
8888 cv_wait(&txwq->txwq_drain_cv,
8889 &txwq->txwq_mutex);
8890 }
8891 mutex_exit(&txwq->txwq_mutex);
8892 }
8893 }
8894 mutex_enter(&mpt->m_mutex);
8895 }
8896 }
8897
8898 static void
8899 mptsas_unblock_tx_waitqs(mptsas_t *mpt)
8900 {
8901 int i;
8902 mptsas_tx_waitqueue_t *txwq;
8903
8904 if (mpt->m_txwq_thread_n == 0) {
8905 return;
8906 }
8907
8908 for (i = 0; i < NUM_TX_WAITQ; i++) {
8909 txwq = &mpt->m_tx_waitq[i];
8910 mutex_enter(&txwq->txwq_mutex);
8911 txwq->txwq_wdrain = FALSE;
8912 cv_signal(&txwq->txwq_cv);
8913 mutex_exit(&txwq->txwq_mutex);
8914 }
8915
8916 mpt->m_txwq_enabled = FALSE;
8917 }
8918
8919 static void
8920 mptsas_accept_tx_waitqs(mptsas_t *mpt)
8921 {
8922 /*
8923 * Block with drain and unblock will leave us in a state where
8924 * we have the main mutex, there is nothing on the tx wait queues
8925 * and they are not in use until watch notices high activity again.
8926 */
8927 mptsas_block_tx_waitqs(mpt, 1);
8928 mptsas_unblock_tx_waitqs(mpt);
8929 }
8930
8931 /*
8932 * mpt tag type lookup
8933 */
8934 static char mptsas_tag_lookup[] =
8935 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
8936
8937 static int
8938 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8939 {
8940 struct scsi_pkt *pkt = CMD2PKT(cmd);
8941 uint32_t control = 0;
8942 caddr_t mem, arsbuf;
8943 pMpi2SCSIIORequest_t io_request;
8944 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
8945 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
8946 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8947 uint16_t SMID, io_flags = 0, ars_size;
8948 uint8_t MSIidx;
8949 uint64_t request_desc;
8950 uint32_t ars_dmaaddrlow;
8951 mptsas_cmd_t *c;
8952
8953 NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd,
8954 cmd->cmd_flags));
8955
8956 /*
8957 * Set SMID and increment index. Rollover to 1 instead of 0 if index
8958 * is at the max. 0 is an invalid SMID, so we call the first index 1.
8959 */
8960 SMID = cmd->cmd_slot;
8961 MSIidx = cmd->cmd_rpqidx;
8962
8963 /*
8964 * It is possible for back to back device reset to
8965 * happen before the reset delay has expired. That's
8966 * ok, just let the device reset go out on the bus.
8967 */
8968 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8969 ASSERT(ptgt->m_reset_delay == 0);
8970 }
8971
8972 /*
8973 * if a non-tagged cmd is submitted to an active tagged target
8974 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8975 * to be untagged
8976 */
8977 mutex_enter(&ptgt->m_t_mutex);
8978 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8979 (ptgt->m_t_ncmds > 1) &&
8980 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8981 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8982 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8983 NDBG23(("target=%d, untagged cmd, start draining\n",
8984 ptgt->m_devhdl));
8985
8986 if (ptgt->m_reset_delay == 0) {
8987 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8988 }
8989 mutex_exit(&ptgt->m_t_mutex);
8990
8991 mutex_enter(&mpt->m_mutex);
8992 mptsas_remove_cmd(mpt, cmd);
8993 cmd->cmd_pkt_flags |= FLAG_HEAD;
8994 mptsas_waitq_add(mpt, cmd);
8995 mutex_exit(&mpt->m_mutex);
8996 } else {
8997 mutex_exit(&ptgt->m_t_mutex);
8998 }
8999 return (DDI_FAILURE);
9000 }
9001
9002 /*
9003 * Set correct tag bits.
9004 */
9005 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
9006 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
9007 FLAG_TAGMASK) >> 12)]) {
9008 case MSG_SIMPLE_QTAG:
9009 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
9010 break;
9011 case MSG_HEAD_QTAG:
9012 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
9013 break;
9014 case MSG_ORDERED_QTAG:
9015 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
9016 break;
9017 default:
9018 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
9019 break;
9020 }
9021 } else {
9022 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
9023 ptgt->m_t_throttle = 1;
9024 }
9025 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
9026 }
9027
9028 /*
9029 * Set timeout.
9030 */
9031 cmd->cmd_active_expiration =
9032 gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC;
9033
9034 c = TAILQ_FIRST(&ptgt->m_active_cmdq);
9035 if (c == NULL ||
9036 c->cmd_active_expiration < cmd->cmd_active_expiration) {
9037 /*
9038 * Common case is that this is the last pending expiration
9039 * (or queue is empty). Insert at head of the queue.
9040 */
9041 TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link);
9042 } else {
9043 /*
9044 * Queue is not empty and first element expires later than
9045 * this command. Search for element expiring sooner.
9046 */
9047 while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) {
9048 if (c->cmd_active_expiration <
9049 cmd->cmd_active_expiration) {
9050 TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link);
9051 break;
9052 }
9053 }
9054 if (c == NULL) {
9055 /*
9056 * No element found expiring sooner, append to
9057 * non-empty queue.
9058 */
9059 TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd,
9060 cmd_active_link);
9061 }
9062 }
9063
9064 mutex_exit(&ptgt->m_t_mutex);
9065
9066 if (cmd->cmd_pkt_flags & FLAG_TLR) {
9067 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
9068 }
9069
9070 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
9071 io_request = (pMpi2SCSIIORequest_t)mem;
9072 if (cmd->cmd_extrqslen != 0) {
9073 /*
9074 * Mapping of the buffer was done in mptsas_pkt_alloc_extern().
9075 * Calculate the DMA address with the same offset.
9076 */
9077 arsbuf = cmd->cmd_arq_buf;
9078 ars_size = cmd->cmd_extrqslen;
9079 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
9080 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
9081 0xffffffffull;
9082 } else {
9083 arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1));
9084 cmd->cmd_arq_buf = arsbuf;
9085 ars_size = mpt->m_req_sense_size;
9086 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
9087 (mpt->m_req_sense_size * (SMID-1))) &
9088 0xffffffffull;
9089 }
9090 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
9091 bzero(arsbuf, ars_size);
9092
9093 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
9094 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
9095 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
9096 MPI2_FUNCTION_SCSI_IO_REQUEST);
9097
9098 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
9099 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
9100
9101 io_flags = cmd->cmd_cdblen;
9102 if (mptsas3_use_fastpath &&
9103 ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) {
9104 io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH;
9105 request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
9106 } else {
9107 request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
9108 }
9109 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
9110 /*
9111 * setup the Scatter/Gather DMA list for this request
9112 */
9113 if (cmd->cmd_cookiec > 0) {
9114 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
9115 } else {
9116 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
9117 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
9118 MPI2_SGE_FLAGS_END_OF_BUFFER |
9119 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9120 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
9121 }
9122
9123 /*
9124 * save ARQ information
9125 */
9126 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
9127 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow);
9128
9129 ddi_put32(acc_hdl, &io_request->Control, control);
9130
9131 NDBG31(("starting message=%d(0x%p), with cmd=0x%p",
9132 SMID, (void *)io_request, (void *)cmd));
9133
9134 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
9135
9136 /*
9137 * Build request descriptor and write it to the request desc post reg.
9138 */
9139 request_desc |= (SMID << 16) + (MSIidx << 8);
9140 request_desc |= ((uint64_t)ptgt->m_devhdl << 48);
9141 MPTSAS_START_CMD(mpt, request_desc);
9142
9143 #if 0
9144 /* Is this of any benefit here, what is it going to catch? */
9145 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
9146 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
9147 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
9148 return (DDI_FAILURE);
9149 }
9150 #endif
9151 return (DDI_SUCCESS);
9152 }
9153
9154 /*
9155 * Select a helper thread to handle given doneq.
9156 * Note that we don't require to have the main m_mutex here, but worst case
9157 * is that we wont follow the thread rotation to the letter.
9158 * However must ensure we have the mutex that covers the source dlist when
9159 * we actually hand off.
9160 */
9161 static void
9162 mptsas_deliver_doneq_thread(mptsas_t *mpt, mptsas_done_list_t *dlist)
9163 {
9164 uint32_t t, i, j = mpt->m_doneq_next_thread;
9165 uint32_t min = 0xffffffff;
9166 mptsas_doneq_thread_list_t *item;
9167
9168 /*
9169 * No need to take indivudual list mutex's during the loop.
9170 * We are only reading values and the worst that will happen is that
9171 * we pick the wrong thread.
9172 */
9173 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
9174 item = &mpt->m_doneq_thread_id[j];
9175
9176 /*
9177 * If the completed command on help thread[i] less than
9178 * doneq_thread_threshold, then pick the thread[j]. Otherwise
9179 * pick a thread which has least completed command.
9180 */
9181 if (item->dlist.dl_len < mpt->m_doneq_thread_threshold) {
9182 t = j;
9183 break;
9184 }
9185 if (item->dlist.dl_len < min) {
9186 min = item->dlist.dl_len;
9187 t = j;
9188 }
9189 if (++j == mpt->m_doneq_thread_n) {
9190 j = 0;
9191 }
9192 }
9193 item = &mpt->m_doneq_thread_id[t];
9194 mutex_enter(&item->mutex);
9195 mptsas_doneq_mv(dlist, item);
9196 cv_signal(&item->cv);
9197 mutex_exit(&item->mutex);
9198
9199 /*
9200 * Next time start at the next thread.
9201 * This will minimize the potential of grabing a lock
9202 * for a thread that is busy, either on a very busy systems
9203 * or on one that is configured to do all command completion
9204 * processing through threads.
9205 */
9206 if (++t == mpt->m_doneq_thread_n) {
9207 t = 0;
9208 }
9209 mpt->m_doneq_next_thread = (uint16_t)t;
9210 }
9211
9212 /*
9213 * move one doneq to another.
9214 */
9215 static void
9216 mptsas_doneq_mv(mptsas_done_list_t *from, mptsas_doneq_thread_list_t *item)
9217 {
9218 mptsas_done_list_t *to = &item->dlist;
9219 mptsas_cmd_t *cmd;
9220
9221 if ((cmd = from->dl_q) != NULL) {
9222 *to->dl_tail = cmd;
9223 to->dl_tail = from->dl_tail;
9224 to->dl_len += from->dl_len;
9225 from->dl_q = NULL;
9226 from->dl_tail = &from->dl_q;
9227 from->dl_len = 0;
9228 }
9229 }
9230
9231 void
9232 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
9233 {
9234 struct scsi_pkt *pkt = CMD2PKT(cmd);
9235
9236 /* Check all acc and dma handles */
9237 if ((mptsas_check_acc_handle(mpt->m_datap) !=
9238 DDI_SUCCESS) ||
9239 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
9240 DDI_SUCCESS) ||
9241 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
9242 DDI_SUCCESS) ||
9243 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
9244 DDI_SUCCESS) ||
9245 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
9246 DDI_SUCCESS) ||
9247 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
9248 DDI_SUCCESS) ||
9249 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
9250 DDI_SUCCESS) ||
9251 (mptsas_check_acc_handle(mpt->m_config_handle) !=
9252 DDI_SUCCESS)) {
9253 ddi_fm_service_impact(mpt->m_dip,
9254 DDI_SERVICE_UNAFFECTED);
9255 ddi_fm_acc_err_clear(mpt->m_config_handle,
9256 DDI_FME_VER0);
9257 pkt->pkt_reason = CMD_TRAN_ERR;
9258 pkt->pkt_statistics = 0;
9259 }
9260 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
9261 DDI_SUCCESS) ||
9262 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
9263 DDI_SUCCESS) ||
9264 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
9265 DDI_SUCCESS) ||
9266 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
9267 DDI_SUCCESS) ||
9268 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
9269 DDI_SUCCESS) ||
9270 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
9271 DDI_SUCCESS)) {
9272 ddi_fm_service_impact(mpt->m_dip,
9273 DDI_SERVICE_UNAFFECTED);
9274 pkt->pkt_reason = CMD_TRAN_ERR;
9275 pkt->pkt_statistics = 0;
9276 }
9277 if (cmd->cmd_dmahandle &&
9278 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
9279 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
9280 pkt->pkt_reason = CMD_TRAN_ERR;
9281 pkt->pkt_statistics = 0;
9282 }
9283 if ((cmd->cmd_extra_frames &&
9284 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
9285 DDI_SUCCESS) ||
9286 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
9287 DDI_SUCCESS)))) {
9288 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
9289 pkt->pkt_reason = CMD_TRAN_ERR;
9290 pkt->pkt_statistics = 0;
9291 }
9292 }
9293
9294 /*
9295 * These routines manipulate the queue of commands that
9296 * are waiting for their completion routines to be called.
9297 * The queue is usually in FIFO order but on an MP system
9298 * it's possible for the completion routines to get out
9299 * of order. If that's a problem you need to add a global
9300 * mutex around the code that calls the completion routine
9301 * in the interrupt handler.
9302 */
9303 static void
9304 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
9305 {
9306 struct scsi_pkt *pkt = CMD2PKT(cmd);
9307
9308 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
9309
9310 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
9311 cmd->cmd_linkp = NULL;
9312 cmd->cmd_flags |= CFLAG_FINISHED;
9313 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
9314
9315 mptsas_fma_check(mpt, cmd);
9316
9317 /*
9318 * only add scsi pkts that have completion routines to
9319 * the doneq. no intr cmds do not have callbacks.
9320 */
9321 if (pkt && (pkt->pkt_comp)) {
9322 *mpt->m_dlist.dl_tail = cmd;
9323 mpt->m_dlist.dl_tail = &cmd->cmd_linkp;
9324 mpt->m_dlist.dl_len++;
9325 }
9326 }
9327
9328 static void
9329 mptsas_rpdoneq_add(mptsas_t *mpt, mptsas_reply_pqueue_t *rpqp,
9330 mptsas_cmd_t *cmd)
9331 {
9332 struct scsi_pkt *pkt = CMD2PKT(cmd);
9333
9334 NDBG31(("mptsas_rpdoneq_add: cmd=0x%p", (void *)cmd));
9335
9336 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
9337 cmd->cmd_linkp = NULL;
9338 cmd->cmd_flags |= CFLAG_FINISHED;
9339 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
9340
9341 mptsas_fma_check(mpt, cmd);
9342
9343 /*
9344 * only add scsi pkts that have completion routines to
9345 * the doneq. no intr cmds do not have callbacks.
9346 */
9347 if (pkt && (pkt->pkt_comp)) {
9348 *rpqp->rpq_dlist.dl_tail = cmd;
9349 rpqp->rpq_dlist.dl_tail = &cmd->cmd_linkp;
9350 rpqp->rpq_dlist.dl_len++;
9351 }
9352 }
9353
9354 static mptsas_cmd_t *
9355 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
9356 {
9357 mptsas_cmd_t *cmd;
9358 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
9359
9360 /* pop one off the done queue */
9361 if ((cmd = item->dlist.dl_q) != NULL) {
9362 /* if the queue is now empty fix the tail pointer */
9363 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
9364 if ((item->dlist.dl_q = cmd->cmd_linkp) == NULL) {
9365 item->dlist.dl_tail = &item->dlist.dl_q;
9366 }
9367 cmd->cmd_linkp = NULL;
9368 item->dlist.dl_len--;
9369 }
9370 return (cmd);
9371 }
9372
9373 static void
9374 mptsas_doneq_empty(mptsas_t *mpt)
9375 {
9376 if (mpt->m_dlist.dl_q) {
9377 mptsas_cmd_t *cmd, *next;
9378 struct scsi_pkt *pkt;
9379
9380 cmd = mpt->m_dlist.dl_q;
9381 mpt->m_dlist.dl_q = NULL;
9382 mpt->m_dlist.dl_tail = &mpt->m_dlist.dl_q;
9383 mpt->m_dlist.dl_len = 0;
9384
9385 mutex_exit(&mpt->m_mutex);
9386 /*
9387 * run the completion routines of all the
9388 * completed commands
9389 */
9390 while (cmd != NULL) {
9391 next = cmd->cmd_linkp;
9392 cmd->cmd_linkp = NULL;
9393 /* run this command's completion routine */
9394 cmd->cmd_flags |= CFLAG_COMPLETED;
9395 pkt = CMD2PKT(cmd);
9396 mptsas_pkt_comp(pkt, cmd);
9397 cmd = next;
9398 }
9399 mutex_enter(&mpt->m_mutex);
9400 }
9401 }
9402
9403 static void
9404 mptsas_rpdoneq_empty(mptsas_reply_pqueue_t *rpqp)
9405 {
9406 if (rpqp->rpq_dlist.dl_q) {
9407 mptsas_cmd_t *cmd, *next;
9408 struct scsi_pkt *pkt;
9409
9410 cmd = rpqp->rpq_dlist.dl_q;
9411 rpqp->rpq_dlist.dl_q = NULL;
9412 rpqp->rpq_dlist.dl_tail = &rpqp->rpq_dlist.dl_q;
9413 rpqp->rpq_dlist.dl_len = 0;
9414
9415 mutex_exit(&rpqp->rpq_mutex);
9416 /*
9417 * run the completion routines of all the
9418 * completed commands
9419 */
9420 while (cmd != NULL) {
9421 next = cmd->cmd_linkp;
9422 cmd->cmd_linkp = NULL;
9423 /* run this command's completion routine */
9424 cmd->cmd_flags |= CFLAG_COMPLETED;
9425 pkt = CMD2PKT(cmd);
9426 mptsas_pkt_comp(pkt, cmd);
9427 cmd = next;
9428 }
9429 mutex_enter(&rpqp->rpq_mutex);
9430 }
9431 }
9432
9433 /*
9434 * These routines manipulate the target's queue of pending requests
9435 */
9436 void
9437 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
9438 {
9439 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
9440 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
9441 cmd->cmd_queued = TRUE;
9442 if (ptgt)
9443 ptgt->m_t_nwait++;
9444 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
9445 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
9446 mpt->m_waitqtail = &cmd->cmd_linkp;
9447 }
9448 mpt->m_waitq = cmd;
9449 } else {
9450 cmd->cmd_linkp = NULL;
9451 *(mpt->m_waitqtail) = cmd;
9452 mpt->m_waitqtail = &cmd->cmd_linkp;
9453 }
9454 }
9455
9456 static mptsas_cmd_t *
9457 mptsas_waitq_rm(mptsas_t *mpt)
9458 {
9459 mptsas_cmd_t *cmd;
9460 mptsas_target_t *ptgt;
9461 NDBG7(("mptsas_waitq_rm"));
9462
9463 MPTSAS_WAITQ_RM(mpt, cmd);
9464
9465 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
9466 if (cmd) {
9467 ptgt = cmd->cmd_tgt_addr;
9468 if (ptgt) {
9469 ptgt->m_t_nwait--;
9470 ASSERT(ptgt->m_t_nwait >= 0);
9471 }
9472 }
9473 return (cmd);
9474 }
9475
9476 /*
9477 * remove specified cmd from the middle of the wait queue.
9478 */
9479 static void
9480 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
9481 {
9482 mptsas_cmd_t *prevp = mpt->m_waitq;
9483 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
9484
9485 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9486 (void *)mpt, (void *)cmd));
9487 if (ptgt) {
9488 ptgt->m_t_nwait--;
9489 ASSERT(ptgt->m_t_nwait >= 0);
9490 }
9491
9492 if (prevp == cmd) {
9493 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
9494 mpt->m_waitqtail = &mpt->m_waitq;
9495
9496 cmd->cmd_linkp = NULL;
9497 cmd->cmd_queued = FALSE;
9498 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9499 (void *)mpt, (void *)cmd));
9500 return;
9501 }
9502
9503 while (prevp != NULL) {
9504 if (prevp->cmd_linkp == cmd) {
9505 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
9506 mpt->m_waitqtail = &prevp->cmd_linkp;
9507
9508 cmd->cmd_linkp = NULL;
9509 cmd->cmd_queued = FALSE;
9510 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
9511 (void *)mpt, (void *)cmd));
9512 return;
9513 }
9514 prevp = prevp->cmd_linkp;
9515 }
9516 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
9517 }
9518
9519 /*
9520 * device and bus reset handling
9521 *
9522 * Notes:
9523 * - RESET_ALL: reset the controller
9524 * - RESET_TARGET: reset the target specified in scsi_address
9525 */
9526 static int
9527 mptsas_scsi_reset(struct scsi_address *ap, int level)
9528 {
9529 mptsas_t *mpt = ADDR2MPT(ap);
9530 int rval;
9531 mptsas_tgt_private_t *tgt_private;
9532 mptsas_target_t *ptgt = NULL;
9533
9534 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
9535 ptgt = tgt_private->t_private;
9536 if (ptgt == NULL) {
9537 return (FALSE);
9538 }
9539 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
9540 level));
9541
9542 mutex_enter(&mpt->m_mutex);
9543 /*
9544 * if we are not in panic set up a reset delay for this target
9545 */
9546 if (!ddi_in_panic()) {
9547 mptsas_setup_bus_reset_delay(mpt);
9548 } else {
9549 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
9550 }
9551 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
9552 mutex_exit(&mpt->m_mutex);
9553
9554 /*
9555 * The transport layer expect to only see TRUE and
9556 * FALSE. Therefore, we will adjust the return value
9557 * if mptsas_do_scsi_reset returns FAILED.
9558 */
9559 if (rval == FAILED)
9560 rval = FALSE;
9561 return (rval);
9562 }
9563
9564 static int
9565 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
9566 {
9567 int rval = FALSE;
9568 uint8_t config, disk;
9569
9570 ASSERT(mutex_owned(&mpt->m_mutex));
9571
9572 if (mptsas_debug_resets) {
9573 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
9574 devhdl);
9575 }
9576
9577 /*
9578 * Issue a Target Reset message to the target specified but not to a
9579 * disk making up a raid volume. Just look through the RAID config
9580 * Phys Disk list of DevHandles. If the target's DevHandle is in this
9581 * list, then don't reset this target.
9582 */
9583 for (config = 0; config < mpt->m_num_raid_configs; config++) {
9584 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
9585 if (devhdl == mpt->m_raidconfig[config].
9586 m_physdisk_devhdl[disk]) {
9587 return (TRUE);
9588 }
9589 }
9590 }
9591
9592 rval = mptsas_ioc_task_management(mpt,
9593 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
9594
9595 mptsas_doneq_empty(mpt);
9596 return (rval);
9597 }
9598
9599 static int
9600 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
9601 void (*callback)(caddr_t), caddr_t arg)
9602 {
9603 mptsas_t *mpt = ADDR2MPT(ap);
9604
9605 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
9606
9607 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
9608 &mpt->m_mutex, &mpt->m_reset_notify_listf));
9609 }
9610
9611 static int
9612 mptsas_get_name(struct scsi_device *sd, char *name, int len)
9613 {
9614 dev_info_t *lun_dip = NULL;
9615
9616 ASSERT(sd != NULL);
9617 ASSERT(name != NULL);
9618 lun_dip = sd->sd_dev;
9619 ASSERT(lun_dip != NULL);
9620
9621 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
9622 return (1);
9623 } else {
9624 return (0);
9625 }
9626 }
9627
9628 static int
9629 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
9630 {
9631 return (mptsas_get_name(sd, name, len));
9632 }
9633
9634 static void
9635 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9636 {
9637
9638 NDBG25(("mptsas_set_throttle: throttle=%x", what));
9639
9640 /*
9641 * if the bus is draining/quiesced, no changes to the throttles
9642 * are allowed. Not allowing change of throttles during draining
9643 * limits error recovery but will reduce draining time
9644 *
9645 * all throttles should have been set to HOLD_THROTTLE
9646 */
9647 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9648 return;
9649 }
9650
9651 if (what == HOLD_THROTTLE) {
9652 ptgt->m_t_throttle = HOLD_THROTTLE;
9653 } else if (ptgt->m_reset_delay == 0) {
9654 ptgt->m_t_throttle = what;
9655 }
9656 }
9657
9658 static void
9659 mptsas_set_throttle_mtx(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9660 {
9661 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9662 return;
9663 }
9664
9665 mutex_enter(&ptgt->m_t_mutex);
9666 mptsas_set_throttle(mpt, ptgt, what);
9667 mutex_exit(&ptgt->m_t_mutex);
9668 }
9669
9670 /*
9671 * Find all commands in the tx_waitq's for target and lun (if lun not -1),
9672 * remove them from the queues and return the linked list.
9673 */
9674 static mptsas_cmd_t *
9675 mptsas_strip_targetlun_from_txwqs(mptsas_t *mpt, ushort_t target, int lun)
9676 {
9677 mptsas_cmd_t *cmd, *clist, **tailp, **prev_tailp;
9678 mptsas_tx_waitqueue_t *txwq;
9679 int i;
9680
9681 clist = NULL;
9682 tailp = &clist;
9683
9684 for (i = 0; i < NUM_TX_WAITQ; i++) {
9685 txwq = &mpt->m_tx_waitq[i];
9686 mutex_enter(&txwq->txwq_mutex);
9687 prev_tailp = &txwq->txwq_cmdq;
9688 cmd = txwq->txwq_cmdq;
9689 while (cmd != NULL) {
9690 if (Tgt(cmd) == target &&
9691 (lun == -1 || (Lun(cmd) == lun))) {
9692 *prev_tailp = cmd->cmd_linkp;
9693 *tailp = cmd;
9694 tailp = &cmd->cmd_linkp;
9695 cmd = cmd->cmd_linkp;
9696 *tailp = NULL;
9697 } else {
9698 prev_tailp = &cmd->cmd_linkp;
9699 cmd = cmd->cmd_linkp;
9700 }
9701 }
9702 txwq->txwq_qtail = prev_tailp;
9703 mutex_exit(&txwq->txwq_mutex);
9704 }
9705 return (clist);
9706 }
9707
9708 /*
9709 * Clean up from a device reset.
9710 * For the case of target reset, this function clears the waitq of all
9711 * commands for a particular target. For the case of abort task set, this
9712 * function clears the waitq of all commonds for a particular target/lun.
9713 */
9714 static void
9715 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
9716 {
9717 mptsas_slots_t *slots = mpt->m_active;
9718 mptsas_cmd_t *cmd, *next_cmd;
9719 int slot;
9720 uchar_t reason;
9721 uint_t stat;
9722 hrtime_t timestamp;
9723
9724 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
9725
9726 timestamp = gethrtime();
9727
9728 /*
9729 * Make sure the I/O Controller has flushed all cmds
9730 * that are associated with this target for a target reset
9731 * and target/lun for abort task set.
9732 * Account for TM requests, which use the last SMID.
9733 */
9734 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9735 if ((cmd = slots->m_slot[slot]) == NULL)
9736 continue;
9737 reason = CMD_RESET;
9738 stat = STAT_DEV_RESET;
9739 switch (tasktype) {
9740 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9741 if (Tgt(cmd) == target) {
9742 if (cmd->cmd_active_expiration <= timestamp) {
9743 /*
9744 * When timeout requested, propagate
9745 * proper reason and statistics to
9746 * target drivers.
9747 */
9748 reason = CMD_TIMEOUT;
9749 stat |= STAT_TIMEOUT;
9750 }
9751 NDBG25(("mptsas_flush_target discovered non-"
9752 "NULL cmd in slot %d, tasktype 0x%x", slot,
9753 tasktype));
9754 mptsas_dump_cmd(mpt, cmd);
9755 mptsas_remove_cmd(mpt, cmd);
9756 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9757 mptsas_doneq_add(mpt, cmd);
9758 }
9759 break;
9760 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9761 reason = CMD_ABORTED;
9762 stat = STAT_ABORTED;
9763 /*FALLTHROUGH*/
9764 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9765 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9766 if (cmd->cmd_active_expiration <= timestamp) {
9767 stat |= STAT_TIMEOUT;
9768 }
9769
9770 NDBG25(("mptsas_flush_target discovered non-"
9771 "NULL cmd in slot %d, tasktype 0x%x", slot,
9772 tasktype));
9773 mptsas_dump_cmd(mpt, cmd);
9774 mptsas_remove_cmd(mpt, cmd);
9775 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9776 mptsas_doneq_add(mpt, cmd);
9777 }
9778 break;
9779 default:
9780 break;
9781 }
9782 }
9783
9784 /*
9785 * Flush the waitq and tx_waitq of this target's cmds
9786 */
9787 cmd = mpt->m_waitq;
9788
9789 reason = CMD_RESET;
9790 stat = STAT_DEV_RESET;
9791
9792 switch (tasktype) {
9793 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9794 while (cmd != NULL) {
9795 next_cmd = cmd->cmd_linkp;
9796 if (Tgt(cmd) == target) {
9797 mptsas_waitq_delete(mpt, cmd);
9798 mptsas_set_pkt_reason(mpt, cmd,
9799 reason, stat);
9800 mptsas_doneq_add(mpt, cmd);
9801 }
9802 cmd = next_cmd;
9803 }
9804 cmd = mptsas_strip_targetlun_from_txwqs(mpt, target, -1);
9805 while (cmd != NULL) {
9806 next_cmd = cmd->cmd_linkp;
9807 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9808 mptsas_doneq_add(mpt, cmd);
9809 cmd = next_cmd;
9810 }
9811 break;
9812 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9813 reason = CMD_ABORTED;
9814 stat = STAT_ABORTED;
9815 /*FALLTHROUGH*/
9816 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9817 while (cmd != NULL) {
9818 next_cmd = cmd->cmd_linkp;
9819 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9820 mptsas_waitq_delete(mpt, cmd);
9821 mptsas_set_pkt_reason(mpt, cmd,
9822 reason, stat);
9823 mptsas_doneq_add(mpt, cmd);
9824 }
9825 cmd = next_cmd;
9826 }
9827 cmd = mptsas_strip_targetlun_from_txwqs(mpt, target, lun);
9828 while (cmd != NULL) {
9829 next_cmd = cmd->cmd_linkp;
9830 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9831 mptsas_doneq_add(mpt, cmd);
9832 cmd = next_cmd;
9833 }
9834 break;
9835 default:
9836 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
9837 tasktype);
9838 break;
9839 }
9840 }
9841
9842 /*
9843 * Clean up hba state, abort all outstanding command and commands in waitq
9844 * reset timeout of all targets.
9845 */
9846 static void
9847 mptsas_flush_hba(mptsas_t *mpt)
9848 {
9849 mptsas_slots_t *slots = mpt->m_active;
9850 mptsas_cmd_t *cmd, *ncmd;
9851 int slot, i;
9852
9853 NDBG25(("mptsas_flush_hba"));
9854
9855 /*
9856 * The I/O Controller should have already sent back
9857 * all commands via the scsi I/O reply frame. Make
9858 * sure all commands have been flushed.
9859 * Account for TM request, which use the last SMID.
9860 */
9861 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9862 if ((cmd = slots->m_slot[slot]) == NULL)
9863 continue;
9864
9865 if (cmd->cmd_flags & CFLAG_CMDIOC) {
9866 /*
9867 * Need to make sure to tell everyone that might be
9868 * waiting on this command that it's going to fail. If
9869 * we get here, this command will never timeout because
9870 * the active command table is going to be re-allocated,
9871 * so there will be nothing to check against a time out.
9872 * Instead, mark the command as failed due to reset.
9873 */
9874 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9875 STAT_BUS_RESET);
9876 if ((cmd->cmd_flags &
9877 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
9878 cmd->cmd_flags |= CFLAG_FINISHED;
9879 cv_broadcast(&mpt->m_passthru_cv);
9880 cv_broadcast(&mpt->m_config_cv);
9881 cv_broadcast(&mpt->m_fw_diag_cv);
9882 }
9883 continue;
9884 }
9885
9886 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
9887 slot));
9888 mptsas_dump_cmd(mpt, cmd);
9889
9890 mptsas_remove_cmd(mpt, cmd);
9891 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9892 mptsas_doneq_add(mpt, cmd);
9893 }
9894
9895 /*
9896 * Flush the waitq.
9897 */
9898 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
9899 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9900 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9901 (cmd->cmd_flags & CFLAG_CONFIG) ||
9902 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9903 cmd->cmd_flags |= CFLAG_FINISHED;
9904 cv_broadcast(&mpt->m_passthru_cv);
9905 cv_broadcast(&mpt->m_config_cv);
9906 cv_broadcast(&mpt->m_fw_diag_cv);
9907 } else {
9908 mptsas_doneq_add(mpt, cmd);
9909 }
9910 }
9911
9912 /*
9913 * Flush the tx_waitqs
9914 */
9915 for (i = 0; i < NUM_TX_WAITQ; i++) {
9916 mutex_enter(&mpt->m_tx_waitq[i].txwq_mutex);
9917 cmd = mpt->m_tx_waitq[i].txwq_cmdq;
9918 mpt->m_tx_waitq[i].txwq_cmdq = NULL;
9919 mpt->m_tx_waitq[i].txwq_qtail = &mpt->m_tx_waitq[i].txwq_cmdq;
9920 mutex_exit(&mpt->m_tx_waitq[i].txwq_mutex);
9921 while (cmd != NULL) {
9922 ncmd = cmd->cmd_linkp;
9923 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9924 STAT_BUS_RESET);
9925 mptsas_doneq_add(mpt, cmd);
9926 cmd = ncmd;
9927 }
9928 }
9929
9930 /*
9931 * Drain the taskqs prior to reallocating resources.
9932 */
9933 mutex_exit(&mpt->m_mutex);
9934 ddi_taskq_wait(mpt->m_event_taskq);
9935 ddi_taskq_wait(mpt->m_dr_taskq);
9936 mutex_enter(&mpt->m_mutex);
9937 }
9938
9939 /*
9940 * set pkt_reason and OR in pkt_statistics flag
9941 */
9942 static void
9943 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
9944 uint_t stat)
9945 {
9946 #ifndef __lock_lint
9947 _NOTE(ARGUNUSED(mpt))
9948 #endif
9949
9950 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
9951 (void *)cmd, reason, stat));
9952
9953 if (cmd) {
9954 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
9955 cmd->cmd_pkt->pkt_reason = reason;
9956 }
9957 cmd->cmd_pkt->pkt_statistics |= stat;
9958 }
9959 }
9960
9961 static void
9962 mptsas_start_watch_reset_delay()
9963 {
9964 NDBG22(("mptsas_start_watch_reset_delay"));
9965
9966 mutex_enter(&mptsas_global_mutex);
9967 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
9968 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
9969 drv_usectohz((clock_t)
9970 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
9971 ASSERT(mptsas_reset_watch != NULL);
9972 }
9973 mutex_exit(&mptsas_global_mutex);
9974 }
9975
9976 static void
9977 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
9978 {
9979 mptsas_target_t *ptgt = NULL;
9980
9981 ASSERT(MUTEX_HELD(&mpt->m_mutex));
9982
9983 NDBG22(("mptsas_setup_bus_reset_delay"));
9984 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9985 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9986 mutex_enter(&ptgt->m_t_mutex);
9987 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9988 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
9989 mutex_exit(&ptgt->m_t_mutex);
9990 }
9991
9992 mptsas_start_watch_reset_delay();
9993 }
9994
9995 /*
9996 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
9997 * mpt instance for active reset delays
9998 */
9999 static void
10000 mptsas_watch_reset_delay(void *arg)
10001 {
10002 #ifndef __lock_lint
10003 _NOTE(ARGUNUSED(arg))
10004 #endif
10005
10006 mptsas_t *mpt;
10007 int not_done = 0;
10008
10009 NDBG22(("mptsas_watch_reset_delay"));
10010
10011 mutex_enter(&mptsas_global_mutex);
10012 mptsas_reset_watch = 0;
10013 mutex_exit(&mptsas_global_mutex);
10014 rw_enter(&mptsas_global_rwlock, RW_READER);
10015 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
10016 if (mpt->m_tran == 0) {
10017 continue;
10018 }
10019 mutex_enter(&mpt->m_mutex);
10020 not_done += mptsas_watch_reset_delay_subr(mpt);
10021 mutex_exit(&mpt->m_mutex);
10022 }
10023 rw_exit(&mptsas_global_rwlock);
10024
10025 if (not_done) {
10026 mptsas_start_watch_reset_delay();
10027 }
10028 }
10029
10030 static int
10031 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
10032 {
10033 int done = 0;
10034 int restart = 0;
10035 mptsas_target_t *ptgt = NULL;
10036
10037 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
10038
10039 ASSERT(mutex_owned(&mpt->m_mutex));
10040
10041 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10042 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10043 mutex_enter(&ptgt->m_t_mutex);
10044 if (ptgt->m_reset_delay != 0) {
10045 ptgt->m_reset_delay -=
10046 MPTSAS_WATCH_RESET_DELAY_TICK;
10047 if (ptgt->m_reset_delay <= 0) {
10048 ptgt->m_reset_delay = 0;
10049 mptsas_set_throttle(mpt, ptgt,
10050 MAX_THROTTLE);
10051 restart++;
10052 } else {
10053 done = -1;
10054 }
10055 }
10056 mutex_exit(&ptgt->m_t_mutex);
10057 }
10058
10059 if (restart > 0) {
10060 mptsas_restart_hba(mpt);
10061 }
10062 return (done);
10063 }
10064
10065 #ifdef MPTSAS_TEST
10066 static void
10067 mptsas_test_reset(mptsas_t *mpt, int target)
10068 {
10069 mptsas_target_t *ptgt = NULL;
10070
10071 if (mptsas_rtest == target) {
10072 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
10073 mptsas_rtest = -1;
10074 }
10075 if (mptsas_rtest == -1) {
10076 NDBG22(("mptsas_test_reset success"));
10077 }
10078 }
10079 }
10080 #endif
10081
10082 /*
10083 * abort handling:
10084 *
10085 * Notes:
10086 * - if pkt is not NULL, abort just that command
10087 * - if pkt is NULL, abort all outstanding commands for target
10088 */
10089 static int
10090 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
10091 {
10092 mptsas_t *mpt = ADDR2MPT(ap);
10093 int rval;
10094 mptsas_tgt_private_t *tgt_private;
10095 int target, lun;
10096
10097 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
10098 tran_tgt_private;
10099 ASSERT(tgt_private != NULL);
10100 target = tgt_private->t_private->m_devhdl;
10101 lun = tgt_private->t_lun;
10102
10103 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
10104
10105 mutex_enter(&mpt->m_mutex);
10106 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
10107 mutex_exit(&mpt->m_mutex);
10108 return (rval);
10109 }
10110
10111 static int
10112 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
10113 {
10114 mptsas_cmd_t *sp = NULL;
10115 mptsas_slots_t *slots = mpt->m_active;
10116 int rval = FALSE;
10117
10118 ASSERT(mutex_owned(&mpt->m_mutex));
10119
10120 /*
10121 * Abort the command pkt on the target/lun in ap. If pkt is
10122 * NULL, abort all outstanding commands on that target/lun.
10123 * If you can abort them, return 1, else return 0.
10124 * Each packet that's aborted should be sent back to the target
10125 * driver through the callback routine, with pkt_reason set to
10126 * CMD_ABORTED.
10127 *
10128 * abort cmd pkt on HBA hardware; clean out of outstanding
10129 * command lists, etc.
10130 */
10131 if (pkt != NULL) {
10132 /* abort the specified packet */
10133 sp = PKT2CMD(pkt);
10134
10135 if (sp->cmd_queued) {
10136 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
10137 (void *)sp));
10138 mptsas_waitq_delete(mpt, sp);
10139 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
10140 STAT_ABORTED);
10141 mptsas_doneq_add(mpt, sp);
10142 rval = TRUE;
10143 goto done;
10144 }
10145
10146 /*
10147 * Have mpt firmware abort this command
10148 */
10149
10150 if (slots->m_slot[sp->cmd_slot] != NULL) {
10151 rval = mptsas_ioc_task_management(mpt,
10152 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
10153 lun, NULL, 0, 0);
10154
10155 /*
10156 * The transport layer expects only TRUE and FALSE.
10157 * Therefore, if mptsas_ioc_task_management returns
10158 * FAILED we will return FALSE.
10159 */
10160 if (rval == FAILED)
10161 rval = FALSE;
10162 goto done;
10163 }
10164 }
10165
10166 /*
10167 * If pkt is NULL then abort task set
10168 */
10169 rval = mptsas_ioc_task_management(mpt,
10170 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
10171
10172 /*
10173 * The transport layer expects only TRUE and FALSE.
10174 * Therefore, if mptsas_ioc_task_management returns
10175 * FAILED we will return FALSE.
10176 */
10177 if (rval == FAILED)
10178 rval = FALSE;
10179
10180 #ifdef MPTSAS_TEST
10181 if (rval && mptsas_test_stop) {
10182 debug_enter("mptsas_do_scsi_abort");
10183 }
10184 #endif
10185
10186 done:
10187 mptsas_doneq_empty(mpt);
10188 return (rval);
10189 }
10190
10191 /*
10192 * capability handling:
10193 * (*tran_getcap). Get the capability named, and return its value.
10194 */
10195 static int
10196 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
10197 {
10198 mptsas_t *mpt = ADDR2MPT(ap);
10199 int ckey;
10200 int rval = FALSE;
10201
10202 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
10203 ap->a_target, cap, tgtonly));
10204
10205 mutex_enter(&mpt->m_mutex);
10206
10207 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
10208 mutex_exit(&mpt->m_mutex);
10209 return (UNDEFINED);
10210 }
10211
10212 switch (ckey) {
10213 case SCSI_CAP_DMA_MAX:
10214 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
10215 break;
10216 case SCSI_CAP_ARQ:
10217 rval = TRUE;
10218 break;
10219 case SCSI_CAP_MSG_OUT:
10220 case SCSI_CAP_PARITY:
10221 case SCSI_CAP_UNTAGGED_QING:
10222 rval = TRUE;
10223 break;
10224 case SCSI_CAP_TAGGED_QING:
10225 rval = TRUE;
10226 break;
10227 case SCSI_CAP_RESET_NOTIFICATION:
10228 rval = TRUE;
10229 break;
10230 case SCSI_CAP_LINKED_CMDS:
10231 rval = FALSE;
10232 break;
10233 case SCSI_CAP_QFULL_RETRIES:
10234 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
10235 tran_tgt_private))->t_private->m_qfull_retries;
10236 break;
10237 case SCSI_CAP_QFULL_RETRY_INTERVAL:
10238 rval = drv_hztousec(((mptsas_tgt_private_t *)
10239 (ap->a_hba_tran->tran_tgt_private))->
10240 t_private->m_qfull_retry_interval) / 1000;
10241 break;
10242 case SCSI_CAP_CDB_LEN:
10243 rval = CDB_GROUP4;
10244 break;
10245 case SCSI_CAP_INTERCONNECT_TYPE:
10246 rval = INTERCONNECT_SAS;
10247 break;
10248 case SCSI_CAP_TRAN_LAYER_RETRIES:
10249 if (mpt->m_ioc_capabilities &
10250 MPI2_IOCFACTS_CAPABILITY_TLR)
10251 rval = TRUE;
10252 else
10253 rval = FALSE;
10254 break;
10255 default:
10256 rval = UNDEFINED;
10257 break;
10258 }
10259
10260 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
10261
10262 mutex_exit(&mpt->m_mutex);
10263 return (rval);
10264 }
10265
10266 /*
10267 * (*tran_setcap). Set the capability named to the value given.
10268 */
10269 static int
10270 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
10271 {
10272 mptsas_t *mpt = ADDR2MPT(ap);
10273 mptsas_target_t *ptgt;
10274 int ckey;
10275 int rval = FALSE;
10276
10277 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
10278 ap->a_target, cap, value, tgtonly));
10279
10280 if (!tgtonly) {
10281 return (rval);
10282 }
10283
10284 mutex_enter(&mpt->m_mutex);
10285
10286 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
10287 mutex_exit(&mpt->m_mutex);
10288 return (UNDEFINED);
10289 }
10290
10291 switch (ckey) {
10292 case SCSI_CAP_DMA_MAX:
10293 case SCSI_CAP_MSG_OUT:
10294 case SCSI_CAP_PARITY:
10295 case SCSI_CAP_INITIATOR_ID:
10296 case SCSI_CAP_LINKED_CMDS:
10297 case SCSI_CAP_UNTAGGED_QING:
10298 case SCSI_CAP_RESET_NOTIFICATION:
10299 /*
10300 * None of these are settable via
10301 * the capability interface.
10302 */
10303 break;
10304 case SCSI_CAP_ARQ:
10305 /*
10306 * We cannot turn off arq so return false if asked to
10307 */
10308 if (value) {
10309 rval = TRUE;
10310 } else {
10311 rval = FALSE;
10312 }
10313 break;
10314 case SCSI_CAP_TAGGED_QING:
10315 ptgt = ((mptsas_tgt_private_t *)
10316 (ap->a_hba_tran->tran_tgt_private))->t_private;
10317 mptsas_set_throttle_mtx(mpt, ptgt, MAX_THROTTLE);
10318 rval = TRUE;
10319 break;
10320 case SCSI_CAP_QFULL_RETRIES:
10321 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
10322 t_private->m_qfull_retries = (uchar_t)value;
10323 rval = TRUE;
10324 break;
10325 case SCSI_CAP_QFULL_RETRY_INTERVAL:
10326 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
10327 t_private->m_qfull_retry_interval =
10328 drv_usectohz(value * 1000);
10329 rval = TRUE;
10330 break;
10331 default:
10332 rval = UNDEFINED;
10333 break;
10334 }
10335 mutex_exit(&mpt->m_mutex);
10336 return (rval);
10337 }
10338
10339 /*
10340 * Utility routine for mptsas_ifsetcap/ifgetcap
10341 */
10342 /*ARGSUSED*/
10343 static int
10344 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
10345 {
10346 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
10347
10348 if (!cap)
10349 return (FALSE);
10350
10351 *cidxp = scsi_hba_lookup_capstr(cap);
10352 return (TRUE);
10353 }
10354
10355 static int
10356 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
10357 {
10358 mptsas_slots_t *old_active = mpt->m_active;
10359 mptsas_slots_t *new_active;
10360 size_t size;
10361
10362 /*
10363 * if there are active commands, then we cannot
10364 * change size of active slots array.
10365 */
10366 ASSERT(mpt->m_ncmds == 0);
10367
10368 size = MPTSAS_SLOTS_SIZE(mpt);
10369 new_active = kmem_zalloc(size, flag);
10370 if (new_active == NULL) {
10371 NDBG1(("new active alloc failed"));
10372 return (-1);
10373 }
10374 /*
10375 * Since SMID 0 is reserved and the TM slot is reserved, the
10376 * number of slots that can be used at any one time is
10377 * m_max_requests - 2.
10378 */
10379 new_active->m_n_normal = (mpt->m_max_requests - 2);
10380 new_active->m_size = size;
10381 new_active->m_rotor = 1;
10382 if (old_active)
10383 mptsas_free_active_slots(mpt);
10384 mpt->m_active = new_active;
10385
10386 return (0);
10387 }
10388
10389 static void
10390 mptsas_free_active_slots(mptsas_t *mpt)
10391 {
10392 mptsas_slots_t *active = mpt->m_active;
10393 size_t size;
10394
10395 if (active == NULL)
10396 return;
10397 size = active->m_size;
10398 kmem_free(active, size);
10399 mpt->m_active = NULL;
10400 }
10401
10402 /*
10403 * Error logging, printing, and debug print routines.
10404 */
10405 static char *mptsas_label = "mpt_sas3";
10406
10407 /*PRINTFLIKE3*/
10408 void
10409 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
10410 {
10411 dev_info_t *dev;
10412 va_list ap;
10413
10414 if (mpt) {
10415 dev = mpt->m_dip;
10416 } else {
10417 dev = 0;
10418 }
10419
10420 mutex_enter(&mptsas_log_mutex);
10421
10422 va_start(ap, fmt);
10423 (void) vsprintf(mptsas_log_buf, fmt, ap);
10424 va_end(ap);
10425
10426 if (level == CE_CONT) {
10427 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
10428 } else {
10429 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
10430 }
10431
10432 mutex_exit(&mptsas_log_mutex);
10433 }
10434
10435 #ifdef MPTSAS_DEBUG
10436 /*
10437 * Use a circular buffer to log messages to private memory.
10438 * No mutexes, so there is the opportunity for this to miss lines.
10439 * But it's fast and does not hold up the proceedings too much.
10440 */
10441 static char mptsas_dbglog_bufs[32][256];
10442 static uint32_t mptsas_dbglog_idx = 1;
10443
10444 /*PRINTFLIKE1*/
10445 void
10446 mptsas_debug_log(char *fmt, ...)
10447 {
10448 va_list ap;
10449 uint32_t idx;
10450
10451 if (!mptsas_dbglog_idx) {
10452 return;
10453 }
10454 idx = (mptsas_dbglog_idx++) & 0x1f;
10455
10456 va_start(ap, fmt);
10457 (void) vsnprintf(mptsas_dbglog_bufs[idx],
10458 sizeof (mptsas_dbglog_bufs[0]), fmt, ap);
10459 va_end(ap);
10460 }
10461
10462 /*PRINTFLIKE1*/
10463 void
10464 mptsas_printf(char *fmt, ...)
10465 {
10466 dev_info_t *dev = 0;
10467 va_list ap;
10468
10469 mutex_enter(&mptsas_log_mutex);
10470
10471 va_start(ap, fmt);
10472 (void) vsprintf(mptsas_log_buf, fmt, ap);
10473 va_end(ap);
10474
10475 #ifdef PROM_PRINTF
10476 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
10477 #else
10478 scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf);
10479 #endif
10480 mutex_exit(&mptsas_log_mutex);
10481 }
10482 #endif
10483
10484 /*
10485 * timeout handling
10486 */
10487 static void
10488 mptsas_watch(void *arg)
10489 {
10490 #ifndef __lock_lint
10491 _NOTE(ARGUNUSED(arg))
10492 #endif
10493
10494 mptsas_t *mpt;
10495 uint32_t doorbell;
10496
10497 NDBG30(("mptsas_watch"));
10498
10499 rw_enter(&mptsas_global_rwlock, RW_READER);
10500 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
10501
10502 mutex_enter(&mpt->m_mutex);
10503
10504 /* Skip device if not powered on */
10505 if (mpt->m_options & MPTSAS_OPT_PM) {
10506 if (mpt->m_power_level == PM_LEVEL_D0) {
10507 (void) pm_busy_component(mpt->m_dip, 0);
10508 mpt->m_busy = 1;
10509 } else {
10510 mutex_exit(&mpt->m_mutex);
10511 continue;
10512 }
10513 }
10514
10515 /*
10516 * Check if controller is in a FAULT state. If so, reset it.
10517 */
10518 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
10519 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
10520 doorbell &= MPI2_DOORBELL_DATA_MASK;
10521 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
10522 "code: %04x", doorbell);
10523 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
10524 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10525 mptsas_log(mpt, CE_WARN, "Reset failed"
10526 "after fault was detected");
10527 }
10528 }
10529
10530 /*
10531 * For now, always call mptsas_watchsubr.
10532 */
10533 mptsas_watchsubr(mpt);
10534
10535 if (mpt->m_options & MPTSAS_OPT_PM) {
10536 mpt->m_busy = 0;
10537 (void) pm_idle_component(mpt->m_dip, 0);
10538 }
10539
10540 mutex_exit(&mpt->m_mutex);
10541 }
10542 rw_exit(&mptsas_global_rwlock);
10543
10544 mutex_enter(&mptsas_global_mutex);
10545 if (mptsas_timeouts_enabled)
10546 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
10547 mutex_exit(&mptsas_global_mutex);
10548 }
10549
10550 int mptsas_monitor_for_txwqs = 1;
10551 static void
10552 mptsas_watchsubr(mptsas_t *mpt)
10553 {
10554 int i;
10555 mptsas_cmd_t *cmd;
10556 mptsas_target_t *ptgt = NULL;
10557 hrtime_t timestamp = gethrtime();
10558 boolean_t restart_hba = B_FALSE;
10559
10560 ASSERT(MUTEX_HELD(&mpt->m_mutex));
10561
10562 NDBG30(("mptsas_watchsubr: mpt=0x%p, ncmds %d, nstarted %d",
10563 (void *)mpt, mpt->m_ncmds, mpt->m_ncstarted));
10564
10565 mpt->m_lncstarted = mpt->m_ncstarted;
10566 if (mpt->m_txwq_thread_n != 0 && mpt->m_txwq_enabled != BLOCKED &&
10567 mptsas_monitor_for_txwqs) {
10568 i = mpt->m_ncstarted/mptsas_scsi_watchdog_tick;
10569 if (i > mpt->m_txwq_thread_threshold) {
10570 mpt->m_txwq_enabled = TRUE;
10571 } else if (i < (mpt->m_txwq_thread_threshold>>1)) {
10572 mpt->m_txwq_enabled = FALSE;
10573 }
10574 }
10575 mpt->m_ncstarted = 0;
10576
10577 /*
10578 * Check for commands stuck in active slot
10579 * Account for TM requests, which use the last SMID.
10580 */
10581 for (i = 0; i <= mpt->m_active->m_n_normal; i++) {
10582 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
10583 if (cmd->cmd_active_expiration <= timestamp) {
10584 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
10585 /*
10586 * There seems to be a command stuck
10587 * in the active slot. Drain throttle.
10588 */
10589 ptgt = cmd->cmd_tgt_addr;
10590 mptsas_set_throttle_mtx(mpt, ptgt,
10591 DRAIN_THROTTLE);
10592 } else if (cmd->cmd_flags &
10593 (CFLAG_PASSTHRU | CFLAG_CONFIG |
10594 CFLAG_FW_DIAG)) {
10595 /*
10596 * passthrough command timeout
10597 */
10598 cmd->cmd_flags |= (CFLAG_FINISHED |
10599 CFLAG_TIMEOUT);
10600 cv_broadcast(&mpt->m_passthru_cv);
10601 cv_broadcast(&mpt->m_config_cv);
10602 cv_broadcast(&mpt->m_fw_diag_cv);
10603 }
10604 }
10605 }
10606 }
10607
10608 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10609 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10610 mutex_enter(&ptgt->m_t_mutex);
10611 /*
10612 * If we were draining due to a qfull condition,
10613 * go back to full throttle.
10614 */
10615 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
10616 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
10617 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
10618 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10619 restart_hba = B_TRUE;
10620 }
10621
10622 cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq);
10623 if (cmd != NULL) {
10624 if (cmd->cmd_active_expiration <= timestamp) {
10625 /*
10626 * Earliest command timeout expired.
10627 * Drain throttle.
10628 */
10629 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
10630
10631 /*
10632 * Check for remaining commands.
10633 */
10634 cmd = TAILQ_FIRST(&ptgt->m_active_cmdq);
10635 if (cmd->cmd_active_expiration > timestamp) {
10636 /*
10637 * Wait for remaining commands to
10638 * complete or time out.
10639 */
10640 NDBG23(("command timed out, "
10641 "pending drain"));
10642 } else {
10643 mutex_exit(&ptgt->m_t_mutex);
10644
10645 /*
10646 * All command timeouts expired.
10647 */
10648 mptsas_log(mpt, CE_NOTE,
10649 "Timeout of %d seconds "
10650 "expired with %d commands on "
10651 "target %d lun %d.",
10652 cmd->cmd_pkt->pkt_time,
10653 ptgt->m_t_ncmds,
10654 ptgt->m_devhdl, Lun(cmd));
10655
10656 mptsas_cmd_timeout(mpt, ptgt);
10657 continue;
10658 }
10659 } else if (cmd->cmd_active_expiration <= timestamp +
10660 (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) {
10661 NDBG23(("pending timeout"));
10662 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
10663 }
10664 }
10665 mutex_exit(&ptgt->m_t_mutex);
10666 }
10667 if (restart_hba == B_TRUE) {
10668 mptsas_restart_hba(mpt);
10669 }
10670 }
10671
10672 /*
10673 * timeout recovery
10674 */
10675 static void
10676 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt)
10677 {
10678 uint16_t devhdl;
10679 uint64_t sas_wwn;
10680 uint8_t phy;
10681 char wwn_str[MPTSAS_WWN_STRLEN];
10682
10683 devhdl = ptgt->m_devhdl;
10684 sas_wwn = ptgt->m_addr.mta_wwn;
10685 phy = ptgt->m_phynum;
10686 if (sas_wwn == 0) {
10687 (void) sprintf(wwn_str, "p%x", phy);
10688 } else {
10689 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
10690 }
10691
10692 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
10693 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
10694 "target %d %s, enclosure %u .", devhdl, wwn_str,
10695 ptgt->m_enclosure);
10696
10697 /*
10698 * Abort all outstanding commands on the device.
10699 */
10700 NDBG29(("mptsas_cmd_timeout: device reset"));
10701 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
10702 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
10703 "recovery failed!", devhdl);
10704 }
10705 }
10706
10707 /*
10708 * Device / Hotplug control
10709 */
10710 static int
10711 mptsas_scsi_quiesce(dev_info_t *dip)
10712 {
10713 mptsas_t *mpt;
10714 scsi_hba_tran_t *tran;
10715
10716 tran = ddi_get_driver_private(dip);
10717 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10718 return (-1);
10719
10720 return (mptsas_quiesce_bus(mpt));
10721 }
10722
10723 static int
10724 mptsas_scsi_unquiesce(dev_info_t *dip)
10725 {
10726 mptsas_t *mpt;
10727 scsi_hba_tran_t *tran;
10728
10729 tran = ddi_get_driver_private(dip);
10730 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10731 return (-1);
10732
10733 return (mptsas_unquiesce_bus(mpt));
10734 }
10735
10736 static int
10737 mptsas_quiesce_bus(mptsas_t *mpt)
10738 {
10739 mptsas_target_t *ptgt = NULL;
10740
10741 NDBG28(("mptsas_quiesce_bus"));
10742 mutex_enter(&mpt->m_mutex);
10743
10744 /* Set all the throttles to zero */
10745 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10746 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10747 mptsas_set_throttle_mtx(mpt, ptgt, HOLD_THROTTLE);
10748 }
10749
10750 /* If there are any outstanding commands in the queue */
10751 if (mpt->m_ncmds) {
10752 mpt->m_softstate |= MPTSAS_SS_DRAINING;
10753 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10754 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
10755 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
10756 /*
10757 * Quiesce has been interrupted
10758 */
10759 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10760 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10761 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10762 mptsas_set_throttle_mtx(mpt, ptgt,
10763 MAX_THROTTLE);
10764 }
10765 mptsas_restart_hba(mpt);
10766 if (mpt->m_quiesce_timeid != 0) {
10767 timeout_id_t tid = mpt->m_quiesce_timeid;
10768 mpt->m_quiesce_timeid = 0;
10769 mutex_exit(&mpt->m_mutex);
10770 (void) untimeout(tid);
10771 return (-1);
10772 }
10773 mutex_exit(&mpt->m_mutex);
10774 return (-1);
10775 } else {
10776 /* Bus has been quiesced */
10777 ASSERT(mpt->m_quiesce_timeid == 0);
10778 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10779 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
10780 mutex_exit(&mpt->m_mutex);
10781 return (0);
10782 }
10783 }
10784 /* Bus was not busy - QUIESCED */
10785 mutex_exit(&mpt->m_mutex);
10786
10787 return (0);
10788 }
10789
10790 static int
10791 mptsas_unquiesce_bus(mptsas_t *mpt)
10792 {
10793 mptsas_target_t *ptgt = NULL;
10794
10795 NDBG28(("mptsas_unquiesce_bus"));
10796 mutex_enter(&mpt->m_mutex);
10797 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
10798 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10799 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10800 mptsas_set_throttle_mtx(mpt, ptgt, MAX_THROTTLE);
10801 }
10802 mptsas_restart_hba(mpt);
10803 mutex_exit(&mpt->m_mutex);
10804 return (0);
10805 }
10806
10807 static void
10808 mptsas_ncmds_checkdrain(void *arg)
10809 {
10810 mptsas_t *mpt = arg;
10811 mptsas_target_t *ptgt = NULL;
10812
10813 mutex_enter(&mpt->m_mutex);
10814 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
10815 mpt->m_quiesce_timeid = 0;
10816 if (mpt->m_ncmds == 0) {
10817 /* Command queue has been drained */
10818 cv_signal(&mpt->m_cv);
10819 } else {
10820 /*
10821 * The throttle may have been reset because
10822 * of a SCSI bus reset
10823 */
10824 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10825 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10826 mptsas_set_throttle_mtx(mpt, ptgt,
10827 HOLD_THROTTLE);
10828 }
10829
10830 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10831 mpt, (MPTSAS_QUIESCE_TIMEOUT *
10832 drv_usectohz(1000000)));
10833 }
10834 }
10835 mutex_exit(&mpt->m_mutex);
10836 }
10837
10838 /*ARGSUSED*/
10839 static void
10840 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
10841 {
10842 int i;
10843 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
10844 char buf[128];
10845
10846 buf[0] = '\0';
10847 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
10848 Tgt(cmd), Lun(cmd)));
10849 (void) sprintf(&buf[0], "\tcdb=[");
10850 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
10851 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
10852 }
10853 (void) sprintf(&buf[strlen(buf)], " ]");
10854 NDBG25(("?%s\n", buf));
10855 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
10856 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
10857 cmd->cmd_pkt->pkt_state));
10858 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
10859 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
10860 }
10861
10862 static void
10863 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10864 pMpi2SGESimple64_t sgep)
10865 {
10866 uint32_t sge_flags;
10867 uint32_t data_size, dataout_size;
10868 ddi_dma_cookie_t data_cookie;
10869 ddi_dma_cookie_t dataout_cookie;
10870
10871 data_size = pt->data_size;
10872 dataout_size = pt->dataout_size;
10873 data_cookie = pt->data_cookie;
10874 dataout_cookie = pt->dataout_cookie;
10875
10876 if (dataout_size) {
10877 sge_flags = dataout_size |
10878 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10879 MPI2_SGE_FLAGS_END_OF_BUFFER |
10880 MPI2_SGE_FLAGS_HOST_TO_IOC |
10881 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10882 MPI2_SGE_FLAGS_SHIFT);
10883 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10884 ddi_put32(acc_hdl, &sgep->Address.Low,
10885 (uint32_t)(dataout_cookie.dmac_laddress & 0xffffffffull));
10886 ddi_put32(acc_hdl, &sgep->Address.High,
10887 (uint32_t)(dataout_cookie.dmac_laddress >> 32));
10888 sgep++;
10889 }
10890 sge_flags = data_size;
10891 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10892 MPI2_SGE_FLAGS_LAST_ELEMENT |
10893 MPI2_SGE_FLAGS_END_OF_BUFFER |
10894 MPI2_SGE_FLAGS_END_OF_LIST |
10895 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10896 MPI2_SGE_FLAGS_SHIFT);
10897 if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10898 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
10899 MPI2_SGE_FLAGS_SHIFT);
10900 } else {
10901 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
10902 MPI2_SGE_FLAGS_SHIFT);
10903 }
10904 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10905 ddi_put32(acc_hdl, &sgep->Address.Low,
10906 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull));
10907 ddi_put32(acc_hdl, &sgep->Address.High,
10908 (uint32_t)(data_cookie.dmac_laddress >> 32));
10909 }
10910
10911 static void
10912 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10913 pMpi2IeeeSgeSimple64_t ieeesgep)
10914 {
10915 uint8_t sge_flags;
10916 uint32_t data_size, dataout_size;
10917 ddi_dma_cookie_t data_cookie;
10918 ddi_dma_cookie_t dataout_cookie;
10919
10920 data_size = pt->data_size;
10921 dataout_size = pt->dataout_size;
10922 data_cookie = pt->data_cookie;
10923 dataout_cookie = pt->dataout_cookie;
10924
10925 sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
10926 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
10927 if (dataout_size) {
10928 ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size);
10929 ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10930 (uint32_t)(dataout_cookie.dmac_laddress &
10931 0xffffffffull));
10932 ddi_put32(acc_hdl, &ieeesgep->Address.High,
10933 (uint32_t)(dataout_cookie.dmac_laddress >> 32));
10934 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10935 ieeesgep++;
10936 }
10937 sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
10938 ddi_put32(acc_hdl, &ieeesgep->Length, data_size);
10939 ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10940 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull));
10941 ddi_put32(acc_hdl, &ieeesgep->Address.High,
10942 (uint32_t)(data_cookie.dmac_laddress >> 32));
10943 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10944 }
10945
10946 static void
10947 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
10948 {
10949 caddr_t memp;
10950 pMPI2RequestHeader_t request_hdrp;
10951 struct scsi_pkt *pkt = cmd->cmd_pkt;
10952 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
10953 uint32_t request_size;
10954 uint64_t request_desc = 0;
10955 uint64_t sense_bufp;
10956 uint8_t desc_type;
10957 uint8_t *request, function;
10958 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
10959 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
10960
10961 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10962
10963 request = pt->request;
10964 request_size = pt->request_size;
10965
10966 /*
10967 * Store the passthrough message in memory location
10968 * corresponding to our slot number
10969 */
10970 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot);
10971 request_hdrp = (pMPI2RequestHeader_t)memp;
10972 bzero(memp, mpt->m_req_frame_size);
10973
10974 bcopy(request, memp, request_size);
10975
10976 NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, "
10977 "size=%d, in %d, out %d", request_hdrp->Function,
10978 request_hdrp->MsgFlags, request_size,
10979 pt->data_size, pt->dataout_size));
10980
10981 /*
10982 * Add an SGE, even if the length is zero.
10983 */
10984 if (mpt->m_MPI25 && pt->simple == 0) {
10985 mptsas_passthru_ieee_sge(acc_hdl, pt,
10986 (pMpi2IeeeSgeSimple64_t)
10987 ((uint8_t *)request_hdrp + pt->sgl_offset));
10988 } else {
10989 mptsas_passthru_sge(acc_hdl, pt,
10990 (pMpi2SGESimple64_t)
10991 ((uint8_t *)request_hdrp + pt->sgl_offset));
10992 }
10993
10994 function = request_hdrp->Function;
10995 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10996 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10997 pMpi2SCSIIORequest_t scsi_io_req;
10998
10999 NDBG15(("mptsas_start_passthru: Is SCSI IO Req"));
11000 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
11001 /*
11002 * Put SGE for data and data_out buffer at the end of
11003 * scsi_io_request message header.(64 bytes in total)
11004 * Following above SGEs, the residual space will be
11005 * used by sense data.
11006 */
11007 ddi_put8(acc_hdl,
11008 &scsi_io_req->SenseBufferLength,
11009 (uint8_t)(request_size - 64));
11010
11011 sense_bufp = (uint32_t)(mpt->m_req_frame_dma_addr +
11012 (mpt->m_req_frame_size * cmd->cmd_slot) & 0xffffffffull);
11013 sense_bufp += 64;
11014 ddi_put32(acc_hdl,
11015 &scsi_io_req->SenseBufferLowAddress, sense_bufp);
11016
11017 /*
11018 * Set SGLOffset0 value
11019 */
11020 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
11021 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
11022
11023 /*
11024 * Setup descriptor info. RAID passthrough must use the
11025 * default request descriptor which is already set, so if this
11026 * is a SCSI IO request, change the descriptor to SCSI IO.
11027 */
11028 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
11029 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
11030 request_desc = (((uint64_t)ddi_get16(acc_hdl,
11031 &scsi_io_req->DevHandle)) << 48);
11032 }
11033 }
11034
11035 /*
11036 * We must wait till the message has been completed before
11037 * beginning the next message so we wait for this one to
11038 * finish.
11039 */
11040 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
11041 request_desc |= ((cmd->cmd_slot << 16) | desc_type);
11042 cmd->cmd_rfm = NULL;
11043 MPTSAS_START_CMD(mpt, request_desc);
11044 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
11045 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
11046 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11047 }
11048 }
11049
11050 typedef void (mps_pre_f)(mptsas_t *, mptsas_pt_request_t *);
11051 static mps_pre_f mpi_pre_ioc_facts;
11052 static mps_pre_f mpi_pre_port_facts;
11053 static mps_pre_f mpi_pre_fw_download;
11054 static mps_pre_f mpi_pre_fw_25_download;
11055 static mps_pre_f mpi_pre_fw_upload;
11056 static mps_pre_f mpi_pre_fw_25_upload;
11057 static mps_pre_f mpi_pre_sata_passthrough;
11058 static mps_pre_f mpi_pre_smp_passthrough;
11059 static mps_pre_f mpi_pre_config;
11060 static mps_pre_f mpi_pre_sas_io_unit_control;
11061 static mps_pre_f mpi_pre_scsi_io_req;
11062
11063 /*
11064 * Prepare the pt for a SAS2 FW_DOWNLOAD request.
11065 */
11066 static void
11067 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
11068 {
11069 pMpi2FWDownloadTCSGE_t tcsge;
11070 pMpi2FWDownloadRequest req;
11071
11072 /*
11073 * If SAS3, call separate function.
11074 */
11075 if (mpt->m_MPI25) {
11076 mpi_pre_fw_25_download(mpt, pt);
11077 return;
11078 }
11079
11080 /*
11081 * User requests should come in with the Transaction
11082 * context element where the SGL will go. Putting the
11083 * SGL after that seems to work, but don't really know
11084 * why. Other drivers tend to create an extra SGL and
11085 * refer to the TCE through that.
11086 */
11087 req = (pMpi2FWDownloadRequest)pt->request;
11088 tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL;
11089 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
11090 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
11091 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
11092 }
11093
11094 pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) +
11095 sizeof (*tcsge);
11096 if (pt->request_size != pt->sgl_offset)
11097 NDBG15(("mpi_pre_fw_download(): Incorrect req size, "
11098 "0x%x, should be 0x%x, dataoutsz 0x%x",
11099 (int)pt->request_size, (int)pt->sgl_offset,
11100 (int)pt->dataout_size));
11101 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY))
11102 NDBG15(("mpi_pre_fw_download(): Incorrect rep size, "
11103 "0x%x, should be 0x%x", pt->data_size,
11104 (int)sizeof (MPI2_FW_DOWNLOAD_REPLY)));
11105 }
11106
11107 /*
11108 * Prepare the pt for a SAS3 FW_DOWNLOAD request.
11109 */
11110 static void
11111 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
11112 {
11113 pMpi2FWDownloadTCSGE_t tcsge;
11114 pMpi2FWDownloadRequest req2;
11115 pMpi25FWDownloadRequest req25;
11116
11117 /*
11118 * User requests should come in with the Transaction
11119 * context element where the SGL will go. The new firmware
11120 * Doesn't use TCE and has space in the main request for
11121 * this information. So move to the right place.
11122 */
11123 req2 = (pMpi2FWDownloadRequest)pt->request;
11124 req25 = (pMpi25FWDownloadRequest)pt->request;
11125 tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL;
11126 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
11127 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
11128 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
11129 }
11130 req25->ImageOffset = tcsge->ImageOffset;
11131 req25->ImageSize = tcsge->ImageSize;
11132
11133 pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL);
11134 if (pt->request_size != pt->sgl_offset)
11135 NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, "
11136 "0x%x, should be 0x%x, dataoutsz 0x%x",
11137 pt->request_size, pt->sgl_offset,
11138 pt->dataout_size));
11139 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY))
11140 NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, "
11141 "0x%x, should be 0x%x", pt->data_size,
11142 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
11143 }
11144
11145 /*
11146 * Prepare the pt for a SAS2 FW_UPLOAD request.
11147 */
11148 static void
11149 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
11150 {
11151 pMpi2FWUploadTCSGE_t tcsge;
11152 pMpi2FWUploadRequest_t req;
11153
11154 /*
11155 * If SAS3, call separate function.
11156 */
11157 if (mpt->m_MPI25) {
11158 mpi_pre_fw_25_upload(mpt, pt);
11159 return;
11160 }
11161
11162 /*
11163 * User requests should come in with the Transaction
11164 * context element where the SGL will go. Putting the
11165 * SGL after that seems to work, but don't really know
11166 * why. Other drivers tend to create an extra SGL and
11167 * refer to the TCE through that.
11168 */
11169 req = (pMpi2FWUploadRequest_t)pt->request;
11170 tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL;
11171 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
11172 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
11173 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
11174 }
11175
11176 pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) +
11177 sizeof (*tcsge);
11178 if (pt->request_size != pt->sgl_offset)
11179 NDBG15(("mpi_pre_fw_upload(): Incorrect req size, "
11180 "0x%x, should be 0x%x, dataoutsz 0x%x",
11181 pt->request_size, pt->sgl_offset,
11182 pt->dataout_size));
11183 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY))
11184 NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, "
11185 "0x%x, should be 0x%x", pt->data_size,
11186 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
11187 }
11188
11189 /*
11190 * Prepare the pt a SAS3 FW_UPLOAD request.
11191 */
11192 static void
11193 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
11194 {
11195 pMpi2FWUploadTCSGE_t tcsge;
11196 pMpi2FWUploadRequest_t req2;
11197 pMpi25FWUploadRequest_t req25;
11198
11199 /*
11200 * User requests should come in with the Transaction
11201 * context element where the SGL will go. The new firmware
11202 * Doesn't use TCE and has space in the main request for
11203 * this information. So move to the right place.
11204 */
11205 req2 = (pMpi2FWUploadRequest_t)pt->request;
11206 req25 = (pMpi25FWUploadRequest_t)pt->request;
11207 tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL;
11208 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
11209 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
11210 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
11211 }
11212 req25->ImageOffset = tcsge->ImageOffset;
11213 req25->ImageSize = tcsge->ImageSize;
11214
11215 pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL);
11216 if (pt->request_size != pt->sgl_offset)
11217 NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, "
11218 "0x%x, should be 0x%x, dataoutsz 0x%x",
11219 pt->request_size, pt->sgl_offset,
11220 pt->dataout_size));
11221 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY))
11222 NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, "
11223 "0x%x, should be 0x%x", pt->data_size,
11224 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
11225 }
11226
11227 /*
11228 * Prepare the pt for an IOC_FACTS request.
11229 */
11230 static void
11231 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
11232 {
11233 #ifndef __lock_lint
11234 _NOTE(ARGUNUSED(mpt))
11235 #endif
11236 if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST))
11237 NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, "
11238 "0x%x, should be 0x%x, dataoutsz 0x%x",
11239 pt->request_size,
11240 (int)sizeof (MPI2_IOC_FACTS_REQUEST),
11241 pt->dataout_size));
11242 if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY))
11243 NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, "
11244 "0x%x, should be 0x%x", pt->data_size,
11245 (int)sizeof (MPI2_IOC_FACTS_REPLY)));
11246 pt->sgl_offset = (uint16_t)pt->request_size;
11247 }
11248
11249 /*
11250 * Prepare the pt for a PORT_FACTS request.
11251 */
11252 static void
11253 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
11254 {
11255 #ifndef __lock_lint
11256 _NOTE(ARGUNUSED(mpt))
11257 #endif
11258 if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST))
11259 NDBG15(("mpi_pre_port_facts(): Incorrect req size, "
11260 "0x%x, should be 0x%x, dataoutsz 0x%x",
11261 pt->request_size,
11262 (int)sizeof (MPI2_PORT_FACTS_REQUEST),
11263 pt->dataout_size));
11264 if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY))
11265 NDBG15(("mpi_pre_port_facts(): Incorrect rep size, "
11266 "0x%x, should be 0x%x", pt->data_size,
11267 (int)sizeof (MPI2_PORT_FACTS_REPLY)));
11268 pt->sgl_offset = (uint16_t)pt->request_size;
11269 }
11270
11271 /*
11272 * Prepare pt for a SATA_PASSTHROUGH request.
11273 */
11274 static void
11275 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
11276 {
11277 #ifndef __lock_lint
11278 _NOTE(ARGUNUSED(mpt))
11279 #endif
11280 pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL);
11281 if (pt->request_size != pt->sgl_offset)
11282 NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, "
11283 "0x%x, should be 0x%x, dataoutsz 0x%x",
11284 pt->request_size, pt->sgl_offset,
11285 pt->dataout_size));
11286 if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY))
11287 NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, "
11288 "0x%x, should be 0x%x", pt->data_size,
11289 (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY)));
11290 }
11291
11292 static void
11293 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
11294 {
11295 #ifndef __lock_lint
11296 _NOTE(ARGUNUSED(mpt))
11297 #endif
11298 pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL);
11299 if (pt->request_size != pt->sgl_offset)
11300 NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, "
11301 "0x%x, should be 0x%x, dataoutsz 0x%x",
11302 pt->request_size, pt->sgl_offset,
11303 pt->dataout_size));
11304 if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY))
11305 NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, "
11306 "0x%x, should be 0x%x", pt->data_size,
11307 (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY)));
11308 }
11309
11310 /*
11311 * Prepare pt for a CONFIG request.
11312 */
11313 static void
11314 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt)
11315 {
11316 #ifndef __lock_lint
11317 _NOTE(ARGUNUSED(mpt))
11318 #endif
11319 pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE);
11320 if (pt->request_size != pt->sgl_offset)
11321 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
11322 "should be 0x%x, dataoutsz 0x%x", pt->request_size,
11323 pt->sgl_offset, pt->dataout_size));
11324 if (pt->data_size != sizeof (MPI2_CONFIG_REPLY))
11325 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
11326 "should be 0x%x", pt->data_size,
11327 (int)sizeof (MPI2_CONFIG_REPLY)));
11328 pt->simple = 1;
11329 }
11330
11331 /*
11332 * Prepare pt for a SCSI_IO_REQ request.
11333 */
11334 static void
11335 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt)
11336 {
11337 #ifndef __lock_lint
11338 _NOTE(ARGUNUSED(mpt))
11339 #endif
11340 pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL);
11341 if (pt->request_size != pt->sgl_offset)
11342 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
11343 "should be 0x%x, dataoutsz 0x%x", pt->request_size,
11344 pt->sgl_offset,
11345 pt->dataout_size));
11346 if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY))
11347 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
11348 "should be 0x%x", pt->data_size,
11349 (int)sizeof (MPI2_SCSI_IO_REPLY)));
11350 }
11351
11352 /*
11353 * Prepare the mps_command for a SAS_IO_UNIT_CONTROL request.
11354 */
11355 static void
11356 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt)
11357 {
11358 #ifndef __lock_lint
11359 _NOTE(ARGUNUSED(mpt))
11360 #endif
11361 pt->sgl_offset = (uint16_t)pt->request_size;
11362 }
11363
11364 /*
11365 * A set of functions to prepare an mps_command for the various
11366 * supported requests.
11367 */
11368 struct mps_func {
11369 U8 Function;
11370 char *Name;
11371 mps_pre_f *f_pre;
11372 } mps_func_list[] = {
11373 { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts },
11374 { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts },
11375 { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download },
11376 { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload },
11377 { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH",
11378 mpi_pre_sata_passthrough },
11379 { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH",
11380 mpi_pre_smp_passthrough},
11381 { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST",
11382 mpi_pre_scsi_io_req},
11383 { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config},
11384 { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL",
11385 mpi_pre_sas_io_unit_control },
11386 { 0xFF, NULL, NULL } /* list end */
11387 };
11388
11389 static void
11390 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt)
11391 {
11392 pMPI2RequestHeader_t hdr;
11393 struct mps_func *f;
11394
11395 hdr = (pMPI2RequestHeader_t)pt->request;
11396
11397 for (f = mps_func_list; f->f_pre != NULL; f++) {
11398 if (hdr->Function == f->Function) {
11399 f->f_pre(mpt, pt);
11400 NDBG15(("mptsas_prep_sgl_offset: Function %s,"
11401 " sgl_offset 0x%x", f->Name,
11402 pt->sgl_offset));
11403 return;
11404 }
11405 }
11406 NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x,"
11407 " returning req_size 0x%x for sgl_offset",
11408 hdr->Function, pt->request_size));
11409 pt->sgl_offset = (uint16_t)pt->request_size;
11410 }
11411
11412
11413 static int
11414 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
11415 uint8_t *data, uint32_t request_size, uint32_t reply_size,
11416 uint32_t data_size, uint8_t direction, uint8_t *dataout,
11417 uint32_t dataout_size, short timeout, int mode)
11418 {
11419 mptsas_pt_request_t pt;
11420 mptsas_dma_alloc_state_t data_dma_state;
11421 mptsas_dma_alloc_state_t dataout_dma_state;
11422 caddr_t memp;
11423 mptsas_cmd_t *cmd = NULL;
11424 struct scsi_pkt *pkt;
11425 uint32_t reply_len = 0, sense_len = 0;
11426 pMPI2RequestHeader_t request_hdrp;
11427 pMPI2RequestHeader_t request_msg;
11428 pMPI2DefaultReply_t reply_msg;
11429 Mpi2SCSIIOReply_t rep_msg;
11430 int i, status = 0, pt_flags = 0, rv = 0;
11431 int rvalue;
11432 uint8_t function;
11433
11434 ASSERT(mutex_owned(&mpt->m_mutex));
11435
11436 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
11437 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
11438 request_msg = kmem_zalloc(request_size, KM_SLEEP);
11439
11440 mutex_exit(&mpt->m_mutex);
11441 /*
11442 * copy in the request buffer since it could be used by
11443 * another thread when the pt request into waitq
11444 */
11445 if (ddi_copyin(request, request_msg, request_size, mode)) {
11446 mutex_enter(&mpt->m_mutex);
11447 status = EFAULT;
11448 mptsas_log(mpt, CE_WARN, "failed to copy request data");
11449 goto out;
11450 }
11451 mutex_enter(&mpt->m_mutex);
11452
11453 function = request_msg->Function;
11454 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
11455 pMpi2SCSITaskManagementRequest_t task;
11456 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
11457 mptsas_setup_bus_reset_delay(mpt);
11458 rv = mptsas_ioc_task_management(mpt, task->TaskType,
11459 task->DevHandle, (int)task->LUN[1], reply, reply_size,
11460 mode);
11461
11462 if (rv != TRUE) {
11463 status = EIO;
11464 mptsas_log(mpt, CE_WARN, "task management failed");
11465 }
11466 goto out;
11467 }
11468
11469 if (data_size != 0) {
11470 data_dma_state.size = data_size;
11471 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
11472 status = ENOMEM;
11473 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
11474 "resource");
11475 goto out;
11476 }
11477 pt_flags |= MPTSAS_DATA_ALLOCATED;
11478 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
11479 mutex_exit(&mpt->m_mutex);
11480 for (i = 0; i < data_size; i++) {
11481 if (ddi_copyin(data + i, (uint8_t *)
11482 data_dma_state.memp + i, 1, mode)) {
11483 mutex_enter(&mpt->m_mutex);
11484 status = EFAULT;
11485 mptsas_log(mpt, CE_WARN, "failed to "
11486 "copy read data");
11487 goto out;
11488 }
11489 }
11490 mutex_enter(&mpt->m_mutex);
11491 }
11492 }
11493 else
11494 bzero(&data_dma_state, sizeof (data_dma_state));
11495
11496 if (dataout_size != 0) {
11497 dataout_dma_state.size = dataout_size;
11498 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
11499 status = ENOMEM;
11500 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
11501 "resource");
11502 goto out;
11503 }
11504 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
11505 mutex_exit(&mpt->m_mutex);
11506 for (i = 0; i < dataout_size; i++) {
11507 if (ddi_copyin(dataout + i, (uint8_t *)
11508 dataout_dma_state.memp + i, 1, mode)) {
11509 mutex_enter(&mpt->m_mutex);
11510 mptsas_log(mpt, CE_WARN, "failed to copy out"
11511 " data");
11512 status = EFAULT;
11513 goto out;
11514 }
11515 }
11516 mutex_enter(&mpt->m_mutex);
11517 }
11518 else
11519 bzero(&dataout_dma_state, sizeof (dataout_dma_state));
11520
11521 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11522 status = EAGAIN;
11523 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
11524 goto out;
11525 }
11526 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
11527
11528 bzero((caddr_t)cmd, sizeof (*cmd));
11529 bzero((caddr_t)pkt, scsi_pkt_size());
11530 bzero((caddr_t)&pt, sizeof (pt));
11531
11532 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
11533
11534 pt.request = (uint8_t *)request_msg;
11535 pt.direction = direction;
11536 pt.simple = 0;
11537 pt.request_size = request_size;
11538 pt.data_size = data_size;
11539 pt.dataout_size = dataout_size;
11540 pt.data_cookie = data_dma_state.cookie;
11541 pt.dataout_cookie = dataout_dma_state.cookie;
11542 mptsas_prep_sgl_offset(mpt, &pt);
11543
11544 /*
11545 * Form a blank cmd/pkt to store the acknowledgement message
11546 */
11547 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
11548 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
11549 pkt->pkt_ha_private = (opaque_t)&pt;
11550 pkt->pkt_flags = FLAG_HEAD;
11551 pkt->pkt_time = timeout;
11552 cmd->cmd_pkt = pkt;
11553 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
11554
11555 /*
11556 * Save the command in a slot
11557 */
11558 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11559 /*
11560 * Once passthru command get slot, set cmd_flags
11561 * CFLAG_PREPARED.
11562 */
11563 cmd->cmd_flags |= CFLAG_PREPARED;
11564 mptsas_start_passthru(mpt, cmd);
11565 } else {
11566 mptsas_waitq_add(mpt, cmd);
11567 }
11568
11569 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11570 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
11571 }
11572
11573 if (cmd->cmd_flags & CFLAG_PREPARED) {
11574 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
11575 cmd->cmd_slot);
11576 request_hdrp = (pMPI2RequestHeader_t)memp;
11577 }
11578
11579 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11580 status = ETIMEDOUT;
11581 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
11582 pt_flags |= MPTSAS_CMD_TIMEOUT;
11583 goto out;
11584 }
11585
11586 if (cmd->cmd_rfm) {
11587 /*
11588 * cmd_rfm is zero means the command reply is a CONTEXT
11589 * reply and no PCI Write to post the free reply SMFA
11590 * because no reply message frame is used.
11591 * cmd_rfm is non-zero means the reply is a ADDRESS
11592 * reply and reply message frame is used.
11593 */
11594 pt_flags |= MPTSAS_ADDRESS_REPLY;
11595 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11596 DDI_DMA_SYNC_FORCPU);
11597 reply_msg = (pMPI2DefaultReply_t)
11598 (mpt->m_reply_frame + (cmd->cmd_rfm -
11599 (mpt->m_reply_frame_dma_addr&0xfffffffful)));
11600 }
11601
11602 mptsas_fma_check(mpt, cmd);
11603 if (pkt->pkt_reason == CMD_TRAN_ERR) {
11604 status = EAGAIN;
11605 mptsas_log(mpt, CE_WARN, "passthru fma error");
11606 goto out;
11607 }
11608 if (pkt->pkt_reason == CMD_RESET) {
11609 status = EAGAIN;
11610 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
11611 goto out;
11612 }
11613
11614 if (pkt->pkt_reason == CMD_INCOMPLETE) {
11615 status = EIO;
11616 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
11617 goto out;
11618 }
11619
11620 mutex_exit(&mpt->m_mutex);
11621 if (cmd->cmd_flags & CFLAG_PREPARED) {
11622 function = request_hdrp->Function;
11623 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
11624 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
11625 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
11626 sense_len = reply_size - reply_len;
11627 } else {
11628 reply_len = reply_size;
11629 sense_len = 0;
11630 }
11631
11632 for (i = 0; i < reply_len; i++) {
11633 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
11634 mode)) {
11635 mutex_enter(&mpt->m_mutex);
11636 status = EFAULT;
11637 mptsas_log(mpt, CE_WARN, "failed to copy out "
11638 "reply data");
11639 goto out;
11640 }
11641 }
11642 for (i = 0; i < sense_len; i++) {
11643 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
11644 reply + reply_len + i, 1, mode)) {
11645 mutex_enter(&mpt->m_mutex);
11646 status = EFAULT;
11647 mptsas_log(mpt, CE_WARN, "failed to copy out "
11648 "sense data");
11649 goto out;
11650 }
11651 }
11652 }
11653
11654 if (data_size) {
11655 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
11656 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
11657 DDI_DMA_SYNC_FORCPU);
11658 for (i = 0; i < data_size; i++) {
11659 if (ddi_copyout((uint8_t *)(
11660 data_dma_state.memp + i), data + i, 1,
11661 mode)) {
11662 mutex_enter(&mpt->m_mutex);
11663 status = EFAULT;
11664 mptsas_log(mpt, CE_WARN, "failed to "
11665 "copy out the reply data");
11666 goto out;
11667 }
11668 }
11669 }
11670 }
11671 mutex_enter(&mpt->m_mutex);
11672 out:
11673 /*
11674 * Put the reply frame back on the free queue, increment the free
11675 * index, and write the new index to the free index register. But only
11676 * if this reply is an ADDRESS reply.
11677 */
11678 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
11679 ddi_put32(mpt->m_acc_free_queue_hdl,
11680 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11681 cmd->cmd_rfm);
11682 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11683 DDI_DMA_SYNC_FORDEV);
11684 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11685 mpt->m_free_index = 0;
11686 }
11687 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11688 mpt->m_free_index);
11689 }
11690 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11691 mptsas_remove_cmd(mpt, cmd);
11692 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11693 }
11694 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
11695 mptsas_return_to_pool(mpt, cmd);
11696 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
11697 if (mptsas_check_dma_handle(data_dma_state.handle) !=
11698 DDI_SUCCESS) {
11699 ddi_fm_service_impact(mpt->m_dip,
11700 DDI_SERVICE_UNAFFECTED);
11701 status = EFAULT;
11702 }
11703 mptsas_dma_free(&data_dma_state);
11704 }
11705 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
11706 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
11707 DDI_SUCCESS) {
11708 ddi_fm_service_impact(mpt->m_dip,
11709 DDI_SERVICE_UNAFFECTED);
11710 status = EFAULT;
11711 }
11712 mptsas_dma_free(&dataout_dma_state);
11713 }
11714 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
11715 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
11716 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
11717 }
11718 }
11719 if (request_msg)
11720 kmem_free(request_msg, request_size);
11721
11722 return (status);
11723 }
11724
11725 static int
11726 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
11727 {
11728 /*
11729 * If timeout is 0, set timeout to default of 60 seconds.
11730 */
11731 if (data->Timeout == 0) {
11732 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
11733 }
11734
11735 if (((data->DataSize == 0) &&
11736 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
11737 ((data->DataSize != 0) &&
11738 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
11739 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
11740 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
11741 (data->DataOutSize != 0))))) {
11742 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
11743 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
11744 } else {
11745 data->DataOutSize = 0;
11746 }
11747 /*
11748 * Send passthru request messages
11749 */
11750 return (mptsas_do_passthru(mpt,
11751 (uint8_t *)((uintptr_t)data->PtrRequest),
11752 (uint8_t *)((uintptr_t)data->PtrReply),
11753 (uint8_t *)((uintptr_t)data->PtrData),
11754 data->RequestSize, data->ReplySize,
11755 data->DataSize, (uint8_t)data->DataDirection,
11756 (uint8_t *)((uintptr_t)data->PtrDataOut),
11757 data->DataOutSize, data->Timeout, mode));
11758 } else {
11759 return (EINVAL);
11760 }
11761 }
11762
11763 static uint8_t
11764 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
11765 {
11766 uint8_t index;
11767
11768 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
11769 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
11770 return (index);
11771 }
11772 }
11773
11774 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
11775 }
11776
11777 static void
11778 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
11779 {
11780 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
11781 pMpi2DiagReleaseRequest_t pDiag_release_msg;
11782 struct scsi_pkt *pkt = cmd->cmd_pkt;
11783 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
11784 uint32_t i;
11785 uint64_t request_desc;
11786
11787 ASSERT(mutex_owned(&mpt->m_mutex));
11788
11789 /*
11790 * Form the diag message depending on the post or release function.
11791 */
11792 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
11793 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
11794 (mpt->m_req_frame + (mpt->m_req_frame_size *
11795 cmd->cmd_slot));
11796 bzero(pDiag_post_msg, mpt->m_req_frame_size);
11797 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
11798 diag->function);
11799 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
11800 diag->pBuffer->buffer_type);
11801 ddi_put8(mpt->m_acc_req_frame_hdl,
11802 &pDiag_post_msg->ExtendedType,
11803 diag->pBuffer->extended_type);
11804 ddi_put32(mpt->m_acc_req_frame_hdl,
11805 &pDiag_post_msg->BufferLength,
11806 diag->pBuffer->buffer_data.size);
11807 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
11808 i++) {
11809 ddi_put32(mpt->m_acc_req_frame_hdl,
11810 &pDiag_post_msg->ProductSpecific[i],
11811 diag->pBuffer->product_specific[i]);
11812 }
11813 ddi_put32(mpt->m_acc_req_frame_hdl,
11814 &pDiag_post_msg->BufferAddress.Low,
11815 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11816 & 0xffffffffull));
11817 ddi_put32(mpt->m_acc_req_frame_hdl,
11818 &pDiag_post_msg->BufferAddress.High,
11819 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11820 >> 32));
11821 } else {
11822 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
11823 (mpt->m_req_frame + (mpt->m_req_frame_size *
11824 cmd->cmd_slot));
11825 bzero(pDiag_release_msg, mpt->m_req_frame_size);
11826 ddi_put8(mpt->m_acc_req_frame_hdl,
11827 &pDiag_release_msg->Function, diag->function);
11828 ddi_put8(mpt->m_acc_req_frame_hdl,
11829 &pDiag_release_msg->BufferType,
11830 diag->pBuffer->buffer_type);
11831 }
11832
11833 /*
11834 * Send the message
11835 */
11836 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
11837 DDI_DMA_SYNC_FORDEV);
11838 request_desc = (cmd->cmd_slot << 16) |
11839 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
11840 cmd->cmd_rfm = NULL;
11841 MPTSAS_START_CMD(mpt, request_desc);
11842 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11843 DDI_SUCCESS) ||
11844 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11845 DDI_SUCCESS)) {
11846 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11847 }
11848 }
11849
11850 static int
11851 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
11852 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
11853 {
11854 mptsas_diag_request_t diag;
11855 int status, slot_num, post_flags = 0;
11856 mptsas_cmd_t *cmd = NULL;
11857 struct scsi_pkt *pkt;
11858 pMpi2DiagBufferPostReply_t reply;
11859 uint16_t iocstatus;
11860 uint32_t iocloginfo, transfer_length;
11861
11862 /*
11863 * If buffer is not enabled, just leave.
11864 */
11865 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
11866 if (!pBuffer->enabled) {
11867 status = DDI_FAILURE;
11868 goto out;
11869 }
11870
11871 /*
11872 * Clear some flags initially.
11873 */
11874 pBuffer->force_release = FALSE;
11875 pBuffer->valid_data = FALSE;
11876 pBuffer->owned_by_firmware = FALSE;
11877
11878 /*
11879 * Get a cmd buffer from the cmd buffer pool
11880 */
11881 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11882 status = DDI_FAILURE;
11883 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
11884 goto out;
11885 }
11886 post_flags |= MPTSAS_REQUEST_POOL_CMD;
11887
11888 bzero((caddr_t)cmd, sizeof (*cmd));
11889 bzero((caddr_t)pkt, scsi_pkt_size());
11890
11891 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11892
11893 diag.pBuffer = pBuffer;
11894 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
11895
11896 /*
11897 * Form a blank cmd/pkt to store the acknowledgement message
11898 */
11899 pkt->pkt_ha_private = (opaque_t)&diag;
11900 pkt->pkt_flags = FLAG_HEAD;
11901 pkt->pkt_time = 60;
11902 cmd->cmd_pkt = pkt;
11903 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11904
11905 /*
11906 * Save the command in a slot
11907 */
11908 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11909 /*
11910 * Once passthru command get slot, set cmd_flags
11911 * CFLAG_PREPARED.
11912 */
11913 cmd->cmd_flags |= CFLAG_PREPARED;
11914 mptsas_start_diag(mpt, cmd);
11915 } else {
11916 mptsas_waitq_add(mpt, cmd);
11917 }
11918
11919 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11920 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11921 }
11922
11923 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11924 status = DDI_FAILURE;
11925 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
11926 goto out;
11927 }
11928
11929 /*
11930 * cmd_rfm points to the reply message if a reply was given. Check the
11931 * IOCStatus to make sure everything went OK with the FW diag request
11932 * and set buffer flags.
11933 */
11934 if (cmd->cmd_rfm) {
11935 post_flags |= MPTSAS_ADDRESS_REPLY;
11936 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11937 DDI_DMA_SYNC_FORCPU);
11938 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
11939 (cmd->cmd_rfm -
11940 (mpt->m_reply_frame_dma_addr&0xfffffffful)));
11941
11942 /*
11943 * Get the reply message data
11944 */
11945 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11946 &reply->IOCStatus);
11947 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11948 &reply->IOCLogInfo);
11949 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
11950 &reply->TransferLength);
11951
11952 /*
11953 * If post failed quit.
11954 */
11955 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
11956 status = DDI_FAILURE;
11957 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
11958 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
11959 iocloginfo, transfer_length));
11960 goto out;
11961 }
11962
11963 /*
11964 * Post was successful.
11965 */
11966 pBuffer->valid_data = TRUE;
11967 pBuffer->owned_by_firmware = TRUE;
11968 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11969 status = DDI_SUCCESS;
11970 }
11971
11972 out:
11973 /*
11974 * Put the reply frame back on the free queue, increment the free
11975 * index, and write the new index to the free index register. But only
11976 * if this reply is an ADDRESS reply.
11977 */
11978 if (post_flags & MPTSAS_ADDRESS_REPLY) {
11979 ddi_put32(mpt->m_acc_free_queue_hdl,
11980 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11981 cmd->cmd_rfm);
11982 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11983 DDI_DMA_SYNC_FORDEV);
11984 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11985 mpt->m_free_index = 0;
11986 }
11987 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11988 mpt->m_free_index);
11989 }
11990 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11991 mptsas_remove_cmd(mpt, cmd);
11992 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11993 }
11994 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
11995 mptsas_return_to_pool(mpt, cmd);
11996 }
11997
11998 return (status);
11999 }
12000
12001 static int
12002 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
12003 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
12004 uint32_t diag_type)
12005 {
12006 mptsas_diag_request_t diag;
12007 int status, slot_num, rel_flags = 0;
12008 mptsas_cmd_t *cmd = NULL;
12009 struct scsi_pkt *pkt;
12010 pMpi2DiagReleaseReply_t reply;
12011 uint16_t iocstatus;
12012 uint32_t iocloginfo;
12013
12014 /*
12015 * If buffer is not enabled, just leave.
12016 */
12017 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
12018 if (!pBuffer->enabled) {
12019 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
12020 "by the IOC");
12021 status = DDI_FAILURE;
12022 goto out;
12023 }
12024
12025 /*
12026 * Clear some flags initially.
12027 */
12028 pBuffer->force_release = FALSE;
12029 pBuffer->valid_data = FALSE;
12030 pBuffer->owned_by_firmware = FALSE;
12031
12032 /*
12033 * Get a cmd buffer from the cmd buffer pool
12034 */
12035 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
12036 status = DDI_FAILURE;
12037 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
12038 "Diag");
12039 goto out;
12040 }
12041 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
12042
12043 bzero((caddr_t)cmd, sizeof (*cmd));
12044 bzero((caddr_t)pkt, scsi_pkt_size());
12045
12046 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
12047
12048 diag.pBuffer = pBuffer;
12049 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
12050
12051 /*
12052 * Form a blank cmd/pkt to store the acknowledgement message
12053 */
12054 pkt->pkt_ha_private = (opaque_t)&diag;
12055 pkt->pkt_flags = FLAG_HEAD;
12056 pkt->pkt_time = 60;
12057 cmd->cmd_pkt = pkt;
12058 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
12059
12060 /*
12061 * Save the command in a slot
12062 */
12063 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
12064 /*
12065 * Once passthru command get slot, set cmd_flags
12066 * CFLAG_PREPARED.
12067 */
12068 cmd->cmd_flags |= CFLAG_PREPARED;
12069 mptsas_start_diag(mpt, cmd);
12070 } else {
12071 mptsas_waitq_add(mpt, cmd);
12072 }
12073
12074 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
12075 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
12076 }
12077
12078 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
12079 status = DDI_FAILURE;
12080 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
12081 goto out;
12082 }
12083
12084 /*
12085 * cmd_rfm points to the reply message if a reply was given. Check the
12086 * IOCStatus to make sure everything went OK with the FW diag request
12087 * and set buffer flags.
12088 */
12089 if (cmd->cmd_rfm) {
12090 rel_flags |= MPTSAS_ADDRESS_REPLY;
12091 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
12092 DDI_DMA_SYNC_FORCPU);
12093 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
12094 (cmd->cmd_rfm -
12095 (mpt->m_reply_frame_dma_addr&0xfffffffful)));
12096
12097 /*
12098 * Get the reply message data
12099 */
12100 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
12101 &reply->IOCStatus);
12102 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
12103 &reply->IOCLogInfo);
12104
12105 /*
12106 * If release failed quit.
12107 */
12108 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
12109 pBuffer->owned_by_firmware) {
12110 status = DDI_FAILURE;
12111 NDBG13(("release FW Diag Buffer failed: "
12112 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
12113 iocloginfo));
12114 goto out;
12115 }
12116
12117 /*
12118 * Release was successful.
12119 */
12120 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
12121 status = DDI_SUCCESS;
12122
12123 /*
12124 * If this was for an UNREGISTER diag type command, clear the
12125 * unique ID.
12126 */
12127 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
12128 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
12129 }
12130 }
12131
12132 out:
12133 /*
12134 * Put the reply frame back on the free queue, increment the free
12135 * index, and write the new index to the free index register. But only
12136 * if this reply is an ADDRESS reply.
12137 */
12138 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
12139 ddi_put32(mpt->m_acc_free_queue_hdl,
12140 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
12141 cmd->cmd_rfm);
12142 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
12143 DDI_DMA_SYNC_FORDEV);
12144 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
12145 mpt->m_free_index = 0;
12146 }
12147 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
12148 mpt->m_free_index);
12149 }
12150 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
12151 mptsas_remove_cmd(mpt, cmd);
12152 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
12153 }
12154 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
12155 mptsas_return_to_pool(mpt, cmd);
12156 }
12157
12158 return (status);
12159 }
12160
12161 static int
12162 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
12163 uint32_t *return_code)
12164 {
12165 mptsas_fw_diagnostic_buffer_t *pBuffer;
12166 uint8_t extended_type, buffer_type, i;
12167 uint32_t buffer_size;
12168 uint32_t unique_id;
12169 int status;
12170
12171 ASSERT(mutex_owned(&mpt->m_mutex));
12172
12173 extended_type = diag_register->ExtendedType;
12174 buffer_type = diag_register->BufferType;
12175 buffer_size = diag_register->RequestedBufferSize;
12176 unique_id = diag_register->UniqueId;
12177
12178 /*
12179 * Check for valid buffer type
12180 */
12181 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
12182 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12183 return (DDI_FAILURE);
12184 }
12185
12186 /*
12187 * Get the current buffer and look up the unique ID. The unique ID
12188 * should not be found. If it is, the ID is already in use.
12189 */
12190 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12191 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
12192 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12193 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12194 return (DDI_FAILURE);
12195 }
12196
12197 /*
12198 * The buffer's unique ID should not be registered yet, and the given
12199 * unique ID cannot be 0.
12200 */
12201 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
12202 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
12203 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12204 return (DDI_FAILURE);
12205 }
12206
12207 /*
12208 * If this buffer is already posted as immediate, just change owner.
12209 */
12210 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
12211 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
12212 pBuffer->immediate = FALSE;
12213 pBuffer->unique_id = unique_id;
12214 return (DDI_SUCCESS);
12215 }
12216
12217 /*
12218 * Post a new buffer after checking if it's enabled. The DMA buffer
12219 * that is allocated will be contiguous (sgl_len = 1).
12220 */
12221 if (!pBuffer->enabled) {
12222 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
12223 return (DDI_FAILURE);
12224 }
12225 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
12226 pBuffer->buffer_data.size = buffer_size;
12227 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
12228 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
12229 "diag buffer: size = %d bytes", buffer_size);
12230 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
12231 return (DDI_FAILURE);
12232 }
12233
12234 /*
12235 * Copy the given info to the diag buffer and post the buffer.
12236 */
12237 pBuffer->buffer_type = buffer_type;
12238 pBuffer->immediate = FALSE;
12239 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
12240 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
12241 i++) {
12242 pBuffer->product_specific[i] =
12243 diag_register->ProductSpecific[i];
12244 }
12245 }
12246 pBuffer->extended_type = extended_type;
12247 pBuffer->unique_id = unique_id;
12248 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
12249
12250 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
12251 DDI_SUCCESS) {
12252 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
12253 "mptsas_diag_register.");
12254 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
12255 status = DDI_FAILURE;
12256 }
12257
12258 /*
12259 * In case there was a failure, free the DMA buffer.
12260 */
12261 if (status == DDI_FAILURE) {
12262 mptsas_dma_free(&pBuffer->buffer_data);
12263 }
12264
12265 return (status);
12266 }
12267
12268 static int
12269 mptsas_diag_unregister(mptsas_t *mpt,
12270 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
12271 {
12272 mptsas_fw_diagnostic_buffer_t *pBuffer;
12273 uint8_t i;
12274 uint32_t unique_id;
12275 int status;
12276
12277 ASSERT(mutex_owned(&mpt->m_mutex));
12278
12279 unique_id = diag_unregister->UniqueId;
12280
12281 /*
12282 * Get the current buffer and look up the unique ID. The unique ID
12283 * should be there.
12284 */
12285 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12286 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12287 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12288 return (DDI_FAILURE);
12289 }
12290
12291 pBuffer = &mpt->m_fw_diag_buffer_list[i];
12292
12293 /*
12294 * Try to release the buffer from FW before freeing it. If release
12295 * fails, don't free the DMA buffer in case FW tries to access it
12296 * later. If buffer is not owned by firmware, can't release it.
12297 */
12298 if (!pBuffer->owned_by_firmware) {
12299 status = DDI_SUCCESS;
12300 } else {
12301 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
12302 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
12303 }
12304
12305 /*
12306 * At this point, return the current status no matter what happens with
12307 * the DMA buffer.
12308 */
12309 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
12310 if (status == DDI_SUCCESS) {
12311 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
12312 DDI_SUCCESS) {
12313 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
12314 "in mptsas_diag_unregister.");
12315 ddi_fm_service_impact(mpt->m_dip,
12316 DDI_SERVICE_UNAFFECTED);
12317 }
12318 mptsas_dma_free(&pBuffer->buffer_data);
12319 }
12320
12321 return (status);
12322 }
12323
12324 static int
12325 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
12326 uint32_t *return_code)
12327 {
12328 mptsas_fw_diagnostic_buffer_t *pBuffer;
12329 uint8_t i;
12330 uint32_t unique_id;
12331
12332 ASSERT(mutex_owned(&mpt->m_mutex));
12333
12334 unique_id = diag_query->UniqueId;
12335
12336 /*
12337 * If ID is valid, query on ID.
12338 * If ID is invalid, query on buffer type.
12339 */
12340 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
12341 i = diag_query->BufferType;
12342 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
12343 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12344 return (DDI_FAILURE);
12345 }
12346 } else {
12347 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12348 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12349 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12350 return (DDI_FAILURE);
12351 }
12352 }
12353
12354 /*
12355 * Fill query structure with the diag buffer info.
12356 */
12357 pBuffer = &mpt->m_fw_diag_buffer_list[i];
12358 diag_query->BufferType = pBuffer->buffer_type;
12359 diag_query->ExtendedType = pBuffer->extended_type;
12360 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
12361 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
12362 i++) {
12363 diag_query->ProductSpecific[i] =
12364 pBuffer->product_specific[i];
12365 }
12366 }
12367 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
12368 diag_query->DriverAddedBufferSize = 0;
12369 diag_query->UniqueId = pBuffer->unique_id;
12370 diag_query->ApplicationFlags = 0;
12371 diag_query->DiagnosticFlags = 0;
12372
12373 /*
12374 * Set/Clear application flags
12375 */
12376 if (pBuffer->immediate) {
12377 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
12378 } else {
12379 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
12380 }
12381 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
12382 diag_query->ApplicationFlags |=
12383 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
12384 } else {
12385 diag_query->ApplicationFlags &=
12386 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
12387 }
12388 if (pBuffer->owned_by_firmware) {
12389 diag_query->ApplicationFlags |=
12390 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
12391 } else {
12392 diag_query->ApplicationFlags &=
12393 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
12394 }
12395
12396 return (DDI_SUCCESS);
12397 }
12398
12399 static int
12400 mptsas_diag_read_buffer(mptsas_t *mpt,
12401 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
12402 uint32_t *return_code, int ioctl_mode)
12403 {
12404 mptsas_fw_diagnostic_buffer_t *pBuffer;
12405 uint8_t i, *pData;
12406 uint32_t unique_id, byte;
12407 int status;
12408
12409 ASSERT(mutex_owned(&mpt->m_mutex));
12410
12411 unique_id = diag_read_buffer->UniqueId;
12412
12413 /*
12414 * Get the current buffer and look up the unique ID. The unique ID
12415 * should be there.
12416 */
12417 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12418 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12419 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12420 return (DDI_FAILURE);
12421 }
12422
12423 pBuffer = &mpt->m_fw_diag_buffer_list[i];
12424
12425 /*
12426 * Make sure requested read is within limits
12427 */
12428 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
12429 pBuffer->buffer_data.size) {
12430 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12431 return (DDI_FAILURE);
12432 }
12433
12434 /*
12435 * Copy the requested data from DMA to the diag_read_buffer. The DMA
12436 * buffer that was allocated is one contiguous buffer.
12437 */
12438 pData = (uint8_t *)(pBuffer->buffer_data.memp +
12439 diag_read_buffer->StartingOffset);
12440 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
12441 DDI_DMA_SYNC_FORCPU);
12442 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
12443 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
12444 != 0) {
12445 return (DDI_FAILURE);
12446 }
12447 }
12448 diag_read_buffer->Status = 0;
12449
12450 /*
12451 * Set or clear the Force Release flag.
12452 */
12453 if (pBuffer->force_release) {
12454 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
12455 } else {
12456 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
12457 }
12458
12459 /*
12460 * If buffer is to be reregistered, make sure it's not already owned by
12461 * firmware first.
12462 */
12463 status = DDI_SUCCESS;
12464 if (!pBuffer->owned_by_firmware) {
12465 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
12466 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
12467 return_code);
12468 }
12469 }
12470
12471 return (status);
12472 }
12473
12474 static int
12475 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
12476 uint32_t *return_code)
12477 {
12478 mptsas_fw_diagnostic_buffer_t *pBuffer;
12479 uint8_t i;
12480 uint32_t unique_id;
12481 int status;
12482
12483 ASSERT(mutex_owned(&mpt->m_mutex));
12484
12485 unique_id = diag_release->UniqueId;
12486
12487 /*
12488 * Get the current buffer and look up the unique ID. The unique ID
12489 * should be there.
12490 */
12491 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
12492 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
12493 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
12494 return (DDI_FAILURE);
12495 }
12496
12497 pBuffer = &mpt->m_fw_diag_buffer_list[i];
12498
12499 /*
12500 * If buffer is not owned by firmware, it's already been released.
12501 */
12502 if (!pBuffer->owned_by_firmware) {
12503 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
12504 return (DDI_FAILURE);
12505 }
12506
12507 /*
12508 * Release the buffer.
12509 */
12510 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
12511 MPTSAS_FW_DIAG_TYPE_RELEASE);
12512 return (status);
12513 }
12514
12515 static int
12516 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
12517 uint32_t length, uint32_t *return_code, int ioctl_mode)
12518 {
12519 mptsas_fw_diag_register_t diag_register;
12520 mptsas_fw_diag_unregister_t diag_unregister;
12521 mptsas_fw_diag_query_t diag_query;
12522 mptsas_diag_read_buffer_t diag_read_buffer;
12523 mptsas_fw_diag_release_t diag_release;
12524 int status = DDI_SUCCESS;
12525 uint32_t original_return_code, read_buf_len;
12526
12527 ASSERT(mutex_owned(&mpt->m_mutex));
12528
12529 original_return_code = *return_code;
12530 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
12531
12532 switch (action) {
12533 case MPTSAS_FW_DIAG_TYPE_REGISTER:
12534 if (!length) {
12535 *return_code =
12536 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12537 status = DDI_FAILURE;
12538 break;
12539 }
12540 if (ddi_copyin(diag_action, &diag_register,
12541 sizeof (diag_register), ioctl_mode) != 0) {
12542 return (DDI_FAILURE);
12543 }
12544 status = mptsas_diag_register(mpt, &diag_register,
12545 return_code);
12546 break;
12547
12548 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
12549 if (length < sizeof (diag_unregister)) {
12550 *return_code =
12551 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12552 status = DDI_FAILURE;
12553 break;
12554 }
12555 if (ddi_copyin(diag_action, &diag_unregister,
12556 sizeof (diag_unregister), ioctl_mode) != 0) {
12557 return (DDI_FAILURE);
12558 }
12559 status = mptsas_diag_unregister(mpt, &diag_unregister,
12560 return_code);
12561 break;
12562
12563 case MPTSAS_FW_DIAG_TYPE_QUERY:
12564 if (length < sizeof (diag_query)) {
12565 *return_code =
12566 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12567 status = DDI_FAILURE;
12568 break;
12569 }
12570 if (ddi_copyin(diag_action, &diag_query,
12571 sizeof (diag_query), ioctl_mode) != 0) {
12572 return (DDI_FAILURE);
12573 }
12574 status = mptsas_diag_query(mpt, &diag_query,
12575 return_code);
12576 if (status == DDI_SUCCESS) {
12577 if (ddi_copyout(&diag_query, diag_action,
12578 sizeof (diag_query), ioctl_mode) != 0) {
12579 return (DDI_FAILURE);
12580 }
12581 }
12582 break;
12583
12584 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
12585 if (ddi_copyin(diag_action, &diag_read_buffer,
12586 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
12587 return (DDI_FAILURE);
12588 }
12589 read_buf_len = sizeof (diag_read_buffer) -
12590 sizeof (diag_read_buffer.DataBuffer) +
12591 diag_read_buffer.BytesToRead;
12592 if (length < read_buf_len) {
12593 *return_code =
12594 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12595 status = DDI_FAILURE;
12596 break;
12597 }
12598 status = mptsas_diag_read_buffer(mpt,
12599 &diag_read_buffer, diag_action +
12600 sizeof (diag_read_buffer) - 4, return_code,
12601 ioctl_mode);
12602 if (status == DDI_SUCCESS) {
12603 if (ddi_copyout(&diag_read_buffer, diag_action,
12604 sizeof (diag_read_buffer) - 4, ioctl_mode)
12605 != 0) {
12606 return (DDI_FAILURE);
12607 }
12608 }
12609 break;
12610
12611 case MPTSAS_FW_DIAG_TYPE_RELEASE:
12612 if (length < sizeof (diag_release)) {
12613 *return_code =
12614 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12615 status = DDI_FAILURE;
12616 break;
12617 }
12618 if (ddi_copyin(diag_action, &diag_release,
12619 sizeof (diag_release), ioctl_mode) != 0) {
12620 return (DDI_FAILURE);
12621 }
12622 status = mptsas_diag_release(mpt, &diag_release,
12623 return_code);
12624 break;
12625
12626 default:
12627 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12628 status = DDI_FAILURE;
12629 break;
12630 }
12631
12632 if ((status == DDI_FAILURE) &&
12633 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
12634 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
12635 status = DDI_SUCCESS;
12636 }
12637
12638 return (status);
12639 }
12640
12641 static int
12642 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
12643 {
12644 int status;
12645 mptsas_diag_action_t driver_data;
12646
12647 ASSERT(mutex_owned(&mpt->m_mutex));
12648
12649 /*
12650 * Copy the user data to a driver data buffer.
12651 */
12652 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
12653 mode) == 0) {
12654 /*
12655 * Send diag action request if Action is valid
12656 */
12657 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
12658 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
12659 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
12660 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
12661 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
12662 status = mptsas_do_diag_action(mpt, driver_data.Action,
12663 (void *)(uintptr_t)driver_data.PtrDiagAction,
12664 driver_data.Length, &driver_data.ReturnCode,
12665 mode);
12666 if (status == DDI_SUCCESS) {
12667 if (ddi_copyout(&driver_data.ReturnCode,
12668 &user_data->ReturnCode,
12669 sizeof (user_data->ReturnCode), mode)
12670 != 0) {
12671 status = EFAULT;
12672 } else {
12673 status = 0;
12674 }
12675 } else {
12676 status = EIO;
12677 }
12678 } else {
12679 status = EINVAL;
12680 }
12681 } else {
12682 status = EFAULT;
12683 }
12684
12685 return (status);
12686 }
12687
12688 /*
12689 * This routine handles the "event query" ioctl.
12690 */
12691 static int
12692 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
12693 int *rval)
12694 {
12695 int status;
12696 mptsas_event_query_t driverdata;
12697 uint8_t i;
12698
12699 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
12700
12701 mutex_enter(&mpt->m_mutex);
12702 for (i = 0; i < 4; i++) {
12703 driverdata.Types[i] = mpt->m_event_mask[i];
12704 }
12705 mutex_exit(&mpt->m_mutex);
12706
12707 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
12708 status = EFAULT;
12709 } else {
12710 *rval = MPTIOCTL_STATUS_GOOD;
12711 status = 0;
12712 }
12713
12714 return (status);
12715 }
12716
12717 /*
12718 * This routine handles the "event enable" ioctl.
12719 */
12720 static int
12721 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
12722 int *rval)
12723 {
12724 int status;
12725 mptsas_event_enable_t driverdata;
12726 uint8_t i;
12727
12728 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12729 mutex_enter(&mpt->m_mutex);
12730 for (i = 0; i < 4; i++) {
12731 mpt->m_event_mask[i] = driverdata.Types[i];
12732 }
12733 mutex_exit(&mpt->m_mutex);
12734
12735 *rval = MPTIOCTL_STATUS_GOOD;
12736 status = 0;
12737 } else {
12738 status = EFAULT;
12739 }
12740 return (status);
12741 }
12742
12743 /*
12744 * This routine handles the "event report" ioctl.
12745 */
12746 static int
12747 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
12748 int *rval)
12749 {
12750 int status;
12751 mptsas_event_report_t driverdata;
12752
12753 mutex_enter(&mpt->m_mutex);
12754
12755 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
12756 mode) == 0) {
12757 if (driverdata.Size >= sizeof (mpt->m_events)) {
12758 if (ddi_copyout(mpt->m_events, data->Events,
12759 sizeof (mpt->m_events), mode) != 0) {
12760 status = EFAULT;
12761 } else {
12762 if (driverdata.Size > sizeof (mpt->m_events)) {
12763 driverdata.Size =
12764 sizeof (mpt->m_events);
12765 if (ddi_copyout(&driverdata.Size,
12766 &data->Size,
12767 sizeof (driverdata.Size),
12768 mode) != 0) {
12769 status = EFAULT;
12770 } else {
12771 *rval = MPTIOCTL_STATUS_GOOD;
12772 status = 0;
12773 }
12774 } else {
12775 *rval = MPTIOCTL_STATUS_GOOD;
12776 status = 0;
12777 }
12778 }
12779 } else {
12780 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12781 status = 0;
12782 }
12783 } else {
12784 status = EFAULT;
12785 }
12786
12787 mutex_exit(&mpt->m_mutex);
12788 return (status);
12789 }
12790
12791 static void
12792 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12793 {
12794 int *reg_data;
12795 uint_t reglen;
12796
12797 /*
12798 * Lookup the 'reg' property and extract the other data
12799 */
12800 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12801 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
12802 DDI_PROP_SUCCESS) {
12803 /*
12804 * Extract the PCI data from the 'reg' property first DWORD.
12805 * The entry looks like the following:
12806 * First DWORD:
12807 * Bits 0 - 7 8-bit Register number
12808 * Bits 8 - 10 3-bit Function number
12809 * Bits 11 - 15 5-bit Device number
12810 * Bits 16 - 23 8-bit Bus number
12811 * Bits 24 - 25 2-bit Address Space type identifier
12812 *
12813 */
12814 adapter_data->PciInformation.u.bits.BusNumber =
12815 (reg_data[0] & 0x00FF0000) >> 16;
12816 adapter_data->PciInformation.u.bits.DeviceNumber =
12817 (reg_data[0] & 0x0000F800) >> 11;
12818 adapter_data->PciInformation.u.bits.FunctionNumber =
12819 (reg_data[0] & 0x00000700) >> 8;
12820 ddi_prop_free((void *)reg_data);
12821 } else {
12822 /*
12823 * If we can't determine the PCI data then we fill in FF's for
12824 * the data to indicate this.
12825 */
12826 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
12827 adapter_data->MpiPortNumber = 0xFFFFFFFF;
12828 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
12829 }
12830
12831 /*
12832 * Saved in the mpt->m_fwversion
12833 */
12834 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
12835 }
12836
12837 static void
12838 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12839 {
12840 char *driver_verstr = MPTSAS_MOD_STRING;
12841
12842 mptsas_lookup_pci_data(mpt, adapter_data);
12843 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS3;
12844 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
12845 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
12846 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
12847 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
12848 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
12849 adapter_data->BiosVersion = 0;
12850 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
12851 }
12852
12853 static void
12854 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
12855 {
12856 int *reg_data, i;
12857 uint_t reglen;
12858
12859 /*
12860 * Lookup the 'reg' property and extract the other data
12861 */
12862 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12863 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
12864 DDI_PROP_SUCCESS) {
12865 /*
12866 * Extract the PCI data from the 'reg' property first DWORD.
12867 * The entry looks like the following:
12868 * First DWORD:
12869 * Bits 8 - 10 3-bit Function number
12870 * Bits 11 - 15 5-bit Device number
12871 * Bits 16 - 23 8-bit Bus number
12872 */
12873 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
12874 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
12875 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
12876 ddi_prop_free((void *)reg_data);
12877 } else {
12878 /*
12879 * If we can't determine the PCI info then we fill in FF's for
12880 * the data to indicate this.
12881 */
12882 pci_info->BusNumber = 0xFFFFFFFF;
12883 pci_info->DeviceNumber = 0xFF;
12884 pci_info->FunctionNumber = 0xFF;
12885 }
12886
12887 /*
12888 * Now get the interrupt vector and the pci header. The vector can
12889 * only be 0 right now. The header is the first 256 bytes of config
12890 * space.
12891 */
12892 pci_info->InterruptVector = 0;
12893 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
12894 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
12895 i);
12896 }
12897 }
12898
12899 static int
12900 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
12901 {
12902 int status = 0;
12903 mptsas_reg_access_t driverdata;
12904
12905 mutex_enter(&mpt->m_mutex);
12906 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12907 switch (driverdata.Command) {
12908 /*
12909 * IO access is not supported.
12910 */
12911 case REG_IO_READ:
12912 case REG_IO_WRITE:
12913 mptsas_log(mpt, CE_WARN, "IO access is not "
12914 "supported. Use memory access.");
12915 status = EINVAL;
12916 break;
12917
12918 case REG_MEM_READ:
12919 driverdata.RegData = ddi_get32(mpt->m_datap,
12920 (uint32_t *)(void *)mpt->m_reg +
12921 driverdata.RegOffset);
12922 if (ddi_copyout(&driverdata.RegData,
12923 &data->RegData,
12924 sizeof (driverdata.RegData), mode) != 0) {
12925 mptsas_log(mpt, CE_WARN, "Register "
12926 "Read Failed");
12927 status = EFAULT;
12928 }
12929 break;
12930
12931 case REG_MEM_WRITE:
12932 ddi_put32(mpt->m_datap,
12933 (uint32_t *)(void *)mpt->m_reg +
12934 driverdata.RegOffset,
12935 driverdata.RegData);
12936 break;
12937
12938 default:
12939 status = EINVAL;
12940 break;
12941 }
12942 } else {
12943 status = EFAULT;
12944 }
12945
12946 mutex_exit(&mpt->m_mutex);
12947 return (status);
12948 }
12949
12950 static int
12951 led_control(mptsas_t *mpt, intptr_t data, int mode)
12952 {
12953 int ret = 0;
12954 mptsas_led_control_t lc;
12955 mptsas_target_t *ptgt;
12956
12957 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
12958 return (EFAULT);
12959 }
12960
12961 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
12962 lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
12963 lc.Led < MPTSAS_LEDCTL_LED_MIN ||
12964 lc.Led > MPTSAS_LEDCTL_LED_MAX ||
12965 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
12966 lc.LedStatus != 1)) {
12967 return (EINVAL);
12968 }
12969
12970 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
12971 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
12972 return (EACCES);
12973
12974 /* Locate the target we're interrogating... */
12975 mutex_enter(&mpt->m_mutex);
12976 ptgt = refhash_linear_search(mpt->m_targets,
12977 mptsas_target_eval_slot, &lc);
12978 if (ptgt == NULL) {
12979 /* We could not find a target for that enclosure/slot. */
12980 mutex_exit(&mpt->m_mutex);
12981 return (ENOENT);
12982 }
12983
12984 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
12985 /* Update our internal LED state. */
12986 ptgt->m_led_status &= ~(1 << (lc.Led - 1));
12987 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1);
12988
12989 /* Flush it to the controller. */
12990 ret = mptsas_flush_led_status(mpt, ptgt);
12991 mutex_exit(&mpt->m_mutex);
12992 return (ret);
12993 }
12994
12995 /* Return our internal LED state. */
12996 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1;
12997 mutex_exit(&mpt->m_mutex);
12998
12999 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
13000 return (EFAULT);
13001 }
13002
13003 return (0);
13004 }
13005
13006 static int
13007 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
13008 {
13009 uint16_t i = 0;
13010 uint16_t count = 0;
13011 int ret = 0;
13012 mptsas_target_t *ptgt;
13013 mptsas_disk_info_t *di;
13014 STRUCT_DECL(mptsas_get_disk_info, gdi);
13015
13016 if ((mode & FREAD) == 0)
13017 return (EACCES);
13018
13019 STRUCT_INIT(gdi, get_udatamodel());
13020
13021 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
13022 mode) != 0) {
13023 return (EFAULT);
13024 }
13025
13026 /* Find out how many targets there are. */
13027 mutex_enter(&mpt->m_mutex);
13028 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13029 ptgt = refhash_next(mpt->m_targets, ptgt)) {
13030 count++;
13031 }
13032 mutex_exit(&mpt->m_mutex);
13033
13034 /*
13035 * If we haven't been asked to copy out information on each target,
13036 * then just return the count.
13037 */
13038 STRUCT_FSET(gdi, DiskCount, count);
13039 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
13040 goto copy_out;
13041
13042 /*
13043 * If we haven't been given a large enough buffer to copy out into,
13044 * let the caller know.
13045 */
13046 if (STRUCT_FGET(gdi, DiskInfoArraySize) <
13047 count * sizeof (mptsas_disk_info_t)) {
13048 ret = ENOSPC;
13049 goto copy_out;
13050 }
13051
13052 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
13053
13054 mutex_enter(&mpt->m_mutex);
13055 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13056 ptgt = refhash_next(mpt->m_targets, ptgt)) {
13057 if (i >= count) {
13058 /*
13059 * The number of targets changed while we weren't
13060 * looking, so give up.
13061 */
13062 refhash_rele(mpt->m_targets, ptgt);
13063 mutex_exit(&mpt->m_mutex);
13064 kmem_free(di, count * sizeof (mptsas_disk_info_t));
13065 return (EAGAIN);
13066 }
13067 di[i].Instance = mpt->m_instance;
13068 di[i].Enclosure = ptgt->m_enclosure;
13069 di[i].Slot = ptgt->m_slot_num;
13070 di[i].SasAddress = ptgt->m_addr.mta_wwn;
13071 i++;
13072 }
13073 mutex_exit(&mpt->m_mutex);
13074 STRUCT_FSET(gdi, DiskCount, i);
13075
13076 /* Copy out the disk information to the caller. */
13077 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
13078 i * sizeof (mptsas_disk_info_t), mode) != 0) {
13079 ret = EFAULT;
13080 }
13081
13082 kmem_free(di, count * sizeof (mptsas_disk_info_t));
13083
13084 copy_out:
13085 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
13086 mode) != 0) {
13087 ret = EFAULT;
13088 }
13089
13090 return (ret);
13091 }
13092
13093 static int
13094 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
13095 int *rval)
13096 {
13097 int status = 0;
13098 mptsas_t *mpt;
13099 mptsas_update_flash_t flashdata;
13100 mptsas_pass_thru_t passthru_data;
13101 mptsas_adapter_data_t adapter_data;
13102 mptsas_pci_info_t pci_info;
13103 int copylen;
13104
13105 int iport_flag = 0;
13106 dev_info_t *dip = NULL;
13107 mptsas_phymask_t phymask = 0;
13108 struct devctl_iocdata *dcp = NULL;
13109 char *addr = NULL;
13110 mptsas_target_t *ptgt = NULL;
13111
13112 *rval = MPTIOCTL_STATUS_GOOD;
13113 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
13114 return (EPERM);
13115 }
13116
13117 mpt = ddi_get_soft_state(mptsas3_state, MINOR2INST(getminor(dev)));
13118 if (mpt == NULL) {
13119 /*
13120 * Called from iport node, get the states
13121 */
13122 iport_flag = 1;
13123 dip = mptsas_get_dip_from_dev(dev, &phymask);
13124 if (dip == NULL) {
13125 return (ENXIO);
13126 }
13127 mpt = DIP2MPT(dip);
13128 }
13129 /* Make sure power level is D0 before accessing registers */
13130 mutex_enter(&mpt->m_mutex);
13131 if (mpt->m_options & MPTSAS_OPT_PM) {
13132 (void) pm_busy_component(mpt->m_dip, 0);
13133 if (mpt->m_power_level != PM_LEVEL_D0) {
13134 mutex_exit(&mpt->m_mutex);
13135 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
13136 DDI_SUCCESS) {
13137 mptsas_log(mpt, CE_WARN,
13138 "mptsas3%d: mptsas_ioctl: Raise power "
13139 "request failed.", mpt->m_instance);
13140 (void) pm_idle_component(mpt->m_dip, 0);
13141 return (ENXIO);
13142 }
13143 } else {
13144 mutex_exit(&mpt->m_mutex);
13145 }
13146 } else {
13147 mutex_exit(&mpt->m_mutex);
13148 }
13149
13150 if (iport_flag) {
13151 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
13152 if (status != 0) {
13153 goto out;
13154 }
13155 /*
13156 * The following code control the OK2RM LED, it doesn't affect
13157 * the ioctl return status.
13158 */
13159 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
13160 (cmd == DEVCTL_DEVICE_OFFLINE)) {
13161 if (ndi_dc_allochdl((void *)data, &dcp) !=
13162 NDI_SUCCESS) {
13163 goto out;
13164 }
13165 addr = ndi_dc_getaddr(dcp);
13166 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
13167 if (ptgt == NULL) {
13168 NDBG14(("mptsas_ioctl led control: tgt %s not "
13169 "found", addr));
13170 ndi_dc_freehdl(dcp);
13171 goto out;
13172 }
13173 mutex_enter(&mpt->m_mutex);
13174 if (cmd == DEVCTL_DEVICE_ONLINE) {
13175 ptgt->m_tgt_unconfigured = 0;
13176 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
13177 ptgt->m_tgt_unconfigured = 1;
13178 }
13179 if (cmd == DEVCTL_DEVICE_OFFLINE) {
13180 ptgt->m_led_status |=
13181 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
13182 } else {
13183 ptgt->m_led_status &=
13184 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
13185 }
13186 (void) mptsas_flush_led_status(mpt, ptgt);
13187 mutex_exit(&mpt->m_mutex);
13188 ndi_dc_freehdl(dcp);
13189 }
13190 goto out;
13191 }
13192 switch (cmd) {
13193 case MPTIOCTL_GET_DISK_INFO:
13194 status = get_disk_info(mpt, data, mode);
13195 break;
13196 case MPTIOCTL_LED_CONTROL:
13197 status = led_control(mpt, data, mode);
13198 break;
13199 case MPTIOCTL_UPDATE_FLASH:
13200 if (ddi_copyin((void *)data, &flashdata,
13201 sizeof (struct mptsas_update_flash), mode)) {
13202 status = EFAULT;
13203 break;
13204 }
13205
13206 mutex_enter(&mpt->m_mutex);
13207 if (mptsas_update_flash(mpt,
13208 (caddr_t)(long)flashdata.PtrBuffer,
13209 flashdata.ImageSize, flashdata.ImageType, mode)) {
13210 status = EFAULT;
13211 }
13212
13213 /*
13214 * Reset the chip to start using the new
13215 * firmware. Reset if failed also.
13216 */
13217 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
13218 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
13219 status = EFAULT;
13220 }
13221 mutex_exit(&mpt->m_mutex);
13222 break;
13223 case MPTIOCTL_PASS_THRU:
13224 /*
13225 * The user has requested to pass through a command to
13226 * be executed by the MPT firmware. Call our routine
13227 * which does this. Only allow one passthru IOCTL at
13228 * one time. Other threads will block on
13229 * m_passthru_mutex, which is of adaptive variant.
13230 */
13231 if (ddi_copyin((void *)data, &passthru_data,
13232 sizeof (mptsas_pass_thru_t), mode)) {
13233 status = EFAULT;
13234 break;
13235 }
13236 mutex_enter(&mpt->m_passthru_mutex);
13237 mutex_enter(&mpt->m_mutex);
13238 status = mptsas_pass_thru(mpt, &passthru_data, mode);
13239 mutex_exit(&mpt->m_mutex);
13240 mutex_exit(&mpt->m_passthru_mutex);
13241
13242 break;
13243 case MPTIOCTL_GET_ADAPTER_DATA:
13244 /*
13245 * The user has requested to read adapter data. Call
13246 * our routine which does this.
13247 */
13248 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
13249 if (ddi_copyin((void *)data, (void *)&adapter_data,
13250 sizeof (mptsas_adapter_data_t), mode)) {
13251 status = EFAULT;
13252 break;
13253 }
13254 if (adapter_data.StructureLength >=
13255 sizeof (mptsas_adapter_data_t)) {
13256 adapter_data.StructureLength = (uint32_t)
13257 sizeof (mptsas_adapter_data_t);
13258 copylen = sizeof (mptsas_adapter_data_t);
13259 mutex_enter(&mpt->m_mutex);
13260 mptsas_read_adapter_data(mpt, &adapter_data);
13261 mutex_exit(&mpt->m_mutex);
13262 } else {
13263 adapter_data.StructureLength = (uint32_t)
13264 sizeof (mptsas_adapter_data_t);
13265 copylen = sizeof (adapter_data.StructureLength);
13266 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
13267 }
13268 if (ddi_copyout((void *)(&adapter_data), (void *)data,
13269 copylen, mode) != 0) {
13270 status = EFAULT;
13271 }
13272 break;
13273 case MPTIOCTL_GET_PCI_INFO:
13274 /*
13275 * The user has requested to read pci info. Call
13276 * our routine which does this.
13277 */
13278 bzero(&pci_info, sizeof (mptsas_pci_info_t));
13279 mutex_enter(&mpt->m_mutex);
13280 mptsas_read_pci_info(mpt, &pci_info);
13281 mutex_exit(&mpt->m_mutex);
13282 if (ddi_copyout((void *)(&pci_info), (void *)data,
13283 sizeof (mptsas_pci_info_t), mode) != 0) {
13284 status = EFAULT;
13285 }
13286 break;
13287 case MPTIOCTL_RESET_ADAPTER:
13288 mutex_enter(&mpt->m_mutex);
13289 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
13290 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
13291 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
13292 "failed");
13293 status = EFAULT;
13294 }
13295 mutex_exit(&mpt->m_mutex);
13296 break;
13297 case MPTIOCTL_DIAG_ACTION:
13298 /*
13299 * The user has done a diag buffer action. Call our
13300 * routine which does this. Only allow one diag action
13301 * at one time.
13302 */
13303 mutex_enter(&mpt->m_mutex);
13304 if (mpt->m_diag_action_in_progress) {
13305 mutex_exit(&mpt->m_mutex);
13306 return (EBUSY);
13307 }
13308 mpt->m_diag_action_in_progress = 1;
13309 status = mptsas_diag_action(mpt,
13310 (mptsas_diag_action_t *)data, mode);
13311 mpt->m_diag_action_in_progress = 0;
13312 mutex_exit(&mpt->m_mutex);
13313 break;
13314 case MPTIOCTL_EVENT_QUERY:
13315 /*
13316 * The user has done an event query. Call our routine
13317 * which does this.
13318 */
13319 status = mptsas_event_query(mpt,
13320 (mptsas_event_query_t *)data, mode, rval);
13321 break;
13322 case MPTIOCTL_EVENT_ENABLE:
13323 /*
13324 * The user has done an event enable. Call our routine
13325 * which does this.
13326 */
13327 status = mptsas_event_enable(mpt,
13328 (mptsas_event_enable_t *)data, mode, rval);
13329 break;
13330 case MPTIOCTL_EVENT_REPORT:
13331 /*
13332 * The user has done an event report. Call our routine
13333 * which does this.
13334 */
13335 status = mptsas_event_report(mpt,
13336 (mptsas_event_report_t *)data, mode, rval);
13337 break;
13338 case MPTIOCTL_REG_ACCESS:
13339 /*
13340 * The user has requested register access. Call our
13341 * routine which does this.
13342 */
13343 status = mptsas_reg_access(mpt,
13344 (mptsas_reg_access_t *)data, mode);
13345 break;
13346 default:
13347 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
13348 rval);
13349 break;
13350 }
13351
13352 out:
13353 return (status);
13354 }
13355
13356 int
13357 mptsas_restart_ioc(mptsas_t *mpt)
13358 {
13359 int rval = DDI_SUCCESS;
13360 mptsas_target_t *ptgt = NULL;
13361
13362 ASSERT(mutex_owned(&mpt->m_mutex));
13363
13364 /*
13365 * Set a flag telling I/O path that we're processing a reset. This is
13366 * needed because after the reset is complete, the hash table still
13367 * needs to be rebuilt. If I/Os are started before the hash table is
13368 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
13369 * so that they can be retried.
13370 */
13371 mpt->m_in_reset = TRUE;
13372
13373 /*
13374 * Set all throttles to HOLD
13375 */
13376 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13377 ptgt = refhash_next(mpt->m_targets, ptgt)) {
13378 mptsas_set_throttle_mtx(mpt, ptgt, HOLD_THROTTLE);
13379 }
13380
13381 /*
13382 * Disable interrupts
13383 */
13384 MPTSAS_DISABLE_INTR(mpt);
13385
13386 /*
13387 * Abort all commands: outstanding commands, commands in waitq and
13388 * tx_waitq.
13389 */
13390 mptsas_flush_hba(mpt);
13391
13392 /*
13393 * Reinitialize the chip.
13394 */
13395 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
13396 rval = DDI_FAILURE;
13397 }
13398
13399 /*
13400 * Enable interrupts again
13401 */
13402 MPTSAS_ENABLE_INTR(mpt);
13403
13404 /*
13405 * If mptsas_init_chip was successful, update the driver data.
13406 */
13407 if (rval == DDI_SUCCESS) {
13408 mptsas_update_driver_data(mpt);
13409 }
13410
13411 /*
13412 * Reset the throttles
13413 */
13414 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
13415 ptgt = refhash_next(mpt->m_targets, ptgt)) {
13416 mptsas_set_throttle_mtx(mpt, ptgt, MAX_THROTTLE);
13417 }
13418
13419 mptsas_doneq_empty(mpt);
13420 mptsas_restart_hba(mpt);
13421
13422 if (rval != DDI_SUCCESS) {
13423 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
13424 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
13425 }
13426
13427 /*
13428 * Clear the reset flag so that I/Os can continue.
13429 */
13430 mpt->m_in_reset = FALSE;
13431
13432 return (rval);
13433 }
13434
13435 static int
13436 mptsas_init_chip(mptsas_t *mpt, int first_time)
13437 {
13438 ddi_dma_cookie_t cookie;
13439 mptsas_reply_pqueue_t *rpqp;
13440 uint32_t i, j;
13441 int rval;
13442
13443 /*
13444 * Check to see if the firmware image is valid
13445 */
13446 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
13447 MPI2_DIAG_FLASH_BAD_SIG) {
13448 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
13449 goto fail;
13450 }
13451
13452 /*
13453 * Reset the chip
13454 */
13455 rval = mptsas_ioc_reset(mpt, first_time);
13456 if (rval == MPTSAS_RESET_FAIL) {
13457 mptsas_log(mpt, CE_WARN, "hard reset failed!");
13458 goto fail;
13459 }
13460
13461 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
13462 goto mur;
13463 }
13464 /*
13465 * Setup configuration space
13466 */
13467 if (mptsas_config_space_init(mpt) == FALSE) {
13468 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
13469 "failed!");
13470 goto fail;
13471 }
13472
13473 /*
13474 * IOC facts can change after a diag reset so all buffers that are
13475 * based on these numbers must be de-allocated and re-allocated. Get
13476 * new IOC facts each time chip is initialized.
13477 */
13478 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
13479 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
13480 goto fail;
13481 }
13482
13483 /*
13484 * Now we know chip MSIX capabilitites and it's not been done
13485 * previously register interrupts accordingly. Need to know this
13486 * information before allocating the reply frames below.
13487 */
13488 if (mpt->m_intr_cnt == 0) {
13489 if (mptsas_register_intrs(mpt) == FALSE)
13490 goto fail;
13491 }
13492
13493 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT,
13494 mptsas_target_addr_hash, mptsas_target_addr_cmp,
13495 mptsas_target_free, sizeof (mptsas_target_t),
13496 offsetof(mptsas_target_t, m_link),
13497 offsetof(mptsas_target_t, m_addr), KM_SLEEP);
13498
13499 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
13500 goto fail;
13501 }
13502 /*
13503 * Allocate request message frames, reply free queue, reply descriptor
13504 * post queue, and reply message frames using latest IOC facts.
13505 */
13506 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
13507 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
13508 goto fail;
13509 }
13510 if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) {
13511 mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed");
13512 goto fail;
13513 }
13514 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
13515 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
13516 goto fail;
13517 }
13518 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
13519 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
13520 goto fail;
13521 }
13522 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
13523 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
13524 goto fail;
13525 }
13526
13527 mur:
13528 /*
13529 * Re-Initialize ioc to operational state
13530 */
13531 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
13532 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
13533 goto fail;
13534 }
13535
13536 mptsas_alloc_reply_args(mpt);
13537
13538 /*
13539 * Initialize the Reply Free Queue with the physical addresses of our
13540 * reply frames.
13541 */
13542 cookie.dmac_address = mpt->m_reply_frame_dma_addr&0xfffffffful;
13543 for (i = 0; i < mpt->m_max_replies; i++) {
13544 ddi_put32(mpt->m_acc_free_queue_hdl,
13545 &((uint32_t *)(void *)mpt->m_free_queue)[i],
13546 cookie.dmac_address);
13547 cookie.dmac_address += mpt->m_reply_frame_size;
13548 }
13549 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
13550 DDI_DMA_SYNC_FORDEV);
13551
13552 /*
13553 * Initialize the reply free index to one past the last frame on the
13554 * queue. This will signify that the queue is empty to start with.
13555 */
13556 mpt->m_free_index = i;
13557 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
13558
13559 /*
13560 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's
13561 * and the indexes to 0.
13562 */
13563 rpqp = mpt->m_rep_post_queues;
13564 for (j = 0; j < mpt->m_post_reply_qcount; j++) {
13565 for (i = 0; i < mpt->m_post_queue_depth; i++) {
13566 ddi_put64(mpt->m_acc_post_queue_hdl,
13567 &((uint64_t *)(void *)rpqp->rpq_queue)[i],
13568 0xFFFFFFFFFFFFFFFF);
13569 }
13570 rpqp->rpq_index = 0;
13571 rpqp++;
13572 }
13573 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
13574 DDI_DMA_SYNC_FORDEV);
13575
13576 /*
13577 * Initialise all the reply post queue indexes.
13578 */
13579 for (j = 0; j < mpt->m_post_reply_qcount; j++) {
13580 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyPostHostIndex,
13581 j << MPI2_RPHI_MSIX_INDEX_SHIFT);
13582 }
13583
13584 /*
13585 * Enable ports
13586 */
13587 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
13588 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
13589 goto fail;
13590 }
13591
13592 /*
13593 * enable events
13594 */
13595 if (mptsas_ioc_enable_event_notification(mpt)) {
13596 mptsas_log(mpt, CE_WARN,
13597 "mptsas_ioc_enable_event_notification failed");
13598 goto fail;
13599 }
13600
13601 /*
13602 * We need checks in attach and these.
13603 * chip_init is called in mult. places
13604 */
13605
13606 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
13607 DDI_SUCCESS) ||
13608 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
13609 DDI_SUCCESS) ||
13610 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
13611 DDI_SUCCESS) ||
13612 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
13613 DDI_SUCCESS) ||
13614 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
13615 DDI_SUCCESS) ||
13616 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
13617 DDI_SUCCESS)) {
13618 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13619 goto fail;
13620 }
13621
13622 /* Check all acc handles */
13623 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
13624 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
13625 DDI_SUCCESS) ||
13626 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
13627 DDI_SUCCESS) ||
13628 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
13629 DDI_SUCCESS) ||
13630 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
13631 DDI_SUCCESS) ||
13632 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
13633 DDI_SUCCESS) ||
13634 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
13635 DDI_SUCCESS) ||
13636 (mptsas_check_acc_handle(mpt->m_config_handle) !=
13637 DDI_SUCCESS)) {
13638 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13639 goto fail;
13640 }
13641
13642 return (DDI_SUCCESS);
13643
13644 fail:
13645 return (DDI_FAILURE);
13646 }
13647
13648 static int
13649 mptsas_get_pci_cap(mptsas_t *mpt)
13650 {
13651 ushort_t caps_ptr, cap, cap_count;
13652
13653 if (mpt->m_config_handle == NULL)
13654 return (FALSE);
13655 /*
13656 * Check if capabilities list is supported and if so,
13657 * get initial capabilities pointer and clear bits 0,1.
13658 */
13659 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
13660 & PCI_STAT_CAP) {
13661 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13662 PCI_CONF_CAP_PTR), 4);
13663 } else {
13664 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
13665 }
13666
13667 /*
13668 * Walk capabilities if supported.
13669 */
13670 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
13671
13672 /*
13673 * Check that we haven't exceeded the maximum number of
13674 * capabilities and that the pointer is in a valid range.
13675 */
13676 if (++cap_count > 48) {
13677 mptsas_log(mpt, CE_WARN,
13678 "too many device capabilities.\n");
13679 break;
13680 }
13681 if (caps_ptr < 64) {
13682 mptsas_log(mpt, CE_WARN,
13683 "capabilities pointer 0x%x out of range.\n",
13684 caps_ptr);
13685 break;
13686 }
13687
13688 /*
13689 * Get next capability and check that it is valid.
13690 * For now, we only support power management.
13691 */
13692 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
13693 switch (cap) {
13694 case PCI_CAP_ID_PM:
13695 mptsas_log(mpt, CE_NOTE,
13696 "?mptsas3%d supports power management.\n",
13697 mpt->m_instance);
13698 mpt->m_options |= MPTSAS_OPT_PM;
13699
13700 /* Save PMCSR offset */
13701 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
13702 break;
13703 case PCI_CAP_ID_MSI:
13704 mptsas_log(mpt, CE_NOTE,
13705 "?mptsas3%d supports MSI.\n",
13706 mpt->m_instance);
13707 mpt->m_options |= MPTSAS_OPT_MSI;
13708 break;
13709 case PCI_CAP_ID_MSI_X:
13710 mptsas_log(mpt, CE_NOTE,
13711 "?mptsas3%d supports MSI-X.\n",
13712 mpt->m_instance);
13713 mpt->m_options |= MPTSAS_OPT_MSI_X;
13714 break;
13715 /*
13716 * The following capabilities are valid. Any others
13717 * will cause a message to be logged.
13718 */
13719 case PCI_CAP_ID_VPD:
13720 case PCI_CAP_ID_PCIX:
13721 case PCI_CAP_ID_PCI_E:
13722 break;
13723 default:
13724 mptsas_log(mpt, CE_NOTE,
13725 "?mptsas3%d unrecognized capability "
13726 "0x%x.\n", mpt->m_instance, cap);
13727 break;
13728 }
13729
13730 /*
13731 * Get next capabilities pointer and clear bits 0,1.
13732 */
13733 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13734 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
13735 }
13736 return (TRUE);
13737 }
13738
13739 static int
13740 mptsas_init_pm(mptsas_t *mpt)
13741 {
13742 char pmc_name[16];
13743 char *pmc[] = {
13744 NULL,
13745 "0=Off (PCI D3 State)",
13746 "3=On (PCI D0 State)",
13747 NULL
13748 };
13749 uint16_t pmcsr_stat;
13750
13751 /*
13752 * If PCI's capability does not support PM, then don't need
13753 * to registe the pm-components
13754 */
13755 if (!(mpt->m_options & MPTSAS_OPT_PM))
13756 return (DDI_SUCCESS);
13757 /*
13758 * If power management is supported by this chip, create
13759 * pm-components property for the power management framework
13760 */
13761 (void) sprintf(pmc_name, "NAME=mptsas3%d", mpt->m_instance);
13762 pmc[0] = pmc_name;
13763 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
13764 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
13765 mpt->m_options &= ~MPTSAS_OPT_PM;
13766 mptsas_log(mpt, CE_WARN,
13767 "mptsas3%d: pm-component property creation failed.",
13768 mpt->m_instance);
13769 return (DDI_FAILURE);
13770 }
13771
13772 /*
13773 * Power on device.
13774 */
13775 (void) pm_busy_component(mpt->m_dip, 0);
13776 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
13777 mpt->m_pmcsr_offset);
13778 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
13779 mptsas_log(mpt, CE_WARN, "mptsas3%d: Power up the device",
13780 mpt->m_instance);
13781 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
13782 PCI_PMCSR_D0);
13783 }
13784 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
13785 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
13786 return (DDI_FAILURE);
13787 }
13788 mpt->m_power_level = PM_LEVEL_D0;
13789 /*
13790 * Set pm idle delay.
13791 */
13792 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
13793 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
13794
13795 return (DDI_SUCCESS);
13796 }
13797
13798 static int
13799 mptsas_register_intrs(mptsas_t *mpt)
13800 {
13801 dev_info_t *dip;
13802 int intr_types;
13803
13804 dip = mpt->m_dip;
13805
13806 /* Get supported interrupt types */
13807 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
13808 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
13809 "failed\n");
13810 return (FALSE);
13811 }
13812
13813 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
13814
13815 /*
13816 * Try MSIX first.
13817 */
13818 if (mptsas_enable_msix && (intr_types & DDI_INTR_TYPE_MSIX)) {
13819 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSIX) == DDI_SUCCESS) {
13820 NDBG6(("Using MSI-X interrupt type"));
13821 mpt->m_intr_type = DDI_INTR_TYPE_MSIX;
13822 return (TRUE);
13823 }
13824 }
13825
13826 /*
13827 * Try MSI, but fall back to FIXED
13828 */
13829 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
13830 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
13831 NDBG6(("Using MSI interrupt type"));
13832 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
13833 return (TRUE);
13834 }
13835 }
13836 if (intr_types & DDI_INTR_TYPE_FIXED) {
13837 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
13838 NDBG6(("Using FIXED interrupt type"));
13839 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
13840 return (TRUE);
13841 } else {
13842 NDBG6(("FIXED interrupt registration failed"));
13843 return (FALSE);
13844 }
13845 }
13846
13847 return (FALSE);
13848 }
13849
13850 static void
13851 mptsas_unregister_intrs(mptsas_t *mpt)
13852 {
13853 mptsas_rem_intrs(mpt);
13854 }
13855
13856 /*
13857 * mptsas_add_intrs:
13858 *
13859 * Register FIXED or MSI interrupts.
13860 */
13861 static int
13862 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
13863 {
13864 dev_info_t *dip = mpt->m_dip;
13865 int avail, actual, count = 0;
13866 int i, flag, ret;
13867
13868 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
13869
13870 /* Get number of interrupts */
13871 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
13872 if ((ret != DDI_SUCCESS) || (count <= 0)) {
13873 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
13874 "ret %d count %d\n", ret, count);
13875
13876 return (DDI_FAILURE);
13877 }
13878
13879 /* Get number of interrupts available to this device */
13880 ret = ddi_intr_get_navail(dip, intr_type, &avail);
13881 if ((ret != DDI_SUCCESS) || (avail == 0)) {
13882 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
13883 "ret %d avail %d\n", ret, avail);
13884
13885 return (DDI_FAILURE);
13886 }
13887
13888 if (count < avail) {
13889 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
13890 "navail() returned %d", count, avail);
13891 }
13892
13893 NDBG6(("mptsas_add_intrs:count %d, avail %d", count, avail));
13894
13895 if (intr_type == DDI_INTR_TYPE_MSIX) {
13896 if (!mptsas3_max_msix_intrs) {
13897 return (DDI_FAILURE);
13898 }
13899
13900 /*
13901 * Restrict the number of interrupts, firstly by
13902 * the number returned from the IOCInfo, then by
13903 * overall restriction.
13904 */
13905 if (avail > mpt->m_max_msix_vectors) {
13906 avail = mpt->m_max_msix_vectors?
13907 mpt->m_max_msix_vectors:1;
13908 NDBG6(("mptsas_add_intrs: mmmv avail %d", avail));
13909 }
13910 if (avail > mptsas3_max_msix_intrs) {
13911 avail = mptsas3_max_msix_intrs;
13912 NDBG6(("mptsas_add_intrs: m3mmi avail %d", avail));
13913 }
13914 }
13915 if (intr_type == DDI_INTR_TYPE_MSI) {
13916 NDBG6(("mptsas_add_intrs: MSI avail %d", avail));
13917 avail = 1;
13918 }
13919
13920 /* Allocate an array of interrupt handles */
13921 mpt->m_intr_size = avail * sizeof (ddi_intr_handle_t);
13922 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
13923
13924 flag = DDI_INTR_ALLOC_NORMAL;
13925
13926 /* call ddi_intr_alloc() */
13927 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
13928 avail, &actual, flag);
13929
13930 if ((ret != DDI_SUCCESS) || (actual == 0)) {
13931 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
13932 ret);
13933 kmem_free(mpt->m_htable, mpt->m_intr_size);
13934 return (DDI_FAILURE);
13935 }
13936
13937 NDBG6(("mptsas_add_intrs: actual %d, avail %d", actual, avail));
13938 /* use interrupt count returned or abort? */
13939 if (actual < avail) {
13940 mptsas_log(mpt, CE_NOTE,
13941 "Interrupts requested: %d, received: %d\n",
13942 avail, actual);
13943 }
13944
13945 /*
13946 * Get priority for first msi, assume remaining are all the same
13947 */
13948 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
13949 &mpt->m_intr_pri)) != DDI_SUCCESS) {
13950 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
13951
13952 /* Free already allocated intr */
13953 for (i = 0; i < actual; i++) {
13954 (void) ddi_intr_free(mpt->m_htable[i]);
13955 }
13956
13957 kmem_free(mpt->m_htable, mpt->m_intr_size);
13958 return (DDI_FAILURE);
13959 }
13960
13961 /* Test for high level mutex */
13962 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
13963 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
13964 "Hi level interrupt not supported\n");
13965
13966 /* Free already allocated intr */
13967 for (i = 0; i < actual; i++) {
13968 (void) ddi_intr_free(mpt->m_htable[i]);
13969 }
13970
13971 kmem_free(mpt->m_htable, mpt->m_intr_size);
13972 return (DDI_FAILURE);
13973 }
13974
13975 /* Call ddi_intr_add_handler() */
13976 for (i = 0; i < actual; i++) {
13977 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
13978 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
13979 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
13980 "failed %d\n", ret);
13981
13982 /* Free already allocated intr */
13983 for (i = 0; i < actual; i++) {
13984 (void) ddi_intr_free(mpt->m_htable[i]);
13985 }
13986
13987 kmem_free(mpt->m_htable, mpt->m_intr_size);
13988 return (DDI_FAILURE);
13989 }
13990 }
13991
13992 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
13993 != DDI_SUCCESS) {
13994 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
13995
13996 /* Free already allocated intr */
13997 for (i = 0; i < actual; i++) {
13998 (void) ddi_intr_free(mpt->m_htable[i]);
13999 }
14000
14001 kmem_free(mpt->m_htable, mpt->m_intr_size);
14002 return (DDI_FAILURE);
14003 }
14004
14005 mpt->m_intr_cnt = actual;
14006
14007 /*
14008 * Enable interrupts
14009 */
14010 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
14011 /* Call ddi_intr_block_enable() for MSI interrupts */
14012 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
14013 } else {
14014 /* Call ddi_intr_enable for MSI or FIXED interrupts */
14015 for (i = 0; i < mpt->m_intr_cnt; i++) {
14016 (void) ddi_intr_enable(mpt->m_htable[i]);
14017 }
14018 }
14019
14020 switch (intr_type) {
14021 case DDI_INTR_TYPE_MSIX:
14022 mptsas_log(mpt, CE_NOTE, "?Using %d MSI-X interrupt(s) "
14023 "(Available sys %d, mpt %d, Requested %d)\n",
14024 actual, count, mpt->m_max_msix_vectors, avail);
14025 break;
14026 case DDI_INTR_TYPE_MSI:
14027 mptsas_log(mpt, CE_NOTE, "Using single MSI interrupt\n");
14028 break;
14029 case DDI_INTR_TYPE_FIXED:
14030 default:
14031 mptsas_log(mpt, CE_NOTE, "Using single fixed interrupt\n");
14032 break;
14033 }
14034
14035 return (DDI_SUCCESS);
14036 }
14037
14038 /*
14039 * mptsas_rem_intrs:
14040 *
14041 * Unregister FIXED or MSI interrupts
14042 */
14043 static void
14044 mptsas_rem_intrs(mptsas_t *mpt)
14045 {
14046 int i;
14047
14048 NDBG6(("mptsas_rem_intrs"));
14049
14050 /* Disable all interrupts */
14051 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
14052 /* Call ddi_intr_block_disable() */
14053 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
14054 } else {
14055 for (i = 0; i < mpt->m_intr_cnt; i++) {
14056 (void) ddi_intr_disable(mpt->m_htable[i]);
14057 }
14058 }
14059
14060 /* Call ddi_intr_remove_handler() */
14061 for (i = 0; i < mpt->m_intr_cnt; i++) {
14062 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
14063 (void) ddi_intr_free(mpt->m_htable[i]);
14064 }
14065 kmem_free(mpt->m_htable, mpt->m_intr_size);
14066 mpt->m_intr_cnt = 0;
14067 }
14068
14069 /*
14070 * The IO fault service error handling callback function
14071 */
14072 /*ARGSUSED*/
14073 static int
14074 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
14075 {
14076 /*
14077 * as the driver can always deal with an error in any dma or
14078 * access handle, we can just return the fme_status value.
14079 */
14080 pci_ereport_post(dip, err, NULL);
14081 return (err->fme_status);
14082 }
14083
14084 /*
14085 * mptsas_fm_init - initialize fma capabilities and register with IO
14086 * fault services.
14087 */
14088 static void
14089 mptsas_fm_init(mptsas_t *mpt)
14090 {
14091 /*
14092 * Need to change iblock to priority for new MSI intr
14093 */
14094 ddi_iblock_cookie_t fm_ibc;
14095
14096 /* Only register with IO Fault Services if we have some capability */
14097 if (mpt->m_fm_capabilities) {
14098 /* Adjust access and dma attributes for FMA */
14099 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
14100 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
14101 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
14102
14103 /*
14104 * Register capabilities with IO Fault Services.
14105 * mpt->m_fm_capabilities will be updated to indicate
14106 * capabilities actually supported (not requested.)
14107 */
14108 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
14109
14110 /*
14111 * Initialize pci ereport capabilities if ereport
14112 * capable (should always be.)
14113 */
14114 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
14115 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
14116 pci_ereport_setup(mpt->m_dip);
14117 }
14118
14119 /*
14120 * Register error callback if error callback capable.
14121 */
14122 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
14123 ddi_fm_handler_register(mpt->m_dip,
14124 mptsas_fm_error_cb, (void *) mpt);
14125 }
14126 }
14127 }
14128
14129 /*
14130 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
14131 * fault services.
14132 *
14133 */
14134 static void
14135 mptsas_fm_fini(mptsas_t *mpt)
14136 {
14137 /* Only unregister FMA capabilities if registered */
14138 if (mpt->m_fm_capabilities) {
14139
14140 /*
14141 * Un-register error callback if error callback capable.
14142 */
14143
14144 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
14145 ddi_fm_handler_unregister(mpt->m_dip);
14146 }
14147
14148 /*
14149 * Release any resources allocated by pci_ereport_setup()
14150 */
14151
14152 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
14153 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
14154 pci_ereport_teardown(mpt->m_dip);
14155 }
14156
14157 /* Unregister from IO Fault Services */
14158 ddi_fm_fini(mpt->m_dip);
14159
14160 /* Adjust access and dma attributes for FMA */
14161 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
14162 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
14163 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
14164
14165 }
14166 }
14167
14168 int
14169 mptsas_check_acc_handle(ddi_acc_handle_t handle)
14170 {
14171 ddi_fm_error_t de;
14172
14173 if (handle == NULL)
14174 return (DDI_FAILURE);
14175 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
14176 return (de.fme_status);
14177 }
14178
14179 int
14180 mptsas_check_dma_handle(ddi_dma_handle_t handle)
14181 {
14182 ddi_fm_error_t de;
14183
14184 if (handle == NULL)
14185 return (DDI_FAILURE);
14186 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
14187 return (de.fme_status);
14188 }
14189
14190 void
14191 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
14192 {
14193 uint64_t ena;
14194 char buf[FM_MAX_CLASS];
14195
14196 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
14197 ena = fm_ena_generate(0, FM_ENA_FMT1);
14198 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
14199 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
14200 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
14201 }
14202 }
14203
14204 static int
14205 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
14206 uint16_t *dev_handle, mptsas_target_t **pptgt)
14207 {
14208 int rval;
14209 uint32_t dev_info;
14210 uint64_t sas_wwn;
14211 mptsas_phymask_t phymask;
14212 uint8_t physport, phynum, config, disk;
14213 uint64_t devicename;
14214 uint16_t pdev_hdl;
14215 mptsas_target_t *tmp_tgt = NULL;
14216 uint16_t bay_num, enclosure, io_flags;
14217
14218 ASSERT(*pptgt == NULL);
14219
14220 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
14221 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
14222 &bay_num, &enclosure, &io_flags);
14223 if (rval != DDI_SUCCESS) {
14224 rval = DEV_INFO_FAIL_PAGE0;
14225 return (rval);
14226 }
14227
14228 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
14229 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14230 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
14231 rval = DEV_INFO_WRONG_DEVICE_TYPE;
14232 return (rval);
14233 }
14234
14235 /*
14236 * Check if the dev handle is for a Phys Disk. If so, set return value
14237 * and exit. Don't add Phys Disks to hash.
14238 */
14239 for (config = 0; config < mpt->m_num_raid_configs; config++) {
14240 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
14241 if (*dev_handle == mpt->m_raidconfig[config].
14242 m_physdisk_devhdl[disk]) {
14243 rval = DEV_INFO_PHYS_DISK;
14244 return (rval);
14245 }
14246 }
14247 }
14248
14249 /*
14250 * Get SATA Device Name from SAS device page0 for
14251 * sata device, if device name doesn't exist, set mta_wwn to
14252 * 0 for direct attached SATA. For the device behind the expander
14253 * we still can use STP address assigned by expander.
14254 */
14255 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14256 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14257 mutex_exit(&mpt->m_mutex);
14258 /* alloc a tmp_tgt to send the cmd */
14259 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target),
14260 KM_SLEEP);
14261 tmp_tgt->m_devhdl = *dev_handle;
14262 tmp_tgt->m_deviceinfo = dev_info;
14263 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
14264 tmp_tgt->m_qfull_retry_interval =
14265 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
14266 tmp_tgt->m_t_throttle = MAX_THROTTLE;
14267 mutex_init(&tmp_tgt->m_t_mutex, NULL, MUTEX_DRIVER, NULL);
14268 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
14269 mutex_destroy(&tmp_tgt->m_t_mutex);
14270 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
14271 mutex_enter(&mpt->m_mutex);
14272 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
14273 sas_wwn = devicename;
14274 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
14275 sas_wwn = 0;
14276 }
14277 }
14278
14279 phymask = mptsas_physport_to_phymask(mpt, physport);
14280 *pptgt = mptsas_tgt_alloc(mpt, *dev_handle, sas_wwn,
14281 dev_info, phymask, phynum);
14282 if (*pptgt == NULL) {
14283 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
14284 "structure!");
14285 rval = DEV_INFO_FAIL_ALLOC;
14286 return (rval);
14287 }
14288 (*pptgt)->m_io_flags = io_flags;
14289 (*pptgt)->m_enclosure = enclosure;
14290 (*pptgt)->m_slot_num = bay_num;
14291 return (DEV_INFO_SUCCESS);
14292 }
14293
14294 uint64_t
14295 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
14296 {
14297 uint64_t sata_guid = 0, *pwwn = NULL;
14298 int target = ptgt->m_devhdl;
14299 uchar_t *inq83 = NULL;
14300 int inq83_len = 0xFF;
14301 uchar_t *dblk = NULL;
14302 int inq83_retry = 3;
14303 int rval = DDI_FAILURE;
14304
14305 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
14306
14307 inq83_retry:
14308 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
14309 inq83_len, NULL, 1);
14310 if (rval != DDI_SUCCESS) {
14311 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
14312 "0x83 for target:%x, lun:%x failed!", target, lun);
14313 goto out;
14314 }
14315 /* According to SAT2, the first descriptor is logic unit name */
14316 dblk = &inq83[4];
14317 if ((dblk[1] & 0x30) != 0) {
14318 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
14319 goto out;
14320 }
14321 pwwn = (uint64_t *)(void *)(&dblk[4]);
14322 if ((dblk[4] & 0xf0) == 0x50) {
14323 sata_guid = BE_64(*pwwn);
14324 goto out;
14325 } else if (dblk[4] == 'A') {
14326 NDBG20(("SATA drive has no NAA format GUID."));
14327 goto out;
14328 } else {
14329 /* The data is not ready, wait and retry */
14330 inq83_retry--;
14331 if (inq83_retry <= 0) {
14332 goto out;
14333 }
14334 NDBG20(("The GUID is not ready, retry..."));
14335 delay(1 * drv_usectohz(1000000));
14336 goto inq83_retry;
14337 }
14338 out:
14339 kmem_free(inq83, inq83_len);
14340 return (sata_guid);
14341 }
14342
14343 static int
14344 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
14345 unsigned char *buf, int len, int *reallen, uchar_t evpd)
14346 {
14347 uchar_t cdb[CDB_GROUP0];
14348 struct scsi_address ap;
14349 struct buf *data_bp = NULL;
14350 int resid = 0;
14351 int ret = DDI_FAILURE;
14352
14353 ASSERT(len <= 0xffff);
14354
14355 ap.a_target = MPTSAS_INVALID_DEVHDL;
14356 ap.a_lun = (uchar_t)(lun);
14357 ap.a_hba_tran = mpt->m_tran;
14358
14359 data_bp = scsi_alloc_consistent_buf(&ap,
14360 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
14361 if (data_bp == NULL) {
14362 return (ret);
14363 }
14364 bzero(cdb, CDB_GROUP0);
14365 cdb[0] = SCMD_INQUIRY;
14366 cdb[1] = evpd;
14367 cdb[2] = page;
14368 cdb[3] = (len & 0xff00) >> 8;
14369 cdb[4] = (len & 0x00ff);
14370 cdb[5] = 0;
14371
14372 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
14373 &resid);
14374 if (ret == DDI_SUCCESS) {
14375 if (reallen) {
14376 *reallen = len - resid;
14377 }
14378 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
14379 }
14380 if (data_bp) {
14381 scsi_free_consistent_buf(data_bp);
14382 }
14383 return (ret);
14384 }
14385
14386 static int
14387 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
14388 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
14389 int *resid)
14390 {
14391 struct scsi_pkt *pktp = NULL;
14392 scsi_hba_tran_t *tran_clone = NULL;
14393 mptsas_tgt_private_t *tgt_private = NULL;
14394 int ret = DDI_FAILURE;
14395
14396 /*
14397 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
14398 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
14399 * to simulate the cmds from sd
14400 */
14401 tran_clone = kmem_alloc(
14402 sizeof (scsi_hba_tran_t), KM_SLEEP);
14403 if (tran_clone == NULL) {
14404 goto out;
14405 }
14406 bcopy((caddr_t)mpt->m_tran,
14407 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
14408 tgt_private = kmem_alloc(
14409 sizeof (mptsas_tgt_private_t), KM_SLEEP);
14410 if (tgt_private == NULL) {
14411 goto out;
14412 }
14413 tgt_private->t_lun = ap->a_lun;
14414 tgt_private->t_private = ptgt;
14415 tran_clone->tran_tgt_private = tgt_private;
14416 ap->a_hba_tran = tran_clone;
14417
14418 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
14419 data_bp, cdblen, sizeof (struct scsi_arq_status),
14420 0, PKT_CONSISTENT, NULL, NULL);
14421 if (pktp == NULL) {
14422 goto out;
14423 }
14424 bcopy(cdb, pktp->pkt_cdbp, cdblen);
14425 pktp->pkt_flags = FLAG_NOPARITY;
14426 pktp->pkt_time = mptsas_scsi_pkt_time;
14427 if (scsi_poll(pktp) < 0) {
14428 goto out;
14429 }
14430 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
14431 goto out;
14432 }
14433 if (resid != NULL) {
14434 *resid = pktp->pkt_resid;
14435 }
14436
14437 ret = DDI_SUCCESS;
14438 out:
14439 if (pktp) {
14440 scsi_destroy_pkt(pktp);
14441 }
14442 if (tran_clone) {
14443 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
14444 }
14445 if (tgt_private) {
14446 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
14447 }
14448 return (ret);
14449 }
14450 static int
14451 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
14452 {
14453 char *cp = NULL;
14454 char *ptr = NULL;
14455 size_t s = 0;
14456 char *wwid_str = NULL;
14457 char *lun_str = NULL;
14458 long lunnum;
14459 long phyid = -1;
14460 int rc = DDI_FAILURE;
14461
14462 ptr = name;
14463 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
14464 ptr++;
14465 if ((cp = strchr(ptr, ',')) == NULL) {
14466 return (DDI_FAILURE);
14467 }
14468
14469 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14470 s = (uintptr_t)cp - (uintptr_t)ptr;
14471
14472 bcopy(ptr, wwid_str, s);
14473 wwid_str[s] = '\0';
14474
14475 ptr = ++cp;
14476
14477 if ((cp = strchr(ptr, '\0')) == NULL) {
14478 goto out;
14479 }
14480 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14481 s = (uintptr_t)cp - (uintptr_t)ptr;
14482
14483 bcopy(ptr, lun_str, s);
14484 lun_str[s] = '\0';
14485
14486 if (name[0] == 'p') {
14487 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
14488 } else {
14489 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
14490 }
14491 if (rc != DDI_SUCCESS)
14492 goto out;
14493
14494 if (phyid != -1) {
14495 ASSERT(phyid < MPTSAS_MAX_PHYS);
14496 *phy = (uint8_t)phyid;
14497 }
14498 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
14499 if (rc != 0)
14500 goto out;
14501
14502 *lun = (int)lunnum;
14503 rc = DDI_SUCCESS;
14504 out:
14505 if (wwid_str)
14506 kmem_free(wwid_str, SCSI_MAXNAMELEN);
14507 if (lun_str)
14508 kmem_free(lun_str, SCSI_MAXNAMELEN);
14509
14510 return (rc);
14511 }
14512
14513 /*
14514 * mptsas_parse_smp_name() is to parse sas wwn string
14515 * which format is "wWWN"
14516 */
14517 static int
14518 mptsas_parse_smp_name(char *name, uint64_t *wwn)
14519 {
14520 char *ptr = name;
14521
14522 if (*ptr != 'w') {
14523 return (DDI_FAILURE);
14524 }
14525
14526 ptr++;
14527 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
14528 return (DDI_FAILURE);
14529 }
14530 return (DDI_SUCCESS);
14531 }
14532
14533 static int
14534 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
14535 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
14536 {
14537 int ret = NDI_FAILURE;
14538 int circ = 0;
14539 int circ1 = 0;
14540 mptsas_t *mpt;
14541 char *ptr = NULL;
14542 char *devnm = NULL;
14543 uint64_t wwid = 0;
14544 uint8_t phy = 0xFF;
14545 int lun = 0;
14546 uint_t mflags = flag;
14547 int bconfig = TRUE;
14548
14549 if (scsi_hba_iport_unit_address(pdip) == 0) {
14550 return (DDI_FAILURE);
14551 }
14552
14553 mpt = DIP2MPT(pdip);
14554 if (!mpt) {
14555 return (DDI_FAILURE);
14556 }
14557 /*
14558 * Hold the nexus across the bus_config
14559 */
14560 ndi_devi_enter(scsi_vhci_dip, &circ);
14561 ndi_devi_enter(pdip, &circ1);
14562 switch (op) {
14563 case BUS_CONFIG_ONE:
14564 /* parse wwid/target name out of name given */
14565 if ((ptr = strchr((char *)arg, '@')) == NULL) {
14566 ret = NDI_FAILURE;
14567 break;
14568 }
14569 ptr++;
14570 if (strncmp((char *)arg, "smp", 3) == 0) {
14571 /*
14572 * This is a SMP target device
14573 */
14574 ret = mptsas_parse_smp_name(ptr, &wwid);
14575 if (ret != DDI_SUCCESS) {
14576 ret = NDI_FAILURE;
14577 break;
14578 }
14579 ret = mptsas_config_smp(pdip, wwid, childp);
14580 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
14581 /*
14582 * OBP could pass down a non-canonical form
14583 * bootpath without LUN part when LUN is 0.
14584 * So driver need adjust the string.
14585 */
14586 if (strchr(ptr, ',') == NULL) {
14587 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14588 (void) sprintf(devnm, "%s,0", (char *)arg);
14589 ptr = strchr(devnm, '@');
14590 ptr++;
14591 }
14592
14593 /*
14594 * The device path is wWWID format and the device
14595 * is not SMP target device.
14596 */
14597 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
14598 if (ret != DDI_SUCCESS) {
14599 ret = NDI_FAILURE;
14600 break;
14601 }
14602 *childp = NULL;
14603 if (ptr[0] == 'w') {
14604 ret = mptsas_config_one_addr(pdip, wwid,
14605 lun, childp);
14606 } else if (ptr[0] == 'p') {
14607 ret = mptsas_config_one_phy(pdip, phy, lun,
14608 childp);
14609 }
14610
14611 /*
14612 * If this is CD/DVD device in OBP path, the
14613 * ndi_busop_bus_config can be skipped as config one
14614 * operation is done above.
14615 */
14616 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
14617 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
14618 (strncmp((char *)arg, "disk", 4) == 0)) {
14619 bconfig = FALSE;
14620 ndi_hold_devi(*childp);
14621 }
14622 } else {
14623 ret = NDI_FAILURE;
14624 break;
14625 }
14626
14627 /*
14628 * DDI group instructed us to use this flag.
14629 */
14630 mflags |= NDI_MDI_FALLBACK;
14631 break;
14632 case BUS_CONFIG_DRIVER:
14633 case BUS_CONFIG_ALL:
14634 mptsas_config_all(pdip);
14635 ret = NDI_SUCCESS;
14636 break;
14637 }
14638
14639 if ((ret == NDI_SUCCESS) && bconfig) {
14640 ret = ndi_busop_bus_config(pdip, mflags, op,
14641 (devnm == NULL) ? arg : devnm, childp, 0);
14642 }
14643
14644 ndi_devi_exit(pdip, circ1);
14645 ndi_devi_exit(scsi_vhci_dip, circ);
14646 if (devnm != NULL)
14647 kmem_free(devnm, SCSI_MAXNAMELEN);
14648 return (ret);
14649 }
14650
14651 static int
14652 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
14653 mptsas_target_t *ptgt)
14654 {
14655 int rval = DDI_FAILURE;
14656 struct scsi_inquiry *sd_inq = NULL;
14657 mptsas_t *mpt = DIP2MPT(pdip);
14658
14659 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14660
14661 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
14662 SUN_INQSIZE, 0, (uchar_t)0);
14663
14664 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14665 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
14666 } else {
14667 rval = DDI_FAILURE;
14668 }
14669
14670 kmem_free(sd_inq, SUN_INQSIZE);
14671 return (rval);
14672 }
14673
14674 static int
14675 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
14676 dev_info_t **lundip)
14677 {
14678 int rval;
14679 mptsas_t *mpt = DIP2MPT(pdip);
14680 int phymask;
14681 mptsas_target_t *ptgt = NULL;
14682
14683 /*
14684 * Get the physical port associated to the iport
14685 */
14686 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14687 "phymask", 0);
14688
14689 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
14690 if (ptgt == NULL) {
14691 /*
14692 * didn't match any device by searching
14693 */
14694 return (DDI_FAILURE);
14695 }
14696 /*
14697 * If the LUN already exists and the status is online,
14698 * we just return the pointer to dev_info_t directly.
14699 * For the mdi_pathinfo node, we'll handle it in
14700 * mptsas_create_virt_lun()
14701 * TODO should be also in mptsas_handle_dr
14702 */
14703
14704 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
14705 if (*lundip != NULL) {
14706 /*
14707 * TODO Another senario is, we hotplug the same disk
14708 * on the same slot, the devhdl changed, is this
14709 * possible?
14710 * tgt_private->t_private != ptgt
14711 */
14712 if (sasaddr != ptgt->m_addr.mta_wwn) {
14713 /*
14714 * The device has changed although the devhdl is the
14715 * same (Enclosure mapping mode, change drive on the
14716 * same slot)
14717 */
14718 return (DDI_FAILURE);
14719 }
14720 return (DDI_SUCCESS);
14721 }
14722
14723 if (phymask == 0) {
14724 /*
14725 * Configure IR volume
14726 */
14727 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
14728 return (rval);
14729 }
14730 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14731
14732 return (rval);
14733 }
14734
14735 static int
14736 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
14737 dev_info_t **lundip)
14738 {
14739 int rval;
14740 mptsas_t *mpt = DIP2MPT(pdip);
14741 mptsas_phymask_t phymask;
14742 mptsas_target_t *ptgt = NULL;
14743
14744 /*
14745 * Get the physical port associated to the iport
14746 */
14747 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14748 "phymask", 0);
14749
14750 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
14751 if (ptgt == NULL) {
14752 /*
14753 * didn't match any device by searching
14754 */
14755 return (DDI_FAILURE);
14756 }
14757
14758 /*
14759 * If the LUN already exists and the status is online,
14760 * we just return the pointer to dev_info_t directly.
14761 * For the mdi_pathinfo node, we'll handle it in
14762 * mptsas_create_virt_lun().
14763 */
14764
14765 *lundip = mptsas_find_child_phy(pdip, phy);
14766 if (*lundip != NULL) {
14767 return (DDI_SUCCESS);
14768 }
14769
14770 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14771
14772 return (rval);
14773 }
14774
14775 static int
14776 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
14777 uint8_t *lun_addr_type)
14778 {
14779 uint32_t lun_idx = 0;
14780
14781 ASSERT(lun_num != NULL);
14782 ASSERT(lun_addr_type != NULL);
14783
14784 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14785 /* determine report luns addressing type */
14786 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
14787 /*
14788 * Vendors in the field have been found to be concatenating
14789 * bus/target/lun to equal the complete lun value instead
14790 * of switching to flat space addressing
14791 */
14792 /* 00b - peripheral device addressing method */
14793 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
14794 /* FALLTHRU */
14795 /* 10b - logical unit addressing method */
14796 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
14797 /* FALLTHRU */
14798 /* 01b - flat space addressing method */
14799 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
14800 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
14801 *lun_addr_type = (buf[lun_idx] &
14802 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
14803 *lun_num = (buf[lun_idx] & 0x3F) << 8;
14804 *lun_num |= buf[lun_idx + 1];
14805 return (DDI_SUCCESS);
14806 default:
14807 return (DDI_FAILURE);
14808 }
14809 }
14810
14811 static int
14812 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
14813 {
14814 struct buf *repluns_bp = NULL;
14815 struct scsi_address ap;
14816 uchar_t cdb[CDB_GROUP5];
14817 int ret = DDI_FAILURE;
14818 int retry = 0;
14819 int lun_list_len = 0;
14820 uint16_t lun_num = 0;
14821 uint8_t lun_addr_type = 0;
14822 uint32_t lun_cnt = 0;
14823 uint32_t lun_total = 0;
14824 dev_info_t *cdip = NULL;
14825 uint16_t *saved_repluns = NULL;
14826 char *buffer = NULL;
14827 int buf_len = 128;
14828 mptsas_t *mpt = DIP2MPT(pdip);
14829 uint64_t sas_wwn = 0;
14830 uint8_t phy = 0xFF;
14831 uint32_t dev_info = 0;
14832
14833 mutex_enter(&mpt->m_mutex);
14834 sas_wwn = ptgt->m_addr.mta_wwn;
14835 phy = ptgt->m_phynum;
14836 dev_info = ptgt->m_deviceinfo;
14837 mutex_exit(&mpt->m_mutex);
14838
14839 if (sas_wwn == 0) {
14840 /*
14841 * It's a SATA without Device Name
14842 * So don't try multi-LUNs
14843 */
14844 if (mptsas_find_child_phy(pdip, phy)) {
14845 return (DDI_SUCCESS);
14846 } else {
14847 /*
14848 * need configure and create node
14849 */
14850 return (DDI_FAILURE);
14851 }
14852 }
14853
14854 /*
14855 * WWN (SAS address or Device Name exist)
14856 */
14857 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14858 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14859 /*
14860 * SATA device with Device Name
14861 * So don't try multi-LUNs
14862 */
14863 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
14864 return (DDI_SUCCESS);
14865 } else {
14866 return (DDI_FAILURE);
14867 }
14868 }
14869
14870 do {
14871 ap.a_target = MPTSAS_INVALID_DEVHDL;
14872 ap.a_lun = 0;
14873 ap.a_hba_tran = mpt->m_tran;
14874 repluns_bp = scsi_alloc_consistent_buf(&ap,
14875 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
14876 if (repluns_bp == NULL) {
14877 retry++;
14878 continue;
14879 }
14880 bzero(cdb, CDB_GROUP5);
14881 cdb[0] = SCMD_REPORT_LUNS;
14882 cdb[6] = (buf_len & 0xff000000) >> 24;
14883 cdb[7] = (buf_len & 0x00ff0000) >> 16;
14884 cdb[8] = (buf_len & 0x0000ff00) >> 8;
14885 cdb[9] = (buf_len & 0x000000ff);
14886
14887 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
14888 repluns_bp, NULL);
14889 if (ret != DDI_SUCCESS) {
14890 scsi_free_consistent_buf(repluns_bp);
14891 retry++;
14892 continue;
14893 }
14894 lun_list_len = BE_32(*(int *)((void *)(
14895 repluns_bp->b_un.b_addr)));
14896 if (buf_len >= lun_list_len + 8) {
14897 ret = DDI_SUCCESS;
14898 break;
14899 }
14900 scsi_free_consistent_buf(repluns_bp);
14901 buf_len = lun_list_len + 8;
14902
14903 } while (retry < 3);
14904
14905 if (ret != DDI_SUCCESS)
14906 return (ret);
14907 buffer = (char *)repluns_bp->b_un.b_addr;
14908 /*
14909 * find out the number of luns returned by the SCSI ReportLun call
14910 * and allocate buffer space
14911 */
14912 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14913 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
14914 if (saved_repluns == NULL) {
14915 scsi_free_consistent_buf(repluns_bp);
14916 return (DDI_FAILURE);
14917 }
14918 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
14919 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
14920 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
14921 continue;
14922 }
14923 saved_repluns[lun_cnt] = lun_num;
14924 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
14925 ret = DDI_SUCCESS;
14926 else
14927 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
14928 ptgt);
14929 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
14930 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
14931 MPTSAS_DEV_GONE);
14932 }
14933 }
14934 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
14935 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
14936 scsi_free_consistent_buf(repluns_bp);
14937 return (DDI_SUCCESS);
14938 }
14939
14940 static int
14941 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
14942 {
14943 int rval = DDI_FAILURE;
14944 struct scsi_inquiry *sd_inq = NULL;
14945 mptsas_t *mpt = DIP2MPT(pdip);
14946 mptsas_target_t *ptgt = NULL;
14947
14948 mutex_enter(&mpt->m_mutex);
14949 ptgt = refhash_linear_search(mpt->m_targets,
14950 mptsas_target_eval_devhdl, &target);
14951 mutex_exit(&mpt->m_mutex);
14952 if (ptgt == NULL) {
14953 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
14954 "not found.", target);
14955 return (rval);
14956 }
14957
14958 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14959 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
14960 SUN_INQSIZE, 0, (uchar_t)0);
14961
14962 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14963 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
14964 0);
14965 } else {
14966 rval = DDI_FAILURE;
14967 }
14968
14969 kmem_free(sd_inq, SUN_INQSIZE);
14970 return (rval);
14971 }
14972
14973 /*
14974 * configure all RAID volumes for virtual iport
14975 */
14976 static void
14977 mptsas_config_all_viport(dev_info_t *pdip)
14978 {
14979 mptsas_t *mpt = DIP2MPT(pdip);
14980 int config, vol;
14981 int target;
14982 dev_info_t *lundip = NULL;
14983
14984 /*
14985 * Get latest RAID info and search for any Volume DevHandles. If any
14986 * are found, configure the volume.
14987 */
14988 mutex_enter(&mpt->m_mutex);
14989 for (config = 0; config < mpt->m_num_raid_configs; config++) {
14990 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
14991 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid
14992 == 1) {
14993 target = mpt->m_raidconfig[config].
14994 m_raidvol[vol].m_raidhandle;
14995 mutex_exit(&mpt->m_mutex);
14996 (void) mptsas_config_raid(pdip, target,
14997 &lundip);
14998 mutex_enter(&mpt->m_mutex);
14999 }
15000 }
15001 }
15002 mutex_exit(&mpt->m_mutex);
15003 }
15004
15005 static void
15006 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
15007 int lun_cnt, mptsas_target_t *ptgt)
15008 {
15009 dev_info_t *child = NULL, *savechild = NULL;
15010 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
15011 uint64_t sas_wwn, wwid;
15012 uint8_t phy;
15013 int lun;
15014 int i;
15015 int find;
15016 char *addr;
15017 char *nodename;
15018 mptsas_t *mpt = DIP2MPT(pdip);
15019
15020 mutex_enter(&mpt->m_mutex);
15021 wwid = ptgt->m_addr.mta_wwn;
15022 mutex_exit(&mpt->m_mutex);
15023
15024 child = ddi_get_child(pdip);
15025 while (child) {
15026 find = 0;
15027 savechild = child;
15028 child = ddi_get_next_sibling(child);
15029
15030 nodename = ddi_node_name(savechild);
15031 if (strcmp(nodename, "smp") == 0) {
15032 continue;
15033 }
15034
15035 addr = ddi_get_name_addr(savechild);
15036 if (addr == NULL) {
15037 continue;
15038 }
15039
15040 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
15041 DDI_SUCCESS) {
15042 continue;
15043 }
15044
15045 if (wwid == sas_wwn) {
15046 for (i = 0; i < lun_cnt; i++) {
15047 if (repluns[i] == lun) {
15048 find = 1;
15049 break;
15050 }
15051 }
15052 } else {
15053 continue;
15054 }
15055 if (find == 0) {
15056 /*
15057 * The lun has not been there already
15058 */
15059 (void) mptsas_offline_lun(pdip, savechild, NULL,
15060 NDI_DEVI_REMOVE);
15061 }
15062 }
15063
15064 pip = mdi_get_next_client_path(pdip, NULL);
15065 while (pip) {
15066 find = 0;
15067 savepip = pip;
15068 addr = MDI_PI(pip)->pi_addr;
15069
15070 pip = mdi_get_next_client_path(pdip, pip);
15071
15072 if (addr == NULL) {
15073 continue;
15074 }
15075
15076 if (mptsas_parse_address(addr, &sas_wwn, &phy,
15077 &lun) != DDI_SUCCESS) {
15078 continue;
15079 }
15080
15081 if (sas_wwn == wwid) {
15082 for (i = 0; i < lun_cnt; i++) {
15083 if (repluns[i] == lun) {
15084 find = 1;
15085 break;
15086 }
15087 }
15088 } else {
15089 continue;
15090 }
15091
15092 if (find == 0) {
15093 /*
15094 * The lun has not been there already
15095 */
15096 (void) mptsas_offline_lun(pdip, NULL, savepip,
15097 NDI_DEVI_REMOVE);
15098 }
15099 }
15100 }
15101
15102 void
15103 mptsas_update_hashtab(struct mptsas *mpt)
15104 {
15105 uint32_t page_address;
15106 int rval = 0;
15107 uint16_t dev_handle;
15108 mptsas_target_t *ptgt = NULL;
15109 mptsas_smp_t smp_node;
15110
15111 /*
15112 * Get latest RAID info.
15113 */
15114 (void) mptsas_get_raid_info(mpt);
15115
15116 dev_handle = mpt->m_smp_devhdl;
15117 for (; mpt->m_done_traverse_smp == 0; ) {
15118 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
15119 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
15120 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
15121 != DDI_SUCCESS) {
15122 break;
15123 }
15124 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
15125 (void) mptsas_smp_alloc(mpt, &smp_node);
15126 }
15127
15128 /*
15129 * Config target devices
15130 */
15131 dev_handle = mpt->m_dev_handle;
15132
15133 /*
15134 * Do loop to get sas device page 0 by GetNextHandle till the
15135 * the last handle. If the sas device is a SATA/SSP target,
15136 * we try to config it.
15137 */
15138 for (; mpt->m_done_traverse_dev == 0; ) {
15139 ptgt = NULL;
15140 page_address =
15141 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15142 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15143 (uint32_t)dev_handle;
15144 rval = mptsas_get_target_device_info(mpt, page_address,
15145 &dev_handle, &ptgt);
15146 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15147 (rval == DEV_INFO_FAIL_ALLOC)) {
15148 break;
15149 }
15150
15151 mpt->m_dev_handle = dev_handle;
15152 }
15153
15154 }
15155
15156 void
15157 mptsas_update_driver_data(struct mptsas *mpt)
15158 {
15159 mptsas_target_t *tp;
15160 mptsas_smp_t *sp;
15161
15162 ASSERT(MUTEX_HELD(&mpt->m_mutex));
15163
15164 /*
15165 * TODO after hard reset, update the driver data structures
15166 * 1. update port/phymask mapping table mpt->m_phy_info
15167 * 2. invalid all the entries in hash table
15168 * m_devhdl = 0xffff and m_deviceinfo = 0
15169 * 3. call sas_device_page/expander_page to update hash table
15170 */
15171 mptsas_update_phymask(mpt);
15172 /*
15173 * Invalid the existing entries
15174 *
15175 * XXX - It seems like we should just delete everything here. We are
15176 * holding the lock and are about to refresh all the targets in both
15177 * hashes anyway. Given the path we're in, what outstanding async
15178 * event could possibly be trying to reference one of these things
15179 * without taking the lock, and how would that be useful anyway?
15180 */
15181 for (tp = refhash_first(mpt->m_targets); tp != NULL;
15182 tp = refhash_next(mpt->m_targets, tp)) {
15183 tp->m_devhdl = MPTSAS_INVALID_DEVHDL;
15184 tp->m_deviceinfo = 0;
15185 tp->m_dr_flag = MPTSAS_DR_INACTIVE;
15186 }
15187 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
15188 sp = refhash_next(mpt->m_smp_targets, sp)) {
15189 sp->m_devhdl = MPTSAS_INVALID_DEVHDL;
15190 sp->m_deviceinfo = 0;
15191 }
15192 mpt->m_done_traverse_dev = 0;
15193 mpt->m_done_traverse_smp = 0;
15194 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
15195 mptsas_update_hashtab(mpt);
15196 }
15197
15198 static void
15199 mptsas_config_all(dev_info_t *pdip)
15200 {
15201 dev_info_t *smpdip = NULL;
15202 mptsas_t *mpt = DIP2MPT(pdip);
15203 int phymask = 0;
15204 mptsas_phymask_t phy_mask;
15205 mptsas_target_t *ptgt = NULL;
15206 mptsas_smp_t *psmp;
15207
15208 /*
15209 * Get the phymask associated to the iport
15210 */
15211 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
15212 "phymask", 0);
15213
15214 /*
15215 * Enumerate RAID volumes here (phymask == 0).
15216 */
15217 if (phymask == 0) {
15218 mptsas_config_all_viport(pdip);
15219 return;
15220 }
15221
15222 mutex_enter(&mpt->m_mutex);
15223
15224 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
15225 mptsas_update_hashtab(mpt);
15226 }
15227
15228 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL;
15229 psmp = refhash_next(mpt->m_smp_targets, psmp)) {
15230 phy_mask = psmp->m_addr.mta_phymask;
15231 if (phy_mask == phymask) {
15232 smpdip = NULL;
15233 mutex_exit(&mpt->m_mutex);
15234 (void) mptsas_online_smp(pdip, psmp, &smpdip);
15235 mutex_enter(&mpt->m_mutex);
15236 }
15237 }
15238
15239 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
15240 ptgt = refhash_next(mpt->m_targets, ptgt)) {
15241 phy_mask = ptgt->m_addr.mta_phymask;
15242 if (phy_mask == phymask) {
15243 mutex_exit(&mpt->m_mutex);
15244 (void) mptsas_config_target(pdip, ptgt);
15245 mutex_enter(&mpt->m_mutex);
15246 }
15247 }
15248 mutex_exit(&mpt->m_mutex);
15249 }
15250
15251 static int
15252 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
15253 {
15254 int rval = DDI_FAILURE;
15255 dev_info_t *tdip;
15256
15257 rval = mptsas_config_luns(pdip, ptgt);
15258 if (rval != DDI_SUCCESS) {
15259 /*
15260 * The return value means the SCMD_REPORT_LUNS
15261 * did not execute successfully. The target maybe
15262 * doesn't support such command.
15263 */
15264 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
15265 }
15266 return (rval);
15267 }
15268
15269 /*
15270 * Return fail if not all the childs/paths are freed.
15271 * if there is any path under the HBA, the return value will be always fail
15272 * because we didn't call mdi_pi_free for path
15273 */
15274 static int
15275 mptsas_offline_targetdev(dev_info_t *pdip, char *name)
15276 {
15277 dev_info_t *child = NULL, *prechild = NULL;
15278 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
15279 int tmp_rval, rval = DDI_SUCCESS;
15280 char *addr, *cp;
15281 size_t s;
15282 mptsas_t *mpt = DIP2MPT(pdip);
15283
15284 child = ddi_get_child(pdip);
15285 while (child) {
15286 addr = ddi_get_name_addr(child);
15287 prechild = child;
15288 child = ddi_get_next_sibling(child);
15289
15290 if (addr == NULL) {
15291 continue;
15292 }
15293 if ((cp = strchr(addr, ',')) == NULL) {
15294 continue;
15295 }
15296
15297 s = (uintptr_t)cp - (uintptr_t)addr;
15298
15299 if (strncmp(addr, name, s) != 0) {
15300 continue;
15301 }
15302
15303 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
15304 NDI_DEVI_REMOVE);
15305 if (tmp_rval != DDI_SUCCESS) {
15306 rval = DDI_FAILURE;
15307 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15308 prechild, MPTSAS_DEV_GONE) !=
15309 DDI_PROP_SUCCESS) {
15310 mptsas_log(mpt, CE_WARN,
15311 "unable to create property for "
15312 "SAS %s (MPTSAS_DEV_GONE)", addr);
15313 }
15314 }
15315 }
15316
15317 pip = mdi_get_next_client_path(pdip, NULL);
15318 while (pip) {
15319 addr = MDI_PI(pip)->pi_addr;
15320 savepip = pip;
15321 pip = mdi_get_next_client_path(pdip, pip);
15322 if (addr == NULL) {
15323 continue;
15324 }
15325
15326 if ((cp = strchr(addr, ',')) == NULL) {
15327 continue;
15328 }
15329
15330 s = (uintptr_t)cp - (uintptr_t)addr;
15331
15332 if (strncmp(addr, name, s) != 0) {
15333 continue;
15334 }
15335
15336 (void) mptsas_offline_lun(pdip, NULL, savepip,
15337 NDI_DEVI_REMOVE);
15338 /*
15339 * driver will not invoke mdi_pi_free, so path will not
15340 * be freed forever, return DDI_FAILURE.
15341 */
15342 rval = DDI_FAILURE;
15343 }
15344 return (rval);
15345 }
15346
15347 static int
15348 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
15349 mdi_pathinfo_t *rpip, uint_t flags)
15350 {
15351 int rval = DDI_FAILURE;
15352 char *devname;
15353 dev_info_t *cdip, *parent;
15354
15355 if (rpip != NULL) {
15356 parent = scsi_vhci_dip;
15357 cdip = mdi_pi_get_client(rpip);
15358 } else if (rdip != NULL) {
15359 parent = pdip;
15360 cdip = rdip;
15361 } else {
15362 return (DDI_FAILURE);
15363 }
15364
15365 /*
15366 * Make sure node is attached otherwise
15367 * it won't have related cache nodes to
15368 * clean up. i_ddi_devi_attached is
15369 * similiar to i_ddi_node_state(cdip) >=
15370 * DS_ATTACHED.
15371 */
15372 if (i_ddi_devi_attached(cdip)) {
15373
15374 /* Get full devname */
15375 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
15376 (void) ddi_deviname(cdip, devname);
15377 /* Clean cache */
15378 (void) devfs_clean(parent, devname + 1,
15379 DV_CLEAN_FORCE);
15380 kmem_free(devname, MAXNAMELEN + 1);
15381 }
15382 if (rpip != NULL) {
15383 if (MDI_PI_IS_OFFLINE(rpip)) {
15384 rval = DDI_SUCCESS;
15385 } else {
15386 rval = mdi_pi_offline(rpip, 0);
15387 }
15388 } else {
15389 rval = ndi_devi_offline(cdip, flags);
15390 }
15391
15392 return (rval);
15393 }
15394
15395 static dev_info_t *
15396 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
15397 {
15398 dev_info_t *child = NULL;
15399 char *smp_wwn = NULL;
15400
15401 child = ddi_get_child(parent);
15402 while (child) {
15403 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
15404 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
15405 != DDI_SUCCESS) {
15406 child = ddi_get_next_sibling(child);
15407 continue;
15408 }
15409
15410 if (strcmp(smp_wwn, str_wwn) == 0) {
15411 ddi_prop_free(smp_wwn);
15412 break;
15413 }
15414 child = ddi_get_next_sibling(child);
15415 ddi_prop_free(smp_wwn);
15416 }
15417 return (child);
15418 }
15419
15420 static int
15421 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
15422 {
15423 int rval = DDI_FAILURE;
15424 char *devname;
15425 char wwn_str[MPTSAS_WWN_STRLEN];
15426 dev_info_t *cdip;
15427
15428 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
15429
15430 cdip = mptsas_find_smp_child(pdip, wwn_str);
15431
15432 if (cdip == NULL)
15433 return (DDI_SUCCESS);
15434
15435 /*
15436 * Make sure node is attached otherwise
15437 * it won't have related cache nodes to
15438 * clean up. i_ddi_devi_attached is
15439 * similiar to i_ddi_node_state(cdip) >=
15440 * DS_ATTACHED.
15441 */
15442 if (i_ddi_devi_attached(cdip)) {
15443
15444 /* Get full devname */
15445 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
15446 (void) ddi_deviname(cdip, devname);
15447 /* Clean cache */
15448 (void) devfs_clean(pdip, devname + 1,
15449 DV_CLEAN_FORCE);
15450 kmem_free(devname, MAXNAMELEN + 1);
15451 }
15452
15453 rval = ndi_devi_offline(cdip, flags);
15454
15455 return (rval);
15456 }
15457
15458 static dev_info_t *
15459 mptsas_find_child(dev_info_t *pdip, char *name)
15460 {
15461 dev_info_t *child = NULL;
15462 char *rname = NULL;
15463 int rval = DDI_FAILURE;
15464
15465 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15466
15467 child = ddi_get_child(pdip);
15468 while (child) {
15469 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
15470 if (rval != DDI_SUCCESS) {
15471 child = ddi_get_next_sibling(child);
15472 bzero(rname, SCSI_MAXNAMELEN);
15473 continue;
15474 }
15475
15476 if (strcmp(rname, name) == 0) {
15477 break;
15478 }
15479 child = ddi_get_next_sibling(child);
15480 bzero(rname, SCSI_MAXNAMELEN);
15481 }
15482
15483 kmem_free(rname, SCSI_MAXNAMELEN);
15484
15485 return (child);
15486 }
15487
15488
15489 static dev_info_t *
15490 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
15491 {
15492 dev_info_t *child = NULL;
15493 char *name = NULL;
15494 char *addr = NULL;
15495
15496 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15497 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15498 (void) sprintf(name, "%016"PRIx64, sasaddr);
15499 (void) sprintf(addr, "w%s,%x", name, lun);
15500 child = mptsas_find_child(pdip, addr);
15501 kmem_free(name, SCSI_MAXNAMELEN);
15502 kmem_free(addr, SCSI_MAXNAMELEN);
15503 return (child);
15504 }
15505
15506 static dev_info_t *
15507 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
15508 {
15509 dev_info_t *child;
15510 char *addr;
15511
15512 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15513 (void) sprintf(addr, "p%x,0", phy);
15514 child = mptsas_find_child(pdip, addr);
15515 kmem_free(addr, SCSI_MAXNAMELEN);
15516 return (child);
15517 }
15518
15519 static mdi_pathinfo_t *
15520 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
15521 {
15522 mdi_pathinfo_t *path;
15523 char *addr = NULL;
15524
15525 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15526 (void) sprintf(addr, "p%x,0", phy);
15527 path = mdi_pi_find(pdip, NULL, addr);
15528 kmem_free(addr, SCSI_MAXNAMELEN);
15529 return (path);
15530 }
15531
15532 static mdi_pathinfo_t *
15533 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
15534 {
15535 mdi_pathinfo_t *path;
15536 char *name = NULL;
15537 char *addr = NULL;
15538
15539 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15540 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15541 (void) sprintf(name, "%016"PRIx64, sasaddr);
15542 (void) sprintf(addr, "w%s,%x", name, lun);
15543 path = mdi_pi_find(parent, NULL, addr);
15544 kmem_free(name, SCSI_MAXNAMELEN);
15545 kmem_free(addr, SCSI_MAXNAMELEN);
15546
15547 return (path);
15548 }
15549
15550 static int
15551 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
15552 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
15553 {
15554 int i = 0;
15555 uchar_t *inq83 = NULL;
15556 int inq83_len1 = 0xFF;
15557 int inq83_len = 0;
15558 int rval = DDI_FAILURE;
15559 ddi_devid_t devid;
15560 char *guid = NULL;
15561 int target = ptgt->m_devhdl;
15562 mdi_pathinfo_t *pip = NULL;
15563 mptsas_t *mpt = DIP2MPT(pdip);
15564
15565 /*
15566 * For DVD/CD ROM and tape devices and optical
15567 * devices, we won't try to enumerate them under
15568 * scsi_vhci, so no need to try page83
15569 */
15570 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
15571 sd_inq->inq_dtype == DTYPE_OPTICAL ||
15572 sd_inq->inq_dtype == DTYPE_ESI))
15573 goto create_lun;
15574
15575 /*
15576 * The LCA returns good SCSI status, but corrupt page 83 data the first
15577 * time it is queried. The solution is to keep trying to request page83
15578 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
15579 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
15580 * give up to get VPD page at this stage and fail the enumeration.
15581 */
15582
15583 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
15584
15585 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
15586 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
15587 inq83_len1, &inq83_len, 1);
15588 if (rval != 0) {
15589 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
15590 "0x83 for target:%x, lun:%x failed!", target, lun);
15591 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
15592 goto create_lun;
15593 goto out;
15594 }
15595 /*
15596 * create DEVID from inquiry data
15597 */
15598 if ((rval = ddi_devid_scsi_encode(
15599 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
15600 sizeof (struct scsi_inquiry), NULL, 0, inq83,
15601 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
15602 /*
15603 * extract GUID from DEVID
15604 */
15605 guid = ddi_devid_to_guid(devid);
15606
15607 /*
15608 * Do not enable MPXIO if the strlen(guid) is greater
15609 * than MPTSAS_MAX_GUID_LEN, this constrain would be
15610 * handled by framework later.
15611 */
15612 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
15613 ddi_devid_free_guid(guid);
15614 guid = NULL;
15615 if (mpt->m_mpxio_enable == TRUE) {
15616 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
15617 "lun:%x doesn't have a valid GUID, "
15618 "multipathing for this drive is "
15619 "not enabled", target, lun);
15620 }
15621 }
15622
15623 /*
15624 * devid no longer needed
15625 */
15626 ddi_devid_free(devid);
15627 break;
15628 } else if (rval == DDI_NOT_WELL_FORMED) {
15629 /*
15630 * return value of ddi_devid_scsi_encode equal to
15631 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
15632 * to retry inquiry page 0x83 and get GUID.
15633 */
15634 NDBG20(("Not well formed devid, retry..."));
15635 delay(1 * drv_usectohz(1000000));
15636 continue;
15637 } else {
15638 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
15639 "path target:%x, lun:%x", target, lun);
15640 rval = DDI_FAILURE;
15641 goto create_lun;
15642 }
15643 }
15644
15645 if (i == mptsas_inq83_retry_timeout) {
15646 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
15647 "for path target:%x, lun:%x", target, lun);
15648 }
15649
15650 rval = DDI_FAILURE;
15651
15652 create_lun:
15653 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
15654 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
15655 ptgt, lun);
15656 }
15657 if (rval != DDI_SUCCESS) {
15658 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
15659 ptgt, lun);
15660
15661 }
15662 out:
15663 if (guid != NULL) {
15664 /*
15665 * guid no longer needed
15666 */
15667 ddi_devid_free_guid(guid);
15668 }
15669 if (inq83 != NULL)
15670 kmem_free(inq83, inq83_len1);
15671 return (rval);
15672 }
15673
15674 static int
15675 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
15676 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
15677 {
15678 int target;
15679 char *nodename = NULL;
15680 char **compatible = NULL;
15681 int ncompatible = 0;
15682 int mdi_rtn = MDI_FAILURE;
15683 int rval = DDI_FAILURE;
15684 char *old_guid = NULL;
15685 mptsas_t *mpt = DIP2MPT(pdip);
15686 char *lun_addr = NULL;
15687 char wwn_str[MPTSAS_WWN_STRLEN];
15688 char *component = NULL;
15689 uint8_t phy = 0xFF;
15690 uint64_t sas_wwn;
15691 int64_t lun64 = 0;
15692 uint32_t devinfo;
15693 uint16_t dev_hdl;
15694 uint16_t pdev_hdl;
15695 uint64_t dev_sas_wwn;
15696 uint64_t pdev_sas_wwn;
15697 uint32_t pdev_info;
15698 uint8_t physport;
15699 uint8_t phy_id;
15700 uint32_t page_address;
15701 uint16_t bay_num, enclosure, io_flags;
15702 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
15703 uint32_t dev_info;
15704
15705 mutex_enter(&mpt->m_mutex);
15706 target = ptgt->m_devhdl;
15707 sas_wwn = ptgt->m_addr.mta_wwn;
15708 devinfo = ptgt->m_deviceinfo;
15709 phy = ptgt->m_phynum;
15710 mutex_exit(&mpt->m_mutex);
15711
15712 if (sas_wwn) {
15713 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
15714 } else {
15715 *pip = mptsas_find_path_phy(pdip, phy);
15716 }
15717
15718 if (*pip != NULL) {
15719 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15720 ASSERT(*lun_dip != NULL);
15721 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
15722 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
15723 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
15724 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
15725 /*
15726 * Same path back online again.
15727 */
15728 (void) ddi_prop_free(old_guid);
15729 if ((!MDI_PI_IS_ONLINE(*pip)) &&
15730 (!MDI_PI_IS_STANDBY(*pip)) &&
15731 (ptgt->m_tgt_unconfigured == 0)) {
15732 rval = mdi_pi_online(*pip, 0);
15733 mutex_enter(&mpt->m_mutex);
15734 ptgt->m_led_status = 0;
15735 (void) mptsas_flush_led_status(mpt,
15736 ptgt);
15737 mutex_exit(&mpt->m_mutex);
15738 } else {
15739 rval = DDI_SUCCESS;
15740 }
15741 if (rval != DDI_SUCCESS) {
15742 mptsas_log(mpt, CE_WARN, "path:target: "
15743 "%x, lun:%x online failed!", target,
15744 lun);
15745 *pip = NULL;
15746 *lun_dip = NULL;
15747 }
15748 return (rval);
15749 } else {
15750 /*
15751 * The GUID of the LUN has changed which maybe
15752 * because customer mapped another volume to the
15753 * same LUN.
15754 */
15755 mptsas_log(mpt, CE_WARN, "The GUID of the "
15756 "target:%x, lun:%x was changed, maybe "
15757 "because someone mapped another volume "
15758 "to the same LUN", target, lun);
15759 (void) ddi_prop_free(old_guid);
15760 if (!MDI_PI_IS_OFFLINE(*pip)) {
15761 rval = mdi_pi_offline(*pip, 0);
15762 if (rval != MDI_SUCCESS) {
15763 mptsas_log(mpt, CE_WARN, "path:"
15764 "target:%x, lun:%x offline "
15765 "failed!", target, lun);
15766 *pip = NULL;
15767 *lun_dip = NULL;
15768 return (DDI_FAILURE);
15769 }
15770 }
15771 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
15772 mptsas_log(mpt, CE_WARN, "path:target:"
15773 "%x, lun:%x free failed!", target,
15774 lun);
15775 *pip = NULL;
15776 *lun_dip = NULL;
15777 return (DDI_FAILURE);
15778 }
15779 }
15780 } else {
15781 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
15782 "property for path:target:%x, lun:%x", target, lun);
15783 *pip = NULL;
15784 *lun_dip = NULL;
15785 return (DDI_FAILURE);
15786 }
15787 }
15788 scsi_hba_nodename_compatible_get(inq, NULL,
15789 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
15790
15791 /*
15792 * if nodename can't be determined then print a message and skip it
15793 */
15794 if (nodename == NULL) {
15795 mptsas_log(mpt, CE_WARN, "found no compatible "
15796 "driver for target%d lun %d dtype:0x%02x", target, lun,
15797 inq->inq_dtype);
15798 return (DDI_FAILURE);
15799 }
15800
15801 /* The property is needed by MPAPI */
15802 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15803
15804 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15805 if (guid) {
15806 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
15807 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15808 } else {
15809 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
15810 (void) sprintf(wwn_str, "p%x", phy);
15811 }
15812
15813 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
15814 guid, lun_addr, compatible, ncompatible,
15815 0, pip);
15816 if (mdi_rtn == MDI_SUCCESS) {
15817
15818 if (mdi_prop_update_string(*pip, MDI_GUID,
15819 guid) != DDI_SUCCESS) {
15820 mptsas_log(mpt, CE_WARN, "unable to "
15821 "create prop for target %d lun %d (MDI_GUID)",
15822 target, lun);
15823 mdi_rtn = MDI_FAILURE;
15824 goto virt_create_done;
15825 }
15826
15827 if (mdi_prop_update_int(*pip, LUN_PROP,
15828 lun) != DDI_SUCCESS) {
15829 mptsas_log(mpt, CE_WARN, "unable to "
15830 "create prop for target %d lun %d (LUN_PROP)",
15831 target, lun);
15832 mdi_rtn = MDI_FAILURE;
15833 goto virt_create_done;
15834 }
15835 lun64 = (int64_t)lun;
15836 if (mdi_prop_update_int64(*pip, LUN64_PROP,
15837 lun64) != DDI_SUCCESS) {
15838 mptsas_log(mpt, CE_WARN, "unable to "
15839 "create prop for target %d (LUN64_PROP)",
15840 target);
15841 mdi_rtn = MDI_FAILURE;
15842 goto virt_create_done;
15843 }
15844 if (mdi_prop_update_string_array(*pip, "compatible",
15845 compatible, ncompatible) !=
15846 DDI_PROP_SUCCESS) {
15847 mptsas_log(mpt, CE_WARN, "unable to "
15848 "create prop for target %d lun %d (COMPATIBLE)",
15849 target, lun);
15850 mdi_rtn = MDI_FAILURE;
15851 goto virt_create_done;
15852 }
15853 if (sas_wwn && (mdi_prop_update_string(*pip,
15854 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
15855 mptsas_log(mpt, CE_WARN, "unable to "
15856 "create prop for target %d lun %d "
15857 "(target-port)", target, lun);
15858 mdi_rtn = MDI_FAILURE;
15859 goto virt_create_done;
15860 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
15861 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
15862 /*
15863 * Direct attached SATA device without DeviceName
15864 */
15865 mptsas_log(mpt, CE_WARN, "unable to "
15866 "create prop for SAS target %d lun %d "
15867 "(sata-phy)", target, lun);
15868 mdi_rtn = MDI_FAILURE;
15869 goto virt_create_done;
15870 }
15871 mutex_enter(&mpt->m_mutex);
15872
15873 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15874 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15875 (uint32_t)ptgt->m_devhdl;
15876 rval = mptsas_get_sas_device_page0(mpt, page_address,
15877 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
15878 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15879 if (rval != DDI_SUCCESS) {
15880 mutex_exit(&mpt->m_mutex);
15881 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15882 "parent device for handle %d", page_address);
15883 mdi_rtn = MDI_FAILURE;
15884 goto virt_create_done;
15885 }
15886
15887 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15888 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15889 rval = mptsas_get_sas_device_page0(mpt, page_address,
15890 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15891 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15892 if (rval != DDI_SUCCESS) {
15893 mutex_exit(&mpt->m_mutex);
15894 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15895 "device info for handle %d", page_address);
15896 mdi_rtn = MDI_FAILURE;
15897 goto virt_create_done;
15898 }
15899
15900 mutex_exit(&mpt->m_mutex);
15901
15902 /*
15903 * If this device direct attached to the controller
15904 * set the attached-port to the base wwid
15905 */
15906 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15907 != DEVINFO_DIRECT_ATTACHED) {
15908 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15909 pdev_sas_wwn);
15910 } else {
15911 /*
15912 * Update the iport's attached-port to guid
15913 */
15914 if (sas_wwn == 0) {
15915 (void) sprintf(wwn_str, "p%x", phy);
15916 } else {
15917 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15918 }
15919 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15920 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15921 DDI_PROP_SUCCESS) {
15922 mptsas_log(mpt, CE_WARN,
15923 "mptsas unable to create "
15924 "property for iport target-port"
15925 " %s (sas_wwn)",
15926 wwn_str);
15927 mdi_rtn = MDI_FAILURE;
15928 goto virt_create_done;
15929 }
15930
15931 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15932 mpt->un.m_base_wwid);
15933 }
15934
15935 if (mdi_prop_update_string(*pip,
15936 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15937 DDI_PROP_SUCCESS) {
15938 mptsas_log(mpt, CE_WARN, "unable to create "
15939 "property for iport attached-port %s (sas_wwn)",
15940 pdev_wwn_str);
15941 mdi_rtn = MDI_FAILURE;
15942 goto virt_create_done;
15943 }
15944
15945
15946 if (inq->inq_dtype == 0) {
15947 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15948 /*
15949 * set obp path for pathinfo
15950 */
15951 (void) snprintf(component, MAXPATHLEN,
15952 "disk@%s", lun_addr);
15953
15954 if (mdi_pi_pathname_obp_set(*pip, component) !=
15955 DDI_SUCCESS) {
15956 mptsas_log(mpt, CE_WARN,
15957 "unable to set obp-path for object %s",
15958 component);
15959 mdi_rtn = MDI_FAILURE;
15960 goto virt_create_done;
15961 }
15962 }
15963
15964 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15965 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15966 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15967 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
15968 "pm-capable", 1)) !=
15969 DDI_PROP_SUCCESS) {
15970 mptsas_log(mpt, CE_WARN,
15971 "failed to create pm-capable "
15972 "property, target %d", target);
15973 mdi_rtn = MDI_FAILURE;
15974 goto virt_create_done;
15975 }
15976 }
15977 /*
15978 * Create the phy-num property
15979 */
15980 if (mdi_prop_update_int(*pip, "phy-num",
15981 ptgt->m_phynum) != DDI_SUCCESS) {
15982 mptsas_log(mpt, CE_WARN, "unable to "
15983 "create phy-num property for target %d lun %d",
15984 target, lun);
15985 mdi_rtn = MDI_FAILURE;
15986 goto virt_create_done;
15987 }
15988 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
15989 mdi_rtn = mdi_pi_online(*pip, 0);
15990 if (mdi_rtn == MDI_SUCCESS) {
15991 mutex_enter(&mpt->m_mutex);
15992 ptgt->m_led_status = 0;
15993 (void) mptsas_flush_led_status(mpt, ptgt);
15994 mutex_exit(&mpt->m_mutex);
15995 }
15996 if (mdi_rtn == MDI_NOT_SUPPORTED) {
15997 mdi_rtn = MDI_FAILURE;
15998 }
15999 virt_create_done:
16000 if (*pip && mdi_rtn != MDI_SUCCESS) {
16001 (void) mdi_pi_free(*pip, 0);
16002 *pip = NULL;
16003 *lun_dip = NULL;
16004 }
16005 }
16006
16007 scsi_hba_nodename_compatible_free(nodename, compatible);
16008 if (lun_addr != NULL) {
16009 kmem_free(lun_addr, SCSI_MAXNAMELEN);
16010 }
16011 if (component != NULL) {
16012 kmem_free(component, MAXPATHLEN);
16013 }
16014
16015 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16016 }
16017
16018 static int
16019 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
16020 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
16021 {
16022 int target;
16023 int rval;
16024 int ndi_rtn = NDI_FAILURE;
16025 uint64_t be_sas_wwn;
16026 char *nodename = NULL;
16027 char **compatible = NULL;
16028 int ncompatible = 0;
16029 int instance = 0;
16030 mptsas_t *mpt = DIP2MPT(pdip);
16031 char wwn_str[MPTSAS_WWN_STRLEN];
16032 char component[MAXPATHLEN];
16033 uint8_t phy = 0xFF;
16034 uint64_t sas_wwn;
16035 uint32_t devinfo;
16036 uint16_t dev_hdl;
16037 uint16_t pdev_hdl;
16038 uint64_t pdev_sas_wwn;
16039 uint64_t dev_sas_wwn;
16040 uint32_t pdev_info;
16041 uint8_t physport;
16042 uint8_t phy_id;
16043 uint32_t page_address;
16044 uint16_t bay_num, enclosure, io_flags;
16045 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
16046 uint32_t dev_info;
16047 int64_t lun64 = 0;
16048
16049 mutex_enter(&mpt->m_mutex);
16050 target = ptgt->m_devhdl;
16051 sas_wwn = ptgt->m_addr.mta_wwn;
16052 devinfo = ptgt->m_deviceinfo;
16053 phy = ptgt->m_phynum;
16054 mutex_exit(&mpt->m_mutex);
16055
16056 /*
16057 * generate compatible property with binding-set "mpt"
16058 */
16059 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
16060 &nodename, &compatible, &ncompatible);
16061
16062 /*
16063 * if nodename can't be determined then print a message and skip it
16064 */
16065 if (nodename == NULL) {
16066 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
16067 "for target %d lun %d", target, lun);
16068 return (DDI_FAILURE);
16069 }
16070
16071 ndi_rtn = ndi_devi_alloc(pdip, nodename,
16072 DEVI_SID_NODEID, lun_dip);
16073
16074 /*
16075 * if lun alloc success, set props
16076 */
16077 if (ndi_rtn == NDI_SUCCESS) {
16078
16079 if (ndi_prop_update_int(DDI_DEV_T_NONE,
16080 *lun_dip, LUN_PROP, lun) !=
16081 DDI_PROP_SUCCESS) {
16082 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16083 "property for target %d lun %d (LUN_PROP)",
16084 target, lun);
16085 ndi_rtn = NDI_FAILURE;
16086 goto phys_create_done;
16087 }
16088
16089 lun64 = (int64_t)lun;
16090 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
16091 *lun_dip, LUN64_PROP, lun64) !=
16092 DDI_PROP_SUCCESS) {
16093 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16094 "property for target %d lun64 %d (LUN64_PROP)",
16095 target, lun);
16096 ndi_rtn = NDI_FAILURE;
16097 goto phys_create_done;
16098 }
16099 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
16100 *lun_dip, "compatible", compatible, ncompatible)
16101 != DDI_PROP_SUCCESS) {
16102 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16103 "property for target %d lun %d (COMPATIBLE)",
16104 target, lun);
16105 ndi_rtn = NDI_FAILURE;
16106 goto phys_create_done;
16107 }
16108
16109 /*
16110 * We need the SAS WWN for non-multipath devices, so
16111 * we'll use the same property as that multipathing
16112 * devices need to present for MPAPI. If we don't have
16113 * a WWN (e.g. parallel SCSI), don't create the prop.
16114 */
16115 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
16116 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
16117 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
16118 != DDI_PROP_SUCCESS) {
16119 mptsas_log(mpt, CE_WARN, "mptsas unable to "
16120 "create property for SAS target %d lun %d "
16121 "(target-port)", target, lun);
16122 ndi_rtn = NDI_FAILURE;
16123 goto phys_create_done;
16124 }
16125
16126 be_sas_wwn = BE_64(sas_wwn);
16127 if (sas_wwn && ndi_prop_update_byte_array(
16128 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
16129 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
16130 mptsas_log(mpt, CE_WARN, "mptsas unable to "
16131 "create property for SAS target %d lun %d "
16132 "(port-wwn)", target, lun);
16133 ndi_rtn = NDI_FAILURE;
16134 goto phys_create_done;
16135 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
16136 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
16137 DDI_PROP_SUCCESS)) {
16138 /*
16139 * Direct attached SATA device without DeviceName
16140 */
16141 mptsas_log(mpt, CE_WARN, "mptsas unable to "
16142 "create property for SAS target %d lun %d "
16143 "(sata-phy)", target, lun);
16144 ndi_rtn = NDI_FAILURE;
16145 goto phys_create_done;
16146 }
16147
16148 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
16149 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
16150 mptsas_log(mpt, CE_WARN, "mptsas unable to"
16151 "create property for SAS target %d lun %d"
16152 " (SAS_PROP)", target, lun);
16153 ndi_rtn = NDI_FAILURE;
16154 goto phys_create_done;
16155 }
16156 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
16157 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
16158 mptsas_log(mpt, CE_WARN, "mptsas unable "
16159 "to create guid property for target %d "
16160 "lun %d", target, lun);
16161 ndi_rtn = NDI_FAILURE;
16162 goto phys_create_done;
16163 }
16164
16165 /*
16166 * The following code is to set properties for SM-HBA support,
16167 * it doesn't apply to RAID volumes
16168 */
16169 if (ptgt->m_addr.mta_phymask == 0)
16170 goto phys_raid_lun;
16171
16172 mutex_enter(&mpt->m_mutex);
16173
16174 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
16175 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
16176 (uint32_t)ptgt->m_devhdl;
16177 rval = mptsas_get_sas_device_page0(mpt, page_address,
16178 &dev_hdl, &dev_sas_wwn, &dev_info,
16179 &physport, &phy_id, &pdev_hdl,
16180 &bay_num, &enclosure, &io_flags);
16181 if (rval != DDI_SUCCESS) {
16182 mutex_exit(&mpt->m_mutex);
16183 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
16184 "parent device for handle %d.", page_address);
16185 ndi_rtn = NDI_FAILURE;
16186 goto phys_create_done;
16187 }
16188
16189 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
16190 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
16191 rval = mptsas_get_sas_device_page0(mpt, page_address,
16192 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
16193 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
16194 if (rval != DDI_SUCCESS) {
16195 mutex_exit(&mpt->m_mutex);
16196 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16197 "device for handle %d.", page_address);
16198 ndi_rtn = NDI_FAILURE;
16199 goto phys_create_done;
16200 }
16201
16202 mutex_exit(&mpt->m_mutex);
16203
16204 /*
16205 * If this device direct attached to the controller
16206 * set the attached-port to the base wwid
16207 */
16208 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
16209 != DEVINFO_DIRECT_ATTACHED) {
16210 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
16211 pdev_sas_wwn);
16212 } else {
16213 /*
16214 * Update the iport's attached-port to guid
16215 */
16216 if (sas_wwn == 0) {
16217 (void) sprintf(wwn_str, "p%x", phy);
16218 } else {
16219 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
16220 }
16221 if (ddi_prop_update_string(DDI_DEV_T_NONE,
16222 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
16223 DDI_PROP_SUCCESS) {
16224 mptsas_log(mpt, CE_WARN,
16225 "mptsas unable to create "
16226 "property for iport target-port"
16227 " %s (sas_wwn)",
16228 wwn_str);
16229 ndi_rtn = NDI_FAILURE;
16230 goto phys_create_done;
16231 }
16232
16233 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
16234 mpt->un.m_base_wwid);
16235 }
16236
16237 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16238 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
16239 DDI_PROP_SUCCESS) {
16240 mptsas_log(mpt, CE_WARN,
16241 "mptsas unable to create "
16242 "property for iport attached-port %s (sas_wwn)",
16243 pdev_wwn_str);
16244 ndi_rtn = NDI_FAILURE;
16245 goto phys_create_done;
16246 }
16247
16248 if (IS_SATA_DEVICE(dev_info)) {
16249 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16250 *lun_dip, MPTSAS_VARIANT, "sata") !=
16251 DDI_PROP_SUCCESS) {
16252 mptsas_log(mpt, CE_WARN,
16253 "mptsas unable to create "
16254 "property for device variant ");
16255 ndi_rtn = NDI_FAILURE;
16256 goto phys_create_done;
16257 }
16258 }
16259
16260 if (IS_ATAPI_DEVICE(dev_info)) {
16261 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16262 *lun_dip, MPTSAS_VARIANT, "atapi") !=
16263 DDI_PROP_SUCCESS) {
16264 mptsas_log(mpt, CE_WARN,
16265 "mptsas unable to create "
16266 "property for device variant ");
16267 ndi_rtn = NDI_FAILURE;
16268 goto phys_create_done;
16269 }
16270 }
16271
16272 phys_raid_lun:
16273 /*
16274 * if this is a SAS controller, and the target is a SATA
16275 * drive, set the 'pm-capable' property for sd and if on
16276 * an OPL platform, also check if this is an ATAPI
16277 * device.
16278 */
16279 instance = ddi_get_instance(mpt->m_dip);
16280 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
16281 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
16282 NDBG2(("mptsas3%d: creating pm-capable property, "
16283 "target %d", instance, target));
16284
16285 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
16286 *lun_dip, "pm-capable", 1)) !=
16287 DDI_PROP_SUCCESS) {
16288 mptsas_log(mpt, CE_WARN, "mptsas "
16289 "failed to create pm-capable "
16290 "property, target %d", target);
16291 ndi_rtn = NDI_FAILURE;
16292 goto phys_create_done;
16293 }
16294
16295 }
16296
16297 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
16298 /*
16299 * add 'obp-path' properties for devinfo
16300 */
16301 bzero(wwn_str, sizeof (wwn_str));
16302 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
16303 if (guid) {
16304 (void) snprintf(component, MAXPATHLEN,
16305 "disk@w%s,%x", wwn_str, lun);
16306 } else {
16307 (void) snprintf(component, MAXPATHLEN,
16308 "disk@p%x,%x", phy, lun);
16309 }
16310 if (ddi_pathname_obp_set(*lun_dip, component)
16311 != DDI_SUCCESS) {
16312 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
16313 "unable to set obp-path for SAS "
16314 "object %s", component);
16315 ndi_rtn = NDI_FAILURE;
16316 goto phys_create_done;
16317 }
16318 }
16319 /*
16320 * Create the phy-num property for non-raid disk
16321 */
16322 if (ptgt->m_addr.mta_phymask != 0) {
16323 if (ndi_prop_update_int(DDI_DEV_T_NONE,
16324 *lun_dip, "phy-num", ptgt->m_phynum) !=
16325 DDI_PROP_SUCCESS) {
16326 mptsas_log(mpt, CE_WARN,
16327 "failed to create phy-num property for "
16328 "target %d", target);
16329 ndi_rtn = NDI_FAILURE;
16330 goto phys_create_done;
16331 }
16332 }
16333 phys_create_done:
16334 /*
16335 * If props were setup ok, online the lun
16336 */
16337 if (ndi_rtn == NDI_SUCCESS) {
16338 /*
16339 * Try to online the new node
16340 */
16341 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
16342 }
16343 if (ndi_rtn == NDI_SUCCESS) {
16344 mutex_enter(&mpt->m_mutex);
16345 ptgt->m_led_status = 0;
16346 (void) mptsas_flush_led_status(mpt, ptgt);
16347 mutex_exit(&mpt->m_mutex);
16348 }
16349
16350 /*
16351 * If success set rtn flag, else unwire alloc'd lun
16352 */
16353 if (ndi_rtn != NDI_SUCCESS) {
16354 NDBG12(("unable to online "
16355 "target %d lun %d", target, lun));
16356 ndi_prop_remove_all(*lun_dip);
16357 (void) ndi_devi_free(*lun_dip);
16358 *lun_dip = NULL;
16359 }
16360 }
16361
16362 scsi_hba_nodename_compatible_free(nodename, compatible);
16363
16364 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16365 }
16366
16367 static int
16368 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
16369 {
16370 mptsas_t *mpt = DIP2MPT(pdip);
16371 struct smp_device smp_sd;
16372
16373 /* XXX An HBA driver should not be allocating an smp_device. */
16374 bzero(&smp_sd, sizeof (struct smp_device));
16375 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
16376 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
16377
16378 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
16379 return (NDI_FAILURE);
16380 return (NDI_SUCCESS);
16381 }
16382
16383 static int
16384 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
16385 {
16386 mptsas_t *mpt = DIP2MPT(pdip);
16387 mptsas_smp_t *psmp = NULL;
16388 int rval;
16389 int phymask;
16390
16391 /*
16392 * Get the physical port associated to the iport
16393 * PHYMASK TODO
16394 */
16395 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
16396 "phymask", 0);
16397 /*
16398 * Find the smp node in hash table with specified sas address and
16399 * physical port
16400 */
16401 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
16402 if (psmp == NULL) {
16403 return (DDI_FAILURE);
16404 }
16405
16406 rval = mptsas_online_smp(pdip, psmp, smp_dip);
16407
16408 return (rval);
16409 }
16410
16411 static int
16412 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
16413 dev_info_t **smp_dip)
16414 {
16415 char wwn_str[MPTSAS_WWN_STRLEN];
16416 char attached_wwn_str[MPTSAS_WWN_STRLEN];
16417 int ndi_rtn = NDI_FAILURE;
16418 int rval = 0;
16419 mptsas_smp_t dev_info;
16420 uint32_t page_address;
16421 mptsas_t *mpt = DIP2MPT(pdip);
16422 uint16_t dev_hdl;
16423 uint64_t sas_wwn;
16424 uint64_t smp_sas_wwn;
16425 uint8_t physport;
16426 uint8_t phy_id;
16427 uint16_t pdev_hdl;
16428 uint8_t numphys = 0;
16429 uint16_t i = 0;
16430 char phymask[MPTSAS_MAX_PHYS];
16431 char *iport = NULL;
16432 mptsas_phymask_t phy_mask = 0;
16433 uint16_t attached_devhdl;
16434 uint16_t bay_num, enclosure, io_flags;
16435
16436 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
16437
16438 /*
16439 * Probe smp device, prevent the node of removed device from being
16440 * configured succesfully
16441 */
16442 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) {
16443 return (DDI_FAILURE);
16444 }
16445
16446 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
16447 return (DDI_SUCCESS);
16448 }
16449
16450 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
16451
16452 /*
16453 * if lun alloc success, set props
16454 */
16455 if (ndi_rtn == NDI_SUCCESS) {
16456 /*
16457 * Set the flavor of the child to be SMP flavored
16458 */
16459 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
16460
16461 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16462 *smp_dip, SMP_WWN, wwn_str) !=
16463 DDI_PROP_SUCCESS) {
16464 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16465 "property for smp device %s (sas_wwn)",
16466 wwn_str);
16467 ndi_rtn = NDI_FAILURE;
16468 goto smp_create_done;
16469 }
16470 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn);
16471 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16472 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
16473 DDI_PROP_SUCCESS) {
16474 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16475 "property for iport target-port %s (sas_wwn)",
16476 wwn_str);
16477 ndi_rtn = NDI_FAILURE;
16478 goto smp_create_done;
16479 }
16480
16481 mutex_enter(&mpt->m_mutex);
16482
16483 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
16484 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
16485 rval = mptsas_get_sas_expander_page0(mpt, page_address,
16486 &dev_info);
16487 if (rval != DDI_SUCCESS) {
16488 mutex_exit(&mpt->m_mutex);
16489 mptsas_log(mpt, CE_WARN,
16490 "mptsas unable to get expander "
16491 "parent device info for %x", page_address);
16492 ndi_rtn = NDI_FAILURE;
16493 goto smp_create_done;
16494 }
16495
16496 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
16497 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
16498 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
16499 (uint32_t)dev_info.m_pdevhdl;
16500 rval = mptsas_get_sas_device_page0(mpt, page_address,
16501 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport,
16502 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
16503 if (rval != DDI_SUCCESS) {
16504 mutex_exit(&mpt->m_mutex);
16505 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
16506 "device info for %x", page_address);
16507 ndi_rtn = NDI_FAILURE;
16508 goto smp_create_done;
16509 }
16510
16511 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
16512 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
16513 (uint32_t)dev_info.m_devhdl;
16514 rval = mptsas_get_sas_device_page0(mpt, page_address,
16515 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
16516 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure,
16517 &io_flags);
16518 if (rval != DDI_SUCCESS) {
16519 mutex_exit(&mpt->m_mutex);
16520 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
16521 "device info for %x", page_address);
16522 ndi_rtn = NDI_FAILURE;
16523 goto smp_create_done;
16524 }
16525 mutex_exit(&mpt->m_mutex);
16526
16527 /*
16528 * If this smp direct attached to the controller
16529 * set the attached-port to the base wwid
16530 */
16531 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
16532 != DEVINFO_DIRECT_ATTACHED) {
16533 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
16534 sas_wwn);
16535 } else {
16536 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
16537 mpt->un.m_base_wwid);
16538 }
16539
16540 if (ndi_prop_update_string(DDI_DEV_T_NONE,
16541 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
16542 DDI_PROP_SUCCESS) {
16543 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
16544 "property for smp attached-port %s (sas_wwn)",
16545 attached_wwn_str);
16546 ndi_rtn = NDI_FAILURE;
16547 goto smp_create_done;
16548 }
16549
16550 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
16551 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
16552 mptsas_log(mpt, CE_WARN, "mptsas unable to "
16553 "create property for SMP %s (SMP_PROP) ",
16554 wwn_str);
16555 ndi_rtn = NDI_FAILURE;
16556 goto smp_create_done;
16557 }
16558
16559 /*
16560 * check the smp to see whether it direct
16561 * attached to the controller
16562 */
16563 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
16564 != DEVINFO_DIRECT_ATTACHED) {
16565 goto smp_create_done;
16566 }
16567 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
16568 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
16569 if (numphys > 0) {
16570 goto smp_create_done;
16571 }
16572 /*
16573 * this iport is an old iport, we need to
16574 * reconfig the props for it.
16575 */
16576 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16577 MPTSAS_VIRTUAL_PORT, 0) !=
16578 DDI_PROP_SUCCESS) {
16579 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16580 MPTSAS_VIRTUAL_PORT);
16581 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
16582 "prop update failed");
16583 goto smp_create_done;
16584 }
16585
16586 mutex_enter(&mpt->m_mutex);
16587 numphys = 0;
16588 iport = ddi_get_name_addr(pdip);
16589 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16590 bzero(phymask, sizeof (phymask));
16591 (void) sprintf(phymask,
16592 "%x", mpt->m_phy_info[i].phy_mask);
16593 if (strcmp(phymask, iport) == 0) {
16594 phy_mask = mpt->m_phy_info[i].phy_mask;
16595 break;
16596 }
16597 }
16598
16599 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16600 if ((phy_mask >> i) & 0x01) {
16601 numphys++;
16602 }
16603 }
16604 /*
16605 * Update PHY info for smhba
16606 */
16607 if (mptsas_smhba_phy_init(mpt)) {
16608 mutex_exit(&mpt->m_mutex);
16609 mptsas_log(mpt, CE_WARN, "mptsas phy update "
16610 "failed");
16611 goto smp_create_done;
16612 }
16613 mutex_exit(&mpt->m_mutex);
16614
16615 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask,
16616 &attached_devhdl);
16617
16618 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16619 MPTSAS_NUM_PHYS, numphys) !=
16620 DDI_PROP_SUCCESS) {
16621 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16622 MPTSAS_NUM_PHYS);
16623 mptsas_log(mpt, CE_WARN, "mptsas update "
16624 "num phys props failed");
16625 goto smp_create_done;
16626 }
16627 /*
16628 * Add parent's props for SMHBA support
16629 */
16630 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
16631 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
16632 DDI_PROP_SUCCESS) {
16633 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16634 SCSI_ADDR_PROP_ATTACHED_PORT);
16635 mptsas_log(mpt, CE_WARN, "mptsas update iport"
16636 "attached-port failed");
16637 goto smp_create_done;
16638 }
16639
16640 smp_create_done:
16641 /*
16642 * If props were setup ok, online the lun
16643 */
16644 if (ndi_rtn == NDI_SUCCESS) {
16645 /*
16646 * Try to online the new node
16647 */
16648 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
16649 }
16650
16651 /*
16652 * If success set rtn flag, else unwire alloc'd lun
16653 */
16654 if (ndi_rtn != NDI_SUCCESS) {
16655 NDBG12(("mptsas unable to online "
16656 "SMP target %s", wwn_str));
16657 ndi_prop_remove_all(*smp_dip);
16658 (void) ndi_devi_free(*smp_dip);
16659 }
16660 }
16661
16662 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16663 }
16664
16665 /* smp transport routine */
16666 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
16667 {
16668 uint64_t wwn;
16669 Mpi2SmpPassthroughRequest_t req;
16670 Mpi2SmpPassthroughReply_t rep;
16671 uint8_t direction = 0;
16672 mptsas_t *mpt;
16673 int ret;
16674 uint64_t tmp64;
16675
16676 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
16677 smp_a_hba_tran->smp_tran_hba_private;
16678
16679 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
16680 /*
16681 * Need to compose a SMP request message
16682 * and call mptsas_do_passthru() function
16683 */
16684 bzero(&req, sizeof (req));
16685 bzero(&rep, sizeof (rep));
16686 req.PassthroughFlags = 0;
16687 req.PhysicalPort = 0xff;
16688 req.ChainOffset = 0;
16689 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
16690
16691 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
16692 smp_pkt->smp_pkt_reason = ERANGE;
16693 return (DDI_FAILURE);
16694 }
16695 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
16696
16697 req.MsgFlags = 0;
16698 tmp64 = LE_64(wwn);
16699 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
16700 if (smp_pkt->smp_pkt_rspsize > 0) {
16701 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
16702 }
16703 if (smp_pkt->smp_pkt_reqsize > 0) {
16704 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
16705 }
16706
16707 mutex_enter(&mpt->m_mutex);
16708 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
16709 (uint8_t *)smp_pkt->smp_pkt_rsp,
16710 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
16711 smp_pkt->smp_pkt_rspsize - 4, direction,
16712 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
16713 smp_pkt->smp_pkt_timeout, FKIOCTL);
16714 mutex_exit(&mpt->m_mutex);
16715 if (ret != 0) {
16716 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
16717 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
16718 return (DDI_FAILURE);
16719 }
16720 /* do passthrough success, check the smp status */
16721 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16722 switch (LE_16(rep.IOCStatus)) {
16723 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
16724 smp_pkt->smp_pkt_reason = ENODEV;
16725 break;
16726 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
16727 smp_pkt->smp_pkt_reason = EOVERFLOW;
16728 break;
16729 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
16730 smp_pkt->smp_pkt_reason = EIO;
16731 break;
16732 default:
16733 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
16734 "status:%x", LE_16(rep.IOCStatus));
16735 smp_pkt->smp_pkt_reason = EIO;
16736 break;
16737 }
16738 return (DDI_FAILURE);
16739 }
16740 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
16741 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
16742 rep.SASStatus);
16743 smp_pkt->smp_pkt_reason = EIO;
16744 return (DDI_FAILURE);
16745 }
16746
16747 return (DDI_SUCCESS);
16748 }
16749
16750 /*
16751 * If we didn't get a match, we need to get sas page0 for each device, and
16752 * untill we get a match. If failed, return NULL
16753 */
16754 static mptsas_target_t *
16755 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy)
16756 {
16757 int i, j = 0;
16758 int rval = 0;
16759 uint16_t cur_handle;
16760 uint32_t page_address;
16761 mptsas_target_t *ptgt = NULL;
16762
16763 /*
16764 * PHY named device must be direct attached and attaches to
16765 * narrow port, if the iport is not parent of the device which
16766 * we are looking for.
16767 */
16768 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16769 if ((1 << i) & phymask)
16770 j++;
16771 }
16772
16773 if (j > 1)
16774 return (NULL);
16775
16776 /*
16777 * Must be a narrow port and single device attached to the narrow port
16778 * So the physical port num of device which is equal to the iport's
16779 * port num is the device what we are looking for.
16780 */
16781
16782 if (mpt->m_phy_info[phy].phy_mask != phymask)
16783 return (NULL);
16784
16785 mutex_enter(&mpt->m_mutex);
16786
16787 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn,
16788 &phy);
16789 if (ptgt != NULL) {
16790 mutex_exit(&mpt->m_mutex);
16791 return (ptgt);
16792 }
16793
16794 if (mpt->m_done_traverse_dev) {
16795 mutex_exit(&mpt->m_mutex);
16796 return (NULL);
16797 }
16798
16799 /* If didn't get a match, come here */
16800 cur_handle = mpt->m_dev_handle;
16801 for (; ; ) {
16802 ptgt = NULL;
16803 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16804 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16805 rval = mptsas_get_target_device_info(mpt, page_address,
16806 &cur_handle, &ptgt);
16807 if ((rval == DEV_INFO_FAIL_PAGE0) ||
16808 (rval == DEV_INFO_FAIL_ALLOC)) {
16809 break;
16810 }
16811 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16812 (rval == DEV_INFO_PHYS_DISK)) {
16813 continue;
16814 }
16815 mpt->m_dev_handle = cur_handle;
16816
16817 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) {
16818 break;
16819 }
16820 }
16821
16822 mutex_exit(&mpt->m_mutex);
16823 return (ptgt);
16824 }
16825
16826 /*
16827 * The ptgt->m_addr.mta_wwn contains the wwid for each disk.
16828 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
16829 * If we didn't get a match, we need to get sas page0 for each device, and
16830 * untill we get a match
16831 * If failed, return NULL
16832 */
16833 static mptsas_target_t *
16834 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16835 {
16836 int rval = 0;
16837 uint16_t cur_handle;
16838 uint32_t page_address;
16839 mptsas_target_t *tmp_tgt = NULL;
16840 mptsas_target_addr_t addr;
16841
16842 addr.mta_wwn = wwid;
16843 addr.mta_phymask = phymask;
16844 mutex_enter(&mpt->m_mutex);
16845 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16846 if (tmp_tgt != NULL) {
16847 mutex_exit(&mpt->m_mutex);
16848 return (tmp_tgt);
16849 }
16850
16851 if (phymask == 0) {
16852 /*
16853 * It's IR volume
16854 */
16855 rval = mptsas_get_raid_info(mpt);
16856 if (rval) {
16857 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16858 }
16859 mutex_exit(&mpt->m_mutex);
16860 return (tmp_tgt);
16861 }
16862
16863 if (mpt->m_done_traverse_dev) {
16864 mutex_exit(&mpt->m_mutex);
16865 return (NULL);
16866 }
16867
16868 /* If didn't get a match, come here */
16869 cur_handle = mpt->m_dev_handle;
16870 for (;;) {
16871 tmp_tgt = NULL;
16872 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16873 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
16874 rval = mptsas_get_target_device_info(mpt, page_address,
16875 &cur_handle, &tmp_tgt);
16876 if ((rval == DEV_INFO_FAIL_PAGE0) ||
16877 (rval == DEV_INFO_FAIL_ALLOC)) {
16878 tmp_tgt = NULL;
16879 break;
16880 }
16881 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16882 (rval == DEV_INFO_PHYS_DISK)) {
16883 continue;
16884 }
16885 mpt->m_dev_handle = cur_handle;
16886 if ((tmp_tgt->m_addr.mta_wwn) &&
16887 (tmp_tgt->m_addr.mta_wwn == wwid) &&
16888 (tmp_tgt->m_addr.mta_phymask == phymask)) {
16889 break;
16890 }
16891 }
16892
16893 mutex_exit(&mpt->m_mutex);
16894 return (tmp_tgt);
16895 }
16896
16897 static mptsas_smp_t *
16898 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16899 {
16900 int rval = 0;
16901 uint16_t cur_handle;
16902 uint32_t page_address;
16903 mptsas_smp_t smp_node, *psmp = NULL;
16904 mptsas_target_addr_t addr;
16905
16906 addr.mta_wwn = wwid;
16907 addr.mta_phymask = phymask;
16908 mutex_enter(&mpt->m_mutex);
16909 psmp = refhash_lookup(mpt->m_smp_targets, &addr);
16910 if (psmp != NULL) {
16911 mutex_exit(&mpt->m_mutex);
16912 return (psmp);
16913 }
16914
16915 if (mpt->m_done_traverse_smp) {
16916 mutex_exit(&mpt->m_mutex);
16917 return (NULL);
16918 }
16919
16920 /* If didn't get a match, come here */
16921 cur_handle = mpt->m_smp_devhdl;
16922 for (;;) {
16923 psmp = NULL;
16924 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
16925 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16926 rval = mptsas_get_sas_expander_page0(mpt, page_address,
16927 &smp_node);
16928 if (rval != DDI_SUCCESS) {
16929 break;
16930 }
16931 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
16932 psmp = mptsas_smp_alloc(mpt, &smp_node);
16933 ASSERT(psmp);
16934 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) &&
16935 (psmp->m_addr.mta_phymask == phymask)) {
16936 break;
16937 }
16938 }
16939
16940 mutex_exit(&mpt->m_mutex);
16941 return (psmp);
16942 }
16943
16944 mptsas_target_t *
16945 mptsas_tgt_alloc(mptsas_t *mpt, uint16_t devhdl, uint64_t wwid,
16946 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
16947 {
16948 mptsas_target_t *tmp_tgt = NULL;
16949 mptsas_target_addr_t addr;
16950
16951 addr.mta_wwn = wwid;
16952 addr.mta_phymask = phymask;
16953 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16954 if (tmp_tgt != NULL) {
16955 NDBG20(("Hash item already exist"));
16956 tmp_tgt->m_deviceinfo = devinfo;
16957 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */
16958 return (tmp_tgt);
16959 }
16960 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
16961 if (tmp_tgt == NULL) {
16962 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
16963 return (NULL);
16964 }
16965 tmp_tgt->m_devhdl = devhdl;
16966 tmp_tgt->m_addr.mta_wwn = wwid;
16967 tmp_tgt->m_deviceinfo = devinfo;
16968 tmp_tgt->m_addr.mta_phymask = phymask;
16969 tmp_tgt->m_phynum = phynum;
16970 /* Initialized the tgt structure */
16971 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
16972 tmp_tgt->m_qfull_retry_interval =
16973 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
16974 tmp_tgt->m_t_throttle = MAX_THROTTLE;
16975 mutex_init(&tmp_tgt->m_t_mutex, NULL, MUTEX_DRIVER, NULL);
16976 TAILQ_INIT(&tmp_tgt->m_active_cmdq);
16977
16978 refhash_insert(mpt->m_targets, tmp_tgt);
16979
16980 return (tmp_tgt);
16981 }
16982
16983 static void
16984 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst)
16985 {
16986 dst->m_devhdl = src->m_devhdl;
16987 dst->m_deviceinfo = src->m_deviceinfo;
16988 dst->m_pdevhdl = src->m_pdevhdl;
16989 dst->m_pdevinfo = src->m_pdevinfo;
16990 }
16991
16992 static mptsas_smp_t *
16993 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data)
16994 {
16995 mptsas_target_addr_t addr;
16996 mptsas_smp_t *ret_data;
16997
16998 addr.mta_wwn = data->m_addr.mta_wwn;
16999 addr.mta_phymask = data->m_addr.mta_phymask;
17000 ret_data = refhash_lookup(mpt->m_smp_targets, &addr);
17001 /*
17002 * If there's already a matching SMP target, update its fields
17003 * in place. Since the address is not changing, it's safe to do
17004 * this. We cannot just bcopy() here because the structure we've
17005 * been given has invalid hash links.
17006 */
17007 if (ret_data != NULL) {
17008 mptsas_smp_target_copy(data, ret_data);
17009 return (ret_data);
17010 }
17011
17012 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
17013 bcopy(data, ret_data, sizeof (mptsas_smp_t));
17014 refhash_insert(mpt->m_smp_targets, ret_data);
17015 return (ret_data);
17016 }
17017
17018 /*
17019 * Functions for SGPIO LED support
17020 */
17021 static dev_info_t *
17022 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
17023 {
17024 dev_info_t *dip;
17025 int prop;
17026 dip = e_ddi_hold_devi_by_dev(dev, 0);
17027 if (dip == NULL)
17028 return (dip);
17029 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
17030 "phymask", 0);
17031 *phymask = (mptsas_phymask_t)prop;
17032 ddi_release_devi(dip);
17033 return (dip);
17034 }
17035 static mptsas_target_t *
17036 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
17037 {
17038 uint8_t phynum;
17039 uint64_t wwn;
17040 int lun;
17041 mptsas_target_t *ptgt = NULL;
17042
17043 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
17044 return (NULL);
17045 }
17046 if (addr[0] == 'w') {
17047 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
17048 } else {
17049 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
17050 }
17051 return (ptgt);
17052 }
17053
17054 static int
17055 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt)
17056 {
17057 uint32_t slotstatus = 0;
17058
17059 /* Build an MPI2 Slot Status based on our view of the world */
17060 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
17061 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
17062 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
17063 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
17064 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
17065 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
17066
17067 /* Write it to the controller */
17068 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
17069 slotstatus, ptgt->m_slot_num));
17070 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
17071 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
17072 }
17073
17074 /*
17075 * send sep request, use enclosure/slot addressing
17076 */
17077 static int
17078 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
17079 uint32_t *status, uint8_t act)
17080 {
17081 Mpi2SepRequest_t req;
17082 Mpi2SepReply_t rep;
17083 int ret;
17084
17085 ASSERT(mutex_owned(&mpt->m_mutex));
17086
17087 /*
17088 * We only support SEP control of directly-attached targets, in which
17089 * case the "SEP" we're talking to is a virtual one contained within
17090 * the HBA itself. This is necessary because DA targets typically have
17091 * no other mechanism for LED control. Targets for which a separate
17092 * enclosure service processor exists should be controlled via ses(7d)
17093 * or sgen(7d). Furthermore, since such requests can time out, they
17094 * should be made in user context rather than in response to
17095 * asynchronous fabric changes.
17096 *
17097 * In addition, we do not support this operation for RAID volumes,
17098 * since there is no slot associated with them.
17099 */
17100 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) ||
17101 ptgt->m_addr.mta_phymask == 0) {
17102 return (ENOTTY);
17103 }
17104
17105 bzero(&req, sizeof (req));
17106 bzero(&rep, sizeof (rep));
17107
17108 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
17109 req.Action = act;
17110 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
17111 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
17112 req.Slot = LE_16(ptgt->m_slot_num);
17113 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
17114 req.SlotStatus = LE_32(*status);
17115 }
17116 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
17117 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
17118 if (ret != 0) {
17119 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
17120 "Processor Request message error %d", ret);
17121 return (ret);
17122 }
17123 /* do passthrough success, check the ioc status */
17124 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
17125 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
17126 "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
17127 LE_32(rep.IOCLogInfo));
17128 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
17129 case MPI2_IOCSTATUS_INVALID_FUNCTION:
17130 case MPI2_IOCSTATUS_INVALID_VPID:
17131 case MPI2_IOCSTATUS_INVALID_FIELD:
17132 case MPI2_IOCSTATUS_INVALID_STATE:
17133 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
17134 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
17135 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
17136 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
17137 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
17138 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
17139 return (EINVAL);
17140 case MPI2_IOCSTATUS_BUSY:
17141 return (EBUSY);
17142 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
17143 return (EAGAIN);
17144 case MPI2_IOCSTATUS_INVALID_SGL:
17145 case MPI2_IOCSTATUS_INTERNAL_ERROR:
17146 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
17147 default:
17148 return (EIO);
17149 }
17150 }
17151 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
17152 *status = LE_32(rep.SlotStatus);
17153 }
17154
17155 return (0);
17156 }
17157
17158 int
17159 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
17160 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
17161 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
17162 {
17163 ddi_dma_cookie_t new_cookie;
17164 size_t alloc_len;
17165 uint_t ncookie;
17166
17167 if (cookiep == NULL)
17168 cookiep = &new_cookie;
17169
17170 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
17171 NULL, dma_hdp) != DDI_SUCCESS) {
17172 return (FALSE);
17173 }
17174
17175 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
17176 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
17177 acc_hdp) != DDI_SUCCESS) {
17178 ddi_dma_free_handle(dma_hdp);
17179 return (FALSE);
17180 }
17181
17182 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
17183 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
17184 cookiep, &ncookie) != DDI_DMA_MAPPED) {
17185 (void) ddi_dma_mem_free(acc_hdp);
17186 ddi_dma_free_handle(dma_hdp);
17187 return (FALSE);
17188 }
17189
17190 return (TRUE);
17191 }
17192
17193 void
17194 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
17195 {
17196 if (*dma_hdp == NULL)
17197 return;
17198
17199 (void) ddi_dma_unbind_handle(*dma_hdp);
17200 (void) ddi_dma_mem_free(acc_hdp);
17201 ddi_dma_free_handle(dma_hdp);
17202 }