23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
26 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
28 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
29 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
30 * OTHER DEALINGS IN THE SOFTWARE.
31 *
32 * Authors:
33 * Gareth Hughes <gareth@valinux.com>
34 *
35 */
36
37 /*
38 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
39 * Use is subject to license terms.
40 */
41
42 /*
43 * I915 DRM Driver for Solaris
44 *
45 * This driver provides the hardware 3D acceleration support for Intel
46 * integrated video devices (e.g. i8xx/i915/i945 series chipsets), under the
47 * DRI (Direct Rendering Infrastructure). DRM (Direct Rendering Manager) here
48 * means the kernel device driver in DRI.
49 *
50 * I915 driver is a device dependent driver only, it depends on a misc module
51 * named drm for generic DRM operations.
52 */
53
54 #include "drmP.h"
55 #include "i915_drm.h"
56 #include "i915_drv.h"
57 #include "drm_pciids.h"
58
59 /*
60 * copied from vgasubr.h
61 */
62
691 (void) S3_READ(MCHBAR_RENDER_STANDBY);
692
693 S3_WRITE(HWS_PGA, s3_priv->saveHWS);
694 if (IS_I965GM(dev))
695 (void) S3_READ(HWS_PGA);
696
697 i915_restore_display(dev);
698
699 /* Clock gating state */
700 S3_WRITE (D_STATE, s3_priv->saveD_STATE);
701 S3_WRITE (CG_2D_DIS, s3_priv->saveCG_2D_DIS);
702
703 /* Cache mode state */
704 S3_WRITE (CACHE_MODE_0, s3_priv->saveCACHE_MODE_0 | 0xffff0000);
705
706 /* Memory arbitration state */
707 S3_WRITE (MI_ARB_STATE, s3_priv->saveMI_ARB_STATE | 0xffff0000);
708
709 for (i = 0; i < 16; i++) {
710 S3_WRITE(SWF0 + (i << 2), s3_priv->saveSWF0[i]);
711 S3_WRITE(SWF10 + (i << 2), s3_priv->saveSWF1[i+7]);
712 }
713 for (i = 0; i < 3; i++)
714 S3_WRITE(SWF30 + (i << 2), s3_priv->saveSWF2[i]);
715
716 S3_WRITE(I915REG_PGTBL_CTRL, s3_priv->pgtbl_ctl);
717
718 (void) pci_config_teardown(&conf_hdl);
719
720 drm_agp_rebind(dev);
721
722 return (DDI_SUCCESS);
723 }
724
725 static int
726 i915_suspend(struct drm_device *dev)
727 {
728 ddi_acc_handle_t conf_hdl;
729 struct s3_i915_private *s3_priv = dev->s3_private;
730 int i;
731
|
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
26 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
28 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
29 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
30 * OTHER DEALINGS IN THE SOFTWARE.
31 *
32 * Authors:
33 * Gareth Hughes <gareth@valinux.com>
34 *
35 */
36
37 /*
38 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
39 * Use is subject to license terms.
40 */
41
42 /*
43 * Copyright 2014 RackTop Systems.
44 */
45
46 /*
47 * I915 DRM Driver for Solaris
48 *
49 * This driver provides the hardware 3D acceleration support for Intel
50 * integrated video devices (e.g. i8xx/i915/i945 series chipsets), under the
51 * DRI (Direct Rendering Infrastructure). DRM (Direct Rendering Manager) here
52 * means the kernel device driver in DRI.
53 *
54 * I915 driver is a device dependent driver only, it depends on a misc module
55 * named drm for generic DRM operations.
56 */
57
58 #include "drmP.h"
59 #include "i915_drm.h"
60 #include "i915_drv.h"
61 #include "drm_pciids.h"
62
63 /*
64 * copied from vgasubr.h
65 */
66
695 (void) S3_READ(MCHBAR_RENDER_STANDBY);
696
697 S3_WRITE(HWS_PGA, s3_priv->saveHWS);
698 if (IS_I965GM(dev))
699 (void) S3_READ(HWS_PGA);
700
701 i915_restore_display(dev);
702
703 /* Clock gating state */
704 S3_WRITE (D_STATE, s3_priv->saveD_STATE);
705 S3_WRITE (CG_2D_DIS, s3_priv->saveCG_2D_DIS);
706
707 /* Cache mode state */
708 S3_WRITE (CACHE_MODE_0, s3_priv->saveCACHE_MODE_0 | 0xffff0000);
709
710 /* Memory arbitration state */
711 S3_WRITE (MI_ARB_STATE, s3_priv->saveMI_ARB_STATE | 0xffff0000);
712
713 for (i = 0; i < 16; i++) {
714 S3_WRITE(SWF0 + (i << 2), s3_priv->saveSWF0[i]);
715 S3_WRITE(SWF10 + (i << 2), s3_priv->saveSWF1[i]);
716 }
717 for (i = 0; i < 3; i++)
718 S3_WRITE(SWF30 + (i << 2), s3_priv->saveSWF2[i]);
719
720 S3_WRITE(I915REG_PGTBL_CTRL, s3_priv->pgtbl_ctl);
721
722 (void) pci_config_teardown(&conf_hdl);
723
724 drm_agp_rebind(dev);
725
726 return (DDI_SUCCESS);
727 }
728
729 static int
730 i915_suspend(struct drm_device *dev)
731 {
732 ddi_acc_handle_t conf_hdl;
733 struct s3_i915_private *s3_priv = dev->s3_private;
734 int i;
735
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