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4853 illumos-gate is not lint-clean when built with openssl 1.0

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          --- old/usr/src/lib/openssl/libsunw_crypto/bn/x86_64-gcc.c
          +++ new/usr/src/lib/openssl/libsunw_crypto/bn/x86_64-gcc.c
   1      -#include "../bn_lcl.h"
        1 +#include <bn_lcl.h>
   2    2  #if !(defined(__GNUC__) && __GNUC__>=2)
   3      -# include "../bn_asm.c" /* kind of dirty hack for Sun Studio */
        3 +# include "bn_asm.c"    /* kind of dirty hack for Sun Studio */
   4    4  #else
   5    5  /*
   6    6   * x86_64 BIGNUM accelerator version 0.1, December 2002.
   7    7   *
   8    8   * Implemented by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
   9    9   * project.
  10   10   *
  11   11   * Rights for redistribution and usage in source and binary forms are
  12   12   * granted according to the OpenSSL license. Warranty of any kind is
  13   13   * disclaimed.
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  65   65  #undef mul_add
  66   66  #undef sqr
  67   67  
  68   68  /*
  69   69   * "m"(a), "+m"(r)      is the way to favor DirectPath µ-code;
  70   70   * "g"(0)               let the compiler to decide where does it
  71   71   *                      want to keep the value of zero;
  72   72   */
  73   73  #define mul_add(r,a,word,carry) do {    \
  74   74          register BN_ULONG high,low;     \
  75      -        asm ("mulq %3"                  \
       75 +        __asm__ ("mulq %3"                      \
  76   76                  : "=a"(low),"=d"(high)  \
  77   77                  : "a"(word),"m"(a)      \
  78   78                  : "cc");                \
  79      -        asm ("addq %2,%0; adcq %3,%1"   \
       79 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
  80   80                  : "+r"(carry),"+d"(high)\
  81   81                  : "a"(low),"g"(0)       \
  82   82                  : "cc");                \
  83      -        asm ("addq %2,%0; adcq %3,%1"   \
       83 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
  84   84                  : "+m"(r),"+d"(high)    \
  85   85                  : "r"(carry),"g"(0)     \
  86   86                  : "cc");                \
  87   87          carry=high;                     \
  88   88          } while (0)
  89   89  
  90   90  #define mul(r,a,word,carry) do {        \
  91   91          register BN_ULONG high,low;     \
  92      -        asm ("mulq %3"                  \
       92 +        __asm__ ("mulq %3"                      \
  93   93                  : "=a"(low),"=d"(high)  \
  94   94                  : "a"(word),"g"(a)      \
  95   95                  : "cc");                \
  96      -        asm ("addq %2,%0; adcq %3,%1"   \
       96 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
  97   97                  : "+r"(carry),"+d"(high)\
  98   98                  : "a"(low),"g"(0)       \
  99   99                  : "cc");                \
 100  100          (r)=carry, carry=high;          \
 101  101          } while (0)
 102  102  
 103  103  #define sqr(r0,r1,a)                    \
 104      -        asm ("mulq %2"                  \
      104 +        __asm__ ("mulq %2"                      \
 105  105                  : "=a"(r0),"=d"(r1)     \
 106  106                  : "a"(a)                \
 107  107                  : "cc");
 108  108  
 109  109  BN_ULONG bn_mul_add_words(BN_ULONG *rp, const BN_ULONG *ap, int num, BN_ULONG w)
 110  110          {
 111  111          BN_ULONG c1=0;
 112  112  
 113  113          if (num <= 0) return(c1);
 114  114  
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 169  169                  {
 170  170                  sqr(r[0],r[1],a[0]); if (--n == 0) return;
 171  171                  sqr(r[2],r[3],a[1]); if (--n == 0) return;
 172  172                  sqr(r[4],r[5],a[2]);
 173  173                  }
 174  174          }
 175  175  
 176  176  BN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)
 177  177  {       BN_ULONG ret,waste;
 178  178  
 179      -        asm ("divq      %4"
      179 +        __asm__ ("divq  %4"
 180  180                  : "=a"(ret),"=d"(waste)
 181  181                  : "a"(l),"d"(h),"g"(d)
 182  182                  : "cc");
 183  183  
 184  184          return ret;
 185  185  }
 186  186  
 187  187  BN_ULONG bn_add_words (BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp,int n)
 188  188  { BN_ULONG ret=0,i=0;
 189  189  
 190  190          if (n <= 0) return 0;
 191  191  
 192      -        asm (
      192 +        __asm__ (
 193  193          "       subq    %2,%2           \n"
 194  194          ".p2align 4                     \n"
 195  195          "1:     movq    (%4,%2,8),%0    \n"
 196  196          "       adcq    (%5,%2,8),%0    \n"
 197  197          "       movq    %0,(%3,%2,8)    \n"
 198  198          "       leaq    1(%2),%2        \n"
 199  199          "       loop    1b              \n"
 200  200          "       sbbq    %0,%0           \n"
 201  201                  : "=&a"(ret),"+c"(n),"=&r"(i)
 202  202                  : "r"(rp),"r"(ap),"r"(bp)
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 205  205  
 206  206    return ret&1;
 207  207  }
 208  208  
 209  209  #ifndef SIMICS
 210  210  BN_ULONG bn_sub_words (BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp,int n)
 211  211  { BN_ULONG ret=0,i=0;
 212  212  
 213  213          if (n <= 0) return 0;
 214  214  
 215      -        asm (
      215 +        __asm__ (
 216  216          "       subq    %2,%2           \n"
 217  217          ".p2align 4                     \n"
 218  218          "1:     movq    (%4,%2,8),%0    \n"
 219  219          "       sbbq    (%5,%2,8),%0    \n"
 220  220          "       movq    %0,(%3,%2,8)    \n"
 221  221          "       leaq    1(%2),%2        \n"
 222  222          "       loop    1b              \n"
 223  223          "       sbbq    %0,%0           \n"
 224  224                  : "=&a"(ret),"+c"(n),"=&r"(i)
 225  225                  : "r"(rp),"r"(ap),"r"(bp)
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 287  287          BN_ULONG ta=(a),tb=(b),t0;      \
 288  288          t1 = BN_UMULT_HIGH(ta,tb);      \
 289  289          t0 = ta * tb;                   \
 290  290          t2 = t1+t1; c2 += (t2<t1)?1:0;  \
 291  291          t1 = t0+t0; t2 += (t1<t0)?1:0;  \
 292  292          c0 += t1; t2 += (c0<t1)?1:0;    \
 293  293          c1 += t2; c2 += (c1<t2)?1:0;    \
 294  294          }
 295  295  #else
 296  296  #define mul_add_c(a,b,c0,c1,c2) do {    \
 297      -        asm ("mulq %3"                  \
      297 +        __asm__ ("mulq %3"                      \
 298  298                  : "=a"(t1),"=d"(t2)     \
 299  299                  : "a"(a),"m"(b)         \
 300  300                  : "cc");                \
 301      -        asm ("addq %2,%0; adcq %3,%1"   \
      301 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
 302  302                  : "+r"(c0),"+d"(t2)     \
 303  303                  : "a"(t1),"g"(0)        \
 304  304                  : "cc");                \
 305      -        asm ("addq %2,%0; adcq %3,%1"   \
      305 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
 306  306                  : "+r"(c1),"+r"(c2)     \
 307  307                  : "d"(t2),"g"(0)        \
 308  308                  : "cc");                \
 309  309          } while (0)
 310  310  
 311  311  #define sqr_add_c(a,i,c0,c1,c2) do {    \
 312      -        asm ("mulq %2"                  \
      312 +        __asm__ ("mulq %2"                      \
 313  313                  : "=a"(t1),"=d"(t2)     \
 314  314                  : "a"(a[i])             \
 315  315                  : "cc");                \
 316      -        asm ("addq %2,%0; adcq %3,%1"   \
      316 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
 317  317                  : "+r"(c0),"+d"(t2)     \
 318  318                  : "a"(t1),"g"(0)        \
 319  319                  : "cc");                \
 320      -        asm ("addq %2,%0; adcq %3,%1"   \
      320 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
 321  321                  : "+r"(c1),"+r"(c2)     \
 322  322                  : "d"(t2),"g"(0)        \
 323  323                  : "cc");                \
 324  324          } while (0)
 325  325  
 326  326  #define mul_add_c2(a,b,c0,c1,c2) do {   \
 327      -        asm ("mulq %3"                  \
      327 +        __asm__ ("mulq %3"                      \
 328  328                  : "=a"(t1),"=d"(t2)     \
 329  329                  : "a"(a),"m"(b)         \
 330  330                  : "cc");                \
 331      -        asm ("addq %0,%0; adcq %2,%1"   \
      331 +        __asm__ ("addq %0,%0; adcq %2,%1"       \
 332  332                  : "+d"(t2),"+r"(c2)     \
 333  333                  : "g"(0)                \
 334  334                  : "cc");                \
 335      -        asm ("addq %0,%0; adcq %2,%1"   \
      335 +        __asm__ ("addq %0,%0; adcq %2,%1"       \
 336  336                  : "+a"(t1),"+d"(t2)     \
 337  337                  : "g"(0)                \
 338  338                  : "cc");                \
 339      -        asm ("addq %2,%0; adcq %3,%1"   \
      339 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
 340  340                  : "+r"(c0),"+d"(t2)     \
 341  341                  : "a"(t1),"g"(0)        \
 342  342                  : "cc");                \
 343      -        asm ("addq %2,%0; adcq %3,%1"   \
      343 +        __asm__ ("addq %2,%0; adcq %3,%1"       \
 344  344                  : "+r"(c1),"+r"(c2)     \
 345  345                  : "d"(t2),"g"(0)        \
 346  346                  : "cc");                \
 347  347          } while (0)
 348  348  #endif
 349  349  
 350  350  #define sqr_add_c2(a,i,j,c0,c1,c2)      \
 351  351          mul_add_c2((a)[i],(a)[j],c0,c1,c2)
 352  352  
 353  353  void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
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