178 The times printed by the command correspond to the wallclock time when the
 179 hardware counters were actually sampled, instead of when the program told the
 180 kernel to sample them. The time is derived from the same timebase as
 181 \fBgethrtime\fR(3C).
 182 .sp
 183 .LP
 184 The processor cycle counts enabled by the \fB-t\fR option always apply to both
 185 user and system modes, regardless of the settings applied to the performance
 186 counter registers.
 187 .sp
 188 .LP
 189 On some hardware platforms running in system mode using the "sys" token, the
 190 counters are implemented using 32-bit registers. While the kernel attempts to
 191 catch all overflows to synthesize 64-bit counters, because of hardware
 192 implementation restrictions, overflows can be lost unless the sampling interval
 193 is kept short enough. The events most prone to wrap are those that count
 194 processor clock cycles. If such an event is of interest, sampling should occur
 195 frequently so that less than 4 billion clock cycles can occur between samples.
 196 .sp
 197 .LP
 198 The output of cpustat is designed to be readily parseable by \fBnawk\fR(1) and
 199 \fBperl\fR(1), thereby allowing performance tools to be composed by embedding
 200 \fBcpustat\fR in scripts. Alternatively, tools can be constructed directly
 201 using the same \fBAPI\fRs that \fBcpustat\fR is built upon using the facilities
 202 of \fBlibcpc\fR(3LIB). See \fBcpc\fR(3CPC).
 203 .sp
 204 .LP
 205 The \fBcpustat\fR utility only monitors the \fBCPU\fRs that are accessible to
 206 it in the current processor set. Thus, several instances of the utility can be
 207 running on the \fBCPU\fRs in different processor sets. See \fBpsrset\fR(1M) for
 208 more information about processor sets.
 209 .sp
 210 .LP
 211 Because \fBcpustat\fR uses \fBLWP\fRs bound to \fBCPU\fRs, the utility might
 212 have to be terminated before the configuration of the relevant processor can be
 213 changed.
 214 .SH EXAMPLES
 215 .SS "SPARC"
 216 .LP
 217 \fBExample 1 \fRMeasuring External Cache References and Misses
 218 .sp

 324 with the desired sample rate. In this case, some samples might be dropped.
 325 .SH ATTRIBUTES
 326 .sp
 327 .LP
 328 See \fBattributes\fR(5) for descriptions of the following attributes:
 329 .sp
 330 
 331 .sp
 332 .TS
 333 box;
 334 c | c
 335 l | l .
 336 ATTRIBUTE TYPE  ATTRIBUTE VALUE
 337 _
 338 Interface Stability     Evolving
 339 .TE
 340 
 341 .SH SEE ALSO
 342 .sp
 343 .LP
 344 \fBcputrack\fR(1), \fBnawk\fR(1), \fBperl\fR(1), \fBiostat\fR(1M),
 345 \fBprstat\fR(1M), \fBpsrset\fR(1M), \fBvmstat\fR(1M), \fBcpc\fR(3CPC),
 346 \fBcpc_open\fR(3CPC), \fBcpc_bind_cpu\fR(3CPC), \fBgethrtime\fR(3C),
 347 \fBstrtoll\fR(3C), \fBlibcpc\fR(3LIB), \fBattributes\fR(5)
 348 .SH NOTES
 349 .sp
 350 .LP
 351 When \fBcpustat\fR is run on a Pentium 4 with HyperThreading enabled, a CPC set
 352 is bound to only one logical CPU of each physical CPU. See
 353 \fBcpc_bind_cpu\fR(3CPC).

 178 The times printed by the command correspond to the wallclock time when the
 179 hardware counters were actually sampled, instead of when the program told the
 180 kernel to sample them. The time is derived from the same timebase as
 181 \fBgethrtime\fR(3C).
 182 .sp
 183 .LP
 184 The processor cycle counts enabled by the \fB-t\fR option always apply to both
 185 user and system modes, regardless of the settings applied to the performance
 186 counter registers.
 187 .sp
 188 .LP
 189 On some hardware platforms running in system mode using the "sys" token, the
 190 counters are implemented using 32-bit registers. While the kernel attempts to
 191 catch all overflows to synthesize 64-bit counters, because of hardware
 192 implementation restrictions, overflows can be lost unless the sampling interval
 193 is kept short enough. The events most prone to wrap are those that count
 194 processor clock cycles. If such an event is of interest, sampling should occur
 195 frequently so that less than 4 billion clock cycles can occur between samples.
 196 .sp
 197 .LP
 198 The output of cpustat is designed to be readily parseable by \fBawk\fR(1) and
 199 \fBperl\fR(1), thereby allowing performance tools to be composed by embedding
 200 \fBcpustat\fR in scripts. Alternatively, tools can be constructed directly
 201 using the same \fBAPI\fRs that \fBcpustat\fR is built upon using the facilities
 202 of \fBlibcpc\fR(3LIB). See \fBcpc\fR(3CPC).
 203 .sp
 204 .LP
 205 The \fBcpustat\fR utility only monitors the \fBCPU\fRs that are accessible to
 206 it in the current processor set. Thus, several instances of the utility can be
 207 running on the \fBCPU\fRs in different processor sets. See \fBpsrset\fR(1M) for
 208 more information about processor sets.
 209 .sp
 210 .LP
 211 Because \fBcpustat\fR uses \fBLWP\fRs bound to \fBCPU\fRs, the utility might
 212 have to be terminated before the configuration of the relevant processor can be
 213 changed.
 214 .SH EXAMPLES
 215 .SS "SPARC"
 216 .LP
 217 \fBExample 1 \fRMeasuring External Cache References and Misses
 218 .sp

 324 with the desired sample rate. In this case, some samples might be dropped.
 325 .SH ATTRIBUTES
 326 .sp
 327 .LP
 328 See \fBattributes\fR(5) for descriptions of the following attributes:
 329 .sp
 330 
 331 .sp
 332 .TS
 333 box;
 334 c | c
 335 l | l .
 336 ATTRIBUTE TYPE  ATTRIBUTE VALUE
 337 _
 338 Interface Stability     Evolving
 339 .TE
 340 
 341 .SH SEE ALSO
 342 .sp
 343 .LP
 344 \fBcputrack\fR(1), \fBawk\fR(1), \fBperl\fR(1), \fBiostat\fR(1M),
 345 \fBprstat\fR(1M), \fBpsrset\fR(1M), \fBvmstat\fR(1M), \fBcpc\fR(3CPC),
 346 \fBcpc_open\fR(3CPC), \fBcpc_bind_cpu\fR(3CPC), \fBgethrtime\fR(3C),
 347 \fBstrtoll\fR(3C), \fBlibcpc\fR(3LIB), \fBattributes\fR(5)
 348 .SH NOTES
 349 .sp
 350 .LP
 351 When \fBcpustat\fR is run on a Pentium 4 with HyperThreading enabled, a CPC set
 352 is bound to only one logical CPU of each physical CPU. See
 353 \fBcpc_bind_cpu\fR(3CPC).