1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 * Copyright 2016 Tegile Systems, Inc. All rights reserved.
15 * Copyright (c) 2016 The MathWorks, Inc. All rights reserved.
16 */
17
18 /*
19 * blkdev driver for NVMe compliant storage devices
20 *
21 * This driver was written to conform to version 1.0e of the NVMe specification.
22 * It may work with newer versions, but that is completely untested and disabled
23 * by default.
24 *
25 * The driver has only been tested on x86 systems and will not work on big-
26 * endian systems without changes to the code accessing registers and data
27 * structures used by the hardware.
28 *
29 *
30 * Interrupt Usage:
31 *
32 * The driver will use a FIXED interrupt while configuring the device as the
33 * specification requires. Later in the attach process it will switch to MSI-X
34 * or MSI if supported. The driver wants to have one interrupt vector per CPU,
35 * but it will work correctly if less are available. Interrupts can be shared
36 * by queues, the interrupt handler will iterate through the I/O queue array by
37 * steps of n_intr_cnt. Usually only the admin queue will share an interrupt
38 * with one I/O queue. The interrupt handler will retrieve completed commands
39 * from all queues sharing an interrupt vector and will post them to a taskq
40 * for completion processing.
41 *
42 *
43 * Command Processing:
44 *
45 * NVMe devices can have up to 65536 I/O queue pairs, with each queue holding up
46 * to 65536 I/O commands. The driver will configure one I/O queue pair per
47 * available interrupt vector, with the queue length usually much smaller than
48 * the maximum of 65536. If the hardware doesn't provide enough queues, fewer
49 * interrupt vectors will be used.
50 *
51 * Additionally the hardware provides a single special admin queue pair that can
52 * hold up to 4096 admin commands.
53 *
54 * From the hardware perspective both queues of a queue pair are independent,
55 * but they share some driver state: the command array (holding pointers to
56 * commands currently being processed by the hardware) and the active command
57 * counter. Access to the submission side of a queue pair and the shared state
58 * is protected by nq_mutex. The completion side of a queue pair does not need
59 * that protection apart from its access to the shared state; it is called only
60 * in the interrupt handler which does not run concurrently for the same
61 * interrupt vector.
62 *
63 * When a command is submitted to a queue pair the active command counter is
64 * incremented and a pointer to the command is stored in the command array. The
65 * array index is used as command identifier (CID) in the submission queue
66 * entry. Some commands may take a very long time to complete, and if the queue
67 * wraps around in that time a submission may find the next array slot to still
68 * be used by a long-running command. In this case the array is sequentially
69 * searched for the next free slot. The length of the command array is the same
70 * as the configured queue length.
71 *
72 *
73 * Namespace Support:
74 *
75 * NVMe devices can have multiple namespaces, each being a independent data
76 * store. The driver supports multiple namespaces and creates a blkdev interface
77 * for each namespace found. Namespaces can have various attributes to support
78 * thin provisioning and protection information. This driver does not support
79 * any of this and ignores namespaces that have these attributes.
80 *
81 *
82 * Blkdev Interface:
83 *
84 * This driver uses blkdev to do all the heavy lifting involved with presenting
85 * a disk device to the system. As a result, the processing of I/O requests is
86 * relatively simple as blkdev takes care of partitioning, boundary checks, DMA
87 * setup, and splitting of transfers into manageable chunks.
88 *
89 * I/O requests coming in from blkdev are turned into NVM commands and posted to
90 * an I/O queue. The queue is selected by taking the CPU id modulo the number of
91 * queues. There is currently no timeout handling of I/O commands.
92 *
93 * Blkdev also supports querying device/media information and generating a
94 * devid. The driver reports the best block size as determined by the namespace
95 * format back to blkdev as physical block size to support partition and block
96 * alignment. The devid is composed using the device vendor ID, model number,
97 * serial number, and the namespace ID.
98 *
99 *
100 * Error Handling:
101 *
102 * Error handling is currently limited to detecting fatal hardware errors,
103 * either by asynchronous events, or synchronously through command status or
104 * admin command timeouts. In case of severe errors the device is fenced off,
105 * all further requests will return EIO. FMA is then called to fault the device.
106 *
107 * The hardware has a limit for outstanding asynchronous event requests. Before
108 * this limit is known the driver assumes it is at least 1 and posts a single
109 * asynchronous request. Later when the limit is known more asynchronous event
110 * requests are posted to allow quicker reception of error information. When an
111 * asynchronous event is posted by the hardware the driver will parse the error
112 * status fields and log information or fault the device, depending on the
113 * severity of the asynchronous event. The asynchronous event request is then
114 * reused and posted to the admin queue again.
115 *
116 * On command completion the command status is checked for errors. In case of
117 * errors indicating a driver bug the driver panics. Almost all other error
118 * status values just cause EIO to be returned.
119 *
120 * Command timeouts are currently detected for all admin commands except
121 * asynchronous event requests. If a command times out and the hardware appears
122 * to be healthy the driver attempts to abort the command. If this fails the
123 * driver assumes the device to be dead, fences it off, and calls FMA to retire
124 * it. In general admin commands are issued at attach time only. No timeout
125 * handling of normal I/O commands is presently done.
126 *
127 * In some cases it may be possible that the ABORT command times out, too. In
128 * that case the device is also declared dead and fenced off.
129 *
130 *
131 * Quiesce / Fast Reboot:
132 *
133 * The driver currently does not support fast reboot. A quiesce(9E) entry point
134 * is still provided which is used to send a shutdown notification to the
135 * device.
136 *
137 *
138 * Driver Configuration:
139 *
140 * The following driver properties can be changed to control some aspects of the
141 * drivers operation:
142 * - strict-version: can be set to 0 to allow devices conforming to newer
143 * versions to be used
144 * - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor
145 * specific command status as a fatal error leading device faulting
146 * - admin-queue-len: the maximum length of the admin queue (16-4096)
147 * - io-queue-len: the maximum length of the I/O queues (16-65536)
148 * - async-event-limit: the maximum number of asynchronous event requests to be
149 * posted by the driver
150 *
151 *
152 * TODO:
153 * - figure out sane default for I/O queue depth reported to blkdev
154 * - polled I/O support to support kernel core dumping
155 * - FMA handling of media errors
156 * - support for the Volatile Write Cache
157 * - support for devices supporting very large I/O requests using chained PRPs
158 * - support for querying log pages from user space
159 * - support for configuring hardware parameters like interrupt coalescing
160 * - support for media formatting and hard partitioning into namespaces
161 * - support for big-endian systems
162 * - support for fast reboot
163 */
164
165 #include <sys/byteorder.h>
166 #ifdef _BIG_ENDIAN
167 #error nvme driver needs porting for big-endian platforms
168 #endif
169
170 #include <sys/modctl.h>
171 #include <sys/conf.h>
172 #include <sys/devops.h>
173 #include <sys/ddi.h>
174 #include <sys/sunddi.h>
175 #include <sys/bitmap.h>
176 #include <sys/sysmacros.h>
177 #include <sys/param.h>
178 #include <sys/varargs.h>
179 #include <sys/cpuvar.h>
180 #include <sys/disp.h>
181 #include <sys/blkdev.h>
182 #include <sys/atomic.h>
183 #include <sys/archsystm.h>
184 #include <sys/sata/sata_hba.h>
185 #include <sys/time.h>
186
187 #include "nvme_reg.h"
188 #include "nvme_var.h"
189
190
191 /* NVMe spec version supported */
192 static const int nvme_version_major = 1;
193 static const int nvme_version_minor = 0;
194
195 /* tunable for admin command timeout in seconds, default is 1s */
196 static volatile int nvme_admin_cmd_timeout = 1;
197
198 static int nvme_attach(dev_info_t *, ddi_attach_cmd_t);
199 static int nvme_detach(dev_info_t *, ddi_detach_cmd_t);
200 static int nvme_quiesce(dev_info_t *);
201 static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *);
202 static int nvme_setup_interrupts(nvme_t *, int, int);
203 static void nvme_release_interrupts(nvme_t *);
204 static uint_t nvme_intr(caddr_t, caddr_t);
205
206 static void nvme_shutdown(nvme_t *, int, boolean_t);
207 static boolean_t nvme_reset(nvme_t *, boolean_t);
208 static int nvme_init(nvme_t *);
209 static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int);
210 static void nvme_free_cmd(nvme_cmd_t *);
211 static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t,
212 bd_xfer_t *);
213 static int nvme_admin_cmd(nvme_cmd_t *, int);
214 static int nvme_submit_cmd(nvme_qpair_t *, nvme_cmd_t *);
215 static int nvme_process_cq_cmds(nvme_t *, nvme_qpair_t *);
216 static boolean_t nvme_wait_cmd(nvme_cmd_t *, uint_t);
217 static void nvme_wakeup_cmd(void *);
218 static void nvme_async_event_task(void *);
219
220 static int nvme_check_unknown_cmd_status(nvme_cmd_t *);
221 static int nvme_check_vendor_cmd_status(nvme_cmd_t *);
222 static int nvme_check_integrity_cmd_status(nvme_cmd_t *);
223 static int nvme_check_specific_cmd_status(nvme_cmd_t *);
224 static int nvme_check_generic_cmd_status(nvme_cmd_t *);
225 static inline int nvme_check_cmd_status(nvme_cmd_t *);
226
227 static void nvme_abort_cmd(nvme_cmd_t *);
228 static int nvme_async_event(nvme_t *);
229 static void *nvme_get_logpage(nvme_t *, uint8_t, ...);
230 static void *nvme_identify(nvme_t *, uint32_t);
231 static int nvme_set_nqueues(nvme_t *, uint16_t);
232
233 static void nvme_free_dma(nvme_dma_t *);
234 static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *,
235 nvme_dma_t **);
236 static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t,
237 nvme_dma_t **);
238 static void nvme_free_qpair(nvme_qpair_t *);
239 static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, int);
240 static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t);
241
242 static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t);
243 static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t);
244 static inline uint64_t nvme_get64(nvme_t *, uintptr_t);
245 static inline uint32_t nvme_get32(nvme_t *, uintptr_t);
246
247 static boolean_t nvme_check_regs_hdl(nvme_t *);
248 static boolean_t nvme_check_dma_hdl(nvme_dma_t *);
249
250 static int nvme_fill_prp(nvme_cmd_t *, bd_xfer_t *);
251
252 static void nvme_bd_xfer_done(void *);
253 static void nvme_bd_driveinfo(void *, bd_drive_t *);
254 static int nvme_bd_mediainfo(void *, bd_media_t *);
255 static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t);
256 static int nvme_bd_read(void *, bd_xfer_t *);
257 static int nvme_bd_write(void *, bd_xfer_t *);
258 static int nvme_bd_sync(void *, bd_xfer_t *);
259 static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *);
260
261 static void nvme_prepare_devid(nvme_t *, uint32_t);
262
263 static void nvme_intr_monitor(void *arg);
264
265 static void *nvme_state;
266 static kmem_cache_t *nvme_cmd_cache;
267
268 static list_t nvme_qp_list;
269 static kmutex_t nvme_global_mutex;
270 static ddi_periodic_t nvme_cyclic;
271 int nvme_cyclic_seconds = 5;
272 hrtime_t nvme_intr_timeout_ns = 3 * NANOSEC;
273 uint64_t nvme_intr_timeouts = 0;
274 boolean_t nvme_enable_intr_monitoring = B_TRUE;
275
276 /*
277 * DMA attributes for queue DMA memory
278 *
279 * Queue DMA memory must be page aligned. The maximum length of a queue is
280 * 65536 entries, and an entry can be 64 bytes long.
281 */
282 static ddi_dma_attr_t nvme_queue_dma_attr = {
283 .dma_attr_version = DMA_ATTR_V0,
284 .dma_attr_addr_lo = 0,
285 .dma_attr_addr_hi = 0xffffffffffffffffULL,
286 .dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1,
287 .dma_attr_align = 0x1000,
288 .dma_attr_burstsizes = 0x7ff,
289 .dma_attr_minxfer = 0x1000,
290 .dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t),
291 .dma_attr_seg = 0xffffffffffffffffULL,
292 .dma_attr_sgllen = 1,
293 .dma_attr_granular = 1,
294 .dma_attr_flags = 0,
295 };
296
297 /*
298 * DMA attributes for transfers using Physical Region Page (PRP) entries
299 *
300 * A PRP entry describes one page of DMA memory using the page size specified
301 * in the controller configuration's memory page size register (CC.MPS). It uses
302 * a 64bit base address aligned to this page size. There is no limitation on
303 * chaining PRPs together for arbitrarily large DMA transfers.
304 */
305 static ddi_dma_attr_t nvme_prp_dma_attr = {
306 .dma_attr_version = DMA_ATTR_V0,
307 .dma_attr_addr_lo = 0,
308 .dma_attr_addr_hi = 0xffffffffffffffffULL,
309 .dma_attr_count_max = 0xfff,
310 .dma_attr_align = 0x1000,
311 .dma_attr_burstsizes = 0x7ff,
312 .dma_attr_minxfer = 0x1000,
313 .dma_attr_maxxfer = 0x1000,
314 .dma_attr_seg = 0xfff,
315 .dma_attr_sgllen = -1,
316 .dma_attr_granular = 1,
317 .dma_attr_flags = 0,
318 };
319
320 /*
321 * DMA attributes for transfers using scatter/gather lists
322 *
323 * A SGL entry describes a chunk of DMA memory using a 64bit base address and a
324 * 32bit length field. SGL Segment and SGL Last Segment entries require the
325 * length to be a multiple of 16 bytes.
326 */
327 static ddi_dma_attr_t nvme_sgl_dma_attr = {
328 .dma_attr_version = DMA_ATTR_V0,
329 .dma_attr_addr_lo = 0,
330 .dma_attr_addr_hi = 0xffffffffffffffffULL,
331 .dma_attr_count_max = 0xffffffffUL,
332 .dma_attr_align = 1,
333 .dma_attr_burstsizes = 0x7ff,
334 .dma_attr_minxfer = 0x10,
335 .dma_attr_maxxfer = 0xfffffffffULL,
336 .dma_attr_seg = 0xffffffffffffffffULL,
337 .dma_attr_sgllen = -1,
338 .dma_attr_granular = 0x10,
339 .dma_attr_flags = 0
340 };
341
342 static ddi_device_acc_attr_t nvme_reg_acc_attr = {
343 .devacc_attr_version = DDI_DEVICE_ATTR_V0,
344 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC,
345 .devacc_attr_dataorder = DDI_STRICTORDER_ACC
346 };
347
348 static struct dev_ops nvme_dev_ops = {
349 .devo_rev = DEVO_REV,
350 .devo_refcnt = 0,
351 .devo_getinfo = ddi_no_info,
352 .devo_identify = nulldev,
353 .devo_probe = nulldev,
354 .devo_attach = nvme_attach,
355 .devo_detach = nvme_detach,
356 .devo_reset = nodev,
357 .devo_cb_ops = NULL,
358 .devo_bus_ops = NULL,
359 .devo_power = NULL,
360 .devo_quiesce = nvme_quiesce,
361 };
362
363 static struct modldrv nvme_modldrv = {
364 .drv_modops = &mod_driverops,
365 .drv_linkinfo = "NVMe v1.0e",
366 .drv_dev_ops = &nvme_dev_ops
367 };
368
369 static struct modlinkage nvme_modlinkage = {
370 .ml_rev = MODREV_1,
371 .ml_linkage = { &nvme_modldrv, NULL }
372 };
373
374 static bd_ops_t nvme_bd_ops = {
375 .o_version = BD_OPS_VERSION_0,
376 .o_drive_info = nvme_bd_driveinfo,
377 .o_media_info = nvme_bd_mediainfo,
378 .o_devid_init = nvme_bd_devid,
379 .o_sync_cache = nvme_bd_sync,
380 .o_read = nvme_bd_read,
381 .o_write = nvme_bd_write,
382 };
383
384 int
385 _init(void)
386 {
387 int error;
388
389 error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1);
390 if (error != DDI_SUCCESS)
391 return (error);
392
393 nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache",
394 sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0);
395
396 mutex_init(&nvme_global_mutex, NULL, MUTEX_DRIVER, 0);
397
398 list_create(&nvme_qp_list, sizeof (nvme_qpair_t),
399 offsetof(nvme_qpair_t, nq_list_node));
400
401 nvme_cyclic = ddi_periodic_add(nvme_intr_monitor, NULL,
402 NANOSEC * nvme_cyclic_seconds, DDI_IPL_0);
403
404 bd_mod_init(&nvme_dev_ops);
405
406 error = mod_install(&nvme_modlinkage);
407 if (error != DDI_SUCCESS) {
408 ddi_soft_state_fini(&nvme_state);
409 bd_mod_fini(&nvme_dev_ops);
410 }
411
412 return (error);
413 }
414
415 int
416 _fini(void)
417 {
418 int error;
419
420 error = mod_remove(&nvme_modlinkage);
421 if (error == DDI_SUCCESS) {
422 ddi_soft_state_fini(&nvme_state);
423 kmem_cache_destroy(nvme_cmd_cache);
424 if (nvme_cyclic != NULL) {
425 ddi_periodic_delete(nvme_cyclic);
426 nvme_cyclic = NULL;
427 }
428 mutex_destroy(&nvme_global_mutex);
429 bd_mod_fini(&nvme_dev_ops);
430 }
431
432 return (error);
433 }
434
435 int
436 _info(struct modinfo *modinfop)
437 {
438 return (mod_info(&nvme_modlinkage, modinfop));
439 }
440
441 static inline void
442 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val)
443 {
444 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
445
446 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
447 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
448 }
449
450 static inline void
451 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val)
452 {
453 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
454
455 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
456 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
457 }
458
459 static inline uint64_t
460 nvme_get64(nvme_t *nvme, uintptr_t reg)
461 {
462 uint64_t val;
463
464 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
465
466 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
467 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
468
469 return (val);
470 }
471
472 static inline uint32_t
473 nvme_get32(nvme_t *nvme, uintptr_t reg)
474 {
475 uint32_t val;
476
477 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
478
479 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
480 val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg));
481
482 return (val);
483 }
484
485 static boolean_t
486 nvme_check_regs_hdl(nvme_t *nvme)
487 {
488 ddi_fm_error_t error;
489
490 ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION);
491
492 if (error.fme_status != DDI_FM_OK)
493 return (B_TRUE);
494
495 return (B_FALSE);
496 }
497
498 static boolean_t
499 nvme_check_dma_hdl(nvme_dma_t *dma)
500 {
501 ddi_fm_error_t error;
502
503 if (dma == NULL)
504 return (B_FALSE);
505
506 ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION);
507
508 if (error.fme_status != DDI_FM_OK)
509 return (B_TRUE);
510
511 return (B_FALSE);
512 }
513
514 static void
515 nvme_free_dma(nvme_dma_t *dma)
516 {
517 if (dma->nd_dmah != NULL)
518 (void) ddi_dma_unbind_handle(dma->nd_dmah);
519 if (dma->nd_acch != NULL)
520 ddi_dma_mem_free(&dma->nd_acch);
521 if (dma->nd_dmah != NULL)
522 ddi_dma_free_handle(&dma->nd_dmah);
523 kmem_free(dma, sizeof (nvme_dma_t));
524 }
525
526 static int
527 nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags,
528 ddi_dma_attr_t *dma_attr, nvme_dma_t **ret)
529 {
530 nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP);
531
532 if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL,
533 &dma->nd_dmah) != DDI_SUCCESS) {
534 /*
535 * Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and
536 * the only other possible error is DDI_DMA_BADATTR which
537 * indicates a driver bug which should cause a panic.
538 */
539 dev_err(nvme->n_dip, CE_PANIC,
540 "!failed to get DMA handle, check DMA attributes");
541 return (DDI_FAILURE);
542 }
543
544 /*
545 * ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified
546 * or the flags are conflicting, which isn't the case here.
547 */
548 (void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr,
549 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp,
550 &dma->nd_len, &dma->nd_acch);
551
552 if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp,
553 dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
554 &dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) {
555 dev_err(nvme->n_dip, CE_WARN,
556 "!failed to bind DMA memory");
557 atomic_inc_32(&nvme->n_dma_bind_err);
558 *ret = NULL;
559 nvme_free_dma(dma);
560 return (DDI_FAILURE);
561 }
562
563 bzero(dma->nd_memp, dma->nd_len);
564
565 *ret = dma;
566 return (DDI_SUCCESS);
567 }
568
569 static int
570 nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len,
571 uint_t flags, nvme_dma_t **dma)
572 {
573 uint32_t len = nentry * qe_len;
574 ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr;
575
576 len = roundup(len, nvme->n_pagesize);
577
578 q_dma_attr.dma_attr_minxfer = len;
579
580 if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma)
581 != DDI_SUCCESS) {
582 dev_err(nvme->n_dip, CE_WARN,
583 "!failed to get DMA memory for queue");
584 goto fail;
585 }
586
587 if ((*dma)->nd_ncookie != 1) {
588 dev_err(nvme->n_dip, CE_WARN,
589 "!got too many cookies for queue DMA");
590 goto fail;
591 }
592
593 return (DDI_SUCCESS);
594
595 fail:
596 if (*dma) {
597 nvme_free_dma(*dma);
598 *dma = NULL;
599 }
600
601 return (DDI_FAILURE);
602 }
603
604 static void
605 nvme_free_qpair(nvme_qpair_t *qp)
606 {
607 int i;
608
609 mutex_destroy(&qp->nq_mutex);
610
611 if (qp->nq_sqdma != NULL)
612 nvme_free_dma(qp->nq_sqdma);
613 if (qp->nq_cqdma != NULL)
614 nvme_free_dma(qp->nq_cqdma);
615
616 if (qp->nq_active_cmds > 0)
617 for (i = 0; i != qp->nq_nentry; i++)
618 if (qp->nq_cmd[i] != NULL)
619 nvme_free_cmd(qp->nq_cmd[i]);
620
621 if (qp->nq_cmd != NULL)
622 kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry);
623
624 kmem_free(qp, sizeof (nvme_qpair_t));
625 }
626
627 static int
628 nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp,
629 int idx)
630 {
631 nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP);
632
633 mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER,
634 DDI_INTR_PRI(nvme->n_intr_pri));
635
636 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t),
637 DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS)
638 goto fail;
639
640 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t),
641 DDI_DMA_READ, &qp->nq_cqdma) != DDI_SUCCESS)
642 goto fail;
643
644 qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp;
645 qp->nq_cq = (nvme_cqe_t *)qp->nq_cqdma->nd_memp;
646 qp->nq_nentry = nentry;
647
648 qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx);
649 qp->nq_cqhdbl = NVME_REG_CQHDBL(nvme, idx);
650
651 qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP);
652 qp->nq_next_cmd = 0;
653
654 *nqp = qp;
655 return (DDI_SUCCESS);
656
657 fail:
658 nvme_free_qpair(qp);
659 *nqp = NULL;
660
661 return (DDI_FAILURE);
662 }
663
664 static nvme_cmd_t *
665 nvme_alloc_cmd(nvme_t *nvme, int kmflag)
666 {
667 nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag);
668
669 if (cmd == NULL)
670 return (cmd);
671
672 bzero(cmd, sizeof (nvme_cmd_t));
673
674 cmd->nc_nvme = nvme;
675
676 mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER,
677 DDI_INTR_PRI(nvme->n_intr_pri));
678 cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL);
679
680 return (cmd);
681 }
682
683 static void
684 nvme_free_cmd(nvme_cmd_t *cmd)
685 {
686 if (cmd->nc_dma) {
687 nvme_free_dma(cmd->nc_dma);
688 cmd->nc_dma = NULL;
689 }
690
691 cv_destroy(&cmd->nc_cv);
692 mutex_destroy(&cmd->nc_mutex);
693
694 kmem_cache_free(nvme_cmd_cache, cmd);
695 }
696
697 static int
698 nvme_submit_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
699 {
700 nvme_reg_sqtdbl_t tail = { 0 };
701
702 mutex_enter(&qp->nq_mutex);
703
704 if (qp->nq_active_cmds == qp->nq_nentry) {
705 mutex_exit(&qp->nq_mutex);
706 return (DDI_FAILURE);
707 }
708
709 cmd->nc_completed = B_FALSE;
710
711 /*
712 * Try to insert the cmd into the active cmd array at the nq_next_cmd
713 * slot. If the slot is already occupied advance to the next slot and
714 * try again. This can happen for long running commands like async event
715 * requests.
716 */
717 while (qp->nq_cmd[qp->nq_next_cmd] != NULL)
718 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
719 qp->nq_cmd[qp->nq_next_cmd] = cmd;
720
721 qp->nq_active_cmds++;
722
723 cmd->nc_sqe.sqe_cid = qp->nq_next_cmd;
724 bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t));
725 (void) ddi_dma_sync(qp->nq_sqdma->nd_dmah,
726 sizeof (nvme_sqe_t) * qp->nq_sqtail,
727 sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV);
728 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
729
730 tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry;
731 nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r);
732
733 if (nvme_enable_intr_monitoring)
734 qp->nq_ts = gethrtime();
735 mutex_exit(&qp->nq_mutex);
736
737 return (DDI_SUCCESS);
738 }
739
740 static int
741 nvme_process_cq_cmds(nvme_t *nvme, nvme_qpair_t *qp)
742 {
743 nvme_reg_cqhdbl_t head = { 0 };
744
745 nvme_cqe_t *cqe;
746 nvme_cmd_t *cmd;
747 int cnt_cmds = 0;
748
749 (void) ddi_dma_sync(qp->nq_cqdma->nd_dmah, 0,
750 sizeof (nvme_cqe_t) * qp->nq_nentry, DDI_DMA_SYNC_FORKERNEL);
751
752 cqe = &qp->nq_cq[qp->nq_cqhead];
753 /* Check phase tag of CQE. Hardware inverts it for new entries. */
754 if (cqe->cqe_sf.sf_p == qp->nq_phase)
755 return (cnt_cmds);
756
757 mutex_enter(&qp->nq_mutex);
758 while (cqe->cqe_sf.sf_p != qp->nq_phase) {
759 ASSERT(nvme->n_ioq[cqe->cqe_sqid] == qp);
760 ASSERT(cqe->cqe_cid < qp->nq_nentry);
761
762 cmd = qp->nq_cmd[cqe->cqe_cid];
763 qp->nq_cmd[cqe->cqe_cid] = NULL;
764 qp->nq_active_cmds--;
765
766 ASSERT(cmd != NULL);
767 ASSERT(cmd->nc_nvme == nvme);
768 ASSERT(cmd->nc_sqid == cqe->cqe_sqid);
769 ASSERT(cmd->nc_sqe.sqe_cid == cqe->cqe_cid);
770 bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t));
771
772 qp->nq_sqhead = cqe->cqe_sqhd;
773
774 qp->nq_cqhead = (qp->nq_cqhead + 1) % qp->nq_nentry;
775
776 /* Toggle phase on wrap-around. */
777 if (qp->nq_cqhead == 0)
778 qp->nq_phase = qp->nq_phase ? 0 : 1;
779 taskq_dispatch_ent((taskq_t *)cmd->nc_nvme->n_cmd_taskq,
780 cmd->nc_callback, cmd, TQ_NOSLEEP, &cmd->nc_tqent);
781 cnt_cmds++;
782 cqe = &qp->nq_cq[qp->nq_cqhead];
783 }
784
785 if (cnt_cmds != 0) {
786 head.b.cqhdbl_cqh = qp->nq_cqhead;
787 nvme_put32(nvme, qp->nq_cqhdbl, head.r);
788 if (nvme_enable_intr_monitoring)
789 qp->nq_ts = gethrtime();
790 }
791
792 mutex_exit(&qp->nq_mutex);
793
794 return (cnt_cmds);
795 }
796
797 static int
798 nvme_check_unknown_cmd_status(nvme_cmd_t *cmd)
799 {
800 nvme_cqe_t *cqe = &cmd->nc_cqe;
801
802 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
803 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
804 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
805 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
806 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
807
808 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
809
810 if (cmd->nc_nvme->n_strict_version) {
811 cmd->nc_nvme->n_dead = B_TRUE;
812 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
813 }
814
815 return (EIO);
816 }
817
818 static int
819 nvme_check_vendor_cmd_status(nvme_cmd_t *cmd)
820 {
821 nvme_cqe_t *cqe = &cmd->nc_cqe;
822
823 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
824 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
825 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
826 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
827 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
828 if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) {
829 cmd->nc_nvme->n_dead = B_TRUE;
830 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
831 }
832
833 return (EIO);
834 }
835
836 static int
837 nvme_check_integrity_cmd_status(nvme_cmd_t *cmd)
838 {
839 nvme_cqe_t *cqe = &cmd->nc_cqe;
840
841 switch (cqe->cqe_sf.sf_sc) {
842 case NVME_CQE_SC_INT_NVM_WRITE:
843 /* write fail */
844 /* TODO: post ereport */
845 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
846 return (EIO);
847
848 case NVME_CQE_SC_INT_NVM_READ:
849 /* read fail */
850 /* TODO: post ereport */
851 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
852 return (EIO);
853
854 default:
855 return (nvme_check_unknown_cmd_status(cmd));
856 }
857 }
858
859 static int
860 nvme_check_generic_cmd_status(nvme_cmd_t *cmd)
861 {
862 nvme_cqe_t *cqe = &cmd->nc_cqe;
863
864 switch (cqe->cqe_sf.sf_sc) {
865 case NVME_CQE_SC_GEN_SUCCESS:
866 return (0);
867
868 /*
869 * Errors indicating a bug in the driver should cause a panic.
870 */
871 case NVME_CQE_SC_GEN_INV_OPC:
872 /* Invalid Command Opcode */
873 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
874 "invalid opcode in cmd %p", (void *)cmd);
875 return (0);
876
877 case NVME_CQE_SC_GEN_INV_FLD:
878 /* Invalid Field in Command */
879 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
880 "invalid field in cmd %p", (void *)cmd);
881 return (0);
882
883 case NVME_CQE_SC_GEN_ID_CNFL:
884 /* Command ID Conflict */
885 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
886 "cmd ID conflict in cmd %p", (void *)cmd);
887 return (0);
888
889 case NVME_CQE_SC_GEN_INV_NS:
890 /* Invalid Namespace or Format */
891 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
892 "invalid NS/format in cmd %p", (void *)cmd);
893 return (0);
894
895 case NVME_CQE_SC_GEN_NVM_LBA_RANGE:
896 /* LBA Out Of Range */
897 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
898 "LBA out of range in cmd %p", (void *)cmd);
899 return (0);
900
901 /*
902 * Non-fatal errors, handle gracefully.
903 */
904 case NVME_CQE_SC_GEN_DATA_XFR_ERR:
905 /* Data Transfer Error (DMA) */
906 /* TODO: post ereport */
907 atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err);
908 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
909 return (EIO);
910
911 case NVME_CQE_SC_GEN_INTERNAL_ERR:
912 /*
913 * Internal Error. The spec (v1.0, section 4.5.1.2) says
914 * detailed error information is returned as async event,
915 * so we pretty much ignore the error here and handle it
916 * in the async event handler.
917 */
918 atomic_inc_32(&cmd->nc_nvme->n_internal_err);
919 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
920 return (EIO);
921
922 case NVME_CQE_SC_GEN_ABORT_REQUEST:
923 /*
924 * Command Abort Requested. This normally happens only when a
925 * command times out.
926 */
927 /* TODO: post ereport or change blkdev to handle this? */
928 atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err);
929 return (ECANCELED);
930
931 case NVME_CQE_SC_GEN_ABORT_PWRLOSS:
932 /* Command Aborted due to Power Loss Notification */
933 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
934 cmd->nc_nvme->n_dead = B_TRUE;
935 return (EIO);
936
937 case NVME_CQE_SC_GEN_ABORT_SQ_DEL:
938 /* Command Aborted due to SQ Deletion */
939 atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del);
940 return (EIO);
941
942 case NVME_CQE_SC_GEN_NVM_CAP_EXC:
943 /* Capacity Exceeded */
944 atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc);
945 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
946 return (EIO);
947
948 case NVME_CQE_SC_GEN_NVM_NS_NOTRDY:
949 /* Namespace Not Ready */
950 atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy);
951 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
952 return (EIO);
953
954 default:
955 return (nvme_check_unknown_cmd_status(cmd));
956 }
957 }
958
959 static int
960 nvme_check_specific_cmd_status(nvme_cmd_t *cmd)
961 {
962 nvme_cqe_t *cqe = &cmd->nc_cqe;
963
964 switch (cqe->cqe_sf.sf_sc) {
965 case NVME_CQE_SC_SPC_INV_CQ:
966 /* Completion Queue Invalid */
967 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE);
968 atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err);
969 return (EINVAL);
970
971 case NVME_CQE_SC_SPC_INV_QID:
972 /* Invalid Queue Identifier */
973 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
974 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE ||
975 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE ||
976 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
977 atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err);
978 return (EINVAL);
979
980 case NVME_CQE_SC_SPC_MAX_QSZ_EXC:
981 /* Max Queue Size Exceeded */
982 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
983 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
984 atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc);
985 return (EINVAL);
986
987 case NVME_CQE_SC_SPC_ABRT_CMD_EXC:
988 /* Abort Command Limit Exceeded */
989 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT);
990 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
991 "abort command limit exceeded in cmd %p", (void *)cmd);
992 return (0);
993
994 case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC:
995 /* Async Event Request Limit Exceeded */
996 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT);
997 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
998 "async event request limit exceeded in cmd %p",
999 (void *)cmd);
1000 return (0);
1001
1002 case NVME_CQE_SC_SPC_INV_INT_VECT:
1003 /* Invalid Interrupt Vector */
1004 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1005 atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect);
1006 return (EINVAL);
1007
1008 case NVME_CQE_SC_SPC_INV_LOG_PAGE:
1009 /* Invalid Log Page */
1010 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE);
1011 atomic_inc_32(&cmd->nc_nvme->n_inv_log_page);
1012 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1013 return (EINVAL);
1014
1015 case NVME_CQE_SC_SPC_INV_FORMAT:
1016 /* Invalid Format */
1017 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT);
1018 atomic_inc_32(&cmd->nc_nvme->n_inv_format);
1019 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1020 return (EINVAL);
1021
1022 case NVME_CQE_SC_SPC_INV_Q_DEL:
1023 /* Invalid Queue Deletion */
1024 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1025 atomic_inc_32(&cmd->nc_nvme->n_inv_q_del);
1026 return (EINVAL);
1027
1028 case NVME_CQE_SC_SPC_NVM_CNFL_ATTR:
1029 /* Conflicting Attributes */
1030 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT ||
1031 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1032 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1033 atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr);
1034 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1035 return (EINVAL);
1036
1037 case NVME_CQE_SC_SPC_NVM_INV_PROT:
1038 /* Invalid Protection Information */
1039 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE ||
1040 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1041 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1042 atomic_inc_32(&cmd->nc_nvme->n_inv_prot);
1043 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1044 return (EINVAL);
1045
1046 case NVME_CQE_SC_SPC_NVM_READONLY:
1047 /* Write to Read Only Range */
1048 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1049 atomic_inc_32(&cmd->nc_nvme->n_readonly);
1050 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1051 return (EROFS);
1052
1053 default:
1054 return (nvme_check_unknown_cmd_status(cmd));
1055 }
1056 }
1057
1058 static inline int
1059 nvme_check_cmd_status(nvme_cmd_t *cmd)
1060 {
1061 nvme_cqe_t *cqe = &cmd->nc_cqe;
1062
1063 /* take a shortcut if everything is alright */
1064 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1065 cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS)
1066 return (0);
1067
1068 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC)
1069 return (nvme_check_generic_cmd_status(cmd));
1070 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC)
1071 return (nvme_check_specific_cmd_status(cmd));
1072 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY)
1073 return (nvme_check_integrity_cmd_status(cmd));
1074 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR)
1075 return (nvme_check_vendor_cmd_status(cmd));
1076
1077 return (nvme_check_unknown_cmd_status(cmd));
1078 }
1079
1080 /*
1081 * nvme_abort_cmd_cb -- replaces nc_callback of aborted commands
1082 *
1083 * This functions takes care of cleaning up aborted commands. The command
1084 * status is checked to catch any fatal errors.
1085 */
1086 static void
1087 nvme_abort_cmd_cb(void *arg)
1088 {
1089 nvme_cmd_t *cmd = arg;
1090
1091 /*
1092 * Grab the command mutex. Once we have it we hold the last reference
1093 * to the command and can safely free it.
1094 */
1095 mutex_enter(&cmd->nc_mutex);
1096 (void) nvme_check_cmd_status(cmd);
1097 mutex_exit(&cmd->nc_mutex);
1098
1099 nvme_free_cmd(cmd);
1100 }
1101
1102 static void
1103 nvme_abort_cmd(nvme_cmd_t *abort_cmd)
1104 {
1105 nvme_t *nvme = abort_cmd->nc_nvme;
1106 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1107 nvme_abort_cmd_t ac = { 0 };
1108
1109 sema_p(&nvme->n_abort_sema);
1110
1111 ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid;
1112 ac.b.ac_sqid = abort_cmd->nc_sqid;
1113
1114 /*
1115 * Drop the mutex of the aborted command. From this point on
1116 * we must assume that the abort callback has freed the command.
1117 */
1118 mutex_exit(&abort_cmd->nc_mutex);
1119
1120 cmd->nc_sqid = 0;
1121 cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT;
1122 cmd->nc_callback = nvme_wakeup_cmd;
1123 cmd->nc_sqe.sqe_cdw10 = ac.r;
1124
1125 /*
1126 * Send the ABORT to the hardware. The ABORT command will return _after_
1127 * the aborted command has completed (aborted or otherwise).
1128 */
1129 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1130 sema_v(&nvme->n_abort_sema);
1131 dev_err(nvme->n_dip, CE_WARN,
1132 "!nvme_admin_cmd failed for ABORT");
1133 atomic_inc_32(&nvme->n_abort_failed);
1134 return;
1135 }
1136 sema_v(&nvme->n_abort_sema);
1137
1138 if (nvme_check_cmd_status(cmd)) {
1139 dev_err(nvme->n_dip, CE_WARN,
1140 "!ABORT failed with sct = %x, sc = %x",
1141 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1142 atomic_inc_32(&nvme->n_abort_failed);
1143 } else {
1144 atomic_inc_32(&nvme->n_cmd_aborted);
1145 }
1146
1147 nvme_free_cmd(cmd);
1148 }
1149
1150 /*
1151 * nvme_wait_cmd -- wait for command completion or timeout
1152 *
1153 * Returns B_TRUE if the command completed normally.
1154 *
1155 * Returns B_FALSE if the command timed out and an abort was attempted. The
1156 * command mutex will be dropped and the command must be considered freed. The
1157 * freeing of the command is normally done by the abort command callback.
1158 *
1159 * In case of a serious error or a timeout of the abort command the hardware
1160 * will be declared dead and FMA will be notified.
1161 */
1162 static boolean_t
1163 nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec)
1164 {
1165 clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC);
1166 nvme_t *nvme = cmd->nc_nvme;
1167 nvme_reg_csts_t csts;
1168
1169 ASSERT(mutex_owned(&cmd->nc_mutex));
1170
1171 while (!cmd->nc_completed) {
1172 if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1)
1173 break;
1174 }
1175
1176 if (cmd->nc_completed)
1177 return (B_TRUE);
1178
1179 /*
1180 * The command timed out. Change the callback to the cleanup function.
1181 */
1182 cmd->nc_callback = nvme_abort_cmd_cb;
1183
1184 /*
1185 * Check controller for fatal status, any errors associated with the
1186 * register or DMA handle, or for a double timeout (abort command timed
1187 * out). If necessary log a warning and call FMA.
1188 */
1189 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1190 dev_err(nvme->n_dip, CE_WARN, "!command timeout, "
1191 "OPC = %x, CFS = %d", cmd->nc_sqe.sqe_opc, csts.b.csts_cfs);
1192 atomic_inc_32(&nvme->n_cmd_timeout);
1193
1194 if (csts.b.csts_cfs ||
1195 nvme_check_regs_hdl(nvme) ||
1196 nvme_check_dma_hdl(cmd->nc_dma) ||
1197 cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) {
1198 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1199 nvme->n_dead = B_TRUE;
1200 mutex_exit(&cmd->nc_mutex);
1201 } else {
1202 /*
1203 * Try to abort the command. The command mutex is released by
1204 * nvme_abort_cmd().
1205 * If the abort succeeds it will have freed the aborted command.
1206 * If the abort fails for other reasons we must assume that the
1207 * command may complete at any time, and the callback will free
1208 * it for us.
1209 */
1210 nvme_abort_cmd(cmd);
1211 }
1212
1213 return (B_FALSE);
1214 }
1215
1216 static void
1217 nvme_wakeup_cmd(void *arg)
1218 {
1219 nvme_cmd_t *cmd = arg;
1220
1221 mutex_enter(&cmd->nc_mutex);
1222 /*
1223 * There is a slight chance that this command completed shortly after
1224 * the timeout was hit in nvme_wait_cmd() but before the callback was
1225 * changed. Catch that case here and clean up accordingly.
1226 */
1227 if (cmd->nc_callback == nvme_abort_cmd_cb) {
1228 mutex_exit(&cmd->nc_mutex);
1229 nvme_abort_cmd_cb(cmd);
1230 return;
1231 }
1232
1233 cmd->nc_completed = B_TRUE;
1234 cv_signal(&cmd->nc_cv);
1235 mutex_exit(&cmd->nc_mutex);
1236 }
1237
1238 static void
1239 nvme_async_event_task(void *arg)
1240 {
1241 nvme_cmd_t *cmd = arg;
1242 nvme_t *nvme = cmd->nc_nvme;
1243 nvme_error_log_entry_t *error_log = NULL;
1244 nvme_health_log_t *health_log = NULL;
1245 nvme_async_event_t event;
1246 int ret;
1247
1248 /*
1249 * Check for errors associated with the async request itself. The only
1250 * command-specific error is "async event limit exceeded", which
1251 * indicates a programming error in the driver and causes a panic in
1252 * nvme_check_cmd_status().
1253 *
1254 * Other possible errors are various scenarios where the async request
1255 * was aborted, or internal errors in the device. Internal errors are
1256 * reported to FMA, the command aborts need no special handling here.
1257 */
1258 if (nvme_check_cmd_status(cmd)) {
1259 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1260 "!async event request returned failure, sct = %x, "
1261 "sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct,
1262 cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr,
1263 cmd->nc_cqe.cqe_sf.sf_m);
1264
1265 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1266 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) {
1267 cmd->nc_nvme->n_dead = B_TRUE;
1268 ddi_fm_service_impact(cmd->nc_nvme->n_dip,
1269 DDI_SERVICE_LOST);
1270 }
1271 nvme_free_cmd(cmd);
1272 return;
1273 }
1274
1275
1276 event.r = cmd->nc_cqe.cqe_dw0;
1277
1278 /* Clear CQE and re-submit the async request. */
1279 bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t));
1280 ret = nvme_submit_cmd(nvme->n_adminq, cmd);
1281
1282 if (ret != DDI_SUCCESS) {
1283 dev_err(nvme->n_dip, CE_WARN,
1284 "!failed to resubmit async event request");
1285 atomic_inc_32(&nvme->n_async_resubmit_failed);
1286 nvme_free_cmd(cmd);
1287 }
1288
1289 switch (event.b.ae_type) {
1290 case NVME_ASYNC_TYPE_ERROR:
1291 if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) {
1292 error_log = (nvme_error_log_entry_t *)
1293 nvme_get_logpage(nvme, event.b.ae_logpage);
1294 } else {
1295 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1296 "async event reply: %d", event.b.ae_logpage);
1297 atomic_inc_32(&nvme->n_wrong_logpage);
1298 }
1299
1300 switch (event.b.ae_info) {
1301 case NVME_ASYNC_ERROR_INV_SQ:
1302 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1303 "invalid submission queue");
1304 return;
1305
1306 case NVME_ASYNC_ERROR_INV_DBL:
1307 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1308 "invalid doorbell write value");
1309 return;
1310
1311 case NVME_ASYNC_ERROR_DIAGFAIL:
1312 dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure");
1313 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1314 nvme->n_dead = B_TRUE;
1315 atomic_inc_32(&nvme->n_diagfail_event);
1316 break;
1317
1318 case NVME_ASYNC_ERROR_PERSISTENT:
1319 dev_err(nvme->n_dip, CE_WARN, "!persistent internal "
1320 "device error");
1321 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1322 nvme->n_dead = B_TRUE;
1323 atomic_inc_32(&nvme->n_persistent_event);
1324 break;
1325
1326 case NVME_ASYNC_ERROR_TRANSIENT:
1327 dev_err(nvme->n_dip, CE_WARN, "!transient internal "
1328 "device error");
1329 /* TODO: send ereport */
1330 atomic_inc_32(&nvme->n_transient_event);
1331 break;
1332
1333 case NVME_ASYNC_ERROR_FW_LOAD:
1334 dev_err(nvme->n_dip, CE_WARN,
1335 "!firmware image load error");
1336 atomic_inc_32(&nvme->n_fw_load_event);
1337 break;
1338 }
1339 break;
1340
1341 case NVME_ASYNC_TYPE_HEALTH:
1342 if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) {
1343 health_log = (nvme_health_log_t *)
1344 nvme_get_logpage(nvme, event.b.ae_logpage, -1);
1345 } else {
1346 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1347 "async event reply: %d", event.b.ae_logpage);
1348 atomic_inc_32(&nvme->n_wrong_logpage);
1349 }
1350
1351 switch (event.b.ae_info) {
1352 case NVME_ASYNC_HEALTH_RELIABILITY:
1353 dev_err(nvme->n_dip, CE_WARN,
1354 "!device reliability compromised");
1355 /* TODO: send ereport */
1356 atomic_inc_32(&nvme->n_reliability_event);
1357 break;
1358
1359 case NVME_ASYNC_HEALTH_TEMPERATURE:
1360 dev_err(nvme->n_dip, CE_WARN,
1361 "!temperature above threshold");
1362 /* TODO: send ereport */
1363 atomic_inc_32(&nvme->n_temperature_event);
1364 break;
1365
1366 case NVME_ASYNC_HEALTH_SPARE:
1367 dev_err(nvme->n_dip, CE_WARN,
1368 "!spare space below threshold");
1369 /* TODO: send ereport */
1370 atomic_inc_32(&nvme->n_spare_event);
1371 break;
1372 }
1373 break;
1374
1375 case NVME_ASYNC_TYPE_VENDOR:
1376 dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event "
1377 "received, info = %x, logpage = %x", event.b.ae_info,
1378 event.b.ae_logpage);
1379 atomic_inc_32(&nvme->n_vendor_event);
1380 break;
1381
1382 default:
1383 dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, "
1384 "type = %x, info = %x, logpage = %x", event.b.ae_type,
1385 event.b.ae_info, event.b.ae_logpage);
1386 atomic_inc_32(&nvme->n_unknown_event);
1387 break;
1388 }
1389
1390 if (error_log)
1391 kmem_free(error_log, sizeof (nvme_error_log_entry_t) *
1392 nvme->n_error_log_len);
1393
1394 if (health_log)
1395 kmem_free(health_log, sizeof (nvme_health_log_t));
1396 }
1397
1398 static int
1399 nvme_admin_cmd(nvme_cmd_t *cmd, int sec)
1400 {
1401 int ret;
1402
1403 mutex_enter(&cmd->nc_mutex);
1404 ret = nvme_submit_cmd(cmd->nc_nvme->n_adminq, cmd);
1405
1406 if (ret != DDI_SUCCESS) {
1407 mutex_exit(&cmd->nc_mutex);
1408 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1409 "!nvme_submit_cmd failed");
1410 atomic_inc_32(&cmd->nc_nvme->n_admin_queue_full);
1411 nvme_free_cmd(cmd);
1412 return (DDI_FAILURE);
1413 }
1414
1415 if (nvme_wait_cmd(cmd, sec) == B_FALSE) {
1416 /*
1417 * The command timed out. An abort command was posted that
1418 * will take care of the cleanup.
1419 */
1420 return (DDI_FAILURE);
1421 }
1422 mutex_exit(&cmd->nc_mutex);
1423
1424 return (DDI_SUCCESS);
1425 }
1426
1427 static int
1428 nvme_async_event(nvme_t *nvme)
1429 {
1430 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1431 int ret;
1432
1433 cmd->nc_sqid = 0;
1434 cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT;
1435 cmd->nc_callback = nvme_async_event_task;
1436
1437 ret = nvme_submit_cmd(nvme->n_adminq, cmd);
1438
1439 if (ret != DDI_SUCCESS) {
1440 dev_err(nvme->n_dip, CE_WARN,
1441 "!nvme_submit_cmd failed for ASYNCHRONOUS EVENT");
1442 nvme_free_cmd(cmd);
1443 return (DDI_FAILURE);
1444 }
1445
1446 return (DDI_SUCCESS);
1447 }
1448
1449 static void *
1450 nvme_get_logpage(nvme_t *nvme, uint8_t logpage, ...)
1451 {
1452 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1453 void *buf = NULL;
1454 nvme_getlogpage_t getlogpage = { 0 };
1455 size_t bufsize;
1456 va_list ap;
1457
1458 va_start(ap, logpage);
1459
1460 cmd->nc_sqid = 0;
1461 cmd->nc_callback = nvme_wakeup_cmd;
1462 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE;
1463
1464 getlogpage.b.lp_lid = logpage;
1465
1466 switch (logpage) {
1467 case NVME_LOGPAGE_ERROR:
1468 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1469 bufsize = nvme->n_error_log_len *
1470 sizeof (nvme_error_log_entry_t);
1471 break;
1472
1473 case NVME_LOGPAGE_HEALTH:
1474 cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t);
1475 bufsize = sizeof (nvme_health_log_t);
1476 break;
1477
1478 case NVME_LOGPAGE_FWSLOT:
1479 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1480 bufsize = sizeof (nvme_fwslot_log_t);
1481 break;
1482
1483 default:
1484 dev_err(nvme->n_dip, CE_WARN, "!unknown log page requested: %d",
1485 logpage);
1486 atomic_inc_32(&nvme->n_unknown_logpage);
1487 goto fail;
1488 }
1489
1490 va_end(ap);
1491
1492 getlogpage.b.lp_numd = bufsize / sizeof (uint32_t) - 1;
1493
1494 cmd->nc_sqe.sqe_cdw10 = getlogpage.r;
1495
1496 if (nvme_zalloc_dma(nvme, getlogpage.b.lp_numd * sizeof (uint32_t),
1497 DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1498 dev_err(nvme->n_dip, CE_WARN,
1499 "!nvme_zalloc_dma failed for GET LOG PAGE");
1500 goto fail;
1501 }
1502
1503 if (cmd->nc_dma->nd_ncookie > 2) {
1504 dev_err(nvme->n_dip, CE_WARN,
1505 "!too many DMA cookies for GET LOG PAGE");
1506 atomic_inc_32(&nvme->n_too_many_cookies);
1507 goto fail;
1508 }
1509
1510 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1511 if (cmd->nc_dma->nd_ncookie > 1) {
1512 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1513 &cmd->nc_dma->nd_cookie);
1514 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1515 cmd->nc_dma->nd_cookie.dmac_laddress;
1516 }
1517
1518 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1519 dev_err(nvme->n_dip, CE_WARN,
1520 "!nvme_admin_cmd failed for GET LOG PAGE");
1521 return (NULL);
1522 }
1523
1524 if (nvme_check_cmd_status(cmd)) {
1525 dev_err(nvme->n_dip, CE_WARN,
1526 "!GET LOG PAGE failed with sct = %x, sc = %x",
1527 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1528 goto fail;
1529 }
1530
1531 buf = kmem_alloc(bufsize, KM_SLEEP);
1532 bcopy(cmd->nc_dma->nd_memp, buf, bufsize);
1533
1534 fail:
1535 nvme_free_cmd(cmd);
1536
1537 return (buf);
1538 }
1539
1540 static void *
1541 nvme_identify(nvme_t *nvme, uint32_t nsid)
1542 {
1543 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1544 void *buf = NULL;
1545
1546 cmd->nc_sqid = 0;
1547 cmd->nc_callback = nvme_wakeup_cmd;
1548 cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY;
1549 cmd->nc_sqe.sqe_nsid = nsid;
1550 cmd->nc_sqe.sqe_cdw10 = nsid ? NVME_IDENTIFY_NSID : NVME_IDENTIFY_CTRL;
1551
1552 if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ,
1553 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1554 dev_err(nvme->n_dip, CE_WARN,
1555 "!nvme_zalloc_dma failed for IDENTIFY");
1556 goto fail;
1557 }
1558
1559 if (cmd->nc_dma->nd_ncookie > 2) {
1560 dev_err(nvme->n_dip, CE_WARN,
1561 "!too many DMA cookies for IDENTIFY");
1562 atomic_inc_32(&nvme->n_too_many_cookies);
1563 goto fail;
1564 }
1565
1566 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1567 if (cmd->nc_dma->nd_ncookie > 1) {
1568 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1569 &cmd->nc_dma->nd_cookie);
1570 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1571 cmd->nc_dma->nd_cookie.dmac_laddress;
1572 }
1573
1574 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1575 dev_err(nvme->n_dip, CE_WARN,
1576 "!nvme_admin_cmd failed for IDENTIFY");
1577 return (NULL);
1578 }
1579
1580 if (nvme_check_cmd_status(cmd)) {
1581 dev_err(nvme->n_dip, CE_WARN,
1582 "!IDENTIFY failed with sct = %x, sc = %x",
1583 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1584 goto fail;
1585 }
1586
1587 buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP);
1588 bcopy(cmd->nc_dma->nd_memp, buf, NVME_IDENTIFY_BUFSIZE);
1589
1590 fail:
1591 nvme_free_cmd(cmd);
1592
1593 return (buf);
1594 }
1595
1596 static int
1597 nvme_set_nqueues(nvme_t *nvme, uint16_t nqueues)
1598 {
1599 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1600 nvme_nqueue_t nq = { 0 };
1601
1602 nq.b.nq_nsq = nq.b.nq_ncq = nqueues - 1;
1603
1604 cmd->nc_sqid = 0;
1605 cmd->nc_callback = nvme_wakeup_cmd;
1606 cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES;
1607 cmd->nc_sqe.sqe_cdw10 = NVME_FEAT_NQUEUES;
1608 cmd->nc_sqe.sqe_cdw11 = nq.r;
1609
1610 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1611 dev_err(nvme->n_dip, CE_WARN,
1612 "!nvme_admin_cmd failed for SET FEATURES (NQUEUES)");
1613 return (0);
1614 }
1615
1616 if (nvme_check_cmd_status(cmd)) {
1617 dev_err(nvme->n_dip, CE_WARN,
1618 "!SET FEATURES (NQUEUES) failed with sct = %x, sc = %x",
1619 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1620 nvme_free_cmd(cmd);
1621 return (0);
1622 }
1623
1624 nq.r = cmd->nc_cqe.cqe_dw0;
1625 nvme_free_cmd(cmd);
1626
1627 /*
1628 * Always use the same number of submission and completion queues, and
1629 * never use more than the requested number of queues.
1630 */
1631 return (MIN(nqueues, MIN(nq.b.nq_nsq, nq.b.nq_ncq) + 1));
1632 }
1633
1634 static int
1635 nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx)
1636 {
1637 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1638 nvme_create_queue_dw10_t dw10 = { 0 };
1639 nvme_create_cq_dw11_t c_dw11 = { 0 };
1640 nvme_create_sq_dw11_t s_dw11 = { 0 };
1641
1642 dw10.b.q_qid = idx;
1643 dw10.b.q_qsize = qp->nq_nentry - 1;
1644
1645 c_dw11.b.cq_pc = 1;
1646 c_dw11.b.cq_ien = 1;
1647 c_dw11.b.cq_iv = idx % nvme->n_intr_cnt;
1648
1649 cmd->nc_sqid = 0;
1650 cmd->nc_callback = nvme_wakeup_cmd;
1651 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE;
1652 cmd->nc_sqe.sqe_cdw10 = dw10.r;
1653 cmd->nc_sqe.sqe_cdw11 = c_dw11.r;
1654 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_cqdma->nd_cookie.dmac_laddress;
1655
1656 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1657 dev_err(nvme->n_dip, CE_WARN,
1658 "!nvme_admin_cmd failed for CREATE CQUEUE");
1659 return (DDI_FAILURE);
1660 }
1661
1662 if (nvme_check_cmd_status(cmd)) {
1663 dev_err(nvme->n_dip, CE_WARN,
1664 "!CREATE CQUEUE failed with sct = %x, sc = %x",
1665 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1666 nvme_free_cmd(cmd);
1667 return (DDI_FAILURE);
1668 }
1669
1670 nvme_free_cmd(cmd);
1671
1672 s_dw11.b.sq_pc = 1;
1673 s_dw11.b.sq_cqid = idx;
1674
1675 cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1676 cmd->nc_sqid = 0;
1677 cmd->nc_callback = nvme_wakeup_cmd;
1678 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE;
1679 cmd->nc_sqe.sqe_cdw10 = dw10.r;
1680 cmd->nc_sqe.sqe_cdw11 = s_dw11.r;
1681 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress;
1682
1683 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1684 dev_err(nvme->n_dip, CE_WARN,
1685 "!nvme_admin_cmd failed for CREATE SQUEUE");
1686 return (DDI_FAILURE);
1687 }
1688
1689 if (nvme_check_cmd_status(cmd)) {
1690 dev_err(nvme->n_dip, CE_WARN,
1691 "!CREATE SQUEUE failed with sct = %x, sc = %x",
1692 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1693 nvme_free_cmd(cmd);
1694 return (DDI_FAILURE);
1695 }
1696
1697 nvme_free_cmd(cmd);
1698
1699 mutex_enter(&nvme_global_mutex);
1700 list_insert_head(&nvme_qp_list, qp);
1701 qp->nq_nvme = nvme;
1702 mutex_exit(&nvme_global_mutex);
1703
1704 return (DDI_SUCCESS);
1705 }
1706
1707 static boolean_t
1708 nvme_reset(nvme_t *nvme, boolean_t quiesce)
1709 {
1710 nvme_reg_csts_t csts;
1711 int i;
1712
1713 nvme_put32(nvme, NVME_REG_CC, 0);
1714
1715 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1716 if (csts.b.csts_rdy == 1) {
1717 nvme_put32(nvme, NVME_REG_CC, 0);
1718 for (i = 0; i != nvme->n_timeout * 10; i++) {
1719 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1720 if (csts.b.csts_rdy == 0)
1721 break;
1722
1723 if (quiesce)
1724 drv_usecwait(50000);
1725 else
1726 delay(drv_usectohz(50000));
1727 }
1728 }
1729
1730 nvme_put32(nvme, NVME_REG_AQA, 0);
1731 nvme_put32(nvme, NVME_REG_ASQ, 0);
1732 nvme_put32(nvme, NVME_REG_ACQ, 0);
1733
1734 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1735 return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE);
1736 }
1737
1738 static void
1739 nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce)
1740 {
1741 nvme_reg_cc_t cc;
1742 nvme_reg_csts_t csts;
1743 int i;
1744
1745 ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT);
1746
1747 cc.r = nvme_get32(nvme, NVME_REG_CC);
1748 cc.b.cc_shn = mode & 0x3;
1749 nvme_put32(nvme, NVME_REG_CC, cc.r);
1750
1751 for (i = 0; i != 10; i++) {
1752 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1753 if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE)
1754 break;
1755
1756 if (quiesce)
1757 drv_usecwait(100000);
1758 else
1759 delay(drv_usectohz(100000));
1760 }
1761 }
1762
1763
1764 static void
1765 nvme_prepare_devid(nvme_t *nvme, uint32_t nsid)
1766 {
1767 char model[sizeof (nvme->n_idctl->id_model) + 1];
1768 char serial[sizeof (nvme->n_idctl->id_serial) + 1];
1769
1770 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
1771 bcopy(nvme->n_idctl->id_serial, serial,
1772 sizeof (nvme->n_idctl->id_serial));
1773
1774 model[sizeof (nvme->n_idctl->id_model)] = '\0';
1775 serial[sizeof (nvme->n_idctl->id_serial)] = '\0';
1776
1777 (void) snprintf(nvme->n_ns[nsid - 1].ns_devid,
1778 sizeof (nvme->n_ns[0].ns_devid), "%4X-%s-%s-%X",
1779 nvme->n_idctl->id_vid, model, serial, nsid);
1780 }
1781
1782 static int
1783 nvme_init(nvme_t *nvme)
1784 {
1785 nvme_reg_cc_t cc = { 0 };
1786 nvme_reg_aqa_t aqa = { 0 };
1787 nvme_reg_asq_t asq = { 0 };
1788 nvme_reg_acq_t acq = { 0 };
1789 nvme_reg_cap_t cap;
1790 nvme_reg_vs_t vs;
1791 nvme_reg_csts_t csts;
1792 int i = 0;
1793 int nqueues;
1794 char model[sizeof (nvme->n_idctl->id_model) + 1];
1795 char *vendor, *product;
1796
1797 /* Check controller version */
1798 vs.r = nvme_get32(nvme, NVME_REG_VS);
1799 dev_err(nvme->n_dip, CE_CONT, "?NVMe spec version %d.%d",
1800 vs.b.vs_mjr, vs.b.vs_mnr);
1801
1802 if (nvme_version_major < vs.b.vs_mjr ||
1803 (nvme_version_major == vs.b.vs_mjr &&
1804 nvme_version_minor < vs.b.vs_mnr)) {
1805 dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.%d",
1806 nvme_version_major, nvme_version_minor);
1807 if (nvme->n_strict_version)
1808 goto fail;
1809 }
1810
1811 /* retrieve controller configuration */
1812 cap.r = nvme_get64(nvme, NVME_REG_CAP);
1813
1814 if ((cap.b.cap_css & NVME_CAP_CSS_NVM) == 0) {
1815 dev_err(nvme->n_dip, CE_WARN,
1816 "!NVM command set not supported by hardware");
1817 goto fail;
1818 }
1819
1820 nvme->n_nssr_supported = cap.b.cap_nssrs;
1821 nvme->n_doorbell_stride = 4 << cap.b.cap_dstrd;
1822 nvme->n_timeout = cap.b.cap_to;
1823 nvme->n_arbitration_mechanisms = cap.b.cap_ams;
1824 nvme->n_cont_queues_reqd = cap.b.cap_cqr;
1825 nvme->n_max_queue_entries = cap.b.cap_mqes + 1;
1826
1827 /*
1828 * The MPSMIN and MPSMAX fields in the CAP register use 0 to specify
1829 * the base page size of 4k (1<<12), so add 12 here to get the real
1830 * page size value.
1831 */
1832 nvme->n_pageshift = MIN(MAX(cap.b.cap_mpsmin + 12, PAGESHIFT),
1833 cap.b.cap_mpsmax + 12);
1834 nvme->n_pagesize = 1UL << (nvme->n_pageshift);
1835
1836 /*
1837 * Set up Queue DMA to transfer at least 1 page-aligned page at a time.
1838 */
1839 nvme->n_queue_dma_attr.dma_attr_align = nvme->n_pagesize;
1840 nvme->n_queue_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
1841
1842 /*
1843 * Set up PRP DMA to transfer 1 page-aligned page at a time.
1844 * Maxxfer may be increased after we identified the controller limits.
1845 */
1846 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_pagesize;
1847 nvme->n_prp_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
1848 nvme->n_prp_dma_attr.dma_attr_align = nvme->n_pagesize;
1849 nvme->n_prp_dma_attr.dma_attr_seg = nvme->n_pagesize - 1;
1850
1851 /*
1852 * Reset controller if it's still in ready state.
1853 */
1854 if (nvme_reset(nvme, B_FALSE) == B_FALSE) {
1855 dev_err(nvme->n_dip, CE_WARN, "!unable to reset controller");
1856 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1857 nvme->n_dead = B_TRUE;
1858 goto fail;
1859 }
1860
1861 /*
1862 * Create the admin queue pair.
1863 */
1864 if (nvme_alloc_qpair(nvme, nvme->n_admin_queue_len, &nvme->n_adminq, 0)
1865 != DDI_SUCCESS) {
1866 dev_err(nvme->n_dip, CE_WARN,
1867 "!unable to allocate admin qpair");
1868 goto fail;
1869 }
1870 nvme->n_ioq = kmem_alloc(sizeof (nvme_qpair_t *), KM_SLEEP);
1871 nvme->n_ioq[0] = nvme->n_adminq;
1872
1873 nvme->n_progress |= NVME_ADMIN_QUEUE;
1874
1875 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
1876 "admin-queue-len", nvme->n_admin_queue_len);
1877
1878 aqa.b.aqa_asqs = aqa.b.aqa_acqs = nvme->n_admin_queue_len - 1;
1879 asq = nvme->n_adminq->nq_sqdma->nd_cookie.dmac_laddress;
1880 acq = nvme->n_adminq->nq_cqdma->nd_cookie.dmac_laddress;
1881
1882 ASSERT((asq & (nvme->n_pagesize - 1)) == 0);
1883 ASSERT((acq & (nvme->n_pagesize - 1)) == 0);
1884
1885 nvme_put32(nvme, NVME_REG_AQA, aqa.r);
1886 nvme_put64(nvme, NVME_REG_ASQ, asq);
1887 nvme_put64(nvme, NVME_REG_ACQ, acq);
1888
1889 cc.b.cc_ams = 0; /* use Round-Robin arbitration */
1890 cc.b.cc_css = 0; /* use NVM command set */
1891 cc.b.cc_mps = nvme->n_pageshift - 12;
1892 cc.b.cc_shn = 0; /* no shutdown in progress */
1893 cc.b.cc_en = 1; /* enable controller */
1894 cc.b.cc_iosqes = 6; /* submission queue entry is 2^6 bytes long */
1895 cc.b.cc_iocqes = 4; /* completion queue entry is 2^4 bytes long */
1896
1897 nvme_put32(nvme, NVME_REG_CC, cc.r);
1898
1899 /*
1900 * Wait for the controller to become ready.
1901 */
1902 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1903 if (csts.b.csts_rdy == 0) {
1904 for (i = 0; i != nvme->n_timeout * 10; i++) {
1905 delay(drv_usectohz(50000));
1906 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1907
1908 if (csts.b.csts_cfs == 1) {
1909 dev_err(nvme->n_dip, CE_WARN,
1910 "!controller fatal status at init");
1911 ddi_fm_service_impact(nvme->n_dip,
1912 DDI_SERVICE_LOST);
1913 nvme->n_dead = B_TRUE;
1914 goto fail;
1915 }
1916
1917 if (csts.b.csts_rdy == 1)
1918 break;
1919 }
1920 }
1921
1922 if (csts.b.csts_rdy == 0) {
1923 dev_err(nvme->n_dip, CE_WARN, "!controller not ready");
1924 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1925 nvme->n_dead = B_TRUE;
1926 goto fail;
1927 }
1928
1929 /*
1930 * Assume an abort command limit of 1. We'll destroy and re-init
1931 * that later when we know the true abort command limit.
1932 */
1933 sema_init(&nvme->n_abort_sema, 1, NULL, SEMA_DRIVER, NULL);
1934
1935 /*
1936 * Setup initial interrupt for admin queue.
1937 */
1938 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 1)
1939 != DDI_SUCCESS) &&
1940 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 1)
1941 != DDI_SUCCESS) &&
1942 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_FIXED, 1)
1943 != DDI_SUCCESS)) {
1944 dev_err(nvme->n_dip, CE_WARN,
1945 "!failed to setup initial interrupt");
1946 goto fail;
1947 }
1948
1949 /*
1950 * Post an asynchronous event command to catch errors.
1951 */
1952 if (nvme_async_event(nvme) != DDI_SUCCESS) {
1953 dev_err(nvme->n_dip, CE_WARN,
1954 "!failed to post async event");
1955 goto fail;
1956 }
1957
1958 /*
1959 * Identify Controller
1960 */
1961 nvme->n_idctl = nvme_identify(nvme, 0);
1962 if (nvme->n_idctl == NULL) {
1963 dev_err(nvme->n_dip, CE_WARN,
1964 "!failed to identify controller");
1965 goto fail;
1966 }
1967
1968 /*
1969 * Get Vendor & Product ID
1970 */
1971 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
1972 model[sizeof (nvme->n_idctl->id_model)] = '\0';
1973 sata_split_model(model, &vendor, &product);
1974
1975 if (vendor == NULL)
1976 nvme->n_vendor = strdup("NVMe");
1977 else
1978 nvme->n_vendor = strdup(vendor);
1979
1980 nvme->n_product = strdup(product);
1981
1982 /*
1983 * Get controller limits.
1984 */
1985 nvme->n_async_event_limit = MAX(NVME_MIN_ASYNC_EVENT_LIMIT,
1986 MIN(nvme->n_admin_queue_len / 10,
1987 MIN(nvme->n_idctl->id_aerl + 1, nvme->n_async_event_limit)));
1988
1989 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
1990 "async-event-limit", nvme->n_async_event_limit);
1991
1992 nvme->n_abort_command_limit = nvme->n_idctl->id_acl + 1;
1993
1994 /*
1995 * Reinitialize the semaphore with the true abort command limit
1996 * supported by the hardware. It's not necessary to disable interrupts
1997 * as only command aborts use the semaphore, and no commands are
1998 * executed or aborted while we're here.
1999 */
2000 sema_destroy(&nvme->n_abort_sema);
2001 sema_init(&nvme->n_abort_sema, nvme->n_abort_command_limit - 1, NULL,
2002 SEMA_DRIVER, NULL);
2003
2004 nvme->n_progress |= NVME_CTRL_LIMITS;
2005
2006 if (nvme->n_idctl->id_mdts == 0)
2007 nvme->n_max_data_transfer_size = nvme->n_pagesize * 65536;
2008 else
2009 nvme->n_max_data_transfer_size =
2010 1ull << (nvme->n_pageshift + nvme->n_idctl->id_mdts);
2011
2012 nvme->n_error_log_len = nvme->n_idctl->id_elpe + 1;
2013
2014 /*
2015 * Limit n_max_data_transfer_size to what we can handle in one PRP.
2016 * Chained PRPs are currently unsupported.
2017 *
2018 * This is a no-op on hardware which doesn't support a transfer size
2019 * big enough to require chained PRPs.
2020 */
2021 nvme->n_max_data_transfer_size = MIN(nvme->n_max_data_transfer_size,
2022 (nvme->n_pagesize / sizeof (uint64_t) * nvme->n_pagesize));
2023
2024 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_max_data_transfer_size;
2025
2026 /*
2027 * Make sure the minimum/maximum queue entry sizes are not
2028 * larger/smaller than the default.
2029 */
2030
2031 if (((1 << nvme->n_idctl->id_sqes.qes_min) > sizeof (nvme_sqe_t)) ||
2032 ((1 << nvme->n_idctl->id_sqes.qes_max) < sizeof (nvme_sqe_t)) ||
2033 ((1 << nvme->n_idctl->id_cqes.qes_min) > sizeof (nvme_cqe_t)) ||
2034 ((1 << nvme->n_idctl->id_cqes.qes_max) < sizeof (nvme_cqe_t)))
2035 goto fail;
2036
2037 /*
2038 * Check for the presence of a Volatile Write Cache. If present,
2039 * enable it by default.
2040 */
2041 if (nvme->n_idctl->id_vwc.vwc_present == 0) {
2042 nvme->n_volatile_write_cache_enabled = B_FALSE;
2043 nvme_bd_ops.o_sync_cache = NULL;
2044 } else {
2045 /*
2046 * TODO: send SET FEATURES to enable VWC
2047 * (have no hardware to test this)
2048 */
2049 nvme->n_volatile_write_cache_enabled = B_FALSE;
2050 nvme_bd_ops.o_sync_cache = NULL;
2051 }
2052
2053 /*
2054 * Grab a copy of all mandatory log pages.
2055 *
2056 * TODO: should go away once user space tool exists to print logs
2057 */
2058 nvme->n_error_log = (nvme_error_log_entry_t *)
2059 nvme_get_logpage(nvme, NVME_LOGPAGE_ERROR);
2060 nvme->n_health_log = (nvme_health_log_t *)
2061 nvme_get_logpage(nvme, NVME_LOGPAGE_HEALTH, -1);
2062 nvme->n_fwslot_log = (nvme_fwslot_log_t *)
2063 nvme_get_logpage(nvme, NVME_LOGPAGE_FWSLOT);
2064
2065 /*
2066 * Identify Namespaces
2067 */
2068 nvme->n_namespace_count = nvme->n_idctl->id_nn;
2069 nvme->n_ns = kmem_zalloc(sizeof (nvme_namespace_t) *
2070 nvme->n_namespace_count, KM_SLEEP);
2071
2072 for (i = 0; i != nvme->n_namespace_count; i++) {
2073 nvme_identify_nsid_t *idns;
2074 int last_rp;
2075
2076 nvme->n_ns[i].ns_nvme = nvme;
2077 nvme->n_ns[i].ns_idns = idns = nvme_identify(nvme, i + 1);
2078
2079 if (idns == NULL) {
2080 dev_err(nvme->n_dip, CE_WARN,
2081 "!failed to identify namespace %d", i + 1);
2082 goto fail;
2083 }
2084
2085 nvme->n_ns[i].ns_id = i + 1;
2086 nvme->n_ns[i].ns_block_count = idns->id_nsize;
2087 nvme->n_ns[i].ns_block_size =
2088 1 << idns->id_lbaf[idns->id_flbas.lba_format].lbaf_lbads;
2089 nvme->n_ns[i].ns_best_block_size = nvme->n_ns[i].ns_block_size;
2090
2091 nvme_prepare_devid(nvme, nvme->n_ns[i].ns_id);
2092
2093 /*
2094 * Find the LBA format with no metadata and the best relative
2095 * performance. A value of 3 means "degraded", 0 is best.
2096 */
2097 last_rp = 3;
2098 for (int j = 0; j <= idns->id_nlbaf; j++) {
2099 if (idns->id_lbaf[j].lbaf_lbads == 0)
2100 break;
2101 if (idns->id_lbaf[j].lbaf_ms != 0)
2102 continue;
2103 if (idns->id_lbaf[j].lbaf_rp >= last_rp)
2104 continue;
2105 last_rp = idns->id_lbaf[j].lbaf_rp;
2106 nvme->n_ns[i].ns_best_block_size =
2107 1 << idns->id_lbaf[j].lbaf_lbads;
2108 }
2109
2110 /*
2111 * We currently don't support namespaces that use either:
2112 * - thin provisioning
2113 * - protection information
2114 */
2115 if (idns->id_nsfeat.f_thin ||
2116 idns->id_dps.dp_pinfo) {
2117 dev_err(nvme->n_dip, CE_WARN,
2118 "!ignoring namespace %d, unsupported features: "
2119 "thin = %d, pinfo = %d", i + 1,
2120 idns->id_nsfeat.f_thin, idns->id_dps.dp_pinfo);
2121 nvme->n_ns[i].ns_ignore = B_TRUE;
2122 }
2123 }
2124
2125 /*
2126 * Try to set up MSI/MSI-X interrupts.
2127 */
2128 if ((nvme->n_intr_types & (DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX))
2129 != 0) {
2130 nvme_release_interrupts(nvme);
2131
2132 nqueues = MIN(UINT16_MAX, ncpus);
2133
2134 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX,
2135 nqueues) != DDI_SUCCESS) &&
2136 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI,
2137 nqueues) != DDI_SUCCESS)) {
2138 dev_err(nvme->n_dip, CE_WARN,
2139 "!failed to setup MSI/MSI-X interrupts");
2140 goto fail;
2141 }
2142 }
2143
2144 nqueues = nvme->n_intr_cnt;
2145
2146 /*
2147 * Create I/O queue pairs.
2148 */
2149 nvme->n_ioq_count = nvme_set_nqueues(nvme, nqueues);
2150 if (nvme->n_ioq_count == 0) {
2151 dev_err(nvme->n_dip, CE_WARN,
2152 "!failed to set number of I/O queues to %d", nqueues);
2153 goto fail;
2154 }
2155
2156 /*
2157 * Reallocate I/O queue array
2158 */
2159 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *));
2160 nvme->n_ioq = kmem_zalloc(sizeof (nvme_qpair_t *) *
2161 (nvme->n_ioq_count + 1), KM_SLEEP);
2162 nvme->n_ioq[0] = nvme->n_adminq;
2163
2164 /*
2165 * If we got less queues than we asked for we might as well give
2166 * some of the interrupt vectors back to the system.
2167 */
2168 if (nvme->n_ioq_count < nqueues) {
2169 nvme_release_interrupts(nvme);
2170
2171 if (nvme_setup_interrupts(nvme, nvme->n_intr_type,
2172 nvme->n_ioq_count) != DDI_SUCCESS) {
2173 dev_err(nvme->n_dip, CE_WARN,
2174 "!failed to reduce number of interrupts");
2175 goto fail;
2176 }
2177 }
2178
2179 /*
2180 * Alloc & register I/O queue pairs
2181 */
2182 nvme->n_io_queue_len =
2183 MIN(nvme->n_io_queue_len, nvme->n_max_queue_entries);
2184 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, "io-queue-len",
2185 nvme->n_io_queue_len);
2186
2187 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
2188 if (nvme_alloc_qpair(nvme, nvme->n_io_queue_len,
2189 &nvme->n_ioq[i], i) != DDI_SUCCESS) {
2190 dev_err(nvme->n_dip, CE_WARN,
2191 "!unable to allocate I/O qpair %d", i);
2192 goto fail;
2193 }
2194
2195 if (nvme_create_io_qpair(nvme, nvme->n_ioq[i], i)
2196 != DDI_SUCCESS) {
2197 dev_err(nvme->n_dip, CE_WARN,
2198 "!unable to create I/O qpair %d", i);
2199 goto fail;
2200 }
2201 }
2202
2203 /*
2204 * Post more asynchronous events commands to reduce event reporting
2205 * latency as suggested by the spec.
2206 */
2207 for (i = 1; i != nvme->n_async_event_limit; i++) {
2208 if (nvme_async_event(nvme) != DDI_SUCCESS) {
2209 dev_err(nvme->n_dip, CE_WARN,
2210 "!failed to post async event %d", i);
2211 goto fail;
2212 }
2213 }
2214
2215 return (DDI_SUCCESS);
2216
2217 fail:
2218 (void) nvme_reset(nvme, B_FALSE);
2219 return (DDI_FAILURE);
2220 }
2221
2222 static uint_t
2223 nvme_intr(caddr_t arg1, caddr_t arg2)
2224 {
2225 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2226 nvme_t *nvme = (nvme_t *)arg1;
2227 int inum = (int)(uintptr_t)arg2;
2228 int ccnt = 0;
2229 int qnum;
2230 nvme_cmd_t *cmd;
2231 int cnt_cmds;
2232
2233 if (inum >= nvme->n_intr_cnt)
2234 return (DDI_INTR_UNCLAIMED);
2235
2236 /*
2237 * The interrupt vector a queue uses is calculated as queue_idx %
2238 * intr_cnt in nvme_create_io_qpair(). Iterate through the queue array
2239 * in steps of n_intr_cnt to process all queues using this vector.
2240 */
2241 for (qnum = inum;
2242 qnum < nvme->n_ioq_count + 1 && nvme->n_ioq[qnum] != NULL;
2243 qnum += nvme->n_intr_cnt) {
2244 cnt_cmds = nvme_process_cq_cmds(nvme, nvme->n_ioq[qnum]);
2245 ccnt += cnt_cmds;
2246 }
2247
2248 return (ccnt > 0 ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED);
2249 }
2250
2251 static void
2252 nvme_release_interrupts(nvme_t *nvme)
2253 {
2254 int i;
2255
2256 for (i = 0; i < nvme->n_intr_cnt; i++) {
2257 if (nvme->n_inth[i] == NULL)
2258 break;
2259
2260 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2261 (void) ddi_intr_block_disable(&nvme->n_inth[i], 1);
2262 else
2263 (void) ddi_intr_disable(nvme->n_inth[i]);
2264
2265 (void) ddi_intr_remove_handler(nvme->n_inth[i]);
2266 (void) ddi_intr_free(nvme->n_inth[i]);
2267 }
2268
2269 kmem_free(nvme->n_inth, nvme->n_inth_sz);
2270 nvme->n_inth = NULL;
2271 nvme->n_inth_sz = 0;
2272
2273 nvme->n_progress &= ~NVME_INTERRUPTS;
2274 }
2275
2276 static int
2277 nvme_setup_interrupts(nvme_t *nvme, int intr_type, int nqpairs)
2278 {
2279 int nintrs, navail, count;
2280 int ret;
2281 int i;
2282
2283 if (nvme->n_intr_types == 0) {
2284 ret = ddi_intr_get_supported_types(nvme->n_dip,
2285 &nvme->n_intr_types);
2286 if (ret != DDI_SUCCESS) {
2287 dev_err(nvme->n_dip, CE_WARN,
2288 "!%s: ddi_intr_get_supported types failed",
2289 __func__);
2290 return (ret);
2291 }
2292 }
2293
2294 if ((nvme->n_intr_types & intr_type) == 0)
2295 return (DDI_FAILURE);
2296
2297 ret = ddi_intr_get_nintrs(nvme->n_dip, intr_type, &nintrs);
2298 if (ret != DDI_SUCCESS) {
2299 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_nintrs failed",
2300 __func__);
2301 return (ret);
2302 }
2303
2304 ret = ddi_intr_get_navail(nvme->n_dip, intr_type, &navail);
2305 if (ret != DDI_SUCCESS) {
2306 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_navail failed",
2307 __func__);
2308 return (ret);
2309 }
2310
2311 /* We want at most one interrupt per queue pair. */
2312 if (navail > nqpairs)
2313 navail = nqpairs;
2314
2315 nvme->n_inth_sz = sizeof (ddi_intr_handle_t) * navail;
2316 nvme->n_inth = kmem_zalloc(nvme->n_inth_sz, KM_SLEEP);
2317
2318 ret = ddi_intr_alloc(nvme->n_dip, nvme->n_inth, intr_type, 0, navail,
2319 &count, 0);
2320 if (ret != DDI_SUCCESS) {
2321 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_alloc failed",
2322 __func__);
2323 goto fail;
2324 }
2325
2326 nvme->n_intr_cnt = count;
2327
2328 ret = ddi_intr_get_pri(nvme->n_inth[0], &nvme->n_intr_pri);
2329 if (ret != DDI_SUCCESS) {
2330 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_pri failed",
2331 __func__);
2332 goto fail;
2333 }
2334
2335 for (i = 0; i < count; i++) {
2336 ret = ddi_intr_add_handler(nvme->n_inth[i], nvme_intr,
2337 (void *)nvme, (void *)(uintptr_t)i);
2338 if (ret != DDI_SUCCESS) {
2339 dev_err(nvme->n_dip, CE_WARN,
2340 "!%s: ddi_intr_add_handler failed", __func__);
2341 goto fail;
2342 }
2343 }
2344
2345 (void) ddi_intr_get_cap(nvme->n_inth[0], &nvme->n_intr_cap);
2346
2347 for (i = 0; i < count; i++) {
2348 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2349 ret = ddi_intr_block_enable(&nvme->n_inth[i], 1);
2350 else
2351 ret = ddi_intr_enable(nvme->n_inth[i]);
2352
2353 if (ret != DDI_SUCCESS) {
2354 dev_err(nvme->n_dip, CE_WARN,
2355 "!%s: enabling interrupt %d failed", __func__, i);
2356 goto fail;
2357 }
2358 }
2359
2360 nvme->n_intr_type = intr_type;
2361
2362 nvme->n_progress |= NVME_INTERRUPTS;
2363
2364 return (DDI_SUCCESS);
2365
2366 fail:
2367 nvme_release_interrupts(nvme);
2368
2369 return (ret);
2370 }
2371
2372 static int
2373 nvme_fm_errcb(dev_info_t *dip, ddi_fm_error_t *fm_error, const void *arg)
2374 {
2375 _NOTE(ARGUNUSED(arg));
2376
2377 pci_ereport_post(dip, fm_error, NULL);
2378 return (fm_error->fme_status);
2379 }
2380
2381 static int
2382 nvme_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2383 {
2384 nvme_t *nvme;
2385 int instance;
2386 int nregs;
2387 off_t regsize;
2388 int i;
2389 char name[32];
2390
2391 if (cmd != DDI_ATTACH)
2392 return (DDI_FAILURE);
2393
2394 instance = ddi_get_instance(dip);
2395
2396 if (ddi_soft_state_zalloc(nvme_state, instance) != DDI_SUCCESS)
2397 return (DDI_FAILURE);
2398
2399 nvme = ddi_get_soft_state(nvme_state, instance);
2400 ddi_set_driver_private(dip, nvme);
2401 nvme->n_dip = dip;
2402
2403 nvme->n_strict_version = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2404 DDI_PROP_DONTPASS, "strict-version", 1) == 1 ? B_TRUE : B_FALSE;
2405 nvme->n_ignore_unknown_vendor_status = ddi_prop_get_int(DDI_DEV_T_ANY,
2406 dip, DDI_PROP_DONTPASS, "ignore-unknown-vendor-status", 0) == 1 ?
2407 B_TRUE : B_FALSE;
2408 nvme->n_admin_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2409 DDI_PROP_DONTPASS, "admin-queue-len", NVME_DEFAULT_ADMIN_QUEUE_LEN);
2410 nvme->n_io_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2411 DDI_PROP_DONTPASS, "io-queue-len", NVME_DEFAULT_IO_QUEUE_LEN);
2412 nvme->n_async_event_limit = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2413 DDI_PROP_DONTPASS, "async-event-limit",
2414 NVME_DEFAULT_ASYNC_EVENT_LIMIT);
2415
2416 if (nvme->n_admin_queue_len < NVME_MIN_ADMIN_QUEUE_LEN)
2417 nvme->n_admin_queue_len = NVME_MIN_ADMIN_QUEUE_LEN;
2418 else if (nvme->n_admin_queue_len > NVME_MAX_ADMIN_QUEUE_LEN)
2419 nvme->n_admin_queue_len = NVME_MAX_ADMIN_QUEUE_LEN;
2420
2421 if (nvme->n_io_queue_len < NVME_MIN_IO_QUEUE_LEN)
2422 nvme->n_io_queue_len = NVME_MIN_IO_QUEUE_LEN;
2423
2424 if (nvme->n_async_event_limit < 1)
2425 nvme->n_async_event_limit = NVME_DEFAULT_ASYNC_EVENT_LIMIT;
2426
2427 nvme->n_reg_acc_attr = nvme_reg_acc_attr;
2428 nvme->n_queue_dma_attr = nvme_queue_dma_attr;
2429 nvme->n_prp_dma_attr = nvme_prp_dma_attr;
2430 nvme->n_sgl_dma_attr = nvme_sgl_dma_attr;
2431
2432 /*
2433 * Setup FMA support.
2434 */
2435 nvme->n_fm_cap = ddi_getprop(DDI_DEV_T_ANY, dip,
2436 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
2437 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
2438 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
2439
2440 ddi_fm_init(dip, &nvme->n_fm_cap, &nvme->n_fm_ibc);
2441
2442 if (nvme->n_fm_cap) {
2443 if (nvme->n_fm_cap & DDI_FM_ACCCHK_CAPABLE)
2444 nvme->n_reg_acc_attr.devacc_attr_access =
2445 DDI_FLAGERR_ACC;
2446
2447 if (nvme->n_fm_cap & DDI_FM_DMACHK_CAPABLE) {
2448 nvme->n_prp_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2449 nvme->n_sgl_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2450 }
2451
2452 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2453 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2454 pci_ereport_setup(dip);
2455
2456 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2457 ddi_fm_handler_register(dip, nvme_fm_errcb,
2458 (void *)nvme);
2459 }
2460
2461 nvme->n_progress |= NVME_FMA_INIT;
2462
2463 /*
2464 * The spec defines several register sets. Only the controller
2465 * registers (set 1) are currently used.
2466 */
2467 if (ddi_dev_nregs(dip, &nregs) == DDI_FAILURE ||
2468 nregs < 2 ||
2469 ddi_dev_regsize(dip, 1, ®size) == DDI_FAILURE)
2470 goto fail;
2471
2472 if (ddi_regs_map_setup(dip, 1, &nvme->n_regs, 0, regsize,
2473 &nvme->n_reg_acc_attr, &nvme->n_regh) != DDI_SUCCESS) {
2474 dev_err(dip, CE_WARN, "!failed to map regset 1");
2475 goto fail;
2476 }
2477
2478 nvme->n_progress |= NVME_REGS_MAPPED;
2479
2480 /*
2481 * Create taskq for command completion.
2482 */
2483 (void) snprintf(name, sizeof (name), "%s%d_cmd_taskq",
2484 ddi_driver_name(dip), ddi_get_instance(dip));
2485 nvme->n_cmd_taskq = ddi_taskq_create(dip, name, MIN(UINT16_MAX, ncpus),
2486 TASKQ_DEFAULTPRI, 0);
2487 if (nvme->n_cmd_taskq == NULL) {
2488 dev_err(dip, CE_WARN, "!failed to create cmd taskq");
2489 goto fail;
2490 }
2491
2492
2493 if (nvme_init(nvme) != DDI_SUCCESS)
2494 goto fail;
2495
2496 /*
2497 * Attach the blkdev driver for each namespace.
2498 */
2499 for (i = 0; i != nvme->n_namespace_count; i++) {
2500 if (nvme->n_ns[i].ns_ignore)
2501 continue;
2502
2503 nvme->n_ns[i].ns_bd_hdl = bd_alloc_handle(&nvme->n_ns[i],
2504 &nvme_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP);
2505
2506 if (nvme->n_ns[i].ns_bd_hdl == NULL) {
2507 dev_err(dip, CE_WARN,
2508 "!failed to get blkdev handle for namespace %d", i);
2509 goto fail;
2510 }
2511
2512 if (bd_attach_handle(dip, nvme->n_ns[i].ns_bd_hdl)
2513 != DDI_SUCCESS) {
2514 dev_err(dip, CE_WARN,
2515 "!failed to attach blkdev handle for namespace %d",
2516 i);
2517 goto fail;
2518 }
2519 }
2520
2521 return (DDI_SUCCESS);
2522
2523 fail:
2524 /* attach successful anyway so that FMA can retire the device */
2525 if (nvme->n_dead)
2526 return (DDI_SUCCESS);
2527
2528 (void) nvme_detach(dip, DDI_DETACH);
2529
2530 return (DDI_FAILURE);
2531 }
2532
2533 static int
2534 nvme_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
2535 {
2536 int instance, i;
2537 nvme_t *nvme;
2538
2539 if (cmd != DDI_DETACH)
2540 return (DDI_FAILURE);
2541
2542 instance = ddi_get_instance(dip);
2543
2544 nvme = ddi_get_soft_state(nvme_state, instance);
2545
2546 if (nvme == NULL)
2547 return (DDI_FAILURE);
2548
2549 if (nvme->n_ns) {
2550 for (i = 0; i != nvme->n_namespace_count; i++) {
2551 if (nvme->n_ns[i].ns_bd_hdl) {
2552 (void) bd_detach_handle(
2553 nvme->n_ns[i].ns_bd_hdl);
2554 bd_free_handle(nvme->n_ns[i].ns_bd_hdl);
2555 }
2556
2557 if (nvme->n_ns[i].ns_idns)
2558 kmem_free(nvme->n_ns[i].ns_idns,
2559 sizeof (nvme_identify_nsid_t));
2560 }
2561
2562 kmem_free(nvme->n_ns, sizeof (nvme_namespace_t) *
2563 nvme->n_namespace_count);
2564 }
2565
2566 if (nvme->n_progress & NVME_INTERRUPTS)
2567 nvme_release_interrupts(nvme);
2568
2569 if (nvme->n_cmd_taskq)
2570 ddi_taskq_wait(nvme->n_cmd_taskq);
2571
2572 if (nvme->n_ioq_count > 0) {
2573 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
2574 if (nvme->n_ioq[i] != NULL) {
2575 /* TODO: send destroy queue commands */
2576 mutex_enter(&nvme_global_mutex);
2577 list_remove(&nvme_qp_list, nvme->n_ioq[i]);
2578 mutex_exit(&nvme_global_mutex);
2579 nvme_free_qpair(nvme->n_ioq[i]);
2580 }
2581 }
2582
2583 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *) *
2584 (nvme->n_ioq_count + 1));
2585 }
2586
2587 if (nvme->n_progress & NVME_REGS_MAPPED) {
2588 nvme_shutdown(nvme, NVME_CC_SHN_NORMAL, B_FALSE);
2589 (void) nvme_reset(nvme, B_FALSE);
2590 }
2591
2592 if (nvme->n_cmd_taskq)
2593 ddi_taskq_destroy(nvme->n_cmd_taskq);
2594
2595 if (nvme->n_progress & NVME_CTRL_LIMITS)
2596 sema_destroy(&nvme->n_abort_sema);
2597
2598 if (nvme->n_progress & NVME_ADMIN_QUEUE)
2599 nvme_free_qpair(nvme->n_adminq);
2600
2601 if (nvme->n_idctl)
2602 kmem_free(nvme->n_idctl, sizeof (nvme_identify_ctrl_t));
2603
2604 if (nvme->n_progress & NVME_REGS_MAPPED)
2605 ddi_regs_map_free(&nvme->n_regh);
2606
2607 if (nvme->n_progress & NVME_FMA_INIT) {
2608 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2609 ddi_fm_handler_unregister(nvme->n_dip);
2610
2611 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2612 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2613 pci_ereport_teardown(nvme->n_dip);
2614
2615 ddi_fm_fini(nvme->n_dip);
2616 }
2617
2618 if (nvme->n_vendor != NULL)
2619 strfree(nvme->n_vendor);
2620
2621 if (nvme->n_product != NULL)
2622 strfree(nvme->n_product);
2623
2624 ddi_soft_state_free(nvme_state, instance);
2625
2626 return (DDI_SUCCESS);
2627 }
2628
2629 static int
2630 nvme_quiesce(dev_info_t *dip)
2631 {
2632 int instance;
2633 nvme_t *nvme;
2634
2635 instance = ddi_get_instance(dip);
2636
2637 nvme = ddi_get_soft_state(nvme_state, instance);
2638
2639 if (nvme == NULL)
2640 return (DDI_FAILURE);
2641
2642 nvme_shutdown(nvme, NVME_CC_SHN_ABRUPT, B_TRUE);
2643
2644 (void) nvme_reset(nvme, B_TRUE);
2645
2646 return (DDI_FAILURE);
2647 }
2648
2649 static int
2650 nvme_fill_prp(nvme_cmd_t *cmd, bd_xfer_t *xfer)
2651 {
2652 nvme_t *nvme = cmd->nc_nvme;
2653 int nprp_page, nprp;
2654 uint64_t *prp;
2655
2656 if (xfer->x_ndmac == 0)
2657 return (DDI_FAILURE);
2658
2659 cmd->nc_sqe.sqe_dptr.d_prp[0] = xfer->x_dmac.dmac_laddress;
2660 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
2661
2662 if (xfer->x_ndmac == 1) {
2663 cmd->nc_sqe.sqe_dptr.d_prp[1] = 0;
2664 return (DDI_SUCCESS);
2665 } else if (xfer->x_ndmac == 2) {
2666 cmd->nc_sqe.sqe_dptr.d_prp[1] = xfer->x_dmac.dmac_laddress;
2667 return (DDI_SUCCESS);
2668 }
2669
2670 xfer->x_ndmac--;
2671
2672 nprp_page = nvme->n_pagesize / sizeof (uint64_t) - 1;
2673 ASSERT(nprp_page > 0);
2674 nprp = (xfer->x_ndmac + nprp_page - 1) / nprp_page;
2675
2676 /*
2677 * We currently don't support chained PRPs and set up our DMA
2678 * attributes to reflect that. If we still get an I/O request
2679 * that needs a chained PRP something is very wrong.
2680 */
2681 VERIFY(nprp == 1);
2682
2683 if (nvme_zalloc_dma(nvme, nvme->n_pagesize * nprp, DDI_DMA_READ,
2684 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
2685 dev_err(nvme->n_dip, CE_WARN, "!%s: nvme_zalloc_dma failed",
2686 __func__);
2687 return (DDI_FAILURE);
2688 }
2689
2690 cmd->nc_sqe.sqe_dptr.d_prp[1] = cmd->nc_dma->nd_cookie.dmac_laddress;
2691 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah, &cmd->nc_dma->nd_cookie);
2692
2693 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2694 for (prp = (uint64_t *)cmd->nc_dma->nd_memp;
2695 xfer->x_ndmac > 0;
2696 prp++, xfer->x_ndmac--) {
2697 *prp = xfer->x_dmac.dmac_laddress;
2698 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
2699 }
2700
2701 (void) ddi_dma_sync(cmd->nc_dma->nd_dmah, 0, cmd->nc_dma->nd_len,
2702 DDI_DMA_SYNC_FORDEV);
2703 return (DDI_SUCCESS);
2704 }
2705
2706 static nvme_cmd_t *
2707 nvme_create_nvm_cmd(nvme_namespace_t *ns, uint8_t opc, bd_xfer_t *xfer)
2708 {
2709 nvme_t *nvme = ns->ns_nvme;
2710 nvme_cmd_t *cmd;
2711
2712 /*
2713 * Blkdev only sets BD_XFER_POLL when dumping, so don't sleep.
2714 */
2715 cmd = nvme_alloc_cmd(nvme, (xfer->x_flags & BD_XFER_POLL) ?
2716 KM_NOSLEEP : KM_SLEEP);
2717
2718 if (cmd == NULL)
2719 return (NULL);
2720
2721 cmd->nc_sqe.sqe_opc = opc;
2722 cmd->nc_callback = nvme_bd_xfer_done;
2723 cmd->nc_xfer = xfer;
2724
2725 switch (opc) {
2726 case NVME_OPC_NVM_WRITE:
2727 case NVME_OPC_NVM_READ:
2728 VERIFY(xfer->x_nblks <= 0x10000);
2729
2730 cmd->nc_sqe.sqe_nsid = ns->ns_id;
2731
2732 cmd->nc_sqe.sqe_cdw10 = xfer->x_blkno & 0xffffffffu;
2733 cmd->nc_sqe.sqe_cdw11 = (xfer->x_blkno >> 32);
2734 cmd->nc_sqe.sqe_cdw12 = (uint16_t)(xfer->x_nblks - 1);
2735
2736 if (nvme_fill_prp(cmd, xfer) != DDI_SUCCESS)
2737 goto fail;
2738 break;
2739
2740 case NVME_OPC_NVM_FLUSH:
2741 cmd->nc_sqe.sqe_nsid = ns->ns_id;
2742 break;
2743
2744 default:
2745 goto fail;
2746 }
2747
2748 return (cmd);
2749
2750 fail:
2751 nvme_free_cmd(cmd);
2752 return (NULL);
2753 }
2754
2755 static void
2756 nvme_bd_xfer_done(void *arg)
2757 {
2758 nvme_cmd_t *cmd = arg;
2759 bd_xfer_t *xfer = cmd->nc_xfer;
2760 int error = 0;
2761
2762 error = nvme_check_cmd_status(cmd);
2763 nvme_free_cmd(cmd);
2764
2765 bd_xfer_done(xfer, error);
2766 }
2767
2768 static void
2769 nvme_bd_driveinfo(void *arg, bd_drive_t *drive)
2770 {
2771 nvme_namespace_t *ns = arg;
2772 nvme_t *nvme = ns->ns_nvme;
2773
2774 /*
2775 * blkdev maintains one queue size per instance (namespace),
2776 * but all namespace share the I/O queues.
2777 * TODO: need to figure out a sane default, or use per-NS I/O queues,
2778 * or change blkdev to handle EAGAIN
2779 */
2780 drive->d_qsize = nvme->n_ioq_count * nvme->n_io_queue_len
2781 / nvme->n_namespace_count;
2782
2783 /*
2784 * d_maxxfer is not set, which means the value is taken from the DMA
2785 * attributes specified to bd_alloc_handle.
2786 */
2787
2788 drive->d_removable = B_FALSE;
2789 drive->d_hotpluggable = B_FALSE;
2790
2791 drive->d_target = ns->ns_id;
2792 drive->d_lun = 0;
2793
2794 drive->d_model = nvme->n_idctl->id_model;
2795 drive->d_model_len = sizeof (nvme->n_idctl->id_model);
2796 drive->d_vendor = nvme->n_vendor;
2797 drive->d_vendor_len = strlen(nvme->n_vendor);
2798 drive->d_product = nvme->n_product;
2799 drive->d_product_len = strlen(nvme->n_product);
2800 drive->d_serial = nvme->n_idctl->id_serial;
2801 drive->d_serial_len = sizeof (nvme->n_idctl->id_serial);
2802 drive->d_revision = nvme->n_idctl->id_fwrev;
2803 drive->d_revision_len = sizeof (nvme->n_idctl->id_fwrev);
2804 }
2805
2806 static int
2807 nvme_bd_mediainfo(void *arg, bd_media_t *media)
2808 {
2809 nvme_namespace_t *ns = arg;
2810
2811 media->m_nblks = ns->ns_block_count;
2812 media->m_blksize = ns->ns_block_size;
2813 media->m_readonly = B_FALSE;
2814 media->m_solidstate = B_TRUE;
2815
2816 media->m_pblksize = ns->ns_best_block_size;
2817
2818 return (0);
2819 }
2820
2821 static int
2822 nvme_bd_cmd(nvme_namespace_t *ns, bd_xfer_t *xfer, uint8_t opc)
2823 {
2824 nvme_t *nvme = ns->ns_nvme;
2825 nvme_cmd_t *cmd;
2826
2827 if (nvme->n_dead)
2828 return (EIO);
2829
2830 /* No polling for now */
2831 if (xfer->x_flags & BD_XFER_POLL)
2832 return (EIO);
2833
2834 cmd = nvme_create_nvm_cmd(ns, opc, xfer);
2835 if (cmd == NULL)
2836 return (ENOMEM);
2837
2838 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1;
2839 ASSERT(cmd->nc_sqid <= nvme->n_ioq_count);
2840
2841 if (nvme_submit_cmd(nvme->n_ioq[cmd->nc_sqid], cmd)
2842 != DDI_SUCCESS)
2843 return (EAGAIN);
2844
2845 return (0);
2846 }
2847
2848 static int
2849 nvme_bd_read(void *arg, bd_xfer_t *xfer)
2850 {
2851 nvme_namespace_t *ns = arg;
2852
2853 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_READ));
2854 }
2855
2856 static int
2857 nvme_bd_write(void *arg, bd_xfer_t *xfer)
2858 {
2859 nvme_namespace_t *ns = arg;
2860
2861 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_WRITE));
2862 }
2863
2864 static int
2865 nvme_bd_sync(void *arg, bd_xfer_t *xfer)
2866 {
2867 nvme_namespace_t *ns = arg;
2868
2869 if (ns->ns_nvme->n_dead)
2870 return (EIO);
2871
2872 /*
2873 * If the volatile write cache isn't enabled the FLUSH command is a
2874 * no-op, so we can take a shortcut here.
2875 */
2876 if (ns->ns_nvme->n_volatile_write_cache_enabled == B_FALSE) {
2877 bd_xfer_done(xfer, ENOTSUP);
2878 return (0);
2879 }
2880
2881 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_FLUSH));
2882 }
2883
2884 static int
2885 nvme_bd_devid(void *arg, dev_info_t *devinfo, ddi_devid_t *devid)
2886 {
2887 nvme_namespace_t *ns = arg;
2888
2889 return (ddi_devid_init(devinfo, DEVID_ENCAP, strlen(ns->ns_devid),
2890 ns->ns_devid, devid));
2891 }
2892
2893 static void
2894 nvme_intr_monitor(void *arg)
2895 {
2896 nvme_qpair_t *qp;
2897 hrtime_t diff, now_ns;
2898
2899 if (!nvme_enable_intr_monitoring)
2900 return;
2901 mutex_enter(&nvme_global_mutex);
2902 now_ns = gethrtime();
2903 for (qp = list_head(&nvme_qp_list); qp != NULL;
2904 qp = list_next(&nvme_qp_list, qp)) {
2905 diff = now_ns - qp->nq_ts;
2906 if (diff >= nvme_intr_timeout_ns && qp->nq_active_cmds > 0) {
2907 if (nvme_process_cq_cmds(qp->nq_nvme, qp)) {
2908 nvme_intr_timeouts++;
2909 qp->nq_nvme->n_intr_timeouts++;
2910 }
2911 }
2912 }
2913 mutex_exit(&nvme_global_mutex);
2914 }