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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/i86pc/io/ioat/ioat.c
+++ new/usr/src/uts/i86pc/io/ioat/ioat.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 #include <sys/errno.h>
28 28 #include <sys/types.h>
29 29 #include <sys/conf.h>
30 30 #include <sys/kmem.h>
31 31 #include <sys/ddi.h>
32 32 #include <sys/stat.h>
33 33 #include <sys/sunddi.h>
34 34 #include <sys/file.h>
35 35 #include <sys/open.h>
36 36 #include <sys/modctl.h>
37 37 #include <sys/ddi_impldefs.h>
38 38 #include <sys/sysmacros.h>
39 39
40 40 #include <sys/ioat.h>
41 41
42 42 static int ioat_open(dev_t *devp, int flag, int otyp, cred_t *cred);
43 43 static int ioat_close(dev_t devp, int flag, int otyp, cred_t *cred);
44 44 static int ioat_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
45 45 static int ioat_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
46 46 static int ioat_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg,
47 47 void **result);
48 48 static int ioat_quiesce(dev_info_t *dip);
49 49
50 50 static struct cb_ops ioat_cb_ops = {
51 51 ioat_open, /* cb_open */
52 52 ioat_close, /* cb_close */
53 53 nodev, /* cb_strategy */
54 54 nodev, /* cb_print */
55 55 nodev, /* cb_dump */
56 56 nodev, /* cb_read */
57 57 nodev, /* cb_write */
58 58 ioat_ioctl, /* cb_ioctl */
59 59 nodev, /* cb_devmap */
60 60 nodev, /* cb_mmap */
61 61 nodev, /* cb_segmap */
62 62 nochpoll, /* cb_chpoll */
63 63 ddi_prop_op, /* cb_prop_op */
64 64 NULL, /* cb_stream */
65 65 D_NEW | D_MP | D_64BIT | D_DEVMAP, /* cb_flag */
66 66 CB_REV
67 67 };
68 68
69 69 static struct dev_ops ioat_dev_ops = {
70 70 DEVO_REV, /* devo_rev */
71 71 0, /* devo_refcnt */
72 72 ioat_getinfo, /* devo_getinfo */
73 73 nulldev, /* devo_identify */
74 74 nulldev, /* devo_probe */
75 75 ioat_attach, /* devo_attach */
76 76 ioat_detach, /* devo_detach */
77 77 nodev, /* devo_reset */
78 78 &ioat_cb_ops, /* devo_cb_ops */
79 79 NULL, /* devo_bus_ops */
80 80 NULL, /* devo_power */
81 81 ioat_quiesce, /* devo_quiesce */
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82 82 };
83 83
84 84 static struct modldrv ioat_modldrv = {
85 85 &mod_driverops, /* Type of module. This one is a driver */
86 86 "ioat driver", /* Name of the module. */
87 87 &ioat_dev_ops, /* driver ops */
88 88 };
89 89
90 90 static struct modlinkage ioat_modlinkage = {
91 91 MODREV_1,
92 - (void *) &ioat_modldrv,
93 - NULL
92 + { (void *) &ioat_modldrv, NULL }
94 93 };
95 94
96 95
97 96 void *ioat_statep;
98 97
99 98 static int ioat_chip_init(ioat_state_t *state);
100 99 static void ioat_chip_fini(ioat_state_t *state);
101 100 static int ioat_drv_init(ioat_state_t *state);
102 101 static void ioat_drv_fini(ioat_state_t *state);
103 102 static uint_t ioat_isr(caddr_t parm);
104 103 static void ioat_intr_enable(ioat_state_t *state);
105 104 static void ioat_intr_disable(ioat_state_t *state);
106 105 void ioat_detach_finish(ioat_state_t *state);
107 106
108 107
109 108 ddi_device_acc_attr_t ioat_acc_attr = {
110 109 DDI_DEVICE_ATTR_V0, /* devacc_attr_version */
111 110 DDI_NEVERSWAP_ACC, /* devacc_attr_endian_flags */
112 111 DDI_STORECACHING_OK_ACC, /* devacc_attr_dataorder */
113 112 DDI_DEFAULT_ACC /* devacc_attr_access */
114 113 };
115 114
116 115 /* dcopy callback interface */
117 116 dcopy_device_cb_t ioat_cb = {
118 117 DCOPY_DEVICECB_V0,
119 118 0, /* reserved */
120 119 ioat_channel_alloc,
121 120 ioat_channel_free,
122 121 ioat_cmd_alloc,
123 122 ioat_cmd_free,
124 123 ioat_cmd_post,
125 124 ioat_cmd_poll,
126 125 ioat_unregister_complete
127 126 };
128 127
129 128 /*
130 129 * _init()
131 130 */
132 131 int
133 132 _init(void)
134 133 {
135 134 int e;
136 135
137 136 e = ddi_soft_state_init(&ioat_statep, sizeof (ioat_state_t), 1);
138 137 if (e != 0) {
139 138 return (e);
140 139 }
141 140
142 141 e = mod_install(&ioat_modlinkage);
143 142 if (e != 0) {
144 143 ddi_soft_state_fini(&ioat_statep);
145 144 return (e);
146 145 }
147 146
148 147 return (0);
149 148 }
150 149
151 150 /*
152 151 * _info()
153 152 */
154 153 int
155 154 _info(struct modinfo *modinfop)
156 155 {
157 156 return (mod_info(&ioat_modlinkage, modinfop));
158 157 }
159 158
160 159 /*
161 160 * _fini()
162 161 */
163 162 int
164 163 _fini(void)
165 164 {
166 165 int e;
167 166
168 167 e = mod_remove(&ioat_modlinkage);
169 168 if (e != 0) {
170 169 return (e);
171 170 }
172 171
173 172 ddi_soft_state_fini(&ioat_statep);
174 173
175 174 return (0);
176 175 }
177 176
178 177 /*
179 178 * ioat_attach()
180 179 */
181 180 static int
182 181 ioat_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
183 182 {
184 183 ioat_state_t *state;
185 184 int instance;
186 185 int e;
187 186
188 187
189 188 switch (cmd) {
190 189 case DDI_ATTACH:
191 190 break;
192 191
193 192 case DDI_RESUME:
194 193 instance = ddi_get_instance(dip);
195 194 state = ddi_get_soft_state(ioat_statep, instance);
196 195 if (state == NULL) {
197 196 return (DDI_FAILURE);
198 197 }
199 198 e = ioat_channel_resume(state);
200 199 if (e != DDI_SUCCESS) {
201 200 return (DDI_FAILURE);
202 201 }
203 202 ioat_intr_enable(state);
204 203 return (DDI_SUCCESS);
205 204
206 205 default:
207 206 return (DDI_FAILURE);
208 207 }
209 208
210 209 instance = ddi_get_instance(dip);
211 210 e = ddi_soft_state_zalloc(ioat_statep, instance);
212 211 if (e != DDI_SUCCESS) {
213 212 return (DDI_FAILURE);
214 213 }
215 214 state = ddi_get_soft_state(ioat_statep, instance);
216 215 if (state == NULL) {
217 216 goto attachfail_get_soft_state;
218 217 }
219 218
220 219 state->is_dip = dip;
221 220 state->is_instance = instance;
222 221
223 222 /* setup the registers, save away some device info */
224 223 e = ioat_chip_init(state);
225 224 if (e != DDI_SUCCESS) {
226 225 goto attachfail_chip_init;
227 226 }
228 227
229 228 /* initialize driver state, must be after chip init */
230 229 e = ioat_drv_init(state);
231 230 if (e != DDI_SUCCESS) {
232 231 goto attachfail_drv_init;
233 232 }
234 233
235 234 /* create the minor node (for the ioctl) */
236 235 e = ddi_create_minor_node(dip, "ioat", S_IFCHR, instance, DDI_PSEUDO,
237 236 0);
238 237 if (e != DDI_SUCCESS) {
239 238 goto attachfail_minor_node;
240 239 }
241 240
242 241 /* Enable device interrupts */
243 242 ioat_intr_enable(state);
244 243
245 244 /* Report that driver was loaded */
246 245 ddi_report_dev(dip);
247 246
248 247 /* register with dcopy */
249 248 e = dcopy_device_register(state, &state->is_deviceinfo,
250 249 &state->is_device_handle);
251 250 if (e != DCOPY_SUCCESS) {
252 251 goto attachfail_register;
253 252 }
254 253
255 254 return (DDI_SUCCESS);
256 255
257 256 attachfail_register:
258 257 ioat_intr_disable(state);
259 258 ddi_remove_minor_node(dip, NULL);
260 259 attachfail_minor_node:
261 260 ioat_drv_fini(state);
262 261 attachfail_drv_init:
263 262 ioat_chip_fini(state);
264 263 attachfail_chip_init:
265 264 attachfail_get_soft_state:
266 265 (void) ddi_soft_state_free(ioat_statep, instance);
267 266
268 267 return (DDI_FAILURE);
269 268 }
270 269
271 270 /*
272 271 * ioat_detach()
273 272 */
274 273 static int
275 274 ioat_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
276 275 {
277 276 ioat_state_t *state;
278 277 int instance;
279 278 int e;
280 279
281 280
282 281 instance = ddi_get_instance(dip);
283 282 state = ddi_get_soft_state(ioat_statep, instance);
284 283 if (state == NULL) {
285 284 return (DDI_FAILURE);
286 285 }
287 286
288 287 switch (cmd) {
289 288 case DDI_DETACH:
290 289 break;
291 290
292 291 case DDI_SUSPEND:
293 292 ioat_channel_suspend(state);
294 293 return (DDI_SUCCESS);
295 294
296 295 default:
297 296 return (DDI_FAILURE);
298 297 }
299 298
300 299 /*
301 300 * try to unregister from dcopy. Since this driver doesn't follow the
302 301 * traditional parent/child model, we may still be in use so we can't
303 302 * detach yet.
304 303 */
305 304 e = dcopy_device_unregister(&state->is_device_handle);
306 305 if (e != DCOPY_SUCCESS) {
307 306 if (e == DCOPY_PENDING) {
308 307 cmn_err(CE_NOTE, "device busy, performing asynchronous"
309 308 " detach\n");
310 309 }
311 310 return (DDI_FAILURE);
312 311 }
313 312
314 313 ioat_detach_finish(state);
315 314
316 315 return (DDI_SUCCESS);
317 316 }
318 317
319 318 /*
320 319 * ioat_getinfo()
321 320 */
322 321 /*ARGSUSED*/
323 322 static int
324 323 ioat_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result)
325 324 {
326 325 ioat_state_t *state;
327 326 int instance;
328 327 dev_t dev;
329 328 int e;
330 329
331 330
332 331 dev = (dev_t)arg;
333 332 instance = getminor(dev);
334 333
335 334 switch (cmd) {
336 335 case DDI_INFO_DEVT2DEVINFO:
337 336 state = ddi_get_soft_state(ioat_statep, instance);
338 337 if (state == NULL) {
339 338 return (DDI_FAILURE);
340 339 }
341 340 *result = (void *)state->is_dip;
342 341 e = DDI_SUCCESS;
343 342 break;
344 343
345 344 case DDI_INFO_DEVT2INSTANCE:
346 345 *result = (void *)(uintptr_t)instance;
347 346 e = DDI_SUCCESS;
348 347 break;
349 348
350 349 default:
351 350 e = DDI_FAILURE;
352 351 break;
353 352 }
354 353
355 354 return (e);
356 355 }
357 356
358 357
359 358 /*
360 359 * ioat_open()
361 360 */
362 361 /*ARGSUSED*/
363 362 static int
364 363 ioat_open(dev_t *devp, int flag, int otyp, cred_t *cred)
365 364 {
366 365 ioat_state_t *state;
367 366 int instance;
368 367
369 368 instance = getminor(*devp);
370 369 state = ddi_get_soft_state(ioat_statep, instance);
371 370 if (state == NULL) {
372 371 return (ENXIO);
373 372 }
374 373
375 374 return (0);
376 375 }
377 376
378 377
379 378 /*
380 379 * ioat_close()
381 380 */
382 381 /*ARGSUSED*/
383 382 static int
384 383 ioat_close(dev_t devp, int flag, int otyp, cred_t *cred)
385 384 {
386 385 return (0);
387 386 }
388 387
389 388
390 389 /*
391 390 * ioat_chip_init()
392 391 */
393 392 static int
394 393 ioat_chip_init(ioat_state_t *state)
395 394 {
396 395 ddi_device_acc_attr_t attr;
397 396 int e;
398 397
399 398
400 399 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
401 400 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
402 401 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
403 402
404 403 e = ddi_regs_map_setup(state->is_dip, 1, (caddr_t *)&state->is_genregs,
405 404 0, 0, &attr, &state->is_reg_handle);
406 405 if (e != DDI_SUCCESS) {
407 406 goto chipinitfail_regsmap;
408 407 }
409 408
410 409 /* save away ioat chip info */
411 410 state->is_num_channels = (uint_t)ddi_get8(state->is_reg_handle,
412 411 &state->is_genregs[IOAT_CHANCNT]);
413 412
414 413 /*
415 414 * If we get a bogus value, something is wrong with the H/W, fail to
416 415 * attach.
417 416 */
418 417 if (state->is_num_channels == 0) {
419 418 goto chipinitfail_numchan;
420 419 }
421 420
422 421 state->is_maxxfer = (uint_t)ddi_get8(state->is_reg_handle,
423 422 &state->is_genregs[IOAT_XFERCAP]);
424 423 state->is_chanoff = (uintptr_t)ddi_get16(state->is_reg_handle,
425 424 (uint16_t *)&state->is_genregs[IOAT_PERPORT_OFF]);
426 425 state->is_cbver = (uint_t)ddi_get8(state->is_reg_handle,
427 426 &state->is_genregs[IOAT_CBVER]);
428 427 state->is_intrdelay = (uint_t)ddi_get16(state->is_reg_handle,
429 428 (uint16_t *)&state->is_genregs[IOAT_INTRDELAY]);
430 429 state->is_status = (uint_t)ddi_get16(state->is_reg_handle,
431 430 (uint16_t *)&state->is_genregs[IOAT_CSSTATUS]);
432 431 state->is_capabilities = (uint_t)ddi_get32(state->is_reg_handle,
433 432 (uint32_t *)&state->is_genregs[IOAT_DMACAPABILITY]);
434 433
435 434 if (state->is_cbver & 0x10) {
436 435 state->is_ver = IOAT_CBv1;
437 436 } else if (state->is_cbver & 0x20) {
438 437 state->is_ver = IOAT_CBv2;
439 438 } else {
440 439 goto chipinitfail_version;
441 440 }
442 441
443 442 return (DDI_SUCCESS);
444 443
445 444 chipinitfail_version:
446 445 chipinitfail_numchan:
447 446 ddi_regs_map_free(&state->is_reg_handle);
448 447 chipinitfail_regsmap:
449 448 return (DDI_FAILURE);
450 449 }
451 450
452 451
453 452 /*
454 453 * ioat_chip_fini()
455 454 */
456 455 static void
457 456 ioat_chip_fini(ioat_state_t *state)
458 457 {
459 458 ddi_regs_map_free(&state->is_reg_handle);
460 459 }
461 460
462 461
463 462 /*
464 463 * ioat_drv_init()
465 464 */
466 465 static int
467 466 ioat_drv_init(ioat_state_t *state)
468 467 {
469 468 ddi_acc_handle_t handle;
470 469 int e;
471 470
472 471
473 472 mutex_init(&state->is_mutex, NULL, MUTEX_DRIVER, NULL);
474 473
475 474 state->is_deviceinfo.di_dip = state->is_dip;
476 475 state->is_deviceinfo.di_num_dma = state->is_num_channels;
477 476 state->is_deviceinfo.di_maxxfer = state->is_maxxfer;
478 477 state->is_deviceinfo.di_capabilities = state->is_capabilities;
479 478 state->is_deviceinfo.di_cb = &ioat_cb;
480 479
481 480 e = pci_config_setup(state->is_dip, &handle);
482 481 if (e != DDI_SUCCESS) {
483 482 goto drvinitfail_config_setup;
484 483 }
485 484
486 485 /* read in Vendor ID */
487 486 state->is_deviceinfo.di_id = (uint64_t)pci_config_get16(handle, 0);
488 487 state->is_deviceinfo.di_id = state->is_deviceinfo.di_id << 16;
489 488
490 489 /* read in Device ID */
491 490 state->is_deviceinfo.di_id |= (uint64_t)pci_config_get16(handle, 2);
492 491 state->is_deviceinfo.di_id = state->is_deviceinfo.di_id << 32;
493 492
494 493 /* Add in chipset version */
495 494 state->is_deviceinfo.di_id |= (uint64_t)state->is_cbver;
496 495 pci_config_teardown(&handle);
497 496
498 497 e = ddi_intr_hilevel(state->is_dip, 0);
499 498 if (e != 0) {
500 499 cmn_err(CE_WARN, "hilevel interrupt not supported\n");
501 500 goto drvinitfail_hilevel;
502 501 }
503 502
504 503 /* we don't support MSIs for v2 yet */
505 504 e = ddi_add_intr(state->is_dip, 0, NULL, NULL, ioat_isr,
506 505 (caddr_t)state);
507 506 if (e != DDI_SUCCESS) {
508 507 goto drvinitfail_add_intr;
509 508 }
510 509
511 510 e = ddi_get_iblock_cookie(state->is_dip, 0, &state->is_iblock_cookie);
512 511 if (e != DDI_SUCCESS) {
513 512 goto drvinitfail_iblock_cookie;
514 513 }
515 514
516 515 e = ioat_channel_init(state);
517 516 if (e != DDI_SUCCESS) {
518 517 goto drvinitfail_channel_init;
519 518 }
520 519
521 520 return (DDI_SUCCESS);
522 521
523 522 drvinitfail_channel_init:
524 523 drvinitfail_iblock_cookie:
525 524 ddi_remove_intr(state->is_dip, 0, state->is_iblock_cookie);
526 525 drvinitfail_add_intr:
527 526 drvinitfail_hilevel:
528 527 drvinitfail_config_setup:
529 528 mutex_destroy(&state->is_mutex);
530 529
531 530 return (DDI_FAILURE);
532 531 }
533 532
534 533
535 534 /*
536 535 * ioat_drv_fini()
537 536 */
538 537 static void
539 538 ioat_drv_fini(ioat_state_t *state)
540 539 {
541 540 ioat_channel_fini(state);
542 541 ddi_remove_intr(state->is_dip, 0, state->is_iblock_cookie);
543 542 mutex_destroy(&state->is_mutex);
544 543 }
545 544
546 545
547 546 /*
548 547 * ioat_unregister_complete()
549 548 */
550 549 void
551 550 ioat_unregister_complete(void *device_private, int status)
552 551 {
553 552 ioat_state_t *state;
554 553
555 554
556 555 state = device_private;
557 556
558 557 if (status != DCOPY_SUCCESS) {
559 558 cmn_err(CE_WARN, "asynchronous detach aborted\n");
560 559 return;
561 560 }
562 561
563 562 cmn_err(CE_CONT, "detach completing\n");
564 563 ioat_detach_finish(state);
565 564 }
566 565
567 566
568 567 /*
569 568 * ioat_detach_finish()
570 569 */
571 570 void
572 571 ioat_detach_finish(ioat_state_t *state)
573 572 {
574 573 ioat_intr_disable(state);
575 574 ddi_remove_minor_node(state->is_dip, NULL);
576 575 ioat_drv_fini(state);
577 576 ioat_chip_fini(state);
578 577 (void) ddi_soft_state_free(ioat_statep, state->is_instance);
579 578 }
580 579
581 580
582 581 /*
583 582 * ioat_intr_enable()
584 583 */
585 584 static void
586 585 ioat_intr_enable(ioat_state_t *state)
587 586 {
588 587 uint32_t intr_status;
589 588
590 589
591 590 /* Clear any pending interrupts */
592 591 intr_status = ddi_get32(state->is_reg_handle,
593 592 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS]);
594 593 if (intr_status != 0) {
595 594 ddi_put32(state->is_reg_handle,
596 595 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS],
597 596 intr_status);
598 597 }
599 598
600 599 /* Enable interrupts on the device */
601 600 ddi_put8(state->is_reg_handle, &state->is_genregs[IOAT_INTRCTL],
602 601 IOAT_INTRCTL_MASTER_EN);
603 602 }
604 603
605 604
606 605 /*
607 606 * ioat_intr_disable()
608 607 */
609 608 static void
610 609 ioat_intr_disable(ioat_state_t *state)
611 610 {
612 611 /*
613 612 * disable interrupts on the device. A read of the interrupt control
614 613 * register clears the enable bit.
615 614 */
616 615 (void) ddi_get8(state->is_reg_handle,
617 616 &state->is_genregs[IOAT_INTRCTL]);
618 617 }
619 618
620 619
621 620 /*
622 621 * ioat_isr()
623 622 */
624 623 static uint_t
625 624 ioat_isr(caddr_t parm)
626 625 {
627 626 uint32_t intr_status;
628 627 ioat_state_t *state;
629 628 uint8_t intrctrl;
630 629 uint32_t chan;
631 630 uint_t r;
632 631 int i;
633 632
634 633 state = (ioat_state_t *)parm;
635 634
636 635 intrctrl = ddi_get8(state->is_reg_handle,
637 636 &state->is_genregs[IOAT_INTRCTL]);
638 637 /* master interrupt enable should always be set */
639 638 ASSERT(intrctrl & IOAT_INTRCTL_MASTER_EN);
640 639
641 640 /* If the interrupt status bit isn't set, it's not ours */
642 641 if (!(intrctrl & IOAT_INTRCTL_INTR_STAT)) {
643 642 /* re-set master interrupt enable (since it clears on read) */
644 643 ddi_put8(state->is_reg_handle,
645 644 &state->is_genregs[IOAT_INTRCTL], intrctrl);
646 645 return (DDI_INTR_UNCLAIMED);
647 646 }
648 647
649 648 /* see which channels generated the interrupt */
650 649 intr_status = ddi_get32(state->is_reg_handle,
651 650 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS]);
652 651
653 652 /* call the intr handler for the channels */
654 653 r = DDI_INTR_UNCLAIMED;
655 654 chan = 1;
656 655 for (i = 0; i < state->is_num_channels; i++) {
657 656 if (intr_status & chan) {
658 657 ioat_channel_intr(&state->is_channel[i]);
659 658 r = DDI_INTR_CLAIMED;
660 659 }
661 660 chan = chan << 1;
662 661 }
663 662
664 663 /*
665 664 * if interrupt status bit was set, there should have been an
666 665 * attention status bit set too.
667 666 */
668 667 ASSERT(r == DDI_INTR_CLAIMED);
669 668
670 669 /* re-set master interrupt enable (since it clears on read) */
671 670 ddi_put8(state->is_reg_handle, &state->is_genregs[IOAT_INTRCTL],
672 671 intrctrl);
673 672
674 673 return (r);
675 674 }
676 675
677 676 static int
678 677 ioat_quiesce(dev_info_t *dip)
679 678 {
680 679 ioat_state_t *state;
681 680 int instance;
682 681
683 682 instance = ddi_get_instance(dip);
684 683 state = ddi_get_soft_state(ioat_statep, instance);
685 684 if (state == NULL) {
686 685 return (DDI_FAILURE);
687 686 }
688 687
689 688 ioat_intr_disable(state);
690 689 ioat_channel_quiesce(state);
691 690
692 691 return (DDI_SUCCESS);
693 692 }
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590 lines elided |
↑ open up ↑ |
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