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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/common/io/ural/ural.c
+++ new/usr/src/uts/common/io/ural/ural.c
1 1 /*
2 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 3 * Use is subject to license terms.
4 4 */
5 5
6 6 /*
7 7 * Copyright (c) 2005, 2006
8 8 * Damien Bergamini <damien.bergamini@free.fr>
9 9 *
10 10 * Permission to use, copy, modify, and distribute this software for any
11 11 * purpose with or without fee is hereby granted, provided that the above
12 12 * copyright notice and this permission notice appear in all copies.
13 13 *
14 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 21 */
22 22
23 23 /*
24 24 * Ralink Technology RT2500USB chipset driver
25 25 * http://www.ralinktech.com/
26 26 */
27 27 #include <sys/types.h>
28 28 #include <sys/cmn_err.h>
29 29 #include <sys/strsubr.h>
30 30 #include <sys/modctl.h>
31 31 #include <sys/devops.h>
32 32 #include <sys/byteorder.h>
33 33 #include <sys/mac_provider.h>
34 34 #include <sys/mac_wifi.h>
35 35 #include <sys/net80211.h>
36 36
37 37 #define USBDRV_MAJOR_VER 2
38 38 #define USBDRV_MINOR_VER 0
39 39 #include <sys/usb/usba.h>
40 40 #include <sys/usb/usba/usba_types.h>
41 41
42 42 #include "ural_reg.h"
43 43 #include "ural_var.h"
44 44
45 45 static void *ural_soft_state_p = NULL;
46 46
47 47 #define RAL_TXBUF_SIZE (IEEE80211_MAX_LEN)
48 48 #define RAL_RXBUF_SIZE (IEEE80211_MAX_LEN)
49 49
50 50 /* quickly determine if a given rate is CCK or OFDM */
51 51 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
52 52 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */
53 53 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */
54 54 #define RAL_SIFS 10 /* us */
55 55 #define RAL_RXTX_TURNAROUND 5 /* us */
56 56
57 57 #define URAL_N(a) (sizeof (a) / sizeof ((a)[0]))
58 58
59 59 /*
60 60 * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
61 61 */
62 62 static const struct ieee80211_rateset ural_rateset_11a =
63 63 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } };
64 64
65 65 static const struct ieee80211_rateset ural_rateset_11b =
66 66 { 4, { 2, 4, 11, 22 } };
67 67
68 68 static const struct ieee80211_rateset ural_rateset_11g =
69 69 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
70 70
71 71 /*
72 72 * Default values for MAC registers; values taken from the reference driver.
73 73 */
74 74 static const struct {
75 75 uint16_t reg;
76 76 uint16_t val;
77 77 } ural_def_mac[] = {
78 78 { RAL_TXRX_CSR5, 0x8c8d },
79 79 { RAL_TXRX_CSR6, 0x8b8a },
80 80 { RAL_TXRX_CSR7, 0x8687 },
81 81 { RAL_TXRX_CSR8, 0x0085 },
82 82 { RAL_MAC_CSR13, 0x1111 },
83 83 { RAL_MAC_CSR14, 0x1e11 },
84 84 { RAL_TXRX_CSR21, 0xe78f },
85 85 { RAL_MAC_CSR9, 0xff1d },
86 86 { RAL_MAC_CSR11, 0x0002 },
87 87 { RAL_MAC_CSR22, 0x0053 },
88 88 { RAL_MAC_CSR15, 0x0000 },
89 89 { RAL_MAC_CSR8, 0x0780 },
90 90 { RAL_TXRX_CSR19, 0x0000 },
91 91 { RAL_TXRX_CSR18, 0x005a },
92 92 { RAL_PHY_CSR2, 0x0000 },
93 93 { RAL_TXRX_CSR0, 0x1ec0 },
94 94 { RAL_PHY_CSR4, 0x000f }
95 95 };
96 96
97 97 /*
98 98 * Default values for BBP registers; values taken from the reference driver.
99 99 */
100 100 static const struct {
101 101 uint8_t reg;
102 102 uint8_t val;
103 103 } ural_def_bbp[] = {
104 104 { 3, 0x02 },
105 105 { 4, 0x19 },
106 106 { 14, 0x1c },
107 107 { 15, 0x30 },
108 108 { 16, 0xac },
109 109 { 17, 0x48 },
110 110 { 18, 0x18 },
111 111 { 19, 0xff },
112 112 { 20, 0x1e },
113 113 { 21, 0x08 },
114 114 { 22, 0x08 },
115 115 { 23, 0x08 },
116 116 { 24, 0x80 },
117 117 { 25, 0x50 },
118 118 { 26, 0x08 },
119 119 { 27, 0x23 },
120 120 { 30, 0x10 },
121 121 { 31, 0x2b },
122 122 { 32, 0xb9 },
123 123 { 34, 0x12 },
124 124 { 35, 0x50 },
125 125 { 39, 0xc4 },
126 126 { 40, 0x02 },
127 127 { 41, 0x60 },
128 128 { 53, 0x10 },
129 129 { 54, 0x18 },
130 130 { 56, 0x08 },
131 131 { 57, 0x10 },
132 132 { 58, 0x08 },
133 133 { 61, 0x60 },
134 134 { 62, 0x10 },
135 135 { 75, 0xff }
136 136 };
137 137
138 138 /*
139 139 * Default values for RF register R2 indexed by channel numbers.
140 140 */
141 141 static const uint32_t ural_rf2522_r2[] = {
142 142 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814,
143 143 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e
144 144 };
145 145
146 146 static const uint32_t ural_rf2523_r2[] = {
147 147 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,
148 148 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346
149 149 };
150 150
151 151 static const uint32_t ural_rf2524_r2[] = {
152 152 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,
153 153 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346
154 154 };
155 155
156 156 static const uint32_t ural_rf2525_r2[] = {
157 157 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d,
158 158 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346
159 159 };
160 160
161 161 static const uint32_t ural_rf2525_hi_r2[] = {
162 162 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345,
163 163 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e
164 164 };
165 165
166 166 static const uint32_t ural_rf2525e_r2[] = {
167 167 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463,
168 168 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b
169 169 };
170 170
171 171 static const uint32_t ural_rf2526_hi_r2[] = {
172 172 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d,
173 173 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241
174 174 };
175 175
176 176 static const uint32_t ural_rf2526_r2[] = {
177 177 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229,
178 178 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d
179 179 };
180 180
181 181 /*
182 182 * For dual-band RF, RF registers R1 and R4 also depend on channel number;
183 183 * values taken from the reference driver.
184 184 */
185 185 static const struct {
186 186 uint8_t chan;
187 187 uint32_t r1;
188 188 uint32_t r2;
189 189 uint32_t r4;
190 190 } ural_rf5222[] = {
191 191 { 1, 0x08808, 0x0044d, 0x00282 },
192 192 { 2, 0x08808, 0x0044e, 0x00282 },
193 193 { 3, 0x08808, 0x0044f, 0x00282 },
194 194 { 4, 0x08808, 0x00460, 0x00282 },
195 195 { 5, 0x08808, 0x00461, 0x00282 },
196 196 { 6, 0x08808, 0x00462, 0x00282 },
197 197 { 7, 0x08808, 0x00463, 0x00282 },
198 198 { 8, 0x08808, 0x00464, 0x00282 },
199 199 { 9, 0x08808, 0x00465, 0x00282 },
200 200 { 10, 0x08808, 0x00466, 0x00282 },
201 201 { 11, 0x08808, 0x00467, 0x00282 },
202 202 { 12, 0x08808, 0x00468, 0x00282 },
203 203 { 13, 0x08808, 0x00469, 0x00282 },
204 204 { 14, 0x08808, 0x0046b, 0x00286 },
205 205
206 206 { 36, 0x08804, 0x06225, 0x00287 },
207 207 { 40, 0x08804, 0x06226, 0x00287 },
208 208 { 44, 0x08804, 0x06227, 0x00287 },
209 209 { 48, 0x08804, 0x06228, 0x00287 },
210 210 { 52, 0x08804, 0x06229, 0x00287 },
211 211 { 56, 0x08804, 0x0622a, 0x00287 },
212 212 { 60, 0x08804, 0x0622b, 0x00287 },
213 213 { 64, 0x08804, 0x0622c, 0x00287 },
214 214
215 215 { 100, 0x08804, 0x02200, 0x00283 },
216 216 { 104, 0x08804, 0x02201, 0x00283 },
217 217 { 108, 0x08804, 0x02202, 0x00283 },
218 218 { 112, 0x08804, 0x02203, 0x00283 },
219 219 { 116, 0x08804, 0x02204, 0x00283 },
220 220 { 120, 0x08804, 0x02205, 0x00283 },
221 221 { 124, 0x08804, 0x02206, 0x00283 },
222 222 { 128, 0x08804, 0x02207, 0x00283 },
223 223 { 132, 0x08804, 0x02208, 0x00283 },
224 224 { 136, 0x08804, 0x02209, 0x00283 },
225 225 { 140, 0x08804, 0x0220a, 0x00283 },
226 226
227 227 { 149, 0x08808, 0x02429, 0x00281 },
228 228 { 153, 0x08808, 0x0242b, 0x00281 },
229 229 { 157, 0x08808, 0x0242d, 0x00281 },
230 230 { 161, 0x08808, 0x0242f, 0x00281 }
231 231 };
232 232
233 233 /*
234 234 * device operations
235 235 */
236 236 static int ural_attach(dev_info_t *, ddi_attach_cmd_t);
237 237 static int ural_detach(dev_info_t *, ddi_detach_cmd_t);
238 238
239 239 /*
240 240 * Module Loading Data & Entry Points
241 241 */
242 242 DDI_DEFINE_STREAM_OPS(ural_dev_ops, nulldev, nulldev, ural_attach,
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243 243 ural_detach, nodev, NULL, D_MP, NULL, ddi_quiesce_not_needed);
244 244
245 245 static struct modldrv ural_modldrv = {
246 246 &mod_driverops, /* Type of module. This one is a driver */
247 247 "ural driver v1.4", /* short description */
248 248 &ural_dev_ops /* driver specific ops */
249 249 };
250 250
251 251 static struct modlinkage modlinkage = {
252 252 MODREV_1,
253 - (void *)&ural_modldrv,
254 - NULL
253 + { (void *)&ural_modldrv, NULL }
255 254 };
256 255
257 256 static int ural_m_stat(void *, uint_t, uint64_t *);
258 257 static int ural_m_start(void *);
259 258 static void ural_m_stop(void *);
260 259 static int ural_m_promisc(void *, boolean_t);
261 260 static int ural_m_multicst(void *, boolean_t, const uint8_t *);
262 261 static int ural_m_unicst(void *, const uint8_t *);
263 262 static mblk_t *ural_m_tx(void *, mblk_t *);
264 263 static void ural_m_ioctl(void *, queue_t *, mblk_t *);
265 264 static int ural_m_setprop(void *, const char *, mac_prop_id_t,
266 265 uint_t, const void *);
267 266 static int ural_m_getprop(void *, const char *, mac_prop_id_t,
268 267 uint_t, void *);
269 268 static void ural_m_propinfo(void *, const char *, mac_prop_id_t,
270 269 mac_prop_info_handle_t);
271 270
272 271 static mac_callbacks_t ural_m_callbacks = {
273 272 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
274 273 ural_m_stat,
275 274 ural_m_start,
276 275 ural_m_stop,
277 276 ural_m_promisc,
278 277 ural_m_multicst,
279 278 ural_m_unicst,
280 279 ural_m_tx,
281 280 NULL,
282 281 ural_m_ioctl,
283 282 NULL, /* mc_getcapab */
284 283 NULL,
285 284 NULL,
286 285 ural_m_setprop,
287 286 ural_m_getprop,
288 287 ural_m_propinfo
289 288 };
290 289
291 290 static void ural_amrr_start(struct ural_softc *, struct ieee80211_node *);
292 291 static int ural_tx_trigger(struct ural_softc *, mblk_t *);
293 292 static int ural_rx_trigger(struct ural_softc *);
294 293
295 294 uint32_t ural_dbg_flags = 0;
296 295
297 296 void
298 297 ral_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
299 298 {
300 299 va_list args;
301 300
302 301 if (dbg_flags & ural_dbg_flags) {
303 302 va_start(args, fmt);
304 303 vcmn_err(CE_CONT, fmt, args);
305 304 va_end(args);
306 305 }
307 306 }
308 307
309 308 static uint16_t
310 309 ural_read(struct ural_softc *sc, uint16_t reg)
311 310 {
312 311 usb_ctrl_setup_t req;
313 312 usb_cr_t cr;
314 313 usb_cb_flags_t cf;
315 314 mblk_t *mp;
316 315 int err;
317 316 uint16_t val;
318 317
319 318 bzero(&req, sizeof (req));
320 319 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST;
321 320 req.bRequest = RAL_READ_MAC;
322 321 req.wValue = 0;
323 322 req.wIndex = reg;
324 323 req.wLength = sizeof (uint16_t);
325 324
326 325 mp = NULL;
327 326 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
328 327 &cr, &cf, 0);
329 328
330 329 if (err != USB_SUCCESS) {
331 330 ral_debug(RAL_DBG_ERR,
332 331 "ural_read(): could not read MAC register:"
333 332 " cr:%s(%d), cf:(%x)\n",
334 333 usb_str_cr(cr), cr, cf);
335 334 return (0);
336 335 }
337 336
338 337 bcopy(mp->b_rptr, &val, sizeof (uint16_t));
339 338
340 339 if (mp)
341 340 freemsg(mp);
342 341
343 342 return (LE_16(val));
344 343 }
345 344
346 345 static void
347 346 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
348 347 {
349 348 usb_ctrl_setup_t req;
350 349 usb_cr_t cr;
351 350 usb_cb_flags_t cf;
352 351 mblk_t *mp;
353 352 int err;
354 353
355 354 bzero(&req, sizeof (req));
356 355 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST;
357 356 req.bRequest = RAL_READ_MULTI_MAC;
358 357 req.wValue = 0;
359 358 req.wIndex = reg;
360 359 req.wLength = (uint16_t)len;
361 360 req.attrs = USB_ATTRS_AUTOCLEARING;
362 361
363 362 mp = NULL;
364 363 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
365 364 &cr, &cf, 0);
366 365
367 366 if (err != USB_SUCCESS) {
368 367 ral_debug(RAL_DBG_ERR,
369 368 "ural_read_multi(): could not read MAC register:"
370 369 "cr:%s(%d), cf:(%x)\n",
371 370 usb_str_cr(cr), cr, cf);
372 371 return;
373 372 }
374 373
375 374 bcopy(mp->b_rptr, buf, len);
376 375
377 376 if (mp)
378 377 freemsg(mp);
379 378 }
380 379
381 380 static void
382 381 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
383 382 {
384 383 usb_ctrl_setup_t req;
385 384 usb_cr_t cr;
386 385 usb_cb_flags_t cf;
387 386 int err;
388 387
389 388 bzero(&req, sizeof (req));
390 389 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_HOST_TO_DEV;
391 390 req.bRequest = RAL_WRITE_MAC;
392 391 req.wValue = val;
393 392 req.wIndex = reg;
394 393 req.wLength = 0;
395 394 req.attrs = USB_ATTRS_NONE;
396 395
397 396 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL,
398 397 &cr, &cf, 0);
399 398
400 399 if (err != USB_SUCCESS) {
401 400 ral_debug(RAL_DBG_ERR,
402 401 "ural_write(): could not write MAC register:"
403 402 "cr:%s(%d), cf:(%x)\n",
404 403 usb_str_cr(cr), cr, cf);
405 404 }
406 405 }
407 406
408 407 /* ARGSUSED */
409 408 static void
410 409 ural_txeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req)
411 410 {
412 411 struct ural_softc *sc = (struct ural_softc *)req->bulk_client_private;
413 412 struct ieee80211com *ic = &sc->sc_ic;
414 413
415 414 ral_debug(RAL_DBG_TX,
416 415 "ural_txeof(): cr:%s(%d), flags:0x%x, tx_queued:%d",
417 416 usb_str_cr(req->bulk_completion_reason),
418 417 req->bulk_completion_reason,
419 418 req->bulk_cb_flags,
420 419 sc->tx_queued);
421 420
422 421 if (req->bulk_completion_reason != USB_CR_OK)
423 422 sc->sc_tx_err++;
424 423
425 424 mutex_enter(&sc->tx_lock);
426 425
427 426 sc->tx_queued--;
428 427 sc->sc_tx_timer = 0;
429 428
430 429 if (sc->sc_need_sched) {
431 430 sc->sc_need_sched = 0;
432 431 mac_tx_update(ic->ic_mach);
433 432 }
434 433
435 434 mutex_exit(&sc->tx_lock);
436 435 usb_free_bulk_req(req);
437 436 }
438 437
439 438 /* ARGSUSED */
440 439 static void
441 440 ural_rxeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req)
442 441 {
443 442 struct ural_softc *sc = (struct ural_softc *)req->bulk_client_private;
444 443 struct ieee80211com *ic = &sc->sc_ic;
445 444
446 445 struct ural_rx_desc *desc;
447 446 struct ieee80211_frame *wh;
448 447 struct ieee80211_node *ni;
449 448
450 449 mblk_t *m, *mp;
451 450 int len, pktlen;
452 451 char *rxbuf;
453 452
454 453 mp = req->bulk_data;
455 454 req->bulk_data = NULL;
456 455
457 456 ral_debug(RAL_DBG_RX,
458 457 "ural_rxeof(): cr:%s(%d), flags:0x%x, rx_queued:%d",
459 458 usb_str_cr(req->bulk_completion_reason),
460 459 req->bulk_completion_reason,
461 460 req->bulk_cb_flags,
462 461 sc->rx_queued);
463 462
464 463 if (req->bulk_completion_reason != USB_CR_OK) {
465 464 sc->sc_rx_err++;
466 465 goto fail;
467 466 }
468 467
469 468 len = (uintptr_t)mp->b_wptr - (uintptr_t)mp->b_rptr;
470 469 rxbuf = (char *)mp->b_rptr;
471 470
472 471 if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) {
473 472 ral_debug(RAL_DBG_ERR,
474 473 "ural_rxeof(): xfer too short %d\n", len);
475 474 sc->sc_rx_err++;
476 475 goto fail;
477 476 }
478 477
479 478 /* rx descriptor is located at the end */
480 479 desc = (struct ural_rx_desc *)(rxbuf + len - RAL_RX_DESC_SIZE);
481 480
482 481 if ((LE_32(desc->flags) & RAL_RX_PHY_ERROR) ||
483 482 (LE_32(desc->flags) & RAL_RX_CRC_ERROR)) {
484 483 /*
485 484 * This should not happen since we did not request to receive
486 485 * those frames when we filled RAL_TXRX_CSR2.
487 486 */
488 487 ral_debug(RAL_DBG_ERR, "PHY or CRC error\n");
489 488 sc->sc_rx_err++;
490 489 goto fail;
491 490 }
492 491
493 492 pktlen = (LE_32(desc->flags) >> 16) & 0xfff;
494 493
495 494 if (pktlen > (len - RAL_RX_DESC_SIZE)) {
496 495 ral_debug(RAL_DBG_ERR,
497 496 "ural_rxeof(): pktlen mismatch <%d, %d>.\n", pktlen, len);
498 497 goto fail;
499 498 }
500 499
501 500 /* Strip trailing 802.11 MAC FCS. */
502 501 pktlen -= IEEE80211_CRC_LEN;
503 502
504 503 if ((m = allocb(pktlen, BPRI_MED)) == NULL) {
505 504 ral_debug(RAL_DBG_ERR,
506 505 "ural_rxeof(): allocate mblk failed.\n");
507 506 sc->sc_rx_nobuf++;
508 507 goto fail;
509 508 }
510 509
511 510 bcopy(rxbuf, m->b_rptr, pktlen);
512 511 m->b_wptr += pktlen;
513 512
514 513 wh = (struct ieee80211_frame *)m->b_rptr;
515 514 ni = ieee80211_find_rxnode(ic, wh);
516 515
517 516 /* send the frame to the 802.11 layer */
518 517 (void) ieee80211_input(ic, m, ni, desc->rssi, 0);
519 518
520 519 /* node is no longer needed */
521 520 ieee80211_free_node(ni);
522 521 fail:
523 522 mutex_enter(&sc->rx_lock);
524 523 sc->rx_queued--;
525 524 mutex_exit(&sc->rx_lock);
526 525
527 526 freemsg(mp);
528 527 usb_free_bulk_req(req);
529 528
530 529 if (RAL_IS_RUNNING(sc))
531 530 (void) ural_rx_trigger(sc);
532 531 }
533 532
534 533 /*
535 534 * Return the expected ack rate for a frame transmitted at rate `rate'.
536 535 * this should depend on the destination node basic rate set.
537 536 */
538 537 static int
539 538 ural_ack_rate(struct ieee80211com *ic, int rate)
540 539 {
541 540 switch (rate) {
542 541 /* CCK rates */
543 542 case 2:
544 543 return (2);
545 544 case 4:
546 545 case 11:
547 546 case 22:
548 547 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
549 548
550 549 /* OFDM rates */
551 550 case 12:
552 551 case 18:
553 552 return (12);
554 553 case 24:
555 554 case 36:
556 555 return (24);
557 556 case 48:
558 557 case 72:
559 558 case 96:
560 559 case 108:
561 560 return (48);
562 561 }
563 562
564 563 /* default to 1Mbps */
565 564 return (2);
566 565 }
567 566
568 567 /*
569 568 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
570 569 * The function automatically determines the operating mode depending on the
571 570 * given rate. `flags' indicates whether short preamble is in use or not.
572 571 */
573 572 static uint16_t
574 573 ural_txtime(int len, int rate, uint32_t flags)
575 574 {
576 575 uint16_t txtime;
577 576
578 577 if (RAL_RATE_IS_OFDM(rate)) {
579 578 /* IEEE Std 802.11a-1999, pp. 37 */
580 579 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
581 580 txtime = 16 + 4 + 4 * txtime + 6;
582 581 } else {
583 582 /* IEEE Std 802.11b-1999, pp. 28 */
584 583 txtime = (16 * len + rate - 1) / rate;
585 584 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
586 585 txtime += 72 + 24;
587 586 else
588 587 txtime += 144 + 48;
589 588 }
590 589 return (txtime);
591 590 }
592 591
593 592 static uint8_t
594 593 ural_plcp_signal(int rate)
595 594 {
596 595 switch (rate) {
597 596 /* CCK rates (returned values are device-dependent) */
598 597 case 2: return (0x0);
599 598 case 4: return (0x1);
600 599 case 11: return (0x2);
601 600 case 22: return (0x3);
602 601
603 602 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
604 603 case 12: return (0xb);
605 604 case 18: return (0xf);
606 605 case 24: return (0xa);
607 606 case 36: return (0xe);
608 607 case 48: return (0x9);
609 608 case 72: return (0xd);
610 609 case 96: return (0x8);
611 610 case 108: return (0xc);
612 611
613 612 /* unsupported rates (should not get there) */
614 613 default: return (0xff);
615 614 }
616 615 }
617 616
618 617 static void
619 618 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc,
620 619 uint32_t flags, int len, int rate)
621 620 {
622 621 struct ieee80211com *ic = &sc->sc_ic;
623 622 uint16_t plcp_length;
624 623 int remainder;
625 624
626 625 desc->flags = LE_32(flags);
627 626 desc->flags |= LE_32(RAL_TX_NEWSEQ);
628 627 desc->flags |= LE_32(len << 16);
629 628
630 629 desc->wme = LE_16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5));
631 630 desc->wme |= LE_16(RAL_IVOFFSET(sizeof (struct ieee80211_frame)));
632 631
633 632 /* setup PLCP fields */
634 633 desc->plcp_signal = ural_plcp_signal(rate);
635 634 desc->plcp_service = 4;
636 635
637 636 len += IEEE80211_CRC_LEN;
638 637 if (RAL_RATE_IS_OFDM(rate)) {
639 638 desc->flags |= LE_32(RAL_TX_OFDM);
640 639
641 640 plcp_length = len & 0xfff;
642 641 desc->plcp_length_hi = plcp_length >> 6;
643 642 desc->plcp_length_lo = plcp_length & 0x3f;
644 643 } else {
645 644 plcp_length = (16 * len + rate - 1) / rate;
646 645 if (rate == 22) {
647 646 remainder = (16 * len) % 22;
648 647 if (remainder != 0 && remainder < 7)
649 648 desc->plcp_service |= RAL_PLCP_LENGEXT;
650 649 }
651 650 desc->plcp_length_hi = plcp_length >> 8;
652 651 desc->plcp_length_lo = plcp_length & 0xff;
653 652
654 653 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
655 654 desc->plcp_signal |= 0x08;
656 655 }
657 656
658 657 desc->iv = 0;
659 658 desc->eiv = 0;
660 659 }
661 660
662 661 #define RAL_TX_TIMEOUT 5
663 662
664 663 static int
665 664 ural_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
666 665 {
667 666 struct ural_softc *sc = (struct ural_softc *)ic;
668 667 struct ural_tx_desc *desc;
669 668
670 669 struct ieee80211_frame *wh;
671 670 struct ieee80211_key *k;
672 671
673 672 uint16_t dur;
674 673 uint32_t flags = 0;
675 674 int rate, err = DDI_SUCCESS;
676 675
677 676 struct ieee80211_node *ni = NULL;
678 677 mblk_t *m, *m0;
679 678 int off, mblen, pktlen, xferlen;
680 679
681 680 /* discard packets while suspending or not inited */
682 681 if (!RAL_IS_RUNNING(sc)) {
683 682 freemsg(mp);
684 683 return (ENXIO);
685 684 }
686 685
687 686 mutex_enter(&sc->tx_lock);
688 687
689 688 if (sc->tx_queued > RAL_TX_LIST_COUNT) {
690 689 ral_debug(RAL_DBG_TX, "ural_send(): "
691 690 "no TX buffer available!\n");
692 691 if ((type & IEEE80211_FC0_TYPE_MASK) ==
693 692 IEEE80211_FC0_TYPE_DATA) {
694 693 sc->sc_need_sched = 1;
695 694 }
696 695 sc->sc_tx_nobuf++;
697 696 err = ENOMEM;
698 697 goto fail;
699 698 }
700 699
701 700 m = allocb(RAL_TXBUF_SIZE + RAL_TX_DESC_SIZE, BPRI_MED);
702 701 if (m == NULL) {
703 702 ral_debug(RAL_DBG_ERR, "ural_send(): can't alloc mblk.\n");
704 703 err = DDI_FAILURE;
705 704 goto fail;
706 705 }
707 706
708 707 m->b_rptr += RAL_TX_DESC_SIZE; /* skip TX descriptor */
709 708 m->b_wptr += RAL_TX_DESC_SIZE;
710 709
711 710 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
712 711 mblen = (uintptr_t)m0->b_wptr - (uintptr_t)m0->b_rptr;
713 712 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen);
714 713 off += mblen;
715 714 }
716 715 m->b_wptr += off;
717 716
718 717 wh = (struct ieee80211_frame *)m->b_rptr;
719 718
720 719 ni = ieee80211_find_txnode(ic, wh->i_addr1);
721 720 if (ni == NULL) {
722 721 err = DDI_FAILURE;
723 722 sc->sc_tx_err++;
724 723 freemsg(m);
725 724 goto fail;
726 725 }
727 726
728 727 if ((type & IEEE80211_FC0_TYPE_MASK) ==
729 728 IEEE80211_FC0_TYPE_DATA) {
730 729 (void) ieee80211_encap(ic, m, ni);
731 730 }
732 731
733 732 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
734 733 k = ieee80211_crypto_encap(ic, m);
735 734 if (k == NULL) {
736 735 sc->sc_tx_err++;
737 736 freemsg(m);
738 737 err = DDI_FAILURE;
739 738 goto fail;
740 739 }
741 740 /* packet header may have moved, reset our local pointer */
742 741 wh = (struct ieee80211_frame *)m->b_rptr;
743 742 }
744 743
745 744 m->b_rptr -= RAL_TX_DESC_SIZE; /* restore */
746 745 desc = (struct ural_tx_desc *)m->b_rptr;
747 746
748 747 if ((type & IEEE80211_FC0_TYPE_MASK) ==
749 748 IEEE80211_FC0_TYPE_DATA) { /* DATA */
750 749 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE)
751 750 rate = ic->ic_bss->in_rates.ir_rates[ic->ic_fixed_rate];
752 751 else
753 752 rate = ni->in_rates.ir_rates[ni->in_txrate];
754 753
755 754 rate &= IEEE80211_RATE_VAL;
756 755 if (rate <= 0) {
757 756 rate = 2; /* basic rate */
758 757 }
759 758
760 759 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
761 760 flags |= RAL_TX_ACK;
762 761 flags |= RAL_TX_RETRY(7);
763 762
764 763 dur = ural_txtime(RAL_ACK_SIZE, ural_ack_rate(ic, rate),
765 764 ic->ic_flags) + RAL_SIFS;
766 765 *(uint16_t *)(uintptr_t)wh->i_dur = LE_16(dur);
767 766 }
768 767 } else { /* MGMT */
769 768 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
770 769
771 770 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
772 771 flags |= RAL_TX_ACK;
773 772
774 773 dur = ural_txtime(RAL_ACK_SIZE, rate, ic->ic_flags)
775 774 + RAL_SIFS;
776 775 *(uint16_t *)(uintptr_t)wh->i_dur = LE_16(dur);
777 776
778 777 /* tell hardware to add timestamp for probe responses */
779 778 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
780 779 IEEE80211_FC0_TYPE_MGT &&
781 780 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
782 781 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
783 782 flags |= RAL_TX_TIMESTAMP;
784 783 }
785 784 }
786 785
787 786 pktlen = (uintptr_t)m->b_wptr - (uintptr_t)m->b_rptr - RAL_TX_DESC_SIZE;
788 787 ural_setup_tx_desc(sc, desc, flags, pktlen, rate);
789 788
790 789 /* align end on a 2-bytes boundary */
791 790 xferlen = (RAL_TX_DESC_SIZE + pktlen + 1) & ~1;
792 791
793 792 /*
794 793 * No space left in the last URB to store the extra 2 bytes, force
795 794 * sending of another URB.
796 795 */
797 796 if ((xferlen % 64) == 0)
798 797 xferlen += 2;
799 798
800 799 m->b_wptr = m->b_rptr + xferlen;
801 800
802 801 ral_debug(RAL_DBG_TX, "sending data frame len=%u rate=%u xfer len=%u\n",
803 802 pktlen, rate, xferlen);
804 803
805 804 (void) ural_tx_trigger(sc, m);
806 805
807 806 ic->ic_stats.is_tx_frags++;
808 807 ic->ic_stats.is_tx_bytes += pktlen;
809 808
810 809 fail:
811 810 if (ni != NULL)
812 811 ieee80211_free_node(ni);
813 812
814 813 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA ||
815 814 err == 0) {
816 815 freemsg(mp);
817 816 }
818 817
819 818 mutex_exit(&sc->tx_lock);
820 819
821 820 return (err);
822 821 }
823 822
824 823 static mblk_t *
825 824 ural_m_tx(void *arg, mblk_t *mp)
826 825 {
827 826 struct ural_softc *sc = (struct ural_softc *)arg;
828 827 struct ieee80211com *ic = &sc->sc_ic;
829 828 mblk_t *next;
830 829
831 830 /*
832 831 * No data frames go out unless we're associated; this
833 832 * should not happen as the 802.11 layer does not enable
834 833 * the xmit queue until we enter the RUN state.
835 834 */
836 835 if (ic->ic_state != IEEE80211_S_RUN) {
837 836 ral_debug(RAL_DBG_ERR, "ural_m_tx(): "
838 837 "discard, state %u\n", ic->ic_state);
839 838 freemsgchain(mp);
840 839 return (NULL);
841 840 }
842 841
843 842 while (mp != NULL) {
844 843 next = mp->b_next;
845 844 mp->b_next = NULL;
846 845 if (ural_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != DDI_SUCCESS) {
847 846 mp->b_next = next;
848 847 freemsgchain(mp);
849 848 return (NULL);
850 849 }
851 850 mp = next;
852 851 }
853 852 return (mp);
854 853 }
855 854
856 855 static void
857 856 ural_set_testmode(struct ural_softc *sc)
858 857 {
859 858 usb_ctrl_setup_t req;
860 859 usb_cr_t cr;
861 860 usb_cb_flags_t cf;
862 861 int err;
863 862
864 863 bzero(&req, sizeof (req));
865 864 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_HOST_TO_DEV;
866 865 req.bRequest = RAL_VENDOR_REQUEST;
867 866 req.wValue = 4;
868 867 req.wIndex = 1;
869 868 req.wLength = 0;
870 869 req.attrs = USB_ATTRS_NONE;
871 870
872 871 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL,
873 872 &cr, &cf, 0);
874 873
875 874 if (err != USB_SUCCESS) {
876 875 ral_debug(RAL_DBG_USB,
877 876 "ural_set_testmode(): could not set test mode:"
878 877 "cr:%s(%d), cf:%(x)\n",
879 878 usb_str_cr(cr), cr, cf);
880 879 }
881 880 }
882 881
883 882 static void
884 883 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len)
885 884 {
886 885 usb_ctrl_setup_t req;
887 886 usb_cr_t cr;
888 887 usb_cb_flags_t cf;
889 888 mblk_t *mp;
890 889 int err;
891 890
892 891 bzero(&req, sizeof (req));
893 892 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST;
894 893 req.bRequest = RAL_READ_EEPROM;
895 894 req.wValue = 0;
896 895 req.wIndex = addr;
897 896 req.wLength = (uint16_t)len;
898 897
899 898 mp = NULL;
900 899 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
901 900 &cr, &cf, 0);
902 901
903 902 if (err != USB_SUCCESS) {
904 903 ral_debug(RAL_DBG_USB,
905 904 "ural_eeprom_read(): could not read EEPROM:"
906 905 "cr:%s(%d), cf:(%x)\n",
907 906 usb_str_cr(cr), cr, cf);
908 907 return;
909 908 }
910 909
911 910 bcopy(mp->b_rptr, buf, len);
912 911
913 912 if (mp)
914 913 freemsg(mp);
915 914 }
916 915
917 916 static void
918 917 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
919 918 {
920 919 uint16_t tmp;
921 920 int ntries;
922 921
923 922 for (ntries = 0; ntries < 5; ntries++) {
924 923 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY))
925 924 break;
926 925 }
927 926 if (ntries == 5) {
928 927 ral_debug(RAL_DBG_ERR,
929 928 "ural_bbp_write(): could not write to BBP\n");
930 929 return;
931 930 }
932 931
933 932 tmp = reg << 8 | val;
934 933 ural_write(sc, RAL_PHY_CSR7, tmp);
935 934 }
936 935
937 936 static uint8_t
938 937 ural_bbp_read(struct ural_softc *sc, uint8_t reg)
939 938 {
940 939 uint16_t val;
941 940 int ntries;
942 941
943 942 val = RAL_BBP_WRITE | reg << 8;
944 943 ural_write(sc, RAL_PHY_CSR7, val);
945 944
946 945 for (ntries = 0; ntries < 5; ntries++) {
947 946 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY))
948 947 break;
949 948 }
950 949 if (ntries == 5) {
951 950 ral_debug(RAL_DBG_ERR, "ural_bbp_read(): could not read BBP\n");
952 951 return (0);
953 952 }
954 953
955 954 return (ural_read(sc, RAL_PHY_CSR7) & 0xff);
956 955 }
957 956
958 957 static void
959 958 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
960 959 {
961 960 uint32_t tmp;
962 961 int ntries;
963 962
964 963 for (ntries = 0; ntries < 5; ntries++) {
965 964 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY))
966 965 break;
967 966 }
968 967 if (ntries == 5) {
969 968 ral_debug(RAL_DBG_ERR,
970 969 "ural_rf_write(): could not write to RF\n");
971 970 return;
972 971 }
973 972
974 973 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xffff) << 2 | (reg & 0x3);
975 974 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff);
976 975 ural_write(sc, RAL_PHY_CSR10, tmp >> 16);
977 976
978 977 /* remember last written value in sc */
979 978 sc->rf_regs[reg] = val;
980 979
981 980 ral_debug(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);
982 981 }
983 982
984 983 /*
985 984 * Disable RF auto-tuning.
986 985 */
987 986 static void
988 987 ural_disable_rf_tune(struct ural_softc *sc)
989 988 {
990 989 uint32_t tmp;
991 990
992 991 if (sc->rf_rev != RAL_RF_2523) {
993 992 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE;
994 993 ural_rf_write(sc, RAL_RF1, tmp);
995 994 }
996 995
997 996 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE;
998 997 ural_rf_write(sc, RAL_RF3, tmp);
999 998
1000 999 ral_debug(RAL_DBG_HW, "disabling RF autotune\n");
1001 1000 }
1002 1001
1003 1002
1004 1003 static void
1005 1004 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c)
1006 1005 {
1007 1006 struct ieee80211com *ic = &sc->sc_ic;
1008 1007 uint8_t power, tmp;
1009 1008 uint_t i, chan;
1010 1009
1011 1010 chan = ieee80211_chan2ieee(ic, c);
1012 1011 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
1013 1012 return;
1014 1013
1015 1014 if (IEEE80211_IS_CHAN_2GHZ(c))
1016 1015 power = min(sc->txpow[chan - 1], 31);
1017 1016 else
1018 1017 power = 31;
1019 1018
1020 1019 /* adjust txpower using ifconfig settings */
1021 1020 power -= (100 - ic->ic_txpowlimit) / 8;
1022 1021
1023 1022 ral_debug(RAL_DBG_HW, "setting channel to %u, txpower to %u\n",
1024 1023 chan, power);
1025 1024
1026 1025 switch (sc->rf_rev) {
1027 1026 case RAL_RF_2522:
1028 1027 ural_rf_write(sc, RAL_RF1, 0x00814);
1029 1028 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]);
1030 1029 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1031 1030 break;
1032 1031
1033 1032 case RAL_RF_2523:
1034 1033 ural_rf_write(sc, RAL_RF1, 0x08804);
1035 1034 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]);
1036 1035 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044);
1037 1036 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1038 1037 break;
1039 1038
1040 1039 case RAL_RF_2524:
1041 1040 ural_rf_write(sc, RAL_RF1, 0x0c808);
1042 1041 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]);
1043 1042 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1044 1043 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1045 1044 break;
1046 1045
1047 1046 case RAL_RF_2525:
1048 1047 ural_rf_write(sc, RAL_RF1, 0x08808);
1049 1048 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]);
1050 1049 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1051 1050 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1052 1051
1053 1052 ural_rf_write(sc, RAL_RF1, 0x08808);
1054 1053 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]);
1055 1054 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1056 1055 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1057 1056 break;
1058 1057
1059 1058 case RAL_RF_2525E:
1060 1059 ural_rf_write(sc, RAL_RF1, 0x08808);
1061 1060 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]);
1062 1061 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1063 1062 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282);
1064 1063 break;
1065 1064
1066 1065 case RAL_RF_2526:
1067 1066 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]);
1068 1067 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
1069 1068 ural_rf_write(sc, RAL_RF1, 0x08804);
1070 1069
1071 1070 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]);
1072 1071 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1073 1072 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
1074 1073 break;
1075 1074
1076 1075 /* dual-band RF */
1077 1076 case RAL_RF_5222:
1078 1077 for (i = 0; ural_rf5222[i].chan != chan; i++) {
1079 1078 if (i > URAL_N(ural_rf5222)) break;
1080 1079 }
1081 1080
1082 1081 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1);
1083 1082 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2);
1084 1083 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1085 1084 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4);
1086 1085 break;
1087 1086 }
1088 1087
1089 1088 if (ic->ic_opmode != IEEE80211_M_MONITOR &&
1090 1089 ic->ic_state != IEEE80211_S_SCAN) {
1091 1090 /* set Japan filter bit for channel 14 */
1092 1091 tmp = ural_bbp_read(sc, 70);
1093 1092
1094 1093 tmp &= ~RAL_JAPAN_FILTER;
1095 1094 if (chan == 14)
1096 1095 tmp |= RAL_JAPAN_FILTER;
1097 1096
1098 1097 ural_bbp_write(sc, 70, tmp);
1099 1098
1100 1099 /* clear CRC errs */
1101 1100 (void) ural_read(sc, RAL_STA_CSR0);
1102 1101
1103 1102 drv_usecwait(10000);
1104 1103 ural_disable_rf_tune(sc);
1105 1104 }
1106 1105 }
1107 1106
1108 1107 /*
1109 1108 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF
1110 1109 * synchronization.
1111 1110 */
1112 1111 static void
1113 1112 ural_enable_tsf_sync(struct ural_softc *sc)
1114 1113 {
1115 1114 struct ieee80211com *ic = &sc->sc_ic;
1116 1115 uint16_t logcwmin, preload, tmp;
1117 1116
1118 1117 /* first, disable TSF synchronization */
1119 1118 ural_write(sc, RAL_TXRX_CSR19, 0);
1120 1119
1121 1120 tmp = (16 * ic->ic_bss->in_intval) << 4;
1122 1121 ural_write(sc, RAL_TXRX_CSR18, tmp);
1123 1122
1124 1123 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0;
1125 1124 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6;
1126 1125 tmp = logcwmin << 12 | preload;
1127 1126 ural_write(sc, RAL_TXRX_CSR20, tmp);
1128 1127
1129 1128 /* finally, enable TSF synchronization */
1130 1129 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN;
1131 1130 if (ic->ic_opmode == IEEE80211_M_STA)
1132 1131 tmp |= RAL_ENABLE_TSF_SYNC(1);
1133 1132 else
1134 1133 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR;
1135 1134 ural_write(sc, RAL_TXRX_CSR19, tmp);
1136 1135
1137 1136 ral_debug(RAL_DBG_HW, "enabling TSF synchronization\n");
1138 1137 }
1139 1138
1140 1139 /*
1141 1140 * This function can be called by ieee80211_set_shortslottime(). Refer to
1142 1141 * IEEE Std 802.11-1999 pp. 85 to know how these values are computed.
1143 1142 */
1144 1143 /* ARGSUSED */
1145 1144 static void
1146 1145 ural_update_slot(struct ieee80211com *ic, int onoff)
1147 1146 {
1148 1147 struct ural_softc *sc = (struct ural_softc *)ic;
1149 1148 uint16_t slottime, sifs, eifs;
1150 1149
1151 1150 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1152 1151 /* slottime = (onoff ? 9 : 20); */
1153 1152
1154 1153 /*
1155 1154 * These settings may sound a bit inconsistent but this is what the
1156 1155 * reference driver does.
1157 1156 */
1158 1157 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1159 1158 sifs = 16 - RAL_RXTX_TURNAROUND;
1160 1159 eifs = 364;
1161 1160 } else {
1162 1161 sifs = 10 - RAL_RXTX_TURNAROUND;
1163 1162 eifs = 64;
1164 1163 }
1165 1164
1166 1165 ural_write(sc, RAL_MAC_CSR10, slottime);
1167 1166 ural_write(sc, RAL_MAC_CSR11, sifs);
1168 1167 ural_write(sc, RAL_MAC_CSR12, eifs);
1169 1168 }
1170 1169
1171 1170 static void
1172 1171 ural_set_txpreamble(struct ural_softc *sc)
1173 1172 {
1174 1173 uint16_t tmp;
1175 1174
1176 1175 tmp = ural_read(sc, RAL_TXRX_CSR10);
1177 1176
1178 1177 tmp &= ~RAL_SHORT_PREAMBLE;
1179 1178 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1180 1179 tmp |= RAL_SHORT_PREAMBLE;
1181 1180
1182 1181 ural_write(sc, RAL_TXRX_CSR10, tmp);
1183 1182 }
1184 1183
1185 1184 static void
1186 1185 ural_set_basicrates(struct ural_softc *sc)
1187 1186 {
1188 1187 struct ieee80211com *ic = &sc->sc_ic;
1189 1188
1190 1189 /* update basic rate set */
1191 1190 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1192 1191 /* 11b basic rates: 1, 2Mbps */
1193 1192 ural_write(sc, RAL_TXRX_CSR11, 0x3);
1194 1193 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->in_chan)) {
1195 1194 /* 11a basic rates: 6, 12, 24Mbps */
1196 1195 ural_write(sc, RAL_TXRX_CSR11, 0x150);
1197 1196 } else {
1198 1197 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */
1199 1198 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
1200 1199 }
1201 1200 }
1202 1201
1203 1202 static void
1204 1203 ural_set_bssid(struct ural_softc *sc, uint8_t *bssid)
1205 1204 {
1206 1205 uint16_t tmp;
1207 1206
1208 1207 tmp = bssid[0] | bssid[1] << 8;
1209 1208 ural_write(sc, RAL_MAC_CSR5, tmp);
1210 1209
1211 1210 tmp = bssid[2] | bssid[3] << 8;
1212 1211 ural_write(sc, RAL_MAC_CSR6, tmp);
1213 1212
1214 1213 tmp = bssid[4] | bssid[5] << 8;
1215 1214 ural_write(sc, RAL_MAC_CSR7, tmp);
1216 1215
1217 1216 ral_debug(RAL_DBG_HW, "setting BSSID to " MACSTR "\n", MAC2STR(bssid));
1218 1217 }
1219 1218
1220 1219 static void
1221 1220 ural_set_macaddr(struct ural_softc *sc, uint8_t *addr)
1222 1221 {
1223 1222 uint16_t tmp;
1224 1223
1225 1224 tmp = addr[0] | addr[1] << 8;
1226 1225 ural_write(sc, RAL_MAC_CSR2, tmp);
1227 1226
1228 1227 tmp = addr[2] | addr[3] << 8;
1229 1228 ural_write(sc, RAL_MAC_CSR3, tmp);
1230 1229
1231 1230 tmp = addr[4] | addr[5] << 8;
1232 1231 ural_write(sc, RAL_MAC_CSR4, tmp);
1233 1232
1234 1233 ral_debug(RAL_DBG_HW,
1235 1234 "setting MAC address to " MACSTR "\n", MAC2STR(addr));
1236 1235 }
1237 1236
1238 1237 static void
1239 1238 ural_update_promisc(struct ural_softc *sc)
1240 1239 {
1241 1240 uint32_t tmp;
1242 1241
1243 1242 tmp = ural_read(sc, RAL_TXRX_CSR2);
1244 1243
1245 1244 tmp &= ~RAL_DROP_NOT_TO_ME;
1246 1245 if (!(sc->sc_rcr & RAL_RCR_PROMISC))
1247 1246 tmp |= RAL_DROP_NOT_TO_ME;
1248 1247
1249 1248 ural_write(sc, RAL_TXRX_CSR2, tmp);
1250 1249
1251 1250 ral_debug(RAL_DBG_HW, "%s promiscuous mode\n",
1252 1251 (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving");
1253 1252 }
1254 1253
1255 1254 static const char *
1256 1255 ural_get_rf(int rev)
1257 1256 {
1258 1257 switch (rev) {
1259 1258 case RAL_RF_2522: return ("RT2522");
1260 1259 case RAL_RF_2523: return ("RT2523");
1261 1260 case RAL_RF_2524: return ("RT2524");
1262 1261 case RAL_RF_2525: return ("RT2525");
1263 1262 case RAL_RF_2525E: return ("RT2525e");
1264 1263 case RAL_RF_2526: return ("RT2526");
1265 1264 case RAL_RF_5222: return ("RT5222");
1266 1265 default: return ("unknown");
1267 1266 }
1268 1267 }
1269 1268
1270 1269 static void
1271 1270 ural_read_eeprom(struct ural_softc *sc)
1272 1271 {
1273 1272 struct ieee80211com *ic = &sc->sc_ic;
1274 1273 uint16_t val;
1275 1274
1276 1275 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2);
1277 1276 val = LE_16(val);
1278 1277 sc->rf_rev = (val >> 11) & 0x7;
1279 1278 sc->hw_radio = (val >> 10) & 0x1;
1280 1279 sc->led_mode = (val >> 6) & 0x7;
1281 1280 sc->rx_ant = (val >> 4) & 0x3;
1282 1281 sc->tx_ant = (val >> 2) & 0x3;
1283 1282 sc->nb_ant = val & 0x3;
1284 1283
1285 1284 /* read MAC address */
1286 1285 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6);
1287 1286
1288 1287 /* read default values for BBP registers */
1289 1288 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16);
1290 1289
1291 1290 /* read Tx power for all b/g channels */
1292 1291 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14);
1293 1292 }
1294 1293
1295 1294 static int
1296 1295 ural_bbp_init(struct ural_softc *sc)
1297 1296 {
1298 1297 int i, ntries;
1299 1298
1300 1299 /* wait for BBP to be ready */
1301 1300 for (ntries = 0; ntries < 100; ntries++) {
1302 1301 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0)
1303 1302 break;
1304 1303 drv_usecwait(1000);
1305 1304 }
1306 1305 if (ntries == 100) {
1307 1306 ral_debug(RAL_DBG_ERR, "timeout waiting for BBP\n");
1308 1307 return (EIO);
1309 1308 }
1310 1309
1311 1310 /* initialize BBP registers to default values */
1312 1311 for (i = 0; i < URAL_N(ural_def_bbp); i++)
1313 1312 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
1314 1313
1315 1314 return (0);
1316 1315 }
1317 1316
1318 1317 static void
1319 1318 ural_set_txantenna(struct ural_softc *sc, int antenna)
1320 1319 {
1321 1320 uint16_t tmp;
1322 1321 uint8_t tx;
1323 1322
1324 1323 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK;
1325 1324 if (antenna == 1)
1326 1325 tx |= RAL_BBP_ANTA;
1327 1326 else if (antenna == 2)
1328 1327 tx |= RAL_BBP_ANTB;
1329 1328 else
1330 1329 tx |= RAL_BBP_DIVERSITY;
1331 1330
1332 1331 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */
1333 1332 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 ||
1334 1333 sc->rf_rev == RAL_RF_5222)
1335 1334 tx |= RAL_BBP_FLIPIQ;
1336 1335
1337 1336 ural_bbp_write(sc, RAL_BBP_TX, tx);
1338 1337
1339 1338 /* update values in PHY_CSR5 and PHY_CSR6 */
1340 1339 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7;
1341 1340 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));
1342 1341
1343 1342 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7;
1344 1343 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));
1345 1344 }
1346 1345
1347 1346 static void
1348 1347 ural_set_rxantenna(struct ural_softc *sc, int antenna)
1349 1348 {
1350 1349 uint8_t rx;
1351 1350
1352 1351 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK;
1353 1352 if (antenna == 1)
1354 1353 rx |= RAL_BBP_ANTA;
1355 1354 else if (antenna == 2)
1356 1355 rx |= RAL_BBP_ANTB;
1357 1356 else
1358 1357 rx |= RAL_BBP_DIVERSITY;
1359 1358
1360 1359 /* need to force no I/Q flip for RF 2525e and 2526 */
1361 1360 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526)
1362 1361 rx &= ~RAL_BBP_FLIPIQ;
1363 1362
1364 1363 ural_bbp_write(sc, RAL_BBP_RX, rx);
1365 1364 }
1366 1365
1367 1366 /*
1368 1367 * This function is called periodically (every 200ms) during scanning to
1369 1368 * switch from one channel to another.
1370 1369 */
1371 1370 static void
1372 1371 ural_next_scan(void *arg)
1373 1372 {
1374 1373 struct ural_softc *sc = arg;
1375 1374 struct ieee80211com *ic = &sc->sc_ic;
1376 1375
1377 1376 if (ic->ic_state == IEEE80211_S_SCAN)
1378 1377 ieee80211_next_scan(ic);
1379 1378 }
1380 1379
1381 1380 static int
1382 1381 ural_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1383 1382 {
1384 1383 struct ural_softc *sc = (struct ural_softc *)ic;
1385 1384 enum ieee80211_state ostate;
1386 1385 struct ieee80211_node *ni;
1387 1386 int err;
1388 1387
1389 1388 RAL_LOCK(sc);
1390 1389
1391 1390 ostate = ic->ic_state;
1392 1391
1393 1392 if (sc->sc_scan_id != 0) {
1394 1393 (void) untimeout(sc->sc_scan_id);
1395 1394 sc->sc_scan_id = 0;
1396 1395 }
1397 1396
1398 1397 if (sc->sc_amrr_id != 0) {
1399 1398 (void) untimeout(sc->sc_amrr_id);
1400 1399 sc->sc_amrr_id = 0;
1401 1400 }
1402 1401
1403 1402 switch (nstate) {
1404 1403 case IEEE80211_S_INIT:
1405 1404 if (ostate == IEEE80211_S_RUN) {
1406 1405 /* abort TSF synchronization */
1407 1406 ural_write(sc, RAL_TXRX_CSR19, 0);
1408 1407 /* force tx led to stop blinking */
1409 1408 ural_write(sc, RAL_MAC_CSR20, 0);
1410 1409 }
1411 1410 break;
1412 1411
1413 1412 case IEEE80211_S_SCAN:
1414 1413 ural_set_chan(sc, ic->ic_curchan);
1415 1414 sc->sc_scan_id = timeout(ural_next_scan, (void *)sc,
1416 1415 drv_usectohz(sc->dwelltime * 1000));
1417 1416 break;
1418 1417
1419 1418 case IEEE80211_S_AUTH:
1420 1419 ural_set_chan(sc, ic->ic_curchan);
1421 1420 break;
1422 1421
1423 1422 case IEEE80211_S_ASSOC:
1424 1423 ural_set_chan(sc, ic->ic_curchan);
1425 1424 break;
1426 1425
1427 1426 case IEEE80211_S_RUN:
1428 1427 ural_set_chan(sc, ic->ic_curchan);
1429 1428
1430 1429 ni = ic->ic_bss;
1431 1430
1432 1431 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1433 1432 ural_update_slot(ic, 1);
1434 1433 ural_set_txpreamble(sc);
1435 1434 ural_set_basicrates(sc);
1436 1435 ural_set_bssid(sc, ni->in_bssid);
1437 1436 }
1438 1437
1439 1438
1440 1439 /* make tx led blink on tx (controlled by ASIC) */
1441 1440 ural_write(sc, RAL_MAC_CSR20, 1);
1442 1441
1443 1442 if (ic->ic_opmode != IEEE80211_M_MONITOR)
1444 1443 ural_enable_tsf_sync(sc);
1445 1444
1446 1445 /* enable automatic rate adaptation in STA mode */
1447 1446 if (ic->ic_opmode == IEEE80211_M_STA &&
1448 1447 ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE)
1449 1448 ural_amrr_start(sc, ni);
1450 1449
1451 1450 break;
1452 1451 }
1453 1452
1454 1453 RAL_UNLOCK(sc);
1455 1454
1456 1455 err = sc->sc_newstate(ic, nstate, arg);
1457 1456 /*
1458 1457 * Finally, start any timers.
1459 1458 */
1460 1459 if (nstate == IEEE80211_S_RUN)
1461 1460 ieee80211_start_watchdog(ic, 1);
1462 1461
1463 1462 return (err);
1464 1463 }
1465 1464
1466 1465
1467 1466
1468 1467 static void
1469 1468 ural_close_pipes(struct ural_softc *sc)
1470 1469 {
1471 1470 usb_flags_t flags = USB_FLAGS_SLEEP;
1472 1471
1473 1472 if (sc->sc_rx_pipeh != NULL) {
1474 1473 usb_pipe_reset(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0);
1475 1474 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0);
1476 1475 sc->sc_rx_pipeh = NULL;
1477 1476 }
1478 1477
1479 1478 if (sc->sc_tx_pipeh != NULL) {
1480 1479 usb_pipe_reset(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0);
1481 1480 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0);
1482 1481 sc->sc_tx_pipeh = NULL;
1483 1482 }
1484 1483 }
1485 1484
1486 1485 static int
1487 1486 ural_open_pipes(struct ural_softc *sc)
1488 1487 {
1489 1488 usb_ep_data_t *ep_node;
1490 1489 usb_pipe_policy_t policy;
1491 1490 int err;
1492 1491
1493 1492 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0,
1494 1493 USB_EP_ATTR_BULK, USB_EP_DIR_OUT);
1495 1494
1496 1495 bzero(&policy, sizeof (usb_pipe_policy_t));
1497 1496 policy.pp_max_async_reqs = RAL_TX_LIST_COUNT;
1498 1497
1499 1498 if ((err = usb_pipe_open(sc->sc_dev,
1500 1499 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP,
1501 1500 &sc->sc_tx_pipeh)) != USB_SUCCESS) {
1502 1501 ral_debug(RAL_DBG_ERR,
1503 1502 "ural_open_pipes(): %x failed to open tx pipe\n", err);
1504 1503 goto fail;
1505 1504 }
1506 1505
1507 1506 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0,
1508 1507 USB_EP_ATTR_BULK, USB_EP_DIR_IN);
1509 1508
1510 1509 bzero(&policy, sizeof (usb_pipe_policy_t));
1511 1510 policy.pp_max_async_reqs = RAL_RX_LIST_COUNT + 32;
1512 1511
1513 1512 if ((err = usb_pipe_open(sc->sc_dev,
1514 1513 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP,
1515 1514 &sc->sc_rx_pipeh)) != USB_SUCCESS) {
1516 1515 ral_debug(RAL_DBG_ERR,
1517 1516 "ural_open_pipes(): %x failed to open rx pipe\n", err);
1518 1517 goto fail;
1519 1518 }
1520 1519
1521 1520 return (USB_SUCCESS);
1522 1521
1523 1522 fail:
1524 1523 if (sc->sc_rx_pipeh != NULL) {
1525 1524 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh,
1526 1525 USB_FLAGS_SLEEP, NULL, 0);
1527 1526 sc->sc_rx_pipeh = NULL;
1528 1527 }
1529 1528
1530 1529 if (sc->sc_tx_pipeh != NULL) {
1531 1530 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh,
1532 1531 USB_FLAGS_SLEEP, NULL, 0);
1533 1532 sc->sc_tx_pipeh = NULL;
1534 1533 }
1535 1534
1536 1535 return (USB_FAILURE);
1537 1536 }
1538 1537
1539 1538 static int
1540 1539 ural_tx_trigger(struct ural_softc *sc, mblk_t *mp)
1541 1540 {
1542 1541 usb_bulk_req_t *req;
1543 1542 int err;
1544 1543
1545 1544 sc->sc_tx_timer = RAL_TX_TIMEOUT;
1546 1545
1547 1546 req = usb_alloc_bulk_req(sc->sc_dev, 0, USB_FLAGS_SLEEP);
1548 1547 if (req == NULL) {
1549 1548 ral_debug(RAL_DBG_ERR,
1550 1549 "ural_tx_trigger(): failed to allocate req");
1551 1550 freemsg(mp);
1552 1551 return (-1);
1553 1552 }
1554 1553
1555 1554 req->bulk_len = (uintptr_t)mp->b_wptr - (uintptr_t)mp->b_rptr;
1556 1555 req->bulk_data = mp;
1557 1556 req->bulk_client_private = (usb_opaque_t)sc;
1558 1557 req->bulk_timeout = RAL_TX_TIMEOUT;
1559 1558 req->bulk_attributes = USB_ATTRS_AUTOCLEARING;
1560 1559 req->bulk_cb = ural_txeof;
1561 1560 req->bulk_exc_cb = ural_txeof;
1562 1561 req->bulk_completion_reason = 0;
1563 1562 req->bulk_cb_flags = 0;
1564 1563
1565 1564 if ((err = usb_pipe_bulk_xfer(sc->sc_tx_pipeh, req, 0))
1566 1565 != USB_SUCCESS) {
1567 1566
1568 1567 ral_debug(RAL_DBG_ERR, "ural_tx_trigger(): "
1569 1568 "failed to do tx xfer, %d", err);
1570 1569 usb_free_bulk_req(req);
1571 1570 return (-1);
1572 1571 }
1573 1572
1574 1573 sc->tx_queued++;
1575 1574
1576 1575 return (0);
1577 1576 }
1578 1577
1579 1578 static int
1580 1579 ural_rx_trigger(struct ural_softc *sc)
1581 1580 {
1582 1581 usb_bulk_req_t *req;
1583 1582 int err;
1584 1583
1585 1584 req = usb_alloc_bulk_req(sc->sc_dev, RAL_RXBUF_SIZE, USB_FLAGS_SLEEP);
1586 1585 if (req == NULL) {
1587 1586 ral_debug(RAL_DBG_ERR,
1588 1587 "ural_rx_trigger(): failed to allocate req");
1589 1588 return (-1);
1590 1589 }
1591 1590
1592 1591 req->bulk_len = RAL_RXBUF_SIZE;
1593 1592 req->bulk_client_private = (usb_opaque_t)sc;
1594 1593 req->bulk_timeout = 0;
1595 1594 req->bulk_attributes = USB_ATTRS_SHORT_XFER_OK
1596 1595 | USB_ATTRS_AUTOCLEARING;
1597 1596 req->bulk_cb = ural_rxeof;
1598 1597 req->bulk_exc_cb = ural_rxeof;
1599 1598 req->bulk_completion_reason = 0;
1600 1599 req->bulk_cb_flags = 0;
1601 1600
1602 1601 err = usb_pipe_bulk_xfer(sc->sc_rx_pipeh, req, 0);
1603 1602
1604 1603 if (err != USB_SUCCESS) {
1605 1604 ral_debug(RAL_DBG_ERR, "ural_rx_trigger(): "
1606 1605 "failed to do rx xfer, %d", err);
1607 1606 usb_free_bulk_req(req);
1608 1607
1609 1608 return (-1);
1610 1609 }
1611 1610
1612 1611 mutex_enter(&sc->rx_lock);
1613 1612 sc->rx_queued++;
1614 1613 mutex_exit(&sc->rx_lock);
1615 1614
1616 1615 return (0);
1617 1616 }
1618 1617
1619 1618 static void
1620 1619 ural_init_tx_queue(struct ural_softc *sc)
1621 1620 {
1622 1621 sc->tx_queued = 0;
1623 1622 }
1624 1623
1625 1624 static int
1626 1625 ural_init_rx_queue(struct ural_softc *sc)
1627 1626 {
1628 1627 int i;
1629 1628
1630 1629 sc->rx_queued = 0;
1631 1630
1632 1631 for (i = 0; i < RAL_RX_LIST_COUNT; i++) {
1633 1632 if (ural_rx_trigger(sc) != 0) {
1634 1633 return (USB_FAILURE);
1635 1634 }
1636 1635 }
1637 1636
1638 1637 return (USB_SUCCESS);
1639 1638 }
1640 1639
1641 1640 static void
1642 1641 ural_stop(struct ural_softc *sc)
1643 1642 {
1644 1643 struct ieee80211com *ic = &sc->sc_ic;
1645 1644
1646 1645 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1647 1646 ieee80211_stop_watchdog(ic); /* stop the watchdog */
1648 1647
1649 1648 RAL_LOCK(sc);
1650 1649
1651 1650 sc->sc_tx_timer = 0;
1652 1651 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
1653 1652
1654 1653 /* disable Rx */
1655 1654 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);
1656 1655
1657 1656 /* reset ASIC and BBP (but won't reset MAC registers!) */
1658 1657 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);
1659 1658 ural_write(sc, RAL_MAC_CSR1, 0);
1660 1659
1661 1660 ural_close_pipes(sc);
1662 1661
1663 1662 RAL_UNLOCK(sc);
1664 1663 }
1665 1664
1666 1665 static int
1667 1666 ural_init(struct ural_softc *sc)
1668 1667 {
1669 1668 struct ieee80211com *ic = &sc->sc_ic;
1670 1669 uint16_t tmp;
1671 1670 int i, ntries;
1672 1671
1673 1672 ural_set_testmode(sc);
1674 1673 ural_write(sc, 0x308, 0x00f0); /* magic */
1675 1674
1676 1675 ural_stop(sc);
1677 1676
1678 1677 /* initialize MAC registers to default values */
1679 1678 for (i = 0; i < URAL_N(ural_def_mac); i++)
1680 1679 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
1681 1680
1682 1681 /* wait for BBP and RF to wake up (this can take a long time!) */
1683 1682 for (ntries = 0; ntries < 100; ntries++) {
1684 1683 tmp = ural_read(sc, RAL_MAC_CSR17);
1685 1684 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) ==
1686 1685 (RAL_BBP_AWAKE | RAL_RF_AWAKE))
1687 1686 break;
1688 1687 drv_usecwait(1000);
1689 1688 }
1690 1689 if (ntries == 100) {
1691 1690 ral_debug(RAL_DBG_ERR,
1692 1691 "ural_init(): timeout waiting for BBP/RF to wakeup\n");
1693 1692 goto fail;
1694 1693 }
1695 1694
1696 1695 /* we're ready! */
1697 1696 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);
1698 1697
1699 1698 /* set basic rate set (will be updated later) */
1700 1699 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
1701 1700
1702 1701 if (ural_bbp_init(sc) != 0)
1703 1702 goto fail;
1704 1703
1705 1704 /* set default BSS channel */
1706 1705 ural_set_chan(sc, ic->ic_curchan);
1707 1706
1708 1707 /* clear statistic registers (STA_CSR0 to STA_CSR10) */
1709 1708 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta));
1710 1709
1711 1710 ural_set_txantenna(sc, sc->tx_ant);
1712 1711 ural_set_rxantenna(sc, sc->rx_ant);
1713 1712
1714 1713 ural_set_macaddr(sc, ic->ic_macaddr);
1715 1714
1716 1715 if (ural_open_pipes(sc) != USB_SUCCESS) {
1717 1716 ral_debug(RAL_DBG_ERR, "ural_init(): "
1718 1717 "could not open pipes.\n");
1719 1718 goto fail;
1720 1719 }
1721 1720
1722 1721 ural_init_tx_queue(sc);
1723 1722
1724 1723 if (ural_init_rx_queue(sc) != USB_SUCCESS)
1725 1724 goto fail;
1726 1725
1727 1726 /* kick Rx */
1728 1727 tmp = RAL_DROP_PHY | RAL_DROP_CRC;
1729 1728 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1730 1729 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION;
1731 1730 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
1732 1731 tmp |= RAL_DROP_TODS;
1733 1732 if (!(sc->sc_rcr & RAL_RCR_PROMISC))
1734 1733 tmp |= RAL_DROP_NOT_TO_ME;
1735 1734 }
1736 1735 ural_write(sc, RAL_TXRX_CSR2, tmp);
1737 1736 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */
1738 1737
1739 1738 return (DDI_SUCCESS);
1740 1739 fail:
1741 1740 ural_stop(sc);
1742 1741 return (EIO);
1743 1742 }
1744 1743
1745 1744 static int
1746 1745 ural_disconnect(dev_info_t *devinfo)
1747 1746 {
1748 1747 struct ural_softc *sc;
1749 1748 struct ieee80211com *ic;
1750 1749
1751 1750 /*
1752 1751 * We can't call ural_stop() here, since the hardware is removed,
1753 1752 * we can't access the register anymore.
1754 1753 */
1755 1754 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo));
1756 1755 ASSERT(sc != NULL);
1757 1756
1758 1757 if (!RAL_IS_RUNNING(sc)) /* different device or not inited */
1759 1758 return (DDI_SUCCESS);
1760 1759
1761 1760 ic = &sc->sc_ic;
1762 1761 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1763 1762 ieee80211_stop_watchdog(ic); /* stop the watchdog */
1764 1763
1765 1764 RAL_LOCK(sc);
1766 1765
1767 1766 sc->sc_tx_timer = 0;
1768 1767 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
1769 1768
1770 1769 ural_close_pipes(sc);
1771 1770
1772 1771 RAL_UNLOCK(sc);
1773 1772
1774 1773 return (DDI_SUCCESS);
1775 1774 }
1776 1775
1777 1776 static int
1778 1777 ural_reconnect(dev_info_t *devinfo)
1779 1778 {
1780 1779 struct ural_softc *sc;
1781 1780 int err;
1782 1781
1783 1782 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo));
1784 1783 ASSERT(sc != NULL);
1785 1784
1786 1785 /* check device changes after disconnect */
1787 1786 if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1,
1788 1787 USB_CHK_BASIC | USB_CHK_CFG, NULL) != USB_SUCCESS) {
1789 1788 ral_debug(RAL_DBG_ERR, "different device connected\n");
1790 1789 return (DDI_FAILURE);
1791 1790 }
1792 1791
1793 1792 err = ural_init(sc);
1794 1793
1795 1794 return (err);
1796 1795 }
1797 1796
1798 1797 static void
1799 1798 ural_resume(struct ural_softc *sc)
1800 1799 {
1801 1800 /* check device changes after suspend */
1802 1801 if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1,
1803 1802 USB_CHK_BASIC | USB_CHK_CFG, NULL) != USB_SUCCESS) {
1804 1803 ral_debug(RAL_DBG_ERR, "no or different device connected\n");
1805 1804 return;
1806 1805 }
1807 1806
1808 1807 (void) ural_init(sc);
1809 1808 }
1810 1809
1811 1810 #define URAL_AMRR_MIN_SUCCESS_THRESHOLD 1
1812 1811 #define URAL_AMRR_MAX_SUCCESS_THRESHOLD 10
1813 1812
1814 1813 /*
1815 1814 * Naive implementation of the Adaptive Multi Rate Retry algorithm:
1816 1815 * "IEEE 802.11 Rate Adaptation: A Practical Approach"
1817 1816 * Mathieu Lacage, Hossein Manshaei, Thierry Turletti
1818 1817 * INRIA Sophia - Projet Planete
1819 1818 * http://www-sop.inria.fr/rapports/sophia/RR-5208.html
1820 1819 *
1821 1820 * This algorithm is particularly well suited for ural since it does not
1822 1821 * require per-frame retry statistics. Note however that since h/w does
1823 1822 * not provide per-frame stats, we can't do per-node rate adaptation and
1824 1823 * thus automatic rate adaptation is only enabled in STA operating mode.
1825 1824 */
1826 1825 #define is_success(amrr) \
1827 1826 ((amrr)->retrycnt < (amrr)->txcnt / 10)
1828 1827 #define is_failure(amrr) \
1829 1828 ((amrr)->retrycnt > (amrr)->txcnt / 3)
1830 1829 #define is_enough(amrr) \
1831 1830 ((amrr)->txcnt > 10)
1832 1831 #define is_min_rate(ni) \
1833 1832 ((ni)->in_txrate == 0)
1834 1833 #define is_max_rate(ni) \
1835 1834 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1)
1836 1835 #define increase_rate(ni) \
1837 1836 ((ni)->in_txrate++)
1838 1837 #define decrease_rate(ni) \
1839 1838 ((ni)->in_txrate--)
1840 1839 #define reset_cnt(amrr) do { \
1841 1840 (amrr)->txcnt = (amrr)->retrycnt = 0; \
1842 1841 _NOTE(CONSTCOND) \
1843 1842 } while (/* CONSTCOND */0)
1844 1843
1845 1844 static void
1846 1845 ural_ratectl(struct ural_amrr *amrr, struct ieee80211_node *ni)
1847 1846 {
1848 1847 int need_change = 0;
1849 1848
1850 1849 if (is_success(amrr) && is_enough(amrr)) {
1851 1850 amrr->success++;
1852 1851 if (amrr->success >= amrr->success_threshold &&
1853 1852 !is_max_rate(ni)) {
1854 1853 amrr->recovery = 1;
1855 1854 amrr->success = 0;
1856 1855 increase_rate(ni);
1857 1856 need_change = 1;
1858 1857 } else {
1859 1858 amrr->recovery = 0;
1860 1859 }
1861 1860 } else if (is_failure(amrr)) {
1862 1861 amrr->success = 0;
1863 1862 if (!is_min_rate(ni)) {
1864 1863 if (amrr->recovery) {
1865 1864 amrr->success_threshold *= 2;
1866 1865 if (amrr->success_threshold >
1867 1866 URAL_AMRR_MAX_SUCCESS_THRESHOLD)
1868 1867 amrr->success_threshold =
1869 1868 URAL_AMRR_MAX_SUCCESS_THRESHOLD;
1870 1869 } else {
1871 1870 amrr->success_threshold =
1872 1871 URAL_AMRR_MIN_SUCCESS_THRESHOLD;
1873 1872 }
1874 1873 decrease_rate(ni);
1875 1874 need_change = 1;
1876 1875 }
1877 1876 amrr->recovery = 0; /* original paper was incorrect */
1878 1877 }
1879 1878
1880 1879 if (is_enough(amrr) || need_change)
1881 1880 reset_cnt(amrr);
1882 1881 }
1883 1882
1884 1883 static void
1885 1884 ural_amrr_timeout(void *arg)
1886 1885 {
1887 1886 struct ural_softc *sc = (struct ural_softc *)arg;
1888 1887 struct ural_amrr *amrr = &sc->amrr;
1889 1888
1890 1889 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta));
1891 1890
1892 1891 /* count TX retry-fail as Tx errors */
1893 1892 sc->sc_tx_err += sc->sta[9];
1894 1893 sc->sc_tx_retries += (sc->sta[7] + sc->sta[8]);
1895 1894
1896 1895 amrr->retrycnt =
1897 1896 sc->sta[7] + /* TX one-retry ok count */
1898 1897 sc->sta[8] + /* TX more-retry ok count */
1899 1898 sc->sta[9]; /* TX retry-fail count */
1900 1899
1901 1900 amrr->txcnt =
1902 1901 amrr->retrycnt +
1903 1902 sc->sta[6]; /* TX no-retry ok count */
1904 1903
1905 1904 ural_ratectl(amrr, sc->sc_ic.ic_bss);
1906 1905
1907 1906 sc->sc_amrr_id = timeout(ural_amrr_timeout, (void *)sc,
1908 1907 drv_usectohz(1000 * 1000)); /* 1 second */
1909 1908 }
1910 1909
1911 1910
1912 1911 static void
1913 1912 ural_amrr_start(struct ural_softc *sc, struct ieee80211_node *ni)
1914 1913 {
1915 1914 struct ural_amrr *amrr = &sc->amrr;
1916 1915 int i;
1917 1916
1918 1917 /* clear statistic registers (STA_CSR0 to STA_CSR10) */
1919 1918 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta));
1920 1919
1921 1920 amrr->success = 0;
1922 1921 amrr->recovery = 0;
1923 1922 amrr->txcnt = amrr->retrycnt = 0;
1924 1923 amrr->success_threshold = URAL_AMRR_MIN_SUCCESS_THRESHOLD;
1925 1924
1926 1925 /* set rate to some reasonable initial value */
1927 1926 for (i = ni->in_rates.ir_nrates - 1;
1928 1927 i > 0 && (ni->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72;
1929 1928 i--) {
1930 1929 }
1931 1930
1932 1931 ni->in_txrate = i;
1933 1932
1934 1933 sc->sc_amrr_id = timeout(ural_amrr_timeout, (void *)sc,
1935 1934 drv_usectohz(1000 * 1000)); /* 1 second */
1936 1935 }
1937 1936
1938 1937 void
1939 1938 ural_watchdog(void *arg)
1940 1939 {
1941 1940 struct ural_softc *sc = arg;
1942 1941 struct ieee80211com *ic = &sc->sc_ic;
1943 1942 int ntimer = 0;
1944 1943
1945 1944 RAL_LOCK(sc);
1946 1945 ic->ic_watchdog_timer = 0;
1947 1946
1948 1947 if (!RAL_IS_RUNNING(sc)) {
1949 1948 RAL_UNLOCK(sc);
1950 1949 return;
1951 1950 }
1952 1951
1953 1952 if (sc->sc_tx_timer > 0) {
1954 1953 if (--sc->sc_tx_timer == 0) {
1955 1954 ral_debug(RAL_DBG_ERR, "tx timer timeout\n");
1956 1955 RAL_UNLOCK(sc);
1957 1956 (void) ural_init(sc);
1958 1957 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1959 1958 return;
1960 1959 }
1961 1960 }
1962 1961
1963 1962 if (ic->ic_state == IEEE80211_S_RUN)
1964 1963 ntimer = 1;
1965 1964
1966 1965 RAL_UNLOCK(sc);
1967 1966
1968 1967 ieee80211_watchdog(ic);
1969 1968
1970 1969 if (ntimer)
1971 1970 ieee80211_start_watchdog(ic, ntimer);
1972 1971 }
1973 1972
1974 1973 static int
1975 1974 ural_m_start(void *arg)
1976 1975 {
1977 1976 struct ural_softc *sc = (struct ural_softc *)arg;
1978 1977 int err;
1979 1978
1980 1979 /*
1981 1980 * initialize RT2500USB hardware
1982 1981 */
1983 1982 err = ural_init(sc);
1984 1983 if (err != DDI_SUCCESS) {
1985 1984 ral_debug(RAL_DBG_ERR, "device configuration failed\n");
1986 1985 goto fail;
1987 1986 }
1988 1987 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */
1989 1988 return (err);
1990 1989
1991 1990 fail:
1992 1991 ural_stop(sc);
1993 1992 return (err);
1994 1993 }
1995 1994
1996 1995 static void
1997 1996 ural_m_stop(void *arg)
1998 1997 {
1999 1998 struct ural_softc *sc = (struct ural_softc *)arg;
2000 1999
2001 2000 (void) ural_stop(sc);
2002 2001 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
2003 2002 }
2004 2003
2005 2004 static int
2006 2005 ural_m_unicst(void *arg, const uint8_t *macaddr)
2007 2006 {
2008 2007 struct ural_softc *sc = (struct ural_softc *)arg;
2009 2008 struct ieee80211com *ic = &sc->sc_ic;
2010 2009
2011 2010 ral_debug(RAL_DBG_MSG, "ural_m_unicst(): " MACSTR "\n",
2012 2011 MAC2STR(macaddr));
2013 2012
2014 2013 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr);
2015 2014 (void) ural_set_macaddr(sc, (uint8_t *)macaddr);
2016 2015 (void) ural_init(sc);
2017 2016
2018 2017 return (0);
2019 2018 }
2020 2019
2021 2020 /*ARGSUSED*/
2022 2021 static int
2023 2022 ural_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
2024 2023 {
2025 2024 return (0);
2026 2025 }
2027 2026
2028 2027 static int
2029 2028 ural_m_promisc(void *arg, boolean_t on)
2030 2029 {
2031 2030 struct ural_softc *sc = (struct ural_softc *)arg;
2032 2031
2033 2032 if (on) {
2034 2033 sc->sc_rcr |= RAL_RCR_PROMISC;
2035 2034 sc->sc_rcr |= RAL_RCR_MULTI;
2036 2035 } else {
2037 2036 sc->sc_rcr &= ~RAL_RCR_PROMISC;
2038 2037 sc->sc_rcr &= ~RAL_RCR_PROMISC;
2039 2038 }
2040 2039
2041 2040 ural_update_promisc(sc);
2042 2041 return (0);
2043 2042 }
2044 2043
2045 2044 /*
2046 2045 * callback functions for /get/set properties
2047 2046 */
2048 2047 static int
2049 2048 ural_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2050 2049 uint_t wldp_length, const void *wldp_buf)
2051 2050 {
2052 2051 struct ural_softc *sc = (struct ural_softc *)arg;
2053 2052 struct ieee80211com *ic = &sc->sc_ic;
2054 2053 int err;
2055 2054
2056 2055 err = ieee80211_setprop(ic, pr_name, wldp_pr_num,
2057 2056 wldp_length, wldp_buf);
2058 2057 RAL_LOCK(sc);
2059 2058 if (err == ENETRESET) {
2060 2059 if (RAL_IS_RUNNING(sc)) {
2061 2060 RAL_UNLOCK(sc);
2062 2061 (void) ural_init(sc);
2063 2062 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2064 2063 RAL_LOCK(sc);
2065 2064 }
2066 2065 err = 0;
2067 2066 }
2068 2067 RAL_UNLOCK(sc);
2069 2068
2070 2069 return (err);
2071 2070 }
2072 2071
2073 2072 static int
2074 2073 ural_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2075 2074 uint_t wldp_length, void *wldp_buf)
2076 2075 {
2077 2076 struct ural_softc *sc = (struct ural_softc *)arg;
2078 2077 int err;
2079 2078
2080 2079 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2081 2080 wldp_length, wldp_buf);
2082 2081
2083 2082 return (err);
2084 2083 }
2085 2084
2086 2085 static void
2087 2086 ural_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2088 2087 mac_prop_info_handle_t mph)
2089 2088 {
2090 2089 struct ural_softc *sc = (struct ural_softc *)arg;
2091 2090
2092 2091 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, mph);
2093 2092 }
2094 2093
2095 2094 static void
2096 2095 ural_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2097 2096 {
2098 2097 struct ural_softc *sc = (struct ural_softc *)arg;
2099 2098 struct ieee80211com *ic = &sc->sc_ic;
2100 2099 int err;
2101 2100
2102 2101 err = ieee80211_ioctl(ic, wq, mp);
2103 2102 RAL_LOCK(sc);
2104 2103 if (err == ENETRESET) {
2105 2104 if (RAL_IS_RUNNING(sc)) {
2106 2105 RAL_UNLOCK(sc);
2107 2106 (void) ural_init(sc);
2108 2107 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2109 2108 RAL_LOCK(sc);
2110 2109 }
2111 2110 }
2112 2111 RAL_UNLOCK(sc);
2113 2112 }
2114 2113
2115 2114 static int
2116 2115 ural_m_stat(void *arg, uint_t stat, uint64_t *val)
2117 2116 {
2118 2117 struct ural_softc *sc = (struct ural_softc *)arg;
2119 2118 ieee80211com_t *ic = &sc->sc_ic;
2120 2119 ieee80211_node_t *ni = ic->ic_bss;
2121 2120 struct ieee80211_rateset *rs = &ni->in_rates;
2122 2121
2123 2122 RAL_LOCK(sc);
2124 2123 switch (stat) {
2125 2124 case MAC_STAT_IFSPEED:
2126 2125 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
2127 2126 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
2128 2127 : ic->ic_fixed_rate) / 2 * 1000000;
2129 2128 break;
2130 2129 case MAC_STAT_NOXMTBUF:
2131 2130 *val = sc->sc_tx_nobuf;
2132 2131 break;
2133 2132 case MAC_STAT_NORCVBUF:
2134 2133 *val = sc->sc_rx_nobuf;
2135 2134 break;
2136 2135 case MAC_STAT_IERRORS:
2137 2136 *val = sc->sc_rx_err;
2138 2137 break;
2139 2138 case MAC_STAT_RBYTES:
2140 2139 *val = ic->ic_stats.is_rx_bytes;
2141 2140 break;
2142 2141 case MAC_STAT_IPACKETS:
2143 2142 *val = ic->ic_stats.is_rx_frags;
2144 2143 break;
2145 2144 case MAC_STAT_OBYTES:
2146 2145 *val = ic->ic_stats.is_tx_bytes;
2147 2146 break;
2148 2147 case MAC_STAT_OPACKETS:
2149 2148 *val = ic->ic_stats.is_tx_frags;
2150 2149 break;
2151 2150 case MAC_STAT_OERRORS:
2152 2151 case WIFI_STAT_TX_FAILED:
2153 2152 *val = sc->sc_tx_err;
2154 2153 break;
2155 2154 case WIFI_STAT_TX_RETRANS:
2156 2155 *val = sc->sc_tx_retries;
2157 2156 break;
2158 2157 case WIFI_STAT_FCS_ERRORS:
2159 2158 case WIFI_STAT_WEP_ERRORS:
2160 2159 case WIFI_STAT_TX_FRAGS:
2161 2160 case WIFI_STAT_MCAST_TX:
2162 2161 case WIFI_STAT_RTS_SUCCESS:
2163 2162 case WIFI_STAT_RTS_FAILURE:
2164 2163 case WIFI_STAT_ACK_FAILURE:
2165 2164 case WIFI_STAT_RX_FRAGS:
2166 2165 case WIFI_STAT_MCAST_RX:
2167 2166 case WIFI_STAT_RX_DUPS:
2168 2167 RAL_UNLOCK(sc);
2169 2168 return (ieee80211_stat(ic, stat, val));
2170 2169 default:
2171 2170 RAL_UNLOCK(sc);
2172 2171 return (ENOTSUP);
2173 2172 }
2174 2173 RAL_UNLOCK(sc);
2175 2174
2176 2175 return (0);
2177 2176 }
2178 2177
2179 2178
2180 2179 static int
2181 2180 ural_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2182 2181 {
2183 2182 struct ural_softc *sc;
2184 2183 struct ieee80211com *ic;
2185 2184 int err, i;
2186 2185 int instance;
2187 2186
2188 2187 char strbuf[32];
2189 2188
2190 2189 wifi_data_t wd = { 0 };
2191 2190 mac_register_t *macp;
2192 2191
2193 2192 switch (cmd) {
2194 2193 case DDI_ATTACH:
2195 2194 break;
2196 2195 case DDI_RESUME:
2197 2196 sc = ddi_get_soft_state(ural_soft_state_p,
2198 2197 ddi_get_instance(devinfo));
2199 2198 ASSERT(sc != NULL);
2200 2199 ural_resume(sc);
2201 2200 return (DDI_SUCCESS);
2202 2201 default:
2203 2202 return (DDI_FAILURE);
2204 2203 }
2205 2204
2206 2205 instance = ddi_get_instance(devinfo);
2207 2206
2208 2207 if (ddi_soft_state_zalloc(ural_soft_state_p, instance) != DDI_SUCCESS) {
2209 2208 ral_debug(RAL_DBG_MSG, "ural_attach(): "
2210 2209 "unable to alloc soft_state_p\n");
2211 2210 return (DDI_FAILURE);
2212 2211 }
2213 2212
2214 2213 sc = ddi_get_soft_state(ural_soft_state_p, instance);
2215 2214 ic = (ieee80211com_t *)&sc->sc_ic;
2216 2215 sc->sc_dev = devinfo;
2217 2216
2218 2217 if (usb_client_attach(devinfo, USBDRV_VERSION, 0) != USB_SUCCESS) {
2219 2218 ral_debug(RAL_DBG_ERR,
2220 2219 "ural_attach(): usb_client_attach failed\n");
2221 2220 goto fail1;
2222 2221 }
2223 2222
2224 2223 if (usb_get_dev_data(devinfo, &sc->sc_udev,
2225 2224 USB_PARSE_LVL_ALL, 0) != USB_SUCCESS) {
2226 2225 sc->sc_udev = NULL;
2227 2226 goto fail2;
2228 2227 }
2229 2228
2230 2229 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
2231 2230 mutex_init(&sc->tx_lock, NULL, MUTEX_DRIVER, NULL);
2232 2231 mutex_init(&sc->rx_lock, NULL, MUTEX_DRIVER, NULL);
2233 2232
2234 2233 /* retrieve RT2570 rev. no */
2235 2234 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0);
2236 2235
2237 2236 /* retrieve MAC address and various other things from EEPROM */
2238 2237 ural_read_eeprom(sc);
2239 2238
2240 2239 ral_debug(RAL_DBG_MSG, "ural: MAC/BBP RT2570 (rev 0x%02x), RF %s\n",
2241 2240 sc->asic_rev, ural_get_rf(sc->rf_rev));
2242 2241
2243 2242 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
2244 2243 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
2245 2244 ic->ic_state = IEEE80211_S_INIT;
2246 2245
2247 2246 ic->ic_maxrssi = 63;
2248 2247 ic->ic_set_shortslot = ural_update_slot;
2249 2248 ic->ic_xmit = ural_send;
2250 2249
2251 2250 /* set device capabilities */
2252 2251 ic->ic_caps =
2253 2252 IEEE80211_C_TXPMGT | /* tx power management */
2254 2253 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
2255 2254 IEEE80211_C_SHSLOT; /* short slot time supported */
2256 2255
2257 2256 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
2258 2257
2259 2258 #define IEEE80211_CHAN_A \
2260 2259 (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM)
2261 2260
2262 2261 if (sc->rf_rev == RAL_RF_5222) {
2263 2262 /* set supported .11a rates */
2264 2263 ic->ic_sup_rates[IEEE80211_MODE_11A] = ural_rateset_11a;
2265 2264
2266 2265 /* set supported .11a channels */
2267 2266 for (i = 36; i <= 64; i += 4) {
2268 2267 ic->ic_sup_channels[i].ich_freq =
2269 2268 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2270 2269 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2271 2270 }
2272 2271 for (i = 100; i <= 140; i += 4) {
2273 2272 ic->ic_sup_channels[i].ich_freq =
2274 2273 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2275 2274 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2276 2275 }
2277 2276 for (i = 149; i <= 161; i += 4) {
2278 2277 ic->ic_sup_channels[i].ich_freq =
2279 2278 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2280 2279 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2281 2280 }
2282 2281 }
2283 2282
2284 2283 /* set supported .11b and .11g rates */
2285 2284 ic->ic_sup_rates[IEEE80211_MODE_11B] = ural_rateset_11b;
2286 2285 ic->ic_sup_rates[IEEE80211_MODE_11G] = ural_rateset_11g;
2287 2286
2288 2287 /* set supported .11b and .11g channels (1 through 14) */
2289 2288 for (i = 1; i <= 14; i++) {
2290 2289 ic->ic_sup_channels[i].ich_freq =
2291 2290 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
2292 2291 ic->ic_sup_channels[i].ich_flags =
2293 2292 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
2294 2293 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
2295 2294 }
2296 2295
2297 2296 ieee80211_attach(ic);
2298 2297
2299 2298 /* register WPA door */
2300 2299 ieee80211_register_door(ic, ddi_driver_name(devinfo),
2301 2300 ddi_get_instance(devinfo));
2302 2301
2303 2302 /* override state transition machine */
2304 2303 sc->sc_newstate = ic->ic_newstate;
2305 2304 ic->ic_newstate = ural_newstate;
2306 2305 ic->ic_watchdog = ural_watchdog;
2307 2306 ieee80211_media_init(ic);
2308 2307 ic->ic_def_txkey = 0;
2309 2308
2310 2309 sc->sc_rcr = 0;
2311 2310 sc->dwelltime = 300;
2312 2311 sc->sc_flags &= 0;
2313 2312
2314 2313 /*
2315 2314 * Provide initial settings for the WiFi plugin; whenever this
2316 2315 * information changes, we need to call mac_plugindata_update()
2317 2316 */
2318 2317 wd.wd_opmode = ic->ic_opmode;
2319 2318 wd.wd_secalloc = WIFI_SEC_NONE;
2320 2319 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
2321 2320
2322 2321 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
2323 2322 ral_debug(RAL_DBG_ERR, "ural_attach(): "
2324 2323 "MAC version mismatch\n");
2325 2324 goto fail3;
2326 2325 }
2327 2326
2328 2327 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
2329 2328 macp->m_driver = sc;
2330 2329 macp->m_dip = devinfo;
2331 2330 macp->m_src_addr = ic->ic_macaddr;
2332 2331 macp->m_callbacks = &ural_m_callbacks;
2333 2332 macp->m_min_sdu = 0;
2334 2333 macp->m_max_sdu = IEEE80211_MTU;
2335 2334 macp->m_pdata = &wd;
2336 2335 macp->m_pdata_size = sizeof (wd);
2337 2336
2338 2337 err = mac_register(macp, &ic->ic_mach);
2339 2338 mac_free(macp);
2340 2339 if (err != 0) {
2341 2340 ral_debug(RAL_DBG_ERR, "ural_attach(): "
2342 2341 "mac_register() err %x\n", err);
2343 2342 goto fail3;
2344 2343 }
2345 2344
2346 2345 if (usb_register_hotplug_cbs(devinfo, ural_disconnect,
2347 2346 ural_reconnect) != USB_SUCCESS) {
2348 2347 ral_debug(RAL_DBG_ERR,
2349 2348 "ural: ural_attach() failed to register events");
2350 2349 goto fail4;
2351 2350 }
2352 2351
2353 2352 /*
2354 2353 * Create minor node of type DDI_NT_NET_WIFI
2355 2354 */
2356 2355 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
2357 2356 "ural", instance);
2358 2357 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
2359 2358 instance + 1, DDI_NT_NET_WIFI, 0);
2360 2359
2361 2360 if (err != DDI_SUCCESS)
2362 2361 ral_debug(RAL_DBG_ERR, "ddi_create_minor_node() failed\n");
2363 2362
2364 2363 /*
2365 2364 * Notify link is down now
2366 2365 */
2367 2366 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
2368 2367
2369 2368 return (DDI_SUCCESS);
2370 2369 fail4:
2371 2370 (void) mac_unregister(ic->ic_mach);
2372 2371 fail3:
2373 2372 mutex_destroy(&sc->sc_genlock);
2374 2373 mutex_destroy(&sc->tx_lock);
2375 2374 mutex_destroy(&sc->rx_lock);
2376 2375 fail2:
2377 2376 usb_client_detach(sc->sc_dev, sc->sc_udev);
2378 2377 fail1:
2379 2378 ddi_soft_state_free(ural_soft_state_p, ddi_get_instance(devinfo));
2380 2379
2381 2380 return (DDI_FAILURE);
2382 2381 }
2383 2382
2384 2383 static int
2385 2384 ural_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
2386 2385 {
2387 2386 struct ural_softc *sc;
2388 2387
2389 2388 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo));
2390 2389 ASSERT(sc != NULL);
2391 2390
2392 2391 switch (cmd) {
2393 2392 case DDI_DETACH:
2394 2393 break;
2395 2394 case DDI_SUSPEND:
2396 2395 if (RAL_IS_RUNNING(sc))
2397 2396 (void) ural_stop(sc);
2398 2397 return (DDI_SUCCESS);
2399 2398 default:
2400 2399 return (DDI_FAILURE);
2401 2400 }
2402 2401
2403 2402 if (mac_disable(sc->sc_ic.ic_mach) != 0)
2404 2403 return (DDI_FAILURE);
2405 2404
2406 2405 ural_stop(sc);
2407 2406 usb_unregister_hotplug_cbs(devinfo);
2408 2407
2409 2408 /*
2410 2409 * Unregister from the MAC layer subsystem
2411 2410 */
2412 2411 (void) mac_unregister(sc->sc_ic.ic_mach);
2413 2412
2414 2413 /*
2415 2414 * detach ieee80211 layer
2416 2415 */
2417 2416 ieee80211_detach(&sc->sc_ic);
2418 2417
2419 2418 mutex_destroy(&sc->sc_genlock);
2420 2419 mutex_destroy(&sc->tx_lock);
2421 2420 mutex_destroy(&sc->rx_lock);
2422 2421
2423 2422 /* pipes will be close in ural_stop() */
2424 2423 usb_client_detach(devinfo, sc->sc_udev);
2425 2424 sc->sc_udev = NULL;
2426 2425
2427 2426 ddi_remove_minor_node(devinfo, NULL);
2428 2427 ddi_soft_state_free(ural_soft_state_p, ddi_get_instance(devinfo));
2429 2428
2430 2429 return (DDI_SUCCESS);
2431 2430 }
2432 2431
2433 2432 int
2434 2433 _info(struct modinfo *modinfop)
2435 2434 {
2436 2435 return (mod_info(&modlinkage, modinfop));
2437 2436 }
2438 2437
2439 2438 int
2440 2439 _init(void)
2441 2440 {
2442 2441 int status;
2443 2442
2444 2443 status = ddi_soft_state_init(&ural_soft_state_p,
2445 2444 sizeof (struct ural_softc), 1);
2446 2445 if (status != 0)
2447 2446 return (status);
2448 2447
2449 2448 mac_init_ops(&ural_dev_ops, "ural");
2450 2449 status = mod_install(&modlinkage);
2451 2450 if (status != 0) {
2452 2451 mac_fini_ops(&ural_dev_ops);
2453 2452 ddi_soft_state_fini(&ural_soft_state_p);
2454 2453 }
2455 2454 return (status);
2456 2455 }
2457 2456
2458 2457 int
2459 2458 _fini(void)
2460 2459 {
2461 2460 int status;
2462 2461
2463 2462 status = mod_remove(&modlinkage);
2464 2463 if (status == 0) {
2465 2464 mac_fini_ops(&ural_dev_ops);
2466 2465 ddi_soft_state_fini(&ural_soft_state_p);
2467 2466 }
2468 2467 return (status);
2469 2468 }
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