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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/common/io/sfe/sfe_util.c
+++ new/usr/src/uts/common/io/sfe/sfe_util.c
1 1 /*
2 2 * sfe_util.c: general ethernet mac driver framework version 2.6
3 3 *
4 4 * Copyright (c) 2002-2008 Masayuki Murayama. All rights reserved.
5 5 *
6 6 * Redistribution and use in source and binary forms, with or without
7 7 * modification, are permitted provided that the following conditions are met:
8 8 *
9 9 * 1. Redistributions of source code must retain the above copyright notice,
10 10 * this list of conditions and the following disclaimer.
11 11 *
12 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 13 * this list of conditions and the following disclaimer in the documentation
14 14 * and/or other materials provided with the distribution.
15 15 *
16 16 * 3. Neither the name of the author nor the names of its contributors may be
17 17 * used to endorse or promote products derived from this software without
18 18 * specific prior written permission.
19 19 *
20 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
27 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
28 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 31 * DAMAGE.
32 32 */
33 33
34 34 /*
35 35 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
36 36 * Use is subject to license terms.
37 37 */
38 38
39 39 /*
40 40 * System Header files.
41 41 */
42 42 #include <sys/types.h>
43 43 #include <sys/conf.h>
44 44 #include <sys/debug.h>
45 45 #include <sys/kmem.h>
46 46 #include <sys/vtrace.h>
47 47 #include <sys/ethernet.h>
48 48 #include <sys/modctl.h>
49 49 #include <sys/errno.h>
50 50 #include <sys/ddi.h>
51 51 #include <sys/sunddi.h>
52 52 #include <sys/stream.h> /* required for MBLK* */
53 53 #include <sys/strsun.h> /* required for mionack() */
54 54 #include <sys/byteorder.h>
55 55 #include <sys/sysmacros.h>
56 56 #include <sys/pci.h>
57 57 #include <inet/common.h>
58 58 #include <inet/led.h>
59 59 #include <inet/mi.h>
60 60 #include <inet/nd.h>
61 61 #include <sys/crc32.h>
62 62
63 63 #include <sys/note.h>
64 64
65 65 #include "sfe_mii.h"
66 66 #include "sfe_util.h"
67 67
68 68
69 69
70 70 extern char ident[];
71 71
72 72 /* Debugging support */
73 73 #ifdef GEM_DEBUG_LEVEL
74 74 static int gem_debug = GEM_DEBUG_LEVEL;
75 75 #define DPRINTF(n, args) if (gem_debug > (n)) cmn_err args
76 76 #else
77 77 #define DPRINTF(n, args)
78 78 #undef ASSERT
79 79 #define ASSERT(x)
80 80 #endif
81 81
82 82 #define IOC_LINESIZE 0x40 /* Is it right for amd64? */
83 83
84 84 /*
85 85 * Useful macros and typedefs
86 86 */
87 87 #define ROUNDUP(x, a) (((x) + (a) - 1) & ~((a) - 1))
88 88
89 89 #define GET_NET16(p) ((((uint8_t *)(p))[0] << 8)| ((uint8_t *)(p))[1])
90 90 #define GET_ETHERTYPE(p) GET_NET16(((uint8_t *)(p)) + ETHERADDRL*2)
91 91
92 92 #define GET_IPTYPEv4(p) (((uint8_t *)(p))[sizeof (struct ether_header) + 9])
93 93 #define GET_IPTYPEv6(p) (((uint8_t *)(p))[sizeof (struct ether_header) + 6])
94 94
95 95
96 96 #ifndef INT32_MAX
97 97 #define INT32_MAX 0x7fffffff
98 98 #endif
99 99
100 100 #define VTAG_OFF (ETHERADDRL*2)
101 101 #ifndef VTAG_SIZE
102 102 #define VTAG_SIZE 4
103 103 #endif
104 104 #ifndef VTAG_TPID
105 105 #define VTAG_TPID 0x8100U
106 106 #endif
107 107
108 108 #define GET_TXBUF(dp, sn) \
109 109 &(dp)->tx_buf[SLOT((dp)->tx_slots_base + (sn), (dp)->gc.gc_tx_buf_size)]
110 110
111 111 #define TXFLAG_VTAG(flag) \
112 112 (((flag) & GEM_TXFLAG_VTAG) >> GEM_TXFLAG_VTAG_SHIFT)
113 113
114 114 #define MAXPKTBUF(dp) \
115 115 ((dp)->mtu + sizeof (struct ether_header) + VTAG_SIZE + ETHERFCSL)
116 116
117 117 #define WATCH_INTERVAL_FAST drv_usectohz(100*1000) /* 100mS */
118 118 #define BOOLEAN(x) ((x) != 0)
119 119
120 120 /*
121 121 * Macros to distinct chip generation.
122 122 */
123 123
124 124 /*
125 125 * Private functions
126 126 */
127 127 static void gem_mii_start(struct gem_dev *);
128 128 static void gem_mii_stop(struct gem_dev *);
129 129
130 130 /* local buffer management */
131 131 static void gem_nd_setup(struct gem_dev *dp);
132 132 static void gem_nd_cleanup(struct gem_dev *dp);
133 133 static int gem_alloc_memory(struct gem_dev *);
134 134 static void gem_free_memory(struct gem_dev *);
135 135 static void gem_init_rx_ring(struct gem_dev *);
136 136 static void gem_init_tx_ring(struct gem_dev *);
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137 137 __INLINE__ static void gem_append_rxbuf(struct gem_dev *, struct rxbuf *);
138 138
139 139 static void gem_tx_timeout(struct gem_dev *);
140 140 static void gem_mii_link_watcher(struct gem_dev *dp);
141 141 static int gem_mac_init(struct gem_dev *dp);
142 142 static int gem_mac_start(struct gem_dev *dp);
143 143 static int gem_mac_stop(struct gem_dev *dp, uint_t flags);
144 144 static void gem_mac_ioctl(struct gem_dev *dp, queue_t *wq, mblk_t *mp);
145 145
146 146 static struct ether_addr gem_etherbroadcastaddr = {
147 - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
147 + { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }
148 148 };
149 149
150 150 int gem_speed_value[] = {10, 100, 1000};
151 151
152 152 /* ============================================================== */
153 153 /*
154 154 * Misc runtime routines
155 155 */
156 156 /* ============================================================== */
157 157 /*
158 158 * Ether CRC calculation according to 21143 data sheet
159 159 */
160 160 uint32_t
161 161 gem_ether_crc_le(const uint8_t *addr, int len)
162 162 {
163 163 uint32_t crc;
164 164
165 165 CRC32(crc, addr, ETHERADDRL, 0xffffffffU, crc32_table);
166 166 return (crc);
167 167 }
168 168
169 169 uint32_t
170 170 gem_ether_crc_be(const uint8_t *addr, int len)
171 171 {
172 172 int idx;
173 173 int bit;
174 174 uint_t data;
175 175 uint32_t crc;
176 176 #define CRC32_POLY_BE 0x04c11db7
177 177
178 178 crc = 0xffffffff;
179 179 for (idx = 0; idx < len; idx++) {
180 180 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) {
181 181 crc = (crc << 1)
182 182 ^ ((((crc >> 31) ^ data) & 1) ? CRC32_POLY_BE : 0);
183 183 }
184 184 }
185 185 return (crc);
186 186 #undef CRC32_POLY_BE
187 187 }
188 188
189 189 int
190 190 gem_prop_get_int(struct gem_dev *dp, char *prop_template, int def_val)
191 191 {
192 192 char propname[32];
193 193
194 194 (void) sprintf(propname, prop_template, dp->name);
195 195
196 196 return (ddi_prop_get_int(DDI_DEV_T_ANY, dp->dip,
197 197 DDI_PROP_DONTPASS, propname, def_val));
198 198 }
199 199
200 200 static int
201 201 gem_population(uint32_t x)
202 202 {
203 203 int i;
204 204 int cnt;
205 205
206 206 cnt = 0;
207 207 for (i = 0; i < 32; i++) {
208 208 if (x & (1 << i)) {
209 209 cnt++;
210 210 }
211 211 }
212 212 return (cnt);
213 213 }
214 214
215 215 #ifdef GEM_DEBUG_LEVEL
216 216 #ifdef GEM_DEBUG_VLAN
217 217 static void
218 218 gem_dump_packet(struct gem_dev *dp, char *title, mblk_t *mp,
219 219 boolean_t check_cksum)
220 220 {
221 221 char msg[180];
222 222 uint8_t buf[18+20+20];
223 223 uint8_t *p;
224 224 size_t offset;
225 225 uint_t ethertype;
226 226 uint_t proto;
227 227 uint_t ipproto = 0;
228 228 uint_t iplen;
229 229 uint_t iphlen;
230 230 uint_t tcplen;
231 231 uint_t udplen;
232 232 uint_t cksum;
233 233 int rest;
234 234 int len;
235 235 char *bp;
236 236 mblk_t *tp;
237 237 extern uint_t ip_cksum(mblk_t *, int, uint32_t);
238 238
239 239 msg[0] = 0;
240 240 bp = msg;
241 241
242 242 rest = sizeof (buf);
243 243 offset = 0;
244 244 for (tp = mp; tp; tp = tp->b_cont) {
245 245 len = tp->b_wptr - tp->b_rptr;
246 246 len = min(rest, len);
247 247 bcopy(tp->b_rptr, &buf[offset], len);
248 248 rest -= len;
249 249 offset += len;
250 250 if (rest == 0) {
251 251 break;
252 252 }
253 253 }
254 254
255 255 offset = 0;
256 256 p = &buf[offset];
257 257
258 258 /* ethernet address */
259 259 sprintf(bp,
260 260 "ether: %02x:%02x:%02x:%02x:%02x:%02x"
261 261 " -> %02x:%02x:%02x:%02x:%02x:%02x",
262 262 p[6], p[7], p[8], p[9], p[10], p[11],
263 263 p[0], p[1], p[2], p[3], p[4], p[5]);
264 264 bp = &msg[strlen(msg)];
265 265
266 266 /* vlag tag and etherrtype */
267 267 ethertype = GET_ETHERTYPE(p);
268 268 if (ethertype == VTAG_TPID) {
269 269 sprintf(bp, " vtag:0x%04x", GET_NET16(&p[14]));
270 270 bp = &msg[strlen(msg)];
271 271
272 272 offset += VTAG_SIZE;
273 273 p = &buf[offset];
274 274 ethertype = GET_ETHERTYPE(p);
275 275 }
276 276 sprintf(bp, " type:%04x", ethertype);
277 277 bp = &msg[strlen(msg)];
278 278
279 279 /* ethernet packet length */
280 280 sprintf(bp, " mblklen:%d", msgdsize(mp));
281 281 bp = &msg[strlen(msg)];
282 282 if (mp->b_cont) {
283 283 sprintf(bp, "(");
284 284 bp = &msg[strlen(msg)];
285 285 for (tp = mp; tp; tp = tp->b_cont) {
286 286 if (tp == mp) {
287 287 sprintf(bp, "%d", tp->b_wptr - tp->b_rptr);
288 288 } else {
289 289 sprintf(bp, "+%d", tp->b_wptr - tp->b_rptr);
290 290 }
291 291 bp = &msg[strlen(msg)];
292 292 }
293 293 sprintf(bp, ")");
294 294 bp = &msg[strlen(msg)];
295 295 }
296 296
297 297 if (ethertype != ETHERTYPE_IP) {
298 298 goto x;
299 299 }
300 300
301 301 /* ip address */
302 302 offset += sizeof (struct ether_header);
303 303 p = &buf[offset];
304 304 ipproto = p[9];
305 305 iplen = GET_NET16(&p[2]);
306 306 sprintf(bp, ", ip: %d.%d.%d.%d -> %d.%d.%d.%d proto:%d iplen:%d",
307 307 p[12], p[13], p[14], p[15],
308 308 p[16], p[17], p[18], p[19],
309 309 ipproto, iplen);
310 310 bp = (void *)&msg[strlen(msg)];
311 311
312 312 iphlen = (p[0] & 0xf) * 4;
313 313
314 314 /* cksum for psuedo header */
315 315 cksum = *(uint16_t *)&p[12];
316 316 cksum += *(uint16_t *)&p[14];
317 317 cksum += *(uint16_t *)&p[16];
318 318 cksum += *(uint16_t *)&p[18];
319 319 cksum += BE_16(ipproto);
320 320
321 321 /* tcp or udp protocol header */
322 322 offset += iphlen;
323 323 p = &buf[offset];
324 324 if (ipproto == IPPROTO_TCP) {
325 325 tcplen = iplen - iphlen;
326 326 sprintf(bp, ", tcp: len:%d cksum:%x",
327 327 tcplen, GET_NET16(&p[16]));
328 328 bp = (void *)&msg[strlen(msg)];
329 329
330 330 if (check_cksum) {
331 331 cksum += BE_16(tcplen);
332 332 cksum = (uint16_t)ip_cksum(mp, offset, cksum);
333 333 sprintf(bp, " (%s)",
334 334 (cksum == 0 || cksum == 0xffff) ? "ok" : "ng");
335 335 bp = (void *)&msg[strlen(msg)];
336 336 }
337 337 } else if (ipproto == IPPROTO_UDP) {
338 338 udplen = GET_NET16(&p[4]);
339 339 sprintf(bp, ", udp: len:%d cksum:%x",
340 340 udplen, GET_NET16(&p[6]));
341 341 bp = (void *)&msg[strlen(msg)];
342 342
343 343 if (GET_NET16(&p[6]) && check_cksum) {
344 344 cksum += *(uint16_t *)&p[4];
345 345 cksum = (uint16_t)ip_cksum(mp, offset, cksum);
346 346 sprintf(bp, " (%s)",
347 347 (cksum == 0 || cksum == 0xffff) ? "ok" : "ng");
348 348 bp = (void *)&msg[strlen(msg)];
349 349 }
350 350 }
351 351 x:
352 352 cmn_err(CE_CONT, "!%s: %s: %s", dp->name, title, msg);
353 353 }
354 354 #endif /* GEM_DEBUG_VLAN */
355 355 #endif /* GEM_DEBUG_LEVEL */
356 356
357 357 /* ============================================================== */
358 358 /*
359 359 * IO cache flush
360 360 */
361 361 /* ============================================================== */
362 362 __INLINE__ void
363 363 gem_rx_desc_dma_sync(struct gem_dev *dp, int head, int nslot, int how)
364 364 {
365 365 int n;
366 366 int m;
367 367 int rx_desc_unit_shift = dp->gc.gc_rx_desc_unit_shift;
368 368
369 369 /* sync active descriptors */
370 370 if (rx_desc_unit_shift < 0 || nslot == 0) {
371 371 /* no rx descriptor ring */
372 372 return;
373 373 }
374 374
375 375 n = dp->gc.gc_rx_ring_size - head;
376 376 if ((m = nslot - n) > 0) {
377 377 (void) ddi_dma_sync(dp->desc_dma_handle,
378 378 (off_t)0,
379 379 (size_t)(m << rx_desc_unit_shift),
380 380 how);
381 381 nslot = n;
382 382 }
383 383
384 384 (void) ddi_dma_sync(dp->desc_dma_handle,
385 385 (off_t)(head << rx_desc_unit_shift),
386 386 (size_t)(nslot << rx_desc_unit_shift),
387 387 how);
388 388 }
389 389
390 390 __INLINE__ void
391 391 gem_tx_desc_dma_sync(struct gem_dev *dp, int head, int nslot, int how)
392 392 {
393 393 int n;
394 394 int m;
395 395 int tx_desc_unit_shift = dp->gc.gc_tx_desc_unit_shift;
396 396
397 397 /* sync active descriptors */
398 398 if (tx_desc_unit_shift < 0 || nslot == 0) {
399 399 /* no tx descriptor ring */
400 400 return;
401 401 }
402 402
403 403 n = dp->gc.gc_tx_ring_size - head;
404 404 if ((m = nslot - n) > 0) {
405 405 (void) ddi_dma_sync(dp->desc_dma_handle,
406 406 (off_t)(dp->tx_ring_dma - dp->rx_ring_dma),
407 407 (size_t)(m << tx_desc_unit_shift),
408 408 how);
409 409 nslot = n;
410 410 }
411 411
412 412 (void) ddi_dma_sync(dp->desc_dma_handle,
413 413 (off_t)((head << tx_desc_unit_shift)
414 414 + (dp->tx_ring_dma - dp->rx_ring_dma)),
415 415 (size_t)(nslot << tx_desc_unit_shift),
416 416 how);
417 417 }
418 418
419 419 static void
420 420 gem_rx_start_default(struct gem_dev *dp, int head, int nslot)
421 421 {
422 422 gem_rx_desc_dma_sync(dp,
423 423 SLOT(head, dp->gc.gc_rx_ring_size), nslot,
424 424 DDI_DMA_SYNC_FORDEV);
425 425 }
426 426
427 427 /* ============================================================== */
428 428 /*
429 429 * Buffer management
430 430 */
431 431 /* ============================================================== */
432 432 static void
433 433 gem_dump_txbuf(struct gem_dev *dp, int level, const char *title)
434 434 {
435 435 cmn_err(level,
436 436 "!%s: %s: tx_active: %d[%d] %d[%d] (+%d), "
437 437 "tx_softq: %d[%d] %d[%d] (+%d), "
438 438 "tx_free: %d[%d] %d[%d] (+%d), "
439 439 "tx_desc: %d[%d] %d[%d] (+%d), "
440 440 "intr: %d[%d] (+%d), ",
441 441 dp->name, title,
442 442 dp->tx_active_head,
443 443 SLOT(dp->tx_active_head, dp->gc.gc_tx_buf_size),
444 444 dp->tx_active_tail,
445 445 SLOT(dp->tx_active_tail, dp->gc.gc_tx_buf_size),
446 446 dp->tx_active_tail - dp->tx_active_head,
447 447 dp->tx_softq_head,
448 448 SLOT(dp->tx_softq_head, dp->gc.gc_tx_buf_size),
449 449 dp->tx_softq_tail,
450 450 SLOT(dp->tx_softq_tail, dp->gc.gc_tx_buf_size),
451 451 dp->tx_softq_tail - dp->tx_softq_head,
452 452 dp->tx_free_head,
453 453 SLOT(dp->tx_free_head, dp->gc.gc_tx_buf_size),
454 454 dp->tx_free_tail,
455 455 SLOT(dp->tx_free_tail, dp->gc.gc_tx_buf_size),
456 456 dp->tx_free_tail - dp->tx_free_head,
457 457 dp->tx_desc_head,
458 458 SLOT(dp->tx_desc_head, dp->gc.gc_tx_ring_size),
459 459 dp->tx_desc_tail,
460 460 SLOT(dp->tx_desc_tail, dp->gc.gc_tx_ring_size),
461 461 dp->tx_desc_tail - dp->tx_desc_head,
462 462 dp->tx_desc_intr,
463 463 SLOT(dp->tx_desc_intr, dp->gc.gc_tx_ring_size),
464 464 dp->tx_desc_intr - dp->tx_desc_head);
465 465 }
466 466
467 467 static void
468 468 gem_free_rxbuf(struct rxbuf *rbp)
469 469 {
470 470 struct gem_dev *dp;
471 471
472 472 dp = rbp->rxb_devp;
473 473 ASSERT(mutex_owned(&dp->intrlock));
474 474 rbp->rxb_next = dp->rx_buf_freelist;
475 475 dp->rx_buf_freelist = rbp;
476 476 dp->rx_buf_freecnt++;
477 477 }
478 478
479 479 /*
480 480 * gem_get_rxbuf: supply a receive buffer which have been mapped into
481 481 * DMA space.
482 482 */
483 483 struct rxbuf *
484 484 gem_get_rxbuf(struct gem_dev *dp, int cansleep)
485 485 {
486 486 struct rxbuf *rbp;
487 487 uint_t count = 0;
488 488 int i;
489 489 int err;
490 490
491 491 ASSERT(mutex_owned(&dp->intrlock));
492 492
493 493 DPRINTF(3, (CE_CONT, "!gem_get_rxbuf: called freecnt:%d",
494 494 dp->rx_buf_freecnt));
495 495 /*
496 496 * Get rx buffer management structure
497 497 */
498 498 rbp = dp->rx_buf_freelist;
499 499 if (rbp) {
500 500 /* get one from the recycle list */
501 501 ASSERT(dp->rx_buf_freecnt > 0);
502 502
503 503 dp->rx_buf_freelist = rbp->rxb_next;
504 504 dp->rx_buf_freecnt--;
505 505 rbp->rxb_next = NULL;
506 506 return (rbp);
507 507 }
508 508
509 509 /*
510 510 * Allocate a rx buffer management structure
511 511 */
512 512 rbp = kmem_zalloc(sizeof (*rbp), cansleep ? KM_SLEEP : KM_NOSLEEP);
513 513 if (rbp == NULL) {
514 514 /* no memory */
515 515 return (NULL);
516 516 }
517 517
518 518 /*
519 519 * Prepare a back pointer to the device structure which will be
520 520 * refered on freeing the buffer later.
521 521 */
522 522 rbp->rxb_devp = dp;
523 523
524 524 /* allocate a dma handle for rx data buffer */
525 525 if ((err = ddi_dma_alloc_handle(dp->dip,
526 526 &dp->gc.gc_dma_attr_rxbuf,
527 527 (cansleep ? DDI_DMA_SLEEP : DDI_DMA_DONTWAIT),
528 528 NULL, &rbp->rxb_dh)) != DDI_SUCCESS) {
529 529
530 530 cmn_err(CE_WARN,
531 531 "!%s: %s: ddi_dma_alloc_handle:1 failed, err=%d",
532 532 dp->name, __func__, err);
533 533
534 534 kmem_free(rbp, sizeof (struct rxbuf));
535 535 return (NULL);
536 536 }
537 537
538 538 /* allocate a bounce buffer for rx */
539 539 if ((err = ddi_dma_mem_alloc(rbp->rxb_dh,
540 540 ROUNDUP(dp->rx_buf_len, IOC_LINESIZE),
541 541 &dp->gc.gc_buf_attr,
542 542 /*
543 543 * if the nic requires a header at the top of receive buffers,
544 544 * it may access the rx buffer randomly.
545 545 */
546 546 (dp->gc.gc_rx_header_len > 0)
547 547 ? DDI_DMA_CONSISTENT : DDI_DMA_STREAMING,
548 548 cansleep ? DDI_DMA_SLEEP : DDI_DMA_DONTWAIT,
549 549 NULL,
550 550 &rbp->rxb_buf, &rbp->rxb_buf_len,
551 551 &rbp->rxb_bah)) != DDI_SUCCESS) {
552 552
553 553 cmn_err(CE_WARN,
554 554 "!%s: %s: ddi_dma_mem_alloc: failed, err=%d",
555 555 dp->name, __func__, err);
556 556
557 557 ddi_dma_free_handle(&rbp->rxb_dh);
558 558 kmem_free(rbp, sizeof (struct rxbuf));
559 559 return (NULL);
560 560 }
561 561
562 562 /* Mapin the bounce buffer into the DMA space */
563 563 if ((err = ddi_dma_addr_bind_handle(rbp->rxb_dh,
564 564 NULL, rbp->rxb_buf, dp->rx_buf_len,
565 565 ((dp->gc.gc_rx_header_len > 0)
566 566 ?(DDI_DMA_RDWR | DDI_DMA_CONSISTENT)
567 567 :(DDI_DMA_READ | DDI_DMA_STREAMING)),
568 568 cansleep ? DDI_DMA_SLEEP : DDI_DMA_DONTWAIT,
569 569 NULL,
570 570 rbp->rxb_dmacookie,
571 571 &count)) != DDI_DMA_MAPPED) {
572 572
573 573 ASSERT(err != DDI_DMA_INUSE);
574 574 DPRINTF(0, (CE_WARN,
575 575 "!%s: ddi_dma_addr_bind_handle: failed, err=%d",
576 576 dp->name, __func__, err));
577 577
578 578 /*
579 579 * we failed to allocate a dma resource
580 580 * for the rx bounce buffer.
581 581 */
582 582 ddi_dma_mem_free(&rbp->rxb_bah);
583 583 ddi_dma_free_handle(&rbp->rxb_dh);
584 584 kmem_free(rbp, sizeof (struct rxbuf));
585 585 return (NULL);
586 586 }
587 587
588 588 /* correct the rest of the DMA mapping */
589 589 for (i = 1; i < count; i++) {
590 590 ddi_dma_nextcookie(rbp->rxb_dh, &rbp->rxb_dmacookie[i]);
591 591 }
592 592 rbp->rxb_nfrags = count;
593 593
594 594 /* Now we successfully prepared an rx buffer */
595 595 dp->rx_buf_allocated++;
596 596
597 597 return (rbp);
598 598 }
599 599
600 600 /* ============================================================== */
601 601 /*
602 602 * memory resource management
603 603 */
604 604 /* ============================================================== */
605 605 static int
606 606 gem_alloc_memory(struct gem_dev *dp)
607 607 {
608 608 caddr_t ring;
609 609 caddr_t buf;
610 610 size_t req_size;
611 611 size_t ring_len;
612 612 size_t buf_len;
613 613 ddi_dma_cookie_t ring_cookie;
614 614 ddi_dma_cookie_t buf_cookie;
615 615 uint_t count;
616 616 int i;
617 617 int err;
618 618 struct txbuf *tbp;
619 619 int tx_buf_len;
620 620 ddi_dma_attr_t dma_attr_txbounce;
621 621
622 622 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
623 623
624 624 dp->desc_dma_handle = NULL;
625 625 req_size = dp->rx_desc_size + dp->tx_desc_size + dp->gc.gc_io_area_size;
626 626
627 627 if (req_size > 0) {
628 628 /*
629 629 * Alloc RX/TX descriptors and a io area.
630 630 */
631 631 if ((err = ddi_dma_alloc_handle(dp->dip,
632 632 &dp->gc.gc_dma_attr_desc,
633 633 DDI_DMA_SLEEP, NULL,
634 634 &dp->desc_dma_handle)) != DDI_SUCCESS) {
635 635 cmn_err(CE_WARN,
636 636 "!%s: %s: ddi_dma_alloc_handle failed: %d",
637 637 dp->name, __func__, err);
638 638 return (ENOMEM);
639 639 }
640 640
641 641 if ((err = ddi_dma_mem_alloc(dp->desc_dma_handle,
642 642 req_size, &dp->gc.gc_desc_attr,
643 643 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
644 644 &ring, &ring_len,
645 645 &dp->desc_acc_handle)) != DDI_SUCCESS) {
646 646 cmn_err(CE_WARN,
647 647 "!%s: %s: ddi_dma_mem_alloc failed: "
648 648 "ret %d, request size: %d",
649 649 dp->name, __func__, err, (int)req_size);
650 650 ddi_dma_free_handle(&dp->desc_dma_handle);
651 651 return (ENOMEM);
652 652 }
653 653
654 654 if ((err = ddi_dma_addr_bind_handle(dp->desc_dma_handle,
655 655 NULL, ring, ring_len,
656 656 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
657 657 DDI_DMA_SLEEP, NULL,
658 658 &ring_cookie, &count)) != DDI_SUCCESS) {
659 659 ASSERT(err != DDI_DMA_INUSE);
660 660 cmn_err(CE_WARN,
661 661 "!%s: %s: ddi_dma_addr_bind_handle failed: %d",
662 662 dp->name, __func__, err);
663 663 ddi_dma_mem_free(&dp->desc_acc_handle);
664 664 ddi_dma_free_handle(&dp->desc_dma_handle);
665 665 return (ENOMEM);
666 666 }
667 667 ASSERT(count == 1);
668 668
669 669 /* set base of rx descriptor ring */
670 670 dp->rx_ring = ring;
671 671 dp->rx_ring_dma = ring_cookie.dmac_laddress;
672 672
673 673 /* set base of tx descriptor ring */
674 674 dp->tx_ring = dp->rx_ring + dp->rx_desc_size;
675 675 dp->tx_ring_dma = dp->rx_ring_dma + dp->rx_desc_size;
676 676
677 677 /* set base of io area */
678 678 dp->io_area = dp->tx_ring + dp->tx_desc_size;
679 679 dp->io_area_dma = dp->tx_ring_dma + dp->tx_desc_size;
680 680 }
681 681
682 682 /*
683 683 * Prepare DMA resources for tx packets
684 684 */
685 685 ASSERT(dp->gc.gc_tx_buf_size > 0);
686 686
687 687 /* Special dma attribute for tx bounce buffers */
688 688 dma_attr_txbounce = dp->gc.gc_dma_attr_txbuf;
689 689 dma_attr_txbounce.dma_attr_sgllen = 1;
690 690 dma_attr_txbounce.dma_attr_align =
691 691 max(dma_attr_txbounce.dma_attr_align, IOC_LINESIZE);
692 692
693 693 /* Size for tx bounce buffers must be max tx packet size. */
694 694 tx_buf_len = MAXPKTBUF(dp);
695 695 tx_buf_len = ROUNDUP(tx_buf_len, IOC_LINESIZE);
696 696
697 697 ASSERT(tx_buf_len >= ETHERMAX+ETHERFCSL);
698 698
699 699 for (i = 0, tbp = dp->tx_buf;
700 700 i < dp->gc.gc_tx_buf_size; i++, tbp++) {
701 701
702 702 /* setup bounce buffers for tx packets */
703 703 if ((err = ddi_dma_alloc_handle(dp->dip,
704 704 &dma_attr_txbounce,
705 705 DDI_DMA_SLEEP, NULL,
706 706 &tbp->txb_bdh)) != DDI_SUCCESS) {
707 707
708 708 cmn_err(CE_WARN,
709 709 "!%s: %s ddi_dma_alloc_handle for bounce buffer failed:"
710 710 " err=%d, i=%d",
711 711 dp->name, __func__, err, i);
712 712 goto err_alloc_dh;
713 713 }
714 714
715 715 if ((err = ddi_dma_mem_alloc(tbp->txb_bdh,
716 716 tx_buf_len,
717 717 &dp->gc.gc_buf_attr,
718 718 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL,
719 719 &buf, &buf_len,
720 720 &tbp->txb_bah)) != DDI_SUCCESS) {
721 721 cmn_err(CE_WARN,
722 722 "!%s: %s: ddi_dma_mem_alloc for bounce buffer failed"
723 723 "ret %d, request size %d",
724 724 dp->name, __func__, err, tx_buf_len);
725 725 ddi_dma_free_handle(&tbp->txb_bdh);
726 726 goto err_alloc_dh;
727 727 }
728 728
729 729 if ((err = ddi_dma_addr_bind_handle(tbp->txb_bdh,
730 730 NULL, buf, buf_len,
731 731 DDI_DMA_WRITE | DDI_DMA_STREAMING,
732 732 DDI_DMA_SLEEP, NULL,
733 733 &buf_cookie, &count)) != DDI_SUCCESS) {
734 734 ASSERT(err != DDI_DMA_INUSE);
735 735 cmn_err(CE_WARN,
736 736 "!%s: %s: ddi_dma_addr_bind_handle for bounce buffer failed: %d",
737 737 dp->name, __func__, err);
738 738 ddi_dma_mem_free(&tbp->txb_bah);
739 739 ddi_dma_free_handle(&tbp->txb_bdh);
740 740 goto err_alloc_dh;
741 741 }
742 742 ASSERT(count == 1);
743 743 tbp->txb_buf = buf;
744 744 tbp->txb_buf_dma = buf_cookie.dmac_laddress;
745 745 }
746 746
747 747 return (0);
748 748
749 749 err_alloc_dh:
750 750 if (dp->gc.gc_tx_buf_size > 0) {
751 751 while (i-- > 0) {
752 752 (void) ddi_dma_unbind_handle(dp->tx_buf[i].txb_bdh);
753 753 ddi_dma_mem_free(&dp->tx_buf[i].txb_bah);
754 754 ddi_dma_free_handle(&dp->tx_buf[i].txb_bdh);
755 755 }
756 756 }
757 757
758 758 if (dp->desc_dma_handle) {
759 759 (void) ddi_dma_unbind_handle(dp->desc_dma_handle);
760 760 ddi_dma_mem_free(&dp->desc_acc_handle);
761 761 ddi_dma_free_handle(&dp->desc_dma_handle);
762 762 dp->desc_dma_handle = NULL;
763 763 }
764 764
765 765 return (ENOMEM);
766 766 }
767 767
768 768 static void
769 769 gem_free_memory(struct gem_dev *dp)
770 770 {
771 771 int i;
772 772 struct rxbuf *rbp;
773 773 struct txbuf *tbp;
774 774
775 775 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
776 776
777 777 /* Free TX/RX descriptors and tx padding buffer */
778 778 if (dp->desc_dma_handle) {
779 779 (void) ddi_dma_unbind_handle(dp->desc_dma_handle);
780 780 ddi_dma_mem_free(&dp->desc_acc_handle);
781 781 ddi_dma_free_handle(&dp->desc_dma_handle);
782 782 dp->desc_dma_handle = NULL;
783 783 }
784 784
785 785 /* Free dma handles for Tx */
786 786 for (i = dp->gc.gc_tx_buf_size, tbp = dp->tx_buf; i--; tbp++) {
787 787 /* Free bounce buffer associated to each txbuf */
788 788 (void) ddi_dma_unbind_handle(tbp->txb_bdh);
789 789 ddi_dma_mem_free(&tbp->txb_bah);
790 790 ddi_dma_free_handle(&tbp->txb_bdh);
791 791 }
792 792
793 793 /* Free rx buffer */
794 794 while ((rbp = dp->rx_buf_freelist) != NULL) {
795 795
796 796 ASSERT(dp->rx_buf_freecnt > 0);
797 797
798 798 dp->rx_buf_freelist = rbp->rxb_next;
799 799 dp->rx_buf_freecnt--;
800 800
801 801 /* release DMA mapping */
802 802 ASSERT(rbp->rxb_dh != NULL);
803 803
804 804 /* free dma handles for rx bbuf */
805 805 /* it has dma mapping always */
806 806 ASSERT(rbp->rxb_nfrags > 0);
807 807 (void) ddi_dma_unbind_handle(rbp->rxb_dh);
808 808
809 809 /* free the associated bounce buffer and dma handle */
810 810 ASSERT(rbp->rxb_bah != NULL);
811 811 ddi_dma_mem_free(&rbp->rxb_bah);
812 812 /* free the associated dma handle */
813 813 ddi_dma_free_handle(&rbp->rxb_dh);
814 814
815 815 /* free the base memory of rx buffer management */
816 816 kmem_free(rbp, sizeof (struct rxbuf));
817 817 }
818 818 }
819 819
820 820 /* ============================================================== */
821 821 /*
822 822 * Rx/Tx descriptor slot management
823 823 */
824 824 /* ============================================================== */
825 825 /*
826 826 * Initialize an empty rx ring.
827 827 */
828 828 static void
829 829 gem_init_rx_ring(struct gem_dev *dp)
830 830 {
831 831 int i;
832 832 int rx_ring_size = dp->gc.gc_rx_ring_size;
833 833
834 834 DPRINTF(1, (CE_CONT, "!%s: %s ring_size:%d, buf_max:%d",
835 835 dp->name, __func__,
836 836 rx_ring_size, dp->gc.gc_rx_buf_max));
837 837
838 838 /* make a physical chain of rx descriptors */
839 839 for (i = 0; i < rx_ring_size; i++) {
840 840 (*dp->gc.gc_rx_desc_init)(dp, i);
841 841 }
842 842 gem_rx_desc_dma_sync(dp, 0, rx_ring_size, DDI_DMA_SYNC_FORDEV);
843 843
844 844 dp->rx_active_head = (seqnum_t)0;
845 845 dp->rx_active_tail = (seqnum_t)0;
846 846
847 847 ASSERT(dp->rx_buf_head == (struct rxbuf *)NULL);
848 848 ASSERT(dp->rx_buf_tail == (struct rxbuf *)NULL);
849 849 }
850 850
851 851 /*
852 852 * Prepare rx buffers and put them into the rx buffer/descriptor ring.
853 853 */
854 854 static void
855 855 gem_prepare_rx_buf(struct gem_dev *dp)
856 856 {
857 857 int i;
858 858 int nrbuf;
859 859 struct rxbuf *rbp;
860 860
861 861 ASSERT(mutex_owned(&dp->intrlock));
862 862
863 863 /* Now we have no active buffers in rx ring */
864 864
865 865 nrbuf = min(dp->gc.gc_rx_ring_size, dp->gc.gc_rx_buf_max);
866 866 for (i = 0; i < nrbuf; i++) {
867 867 if ((rbp = gem_get_rxbuf(dp, B_TRUE)) == NULL) {
868 868 break;
869 869 }
870 870 gem_append_rxbuf(dp, rbp);
871 871 }
872 872
873 873 gem_rx_desc_dma_sync(dp,
874 874 0, dp->gc.gc_rx_ring_size, DDI_DMA_SYNC_FORDEV);
875 875 }
876 876
877 877 /*
878 878 * Reclaim active rx buffers in rx buffer ring.
879 879 */
880 880 static void
881 881 gem_clean_rx_buf(struct gem_dev *dp)
882 882 {
883 883 int i;
884 884 struct rxbuf *rbp;
885 885 int rx_ring_size = dp->gc.gc_rx_ring_size;
886 886 #ifdef GEM_DEBUG_LEVEL
887 887 int total;
888 888 #endif
889 889 ASSERT(mutex_owned(&dp->intrlock));
890 890
891 891 DPRINTF(2, (CE_CONT, "!%s: %s: %d buffers are free",
892 892 dp->name, __func__, dp->rx_buf_freecnt));
893 893 /*
894 894 * clean up HW descriptors
895 895 */
896 896 for (i = 0; i < rx_ring_size; i++) {
897 897 (*dp->gc.gc_rx_desc_clean)(dp, i);
898 898 }
899 899 gem_rx_desc_dma_sync(dp, 0, rx_ring_size, DDI_DMA_SYNC_FORDEV);
900 900
901 901 #ifdef GEM_DEBUG_LEVEL
902 902 total = 0;
903 903 #endif
904 904 /*
905 905 * Reclaim allocated rx buffers
906 906 */
907 907 while ((rbp = dp->rx_buf_head) != NULL) {
908 908 #ifdef GEM_DEBUG_LEVEL
909 909 total++;
910 910 #endif
911 911 /* remove the first one from rx buffer list */
912 912 dp->rx_buf_head = rbp->rxb_next;
913 913
914 914 /* recycle the rxbuf */
915 915 gem_free_rxbuf(rbp);
916 916 }
917 917 dp->rx_buf_tail = (struct rxbuf *)NULL;
918 918
919 919 DPRINTF(2, (CE_CONT,
920 920 "!%s: %s: %d buffers freeed, total: %d free",
921 921 dp->name, __func__, total, dp->rx_buf_freecnt));
922 922 }
923 923
924 924 /*
925 925 * Initialize an empty transmit buffer/descriptor ring
926 926 */
927 927 static void
928 928 gem_init_tx_ring(struct gem_dev *dp)
929 929 {
930 930 int i;
931 931 int tx_buf_size = dp->gc.gc_tx_buf_size;
932 932 int tx_ring_size = dp->gc.gc_tx_ring_size;
933 933
934 934 DPRINTF(2, (CE_CONT, "!%s: %s: ring_size:%d, buf_size:%d",
935 935 dp->name, __func__,
936 936 dp->gc.gc_tx_ring_size, dp->gc.gc_tx_buf_size));
937 937
938 938 ASSERT(!dp->mac_active);
939 939
940 940 /* initialize active list and free list */
941 941 dp->tx_slots_base =
942 942 SLOT(dp->tx_slots_base + dp->tx_softq_head, tx_buf_size);
943 943 dp->tx_softq_tail -= dp->tx_softq_head;
944 944 dp->tx_softq_head = (seqnum_t)0;
945 945
946 946 dp->tx_active_head = dp->tx_softq_head;
947 947 dp->tx_active_tail = dp->tx_softq_head;
948 948
949 949 dp->tx_free_head = dp->tx_softq_tail;
950 950 dp->tx_free_tail = dp->gc.gc_tx_buf_limit;
951 951
952 952 dp->tx_desc_head = (seqnum_t)0;
953 953 dp->tx_desc_tail = (seqnum_t)0;
954 954 dp->tx_desc_intr = (seqnum_t)0;
955 955
956 956 for (i = 0; i < tx_ring_size; i++) {
957 957 (*dp->gc.gc_tx_desc_init)(dp, i);
958 958 }
959 959 gem_tx_desc_dma_sync(dp, 0, tx_ring_size, DDI_DMA_SYNC_FORDEV);
960 960 }
961 961
962 962 __INLINE__
963 963 static void
964 964 gem_txbuf_free_dma_resources(struct txbuf *tbp)
965 965 {
966 966 if (tbp->txb_mp) {
967 967 freemsg(tbp->txb_mp);
968 968 tbp->txb_mp = NULL;
969 969 }
970 970 tbp->txb_nfrags = 0;
971 971 tbp->txb_flag = 0;
972 972 }
973 973 #pragma inline(gem_txbuf_free_dma_resources)
974 974
975 975 /*
976 976 * reclaim active tx buffers and reset positions in tx rings.
977 977 */
978 978 static void
979 979 gem_clean_tx_buf(struct gem_dev *dp)
980 980 {
981 981 int i;
982 982 seqnum_t head;
983 983 seqnum_t tail;
984 984 seqnum_t sn;
985 985 struct txbuf *tbp;
986 986 int tx_ring_size = dp->gc.gc_tx_ring_size;
987 987 #ifdef GEM_DEBUG_LEVEL
988 988 int err;
989 989 #endif
990 990
991 991 ASSERT(!dp->mac_active);
992 992 ASSERT(dp->tx_busy == 0);
993 993 ASSERT(dp->tx_softq_tail == dp->tx_free_head);
994 994
995 995 /*
996 996 * clean up all HW descriptors
997 997 */
998 998 for (i = 0; i < tx_ring_size; i++) {
999 999 (*dp->gc.gc_tx_desc_clean)(dp, i);
1000 1000 }
1001 1001 gem_tx_desc_dma_sync(dp, 0, tx_ring_size, DDI_DMA_SYNC_FORDEV);
1002 1002
1003 1003 /* dequeue all active and loaded buffers */
1004 1004 head = dp->tx_active_head;
1005 1005 tail = dp->tx_softq_tail;
1006 1006
1007 1007 ASSERT(dp->tx_free_head - head >= 0);
1008 1008 tbp = GET_TXBUF(dp, head);
1009 1009 for (sn = head; sn != tail; sn++) {
1010 1010 gem_txbuf_free_dma_resources(tbp);
1011 1011 ASSERT(tbp->txb_mp == NULL);
1012 1012 dp->stats.errxmt++;
1013 1013 tbp = tbp->txb_next;
1014 1014 }
1015 1015
1016 1016 #ifdef GEM_DEBUG_LEVEL
1017 1017 /* ensure no dma resources for tx are not in use now */
1018 1018 err = 0;
1019 1019 while (sn != head + dp->gc.gc_tx_buf_size) {
1020 1020 if (tbp->txb_mp || tbp->txb_nfrags) {
1021 1021 DPRINTF(0, (CE_CONT,
1022 1022 "%s: %s: sn:%d[%d] mp:%p nfrags:%d",
1023 1023 dp->name, __func__,
1024 1024 sn, SLOT(sn, dp->gc.gc_tx_buf_size),
1025 1025 tbp->txb_mp, tbp->txb_nfrags));
1026 1026 err = 1;
1027 1027 }
1028 1028 sn++;
1029 1029 tbp = tbp->txb_next;
1030 1030 }
1031 1031
1032 1032 if (err) {
1033 1033 gem_dump_txbuf(dp, CE_WARN,
1034 1034 "gem_clean_tx_buf: tbp->txb_mp != NULL");
1035 1035 }
1036 1036 #endif
1037 1037 /* recycle buffers, now no active tx buffers in the ring */
1038 1038 dp->tx_free_tail += tail - head;
1039 1039 ASSERT(dp->tx_free_tail == dp->tx_free_head + dp->gc.gc_tx_buf_limit);
1040 1040
1041 1041 /* fix positions in tx buffer rings */
1042 1042 dp->tx_active_head = dp->tx_free_head;
1043 1043 dp->tx_active_tail = dp->tx_free_head;
1044 1044 dp->tx_softq_head = dp->tx_free_head;
1045 1045 dp->tx_softq_tail = dp->tx_free_head;
1046 1046 }
1047 1047
1048 1048 /*
1049 1049 * Reclaim transmitted buffers from tx buffer/descriptor ring.
1050 1050 */
1051 1051 __INLINE__ int
1052 1052 gem_reclaim_txbuf(struct gem_dev *dp)
1053 1053 {
1054 1054 struct txbuf *tbp;
1055 1055 uint_t txstat;
1056 1056 int err = GEM_SUCCESS;
1057 1057 seqnum_t head;
1058 1058 seqnum_t tail;
1059 1059 seqnum_t sn;
1060 1060 seqnum_t desc_head;
1061 1061 int tx_ring_size = dp->gc.gc_tx_ring_size;
1062 1062 uint_t (*tx_desc_stat)(struct gem_dev *dp,
1063 1063 int slot, int ndesc) = dp->gc.gc_tx_desc_stat;
1064 1064 clock_t now;
1065 1065
1066 1066 now = ddi_get_lbolt();
1067 1067 if (now == (clock_t)0) {
1068 1068 /* make non-zero timestamp */
1069 1069 now--;
1070 1070 }
1071 1071
1072 1072 mutex_enter(&dp->xmitlock);
1073 1073
1074 1074 head = dp->tx_active_head;
1075 1075 tail = dp->tx_active_tail;
1076 1076
1077 1077 #if GEM_DEBUG_LEVEL > 2
1078 1078 if (head != tail) {
1079 1079 cmn_err(CE_CONT, "!%s: %s: "
1080 1080 "testing active_head:%d[%d], active_tail:%d[%d]",
1081 1081 dp->name, __func__,
1082 1082 head, SLOT(head, dp->gc.gc_tx_buf_size),
1083 1083 tail, SLOT(tail, dp->gc.gc_tx_buf_size));
1084 1084 }
1085 1085 #endif
1086 1086 #ifdef DEBUG
1087 1087 if (dp->tx_reclaim_busy == 0) {
1088 1088 /* check tx buffer management consistency */
1089 1089 ASSERT(dp->tx_free_tail - dp->tx_active_head
1090 1090 == dp->gc.gc_tx_buf_limit);
1091 1091 /* EMPTY */
1092 1092 }
1093 1093 #endif
1094 1094 dp->tx_reclaim_busy++;
1095 1095
1096 1096 /* sync all active HW descriptors */
1097 1097 gem_tx_desc_dma_sync(dp,
1098 1098 SLOT(dp->tx_desc_head, tx_ring_size),
1099 1099 dp->tx_desc_tail - dp->tx_desc_head,
1100 1100 DDI_DMA_SYNC_FORKERNEL);
1101 1101
1102 1102 tbp = GET_TXBUF(dp, head);
1103 1103 desc_head = dp->tx_desc_head;
1104 1104 for (sn = head; sn != tail;
1105 1105 dp->tx_active_head = (++sn), tbp = tbp->txb_next) {
1106 1106 int ndescs;
1107 1107
1108 1108 ASSERT(tbp->txb_desc == desc_head);
1109 1109
1110 1110 ndescs = tbp->txb_ndescs;
1111 1111 if (ndescs == 0) {
1112 1112 /* skip errored descriptors */
1113 1113 continue;
1114 1114 }
1115 1115 txstat = (*tx_desc_stat)(dp,
1116 1116 SLOT(tbp->txb_desc, tx_ring_size), ndescs);
1117 1117
1118 1118 if (txstat == 0) {
1119 1119 /* not transmitted yet */
1120 1120 break;
1121 1121 }
1122 1122
1123 1123 if (!dp->tx_blocked && (tbp->txb_flag & GEM_TXFLAG_INTR)) {
1124 1124 dp->tx_blocked = now;
1125 1125 }
1126 1126
1127 1127 ASSERT(txstat & (GEM_TX_DONE | GEM_TX_ERR));
1128 1128
1129 1129 if (txstat & GEM_TX_ERR) {
1130 1130 err = GEM_FAILURE;
1131 1131 cmn_err(CE_WARN, "!%s: tx error at desc %d[%d]",
1132 1132 dp->name, sn, SLOT(sn, tx_ring_size));
1133 1133 }
1134 1134 #if GEM_DEBUG_LEVEL > 4
1135 1135 if (now - tbp->txb_stime >= 50) {
1136 1136 cmn_err(CE_WARN, "!%s: tx delay while %d mS",
1137 1137 dp->name, (now - tbp->txb_stime)*10);
1138 1138 }
1139 1139 #endif
1140 1140 /* free transmitted descriptors */
1141 1141 desc_head += ndescs;
1142 1142 }
1143 1143
1144 1144 if (dp->tx_desc_head != desc_head) {
1145 1145 /* we have reclaimed one or more tx buffers */
1146 1146 dp->tx_desc_head = desc_head;
1147 1147
1148 1148 /* If we passed the next interrupt position, update it */
1149 1149 if (desc_head - dp->tx_desc_intr > 0) {
1150 1150 dp->tx_desc_intr = desc_head;
1151 1151 }
1152 1152 }
1153 1153 mutex_exit(&dp->xmitlock);
1154 1154
1155 1155 /* free dma mapping resources associated with transmitted tx buffers */
1156 1156 tbp = GET_TXBUF(dp, head);
1157 1157 tail = sn;
1158 1158 #if GEM_DEBUG_LEVEL > 2
1159 1159 if (head != tail) {
1160 1160 cmn_err(CE_CONT, "%s: freeing head:%d[%d], tail:%d[%d]",
1161 1161 __func__,
1162 1162 head, SLOT(head, dp->gc.gc_tx_buf_size),
1163 1163 tail, SLOT(tail, dp->gc.gc_tx_buf_size));
1164 1164 }
1165 1165 #endif
1166 1166 for (sn = head; sn != tail; sn++, tbp = tbp->txb_next) {
1167 1167 gem_txbuf_free_dma_resources(tbp);
1168 1168 }
1169 1169
1170 1170 /* recycle the tx buffers */
1171 1171 mutex_enter(&dp->xmitlock);
1172 1172 if (--dp->tx_reclaim_busy == 0) {
1173 1173 /* we are the last thread who can update free tail */
1174 1174 #if GEM_DEBUG_LEVEL > 4
1175 1175 /* check all resouces have been deallocated */
1176 1176 sn = dp->tx_free_tail;
1177 1177 tbp = GET_TXBUF(dp, new_tail);
1178 1178 while (sn != dp->tx_active_head + dp->gc.gc_tx_buf_limit) {
1179 1179 if (tbp->txb_nfrags) {
1180 1180 /* in use */
1181 1181 break;
1182 1182 }
1183 1183 ASSERT(tbp->txb_mp == NULL);
1184 1184 tbp = tbp->txb_next;
1185 1185 sn++;
1186 1186 }
1187 1187 ASSERT(dp->tx_active_head + dp->gc.gc_tx_buf_limit == sn);
1188 1188 #endif
1189 1189 dp->tx_free_tail =
1190 1190 dp->tx_active_head + dp->gc.gc_tx_buf_limit;
1191 1191 }
1192 1192 if (!dp->mac_active) {
1193 1193 /* someone may be waiting for me. */
1194 1194 cv_broadcast(&dp->tx_drain_cv);
1195 1195 }
1196 1196 #if GEM_DEBUG_LEVEL > 2
1197 1197 cmn_err(CE_CONT, "!%s: %s: called, "
1198 1198 "free_head:%d free_tail:%d(+%d) added:%d",
1199 1199 dp->name, __func__,
1200 1200 dp->tx_free_head, dp->tx_free_tail,
1201 1201 dp->tx_free_tail - dp->tx_free_head, tail - head);
1202 1202 #endif
1203 1203 mutex_exit(&dp->xmitlock);
1204 1204
1205 1205 return (err);
1206 1206 }
1207 1207 #pragma inline(gem_reclaim_txbuf)
1208 1208
1209 1209
1210 1210 /*
1211 1211 * Make tx descriptors in out-of-order manner
1212 1212 */
1213 1213 static void
1214 1214 gem_tx_load_descs_oo(struct gem_dev *dp,
1215 1215 seqnum_t start_slot, seqnum_t end_slot, uint64_t flags)
1216 1216 {
1217 1217 seqnum_t sn;
1218 1218 struct txbuf *tbp;
1219 1219 int tx_ring_size = dp->gc.gc_tx_ring_size;
1220 1220 int (*tx_desc_write)
1221 1221 (struct gem_dev *dp, int slot,
1222 1222 ddi_dma_cookie_t *dmacookie,
1223 1223 int frags, uint64_t flag) = dp->gc.gc_tx_desc_write;
1224 1224 clock_t now = ddi_get_lbolt();
1225 1225
1226 1226 sn = start_slot;
1227 1227 tbp = GET_TXBUF(dp, sn);
1228 1228 do {
1229 1229 #if GEM_DEBUG_LEVEL > 1
1230 1230 if (dp->tx_cnt < 100) {
1231 1231 dp->tx_cnt++;
1232 1232 flags |= GEM_TXFLAG_INTR;
1233 1233 }
1234 1234 #endif
1235 1235 /* write a tx descriptor */
1236 1236 tbp->txb_desc = sn;
1237 1237 tbp->txb_ndescs = (*tx_desc_write)(dp,
1238 1238 SLOT(sn, tx_ring_size),
1239 1239 tbp->txb_dmacookie,
1240 1240 tbp->txb_nfrags, flags | tbp->txb_flag);
1241 1241 tbp->txb_stime = now;
1242 1242 ASSERT(tbp->txb_ndescs == 1);
1243 1243
1244 1244 flags = 0;
1245 1245 sn++;
1246 1246 tbp = tbp->txb_next;
1247 1247 } while (sn != end_slot);
1248 1248 }
1249 1249
1250 1250 __INLINE__
1251 1251 static size_t
1252 1252 gem_setup_txbuf_copy(struct gem_dev *dp, mblk_t *mp, struct txbuf *tbp)
1253 1253 {
1254 1254 size_t min_pkt;
1255 1255 caddr_t bp;
1256 1256 size_t off;
1257 1257 mblk_t *tp;
1258 1258 size_t len;
1259 1259 uint64_t flag;
1260 1260
1261 1261 ASSERT(tbp->txb_mp == NULL);
1262 1262
1263 1263 /* we use bounce buffer for the packet */
1264 1264 min_pkt = ETHERMIN;
1265 1265 bp = tbp->txb_buf;
1266 1266 off = 0;
1267 1267 tp = mp;
1268 1268
1269 1269 flag = tbp->txb_flag;
1270 1270 if (flag & GEM_TXFLAG_SWVTAG) {
1271 1271 /* need to increase min packet size */
1272 1272 min_pkt += VTAG_SIZE;
1273 1273 ASSERT((flag & GEM_TXFLAG_VTAG) == 0);
1274 1274 }
1275 1275
1276 1276 /* copy the rest */
1277 1277 for (; tp; tp = tp->b_cont) {
1278 1278 if ((len = (long)tp->b_wptr - (long)tp->b_rptr) > 0) {
1279 1279 bcopy(tp->b_rptr, &bp[off], len);
1280 1280 off += len;
1281 1281 }
1282 1282 }
1283 1283
1284 1284 if (off < min_pkt &&
1285 1285 (min_pkt > ETHERMIN || !dp->gc.gc_tx_auto_pad)) {
1286 1286 /*
1287 1287 * Extend the packet to minimum packet size explicitly.
1288 1288 * For software vlan packets, we shouldn't use tx autopad
1289 1289 * function because nics may not be aware of vlan.
1290 1290 * we must keep 46 octet of payload even if we use vlan.
1291 1291 */
1292 1292 bzero(&bp[off], min_pkt - off);
1293 1293 off = min_pkt;
1294 1294 }
1295 1295
1296 1296 (void) ddi_dma_sync(tbp->txb_bdh, (off_t)0, off, DDI_DMA_SYNC_FORDEV);
1297 1297
1298 1298 tbp->txb_dmacookie[0].dmac_laddress = tbp->txb_buf_dma;
1299 1299 tbp->txb_dmacookie[0].dmac_size = off;
1300 1300
1301 1301 DPRINTF(2, (CE_CONT,
1302 1302 "!%s: %s: copy: addr:0x%llx len:0x%x, vtag:0x%04x, min_pkt:%d",
1303 1303 dp->name, __func__,
1304 1304 tbp->txb_dmacookie[0].dmac_laddress,
1305 1305 tbp->txb_dmacookie[0].dmac_size,
1306 1306 (flag & GEM_TXFLAG_VTAG) >> GEM_TXFLAG_VTAG_SHIFT,
1307 1307 min_pkt));
1308 1308
1309 1309 /* save misc info */
1310 1310 tbp->txb_mp = mp;
1311 1311 tbp->txb_nfrags = 1;
1312 1312 #ifdef DEBUG_MULTIFRAGS
1313 1313 if (dp->gc.gc_tx_max_frags >= 3 &&
1314 1314 tbp->txb_dmacookie[0].dmac_size > 16*3) {
1315 1315 tbp->txb_dmacookie[1].dmac_laddress =
1316 1316 tbp->txb_dmacookie[0].dmac_laddress + 16;
1317 1317 tbp->txb_dmacookie[2].dmac_laddress =
1318 1318 tbp->txb_dmacookie[1].dmac_laddress + 16;
1319 1319
1320 1320 tbp->txb_dmacookie[2].dmac_size =
1321 1321 tbp->txb_dmacookie[0].dmac_size - 16*2;
1322 1322 tbp->txb_dmacookie[1].dmac_size = 16;
1323 1323 tbp->txb_dmacookie[0].dmac_size = 16;
1324 1324 tbp->txb_nfrags = 3;
1325 1325 }
1326 1326 #endif
1327 1327 return (off);
1328 1328 }
1329 1329 #pragma inline(gem_setup_txbuf_copy)
1330 1330
1331 1331 __INLINE__
1332 1332 static void
1333 1333 gem_tx_start_unit(struct gem_dev *dp)
1334 1334 {
1335 1335 seqnum_t head;
1336 1336 seqnum_t tail;
1337 1337 struct txbuf *tbp_head;
1338 1338 struct txbuf *tbp_tail;
1339 1339
1340 1340 /* update HW descriptors from soft queue */
1341 1341 ASSERT(mutex_owned(&dp->xmitlock));
1342 1342 ASSERT(dp->tx_softq_head == dp->tx_active_tail);
1343 1343
1344 1344 head = dp->tx_softq_head;
1345 1345 tail = dp->tx_softq_tail;
1346 1346
1347 1347 DPRINTF(1, (CE_CONT,
1348 1348 "%s: %s: called, softq %d %d[+%d], desc %d %d[+%d]",
1349 1349 dp->name, __func__, head, tail, tail - head,
1350 1350 dp->tx_desc_head, dp->tx_desc_tail,
1351 1351 dp->tx_desc_tail - dp->tx_desc_head));
1352 1352
1353 1353 ASSERT(tail - head > 0);
1354 1354
1355 1355 dp->tx_desc_tail = tail;
1356 1356
1357 1357 tbp_head = GET_TXBUF(dp, head);
1358 1358 tbp_tail = GET_TXBUF(dp, tail - 1);
1359 1359
1360 1360 ASSERT(tbp_tail->txb_desc + tbp_tail->txb_ndescs == dp->tx_desc_tail);
1361 1361
1362 1362 dp->gc.gc_tx_start(dp,
1363 1363 SLOT(tbp_head->txb_desc, dp->gc.gc_tx_ring_size),
1364 1364 tbp_tail->txb_desc + tbp_tail->txb_ndescs - tbp_head->txb_desc);
1365 1365
1366 1366 /* advance softq head and active tail */
1367 1367 dp->tx_softq_head = dp->tx_active_tail = tail;
1368 1368 }
1369 1369 #pragma inline(gem_tx_start_unit)
1370 1370
1371 1371 #ifdef GEM_DEBUG_LEVEL
1372 1372 static int gem_send_cnt[10];
1373 1373 #endif
1374 1374 #define PKT_MIN_SIZE (sizeof (struct ether_header) + 10 + VTAG_SIZE)
1375 1375 #define EHLEN (sizeof (struct ether_header))
1376 1376 /*
1377 1377 * check ether packet type and ip protocol
1378 1378 */
1379 1379 static uint64_t
1380 1380 gem_txbuf_options(struct gem_dev *dp, mblk_t *mp, uint8_t *bp)
1381 1381 {
1382 1382 mblk_t *tp;
1383 1383 ssize_t len;
1384 1384 uint_t vtag;
1385 1385 int off;
1386 1386 uint64_t flag;
1387 1387
1388 1388 flag = 0ULL;
1389 1389
1390 1390 /*
1391 1391 * prepare continuous header of the packet for protocol analysis
1392 1392 */
1393 1393 if ((long)mp->b_wptr - (long)mp->b_rptr < PKT_MIN_SIZE) {
1394 1394 /* we use work buffer to copy mblk */
1395 1395 for (tp = mp, off = 0;
1396 1396 tp && (off < PKT_MIN_SIZE);
1397 1397 tp = tp->b_cont, off += len) {
1398 1398 len = (long)tp->b_wptr - (long)tp->b_rptr;
1399 1399 len = min(len, PKT_MIN_SIZE - off);
1400 1400 bcopy(tp->b_rptr, &bp[off], len);
1401 1401 }
1402 1402 } else {
1403 1403 /* we can use mblk without copy */
1404 1404 bp = mp->b_rptr;
1405 1405 }
1406 1406
1407 1407 /* process vlan tag for GLD v3 */
1408 1408 if (GET_NET16(&bp[VTAG_OFF]) == VTAG_TPID) {
1409 1409 if (dp->misc_flag & GEM_VLAN_HARD) {
1410 1410 vtag = GET_NET16(&bp[VTAG_OFF + 2]);
1411 1411 ASSERT(vtag);
1412 1412 flag |= vtag << GEM_TXFLAG_VTAG_SHIFT;
1413 1413 } else {
1414 1414 flag |= GEM_TXFLAG_SWVTAG;
1415 1415 }
1416 1416 }
1417 1417 return (flag);
1418 1418 }
1419 1419 #undef EHLEN
1420 1420 #undef PKT_MIN_SIZE
1421 1421 /*
1422 1422 * gem_send_common is an exported function because hw depend routines may
1423 1423 * use it for sending control frames like setup frames for 2114x chipset.
1424 1424 */
1425 1425 mblk_t *
1426 1426 gem_send_common(struct gem_dev *dp, mblk_t *mp_head, uint32_t flags)
1427 1427 {
1428 1428 int nmblk;
1429 1429 int avail;
1430 1430 mblk_t *tp;
1431 1431 mblk_t *mp;
1432 1432 int i;
1433 1433 struct txbuf *tbp;
1434 1434 seqnum_t head;
1435 1435 uint64_t load_flags;
1436 1436 uint64_t len_total = 0;
1437 1437 uint32_t bcast = 0;
1438 1438 uint32_t mcast = 0;
1439 1439
1440 1440 ASSERT(mp_head != NULL);
1441 1441
1442 1442 mp = mp_head;
1443 1443 nmblk = 1;
1444 1444 while ((mp = mp->b_next) != NULL) {
1445 1445 nmblk++;
1446 1446 }
1447 1447 #ifdef GEM_DEBUG_LEVEL
1448 1448 gem_send_cnt[0]++;
1449 1449 gem_send_cnt[min(nmblk, 9)]++;
1450 1450 #endif
1451 1451 /*
1452 1452 * Aquire resources
1453 1453 */
1454 1454 mutex_enter(&dp->xmitlock);
1455 1455 if (dp->mac_suspended) {
1456 1456 mutex_exit(&dp->xmitlock);
1457 1457 mp = mp_head;
1458 1458 while (mp) {
1459 1459 tp = mp->b_next;
1460 1460 freemsg(mp);
1461 1461 mp = tp;
1462 1462 }
1463 1463 return (NULL);
1464 1464 }
1465 1465
1466 1466 if (!dp->mac_active && (flags & GEM_SEND_CTRL) == 0) {
1467 1467 /* don't send data packets while mac isn't active */
1468 1468 /* XXX - should we discard packets? */
1469 1469 mutex_exit(&dp->xmitlock);
1470 1470 return (mp_head);
1471 1471 }
1472 1472
1473 1473 /* allocate free slots */
1474 1474 head = dp->tx_free_head;
1475 1475 avail = dp->tx_free_tail - head;
1476 1476
1477 1477 DPRINTF(2, (CE_CONT,
1478 1478 "!%s: %s: called, free_head:%d free_tail:%d(+%d) req:%d",
1479 1479 dp->name, __func__,
1480 1480 dp->tx_free_head, dp->tx_free_tail, avail, nmblk));
1481 1481
1482 1482 avail = min(avail, dp->tx_max_packets);
1483 1483
1484 1484 if (nmblk > avail) {
1485 1485 if (avail == 0) {
1486 1486 /* no resources; short cut */
1487 1487 DPRINTF(2, (CE_CONT, "!%s: no resources", __func__));
1488 1488 dp->tx_max_packets = max(dp->tx_max_packets - 1, 1);
1489 1489 goto done;
1490 1490 }
1491 1491 nmblk = avail;
1492 1492 }
1493 1493
1494 1494 dp->tx_free_head = head + nmblk;
1495 1495 load_flags = ((dp->tx_busy++) == 0) ? GEM_TXFLAG_HEAD : 0;
1496 1496
1497 1497 /* update last interrupt position if tx buffers exhaust. */
1498 1498 if (nmblk == avail) {
1499 1499 tbp = GET_TXBUF(dp, head + avail - 1);
1500 1500 tbp->txb_flag = GEM_TXFLAG_INTR;
1501 1501 dp->tx_desc_intr = head + avail;
1502 1502 }
1503 1503 mutex_exit(&dp->xmitlock);
1504 1504
1505 1505 tbp = GET_TXBUF(dp, head);
1506 1506
1507 1507 for (i = nmblk; i > 0; i--, tbp = tbp->txb_next) {
1508 1508 uint8_t *bp;
1509 1509 uint64_t txflag;
1510 1510
1511 1511 /* remove one from the mblk list */
1512 1512 ASSERT(mp_head != NULL);
1513 1513 mp = mp_head;
1514 1514 mp_head = mp_head->b_next;
1515 1515 mp->b_next = NULL;
1516 1516
1517 1517 /* statistics for non-unicast packets */
1518 1518 bp = mp->b_rptr;
1519 1519 if ((bp[0] & 1) && (flags & GEM_SEND_CTRL) == 0) {
1520 1520 if (bcmp(bp, gem_etherbroadcastaddr.ether_addr_octet,
1521 1521 ETHERADDRL) == 0) {
1522 1522 bcast++;
1523 1523 } else {
1524 1524 mcast++;
1525 1525 }
1526 1526 }
1527 1527
1528 1528 /* save misc info */
1529 1529 txflag = tbp->txb_flag;
1530 1530 txflag |= (flags & GEM_SEND_CTRL) << GEM_TXFLAG_PRIVATE_SHIFT;
1531 1531 txflag |= gem_txbuf_options(dp, mp, (uint8_t *)tbp->txb_buf);
1532 1532 tbp->txb_flag = txflag;
1533 1533
1534 1534 len_total += gem_setup_txbuf_copy(dp, mp, tbp);
1535 1535 }
1536 1536
1537 1537 (void) gem_tx_load_descs_oo(dp, head, head + nmblk, load_flags);
1538 1538
1539 1539 /* Append the tbp at the tail of the active tx buffer list */
1540 1540 mutex_enter(&dp->xmitlock);
1541 1541
1542 1542 if ((--dp->tx_busy) == 0) {
1543 1543 /* extend the tail of softq, as new packets have been ready. */
1544 1544 dp->tx_softq_tail = dp->tx_free_head;
1545 1545
1546 1546 if (!dp->mac_active && (flags & GEM_SEND_CTRL) == 0) {
1547 1547 /*
1548 1548 * The device status has changed while we are
1549 1549 * preparing tx buf.
1550 1550 * As we are the last one that make tx non-busy.
1551 1551 * wake up someone who may wait for us.
1552 1552 */
1553 1553 cv_broadcast(&dp->tx_drain_cv);
1554 1554 } else {
1555 1555 ASSERT(dp->tx_softq_tail - dp->tx_softq_head > 0);
1556 1556 gem_tx_start_unit(dp);
1557 1557 }
1558 1558 }
1559 1559 dp->stats.obytes += len_total;
1560 1560 dp->stats.opackets += nmblk;
1561 1561 dp->stats.obcast += bcast;
1562 1562 dp->stats.omcast += mcast;
1563 1563 done:
1564 1564 mutex_exit(&dp->xmitlock);
1565 1565
1566 1566 return (mp_head);
1567 1567 }
1568 1568
1569 1569 /* ========================================================== */
1570 1570 /*
1571 1571 * error detection and restart routines
1572 1572 */
1573 1573 /* ========================================================== */
1574 1574 int
1575 1575 gem_restart_nic(struct gem_dev *dp, uint_t flags)
1576 1576 {
1577 1577 ASSERT(mutex_owned(&dp->intrlock));
1578 1578
1579 1579 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
1580 1580 #ifdef GEM_DEBUG_LEVEL
1581 1581 #if GEM_DEBUG_LEVEL > 1
1582 1582 gem_dump_txbuf(dp, CE_CONT, "gem_restart_nic");
1583 1583 #endif
1584 1584 #endif
1585 1585
1586 1586 if (dp->mac_suspended) {
1587 1587 /* should we return GEM_FAILURE ? */
1588 1588 return (GEM_FAILURE);
1589 1589 }
1590 1590
1591 1591 /*
1592 1592 * We should avoid calling any routines except xxx_chip_reset
1593 1593 * when we are resuming the system.
1594 1594 */
1595 1595 if (dp->mac_active) {
1596 1596 if (flags & GEM_RESTART_KEEP_BUF) {
1597 1597 /* stop rx gracefully */
1598 1598 dp->rxmode &= ~RXMODE_ENABLE;
1599 1599 (void) (*dp->gc.gc_set_rx_filter)(dp);
1600 1600 }
1601 1601 (void) gem_mac_stop(dp, flags);
1602 1602 }
1603 1603
1604 1604 /* reset the chip. */
1605 1605 if ((*dp->gc.gc_reset_chip)(dp) != GEM_SUCCESS) {
1606 1606 cmn_err(CE_WARN, "%s: %s: failed to reset chip",
1607 1607 dp->name, __func__);
1608 1608 goto err;
1609 1609 }
1610 1610
1611 1611 if (gem_mac_init(dp) != GEM_SUCCESS) {
1612 1612 goto err;
1613 1613 }
1614 1614
1615 1615 /* setup media mode if the link have been up */
1616 1616 if (dp->mii_state == MII_STATE_LINKUP) {
1617 1617 if ((dp->gc.gc_set_media)(dp) != GEM_SUCCESS) {
1618 1618 goto err;
1619 1619 }
1620 1620 }
1621 1621
1622 1622 /* setup mac address and enable rx filter */
1623 1623 dp->rxmode |= RXMODE_ENABLE;
1624 1624 if ((*dp->gc.gc_set_rx_filter)(dp) != GEM_SUCCESS) {
1625 1625 goto err;
1626 1626 }
1627 1627
1628 1628 /*
1629 1629 * XXX - a panic happened because of linkdown.
1630 1630 * We must check mii_state here, because the link can be down just
1631 1631 * before the restart event happen. If the link is down now,
1632 1632 * gem_mac_start() will be called from gem_mii_link_check() when
1633 1633 * the link become up later.
1634 1634 */
1635 1635 if (dp->mii_state == MII_STATE_LINKUP) {
1636 1636 /* restart the nic */
1637 1637 ASSERT(!dp->mac_active);
1638 1638 (void) gem_mac_start(dp);
1639 1639 }
1640 1640 return (GEM_SUCCESS);
1641 1641 err:
1642 1642 return (GEM_FAILURE);
1643 1643 }
1644 1644
1645 1645
1646 1646 static void
1647 1647 gem_tx_timeout(struct gem_dev *dp)
1648 1648 {
1649 1649 clock_t now;
1650 1650 boolean_t tx_sched;
1651 1651 struct txbuf *tbp;
1652 1652
1653 1653 mutex_enter(&dp->intrlock);
1654 1654
1655 1655 tx_sched = B_FALSE;
1656 1656 now = ddi_get_lbolt();
1657 1657
1658 1658 mutex_enter(&dp->xmitlock);
1659 1659 if (!dp->mac_active || dp->mii_state != MII_STATE_LINKUP) {
1660 1660 mutex_exit(&dp->xmitlock);
1661 1661 goto schedule_next;
1662 1662 }
1663 1663 mutex_exit(&dp->xmitlock);
1664 1664
1665 1665 /* reclaim transmitted buffers to check the trasmitter hangs or not. */
1666 1666 if (gem_reclaim_txbuf(dp) != GEM_SUCCESS) {
1667 1667 /* tx error happened, reset transmitter in the chip */
1668 1668 (void) gem_restart_nic(dp, 0);
1669 1669 tx_sched = B_TRUE;
1670 1670 dp->tx_blocked = (clock_t)0;
1671 1671
1672 1672 goto schedule_next;
1673 1673 }
1674 1674
1675 1675 mutex_enter(&dp->xmitlock);
1676 1676 /* check if the transmitter thread is stuck */
1677 1677 if (dp->tx_active_head == dp->tx_active_tail) {
1678 1678 /* no tx buffer is loaded to the nic */
1679 1679 if (dp->tx_blocked &&
1680 1680 now - dp->tx_blocked > dp->gc.gc_tx_timeout_interval) {
1681 1681 gem_dump_txbuf(dp, CE_WARN,
1682 1682 "gem_tx_timeout: tx blocked");
1683 1683 tx_sched = B_TRUE;
1684 1684 dp->tx_blocked = (clock_t)0;
1685 1685 }
1686 1686 mutex_exit(&dp->xmitlock);
1687 1687 goto schedule_next;
1688 1688 }
1689 1689
1690 1690 tbp = GET_TXBUF(dp, dp->tx_active_head);
1691 1691 if (now - tbp->txb_stime < dp->gc.gc_tx_timeout) {
1692 1692 mutex_exit(&dp->xmitlock);
1693 1693 goto schedule_next;
1694 1694 }
1695 1695 mutex_exit(&dp->xmitlock);
1696 1696
1697 1697 gem_dump_txbuf(dp, CE_WARN, "gem_tx_timeout: tx timeout");
1698 1698
1699 1699 /* discard untransmitted packet and restart tx. */
1700 1700 (void) gem_restart_nic(dp, GEM_RESTART_NOWAIT);
1701 1701 tx_sched = B_TRUE;
1702 1702 dp->tx_blocked = (clock_t)0;
1703 1703
1704 1704 schedule_next:
1705 1705 mutex_exit(&dp->intrlock);
1706 1706
1707 1707 /* restart the downstream if needed */
1708 1708 if (tx_sched) {
1709 1709 mac_tx_update(dp->mh);
1710 1710 }
1711 1711
1712 1712 DPRINTF(4, (CE_CONT,
1713 1713 "!%s: blocked:%d active_head:%d active_tail:%d desc_intr:%d",
1714 1714 dp->name, BOOLEAN(dp->tx_blocked),
1715 1715 dp->tx_active_head, dp->tx_active_tail, dp->tx_desc_intr));
1716 1716 dp->timeout_id =
1717 1717 timeout((void (*)(void *))gem_tx_timeout,
1718 1718 (void *)dp, dp->gc.gc_tx_timeout_interval);
1719 1719 }
1720 1720
1721 1721 /* ================================================================== */
1722 1722 /*
1723 1723 * Interrupt handler
1724 1724 */
1725 1725 /* ================================================================== */
1726 1726 __INLINE__
1727 1727 static void
1728 1728 gem_append_rxbuf(struct gem_dev *dp, struct rxbuf *rbp_head)
1729 1729 {
1730 1730 struct rxbuf *rbp;
1731 1731 seqnum_t tail;
1732 1732 int rx_ring_size = dp->gc.gc_rx_ring_size;
1733 1733
1734 1734 ASSERT(rbp_head != NULL);
1735 1735 ASSERT(mutex_owned(&dp->intrlock));
1736 1736
1737 1737 DPRINTF(3, (CE_CONT, "!%s: %s: slot_head:%d, slot_tail:%d",
1738 1738 dp->name, __func__, dp->rx_active_head, dp->rx_active_tail));
1739 1739
1740 1740 /*
1741 1741 * Add new buffers into active rx buffer list
1742 1742 */
1743 1743 if (dp->rx_buf_head == NULL) {
1744 1744 dp->rx_buf_head = rbp_head;
1745 1745 ASSERT(dp->rx_buf_tail == NULL);
1746 1746 } else {
1747 1747 dp->rx_buf_tail->rxb_next = rbp_head;
1748 1748 }
1749 1749
1750 1750 tail = dp->rx_active_tail;
1751 1751 for (rbp = rbp_head; rbp; rbp = rbp->rxb_next) {
1752 1752 /* need to notify the tail for the lower layer */
1753 1753 dp->rx_buf_tail = rbp;
1754 1754
1755 1755 dp->gc.gc_rx_desc_write(dp,
1756 1756 SLOT(tail, rx_ring_size),
1757 1757 rbp->rxb_dmacookie,
1758 1758 rbp->rxb_nfrags);
1759 1759
1760 1760 dp->rx_active_tail = tail = tail + 1;
1761 1761 }
1762 1762 }
1763 1763 #pragma inline(gem_append_rxbuf)
1764 1764
1765 1765 mblk_t *
1766 1766 gem_get_packet_default(struct gem_dev *dp, struct rxbuf *rbp, size_t len)
1767 1767 {
1768 1768 int rx_header_len = dp->gc.gc_rx_header_len;
1769 1769 uint8_t *bp;
1770 1770 mblk_t *mp;
1771 1771
1772 1772 /* allocate a new mblk */
1773 1773 if (mp = allocb(len + VTAG_SIZE, BPRI_MED)) {
1774 1774 ASSERT(mp->b_next == NULL);
1775 1775 ASSERT(mp->b_cont == NULL);
1776 1776
1777 1777 mp->b_rptr += VTAG_SIZE;
1778 1778 bp = mp->b_rptr;
1779 1779 mp->b_wptr = bp + len;
1780 1780
1781 1781 /*
1782 1782 * flush the range of the entire buffer to invalidate
1783 1783 * all of corresponding dirty entries in iocache.
1784 1784 */
1785 1785 (void) ddi_dma_sync(rbp->rxb_dh, rx_header_len,
1786 1786 0, DDI_DMA_SYNC_FORKERNEL);
1787 1787
1788 1788 bcopy(rbp->rxb_buf + rx_header_len, bp, len);
1789 1789 }
1790 1790 return (mp);
1791 1791 }
1792 1792
1793 1793 #ifdef GEM_DEBUG_LEVEL
1794 1794 uint_t gem_rx_pkts[17];
1795 1795 #endif
1796 1796
1797 1797
1798 1798 int
1799 1799 gem_receive(struct gem_dev *dp)
1800 1800 {
1801 1801 uint64_t len_total = 0;
1802 1802 struct rxbuf *rbp;
1803 1803 mblk_t *mp;
1804 1804 int cnt = 0;
1805 1805 uint64_t rxstat;
1806 1806 struct rxbuf *newbufs;
1807 1807 struct rxbuf **newbufs_tailp;
1808 1808 mblk_t *rx_head;
1809 1809 mblk_t **rx_tailp;
1810 1810 int rx_ring_size = dp->gc.gc_rx_ring_size;
1811 1811 seqnum_t active_head;
1812 1812 uint64_t (*rx_desc_stat)(struct gem_dev *dp,
1813 1813 int slot, int ndesc);
1814 1814 int ethermin = ETHERMIN;
1815 1815 int ethermax = dp->mtu + sizeof (struct ether_header);
1816 1816 int rx_header_len = dp->gc.gc_rx_header_len;
1817 1817
1818 1818 ASSERT(mutex_owned(&dp->intrlock));
1819 1819
1820 1820 DPRINTF(3, (CE_CONT, "!%s: gem_receive: rx_buf_head:%p",
1821 1821 dp->name, dp->rx_buf_head));
1822 1822
1823 1823 rx_desc_stat = dp->gc.gc_rx_desc_stat;
1824 1824 newbufs_tailp = &newbufs;
1825 1825 rx_tailp = &rx_head;
1826 1826 for (active_head = dp->rx_active_head;
1827 1827 (rbp = dp->rx_buf_head) != NULL; active_head++) {
1828 1828 int len;
1829 1829 if (cnt == 0) {
1830 1830 cnt = max(dp->poll_pkt_delay*2, 10);
1831 1831 cnt = min(cnt,
1832 1832 dp->rx_active_tail - active_head);
1833 1833 gem_rx_desc_dma_sync(dp,
1834 1834 SLOT(active_head, rx_ring_size),
1835 1835 cnt,
1836 1836 DDI_DMA_SYNC_FORKERNEL);
1837 1837 }
1838 1838
1839 1839 if (rx_header_len > 0) {
1840 1840 (void) ddi_dma_sync(rbp->rxb_dh, 0,
1841 1841 rx_header_len, DDI_DMA_SYNC_FORKERNEL);
1842 1842 }
1843 1843
1844 1844 if (((rxstat = (*rx_desc_stat)(dp,
1845 1845 SLOT(active_head, rx_ring_size),
1846 1846 rbp->rxb_nfrags))
1847 1847 & (GEM_RX_DONE | GEM_RX_ERR)) == 0) {
1848 1848 /* not received yet */
1849 1849 break;
1850 1850 }
1851 1851
1852 1852 /* Remove the head of the rx buffer list */
1853 1853 dp->rx_buf_head = rbp->rxb_next;
1854 1854 cnt--;
1855 1855
1856 1856
1857 1857 if (rxstat & GEM_RX_ERR) {
1858 1858 goto next;
1859 1859 }
1860 1860
1861 1861 len = rxstat & GEM_RX_LEN;
1862 1862 DPRINTF(3, (CE_CONT, "!%s: %s: rxstat:0x%llx, len:0x%x",
1863 1863 dp->name, __func__, rxstat, len));
1864 1864
1865 1865 /*
1866 1866 * Copy the packet
1867 1867 */
1868 1868 if ((mp = dp->gc.gc_get_packet(dp, rbp, len)) == NULL) {
1869 1869 /* no memory, discard the packet */
1870 1870 dp->stats.norcvbuf++;
1871 1871 goto next;
1872 1872 }
1873 1873
1874 1874 /*
1875 1875 * Process VLAN tag
1876 1876 */
1877 1877 ethermin = ETHERMIN;
1878 1878 ethermax = dp->mtu + sizeof (struct ether_header);
1879 1879 if (GET_NET16(mp->b_rptr + VTAG_OFF) == VTAG_TPID) {
1880 1880 ethermax += VTAG_SIZE;
1881 1881 }
1882 1882
1883 1883 /* check packet size */
1884 1884 if (len < ethermin) {
1885 1885 dp->stats.errrcv++;
1886 1886 dp->stats.runt++;
1887 1887 freemsg(mp);
1888 1888 goto next;
1889 1889 }
1890 1890
1891 1891 if (len > ethermax) {
1892 1892 dp->stats.errrcv++;
1893 1893 dp->stats.frame_too_long++;
1894 1894 freemsg(mp);
1895 1895 goto next;
1896 1896 }
1897 1897
1898 1898 len_total += len;
1899 1899
1900 1900 #ifdef GEM_DEBUG_VLAN
1901 1901 if (GET_ETHERTYPE(mp->b_rptr) == VTAG_TPID) {
1902 1902 gem_dump_packet(dp, (char *)__func__, mp, B_TRUE);
1903 1903 }
1904 1904 #endif
1905 1905 /* append received packet to temporaly rx buffer list */
1906 1906 *rx_tailp = mp;
1907 1907 rx_tailp = &mp->b_next;
1908 1908
1909 1909 if (mp->b_rptr[0] & 1) {
1910 1910 if (bcmp(mp->b_rptr,
1911 1911 gem_etherbroadcastaddr.ether_addr_octet,
1912 1912 ETHERADDRL) == 0) {
1913 1913 dp->stats.rbcast++;
1914 1914 } else {
1915 1915 dp->stats.rmcast++;
1916 1916 }
1917 1917 }
1918 1918 next:
1919 1919 ASSERT(rbp != NULL);
1920 1920
1921 1921 /* append new one to temporal new buffer list */
1922 1922 *newbufs_tailp = rbp;
1923 1923 newbufs_tailp = &rbp->rxb_next;
1924 1924 }
1925 1925
1926 1926 /* advance rx_active_head */
1927 1927 if ((cnt = active_head - dp->rx_active_head) > 0) {
1928 1928 dp->stats.rbytes += len_total;
1929 1929 dp->stats.rpackets += cnt;
1930 1930 }
1931 1931 dp->rx_active_head = active_head;
1932 1932
1933 1933 /* terminate the working list */
1934 1934 *newbufs_tailp = NULL;
1935 1935 *rx_tailp = NULL;
1936 1936
1937 1937 if (dp->rx_buf_head == NULL) {
1938 1938 dp->rx_buf_tail = NULL;
1939 1939 }
1940 1940
1941 1941 DPRINTF(4, (CE_CONT, "%s: %s: cnt:%d, rx_head:%p",
1942 1942 dp->name, __func__, cnt, rx_head));
1943 1943
1944 1944 if (newbufs) {
1945 1945 /*
1946 1946 * fillfull rx list with new buffers
1947 1947 */
1948 1948 seqnum_t head;
1949 1949
1950 1950 /* save current tail */
1951 1951 head = dp->rx_active_tail;
1952 1952 gem_append_rxbuf(dp, newbufs);
1953 1953
1954 1954 /* call hw depend start routine if we have. */
1955 1955 dp->gc.gc_rx_start(dp,
1956 1956 SLOT(head, rx_ring_size), dp->rx_active_tail - head);
1957 1957 }
1958 1958
1959 1959 if (rx_head) {
1960 1960 /*
1961 1961 * send up received packets
1962 1962 */
1963 1963 mutex_exit(&dp->intrlock);
1964 1964 mac_rx(dp->mh, NULL, rx_head);
1965 1965 mutex_enter(&dp->intrlock);
1966 1966 }
1967 1967
1968 1968 #ifdef GEM_DEBUG_LEVEL
1969 1969 gem_rx_pkts[min(cnt, sizeof (gem_rx_pkts)/sizeof (uint_t)-1)]++;
1970 1970 #endif
1971 1971 return (cnt);
1972 1972 }
1973 1973
1974 1974 boolean_t
1975 1975 gem_tx_done(struct gem_dev *dp)
1976 1976 {
1977 1977 boolean_t tx_sched = B_FALSE;
1978 1978
1979 1979 if (gem_reclaim_txbuf(dp) != GEM_SUCCESS) {
1980 1980 (void) gem_restart_nic(dp, GEM_RESTART_KEEP_BUF);
1981 1981 DPRINTF(2, (CE_CONT, "!%s: gem_tx_done: tx_desc: %d %d",
1982 1982 dp->name, dp->tx_active_head, dp->tx_active_tail));
1983 1983 tx_sched = B_TRUE;
1984 1984 goto x;
1985 1985 }
1986 1986
1987 1987 mutex_enter(&dp->xmitlock);
1988 1988
1989 1989 /* XXX - we must not have any packets in soft queue */
1990 1990 ASSERT(dp->tx_softq_head == dp->tx_softq_tail);
1991 1991 /*
1992 1992 * If we won't have chance to get more free tx buffers, and blocked,
1993 1993 * it is worth to reschedule the downstream i.e. tx side.
1994 1994 */
1995 1995 ASSERT(dp->tx_desc_intr - dp->tx_desc_head >= 0);
1996 1996 if (dp->tx_blocked && dp->tx_desc_intr == dp->tx_desc_head) {
1997 1997 /*
1998 1998 * As no further tx-done interrupts are scheduled, this
1999 1999 * is the last chance to kick tx side, which may be
2000 2000 * blocked now, otherwise the tx side never works again.
2001 2001 */
2002 2002 tx_sched = B_TRUE;
2003 2003 dp->tx_blocked = (clock_t)0;
2004 2004 dp->tx_max_packets =
2005 2005 min(dp->tx_max_packets + 2, dp->gc.gc_tx_buf_limit);
2006 2006 }
2007 2007
2008 2008 mutex_exit(&dp->xmitlock);
2009 2009
2010 2010 DPRINTF(3, (CE_CONT, "!%s: %s: ret: blocked:%d",
2011 2011 dp->name, __func__, BOOLEAN(dp->tx_blocked)));
2012 2012 x:
2013 2013 return (tx_sched);
2014 2014 }
2015 2015
2016 2016 static uint_t
2017 2017 gem_intr(struct gem_dev *dp)
2018 2018 {
2019 2019 uint_t ret;
2020 2020
2021 2021 mutex_enter(&dp->intrlock);
2022 2022 if (dp->mac_suspended) {
2023 2023 mutex_exit(&dp->intrlock);
2024 2024 return (DDI_INTR_UNCLAIMED);
2025 2025 }
2026 2026 dp->intr_busy = B_TRUE;
2027 2027
2028 2028 ret = (*dp->gc.gc_interrupt)(dp);
2029 2029
2030 2030 if (ret == DDI_INTR_UNCLAIMED) {
2031 2031 dp->intr_busy = B_FALSE;
2032 2032 mutex_exit(&dp->intrlock);
2033 2033 return (ret);
2034 2034 }
2035 2035
2036 2036 if (!dp->mac_active) {
2037 2037 cv_broadcast(&dp->tx_drain_cv);
2038 2038 }
2039 2039
2040 2040
2041 2041 dp->stats.intr++;
2042 2042 dp->intr_busy = B_FALSE;
2043 2043
2044 2044 mutex_exit(&dp->intrlock);
2045 2045
2046 2046 if (ret & INTR_RESTART_TX) {
2047 2047 DPRINTF(4, (CE_CONT, "!%s: calling mac_tx_update", dp->name));
2048 2048 mac_tx_update(dp->mh);
2049 2049 ret &= ~INTR_RESTART_TX;
2050 2050 }
2051 2051 return (ret);
2052 2052 }
2053 2053
2054 2054 static void
2055 2055 gem_intr_watcher(struct gem_dev *dp)
2056 2056 {
2057 2057 (void) gem_intr(dp);
2058 2058
2059 2059 /* schedule next call of tu_intr_watcher */
2060 2060 dp->intr_watcher_id =
2061 2061 timeout((void (*)(void *))gem_intr_watcher, (void *)dp, 1);
2062 2062 }
2063 2063
2064 2064 /* ======================================================================== */
2065 2065 /*
2066 2066 * MII support routines
2067 2067 */
2068 2068 /* ======================================================================== */
2069 2069 static void
2070 2070 gem_choose_forcedmode(struct gem_dev *dp)
2071 2071 {
2072 2072 /* choose media mode */
2073 2073 if (dp->anadv_1000fdx || dp->anadv_1000hdx) {
2074 2074 dp->speed = GEM_SPD_1000;
2075 2075 dp->full_duplex = dp->anadv_1000fdx;
2076 2076 } else if (dp->anadv_100fdx || dp->anadv_100t4) {
2077 2077 dp->speed = GEM_SPD_100;
2078 2078 dp->full_duplex = B_TRUE;
2079 2079 } else if (dp->anadv_100hdx) {
2080 2080 dp->speed = GEM_SPD_100;
2081 2081 dp->full_duplex = B_FALSE;
2082 2082 } else {
2083 2083 dp->speed = GEM_SPD_10;
2084 2084 dp->full_duplex = dp->anadv_10fdx;
2085 2085 }
2086 2086 }
2087 2087
2088 2088 uint16_t
2089 2089 gem_mii_read(struct gem_dev *dp, uint_t reg)
2090 2090 {
2091 2091 if ((dp->mii_status & MII_STATUS_MFPRMBLSUPR) == 0) {
2092 2092 (*dp->gc.gc_mii_sync)(dp);
2093 2093 }
2094 2094 return ((*dp->gc.gc_mii_read)(dp, reg));
2095 2095 }
2096 2096
2097 2097 void
2098 2098 gem_mii_write(struct gem_dev *dp, uint_t reg, uint16_t val)
2099 2099 {
2100 2100 if ((dp->mii_status & MII_STATUS_MFPRMBLSUPR) == 0) {
2101 2101 (*dp->gc.gc_mii_sync)(dp);
2102 2102 }
2103 2103 (*dp->gc.gc_mii_write)(dp, reg, val);
2104 2104 }
2105 2105
2106 2106 #define fc_cap_decode(x) \
2107 2107 ((((x) & MII_ABILITY_PAUSE) ? 1 : 0) | \
2108 2108 (((x) & MII_ABILITY_ASMPAUSE) ? 2 : 0))
2109 2109
2110 2110 int
2111 2111 gem_mii_config_default(struct gem_dev *dp)
2112 2112 {
2113 2113 uint16_t mii_stat;
2114 2114 uint16_t val;
2115 2115 static uint16_t fc_cap_encode[4] = {
2116 2116 0, /* none */
2117 2117 MII_ABILITY_PAUSE, /* symmetric */
2118 2118 MII_ABILITY_ASMPAUSE, /* tx */
2119 2119 MII_ABILITY_PAUSE | MII_ABILITY_ASMPAUSE, /* rx-symmetric */
2120 2120 };
2121 2121
2122 2122 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
2123 2123
2124 2124 /*
2125 2125 * Configure bits in advertisement register
2126 2126 */
2127 2127 mii_stat = dp->mii_status;
2128 2128
2129 2129 DPRINTF(1, (CE_CONT, "!%s: %s: MII_STATUS reg:%b",
2130 2130 dp->name, __func__, mii_stat, MII_STATUS_BITS));
2131 2131
2132 2132 if ((mii_stat & MII_STATUS_ABILITY_TECH) == 0) {
2133 2133 /* it's funny */
2134 2134 cmn_err(CE_WARN, "!%s: wrong ability bits: mii_status:%b",
2135 2135 dp->name, mii_stat, MII_STATUS_BITS);
2136 2136 return (GEM_FAILURE);
2137 2137 }
2138 2138
2139 2139 /* Do not change the rest of the ability bits in the advert reg */
2140 2140 val = gem_mii_read(dp, MII_AN_ADVERT) & ~MII_ABILITY_ALL;
2141 2141
2142 2142 DPRINTF(0, (CE_CONT,
2143 2143 "!%s: %s: 100T4:%d 100F:%d 100H:%d 10F:%d 10H:%d",
2144 2144 dp->name, __func__,
2145 2145 dp->anadv_100t4, dp->anadv_100fdx, dp->anadv_100hdx,
2146 2146 dp->anadv_10fdx, dp->anadv_10hdx));
2147 2147
2148 2148 if (dp->anadv_100t4) {
2149 2149 val |= MII_ABILITY_100BASE_T4;
2150 2150 }
2151 2151 if (dp->anadv_100fdx) {
2152 2152 val |= MII_ABILITY_100BASE_TX_FD;
2153 2153 }
2154 2154 if (dp->anadv_100hdx) {
2155 2155 val |= MII_ABILITY_100BASE_TX;
2156 2156 }
2157 2157 if (dp->anadv_10fdx) {
2158 2158 val |= MII_ABILITY_10BASE_T_FD;
2159 2159 }
2160 2160 if (dp->anadv_10hdx) {
2161 2161 val |= MII_ABILITY_10BASE_T;
2162 2162 }
2163 2163
2164 2164 /* set flow control capability */
2165 2165 val |= fc_cap_encode[dp->anadv_flow_control];
2166 2166
2167 2167 DPRINTF(0, (CE_CONT,
2168 2168 "!%s: %s: setting MII_AN_ADVERT reg:%b, mii_mode:%d, fc:%d",
2169 2169 dp->name, __func__, val, MII_ABILITY_BITS, dp->gc.gc_mii_mode,
2170 2170 dp->anadv_flow_control));
2171 2171
2172 2172 gem_mii_write(dp, MII_AN_ADVERT, val);
2173 2173
2174 2174 if (mii_stat & MII_STATUS_XSTATUS) {
2175 2175 /*
2176 2176 * 1000Base-T GMII support
2177 2177 */
2178 2178 if (!dp->anadv_autoneg) {
2179 2179 /* enable manual configuration */
2180 2180 val = MII_1000TC_CFG_EN;
2181 2181 } else {
2182 2182 val = 0;
2183 2183 if (dp->anadv_1000fdx) {
2184 2184 val |= MII_1000TC_ADV_FULL;
2185 2185 }
2186 2186 if (dp->anadv_1000hdx) {
2187 2187 val |= MII_1000TC_ADV_HALF;
2188 2188 }
2189 2189 }
2190 2190 DPRINTF(0, (CE_CONT,
2191 2191 "!%s: %s: setting MII_1000TC reg:%b",
2192 2192 dp->name, __func__, val, MII_1000TC_BITS));
2193 2193
2194 2194 gem_mii_write(dp, MII_1000TC, val);
2195 2195 }
2196 2196
2197 2197 return (GEM_SUCCESS);
2198 2198 }
2199 2199
2200 2200 #define GEM_LINKUP(dp) mac_link_update((dp)->mh, LINK_STATE_UP)
2201 2201 #define GEM_LINKDOWN(dp) mac_link_update((dp)->mh, LINK_STATE_DOWN)
2202 2202
2203 2203 static uint8_t gem_fc_result[4 /* my cap */ ][4 /* lp cap */] = {
2204 2204 /* none symm tx rx/symm */
2205 2205 /* none */
2206 2206 {FLOW_CONTROL_NONE,
2207 2207 FLOW_CONTROL_NONE,
2208 2208 FLOW_CONTROL_NONE,
2209 2209 FLOW_CONTROL_NONE},
2210 2210 /* sym */
2211 2211 {FLOW_CONTROL_NONE,
2212 2212 FLOW_CONTROL_SYMMETRIC,
2213 2213 FLOW_CONTROL_NONE,
2214 2214 FLOW_CONTROL_SYMMETRIC},
2215 2215 /* tx */
2216 2216 {FLOW_CONTROL_NONE,
2217 2217 FLOW_CONTROL_NONE,
2218 2218 FLOW_CONTROL_NONE,
2219 2219 FLOW_CONTROL_TX_PAUSE},
2220 2220 /* rx/symm */
2221 2221 {FLOW_CONTROL_NONE,
2222 2222 FLOW_CONTROL_SYMMETRIC,
2223 2223 FLOW_CONTROL_RX_PAUSE,
2224 2224 FLOW_CONTROL_SYMMETRIC},
2225 2225 };
2226 2226
2227 2227 static char *gem_fc_type[] = {
2228 2228 "without",
2229 2229 "with symmetric",
2230 2230 "with tx",
2231 2231 "with rx",
2232 2232 };
2233 2233
2234 2234 boolean_t
2235 2235 gem_mii_link_check(struct gem_dev *dp)
2236 2236 {
2237 2237 uint16_t old_mii_state;
2238 2238 boolean_t tx_sched = B_FALSE;
2239 2239 uint16_t status;
2240 2240 uint16_t advert;
2241 2241 uint16_t lpable;
2242 2242 uint16_t exp;
2243 2243 uint16_t ctl1000;
2244 2244 uint16_t stat1000;
2245 2245 uint16_t val;
2246 2246 clock_t now;
2247 2247 clock_t diff;
2248 2248 int linkdown_action;
2249 2249 boolean_t fix_phy = B_FALSE;
2250 2250
2251 2251 now = ddi_get_lbolt();
2252 2252 old_mii_state = dp->mii_state;
2253 2253
2254 2254 DPRINTF(3, (CE_CONT, "!%s: %s: time:%d state:%d",
2255 2255 dp->name, __func__, now, dp->mii_state));
2256 2256
2257 2257 diff = now - dp->mii_last_check;
2258 2258 dp->mii_last_check = now;
2259 2259
2260 2260 /*
2261 2261 * For NWAM, don't show linkdown state right
2262 2262 * after the system boots
2263 2263 */
2264 2264 if (dp->linkup_delay > 0) {
2265 2265 if (dp->linkup_delay > diff) {
2266 2266 dp->linkup_delay -= diff;
2267 2267 } else {
2268 2268 /* link up timeout */
2269 2269 dp->linkup_delay = -1;
2270 2270 }
2271 2271 }
2272 2272
2273 2273 next_nowait:
2274 2274 switch (dp->mii_state) {
2275 2275 case MII_STATE_UNKNOWN:
2276 2276 /* power-up, DP83840 requires 32 sync bits */
2277 2277 (*dp->gc.gc_mii_sync)(dp);
2278 2278 goto reset_phy;
2279 2279
2280 2280 case MII_STATE_RESETTING:
2281 2281 dp->mii_timer -= diff;
2282 2282 if (dp->mii_timer > 0) {
2283 2283 /* don't read phy registers in resetting */
2284 2284 dp->mii_interval = WATCH_INTERVAL_FAST;
2285 2285 goto next;
2286 2286 }
2287 2287
2288 2288 /* Timer expired, ensure reset bit is not set */
2289 2289
2290 2290 if (dp->mii_status & MII_STATUS_MFPRMBLSUPR) {
2291 2291 /* some phys need sync bits after reset */
2292 2292 (*dp->gc.gc_mii_sync)(dp);
2293 2293 }
2294 2294 val = gem_mii_read(dp, MII_CONTROL);
2295 2295 if (val & MII_CONTROL_RESET) {
2296 2296 cmn_err(CE_NOTE,
2297 2297 "!%s: time:%ld resetting phy not complete."
2298 2298 " mii_control:0x%b",
2299 2299 dp->name, ddi_get_lbolt(),
2300 2300 val, MII_CONTROL_BITS);
2301 2301 }
2302 2302
2303 2303 /* ensure neither isolated nor pwrdown nor auto-nego mode */
2304 2304 /* XXX -- this operation is required for NS DP83840A. */
2305 2305 gem_mii_write(dp, MII_CONTROL, 0);
2306 2306
2307 2307 /* As resetting PHY has completed, configure PHY registers */
2308 2308 if ((*dp->gc.gc_mii_config)(dp) != GEM_SUCCESS) {
2309 2309 /* we failed to configure PHY. */
2310 2310 goto reset_phy;
2311 2311 }
2312 2312
2313 2313 /* mii_config may disable autonegatiation */
2314 2314 gem_choose_forcedmode(dp);
2315 2315
2316 2316 dp->mii_lpable = 0;
2317 2317 dp->mii_advert = 0;
2318 2318 dp->mii_exp = 0;
2319 2319 dp->mii_ctl1000 = 0;
2320 2320 dp->mii_stat1000 = 0;
2321 2321 dp->flow_control = FLOW_CONTROL_NONE;
2322 2322
2323 2323 if (!dp->anadv_autoneg) {
2324 2324 /* skip auto-negotiation phase */
2325 2325 dp->mii_state = MII_STATE_MEDIA_SETUP;
2326 2326 dp->mii_timer = 0;
2327 2327 dp->mii_interval = 0;
2328 2328 goto next_nowait;
2329 2329 }
2330 2330
2331 2331 /* Issue auto-negotiation command */
2332 2332 goto autonego;
2333 2333
2334 2334 case MII_STATE_AUTONEGOTIATING:
2335 2335 /*
2336 2336 * Autonegotiation is in progress
2337 2337 */
2338 2338 dp->mii_timer -= diff;
2339 2339 if (dp->mii_timer -
2340 2340 (dp->gc.gc_mii_an_timeout
2341 2341 - dp->gc.gc_mii_an_wait) > 0) {
2342 2342 /*
2343 2343 * wait for a while, typically autonegotiation
2344 2344 * completes in 2.3 - 2.5 sec.
2345 2345 */
2346 2346 dp->mii_interval = WATCH_INTERVAL_FAST;
2347 2347 goto next;
2348 2348 }
2349 2349
2350 2350 /* read PHY status */
2351 2351 status = gem_mii_read(dp, MII_STATUS);
2352 2352 DPRINTF(4, (CE_CONT,
2353 2353 "!%s: %s: called: mii_state:%d MII_STATUS reg:%b",
2354 2354 dp->name, __func__, dp->mii_state,
2355 2355 status, MII_STATUS_BITS));
2356 2356
2357 2357 if (status & MII_STATUS_REMFAULT) {
2358 2358 /*
2359 2359 * The link parnert told me something wrong happend.
2360 2360 * What do we do ?
2361 2361 */
2362 2362 cmn_err(CE_CONT,
2363 2363 "!%s: auto-negotiation failed: remote fault",
2364 2364 dp->name);
2365 2365 goto autonego;
2366 2366 }
2367 2367
2368 2368 if ((status & MII_STATUS_ANDONE) == 0) {
2369 2369 if (dp->mii_timer <= 0) {
2370 2370 /*
2371 2371 * Auto-negotiation was timed out,
2372 2372 * try again w/o resetting phy.
2373 2373 */
2374 2374 if (!dp->mii_supress_msg) {
2375 2375 cmn_err(CE_WARN,
2376 2376 "!%s: auto-negotiation failed: timeout",
2377 2377 dp->name);
2378 2378 dp->mii_supress_msg = B_TRUE;
2379 2379 }
2380 2380 goto autonego;
2381 2381 }
2382 2382 /*
2383 2383 * Auto-negotiation is in progress. Wait.
2384 2384 */
2385 2385 dp->mii_interval = dp->gc.gc_mii_an_watch_interval;
2386 2386 goto next;
2387 2387 }
2388 2388
2389 2389 /*
2390 2390 * Auto-negotiation have completed.
2391 2391 * Assume linkdown and fall through.
2392 2392 */
2393 2393 dp->mii_supress_msg = B_FALSE;
2394 2394 dp->mii_state = MII_STATE_AN_DONE;
2395 2395 DPRINTF(0, (CE_CONT,
2396 2396 "!%s: auto-negotiation completed, MII_STATUS:%b",
2397 2397 dp->name, status, MII_STATUS_BITS));
2398 2398
2399 2399 if (dp->gc.gc_mii_an_delay > 0) {
2400 2400 dp->mii_timer = dp->gc.gc_mii_an_delay;
2401 2401 dp->mii_interval = drv_usectohz(20*1000);
2402 2402 goto next;
2403 2403 }
2404 2404
2405 2405 dp->mii_timer = 0;
2406 2406 diff = 0;
2407 2407 goto next_nowait;
2408 2408
2409 2409 case MII_STATE_AN_DONE:
2410 2410 /*
2411 2411 * Auto-negotiation have done. Now we can set up media.
2412 2412 */
2413 2413 dp->mii_timer -= diff;
2414 2414 if (dp->mii_timer > 0) {
2415 2415 /* wait for a while */
2416 2416 dp->mii_interval = WATCH_INTERVAL_FAST;
2417 2417 goto next;
2418 2418 }
2419 2419
2420 2420 /*
2421 2421 * set up the result of auto negotiation
2422 2422 */
2423 2423
2424 2424 /*
2425 2425 * Read registers required to determin current
2426 2426 * duplex mode and media speed.
2427 2427 */
2428 2428 if (dp->gc.gc_mii_an_delay > 0) {
2429 2429 /*
2430 2430 * As the link watcher context has been suspended,
2431 2431 * 'status' is invalid. We must status register here
2432 2432 */
2433 2433 status = gem_mii_read(dp, MII_STATUS);
2434 2434 }
2435 2435 advert = gem_mii_read(dp, MII_AN_ADVERT);
2436 2436 lpable = gem_mii_read(dp, MII_AN_LPABLE);
2437 2437 exp = gem_mii_read(dp, MII_AN_EXPANSION);
2438 2438 if (exp == 0xffff) {
2439 2439 /* some phys don't have exp register */
2440 2440 exp = 0;
2441 2441 }
2442 2442 ctl1000 = 0;
2443 2443 stat1000 = 0;
2444 2444 if (dp->mii_status & MII_STATUS_XSTATUS) {
2445 2445 ctl1000 = gem_mii_read(dp, MII_1000TC);
2446 2446 stat1000 = gem_mii_read(dp, MII_1000TS);
2447 2447 }
2448 2448 dp->mii_lpable = lpable;
2449 2449 dp->mii_advert = advert;
2450 2450 dp->mii_exp = exp;
2451 2451 dp->mii_ctl1000 = ctl1000;
2452 2452 dp->mii_stat1000 = stat1000;
2453 2453
2454 2454 cmn_err(CE_CONT,
2455 2455 "!%s: auto-negotiation done, advert:%b, lpable:%b, exp:%b",
2456 2456 dp->name,
2457 2457 advert, MII_ABILITY_BITS,
2458 2458 lpable, MII_ABILITY_BITS,
2459 2459 exp, MII_AN_EXP_BITS);
2460 2460
2461 2461 if (dp->mii_status & MII_STATUS_XSTATUS) {
2462 2462 cmn_err(CE_CONT,
2463 2463 "! MII_1000TC:%b, MII_1000TS:%b",
2464 2464 ctl1000, MII_1000TC_BITS,
2465 2465 stat1000, MII_1000TS_BITS);
2466 2466 }
2467 2467
2468 2468 if (gem_population(lpable) <= 1 &&
2469 2469 (exp & MII_AN_EXP_LPCANAN) == 0) {
2470 2470 if ((advert & MII_ABILITY_TECH) != lpable) {
2471 2471 cmn_err(CE_WARN,
2472 2472 "!%s: but the link partnar doesn't seem"
2473 2473 " to have auto-negotiation capability."
2474 2474 " please check the link configuration.",
2475 2475 dp->name);
2476 2476 }
2477 2477 /*
2478 2478 * it should be result of parallel detection, which
2479 2479 * cannot detect duplex mode.
2480 2480 */
2481 2481 if (lpable & MII_ABILITY_100BASE_TX) {
2482 2482 /*
2483 2483 * we prefer full duplex mode for 100Mbps
2484 2484 * connection, if we can.
2485 2485 */
2486 2486 lpable |= advert & MII_ABILITY_100BASE_TX_FD;
2487 2487 }
2488 2488
2489 2489 if ((advert & lpable) == 0 &&
2490 2490 lpable & MII_ABILITY_10BASE_T) {
2491 2491 lpable |= advert & MII_ABILITY_10BASE_T_FD;
2492 2492 }
2493 2493 /*
2494 2494 * as the link partnar isn't auto-negotiatable, use
2495 2495 * fixed mode temporally.
2496 2496 */
2497 2497 fix_phy = B_TRUE;
2498 2498 } else if (lpable == 0) {
2499 2499 cmn_err(CE_WARN, "!%s: wrong lpable.", dp->name);
2500 2500 goto reset_phy;
2501 2501 }
2502 2502 /*
2503 2503 * configure current link mode according to AN priority.
2504 2504 */
2505 2505 val = advert & lpable;
2506 2506 if ((ctl1000 & MII_1000TC_ADV_FULL) &&
2507 2507 (stat1000 & MII_1000TS_LP_FULL)) {
2508 2508 /* 1000BaseT & full duplex */
2509 2509 dp->speed = GEM_SPD_1000;
2510 2510 dp->full_duplex = B_TRUE;
2511 2511 } else if ((ctl1000 & MII_1000TC_ADV_HALF) &&
2512 2512 (stat1000 & MII_1000TS_LP_HALF)) {
2513 2513 /* 1000BaseT & half duplex */
2514 2514 dp->speed = GEM_SPD_1000;
2515 2515 dp->full_duplex = B_FALSE;
2516 2516 } else if (val & MII_ABILITY_100BASE_TX_FD) {
2517 2517 /* 100BaseTx & full duplex */
2518 2518 dp->speed = GEM_SPD_100;
2519 2519 dp->full_duplex = B_TRUE;
2520 2520 } else if (val & MII_ABILITY_100BASE_T4) {
2521 2521 /* 100BaseT4 & full duplex */
2522 2522 dp->speed = GEM_SPD_100;
2523 2523 dp->full_duplex = B_TRUE;
2524 2524 } else if (val & MII_ABILITY_100BASE_TX) {
2525 2525 /* 100BaseTx & half duplex */
2526 2526 dp->speed = GEM_SPD_100;
2527 2527 dp->full_duplex = B_FALSE;
2528 2528 } else if (val & MII_ABILITY_10BASE_T_FD) {
2529 2529 /* 10BaseT & full duplex */
2530 2530 dp->speed = GEM_SPD_10;
2531 2531 dp->full_duplex = B_TRUE;
2532 2532 } else if (val & MII_ABILITY_10BASE_T) {
2533 2533 /* 10BaseT & half duplex */
2534 2534 dp->speed = GEM_SPD_10;
2535 2535 dp->full_duplex = B_FALSE;
2536 2536 } else {
2537 2537 /*
2538 2538 * It seems that the link partnar doesn't have
2539 2539 * auto-negotiation capability and our PHY
2540 2540 * could not report the correct current mode.
2541 2541 * We guess current mode by mii_control register.
2542 2542 */
2543 2543 val = gem_mii_read(dp, MII_CONTROL);
2544 2544
2545 2545 /* select 100m full or 10m half */
2546 2546 dp->speed = (val & MII_CONTROL_100MB) ?
2547 2547 GEM_SPD_100 : GEM_SPD_10;
2548 2548 dp->full_duplex = dp->speed != GEM_SPD_10;
2549 2549 fix_phy = B_TRUE;
2550 2550
2551 2551 cmn_err(CE_NOTE,
2552 2552 "!%s: auto-negotiation done but "
2553 2553 "common ability not found.\n"
2554 2554 "PHY state: control:%b advert:%b lpable:%b\n"
2555 2555 "guessing %d Mbps %s duplex mode",
2556 2556 dp->name,
2557 2557 val, MII_CONTROL_BITS,
2558 2558 advert, MII_ABILITY_BITS,
2559 2559 lpable, MII_ABILITY_BITS,
2560 2560 gem_speed_value[dp->speed],
2561 2561 dp->full_duplex ? "full" : "half");
2562 2562 }
2563 2563
2564 2564 if (dp->full_duplex) {
2565 2565 dp->flow_control =
2566 2566 gem_fc_result[fc_cap_decode(advert)]
2567 2567 [fc_cap_decode(lpable)];
2568 2568 } else {
2569 2569 dp->flow_control = FLOW_CONTROL_NONE;
2570 2570 }
2571 2571 dp->mii_state = MII_STATE_MEDIA_SETUP;
2572 2572 /* FALLTHROUGH */
2573 2573
2574 2574 case MII_STATE_MEDIA_SETUP:
2575 2575 dp->mii_state = MII_STATE_LINKDOWN;
2576 2576 dp->mii_timer = dp->gc.gc_mii_linkdown_timeout;
2577 2577 DPRINTF(2, (CE_CONT, "!%s: setup midia mode done", dp->name));
2578 2578 dp->mii_supress_msg = B_FALSE;
2579 2579
2580 2580 /* use short interval */
2581 2581 dp->mii_interval = WATCH_INTERVAL_FAST;
2582 2582
2583 2583 if ((!dp->anadv_autoneg) ||
2584 2584 dp->gc.gc_mii_an_oneshot || fix_phy) {
2585 2585
2586 2586 /*
2587 2587 * write specified mode to phy.
2588 2588 */
2589 2589 val = gem_mii_read(dp, MII_CONTROL);
2590 2590 val &= ~(MII_CONTROL_SPEED | MII_CONTROL_FDUPLEX |
2591 2591 MII_CONTROL_ANE | MII_CONTROL_RSAN);
2592 2592
2593 2593 if (dp->full_duplex) {
2594 2594 val |= MII_CONTROL_FDUPLEX;
2595 2595 }
2596 2596
2597 2597 switch (dp->speed) {
2598 2598 case GEM_SPD_1000:
2599 2599 val |= MII_CONTROL_1000MB;
2600 2600 break;
2601 2601
2602 2602 case GEM_SPD_100:
2603 2603 val |= MII_CONTROL_100MB;
2604 2604 break;
2605 2605
2606 2606 default:
2607 2607 cmn_err(CE_WARN, "%s: unknown speed:%d",
2608 2608 dp->name, dp->speed);
2609 2609 /* FALLTHROUGH */
2610 2610 case GEM_SPD_10:
2611 2611 /* for GEM_SPD_10, do nothing */
2612 2612 break;
2613 2613 }
2614 2614
2615 2615 if (dp->mii_status & MII_STATUS_XSTATUS) {
2616 2616 gem_mii_write(dp,
2617 2617 MII_1000TC, MII_1000TC_CFG_EN);
2618 2618 }
2619 2619 gem_mii_write(dp, MII_CONTROL, val);
2620 2620 }
2621 2621
2622 2622 if (dp->nic_state >= NIC_STATE_INITIALIZED) {
2623 2623 /* notify the result of auto-negotiation to mac */
2624 2624 (*dp->gc.gc_set_media)(dp);
2625 2625 }
2626 2626
2627 2627 if ((void *)dp->gc.gc_mii_tune_phy) {
2628 2628 /* for built-in sis900 */
2629 2629 /* XXX - this code should be removed. */
2630 2630 (*dp->gc.gc_mii_tune_phy)(dp);
2631 2631 }
2632 2632
2633 2633 goto next_nowait;
2634 2634
2635 2635 case MII_STATE_LINKDOWN:
2636 2636 status = gem_mii_read(dp, MII_STATUS);
2637 2637 if (status & MII_STATUS_LINKUP) {
2638 2638 /*
2639 2639 * Link going up
2640 2640 */
2641 2641 dp->mii_state = MII_STATE_LINKUP;
2642 2642 dp->mii_supress_msg = B_FALSE;
2643 2643
2644 2644 DPRINTF(0, (CE_CONT,
2645 2645 "!%s: link up detected: mii_stat:%b",
2646 2646 dp->name, status, MII_STATUS_BITS));
2647 2647
2648 2648 /*
2649 2649 * MII_CONTROL_100MB and MII_CONTROL_FDUPLEX are
2650 2650 * ignored when MII_CONTROL_ANE is set.
2651 2651 */
2652 2652 cmn_err(CE_CONT,
2653 2653 "!%s: Link up: %d Mbps %s duplex %s flow control",
2654 2654 dp->name,
2655 2655 gem_speed_value[dp->speed],
2656 2656 dp->full_duplex ? "full" : "half",
2657 2657 gem_fc_type[dp->flow_control]);
2658 2658
2659 2659 dp->mii_interval = dp->gc.gc_mii_link_watch_interval;
2660 2660
2661 2661 /* XXX - we need other timer to watch statictics */
2662 2662 if (dp->gc.gc_mii_hw_link_detection &&
2663 2663 dp->nic_state == NIC_STATE_ONLINE) {
2664 2664 dp->mii_interval = 0;
2665 2665 }
2666 2666
2667 2667 if (dp->nic_state == NIC_STATE_ONLINE) {
2668 2668 if (!dp->mac_active) {
2669 2669 (void) gem_mac_start(dp);
2670 2670 }
2671 2671 tx_sched = B_TRUE;
2672 2672 }
2673 2673 goto next;
2674 2674 }
2675 2675
2676 2676 dp->mii_supress_msg = B_TRUE;
2677 2677 if (dp->anadv_autoneg) {
2678 2678 dp->mii_timer -= diff;
2679 2679 if (dp->mii_timer <= 0) {
2680 2680 /*
2681 2681 * link down timer expired.
2682 2682 * need to restart auto-negotiation.
2683 2683 */
2684 2684 linkdown_action =
2685 2685 dp->gc.gc_mii_linkdown_timeout_action;
2686 2686 goto restart_autonego;
2687 2687 }
2688 2688 }
2689 2689 /* don't change mii_state */
2690 2690 break;
2691 2691
2692 2692 case MII_STATE_LINKUP:
2693 2693 status = gem_mii_read(dp, MII_STATUS);
2694 2694 if ((status & MII_STATUS_LINKUP) == 0) {
2695 2695 /*
2696 2696 * Link going down
2697 2697 */
2698 2698 cmn_err(CE_NOTE,
2699 2699 "!%s: link down detected: mii_stat:%b",
2700 2700 dp->name, status, MII_STATUS_BITS);
2701 2701
2702 2702 if (dp->nic_state == NIC_STATE_ONLINE &&
2703 2703 dp->mac_active &&
2704 2704 dp->gc.gc_mii_stop_mac_on_linkdown) {
2705 2705 (void) gem_mac_stop(dp, 0);
2706 2706
2707 2707 if (dp->tx_blocked) {
2708 2708 /* drain tx */
2709 2709 tx_sched = B_TRUE;
2710 2710 }
2711 2711 }
2712 2712
2713 2713 if (dp->anadv_autoneg) {
2714 2714 /* need to restart auto-negotiation */
2715 2715 linkdown_action = dp->gc.gc_mii_linkdown_action;
2716 2716 goto restart_autonego;
2717 2717 }
2718 2718
2719 2719 dp->mii_state = MII_STATE_LINKDOWN;
2720 2720 dp->mii_timer = dp->gc.gc_mii_linkdown_timeout;
2721 2721
2722 2722 if ((void *)dp->gc.gc_mii_tune_phy) {
2723 2723 /* for built-in sis900 */
2724 2724 (*dp->gc.gc_mii_tune_phy)(dp);
2725 2725 }
2726 2726 dp->mii_interval = dp->gc.gc_mii_link_watch_interval;
2727 2727 goto next;
2728 2728 }
2729 2729
2730 2730 /* don't change mii_state */
2731 2731 if (dp->gc.gc_mii_hw_link_detection &&
2732 2732 dp->nic_state == NIC_STATE_ONLINE) {
2733 2733 dp->mii_interval = 0;
2734 2734 goto next;
2735 2735 }
2736 2736 break;
2737 2737 }
2738 2738 dp->mii_interval = dp->gc.gc_mii_link_watch_interval;
2739 2739 goto next;
2740 2740
2741 2741 /* Actions on the end of state routine */
2742 2742
2743 2743 restart_autonego:
2744 2744 switch (linkdown_action) {
2745 2745 case MII_ACTION_RESET:
2746 2746 if (!dp->mii_supress_msg) {
2747 2747 cmn_err(CE_CONT, "!%s: resetting PHY", dp->name);
2748 2748 }
2749 2749 dp->mii_supress_msg = B_TRUE;
2750 2750 goto reset_phy;
2751 2751
2752 2752 case MII_ACTION_NONE:
2753 2753 dp->mii_supress_msg = B_TRUE;
2754 2754 if (dp->gc.gc_mii_an_oneshot) {
2755 2755 goto autonego;
2756 2756 }
2757 2757 /* PHY will restart autonego automatically */
2758 2758 dp->mii_state = MII_STATE_AUTONEGOTIATING;
2759 2759 dp->mii_timer = dp->gc.gc_mii_an_timeout;
2760 2760 dp->mii_interval = dp->gc.gc_mii_an_watch_interval;
2761 2761 goto next;
2762 2762
2763 2763 case MII_ACTION_RSA:
2764 2764 if (!dp->mii_supress_msg) {
2765 2765 cmn_err(CE_CONT, "!%s: restarting auto-negotiation",
2766 2766 dp->name);
2767 2767 }
2768 2768 dp->mii_supress_msg = B_TRUE;
2769 2769 goto autonego;
2770 2770
2771 2771 default:
2772 2772 cmn_err(CE_WARN, "!%s: unknowm linkdown action: %d",
2773 2773 dp->name, dp->gc.gc_mii_linkdown_action);
2774 2774 dp->mii_supress_msg = B_TRUE;
2775 2775 }
2776 2776 /* NOTREACHED */
2777 2777
2778 2778 reset_phy:
2779 2779 if (!dp->mii_supress_msg) {
2780 2780 cmn_err(CE_CONT, "!%s: resetting PHY", dp->name);
2781 2781 }
2782 2782 dp->mii_state = MII_STATE_RESETTING;
2783 2783 dp->mii_timer = dp->gc.gc_mii_reset_timeout;
2784 2784 if (!dp->gc.gc_mii_dont_reset) {
2785 2785 gem_mii_write(dp, MII_CONTROL, MII_CONTROL_RESET);
2786 2786 }
2787 2787 dp->mii_interval = WATCH_INTERVAL_FAST;
2788 2788 goto next;
2789 2789
2790 2790 autonego:
2791 2791 if (!dp->mii_supress_msg) {
2792 2792 cmn_err(CE_CONT, "!%s: auto-negotiation started", dp->name);
2793 2793 }
2794 2794 dp->mii_state = MII_STATE_AUTONEGOTIATING;
2795 2795 dp->mii_timer = dp->gc.gc_mii_an_timeout;
2796 2796
2797 2797 /* start/restart auto nego */
2798 2798 val = gem_mii_read(dp, MII_CONTROL) &
2799 2799 ~(MII_CONTROL_ISOLATE | MII_CONTROL_PWRDN | MII_CONTROL_RESET);
2800 2800
2801 2801 gem_mii_write(dp, MII_CONTROL,
2802 2802 val | MII_CONTROL_RSAN | MII_CONTROL_ANE);
2803 2803
2804 2804 dp->mii_interval = dp->gc.gc_mii_an_watch_interval;
2805 2805
2806 2806 next:
2807 2807 if (dp->link_watcher_id == 0 && dp->mii_interval) {
2808 2808 /* we must schedule next mii_watcher */
2809 2809 dp->link_watcher_id =
2810 2810 timeout((void (*)(void *))&gem_mii_link_watcher,
2811 2811 (void *)dp, dp->mii_interval);
2812 2812 }
2813 2813
2814 2814 if (old_mii_state != dp->mii_state) {
2815 2815 /* notify new mii link state */
2816 2816 if (dp->mii_state == MII_STATE_LINKUP) {
2817 2817 dp->linkup_delay = 0;
2818 2818 GEM_LINKUP(dp);
2819 2819 } else if (dp->linkup_delay <= 0) {
2820 2820 GEM_LINKDOWN(dp);
2821 2821 }
2822 2822 } else if (dp->linkup_delay < 0) {
2823 2823 /* first linkup timeout */
2824 2824 dp->linkup_delay = 0;
2825 2825 GEM_LINKDOWN(dp);
2826 2826 }
2827 2827
2828 2828 return (tx_sched);
2829 2829 }
2830 2830
2831 2831 static void
2832 2832 gem_mii_link_watcher(struct gem_dev *dp)
2833 2833 {
2834 2834 boolean_t tx_sched;
2835 2835
2836 2836 mutex_enter(&dp->intrlock);
2837 2837
2838 2838 dp->link_watcher_id = 0;
2839 2839 tx_sched = gem_mii_link_check(dp);
2840 2840 #if GEM_DEBUG_LEVEL > 2
2841 2841 if (dp->link_watcher_id == 0) {
2842 2842 cmn_err(CE_CONT, "%s: link watcher stopped", dp->name);
2843 2843 }
2844 2844 #endif
2845 2845 mutex_exit(&dp->intrlock);
2846 2846
2847 2847 if (tx_sched) {
2848 2848 /* kick potentially stopped downstream */
2849 2849 mac_tx_update(dp->mh);
2850 2850 }
2851 2851 }
2852 2852
2853 2853 int
2854 2854 gem_mii_probe_default(struct gem_dev *dp)
2855 2855 {
2856 2856 int8_t phy;
2857 2857 uint16_t status;
2858 2858 uint16_t adv;
2859 2859 uint16_t adv_org;
2860 2860
2861 2861 DPRINTF(3, (CE_CONT, "!%s: %s: called", dp->name, __func__));
2862 2862
2863 2863 /*
2864 2864 * Scan PHY
2865 2865 */
2866 2866 /* ensure to send sync bits */
2867 2867 dp->mii_status = 0;
2868 2868
2869 2869 /* Try default phy first */
2870 2870 if (dp->mii_phy_addr) {
2871 2871 status = gem_mii_read(dp, MII_STATUS);
2872 2872 if (status != 0xffff && status != 0) {
2873 2873 gem_mii_write(dp, MII_CONTROL, 0);
2874 2874 goto PHY_found;
2875 2875 }
2876 2876
2877 2877 if (dp->mii_phy_addr < 0) {
2878 2878 cmn_err(CE_NOTE,
2879 2879 "!%s: failed to probe default internal and/or non-MII PHY",
2880 2880 dp->name);
2881 2881 return (GEM_FAILURE);
2882 2882 }
2883 2883
2884 2884 cmn_err(CE_NOTE,
2885 2885 "!%s: failed to probe default MII PHY at %d",
2886 2886 dp->name, dp->mii_phy_addr);
2887 2887 }
2888 2888
2889 2889 /* Try all possible address */
2890 2890 for (phy = dp->gc.gc_mii_addr_min; phy < 32; phy++) {
2891 2891 dp->mii_phy_addr = phy;
2892 2892 status = gem_mii_read(dp, MII_STATUS);
2893 2893
2894 2894 if (status != 0xffff && status != 0) {
2895 2895 gem_mii_write(dp, MII_CONTROL, 0);
2896 2896 goto PHY_found;
2897 2897 }
2898 2898 }
2899 2899
2900 2900 for (phy = dp->gc.gc_mii_addr_min; phy < 32; phy++) {
2901 2901 dp->mii_phy_addr = phy;
2902 2902 gem_mii_write(dp, MII_CONTROL, 0);
2903 2903 status = gem_mii_read(dp, MII_STATUS);
2904 2904
2905 2905 if (status != 0xffff && status != 0) {
2906 2906 goto PHY_found;
2907 2907 }
2908 2908 }
2909 2909
2910 2910 cmn_err(CE_NOTE, "!%s: no MII PHY found", dp->name);
2911 2911 dp->mii_phy_addr = -1;
2912 2912
2913 2913 return (GEM_FAILURE);
2914 2914
2915 2915 PHY_found:
2916 2916 dp->mii_status = status;
2917 2917 dp->mii_phy_id = (gem_mii_read(dp, MII_PHYIDH) << 16) |
2918 2918 gem_mii_read(dp, MII_PHYIDL);
2919 2919
2920 2920 if (dp->mii_phy_addr < 0) {
2921 2921 cmn_err(CE_CONT, "!%s: using internal/non-MII PHY(0x%08x)",
2922 2922 dp->name, dp->mii_phy_id);
2923 2923 } else {
2924 2924 cmn_err(CE_CONT, "!%s: MII PHY (0x%08x) found at %d",
2925 2925 dp->name, dp->mii_phy_id, dp->mii_phy_addr);
2926 2926 }
2927 2927
2928 2928 cmn_err(CE_CONT, "!%s: PHY control:%b, status:%b, advert:%b, lpar:%b",
2929 2929 dp->name,
2930 2930 gem_mii_read(dp, MII_CONTROL), MII_CONTROL_BITS,
2931 2931 status, MII_STATUS_BITS,
2932 2932 gem_mii_read(dp, MII_AN_ADVERT), MII_ABILITY_BITS,
2933 2933 gem_mii_read(dp, MII_AN_LPABLE), MII_ABILITY_BITS);
2934 2934
2935 2935 dp->mii_xstatus = 0;
2936 2936 if (status & MII_STATUS_XSTATUS) {
2937 2937 dp->mii_xstatus = gem_mii_read(dp, MII_XSTATUS);
2938 2938
2939 2939 cmn_err(CE_CONT, "!%s: xstatus:%b",
2940 2940 dp->name, dp->mii_xstatus, MII_XSTATUS_BITS);
2941 2941 }
2942 2942
2943 2943 /* check if the phy can advertize pause abilities */
2944 2944 adv_org = gem_mii_read(dp, MII_AN_ADVERT);
2945 2945
2946 2946 gem_mii_write(dp, MII_AN_ADVERT,
2947 2947 MII_ABILITY_PAUSE | MII_ABILITY_ASMPAUSE);
2948 2948
2949 2949 adv = gem_mii_read(dp, MII_AN_ADVERT);
2950 2950
2951 2951 if ((adv & MII_ABILITY_PAUSE) == 0) {
2952 2952 dp->gc.gc_flow_control &= ~1;
2953 2953 }
2954 2954
2955 2955 if ((adv & MII_ABILITY_ASMPAUSE) == 0) {
2956 2956 dp->gc.gc_flow_control &= ~2;
2957 2957 }
2958 2958
2959 2959 gem_mii_write(dp, MII_AN_ADVERT, adv_org);
2960 2960
2961 2961 return (GEM_SUCCESS);
2962 2962 }
2963 2963
2964 2964 static void
2965 2965 gem_mii_start(struct gem_dev *dp)
2966 2966 {
2967 2967 DPRINTF(3, (CE_CONT, "!%s: %s: called", dp->name, __func__));
2968 2968
2969 2969 /* make a first call of check link */
2970 2970 dp->mii_state = MII_STATE_UNKNOWN;
2971 2971 dp->mii_last_check = ddi_get_lbolt();
2972 2972 dp->linkup_delay = dp->gc.gc_mii_linkdown_timeout;
2973 2973 (void) gem_mii_link_watcher(dp);
2974 2974 }
2975 2975
2976 2976 static void
2977 2977 gem_mii_stop(struct gem_dev *dp)
2978 2978 {
2979 2979 DPRINTF(3, (CE_CONT, "!%s: %s: called", dp->name, __func__));
2980 2980
2981 2981 /* Ensure timer routine stopped */
2982 2982 mutex_enter(&dp->intrlock);
2983 2983 if (dp->link_watcher_id) {
2984 2984 while (untimeout(dp->link_watcher_id) == -1)
2985 2985 ;
2986 2986 dp->link_watcher_id = 0;
2987 2987 }
2988 2988 mutex_exit(&dp->intrlock);
2989 2989 }
2990 2990
2991 2991 boolean_t
2992 2992 gem_get_mac_addr_conf(struct gem_dev *dp)
2993 2993 {
2994 2994 char propname[32];
2995 2995 char *valstr;
2996 2996 uint8_t mac[ETHERADDRL];
2997 2997 char *cp;
2998 2998 int c;
2999 2999 int i;
3000 3000 int j;
3001 3001 uint8_t v;
3002 3002 uint8_t d;
3003 3003 uint8_t ored;
3004 3004
3005 3005 DPRINTF(3, (CE_CONT, "!%s: %s: called", dp->name, __func__));
3006 3006 /*
3007 3007 * Get ethernet address from .conf file
3008 3008 */
3009 3009 (void) sprintf(propname, "mac-addr");
3010 3010 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, dp->dip,
3011 3011 DDI_PROP_DONTPASS, propname, &valstr)) !=
3012 3012 DDI_PROP_SUCCESS) {
3013 3013 return (B_FALSE);
3014 3014 }
3015 3015
3016 3016 if (strlen(valstr) != ETHERADDRL*3-1) {
3017 3017 goto syntax_err;
3018 3018 }
3019 3019
3020 3020 cp = valstr;
3021 3021 j = 0;
3022 3022 ored = 0;
3023 3023 for (;;) {
3024 3024 v = 0;
3025 3025 for (i = 0; i < 2; i++) {
3026 3026 c = *cp++;
3027 3027
3028 3028 if (c >= 'a' && c <= 'f') {
3029 3029 d = c - 'a' + 10;
3030 3030 } else if (c >= 'A' && c <= 'F') {
3031 3031 d = c - 'A' + 10;
3032 3032 } else if (c >= '0' && c <= '9') {
3033 3033 d = c - '0';
3034 3034 } else {
3035 3035 goto syntax_err;
3036 3036 }
3037 3037 v = (v << 4) | d;
3038 3038 }
3039 3039
3040 3040 mac[j++] = v;
3041 3041 ored |= v;
3042 3042 if (j == ETHERADDRL) {
3043 3043 /* done */
3044 3044 break;
3045 3045 }
3046 3046
3047 3047 c = *cp++;
3048 3048 if (c != ':') {
3049 3049 goto syntax_err;
3050 3050 }
3051 3051 }
3052 3052
3053 3053 if (ored == 0) {
3054 3054 goto err;
3055 3055 }
3056 3056 for (i = 0; i < ETHERADDRL; i++) {
3057 3057 dp->dev_addr.ether_addr_octet[i] = mac[i];
3058 3058 }
3059 3059 ddi_prop_free(valstr);
3060 3060 return (B_TRUE);
3061 3061
3062 3062 syntax_err:
3063 3063 cmn_err(CE_CONT,
3064 3064 "!%s: read mac addr: trying .conf: syntax err %s",
3065 3065 dp->name, valstr);
3066 3066 err:
3067 3067 ddi_prop_free(valstr);
3068 3068
3069 3069 return (B_FALSE);
3070 3070 }
3071 3071
3072 3072
3073 3073 /* ============================================================== */
3074 3074 /*
3075 3075 * internal start/stop interface
3076 3076 */
3077 3077 /* ============================================================== */
3078 3078 static int
3079 3079 gem_mac_set_rx_filter(struct gem_dev *dp)
3080 3080 {
3081 3081 return ((*dp->gc.gc_set_rx_filter)(dp));
3082 3082 }
3083 3083
3084 3084 /*
3085 3085 * gem_mac_init: cold start
3086 3086 */
3087 3087 static int
3088 3088 gem_mac_init(struct gem_dev *dp)
3089 3089 {
3090 3090 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
3091 3091
3092 3092 if (dp->mac_suspended) {
3093 3093 return (GEM_FAILURE);
3094 3094 }
3095 3095
3096 3096 dp->mac_active = B_FALSE;
3097 3097
3098 3098 gem_init_rx_ring(dp);
3099 3099 gem_init_tx_ring(dp);
3100 3100
3101 3101 /* reset transmitter state */
3102 3102 dp->tx_blocked = (clock_t)0;
3103 3103 dp->tx_busy = 0;
3104 3104 dp->tx_reclaim_busy = 0;
3105 3105 dp->tx_max_packets = dp->gc.gc_tx_buf_limit;
3106 3106
3107 3107 if ((*dp->gc.gc_init_chip)(dp) != GEM_SUCCESS) {
3108 3108 return (GEM_FAILURE);
3109 3109 }
3110 3110
3111 3111 gem_prepare_rx_buf(dp);
3112 3112
3113 3113 return (GEM_SUCCESS);
3114 3114 }
3115 3115 /*
3116 3116 * gem_mac_start: warm start
3117 3117 */
3118 3118 static int
3119 3119 gem_mac_start(struct gem_dev *dp)
3120 3120 {
3121 3121 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
3122 3122
3123 3123 ASSERT(mutex_owned(&dp->intrlock));
3124 3124 ASSERT(dp->nic_state == NIC_STATE_ONLINE);
3125 3125 ASSERT(dp->mii_state == MII_STATE_LINKUP);
3126 3126
3127 3127 /* enable tx and rx */
3128 3128 mutex_enter(&dp->xmitlock);
3129 3129 if (dp->mac_suspended) {
3130 3130 mutex_exit(&dp->xmitlock);
3131 3131 return (GEM_FAILURE);
3132 3132 }
3133 3133 dp->mac_active = B_TRUE;
3134 3134 mutex_exit(&dp->xmitlock);
3135 3135
3136 3136 /* setup rx buffers */
3137 3137 (*dp->gc.gc_rx_start)(dp,
3138 3138 SLOT(dp->rx_active_head, dp->gc.gc_rx_ring_size),
3139 3139 dp->rx_active_tail - dp->rx_active_head);
3140 3140
3141 3141 if ((*dp->gc.gc_start_chip)(dp) != GEM_SUCCESS) {
3142 3142 cmn_err(CE_WARN, "%s: %s: start_chip: failed",
3143 3143 dp->name, __func__);
3144 3144 return (GEM_FAILURE);
3145 3145 }
3146 3146
3147 3147 mutex_enter(&dp->xmitlock);
3148 3148
3149 3149 /* load untranmitted packets to the nic */
3150 3150 ASSERT(dp->tx_softq_tail - dp->tx_softq_head >= 0);
3151 3151 if (dp->tx_softq_tail - dp->tx_softq_head > 0) {
3152 3152 gem_tx_load_descs_oo(dp,
3153 3153 dp->tx_softq_head, dp->tx_softq_tail,
3154 3154 GEM_TXFLAG_HEAD);
3155 3155 /* issue preloaded tx buffers */
3156 3156 gem_tx_start_unit(dp);
3157 3157 }
3158 3158
3159 3159 mutex_exit(&dp->xmitlock);
3160 3160
3161 3161 return (GEM_SUCCESS);
3162 3162 }
3163 3163
3164 3164 static int
3165 3165 gem_mac_stop(struct gem_dev *dp, uint_t flags)
3166 3166 {
3167 3167 int i;
3168 3168 int wait_time; /* in uS */
3169 3169 #ifdef GEM_DEBUG_LEVEL
3170 3170 clock_t now;
3171 3171 #endif
3172 3172 int ret = GEM_SUCCESS;
3173 3173
3174 3174 DPRINTF(1, (CE_CONT, "!%s: %s: called, rx_buf_free:%d",
3175 3175 dp->name, __func__, dp->rx_buf_freecnt));
3176 3176
3177 3177 ASSERT(mutex_owned(&dp->intrlock));
3178 3178 ASSERT(!mutex_owned(&dp->xmitlock));
3179 3179
3180 3180 /*
3181 3181 * Block transmits
3182 3182 */
3183 3183 mutex_enter(&dp->xmitlock);
3184 3184 if (dp->mac_suspended) {
3185 3185 mutex_exit(&dp->xmitlock);
3186 3186 return (GEM_SUCCESS);
3187 3187 }
3188 3188 dp->mac_active = B_FALSE;
3189 3189
3190 3190 while (dp->tx_busy > 0) {
3191 3191 cv_wait(&dp->tx_drain_cv, &dp->xmitlock);
3192 3192 }
3193 3193 mutex_exit(&dp->xmitlock);
3194 3194
3195 3195 if ((flags & GEM_RESTART_NOWAIT) == 0) {
3196 3196 /*
3197 3197 * Wait for all tx buffers sent.
3198 3198 */
3199 3199 wait_time =
3200 3200 2 * (8 * MAXPKTBUF(dp) / gem_speed_value[dp->speed]) *
3201 3201 (dp->tx_active_tail - dp->tx_active_head);
3202 3202
3203 3203 DPRINTF(0, (CE_CONT, "%s: %s: max drain time: %d uS",
3204 3204 dp->name, __func__, wait_time));
3205 3205 i = 0;
3206 3206 #ifdef GEM_DEBUG_LEVEL
3207 3207 now = ddi_get_lbolt();
3208 3208 #endif
3209 3209 while (dp->tx_active_tail != dp->tx_active_head) {
3210 3210 if (i > wait_time) {
3211 3211 /* timeout */
3212 3212 cmn_err(CE_NOTE, "%s: %s timeout: tx drain",
3213 3213 dp->name, __func__);
3214 3214 break;
3215 3215 }
3216 3216 (void) gem_reclaim_txbuf(dp);
3217 3217 drv_usecwait(100);
3218 3218 i += 100;
3219 3219 }
3220 3220 DPRINTF(0, (CE_NOTE,
3221 3221 "!%s: %s: the nic have drained in %d uS, real %d mS",
3222 3222 dp->name, __func__, i,
3223 3223 10*((int)(ddi_get_lbolt() - now))));
3224 3224 }
3225 3225
3226 3226 /*
3227 3227 * Now we can stop the nic safely.
3228 3228 */
3229 3229 if ((*dp->gc.gc_stop_chip)(dp) != GEM_SUCCESS) {
3230 3230 cmn_err(CE_NOTE, "%s: %s: resetting the chip to stop it",
3231 3231 dp->name, __func__);
3232 3232 if ((*dp->gc.gc_reset_chip)(dp) != GEM_SUCCESS) {
3233 3233 cmn_err(CE_WARN, "%s: %s: failed to reset chip",
3234 3234 dp->name, __func__);
3235 3235 }
3236 3236 }
3237 3237
3238 3238 /*
3239 3239 * Clear all rx buffers
3240 3240 */
3241 3241 if (flags & GEM_RESTART_KEEP_BUF) {
3242 3242 (void) gem_receive(dp);
3243 3243 }
3244 3244 gem_clean_rx_buf(dp);
3245 3245
3246 3246 /*
3247 3247 * Update final statistics
3248 3248 */
3249 3249 (*dp->gc.gc_get_stats)(dp);
3250 3250
3251 3251 /*
3252 3252 * Clear all pended tx packets
3253 3253 */
3254 3254 ASSERT(dp->tx_active_tail == dp->tx_softq_head);
3255 3255 ASSERT(dp->tx_softq_tail == dp->tx_free_head);
3256 3256 if (flags & GEM_RESTART_KEEP_BUF) {
3257 3257 /* restore active tx buffers */
3258 3258 dp->tx_active_tail = dp->tx_active_head;
3259 3259 dp->tx_softq_head = dp->tx_active_head;
3260 3260 } else {
3261 3261 gem_clean_tx_buf(dp);
3262 3262 }
3263 3263
3264 3264 return (ret);
3265 3265 }
3266 3266
3267 3267 static int
3268 3268 gem_add_multicast(struct gem_dev *dp, const uint8_t *ep)
3269 3269 {
3270 3270 int cnt;
3271 3271 int err;
3272 3272
3273 3273 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
3274 3274
3275 3275 mutex_enter(&dp->intrlock);
3276 3276 if (dp->mac_suspended) {
3277 3277 mutex_exit(&dp->intrlock);
3278 3278 return (GEM_FAILURE);
3279 3279 }
3280 3280
3281 3281 if (dp->mc_count_req++ < GEM_MAXMC) {
3282 3282 /* append the new address at the end of the mclist */
3283 3283 cnt = dp->mc_count;
3284 3284 bcopy(ep, dp->mc_list[cnt].addr.ether_addr_octet,
3285 3285 ETHERADDRL);
3286 3286 if (dp->gc.gc_multicast_hash) {
3287 3287 dp->mc_list[cnt].hash =
3288 3288 (*dp->gc.gc_multicast_hash)(dp, (uint8_t *)ep);
3289 3289 }
3290 3290 dp->mc_count = cnt + 1;
3291 3291 }
3292 3292
3293 3293 if (dp->mc_count_req != dp->mc_count) {
3294 3294 /* multicast address list overflow */
3295 3295 dp->rxmode |= RXMODE_MULTI_OVF;
3296 3296 } else {
3297 3297 dp->rxmode &= ~RXMODE_MULTI_OVF;
3298 3298 }
3299 3299
3300 3300 /* tell new multicast list to the hardware */
3301 3301 err = gem_mac_set_rx_filter(dp);
3302 3302
3303 3303 mutex_exit(&dp->intrlock);
3304 3304
3305 3305 return (err);
3306 3306 }
3307 3307
3308 3308 static int
3309 3309 gem_remove_multicast(struct gem_dev *dp, const uint8_t *ep)
3310 3310 {
3311 3311 size_t len;
3312 3312 int i;
3313 3313 int cnt;
3314 3314 int err;
3315 3315
3316 3316 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
3317 3317
3318 3318 mutex_enter(&dp->intrlock);
3319 3319 if (dp->mac_suspended) {
3320 3320 mutex_exit(&dp->intrlock);
3321 3321 return (GEM_FAILURE);
3322 3322 }
3323 3323
3324 3324 dp->mc_count_req--;
3325 3325 cnt = dp->mc_count;
3326 3326 for (i = 0; i < cnt; i++) {
3327 3327 if (bcmp(ep, &dp->mc_list[i].addr, ETHERADDRL)) {
3328 3328 continue;
3329 3329 }
3330 3330 /* shrink the mclist by copying forward */
3331 3331 len = (cnt - (i + 1)) * sizeof (*dp->mc_list);
3332 3332 if (len > 0) {
3333 3333 bcopy(&dp->mc_list[i+1], &dp->mc_list[i], len);
3334 3334 }
3335 3335 dp->mc_count--;
3336 3336 break;
3337 3337 }
3338 3338
3339 3339 if (dp->mc_count_req != dp->mc_count) {
3340 3340 /* multicast address list overflow */
3341 3341 dp->rxmode |= RXMODE_MULTI_OVF;
3342 3342 } else {
3343 3343 dp->rxmode &= ~RXMODE_MULTI_OVF;
3344 3344 }
3345 3345 /* In gem v2, don't hold xmitlock on calling set_rx_filter */
3346 3346 err = gem_mac_set_rx_filter(dp);
3347 3347
3348 3348 mutex_exit(&dp->intrlock);
3349 3349
3350 3350 return (err);
3351 3351 }
3352 3352
3353 3353 /* ============================================================== */
3354 3354 /*
3355 3355 * ND interface
3356 3356 */
3357 3357 /* ============================================================== */
3358 3358 enum {
3359 3359 PARAM_AUTONEG_CAP,
3360 3360 PARAM_PAUSE_CAP,
3361 3361 PARAM_ASYM_PAUSE_CAP,
3362 3362 PARAM_1000FDX_CAP,
3363 3363 PARAM_1000HDX_CAP,
3364 3364 PARAM_100T4_CAP,
3365 3365 PARAM_100FDX_CAP,
3366 3366 PARAM_100HDX_CAP,
3367 3367 PARAM_10FDX_CAP,
3368 3368 PARAM_10HDX_CAP,
3369 3369
3370 3370 PARAM_ADV_AUTONEG_CAP,
3371 3371 PARAM_ADV_PAUSE_CAP,
3372 3372 PARAM_ADV_ASYM_PAUSE_CAP,
3373 3373 PARAM_ADV_1000FDX_CAP,
3374 3374 PARAM_ADV_1000HDX_CAP,
3375 3375 PARAM_ADV_100T4_CAP,
3376 3376 PARAM_ADV_100FDX_CAP,
3377 3377 PARAM_ADV_100HDX_CAP,
3378 3378 PARAM_ADV_10FDX_CAP,
3379 3379 PARAM_ADV_10HDX_CAP,
3380 3380
3381 3381 PARAM_LP_AUTONEG_CAP,
3382 3382 PARAM_LP_PAUSE_CAP,
3383 3383 PARAM_LP_ASYM_PAUSE_CAP,
3384 3384 PARAM_LP_1000FDX_CAP,
3385 3385 PARAM_LP_1000HDX_CAP,
3386 3386 PARAM_LP_100T4_CAP,
3387 3387 PARAM_LP_100FDX_CAP,
3388 3388 PARAM_LP_100HDX_CAP,
3389 3389 PARAM_LP_10FDX_CAP,
3390 3390 PARAM_LP_10HDX_CAP,
3391 3391
3392 3392 PARAM_LINK_STATUS,
3393 3393 PARAM_LINK_SPEED,
3394 3394 PARAM_LINK_DUPLEX,
3395 3395
3396 3396 PARAM_LINK_AUTONEG,
3397 3397 PARAM_LINK_RX_PAUSE,
3398 3398 PARAM_LINK_TX_PAUSE,
3399 3399
3400 3400 PARAM_LOOP_MODE,
3401 3401 PARAM_MSI_CNT,
3402 3402
3403 3403 #ifdef DEBUG_RESUME
3404 3404 PARAM_RESUME_TEST,
3405 3405 #endif
3406 3406 PARAM_COUNT
3407 3407 };
3408 3408
3409 3409 enum ioc_reply {
3410 3410 IOC_INVAL = -1, /* bad, NAK with EINVAL */
3411 3411 IOC_DONE, /* OK, reply sent */
3412 3412 IOC_ACK, /* OK, just send ACK */
3413 3413 IOC_REPLY, /* OK, just send reply */
3414 3414 IOC_RESTART_ACK, /* OK, restart & ACK */
3415 3415 IOC_RESTART_REPLY /* OK, restart & reply */
3416 3416 };
3417 3417
3418 3418 struct gem_nd_arg {
3419 3419 struct gem_dev *dp;
3420 3420 int item;
3421 3421 };
3422 3422
3423 3423 static int
3424 3424 gem_param_get(queue_t *q, mblk_t *mp, caddr_t arg, cred_t *credp)
3425 3425 {
3426 3426 struct gem_dev *dp = ((struct gem_nd_arg *)(void *)arg)->dp;
3427 3427 int item = ((struct gem_nd_arg *)(void *)arg)->item;
3428 3428 long val;
3429 3429
3430 3430 DPRINTF(0, (CE_CONT, "!%s: %s: called, item:%d",
3431 3431 dp->name, __func__, item));
3432 3432
3433 3433 switch (item) {
3434 3434 case PARAM_AUTONEG_CAP:
3435 3435 val = BOOLEAN(dp->mii_status & MII_STATUS_CANAUTONEG);
3436 3436 DPRINTF(0, (CE_CONT, "autoneg_cap:%d", val));
3437 3437 break;
3438 3438
3439 3439 case PARAM_PAUSE_CAP:
3440 3440 val = BOOLEAN(dp->gc.gc_flow_control & 1);
3441 3441 break;
3442 3442
3443 3443 case PARAM_ASYM_PAUSE_CAP:
3444 3444 val = BOOLEAN(dp->gc.gc_flow_control & 2);
3445 3445 break;
3446 3446
3447 3447 case PARAM_1000FDX_CAP:
3448 3448 val = (dp->mii_xstatus & MII_XSTATUS_1000BASET_FD) ||
3449 3449 (dp->mii_xstatus & MII_XSTATUS_1000BASEX_FD);
3450 3450 break;
3451 3451
3452 3452 case PARAM_1000HDX_CAP:
3453 3453 val = (dp->mii_xstatus & MII_XSTATUS_1000BASET) ||
3454 3454 (dp->mii_xstatus & MII_XSTATUS_1000BASEX);
3455 3455 break;
3456 3456
3457 3457 case PARAM_100T4_CAP:
3458 3458 val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);
3459 3459 break;
3460 3460
3461 3461 case PARAM_100FDX_CAP:
3462 3462 val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASEX_FD);
3463 3463 break;
3464 3464
3465 3465 case PARAM_100HDX_CAP:
3466 3466 val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASEX);
3467 3467 break;
3468 3468
3469 3469 case PARAM_10FDX_CAP:
3470 3470 val = BOOLEAN(dp->mii_status & MII_STATUS_10_FD);
3471 3471 break;
3472 3472
3473 3473 case PARAM_10HDX_CAP:
3474 3474 val = BOOLEAN(dp->mii_status & MII_STATUS_10);
3475 3475 break;
3476 3476
3477 3477 case PARAM_ADV_AUTONEG_CAP:
3478 3478 val = dp->anadv_autoneg;
3479 3479 break;
3480 3480
3481 3481 case PARAM_ADV_PAUSE_CAP:
3482 3482 val = BOOLEAN(dp->anadv_flow_control & 1);
3483 3483 break;
3484 3484
3485 3485 case PARAM_ADV_ASYM_PAUSE_CAP:
3486 3486 val = BOOLEAN(dp->anadv_flow_control & 2);
3487 3487 break;
3488 3488
3489 3489 case PARAM_ADV_1000FDX_CAP:
3490 3490 val = dp->anadv_1000fdx;
3491 3491 break;
3492 3492
3493 3493 case PARAM_ADV_1000HDX_CAP:
3494 3494 val = dp->anadv_1000hdx;
3495 3495 break;
3496 3496
3497 3497 case PARAM_ADV_100T4_CAP:
3498 3498 val = dp->anadv_100t4;
3499 3499 break;
3500 3500
3501 3501 case PARAM_ADV_100FDX_CAP:
3502 3502 val = dp->anadv_100fdx;
3503 3503 break;
3504 3504
3505 3505 case PARAM_ADV_100HDX_CAP:
3506 3506 val = dp->anadv_100hdx;
3507 3507 break;
3508 3508
3509 3509 case PARAM_ADV_10FDX_CAP:
3510 3510 val = dp->anadv_10fdx;
3511 3511 break;
3512 3512
3513 3513 case PARAM_ADV_10HDX_CAP:
3514 3514 val = dp->anadv_10hdx;
3515 3515 break;
3516 3516
3517 3517 case PARAM_LP_AUTONEG_CAP:
3518 3518 val = BOOLEAN(dp->mii_exp & MII_AN_EXP_LPCANAN);
3519 3519 break;
3520 3520
3521 3521 case PARAM_LP_PAUSE_CAP:
3522 3522 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_PAUSE);
3523 3523 break;
3524 3524
3525 3525 case PARAM_LP_ASYM_PAUSE_CAP:
3526 3526 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_ASMPAUSE);
3527 3527 break;
3528 3528
3529 3529 case PARAM_LP_1000FDX_CAP:
3530 3530 val = BOOLEAN(dp->mii_stat1000 & MII_1000TS_LP_FULL);
3531 3531 break;
3532 3532
3533 3533 case PARAM_LP_1000HDX_CAP:
3534 3534 val = BOOLEAN(dp->mii_stat1000 & MII_1000TS_LP_HALF);
3535 3535 break;
3536 3536
3537 3537 case PARAM_LP_100T4_CAP:
3538 3538 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_T4);
3539 3539 break;
3540 3540
3541 3541 case PARAM_LP_100FDX_CAP:
3542 3542 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_TX_FD);
3543 3543 break;
3544 3544
3545 3545 case PARAM_LP_100HDX_CAP:
3546 3546 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_TX);
3547 3547 break;
3548 3548
3549 3549 case PARAM_LP_10FDX_CAP:
3550 3550 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_10BASE_T_FD);
3551 3551 break;
3552 3552
3553 3553 case PARAM_LP_10HDX_CAP:
3554 3554 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_10BASE_T);
3555 3555 break;
3556 3556
3557 3557 case PARAM_LINK_STATUS:
3558 3558 val = (dp->mii_state == MII_STATE_LINKUP);
3559 3559 break;
3560 3560
3561 3561 case PARAM_LINK_SPEED:
3562 3562 val = gem_speed_value[dp->speed];
3563 3563 break;
3564 3564
3565 3565 case PARAM_LINK_DUPLEX:
3566 3566 val = 0;
3567 3567 if (dp->mii_state == MII_STATE_LINKUP) {
3568 3568 val = dp->full_duplex ? 2 : 1;
3569 3569 }
3570 3570 break;
3571 3571
3572 3572 case PARAM_LINK_AUTONEG:
3573 3573 val = BOOLEAN(dp->mii_exp & MII_AN_EXP_LPCANAN);
3574 3574 break;
3575 3575
3576 3576 case PARAM_LINK_RX_PAUSE:
3577 3577 val = (dp->flow_control == FLOW_CONTROL_SYMMETRIC) ||
3578 3578 (dp->flow_control == FLOW_CONTROL_RX_PAUSE);
3579 3579 break;
3580 3580
3581 3581 case PARAM_LINK_TX_PAUSE:
3582 3582 val = (dp->flow_control == FLOW_CONTROL_SYMMETRIC) ||
3583 3583 (dp->flow_control == FLOW_CONTROL_TX_PAUSE);
3584 3584 break;
3585 3585
3586 3586 #ifdef DEBUG_RESUME
3587 3587 case PARAM_RESUME_TEST:
3588 3588 val = 0;
3589 3589 break;
3590 3590 #endif
3591 3591 default:
3592 3592 cmn_err(CE_WARN, "%s: unimplemented ndd control (%d)",
3593 3593 dp->name, item);
3594 3594 break;
3595 3595 }
3596 3596
3597 3597 (void) mi_mpprintf(mp, "%ld", val);
3598 3598
3599 3599 return (0);
3600 3600 }
3601 3601
3602 3602 static int
3603 3603 gem_param_set(queue_t *q, mblk_t *mp, char *value, caddr_t arg, cred_t *credp)
3604 3604 {
3605 3605 struct gem_dev *dp = ((struct gem_nd_arg *)(void *)arg)->dp;
3606 3606 int item = ((struct gem_nd_arg *)(void *)arg)->item;
3607 3607 long val;
3608 3608 char *end;
3609 3609
3610 3610 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
3611 3611 if (ddi_strtol(value, &end, 10, &val)) {
3612 3612 return (EINVAL);
3613 3613 }
3614 3614 if (end == value) {
3615 3615 return (EINVAL);
3616 3616 }
3617 3617
3618 3618 switch (item) {
3619 3619 case PARAM_ADV_AUTONEG_CAP:
3620 3620 if (val != 0 && val != 1) {
3621 3621 goto err;
3622 3622 }
3623 3623 if (val && (dp->mii_status & MII_STATUS_CANAUTONEG) == 0) {
3624 3624 goto err;
3625 3625 }
3626 3626 dp->anadv_autoneg = (int)val;
3627 3627 break;
3628 3628
3629 3629 case PARAM_ADV_PAUSE_CAP:
3630 3630 if (val != 0 && val != 1) {
3631 3631 goto err;
3632 3632 }
3633 3633 if (val) {
3634 3634 dp->anadv_flow_control |= 1;
3635 3635 } else {
3636 3636 dp->anadv_flow_control &= ~1;
3637 3637 }
3638 3638 break;
3639 3639
3640 3640 case PARAM_ADV_ASYM_PAUSE_CAP:
3641 3641 if (val != 0 && val != 1) {
3642 3642 goto err;
3643 3643 }
3644 3644 if (val) {
3645 3645 dp->anadv_flow_control |= 2;
3646 3646 } else {
3647 3647 dp->anadv_flow_control &= ~2;
3648 3648 }
3649 3649 break;
3650 3650
3651 3651 case PARAM_ADV_1000FDX_CAP:
3652 3652 if (val != 0 && val != 1) {
3653 3653 goto err;
3654 3654 }
3655 3655 if (val && (dp->mii_xstatus &
3656 3656 (MII_XSTATUS_1000BASET_FD |
3657 3657 MII_XSTATUS_1000BASEX_FD)) == 0) {
3658 3658 goto err;
3659 3659 }
3660 3660 dp->anadv_1000fdx = (int)val;
3661 3661 break;
3662 3662
3663 3663 case PARAM_ADV_1000HDX_CAP:
3664 3664 if (val != 0 && val != 1) {
3665 3665 goto err;
3666 3666 }
3667 3667 if (val && (dp->mii_xstatus &
3668 3668 (MII_XSTATUS_1000BASET | MII_XSTATUS_1000BASEX)) == 0) {
3669 3669 goto err;
3670 3670 }
3671 3671 dp->anadv_1000hdx = (int)val;
3672 3672 break;
3673 3673
3674 3674 case PARAM_ADV_100T4_CAP:
3675 3675 if (val != 0 && val != 1) {
3676 3676 goto err;
3677 3677 }
3678 3678 if (val && (dp->mii_status & MII_STATUS_100_BASE_T4) == 0) {
3679 3679 goto err;
3680 3680 }
3681 3681 dp->anadv_100t4 = (int)val;
3682 3682 break;
3683 3683
3684 3684 case PARAM_ADV_100FDX_CAP:
3685 3685 if (val != 0 && val != 1) {
3686 3686 goto err;
3687 3687 }
3688 3688 if (val && (dp->mii_status & MII_STATUS_100_BASEX_FD) == 0) {
3689 3689 goto err;
3690 3690 }
3691 3691 dp->anadv_100fdx = (int)val;
3692 3692 break;
3693 3693
3694 3694 case PARAM_ADV_100HDX_CAP:
3695 3695 if (val != 0 && val != 1) {
3696 3696 goto err;
3697 3697 }
3698 3698 if (val && (dp->mii_status & MII_STATUS_100_BASEX) == 0) {
3699 3699 goto err;
3700 3700 }
3701 3701 dp->anadv_100hdx = (int)val;
3702 3702 break;
3703 3703
3704 3704 case PARAM_ADV_10FDX_CAP:
3705 3705 if (val != 0 && val != 1) {
3706 3706 goto err;
3707 3707 }
3708 3708 if (val && (dp->mii_status & MII_STATUS_10_FD) == 0) {
3709 3709 goto err;
3710 3710 }
3711 3711 dp->anadv_10fdx = (int)val;
3712 3712 break;
3713 3713
3714 3714 case PARAM_ADV_10HDX_CAP:
3715 3715 if (val != 0 && val != 1) {
3716 3716 goto err;
3717 3717 }
3718 3718 if (val && (dp->mii_status & MII_STATUS_10) == 0) {
3719 3719 goto err;
3720 3720 }
3721 3721 dp->anadv_10hdx = (int)val;
3722 3722 break;
3723 3723 }
3724 3724
3725 3725 /* sync with PHY */
3726 3726 gem_choose_forcedmode(dp);
3727 3727
3728 3728 dp->mii_state = MII_STATE_UNKNOWN;
3729 3729 if (dp->gc.gc_mii_hw_link_detection && dp->link_watcher_id == 0) {
3730 3730 /* XXX - Can we ignore the return code ? */
3731 3731 (void) gem_mii_link_check(dp);
3732 3732 }
3733 3733
3734 3734 return (0);
3735 3735 err:
3736 3736 return (EINVAL);
3737 3737 }
3738 3738
3739 3739 static void
3740 3740 gem_nd_load(struct gem_dev *dp, char *name, ndgetf_t gf, ndsetf_t sf, int item)
3741 3741 {
3742 3742 struct gem_nd_arg *arg;
3743 3743
3744 3744 ASSERT(item >= 0);
3745 3745 ASSERT(item < PARAM_COUNT);
3746 3746
3747 3747 arg = &((struct gem_nd_arg *)(void *)dp->nd_arg_p)[item];
3748 3748 arg->dp = dp;
3749 3749 arg->item = item;
3750 3750
3751 3751 DPRINTF(2, (CE_CONT, "!%s: %s: name:%s, item:%d",
3752 3752 dp->name, __func__, name, item));
3753 3753 (void) nd_load(&dp->nd_data_p, name, gf, sf, (caddr_t)arg);
3754 3754 }
3755 3755
3756 3756 static void
3757 3757 gem_nd_setup(struct gem_dev *dp)
3758 3758 {
3759 3759 DPRINTF(0, (CE_CONT, "!%s: %s: called, mii_status:0x%b",
3760 3760 dp->name, __func__, dp->mii_status, MII_STATUS_BITS));
3761 3761
3762 3762 ASSERT(dp->nd_arg_p == NULL);
3763 3763
3764 3764 dp->nd_arg_p =
3765 3765 kmem_zalloc(sizeof (struct gem_nd_arg) * PARAM_COUNT, KM_SLEEP);
3766 3766
3767 3767 #define SETFUNC(x) ((x) ? gem_param_set : NULL)
3768 3768
3769 3769 gem_nd_load(dp, "autoneg_cap",
3770 3770 gem_param_get, NULL, PARAM_AUTONEG_CAP);
3771 3771 gem_nd_load(dp, "pause_cap",
3772 3772 gem_param_get, NULL, PARAM_PAUSE_CAP);
3773 3773 gem_nd_load(dp, "asym_pause_cap",
3774 3774 gem_param_get, NULL, PARAM_ASYM_PAUSE_CAP);
3775 3775 gem_nd_load(dp, "1000fdx_cap",
3776 3776 gem_param_get, NULL, PARAM_1000FDX_CAP);
3777 3777 gem_nd_load(dp, "1000hdx_cap",
3778 3778 gem_param_get, NULL, PARAM_1000HDX_CAP);
3779 3779 gem_nd_load(dp, "100T4_cap",
3780 3780 gem_param_get, NULL, PARAM_100T4_CAP);
3781 3781 gem_nd_load(dp, "100fdx_cap",
3782 3782 gem_param_get, NULL, PARAM_100FDX_CAP);
3783 3783 gem_nd_load(dp, "100hdx_cap",
3784 3784 gem_param_get, NULL, PARAM_100HDX_CAP);
3785 3785 gem_nd_load(dp, "10fdx_cap",
3786 3786 gem_param_get, NULL, PARAM_10FDX_CAP);
3787 3787 gem_nd_load(dp, "10hdx_cap",
3788 3788 gem_param_get, NULL, PARAM_10HDX_CAP);
3789 3789
3790 3790 /* Our advertised capabilities */
3791 3791 gem_nd_load(dp, "adv_autoneg_cap", gem_param_get,
3792 3792 SETFUNC(dp->mii_status & MII_STATUS_CANAUTONEG),
3793 3793 PARAM_ADV_AUTONEG_CAP);
3794 3794 gem_nd_load(dp, "adv_pause_cap", gem_param_get,
3795 3795 SETFUNC(dp->gc.gc_flow_control & 1),
3796 3796 PARAM_ADV_PAUSE_CAP);
3797 3797 gem_nd_load(dp, "adv_asym_pause_cap", gem_param_get,
3798 3798 SETFUNC(dp->gc.gc_flow_control & 2),
3799 3799 PARAM_ADV_ASYM_PAUSE_CAP);
3800 3800 gem_nd_load(dp, "adv_1000fdx_cap", gem_param_get,
3801 3801 SETFUNC(dp->mii_xstatus &
3802 3802 (MII_XSTATUS_1000BASEX_FD | MII_XSTATUS_1000BASET_FD)),
3803 3803 PARAM_ADV_1000FDX_CAP);
3804 3804 gem_nd_load(dp, "adv_1000hdx_cap", gem_param_get,
3805 3805 SETFUNC(dp->mii_xstatus &
3806 3806 (MII_XSTATUS_1000BASEX | MII_XSTATUS_1000BASET)),
3807 3807 PARAM_ADV_1000HDX_CAP);
3808 3808 gem_nd_load(dp, "adv_100T4_cap", gem_param_get,
3809 3809 SETFUNC((dp->mii_status & MII_STATUS_100_BASE_T4) &&
3810 3810 !dp->mii_advert_ro),
3811 3811 PARAM_ADV_100T4_CAP);
3812 3812 gem_nd_load(dp, "adv_100fdx_cap", gem_param_get,
3813 3813 SETFUNC((dp->mii_status & MII_STATUS_100_BASEX_FD) &&
3814 3814 !dp->mii_advert_ro),
3815 3815 PARAM_ADV_100FDX_CAP);
3816 3816 gem_nd_load(dp, "adv_100hdx_cap", gem_param_get,
3817 3817 SETFUNC((dp->mii_status & MII_STATUS_100_BASEX) &&
3818 3818 !dp->mii_advert_ro),
3819 3819 PARAM_ADV_100HDX_CAP);
3820 3820 gem_nd_load(dp, "adv_10fdx_cap", gem_param_get,
3821 3821 SETFUNC((dp->mii_status & MII_STATUS_10_FD) &&
3822 3822 !dp->mii_advert_ro),
3823 3823 PARAM_ADV_10FDX_CAP);
3824 3824 gem_nd_load(dp, "adv_10hdx_cap", gem_param_get,
3825 3825 SETFUNC((dp->mii_status & MII_STATUS_10) &&
3826 3826 !dp->mii_advert_ro),
3827 3827 PARAM_ADV_10HDX_CAP);
3828 3828
3829 3829 /* Partner's advertised capabilities */
3830 3830 gem_nd_load(dp, "lp_autoneg_cap",
3831 3831 gem_param_get, NULL, PARAM_LP_AUTONEG_CAP);
3832 3832 gem_nd_load(dp, "lp_pause_cap",
3833 3833 gem_param_get, NULL, PARAM_LP_PAUSE_CAP);
3834 3834 gem_nd_load(dp, "lp_asym_pause_cap",
3835 3835 gem_param_get, NULL, PARAM_LP_ASYM_PAUSE_CAP);
3836 3836 gem_nd_load(dp, "lp_1000fdx_cap",
3837 3837 gem_param_get, NULL, PARAM_LP_1000FDX_CAP);
3838 3838 gem_nd_load(dp, "lp_1000hdx_cap",
3839 3839 gem_param_get, NULL, PARAM_LP_1000HDX_CAP);
3840 3840 gem_nd_load(dp, "lp_100T4_cap",
3841 3841 gem_param_get, NULL, PARAM_LP_100T4_CAP);
3842 3842 gem_nd_load(dp, "lp_100fdx_cap",
3843 3843 gem_param_get, NULL, PARAM_LP_100FDX_CAP);
3844 3844 gem_nd_load(dp, "lp_100hdx_cap",
3845 3845 gem_param_get, NULL, PARAM_LP_100HDX_CAP);
3846 3846 gem_nd_load(dp, "lp_10fdx_cap",
3847 3847 gem_param_get, NULL, PARAM_LP_10FDX_CAP);
3848 3848 gem_nd_load(dp, "lp_10hdx_cap",
3849 3849 gem_param_get, NULL, PARAM_LP_10HDX_CAP);
3850 3850
3851 3851 /* Current operating modes */
3852 3852 gem_nd_load(dp, "link_status",
3853 3853 gem_param_get, NULL, PARAM_LINK_STATUS);
3854 3854 gem_nd_load(dp, "link_speed",
3855 3855 gem_param_get, NULL, PARAM_LINK_SPEED);
3856 3856 gem_nd_load(dp, "link_duplex",
3857 3857 gem_param_get, NULL, PARAM_LINK_DUPLEX);
3858 3858 gem_nd_load(dp, "link_autoneg",
3859 3859 gem_param_get, NULL, PARAM_LINK_AUTONEG);
3860 3860 gem_nd_load(dp, "link_rx_pause",
3861 3861 gem_param_get, NULL, PARAM_LINK_RX_PAUSE);
3862 3862 gem_nd_load(dp, "link_tx_pause",
3863 3863 gem_param_get, NULL, PARAM_LINK_TX_PAUSE);
3864 3864 #ifdef DEBUG_RESUME
3865 3865 gem_nd_load(dp, "resume_test",
3866 3866 gem_param_get, NULL, PARAM_RESUME_TEST);
3867 3867 #endif
3868 3868 #undef SETFUNC
3869 3869 }
3870 3870
3871 3871 static
3872 3872 enum ioc_reply
3873 3873 gem_nd_ioctl(struct gem_dev *dp, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
3874 3874 {
3875 3875 boolean_t ok;
3876 3876
3877 3877 ASSERT(mutex_owned(&dp->intrlock));
3878 3878
3879 3879 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
3880 3880
3881 3881 switch (iocp->ioc_cmd) {
3882 3882 case ND_GET:
3883 3883 ok = nd_getset(wq, dp->nd_data_p, mp);
3884 3884 DPRINTF(0, (CE_CONT,
3885 3885 "%s: get %s", dp->name, ok ? "OK" : "FAIL"));
3886 3886 return (ok ? IOC_REPLY : IOC_INVAL);
3887 3887
3888 3888 case ND_SET:
3889 3889 ok = nd_getset(wq, dp->nd_data_p, mp);
3890 3890
3891 3891 DPRINTF(0, (CE_CONT, "%s: set %s err %d",
3892 3892 dp->name, ok ? "OK" : "FAIL", iocp->ioc_error));
3893 3893
3894 3894 if (!ok) {
3895 3895 return (IOC_INVAL);
3896 3896 }
3897 3897
3898 3898 if (iocp->ioc_error) {
3899 3899 return (IOC_REPLY);
3900 3900 }
3901 3901
3902 3902 return (IOC_RESTART_REPLY);
3903 3903 }
3904 3904
3905 3905 cmn_err(CE_WARN, "%s: invalid cmd 0x%x", dp->name, iocp->ioc_cmd);
3906 3906
3907 3907 return (IOC_INVAL);
3908 3908 }
3909 3909
3910 3910 static void
3911 3911 gem_nd_cleanup(struct gem_dev *dp)
3912 3912 {
3913 3913 ASSERT(dp->nd_data_p != NULL);
3914 3914 ASSERT(dp->nd_arg_p != NULL);
3915 3915
3916 3916 nd_free(&dp->nd_data_p);
3917 3917
3918 3918 kmem_free(dp->nd_arg_p, sizeof (struct gem_nd_arg) * PARAM_COUNT);
3919 3919 dp->nd_arg_p = NULL;
3920 3920 }
3921 3921
3922 3922 static void
3923 3923 gem_mac_ioctl(struct gem_dev *dp, queue_t *wq, mblk_t *mp)
3924 3924 {
3925 3925 struct iocblk *iocp;
3926 3926 enum ioc_reply status;
3927 3927 int cmd;
3928 3928
3929 3929 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
3930 3930
3931 3931 /*
3932 3932 * Validate the command before bothering with the mutex ...
3933 3933 */
3934 3934 iocp = (void *)mp->b_rptr;
3935 3935 iocp->ioc_error = 0;
3936 3936 cmd = iocp->ioc_cmd;
3937 3937
3938 3938 DPRINTF(0, (CE_CONT, "%s: %s cmd:0x%x", dp->name, __func__, cmd));
3939 3939
3940 3940 mutex_enter(&dp->intrlock);
3941 3941 mutex_enter(&dp->xmitlock);
3942 3942
3943 3943 switch (cmd) {
3944 3944 default:
3945 3945 _NOTE(NOTREACHED)
3946 3946 status = IOC_INVAL;
3947 3947 break;
3948 3948
3949 3949 case ND_GET:
3950 3950 case ND_SET:
3951 3951 status = gem_nd_ioctl(dp, wq, mp, iocp);
3952 3952 break;
3953 3953 }
3954 3954
3955 3955 mutex_exit(&dp->xmitlock);
3956 3956 mutex_exit(&dp->intrlock);
3957 3957
3958 3958 #ifdef DEBUG_RESUME
3959 3959 if (cmd == ND_GET) {
3960 3960 gem_suspend(dp->dip);
3961 3961 gem_resume(dp->dip);
3962 3962 }
3963 3963 #endif
3964 3964 /*
3965 3965 * Finally, decide how to reply
3966 3966 */
3967 3967 switch (status) {
3968 3968 default:
3969 3969 case IOC_INVAL:
3970 3970 /*
3971 3971 * Error, reply with a NAK and EINVAL or the specified error
3972 3972 */
3973 3973 miocnak(wq, mp, 0, iocp->ioc_error == 0 ?
3974 3974 EINVAL : iocp->ioc_error);
3975 3975 break;
3976 3976
3977 3977 case IOC_DONE:
3978 3978 /*
3979 3979 * OK, reply already sent
3980 3980 */
3981 3981 break;
3982 3982
3983 3983 case IOC_RESTART_ACK:
3984 3984 case IOC_ACK:
3985 3985 /*
3986 3986 * OK, reply with an ACK
3987 3987 */
3988 3988 miocack(wq, mp, 0, 0);
3989 3989 break;
3990 3990
3991 3991 case IOC_RESTART_REPLY:
3992 3992 case IOC_REPLY:
3993 3993 /*
3994 3994 * OK, send prepared reply as ACK or NAK
3995 3995 */
3996 3996 mp->b_datap->db_type =
3997 3997 iocp->ioc_error == 0 ? M_IOCACK : M_IOCNAK;
3998 3998 qreply(wq, mp);
3999 3999 break;
4000 4000 }
4001 4001 }
4002 4002
4003 4003 #ifndef SYS_MAC_H
4004 4004 #define XCVR_UNDEFINED 0
4005 4005 #define XCVR_NONE 1
4006 4006 #define XCVR_10 2
4007 4007 #define XCVR_100T4 3
4008 4008 #define XCVR_100X 4
4009 4009 #define XCVR_100T2 5
4010 4010 #define XCVR_1000X 6
4011 4011 #define XCVR_1000T 7
4012 4012 #endif
4013 4013 static int
4014 4014 gem_mac_xcvr_inuse(struct gem_dev *dp)
4015 4015 {
4016 4016 int val = XCVR_UNDEFINED;
4017 4017
4018 4018 if ((dp->mii_status & MII_STATUS_XSTATUS) == 0) {
4019 4019 if (dp->mii_status & MII_STATUS_100_BASE_T4) {
4020 4020 val = XCVR_100T4;
4021 4021 } else if (dp->mii_status &
4022 4022 (MII_STATUS_100_BASEX_FD |
4023 4023 MII_STATUS_100_BASEX)) {
4024 4024 val = XCVR_100X;
4025 4025 } else if (dp->mii_status &
4026 4026 (MII_STATUS_100_BASE_T2_FD |
4027 4027 MII_STATUS_100_BASE_T2)) {
4028 4028 val = XCVR_100T2;
4029 4029 } else if (dp->mii_status &
4030 4030 (MII_STATUS_10_FD | MII_STATUS_10)) {
4031 4031 val = XCVR_10;
4032 4032 }
4033 4033 } else if (dp->mii_xstatus &
4034 4034 (MII_XSTATUS_1000BASET_FD | MII_XSTATUS_1000BASET)) {
4035 4035 val = XCVR_1000T;
4036 4036 } else if (dp->mii_xstatus &
4037 4037 (MII_XSTATUS_1000BASEX_FD | MII_XSTATUS_1000BASEX)) {
4038 4038 val = XCVR_1000X;
4039 4039 }
4040 4040
4041 4041 return (val);
4042 4042 }
4043 4043
4044 4044 /* ============================================================== */
4045 4045 /*
4046 4046 * GLDv3 interface
4047 4047 */
4048 4048 /* ============================================================== */
4049 4049 static int gem_m_getstat(void *, uint_t, uint64_t *);
4050 4050 static int gem_m_start(void *);
4051 4051 static void gem_m_stop(void *);
4052 4052 static int gem_m_setpromisc(void *, boolean_t);
4053 4053 static int gem_m_multicst(void *, boolean_t, const uint8_t *);
4054 4054 static int gem_m_unicst(void *, const uint8_t *);
4055 4055 static mblk_t *gem_m_tx(void *, mblk_t *);
4056 4056 static void gem_m_ioctl(void *, queue_t *, mblk_t *);
4057 4057 static boolean_t gem_m_getcapab(void *, mac_capab_t, void *);
4058 4058
4059 4059 #define GEM_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB)
4060 4060
4061 4061 static mac_callbacks_t gem_m_callbacks = {
4062 4062 GEM_M_CALLBACK_FLAGS,
4063 4063 gem_m_getstat,
4064 4064 gem_m_start,
4065 4065 gem_m_stop,
4066 4066 gem_m_setpromisc,
4067 4067 gem_m_multicst,
4068 4068 gem_m_unicst,
4069 4069 gem_m_tx,
4070 4070 NULL,
4071 4071 gem_m_ioctl,
4072 4072 gem_m_getcapab,
4073 4073 };
4074 4074
4075 4075 static int
4076 4076 gem_m_start(void *arg)
4077 4077 {
4078 4078 int err = 0;
4079 4079 struct gem_dev *dp = arg;
4080 4080
4081 4081 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
4082 4082
4083 4083 mutex_enter(&dp->intrlock);
4084 4084 if (dp->mac_suspended) {
4085 4085 err = EIO;
4086 4086 goto x;
4087 4087 }
4088 4088 if (gem_mac_init(dp) != GEM_SUCCESS) {
4089 4089 err = EIO;
4090 4090 goto x;
4091 4091 }
4092 4092 dp->nic_state = NIC_STATE_INITIALIZED;
4093 4093
4094 4094 /* reset rx filter state */
4095 4095 dp->mc_count = 0;
4096 4096 dp->mc_count_req = 0;
4097 4097
4098 4098 /* setup media mode if the link have been up */
4099 4099 if (dp->mii_state == MII_STATE_LINKUP) {
4100 4100 (dp->gc.gc_set_media)(dp);
4101 4101 }
4102 4102
4103 4103 /* setup initial rx filter */
4104 4104 bcopy(dp->dev_addr.ether_addr_octet,
4105 4105 dp->cur_addr.ether_addr_octet, ETHERADDRL);
4106 4106 dp->rxmode |= RXMODE_ENABLE;
4107 4107
4108 4108 if (gem_mac_set_rx_filter(dp) != GEM_SUCCESS) {
4109 4109 err = EIO;
4110 4110 goto x;
4111 4111 }
4112 4112
4113 4113 dp->nic_state = NIC_STATE_ONLINE;
4114 4114 if (dp->mii_state == MII_STATE_LINKUP) {
4115 4115 if (gem_mac_start(dp) != GEM_SUCCESS) {
4116 4116 err = EIO;
4117 4117 goto x;
4118 4118 }
4119 4119 }
4120 4120
4121 4121 dp->timeout_id = timeout((void (*)(void *))gem_tx_timeout,
4122 4122 (void *)dp, dp->gc.gc_tx_timeout_interval);
4123 4123 mutex_exit(&dp->intrlock);
4124 4124
4125 4125 return (0);
4126 4126 x:
4127 4127 dp->nic_state = NIC_STATE_STOPPED;
4128 4128 mutex_exit(&dp->intrlock);
4129 4129 return (err);
4130 4130 }
4131 4131
4132 4132 static void
4133 4133 gem_m_stop(void *arg)
4134 4134 {
4135 4135 struct gem_dev *dp = arg;
4136 4136
4137 4137 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
4138 4138
4139 4139 /* stop rx */
4140 4140 mutex_enter(&dp->intrlock);
4141 4141 if (dp->mac_suspended) {
4142 4142 mutex_exit(&dp->intrlock);
4143 4143 return;
4144 4144 }
4145 4145 dp->rxmode &= ~RXMODE_ENABLE;
4146 4146 (void) gem_mac_set_rx_filter(dp);
4147 4147 mutex_exit(&dp->intrlock);
4148 4148
4149 4149 /* stop tx timeout watcher */
4150 4150 if (dp->timeout_id) {
4151 4151 while (untimeout(dp->timeout_id) == -1)
4152 4152 ;
4153 4153 dp->timeout_id = 0;
4154 4154 }
4155 4155
4156 4156 /* make the nic state inactive */
4157 4157 mutex_enter(&dp->intrlock);
4158 4158 if (dp->mac_suspended) {
4159 4159 mutex_exit(&dp->intrlock);
4160 4160 return;
4161 4161 }
4162 4162 dp->nic_state = NIC_STATE_STOPPED;
4163 4163
4164 4164 /* we need deassert mac_active due to block interrupt handler */
4165 4165 mutex_enter(&dp->xmitlock);
4166 4166 dp->mac_active = B_FALSE;
4167 4167 mutex_exit(&dp->xmitlock);
4168 4168
4169 4169 /* block interrupts */
4170 4170 while (dp->intr_busy) {
4171 4171 cv_wait(&dp->tx_drain_cv, &dp->intrlock);
4172 4172 }
4173 4173 (void) gem_mac_stop(dp, 0);
4174 4174 mutex_exit(&dp->intrlock);
4175 4175 }
4176 4176
4177 4177 static int
4178 4178 gem_m_multicst(void *arg, boolean_t add, const uint8_t *ep)
4179 4179 {
4180 4180 int err;
4181 4181 int ret;
4182 4182 struct gem_dev *dp = arg;
4183 4183
4184 4184 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
4185 4185
4186 4186 if (add) {
4187 4187 ret = gem_add_multicast(dp, ep);
4188 4188 } else {
4189 4189 ret = gem_remove_multicast(dp, ep);
4190 4190 }
4191 4191
4192 4192 err = 0;
4193 4193 if (ret != GEM_SUCCESS) {
4194 4194 err = EIO;
4195 4195 }
4196 4196
4197 4197 return (err);
4198 4198 }
4199 4199
4200 4200 static int
4201 4201 gem_m_setpromisc(void *arg, boolean_t on)
4202 4202 {
4203 4203 int err = 0; /* no error */
4204 4204 struct gem_dev *dp = arg;
4205 4205
4206 4206 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
4207 4207
4208 4208 mutex_enter(&dp->intrlock);
4209 4209 if (dp->mac_suspended) {
4210 4210 mutex_exit(&dp->intrlock);
4211 4211 return (EIO);
4212 4212 }
4213 4213 if (on) {
4214 4214 dp->rxmode |= RXMODE_PROMISC;
4215 4215 } else {
4216 4216 dp->rxmode &= ~RXMODE_PROMISC;
4217 4217 }
4218 4218
4219 4219 if (gem_mac_set_rx_filter(dp) != GEM_SUCCESS) {
4220 4220 err = EIO;
4221 4221 }
4222 4222 mutex_exit(&dp->intrlock);
4223 4223
4224 4224 return (err);
4225 4225 }
4226 4226
4227 4227 int
4228 4228 gem_m_getstat(void *arg, uint_t stat, uint64_t *valp)
4229 4229 {
4230 4230 struct gem_dev *dp = arg;
4231 4231 struct gem_stats *gstp = &dp->stats;
4232 4232 uint64_t val = 0;
4233 4233
4234 4234 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
4235 4235
4236 4236 if (mutex_owned(&dp->intrlock)) {
4237 4237 if (dp->mac_suspended) {
4238 4238 return (EIO);
4239 4239 }
4240 4240 } else {
4241 4241 mutex_enter(&dp->intrlock);
4242 4242 if (dp->mac_suspended) {
4243 4243 mutex_exit(&dp->intrlock);
4244 4244 return (EIO);
4245 4245 }
4246 4246 mutex_exit(&dp->intrlock);
4247 4247 }
4248 4248
4249 4249 if ((*dp->gc.gc_get_stats)(dp) != GEM_SUCCESS) {
4250 4250 return (EIO);
4251 4251 }
4252 4252
4253 4253 switch (stat) {
4254 4254 case MAC_STAT_IFSPEED:
4255 4255 val = gem_speed_value[dp->speed] *1000000ull;
4256 4256 break;
4257 4257
4258 4258 case MAC_STAT_MULTIRCV:
4259 4259 val = gstp->rmcast;
4260 4260 break;
4261 4261
4262 4262 case MAC_STAT_BRDCSTRCV:
4263 4263 val = gstp->rbcast;
4264 4264 break;
4265 4265
4266 4266 case MAC_STAT_MULTIXMT:
4267 4267 val = gstp->omcast;
4268 4268 break;
4269 4269
4270 4270 case MAC_STAT_BRDCSTXMT:
4271 4271 val = gstp->obcast;
4272 4272 break;
4273 4273
4274 4274 case MAC_STAT_NORCVBUF:
4275 4275 val = gstp->norcvbuf + gstp->missed;
4276 4276 break;
4277 4277
4278 4278 case MAC_STAT_IERRORS:
4279 4279 val = gstp->errrcv;
4280 4280 break;
4281 4281
4282 4282 case MAC_STAT_NOXMTBUF:
4283 4283 val = gstp->noxmtbuf;
4284 4284 break;
4285 4285
4286 4286 case MAC_STAT_OERRORS:
4287 4287 val = gstp->errxmt;
4288 4288 break;
4289 4289
4290 4290 case MAC_STAT_COLLISIONS:
4291 4291 val = gstp->collisions;
4292 4292 break;
4293 4293
4294 4294 case MAC_STAT_RBYTES:
4295 4295 val = gstp->rbytes;
4296 4296 break;
4297 4297
4298 4298 case MAC_STAT_IPACKETS:
4299 4299 val = gstp->rpackets;
4300 4300 break;
4301 4301
4302 4302 case MAC_STAT_OBYTES:
4303 4303 val = gstp->obytes;
4304 4304 break;
4305 4305
4306 4306 case MAC_STAT_OPACKETS:
4307 4307 val = gstp->opackets;
4308 4308 break;
4309 4309
4310 4310 case MAC_STAT_UNDERFLOWS:
4311 4311 val = gstp->underflow;
4312 4312 break;
4313 4313
4314 4314 case MAC_STAT_OVERFLOWS:
4315 4315 val = gstp->overflow;
4316 4316 break;
4317 4317
4318 4318 case ETHER_STAT_ALIGN_ERRORS:
4319 4319 val = gstp->frame;
4320 4320 break;
4321 4321
4322 4322 case ETHER_STAT_FCS_ERRORS:
4323 4323 val = gstp->crc;
4324 4324 break;
4325 4325
4326 4326 case ETHER_STAT_FIRST_COLLISIONS:
4327 4327 val = gstp->first_coll;
4328 4328 break;
4329 4329
4330 4330 case ETHER_STAT_MULTI_COLLISIONS:
4331 4331 val = gstp->multi_coll;
4332 4332 break;
4333 4333
4334 4334 case ETHER_STAT_SQE_ERRORS:
4335 4335 val = gstp->sqe;
4336 4336 break;
4337 4337
4338 4338 case ETHER_STAT_DEFER_XMTS:
4339 4339 val = gstp->defer;
4340 4340 break;
4341 4341
4342 4342 case ETHER_STAT_TX_LATE_COLLISIONS:
4343 4343 val = gstp->xmtlatecoll;
4344 4344 break;
4345 4345
4346 4346 case ETHER_STAT_EX_COLLISIONS:
4347 4347 val = gstp->excoll;
4348 4348 break;
4349 4349
4350 4350 case ETHER_STAT_MACXMT_ERRORS:
4351 4351 val = gstp->xmit_internal_err;
4352 4352 break;
4353 4353
4354 4354 case ETHER_STAT_CARRIER_ERRORS:
4355 4355 val = gstp->nocarrier;
4356 4356 break;
4357 4357
4358 4358 case ETHER_STAT_TOOLONG_ERRORS:
4359 4359 val = gstp->frame_too_long;
4360 4360 break;
4361 4361
4362 4362 case ETHER_STAT_MACRCV_ERRORS:
4363 4363 val = gstp->rcv_internal_err;
4364 4364 break;
4365 4365
4366 4366 case ETHER_STAT_XCVR_ADDR:
4367 4367 val = dp->mii_phy_addr;
4368 4368 break;
4369 4369
4370 4370 case ETHER_STAT_XCVR_ID:
4371 4371 val = dp->mii_phy_id;
4372 4372 break;
4373 4373
4374 4374 case ETHER_STAT_XCVR_INUSE:
4375 4375 val = gem_mac_xcvr_inuse(dp);
4376 4376 break;
4377 4377
4378 4378 case ETHER_STAT_CAP_1000FDX:
4379 4379 val = (dp->mii_xstatus & MII_XSTATUS_1000BASET_FD) ||
4380 4380 (dp->mii_xstatus & MII_XSTATUS_1000BASEX_FD);
4381 4381 break;
4382 4382
4383 4383 case ETHER_STAT_CAP_1000HDX:
4384 4384 val = (dp->mii_xstatus & MII_XSTATUS_1000BASET) ||
4385 4385 (dp->mii_xstatus & MII_XSTATUS_1000BASEX);
4386 4386 break;
4387 4387
4388 4388 case ETHER_STAT_CAP_100FDX:
4389 4389 val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASEX_FD);
4390 4390 break;
4391 4391
4392 4392 case ETHER_STAT_CAP_100HDX:
4393 4393 val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASEX);
4394 4394 break;
4395 4395
4396 4396 case ETHER_STAT_CAP_10FDX:
4397 4397 val = BOOLEAN(dp->mii_status & MII_STATUS_10_FD);
4398 4398 break;
4399 4399
4400 4400 case ETHER_STAT_CAP_10HDX:
4401 4401 val = BOOLEAN(dp->mii_status & MII_STATUS_10);
4402 4402 break;
4403 4403
4404 4404 case ETHER_STAT_CAP_ASMPAUSE:
4405 4405 val = BOOLEAN(dp->gc.gc_flow_control & 2);
4406 4406 break;
4407 4407
4408 4408 case ETHER_STAT_CAP_PAUSE:
4409 4409 val = BOOLEAN(dp->gc.gc_flow_control & 1);
4410 4410 break;
4411 4411
4412 4412 case ETHER_STAT_CAP_AUTONEG:
4413 4413 val = BOOLEAN(dp->mii_status & MII_STATUS_CANAUTONEG);
4414 4414 break;
4415 4415
4416 4416 case ETHER_STAT_ADV_CAP_1000FDX:
4417 4417 val = dp->anadv_1000fdx;
4418 4418 break;
4419 4419
4420 4420 case ETHER_STAT_ADV_CAP_1000HDX:
4421 4421 val = dp->anadv_1000hdx;
4422 4422 break;
4423 4423
4424 4424 case ETHER_STAT_ADV_CAP_100FDX:
4425 4425 val = dp->anadv_100fdx;
4426 4426 break;
4427 4427
4428 4428 case ETHER_STAT_ADV_CAP_100HDX:
4429 4429 val = dp->anadv_100hdx;
4430 4430 break;
4431 4431
4432 4432 case ETHER_STAT_ADV_CAP_10FDX:
4433 4433 val = dp->anadv_10fdx;
4434 4434 break;
4435 4435
4436 4436 case ETHER_STAT_ADV_CAP_10HDX:
4437 4437 val = dp->anadv_10hdx;
4438 4438 break;
4439 4439
4440 4440 case ETHER_STAT_ADV_CAP_ASMPAUSE:
4441 4441 val = BOOLEAN(dp->anadv_flow_control & 2);
4442 4442 break;
4443 4443
4444 4444 case ETHER_STAT_ADV_CAP_PAUSE:
4445 4445 val = BOOLEAN(dp->anadv_flow_control & 1);
4446 4446 break;
4447 4447
4448 4448 case ETHER_STAT_ADV_CAP_AUTONEG:
4449 4449 val = dp->anadv_autoneg;
4450 4450 break;
4451 4451
4452 4452 case ETHER_STAT_LP_CAP_1000FDX:
4453 4453 val = BOOLEAN(dp->mii_stat1000 & MII_1000TS_LP_FULL);
4454 4454 break;
4455 4455
4456 4456 case ETHER_STAT_LP_CAP_1000HDX:
4457 4457 val = BOOLEAN(dp->mii_stat1000 & MII_1000TS_LP_HALF);
4458 4458 break;
4459 4459
4460 4460 case ETHER_STAT_LP_CAP_100FDX:
4461 4461 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_TX_FD);
4462 4462 break;
4463 4463
4464 4464 case ETHER_STAT_LP_CAP_100HDX:
4465 4465 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_TX);
4466 4466 break;
4467 4467
4468 4468 case ETHER_STAT_LP_CAP_10FDX:
4469 4469 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_10BASE_T_FD);
4470 4470 break;
4471 4471
4472 4472 case ETHER_STAT_LP_CAP_10HDX:
4473 4473 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_10BASE_T);
4474 4474 break;
4475 4475
4476 4476 case ETHER_STAT_LP_CAP_ASMPAUSE:
4477 4477 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_ASMPAUSE);
4478 4478 break;
4479 4479
4480 4480 case ETHER_STAT_LP_CAP_PAUSE:
4481 4481 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_PAUSE);
4482 4482 break;
4483 4483
4484 4484 case ETHER_STAT_LP_CAP_AUTONEG:
4485 4485 val = BOOLEAN(dp->mii_exp & MII_AN_EXP_LPCANAN);
4486 4486 break;
4487 4487
4488 4488 case ETHER_STAT_LINK_ASMPAUSE:
4489 4489 val = BOOLEAN(dp->flow_control & 2);
4490 4490 break;
4491 4491
4492 4492 case ETHER_STAT_LINK_PAUSE:
4493 4493 val = BOOLEAN(dp->flow_control & 1);
4494 4494 break;
4495 4495
4496 4496 case ETHER_STAT_LINK_AUTONEG:
4497 4497 val = dp->anadv_autoneg &&
4498 4498 BOOLEAN(dp->mii_exp & MII_AN_EXP_LPCANAN);
4499 4499 break;
4500 4500
4501 4501 case ETHER_STAT_LINK_DUPLEX:
4502 4502 val = (dp->mii_state == MII_STATE_LINKUP) ?
4503 4503 (dp->full_duplex ? 2 : 1) : 0;
4504 4504 break;
4505 4505
4506 4506 case ETHER_STAT_TOOSHORT_ERRORS:
4507 4507 val = gstp->runt;
4508 4508 break;
4509 4509 case ETHER_STAT_LP_REMFAULT:
4510 4510 val = BOOLEAN(dp->mii_lpable & MII_AN_ADVERT_REMFAULT);
4511 4511 break;
4512 4512
4513 4513 case ETHER_STAT_JABBER_ERRORS:
4514 4514 val = gstp->jabber;
4515 4515 break;
4516 4516
4517 4517 case ETHER_STAT_CAP_100T4:
4518 4518 val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);
4519 4519 break;
4520 4520
4521 4521 case ETHER_STAT_ADV_CAP_100T4:
4522 4522 val = dp->anadv_100t4;
4523 4523 break;
4524 4524
4525 4525 case ETHER_STAT_LP_CAP_100T4:
4526 4526 val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_T4);
4527 4527 break;
4528 4528
4529 4529 default:
4530 4530 #if GEM_DEBUG_LEVEL > 2
4531 4531 cmn_err(CE_WARN,
4532 4532 "%s: unrecognized parameter value = %d",
4533 4533 __func__, stat);
4534 4534 #endif
4535 4535 return (ENOTSUP);
4536 4536 }
4537 4537
4538 4538 *valp = val;
4539 4539
4540 4540 return (0);
4541 4541 }
4542 4542
4543 4543 static int
4544 4544 gem_m_unicst(void *arg, const uint8_t *mac)
4545 4545 {
4546 4546 int err = 0;
4547 4547 struct gem_dev *dp = arg;
4548 4548
4549 4549 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
4550 4550
4551 4551 mutex_enter(&dp->intrlock);
4552 4552 if (dp->mac_suspended) {
4553 4553 mutex_exit(&dp->intrlock);
4554 4554 return (EIO);
4555 4555 }
4556 4556 bcopy(mac, dp->cur_addr.ether_addr_octet, ETHERADDRL);
4557 4557 dp->rxmode |= RXMODE_ENABLE;
4558 4558
4559 4559 if (gem_mac_set_rx_filter(dp) != GEM_SUCCESS) {
4560 4560 err = EIO;
4561 4561 }
4562 4562 mutex_exit(&dp->intrlock);
4563 4563
4564 4564 return (err);
4565 4565 }
4566 4566
4567 4567 /*
4568 4568 * gem_m_tx is used only for sending data packets into ethernet wire.
4569 4569 */
4570 4570 static mblk_t *
4571 4571 gem_m_tx(void *arg, mblk_t *mp)
4572 4572 {
4573 4573 uint32_t flags = 0;
4574 4574 struct gem_dev *dp = arg;
4575 4575 mblk_t *tp;
4576 4576
4577 4577 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
4578 4578
4579 4579 ASSERT(dp->nic_state == NIC_STATE_ONLINE);
4580 4580 if (dp->mii_state != MII_STATE_LINKUP) {
4581 4581 /* Some nics hate to send packets when the link is down. */
4582 4582 while (mp) {
4583 4583 tp = mp->b_next;
4584 4584 mp->b_next = NULL;
4585 4585 freemsg(mp);
4586 4586 mp = tp;
4587 4587 }
4588 4588 return (NULL);
4589 4589 }
4590 4590
4591 4591 return (gem_send_common(dp, mp, flags));
4592 4592 }
4593 4593
4594 4594 static void
4595 4595 gem_m_ioctl(void *arg, queue_t *wq, mblk_t *mp)
4596 4596 {
4597 4597 DPRINTF(0, (CE_CONT, "!%s: %s: called",
4598 4598 ((struct gem_dev *)arg)->name, __func__));
4599 4599
4600 4600 gem_mac_ioctl((struct gem_dev *)arg, wq, mp);
4601 4601 }
4602 4602
4603 4603 /* ARGSUSED */
4604 4604 static boolean_t
4605 4605 gem_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
4606 4606 {
4607 4607 return (B_FALSE);
4608 4608 }
4609 4609
4610 4610 static void
4611 4611 gem_gld3_init(struct gem_dev *dp, mac_register_t *macp)
4612 4612 {
4613 4613 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
4614 4614 macp->m_driver = dp;
4615 4615 macp->m_dip = dp->dip;
4616 4616 macp->m_src_addr = dp->dev_addr.ether_addr_octet;
4617 4617 macp->m_callbacks = &gem_m_callbacks;
4618 4618 macp->m_min_sdu = 0;
4619 4619 macp->m_max_sdu = dp->mtu;
4620 4620
4621 4621 if (dp->misc_flag & GEM_VLAN) {
4622 4622 macp->m_margin = VTAG_SIZE;
4623 4623 }
4624 4624 }
4625 4625
4626 4626 /* ======================================================================== */
4627 4627 /*
4628 4628 * attach/detatch support
4629 4629 */
4630 4630 /* ======================================================================== */
4631 4631 static void
4632 4632 gem_read_conf(struct gem_dev *dp)
4633 4633 {
4634 4634 int val;
4635 4635
4636 4636 DPRINTF(1, (CE_CONT, "!%s: %s: called", dp->name, __func__));
4637 4637
4638 4638 /*
4639 4639 * Get media mode infomation from .conf file
4640 4640 */
4641 4641 dp->anadv_autoneg = gem_prop_get_int(dp, "adv_autoneg_cap", 1) != 0;
4642 4642 dp->anadv_1000fdx = gem_prop_get_int(dp, "adv_1000fdx_cap", 1) != 0;
4643 4643 dp->anadv_1000hdx = gem_prop_get_int(dp, "adv_1000hdx_cap", 1) != 0;
4644 4644 dp->anadv_100t4 = gem_prop_get_int(dp, "adv_100T4_cap", 1) != 0;
4645 4645 dp->anadv_100fdx = gem_prop_get_int(dp, "adv_100fdx_cap", 1) != 0;
4646 4646 dp->anadv_100hdx = gem_prop_get_int(dp, "adv_100hdx_cap", 1) != 0;
4647 4647 dp->anadv_10fdx = gem_prop_get_int(dp, "adv_10fdx_cap", 1) != 0;
4648 4648 dp->anadv_10hdx = gem_prop_get_int(dp, "adv_10hdx_cap", 1) != 0;
4649 4649
4650 4650 if ((ddi_prop_exists(DDI_DEV_T_ANY, dp->dip,
4651 4651 DDI_PROP_DONTPASS, "full-duplex"))) {
4652 4652 dp->full_duplex = gem_prop_get_int(dp, "full-duplex", 1) != 0;
4653 4653 dp->anadv_autoneg = B_FALSE;
4654 4654 if (dp->full_duplex) {
4655 4655 dp->anadv_1000hdx = B_FALSE;
4656 4656 dp->anadv_100hdx = B_FALSE;
4657 4657 dp->anadv_10hdx = B_FALSE;
4658 4658 } else {
4659 4659 dp->anadv_1000fdx = B_FALSE;
4660 4660 dp->anadv_100fdx = B_FALSE;
4661 4661 dp->anadv_10fdx = B_FALSE;
4662 4662 }
4663 4663 }
4664 4664
4665 4665 if ((val = gem_prop_get_int(dp, "speed", 0)) > 0) {
4666 4666 dp->anadv_autoneg = B_FALSE;
4667 4667 switch (val) {
4668 4668 case 1000:
4669 4669 dp->speed = GEM_SPD_1000;
4670 4670 dp->anadv_100t4 = B_FALSE;
4671 4671 dp->anadv_100fdx = B_FALSE;
4672 4672 dp->anadv_100hdx = B_FALSE;
4673 4673 dp->anadv_10fdx = B_FALSE;
4674 4674 dp->anadv_10hdx = B_FALSE;
4675 4675 break;
4676 4676 case 100:
4677 4677 dp->speed = GEM_SPD_100;
4678 4678 dp->anadv_1000fdx = B_FALSE;
4679 4679 dp->anadv_1000hdx = B_FALSE;
4680 4680 dp->anadv_10fdx = B_FALSE;
4681 4681 dp->anadv_10hdx = B_FALSE;
4682 4682 break;
4683 4683 case 10:
4684 4684 dp->speed = GEM_SPD_10;
4685 4685 dp->anadv_1000fdx = B_FALSE;
4686 4686 dp->anadv_1000hdx = B_FALSE;
4687 4687 dp->anadv_100t4 = B_FALSE;
4688 4688 dp->anadv_100fdx = B_FALSE;
4689 4689 dp->anadv_100hdx = B_FALSE;
4690 4690 break;
4691 4691 default:
4692 4692 cmn_err(CE_WARN,
4693 4693 "!%s: property %s: illegal value:%d",
4694 4694 dp->name, "speed", val);
4695 4695 dp->anadv_autoneg = B_TRUE;
4696 4696 break;
4697 4697 }
4698 4698 }
4699 4699
4700 4700 val = gem_prop_get_int(dp, "flow-control", dp->gc.gc_flow_control);
4701 4701 if (val > FLOW_CONTROL_RX_PAUSE || val < FLOW_CONTROL_NONE) {
4702 4702 cmn_err(CE_WARN,
4703 4703 "!%s: property %s: illegal value:%d",
4704 4704 dp->name, "flow-control", val);
4705 4705 } else {
4706 4706 val = min(val, dp->gc.gc_flow_control);
4707 4707 }
4708 4708 dp->anadv_flow_control = val;
4709 4709
4710 4710 if (gem_prop_get_int(dp, "nointr", 0)) {
4711 4711 dp->misc_flag |= GEM_NOINTR;
4712 4712 cmn_err(CE_NOTE, "!%s: polling mode enabled", dp->name);
4713 4713 }
4714 4714
4715 4715 dp->mtu = gem_prop_get_int(dp, "mtu", dp->mtu);
4716 4716 dp->txthr = gem_prop_get_int(dp, "txthr", dp->txthr);
4717 4717 dp->rxthr = gem_prop_get_int(dp, "rxthr", dp->rxthr);
4718 4718 dp->txmaxdma = gem_prop_get_int(dp, "txmaxdma", dp->txmaxdma);
4719 4719 dp->rxmaxdma = gem_prop_get_int(dp, "rxmaxdma", dp->rxmaxdma);
4720 4720 }
4721 4721
4722 4722
4723 4723 /*
4724 4724 * Gem kstat support
4725 4725 */
4726 4726
4727 4727 #define GEM_LOCAL_DATA_SIZE(gc) \
4728 4728 (sizeof (struct gem_dev) + \
4729 4729 sizeof (struct mcast_addr) * GEM_MAXMC + \
4730 4730 sizeof (struct txbuf) * ((gc)->gc_tx_buf_size) + \
4731 4731 sizeof (void *) * ((gc)->gc_tx_buf_size))
4732 4732
4733 4733 struct gem_dev *
4734 4734 gem_do_attach(dev_info_t *dip, int port,
4735 4735 struct gem_conf *gc, void *base, ddi_acc_handle_t *regs_handlep,
4736 4736 void *lp, int lmsize)
4737 4737 {
4738 4738 struct gem_dev *dp;
4739 4739 int i;
4740 4740 ddi_iblock_cookie_t c;
4741 4741 mac_register_t *macp = NULL;
4742 4742 int ret;
4743 4743 int unit;
4744 4744 int nports;
4745 4745
4746 4746 unit = ddi_get_instance(dip);
4747 4747 if ((nports = gc->gc_nports) == 0) {
4748 4748 nports = 1;
4749 4749 }
4750 4750 if (nports == 1) {
4751 4751 ddi_set_driver_private(dip, NULL);
4752 4752 }
4753 4753
4754 4754 DPRINTF(2, (CE_CONT, "!gem%d: gem_do_attach: called cmd:ATTACH",
4755 4755 unit));
4756 4756
4757 4757 /*
4758 4758 * Allocate soft data structure
4759 4759 */
4760 4760 dp = kmem_zalloc(GEM_LOCAL_DATA_SIZE(gc), KM_SLEEP);
4761 4761
4762 4762 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
4763 4763 cmn_err(CE_WARN, "!gem%d: %s: mac_alloc failed",
4764 4764 unit, __func__);
4765 4765 return (NULL);
4766 4766 }
4767 4767 /* ddi_set_driver_private(dip, dp); */
4768 4768
4769 4769 /* link to private area */
4770 4770 dp->private = lp;
4771 4771 dp->priv_size = lmsize;
4772 4772 dp->mc_list = (struct mcast_addr *)&dp[1];
4773 4773
4774 4774 dp->dip = dip;
4775 4775 (void) sprintf(dp->name, gc->gc_name, nports * unit + port);
4776 4776
4777 4777 /*
4778 4778 * Get iblock cookie
4779 4779 */
4780 4780 if (ddi_get_iblock_cookie(dip, 0, &c) != DDI_SUCCESS) {
4781 4781 cmn_err(CE_CONT,
4782 4782 "!%s: gem_do_attach: ddi_get_iblock_cookie: failed",
4783 4783 dp->name);
4784 4784 goto err_free_private;
4785 4785 }
4786 4786 dp->iblock_cookie = c;
4787 4787
4788 4788 /*
4789 4789 * Initialize mutex's for this device.
4790 4790 */
4791 4791 mutex_init(&dp->intrlock, NULL, MUTEX_DRIVER, (void *)c);
4792 4792 mutex_init(&dp->xmitlock, NULL, MUTEX_DRIVER, (void *)c);
4793 4793 cv_init(&dp->tx_drain_cv, NULL, CV_DRIVER, NULL);
4794 4794
4795 4795 /*
4796 4796 * configure gem parameter
4797 4797 */
4798 4798 dp->base_addr = base;
4799 4799 dp->regs_handle = *regs_handlep;
4800 4800 dp->gc = *gc;
4801 4801 gc = &dp->gc;
4802 4802 /* patch for simplify dma resource management */
4803 4803 gc->gc_tx_max_frags = 1;
4804 4804 gc->gc_tx_max_descs_per_pkt = 1;
4805 4805 gc->gc_tx_ring_size = gc->gc_tx_buf_size;
4806 4806 gc->gc_tx_ring_limit = gc->gc_tx_buf_limit;
4807 4807 gc->gc_tx_desc_write_oo = B_TRUE;
4808 4808
4809 4809 gc->gc_nports = nports; /* fix nports */
4810 4810
4811 4811 /* fix copy threadsholds */
4812 4812 gc->gc_tx_copy_thresh = max(ETHERMIN, gc->gc_tx_copy_thresh);
4813 4813 gc->gc_rx_copy_thresh = max(ETHERMIN, gc->gc_rx_copy_thresh);
4814 4814
4815 4815 /* fix rx buffer boundary for iocache line size */
4816 4816 ASSERT(gc->gc_dma_attr_txbuf.dma_attr_align-1 == gc->gc_tx_buf_align);
4817 4817 ASSERT(gc->gc_dma_attr_rxbuf.dma_attr_align-1 == gc->gc_rx_buf_align);
4818 4818 gc->gc_rx_buf_align = max(gc->gc_rx_buf_align, IOC_LINESIZE - 1);
4819 4819 gc->gc_dma_attr_rxbuf.dma_attr_align = gc->gc_rx_buf_align + 1;
4820 4820
4821 4821 /* fix descriptor boundary for cache line size */
4822 4822 gc->gc_dma_attr_desc.dma_attr_align =
4823 4823 max(gc->gc_dma_attr_desc.dma_attr_align, IOC_LINESIZE);
4824 4824
4825 4825 /* patch get_packet method */
4826 4826 if (gc->gc_get_packet == NULL) {
4827 4827 gc->gc_get_packet = &gem_get_packet_default;
4828 4828 }
4829 4829
4830 4830 /* patch get_rx_start method */
4831 4831 if (gc->gc_rx_start == NULL) {
4832 4832 gc->gc_rx_start = &gem_rx_start_default;
4833 4833 }
4834 4834
4835 4835 /* calculate descriptor area */
4836 4836 if (gc->gc_rx_desc_unit_shift >= 0) {
4837 4837 dp->rx_desc_size =
4838 4838 ROUNDUP(gc->gc_rx_ring_size << gc->gc_rx_desc_unit_shift,
4839 4839 gc->gc_dma_attr_desc.dma_attr_align);
4840 4840 }
4841 4841 if (gc->gc_tx_desc_unit_shift >= 0) {
4842 4842 dp->tx_desc_size =
4843 4843 ROUNDUP(gc->gc_tx_ring_size << gc->gc_tx_desc_unit_shift,
4844 4844 gc->gc_dma_attr_desc.dma_attr_align);
4845 4845 }
4846 4846
4847 4847 dp->mtu = ETHERMTU;
4848 4848 dp->tx_buf = (void *)&dp->mc_list[GEM_MAXMC];
4849 4849 /* link tx buffers */
4850 4850 for (i = 0; i < dp->gc.gc_tx_buf_size; i++) {
4851 4851 dp->tx_buf[i].txb_next =
4852 4852 &dp->tx_buf[SLOT(i + 1, dp->gc.gc_tx_buf_size)];
4853 4853 }
4854 4854
4855 4855 dp->rxmode = 0;
4856 4856 dp->speed = GEM_SPD_10; /* default is 10Mbps */
4857 4857 dp->full_duplex = B_FALSE; /* default is half */
4858 4858 dp->flow_control = FLOW_CONTROL_NONE;
4859 4859 dp->poll_pkt_delay = 8; /* typical coalease for rx packets */
4860 4860
4861 4861 /* performance tuning parameters */
4862 4862 dp->txthr = ETHERMAX; /* tx fifo threshold */
4863 4863 dp->txmaxdma = 16*4; /* tx max dma burst size */
4864 4864 dp->rxthr = 128; /* rx fifo threshold */
4865 4865 dp->rxmaxdma = 16*4; /* rx max dma burst size */
4866 4866
4867 4867 /*
4868 4868 * Get media mode information from .conf file
4869 4869 */
4870 4870 gem_read_conf(dp);
4871 4871
4872 4872 /* rx_buf_len is required buffer length without padding for alignment */
4873 4873 dp->rx_buf_len = MAXPKTBUF(dp) + dp->gc.gc_rx_header_len;
4874 4874
4875 4875 /*
4876 4876 * Reset the chip
4877 4877 */
4878 4878 mutex_enter(&dp->intrlock);
4879 4879 dp->nic_state = NIC_STATE_STOPPED;
4880 4880 ret = (*dp->gc.gc_reset_chip)(dp);
4881 4881 mutex_exit(&dp->intrlock);
4882 4882 if (ret != GEM_SUCCESS) {
4883 4883 goto err_free_regs;
4884 4884 }
4885 4885
4886 4886 /*
4887 4887 * HW dependant paremeter initialization
4888 4888 */
4889 4889 mutex_enter(&dp->intrlock);
4890 4890 ret = (*dp->gc.gc_attach_chip)(dp);
4891 4891 mutex_exit(&dp->intrlock);
4892 4892 if (ret != GEM_SUCCESS) {
4893 4893 goto err_free_regs;
4894 4894 }
4895 4895
4896 4896 #ifdef DEBUG_MULTIFRAGS
4897 4897 dp->gc.gc_tx_copy_thresh = dp->mtu;
4898 4898 #endif
4899 4899 /* allocate tx and rx resources */
4900 4900 if (gem_alloc_memory(dp)) {
4901 4901 goto err_free_regs;
4902 4902 }
4903 4903
4904 4904 DPRINTF(0, (CE_CONT,
4905 4905 "!%s: at 0x%x, %02x:%02x:%02x:%02x:%02x:%02x",
4906 4906 dp->name, (long)dp->base_addr,
4907 4907 dp->dev_addr.ether_addr_octet[0],
4908 4908 dp->dev_addr.ether_addr_octet[1],
4909 4909 dp->dev_addr.ether_addr_octet[2],
4910 4910 dp->dev_addr.ether_addr_octet[3],
4911 4911 dp->dev_addr.ether_addr_octet[4],
4912 4912 dp->dev_addr.ether_addr_octet[5]));
4913 4913
4914 4914 /* copy mac address */
4915 4915 dp->cur_addr = dp->dev_addr;
4916 4916
4917 4917 gem_gld3_init(dp, macp);
4918 4918
4919 4919 /* Probe MII phy (scan phy) */
4920 4920 dp->mii_lpable = 0;
4921 4921 dp->mii_advert = 0;
4922 4922 dp->mii_exp = 0;
4923 4923 dp->mii_ctl1000 = 0;
4924 4924 dp->mii_stat1000 = 0;
4925 4925 if ((*dp->gc.gc_mii_probe)(dp) != GEM_SUCCESS) {
4926 4926 goto err_free_ring;
4927 4927 }
4928 4928
4929 4929 /* mask unsupported abilities */
4930 4930 dp->anadv_autoneg &= BOOLEAN(dp->mii_status & MII_STATUS_CANAUTONEG);
4931 4931 dp->anadv_1000fdx &=
4932 4932 BOOLEAN(dp->mii_xstatus &
4933 4933 (MII_XSTATUS_1000BASEX_FD | MII_XSTATUS_1000BASET_FD));
4934 4934 dp->anadv_1000hdx &=
4935 4935 BOOLEAN(dp->mii_xstatus &
4936 4936 (MII_XSTATUS_1000BASEX | MII_XSTATUS_1000BASET));
4937 4937 dp->anadv_100t4 &= BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);
4938 4938 dp->anadv_100fdx &= BOOLEAN(dp->mii_status & MII_STATUS_100_BASEX_FD);
4939 4939 dp->anadv_100hdx &= BOOLEAN(dp->mii_status & MII_STATUS_100_BASEX);
4940 4940 dp->anadv_10fdx &= BOOLEAN(dp->mii_status & MII_STATUS_10_FD);
4941 4941 dp->anadv_10hdx &= BOOLEAN(dp->mii_status & MII_STATUS_10);
4942 4942
4943 4943 gem_choose_forcedmode(dp);
4944 4944
4945 4945 /* initialize MII phy if required */
4946 4946 if (dp->gc.gc_mii_init) {
4947 4947 if ((*dp->gc.gc_mii_init)(dp) != GEM_SUCCESS) {
4948 4948 goto err_free_ring;
4949 4949 }
4950 4950 }
4951 4951
4952 4952 /*
4953 4953 * initialize kstats including mii statistics
4954 4954 */
4955 4955 gem_nd_setup(dp);
4956 4956
4957 4957 /*
4958 4958 * Add interrupt to system.
4959 4959 */
4960 4960 if (ret = mac_register(macp, &dp->mh)) {
4961 4961 cmn_err(CE_WARN, "!%s: mac_register failed, error:%d",
4962 4962 dp->name, ret);
4963 4963 goto err_release_stats;
4964 4964 }
4965 4965 mac_free(macp);
4966 4966 macp = NULL;
4967 4967
4968 4968 if (dp->misc_flag & GEM_SOFTINTR) {
4969 4969 if (ddi_add_softintr(dip,
4970 4970 DDI_SOFTINT_LOW, &dp->soft_id,
4971 4971 NULL, NULL,
4972 4972 (uint_t (*)(caddr_t))gem_intr,
4973 4973 (caddr_t)dp) != DDI_SUCCESS) {
4974 4974 cmn_err(CE_WARN, "!%s: ddi_add_softintr failed",
4975 4975 dp->name);
4976 4976 goto err_unregister;
4977 4977 }
4978 4978 } else if ((dp->misc_flag & GEM_NOINTR) == 0) {
4979 4979 if (ddi_add_intr(dip, 0, NULL, NULL,
4980 4980 (uint_t (*)(caddr_t))gem_intr,
4981 4981 (caddr_t)dp) != DDI_SUCCESS) {
4982 4982 cmn_err(CE_WARN, "!%s: ddi_add_intr failed", dp->name);
4983 4983 goto err_unregister;
4984 4984 }
4985 4985 } else {
4986 4986 /*
4987 4987 * Dont use interrupt.
4988 4988 * schedule first call of gem_intr_watcher
4989 4989 */
4990 4990 dp->intr_watcher_id =
4991 4991 timeout((void (*)(void *))gem_intr_watcher,
4992 4992 (void *)dp, drv_usectohz(3*1000000));
4993 4993 }
4994 4994
4995 4995 /* link this device to dev_info */
4996 4996 dp->next = (struct gem_dev *)ddi_get_driver_private(dip);
4997 4997 dp->port = port;
4998 4998 ddi_set_driver_private(dip, (caddr_t)dp);
4999 4999
5000 5000 /* reset mii phy and start mii link watcher */
5001 5001 gem_mii_start(dp);
5002 5002
5003 5003 DPRINTF(2, (CE_CONT, "!gem_do_attach: return: success"));
5004 5004 return (dp);
5005 5005
5006 5006 err_unregister:
5007 5007 (void) mac_unregister(dp->mh);
5008 5008 err_release_stats:
5009 5009 /* release NDD resources */
5010 5010 gem_nd_cleanup(dp);
5011 5011
5012 5012 err_free_ring:
5013 5013 gem_free_memory(dp);
5014 5014 err_free_regs:
5015 5015 ddi_regs_map_free(&dp->regs_handle);
5016 5016 err_free_locks:
5017 5017 mutex_destroy(&dp->xmitlock);
5018 5018 mutex_destroy(&dp->intrlock);
5019 5019 cv_destroy(&dp->tx_drain_cv);
5020 5020 err_free_private:
5021 5021 if (macp) {
5022 5022 mac_free(macp);
5023 5023 }
5024 5024 kmem_free((caddr_t)dp, GEM_LOCAL_DATA_SIZE(gc));
5025 5025
5026 5026 return (NULL);
5027 5027 }
5028 5028
5029 5029 int
5030 5030 gem_do_detach(dev_info_t *dip)
5031 5031 {
5032 5032 struct gem_dev *dp;
5033 5033 struct gem_dev *tmp;
5034 5034 caddr_t private;
5035 5035 int priv_size;
5036 5036 ddi_acc_handle_t rh;
5037 5037
5038 5038 dp = GEM_GET_DEV(dip);
5039 5039 if (dp == NULL) {
5040 5040 return (DDI_SUCCESS);
5041 5041 }
5042 5042
5043 5043 rh = dp->regs_handle;
5044 5044 private = dp->private;
5045 5045 priv_size = dp->priv_size;
5046 5046
5047 5047 while (dp) {
5048 5048 /* unregister with gld v3 */
5049 5049 if (mac_unregister(dp->mh) != 0) {
5050 5050 return (DDI_FAILURE);
5051 5051 }
5052 5052
5053 5053 /* ensure any rx buffers are not used */
5054 5054 if (dp->rx_buf_allocated != dp->rx_buf_freecnt) {
5055 5055 /* resource is busy */
5056 5056 cmn_err(CE_PANIC,
5057 5057 "!%s: %s: rxbuf is busy: allocated:%d, freecnt:%d",
5058 5058 dp->name, __func__,
5059 5059 dp->rx_buf_allocated, dp->rx_buf_freecnt);
5060 5060 /* NOT REACHED */
5061 5061 }
5062 5062
5063 5063 /* stop mii link watcher */
5064 5064 gem_mii_stop(dp);
5065 5065
5066 5066 /* unregister interrupt handler */
5067 5067 if (dp->misc_flag & GEM_SOFTINTR) {
5068 5068 ddi_remove_softintr(dp->soft_id);
5069 5069 } else if ((dp->misc_flag & GEM_NOINTR) == 0) {
5070 5070 ddi_remove_intr(dip, 0, dp->iblock_cookie);
5071 5071 } else {
5072 5072 /* stop interrupt watcher */
5073 5073 if (dp->intr_watcher_id) {
5074 5074 while (untimeout(dp->intr_watcher_id) == -1)
5075 5075 ;
5076 5076 dp->intr_watcher_id = 0;
5077 5077 }
5078 5078 }
5079 5079
5080 5080 /* release NDD resources */
5081 5081 gem_nd_cleanup(dp);
5082 5082 /* release buffers, descriptors and dma resources */
5083 5083 gem_free_memory(dp);
5084 5084
5085 5085 /* release locks and condition variables */
5086 5086 mutex_destroy(&dp->xmitlock);
5087 5087 mutex_destroy(&dp->intrlock);
5088 5088 cv_destroy(&dp->tx_drain_cv);
5089 5089
5090 5090 /* release basic memory resources */
5091 5091 tmp = dp->next;
5092 5092 kmem_free((caddr_t)dp, GEM_LOCAL_DATA_SIZE(&dp->gc));
5093 5093 dp = tmp;
5094 5094 }
5095 5095
5096 5096 /* release common private memory for the nic */
5097 5097 kmem_free(private, priv_size);
5098 5098
5099 5099 /* release register mapping resources */
5100 5100 ddi_regs_map_free(&rh);
5101 5101
5102 5102 DPRINTF(2, (CE_CONT, "!%s%d: gem_do_detach: return: success",
5103 5103 ddi_driver_name(dip), ddi_get_instance(dip)));
5104 5104
5105 5105 return (DDI_SUCCESS);
5106 5106 }
5107 5107
5108 5108 int
5109 5109 gem_suspend(dev_info_t *dip)
5110 5110 {
5111 5111 struct gem_dev *dp;
5112 5112
5113 5113 /*
5114 5114 * stop the device
5115 5115 */
5116 5116 dp = GEM_GET_DEV(dip);
5117 5117 ASSERT(dp);
5118 5118
5119 5119 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
5120 5120
5121 5121 for (; dp; dp = dp->next) {
5122 5122
5123 5123 /* stop mii link watcher */
5124 5124 gem_mii_stop(dp);
5125 5125
5126 5126 /* stop interrupt watcher for no-intr mode */
5127 5127 if (dp->misc_flag & GEM_NOINTR) {
5128 5128 if (dp->intr_watcher_id) {
5129 5129 while (untimeout(dp->intr_watcher_id) == -1)
5130 5130 ;
5131 5131 }
5132 5132 dp->intr_watcher_id = 0;
5133 5133 }
5134 5134
5135 5135 /* stop tx timeout watcher */
5136 5136 if (dp->timeout_id) {
5137 5137 while (untimeout(dp->timeout_id) == -1)
5138 5138 ;
5139 5139 dp->timeout_id = 0;
5140 5140 }
5141 5141
5142 5142 /* make the nic state inactive */
5143 5143 mutex_enter(&dp->intrlock);
5144 5144 (void) gem_mac_stop(dp, 0);
5145 5145 ASSERT(!dp->mac_active);
5146 5146
5147 5147 /* no further register access */
5148 5148 dp->mac_suspended = B_TRUE;
5149 5149 mutex_exit(&dp->intrlock);
5150 5150 }
5151 5151
5152 5152 /* XXX - power down the nic */
5153 5153
5154 5154 return (DDI_SUCCESS);
5155 5155 }
5156 5156
5157 5157 int
5158 5158 gem_resume(dev_info_t *dip)
5159 5159 {
5160 5160 struct gem_dev *dp;
5161 5161
5162 5162 /*
5163 5163 * restart the device
5164 5164 */
5165 5165 dp = GEM_GET_DEV(dip);
5166 5166 ASSERT(dp);
5167 5167
5168 5168 DPRINTF(0, (CE_CONT, "!%s: %s: called", dp->name, __func__));
5169 5169
5170 5170 for (; dp; dp = dp->next) {
5171 5171
5172 5172 /*
5173 5173 * Bring up the nic after power up
5174 5174 */
5175 5175
5176 5176 /* gem_xxx.c layer to setup power management state. */
5177 5177 ASSERT(!dp->mac_active);
5178 5178
5179 5179 /* reset the chip, because we are just after power up. */
5180 5180 mutex_enter(&dp->intrlock);
5181 5181
5182 5182 dp->mac_suspended = B_FALSE;
5183 5183 dp->nic_state = NIC_STATE_STOPPED;
5184 5184
5185 5185 if ((*dp->gc.gc_reset_chip)(dp) != GEM_SUCCESS) {
5186 5186 cmn_err(CE_WARN, "%s: %s: failed to reset chip",
5187 5187 dp->name, __func__);
5188 5188 mutex_exit(&dp->intrlock);
5189 5189 goto err;
5190 5190 }
5191 5191 mutex_exit(&dp->intrlock);
5192 5192
5193 5193 /* initialize mii phy because we are just after power up */
5194 5194 if (dp->gc.gc_mii_init) {
5195 5195 (void) (*dp->gc.gc_mii_init)(dp);
5196 5196 }
5197 5197
5198 5198 if (dp->misc_flag & GEM_NOINTR) {
5199 5199 /*
5200 5200 * schedule first call of gem_intr_watcher
5201 5201 * instead of interrupts.
5202 5202 */
5203 5203 dp->intr_watcher_id =
5204 5204 timeout((void (*)(void *))gem_intr_watcher,
5205 5205 (void *)dp, drv_usectohz(3*1000000));
5206 5206 }
5207 5207
5208 5208 /* restart mii link watcher */
5209 5209 gem_mii_start(dp);
5210 5210
5211 5211 /* restart mac */
5212 5212 mutex_enter(&dp->intrlock);
5213 5213
5214 5214 if (gem_mac_init(dp) != GEM_SUCCESS) {
5215 5215 mutex_exit(&dp->intrlock);
5216 5216 goto err_reset;
5217 5217 }
5218 5218 dp->nic_state = NIC_STATE_INITIALIZED;
5219 5219
5220 5220 /* setup media mode if the link have been up */
5221 5221 if (dp->mii_state == MII_STATE_LINKUP) {
5222 5222 if ((dp->gc.gc_set_media)(dp) != GEM_SUCCESS) {
5223 5223 mutex_exit(&dp->intrlock);
5224 5224 goto err_reset;
5225 5225 }
5226 5226 }
5227 5227
5228 5228 /* enable mac address and rx filter */
5229 5229 dp->rxmode |= RXMODE_ENABLE;
5230 5230 if ((*dp->gc.gc_set_rx_filter)(dp) != GEM_SUCCESS) {
5231 5231 mutex_exit(&dp->intrlock);
5232 5232 goto err_reset;
5233 5233 }
5234 5234 dp->nic_state = NIC_STATE_ONLINE;
5235 5235
5236 5236 /* restart tx timeout watcher */
5237 5237 dp->timeout_id = timeout((void (*)(void *))gem_tx_timeout,
5238 5238 (void *)dp,
5239 5239 dp->gc.gc_tx_timeout_interval);
5240 5240
5241 5241 /* now the nic is fully functional */
5242 5242 if (dp->mii_state == MII_STATE_LINKUP) {
5243 5243 if (gem_mac_start(dp) != GEM_SUCCESS) {
5244 5244 mutex_exit(&dp->intrlock);
5245 5245 goto err_reset;
5246 5246 }
5247 5247 }
5248 5248 mutex_exit(&dp->intrlock);
5249 5249 }
5250 5250
5251 5251 return (DDI_SUCCESS);
5252 5252
5253 5253 err_reset:
5254 5254 if (dp->intr_watcher_id) {
5255 5255 while (untimeout(dp->intr_watcher_id) == -1)
5256 5256 ;
5257 5257 dp->intr_watcher_id = 0;
5258 5258 }
5259 5259 mutex_enter(&dp->intrlock);
5260 5260 (*dp->gc.gc_reset_chip)(dp);
5261 5261 dp->nic_state = NIC_STATE_STOPPED;
5262 5262 mutex_exit(&dp->intrlock);
5263 5263
5264 5264 err:
5265 5265 return (DDI_FAILURE);
5266 5266 }
5267 5267
5268 5268 /*
5269 5269 * misc routines for PCI
5270 5270 */
5271 5271 uint8_t
5272 5272 gem_search_pci_cap(dev_info_t *dip,
5273 5273 ddi_acc_handle_t conf_handle, uint8_t target)
5274 5274 {
5275 5275 uint8_t pci_cap_ptr;
5276 5276 uint32_t pci_cap;
5277 5277
5278 5278 /* search power management capablities */
5279 5279 pci_cap_ptr = pci_config_get8(conf_handle, PCI_CONF_CAP_PTR);
5280 5280 while (pci_cap_ptr) {
5281 5281 /* read pci capability header */
5282 5282 pci_cap = pci_config_get32(conf_handle, pci_cap_ptr);
5283 5283 if ((pci_cap & 0xff) == target) {
5284 5284 /* found */
5285 5285 break;
5286 5286 }
5287 5287 /* get next_ptr */
5288 5288 pci_cap_ptr = (pci_cap >> 8) & 0xff;
5289 5289 }
5290 5290 return (pci_cap_ptr);
5291 5291 }
5292 5292
5293 5293 int
5294 5294 gem_pci_set_power_state(dev_info_t *dip,
5295 5295 ddi_acc_handle_t conf_handle, uint_t new_mode)
5296 5296 {
5297 5297 uint8_t pci_cap_ptr;
5298 5298 uint32_t pmcsr;
5299 5299 uint_t unit;
5300 5300 const char *drv_name;
5301 5301
5302 5302 ASSERT(new_mode < 4);
5303 5303
5304 5304 unit = ddi_get_instance(dip);
5305 5305 drv_name = ddi_driver_name(dip);
5306 5306
5307 5307 /* search power management capablities */
5308 5308 pci_cap_ptr = gem_search_pci_cap(dip, conf_handle, PCI_CAP_ID_PM);
5309 5309
5310 5310 if (pci_cap_ptr == 0) {
5311 5311 cmn_err(CE_CONT,
5312 5312 "!%s%d: doesn't have pci power management capability",
5313 5313 drv_name, unit);
5314 5314 return (DDI_FAILURE);
5315 5315 }
5316 5316
5317 5317 /* read power management capabilities */
5318 5318 pmcsr = pci_config_get32(conf_handle, pci_cap_ptr + PCI_PMCSR);
5319 5319
5320 5320 DPRINTF(0, (CE_CONT,
5321 5321 "!%s%d: pmc found at 0x%x: pmcsr: 0x%08x",
5322 5322 drv_name, unit, pci_cap_ptr, pmcsr));
5323 5323
5324 5324 /*
5325 5325 * Is the resuested power mode supported?
5326 5326 */
5327 5327 /* not yet */
5328 5328
5329 5329 /*
5330 5330 * move to new mode
5331 5331 */
5332 5332 pmcsr = (pmcsr & ~PCI_PMCSR_STATE_MASK) | new_mode;
5333 5333 pci_config_put32(conf_handle, pci_cap_ptr + PCI_PMCSR, pmcsr);
5334 5334
5335 5335 return (DDI_SUCCESS);
5336 5336 }
5337 5337
5338 5338 /*
5339 5339 * select suitable register for by specified address space or register
5340 5340 * offset in PCI config space
5341 5341 */
5342 5342 int
5343 5343 gem_pci_regs_map_setup(dev_info_t *dip, uint32_t which, uint32_t mask,
5344 5344 struct ddi_device_acc_attr *attrp,
5345 5345 caddr_t *basep, ddi_acc_handle_t *hp)
5346 5346 {
5347 5347 struct pci_phys_spec *regs;
5348 5348 uint_t len;
5349 5349 uint_t unit;
5350 5350 uint_t n;
5351 5351 uint_t i;
5352 5352 int ret;
5353 5353 const char *drv_name;
5354 5354
5355 5355 unit = ddi_get_instance(dip);
5356 5356 drv_name = ddi_driver_name(dip);
5357 5357
5358 5358 /* Search IO-range or memory-range to be mapped */
5359 5359 regs = NULL;
5360 5360 len = 0;
5361 5361
5362 5362 if ((ret = ddi_prop_lookup_int_array(
5363 5363 DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
5364 5364 "reg", (void *)®s, &len)) != DDI_PROP_SUCCESS) {
5365 5365 cmn_err(CE_WARN,
5366 5366 "!%s%d: failed to get reg property (ret:%d)",
5367 5367 drv_name, unit, ret);
5368 5368 return (DDI_FAILURE);
5369 5369 }
5370 5370 n = len / (sizeof (struct pci_phys_spec) / sizeof (int));
5371 5371
5372 5372 ASSERT(regs != NULL && len > 0);
5373 5373
5374 5374 #if GEM_DEBUG_LEVEL > 0
5375 5375 for (i = 0; i < n; i++) {
5376 5376 cmn_err(CE_CONT,
5377 5377 "!%s%d: regs[%d]: %08x.%08x.%08x.%08x.%08x",
5378 5378 drv_name, unit, i,
5379 5379 regs[i].pci_phys_hi,
5380 5380 regs[i].pci_phys_mid,
5381 5381 regs[i].pci_phys_low,
5382 5382 regs[i].pci_size_hi,
5383 5383 regs[i].pci_size_low);
5384 5384 }
5385 5385 #endif
5386 5386 for (i = 0; i < n; i++) {
5387 5387 if ((regs[i].pci_phys_hi & mask) == which) {
5388 5388 /* it's the requested space */
5389 5389 ddi_prop_free(regs);
5390 5390 goto address_range_found;
5391 5391 }
5392 5392 }
5393 5393 ddi_prop_free(regs);
5394 5394 return (DDI_FAILURE);
5395 5395
5396 5396 address_range_found:
5397 5397 if ((ret = ddi_regs_map_setup(dip, i, basep, 0, 0, attrp, hp))
5398 5398 != DDI_SUCCESS) {
5399 5399 cmn_err(CE_CONT,
5400 5400 "!%s%d: ddi_regs_map_setup failed (ret:%d)",
5401 5401 drv_name, unit, ret);
5402 5402 }
5403 5403
5404 5404 return (ret);
5405 5405 }
5406 5406
5407 5407 void
5408 5408 gem_mod_init(struct dev_ops *dop, char *name)
5409 5409 {
5410 5410 mac_init_ops(dop, name);
5411 5411 }
5412 5412
5413 5413 void
5414 5414 gem_mod_fini(struct dev_ops *dop)
5415 5415 {
5416 5416 mac_fini_ops(dop);
5417 5417 }
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