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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/common/io/rwn/rt2860.c
+++ new/usr/src/uts/common/io/rwn/rt2860.c
1 1 /*
2 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 3 * Use is subject to license terms.
4 4 */
5 5
6 6 /*
7 7 * Copyright (c) 2007, 2008
8 8 * Damien Bergamini <damien.bergamini@free.fr>
9 9 *
10 10 * Permission to use, copy, modify, and distribute this software for any
11 11 * purpose with or without fee is hereby granted, provided that the above
12 12 * copyright notice and this permission notice appear in all copies.
13 13 *
14 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 21 */
22 22
23 23 /*
24 24 * Ralink Technology RT2860 chipset driver
25 25 * http://www.ralinktech.com/
26 26 */
27 27
28 28 #include <sys/types.h>
29 29 #include <sys/byteorder.h>
30 30 #include <sys/conf.h>
31 31 #include <sys/cmn_err.h>
32 32 #include <sys/stat.h>
33 33 #include <sys/ddi.h>
34 34 #include <sys/sunddi.h>
35 35 #include <sys/strsubr.h>
36 36 #include <inet/common.h>
37 37 #include <sys/note.h>
38 38 #include <sys/stream.h>
39 39 #include <sys/strsun.h>
40 40 #include <sys/modctl.h>
41 41 #include <sys/devops.h>
42 42 #include <sys/mac_provider.h>
43 43 #include <sys/mac_wifi.h>
44 44 #include <sys/net80211.h>
45 45 #include <sys/net80211_proto.h>
46 46 #include <sys/varargs.h>
47 47 #include <sys/pci.h>
48 48 #include <sys/crypto/common.h>
49 49 #include <sys/crypto/api.h>
50 50 #include <inet/wifi_ioctl.h>
51 51
52 52 #include "rt2860_reg.h"
53 53 #include "rt2860_var.h"
54 54
55 55 #define RT2860_DBG_80211 (1 << 0)
56 56 #define RT2860_DBG_DMA (1 << 1)
57 57 #define RT2860_DBG_EEPROM (1 << 2)
58 58 #define RT2860_DBG_FW (1 << 3)
59 59 #define RT2860_DBG_HW (1 << 4)
60 60 #define RT2860_DBG_INTR (1 << 5)
61 61 #define RT2860_DBG_RX (1 << 6)
62 62 #define RT2860_DBG_SCAN (1 << 7)
63 63 #define RT2860_DBG_TX (1 << 8)
64 64 #define RT2860_DBG_RADIO (1 << 9)
65 65 #define RT2860_DBG_RESUME (1 << 10)
66 66 #define RT2860_DBG_MSG (1 << 11)
67 67
68 68 uint32_t rt2860_dbg_flags = 0x0;
69 69
70 70 #ifdef DEBUG
71 71 #define RWN_DEBUG \
72 72 rt2860_debug
73 73 #else
74 74 #define RWN_DEBUG
75 75 #endif
76 76
77 77 static void *rt2860_soft_state_p = NULL;
78 78 static uint8_t rt2860_fw_bin [] = {
79 79 #include "fw-rt2860/rt2860.ucode"
80 80 };
81 81
82 82 static const struct ieee80211_rateset rt2860_rateset_11b =
83 83 { 4, { 2, 4, 11, 22 } };
84 84
85 85 static const struct ieee80211_rateset rt2860_rateset_11g =
86 86 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
87 87
88 88 static const struct {
89 89 uint32_t reg;
90 90 uint32_t val;
91 91 } rt2860_def_mac[] = {
92 92 RT2860_DEF_MAC
93 93 };
94 94
95 95 static const struct {
96 96 uint8_t reg;
97 97 uint8_t val;
98 98 } rt2860_def_bbp[] = {
99 99 RT2860_DEF_BBP
100 100 };
101 101
102 102 static const struct rfprog {
103 103 uint8_t chan;
104 104 uint32_t r1, r2, r3, r4;
105 105 } rt2860_rf2850[] = {
106 106 RT2860_RF2850
107 107 };
108 108
109 109 /*
110 110 * PIO access attributes for registers
111 111 */
112 112 static ddi_device_acc_attr_t rwn_csr_accattr = {
113 113 DDI_DEVICE_ATTR_V0,
114 114 DDI_STRUCTURE_LE_ACC,
115 115 DDI_STRICTORDER_ACC
116 116 };
117 117
118 118 /*
119 119 * DMA access attributes for descriptors: NOT to be byte swapped.
120 120 */
121 121 static ddi_device_acc_attr_t rt2860_desc_accattr = {
122 122 DDI_DEVICE_ATTR_V0,
123 123 DDI_STRUCTURE_LE_ACC,
124 124 DDI_STRICTORDER_ACC
125 125 };
126 126
127 127 static ddi_device_acc_attr_t rt2860_buf_accattr = {
128 128 DDI_DEVICE_ATTR_V0,
129 129 DDI_NEVERSWAP_ACC,
130 130 DDI_STRICTORDER_ACC,
131 131 DDI_DEFAULT_ACC
132 132 };
133 133
134 134 /*
135 135 * Describes the chip's DMA engine
136 136 */
137 137 static ddi_dma_attr_t rt2860_dma_attr = {
138 138 DMA_ATTR_V0, /* dma_attr version */
139 139 0x0, /* dma_attr_addr_lo */
140 140 0xffffffffU, /* dma_attr_addr_hi */
141 141 0xffffffffU, /* dma_attr_count_max */
142 142 16, /* dma_attr_align */
143 143 0x00000fff, /* dma_attr_burstsizes */
144 144 1, /* dma_attr_minxfer */
145 145 0xffffffffU, /* dma_attr_maxxfer */
146 146 0xffffffffU, /* dma_attr_seg */
147 147 1, /* dma_attr_sgllen */
148 148 1, /* dma_attr_granular */
149 149 0 /* dma_attr_flags */
150 150 };
151 151
152 152 static uint16_t rt2860_eeprom_read(struct rt2860_softc *, uint8_t);
153 153 static int rt2860_read_eeprom(struct rt2860_softc *);
154 154 const char *rt2860_get_rf(uint8_t);
155 155 static int rt2860_alloc_dma_mem(dev_info_t *, ddi_dma_attr_t *, size_t,
156 156 ddi_device_acc_attr_t *, uint_t, uint_t, struct dma_area *);
157 157 static void rt2860_free_dma_mem(struct dma_area *);
158 158 static int rt2860_alloc_tx_ring(struct rt2860_softc *,
159 159 struct rt2860_tx_ring *);
160 160 static void rt2860_free_tx_ring(struct rt2860_softc *,
161 161 struct rt2860_tx_ring *);
162 162 static int rt2860_alloc_rx_ring(struct rt2860_softc *,
163 163 struct rt2860_rx_ring *);
164 164 static void rt2860_free_rx_ring(struct rt2860_softc *,
165 165 struct rt2860_rx_ring *);
166 166 static int rt2860_alloc_tx_pool(struct rt2860_softc *);
167 167 static void rt2860_free_tx_pool(struct rt2860_softc *);
168 168 static uint16_t rt2860_txtime(int, int, uint32_t);
169 169 static int rt2860_ack_rate(struct ieee80211com *, int);
170 170 static int rt2860_send(ieee80211com_t *, mblk_t *, uint8_t);
171 171 static uint8_t rt2860_maxrssi_chain(struct rt2860_softc *,
172 172 const struct rt2860_rxwi *);
173 173 static void rt2860_drain_stats_fifo(struct rt2860_softc *);
174 174 static void rt2860_tx_intr(struct rt2860_softc *, int);
175 175 static void rt2860_rx_intr(struct rt2860_softc *);
176 176 static uint_t rt2860_softintr(caddr_t);
177 177 static uint_t rt2860_intr(caddr_t);
178 178 static void rt2860_set_region_4(struct rt2860_softc *,
179 179 uint32_t, uint32_t, int);
180 180 static int rt2860_load_microcode(struct rt2860_softc *);
181 181 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
182 182 static int rt2860_bbp_init(struct rt2860_softc *);
183 183 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
184 184 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
185 185 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t);
186 186 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
187 187 static void rt2860_select_chan_group(struct rt2860_softc *, int);
188 188 static void rt2860_set_chan(struct rt2860_softc *,
189 189 struct ieee80211_channel *);
190 190 static void rt2860_updateprot(struct ieee80211com *);
191 191 static void rt2860_set_leds(struct rt2860_softc *, uint16_t);
192 192 static void rt2860_next_scan(void *);
193 193 static void rt2860_iter_func(void *, struct ieee80211_node *);
194 194 static void rt2860_updateslot(struct rt2860_softc *);
195 195 static uint8_t rt2860_rate2mcs(uint8_t);
196 196 static void rt2860_enable_mrr(struct rt2860_softc *);
197 197 static void rt2860_set_txpreamble(struct rt2860_softc *);
198 198 static void rt2860_set_basicrates(struct rt2860_softc *);
199 199 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
200 200 static void rt2860_amrr_node_init(const struct rt2860_amrr *,
201 201 struct rt2860_amrr_node *);
202 202 static void rt2860_amrr_choose(struct rt2860_amrr *,
203 203 struct ieee80211_node *, struct rt2860_amrr_node *);
204 204 static void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *,
205 205 int);
206 206 static void rt2860_enable_tsf_sync(struct rt2860_softc *);
207 207 static int rt2860_newstate(struct ieee80211com *,
208 208 enum ieee80211_state, int);
209 209 static int rt2860_init(struct rt2860_softc *);
210 210 static void rt2860_stop(struct rt2860_softc *);
211 211 static int rt2860_quiesce(dev_info_t *t);
212 212
213 213 /*
214 214 * device operations
215 215 */
216 216 static int rt2860_attach(dev_info_t *, ddi_attach_cmd_t);
217 217 static int rt2860_detach(dev_info_t *, ddi_detach_cmd_t);
218 218
219 219 /*
220 220 * Module Loading Data & Entry Points
221 221 */
222 222 DDI_DEFINE_STREAM_OPS(rwn_dev_ops, nulldev, nulldev, rt2860_attach,
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223 223 rt2860_detach, nodev, NULL, D_MP, NULL, rt2860_quiesce);
224 224
225 225 static struct modldrv rwn_modldrv = {
226 226 &mod_driverops, /* Type of module. This one is a driver */
227 227 "Ralink RT2700/2800 driver v1.2", /* short description */
228 228 &rwn_dev_ops /* driver specific ops */
229 229 };
230 230
231 231 static struct modlinkage modlinkage = {
232 232 MODREV_1,
233 - (void *)&rwn_modldrv,
234 - NULL
233 + { (void *)&rwn_modldrv, NULL }
235 234 };
236 235
237 236 static int rt2860_m_stat(void *, uint_t, uint64_t *);
238 237 static int rt2860_m_start(void *);
239 238 static void rt2860_m_stop(void *);
240 239 static int rt2860_m_promisc(void *, boolean_t);
241 240 static int rt2860_m_multicst(void *, boolean_t, const uint8_t *);
242 241 static int rt2860_m_unicst(void *, const uint8_t *);
243 242 static mblk_t *rt2860_m_tx(void *, mblk_t *);
244 243 static void rt2860_m_ioctl(void *, queue_t *, mblk_t *);
245 244 static int rt2860_m_setprop(void *arg, const char *pr_name,
246 245 mac_prop_id_t wldp_pr_num,
247 246 uint_t wldp_length, const void *wldp_buf);
248 247 static void rt2860_m_propinfo(void *arg, const char *pr_name,
249 248 mac_prop_id_t wldp_pr_num, mac_prop_info_handle_t prh);
250 249 static int rt2860_m_getprop(void *arg, const char *pr_name,
251 250 mac_prop_id_t wldp_pr_num, uint_t wldp_length,
252 251 void *wldp_buf);
253 252
254 253 static mac_callbacks_t rt2860_m_callbacks = {
255 254 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
256 255 rt2860_m_stat,
257 256 rt2860_m_start,
258 257 rt2860_m_stop,
259 258 rt2860_m_promisc,
260 259 rt2860_m_multicst,
261 260 rt2860_m_unicst,
262 261 rt2860_m_tx,
263 262 NULL,
264 263 rt2860_m_ioctl,
265 264 NULL,
266 265 NULL,
267 266 NULL,
268 267 rt2860_m_setprop,
269 268 rt2860_m_getprop,
270 269 rt2860_m_propinfo
271 270 };
272 271
273 272 #ifdef DEBUG
274 273 void
275 274 rt2860_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
276 275 {
277 276 va_list args;
278 277
279 278 if (dbg_flags & rt2860_dbg_flags) {
280 279 va_start(args, fmt);
281 280 vcmn_err(CE_CONT, fmt, args);
282 281 va_end(args);
283 282 }
284 283 }
285 284 #endif
286 285
287 286 const char *
288 287 rt2860_get_rf(uint8_t rev)
289 288 {
290 289 switch (rev) {
291 290 case RT2860_RF_2820: return "RT2820";
292 291 case RT2860_RF_2850: return "RT2850";
293 292 case RT2860_RF_2720: return "RT2720";
294 293 case RT2860_RF_2750: return "RT2750";
295 294 default: return "unknown";
296 295 }
297 296 }
298 297
299 298 /*
300 299 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
301 300 * 93C66 or 93C86).
302 301 */
303 302 static uint16_t
304 303 rt2860_eeprom_read(struct rt2860_softc *sc, uint8_t addr)
305 304 {
306 305 int n;
307 306 uint16_t val;
308 307 uint32_t tmp;
309 308
310 309 /* clock C once before the first command */
311 310 RT2860_EEPROM_CTL(sc, 0);
312 311
313 312 RT2860_EEPROM_CTL(sc, RT2860_S);
314 313 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
315 314 RT2860_EEPROM_CTL(sc, RT2860_S);
316 315
317 316 /* write start bit (1) */
318 317 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
319 318 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
320 319
321 320 /* write READ opcode (10) */
322 321 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
323 322 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
324 323 RT2860_EEPROM_CTL(sc, RT2860_S);
325 324 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
326 325
327 326 /* write address (A5-A0 or A7-A0) */
328 327 n = ((RT2860_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
329 328 for (; n >= 0; n--) {
330 329 RT2860_EEPROM_CTL(sc, RT2860_S |
331 330 (((addr >> n) & 1) << RT2860_SHIFT_D));
332 331 RT2860_EEPROM_CTL(sc, RT2860_S |
333 332 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
334 333 }
335 334
336 335 RT2860_EEPROM_CTL(sc, RT2860_S);
337 336
338 337 /* read data Q15-Q0 */
339 338 val = 0;
340 339 for (n = 15; n >= 0; n--) {
341 340 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
342 341 tmp = RT2860_READ(sc, RT2860_PCI_EECTRL);
343 342 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
344 343 RT2860_EEPROM_CTL(sc, RT2860_S);
345 344 }
346 345
347 346 RT2860_EEPROM_CTL(sc, 0);
348 347
349 348 /* clear Chip Select and clock C */
350 349 RT2860_EEPROM_CTL(sc, RT2860_S);
351 350 RT2860_EEPROM_CTL(sc, 0);
352 351 RT2860_EEPROM_CTL(sc, RT2860_C);
353 352
354 353 return (val);
355 354 }
356 355
357 356 /*
358 357 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
359 358 * Used to adjust per-rate Tx power registers.
360 359 */
361 360 static inline uint32_t
362 361 b4inc(uint32_t b32, int8_t delta)
363 362 {
364 363 int8_t i, b4;
365 364
366 365 for (i = 0; i < 8; i++) {
367 366 b4 = b32 & 0xf;
368 367 b4 += delta;
369 368 if (b4 < 0)
370 369 b4 = 0;
371 370 else if (b4 > 0xf)
372 371 b4 = 0xf;
373 372 b32 = b32 >> 4 | b4 << 28;
374 373 }
375 374 return (b32);
376 375 }
377 376
378 377 static int
379 378 rt2860_read_eeprom(struct rt2860_softc *sc)
380 379 {
381 380 struct ieee80211com *ic = &sc->sc_ic;
382 381 int ridx, ant, i;
383 382 int8_t delta_2ghz, delta_5ghz;
384 383 uint16_t val;
385 384
386 385 /* read EEPROM version */
387 386 val = rt2860_eeprom_read(sc, RT2860_EEPROM_VERSION);
388 387 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
389 388 "EEPROM rev=%d, FAE=%d\n",
390 389 val & 0xff, val >> 8);
391 390
392 391 /* read MAC address */
393 392 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC01);
394 393 ic->ic_macaddr[0] = val & 0xff;
395 394 ic->ic_macaddr[1] = val >> 8;
396 395 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC23);
397 396 ic->ic_macaddr[2] = val & 0xff;
398 397 ic->ic_macaddr[3] = val >> 8;
399 398 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC45);
400 399 ic->ic_macaddr[4] = val & 0xff;
401 400 ic->ic_macaddr[5] = val >> 8;
402 401 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
403 402 "MAC address is: %x:%x:%x:%x:%x:%x\n",
404 403 ic->ic_macaddr[0], ic->ic_macaddr[1],
405 404 ic->ic_macaddr[2], ic->ic_macaddr[3],
406 405 ic->ic_macaddr[4], ic->ic_macaddr[5]);
407 406
408 407 /* read country code */
409 408 val = rt2860_eeprom_read(sc, RT2860_EEPROM_COUNTRY);
410 409 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
411 410 "EEPROM region code=0x%04x\n", val);
412 411
413 412 /* read default BBP settings */
414 413 for (i = 0; i < 8; i++) {
415 414 val = rt2860_eeprom_read(sc, RT2860_EEPROM_BBP_BASE + i);
416 415 sc->bbp[i].val = val & 0xff;
417 416 sc->bbp[i].reg = val >> 8;
418 417 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
419 418 "BBP%d=0x%02x\n",
420 419 sc->bbp[i].reg, sc->bbp[i].val);
421 420 }
422 421
423 422 /* read RF frequency offset from EEPROM */
424 423 val = rt2860_eeprom_read(sc, RT2860_EEPROM_FREQ_LEDS);
425 424 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
426 425 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
427 426 "EEPROM freq offset %d\n", sc->freq & 0xff);
428 427
429 428 if ((sc->leds = val >> 8) != 0xff) {
430 429 /* read LEDs operating mode */
431 430 sc->led[0] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED1);
432 431 sc->led[1] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED2);
433 432 sc->led[2] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED3);
434 433 } else {
435 434 /* broken EEPROM, use default settings */
436 435 sc->leds = 0x01;
437 436 sc->led[0] = 0x5555;
438 437 sc->led[1] = 0x2221;
439 438 sc->led[2] = 0xa9f8;
440 439 }
441 440 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
442 441 "EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
443 442 sc->leds, sc->led[0], sc->led[1], sc->led[2]);
444 443
445 444 /* read RF information */
446 445 val = rt2860_eeprom_read(sc, RT2860_EEPROM_ANTENNA);
447 446 if (val == 0xffff) {
448 447 /* broken EEPROM, default to RF2820 1T2R */
449 448 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
450 449 "invalid EEPROM antenna info, using default\n");
451 450 sc->rf_rev = RT2860_RF_2820;
452 451 sc->ntxchains = 1;
453 452 sc->nrxchains = 2;
454 453 } else {
455 454 sc->rf_rev = (val >> 8) & 0xf;
456 455 sc->ntxchains = (val >> 4) & 0xf;
457 456 sc->nrxchains = val & 0xf;
458 457 }
459 458 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
460 459 "EEPROM RF rev=0x%02x chains=%dT%dR\n",
461 460 sc->rf_rev, sc->ntxchains, sc->nrxchains);
462 461
463 462 /* check if RF supports automatic Tx access gain control */
464 463 val = rt2860_eeprom_read(sc, RT2860_EEPROM_CONFIG);
465 464 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
466 465 "EEPROM CFG 0x%04x\n", val);
467 466 if ((val & 0xff) != 0xff)
468 467 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */;
469 468
470 469 if (sc->sc_flags & RT2860_ADVANCED_PS) {
471 470 /* read PCIe power save level */
472 471 val = rt2860_eeprom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
473 472 if ((val & 0xff) != 0xff) {
474 473 sc->pslevel = val & 0x3;
475 474 val = rt2860_eeprom_read(sc, RT2860_EEPROM_REV);
476 475 if (val >> 8 != 0x92 || !(val & 0x80))
477 476 sc->pslevel = MIN(sc->pslevel, 1);
478 477 RWN_DEBUG(RT2860_DBG_EEPROM,
479 478 "rwn: rt2860_read_eeprom(): "
480 479 "EEPROM PCIe PS Level=%d\n",
481 480 sc->pslevel);
482 481 }
483 482 }
484 483 /* read power settings for 2GHz channels */
485 484 for (i = 0; i < 14; i += 2) {
486 485 val = rt2860_eeprom_read(sc,
487 486 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
488 487 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
489 488 sc->txpow1[i + 1] = (int8_t)(val >> 8);
490 489
491 490 val = rt2860_eeprom_read(sc,
492 491 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
493 492 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
494 493 sc->txpow2[i + 1] = (int8_t)(val >> 8);
495 494 }
496 495 /* fix broken Tx power entries */
497 496 for (i = 0; i < 14; i++) {
498 497 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31)
499 498 sc->txpow1[i] = 5;
500 499 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31)
501 500 sc->txpow2[i] = 5;
502 501 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
503 502 "chan %d: power1=%d, power2=%d\n",
504 503 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]);
505 504 }
506 505 /* read power settings for 5GHz channels */
507 506 for (i = 0; i < 36; i += 2) {
508 507 val = rt2860_eeprom_read(sc,
509 508 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
510 509 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
511 510 sc->txpow1[i + 15] = (int8_t)(val >> 8);
512 511
513 512 val = rt2860_eeprom_read(sc,
514 513 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
515 514 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
516 515 sc->txpow2[i + 15] = (int8_t)(val >> 8);
517 516 }
518 517 /* fix broken Tx power entries */
519 518 for (i = 0; i < 36; i++) {
520 519 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
521 520 sc->txpow1[14 + i] = 5;
522 521 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
523 522 sc->txpow2[14 + i] = 5;
524 523 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
525 524 "chan %d: power1=%d, power2=%d\n",
526 525 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
527 526 sc->txpow2[14 + i]);
528 527 }
529 528
530 529 /* read Tx power compensation for each Tx rate */
531 530 val = rt2860_eeprom_read(sc, RT2860_EEPROM_DELTAPWR);
532 531 delta_2ghz = delta_5ghz = 0;
533 532 if ((val & 0xff) != 0xff && (val & 0x80)) {
534 533 delta_2ghz = val & 0xf;
535 534 if (!(val & 0x40)) /* negative number */
536 535 delta_2ghz = -delta_2ghz;
537 536 }
538 537 val >>= 8;
539 538 if ((val & 0xff) != 0xff && (val & 0x80)) {
540 539 delta_5ghz = val & 0xf;
541 540 if (!(val & 0x40)) /* negative number */
542 541 delta_5ghz = -delta_5ghz;
543 542 }
544 543 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
545 544 "power compensation=%d (2GHz), %d (5GHz) \n",
546 545 delta_2ghz, delta_5ghz);
547 546
548 547 for (ridx = 0; ridx < 5; ridx++) {
549 548 uint32_t reg;
550 549
551 550 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx);
552 551 reg = (uint32_t)val << 16;
553 552 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx + 1);
554 553 reg |= val;
555 554
556 555 sc->txpow20mhz[ridx] = reg;
557 556 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
558 557 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
559 558
560 559 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
561 560 "ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
562 561 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
563 562 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]);
564 563 }
565 564
566 565 /* read factory-calibrated samples for temperature compensation */
567 566 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
568 567 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
569 568 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
570 569 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
571 570 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
572 571 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
573 572 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
574 573 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
575 574 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
576 575 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
577 576 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
578 577 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
579 578 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
580 579 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
581 580 sc->step_2ghz = val >> 8;
582 581 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
583 582 "TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
584 583 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
585 584 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
586 585 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
587 586 sc->tssi_2ghz[8], sc->step_2ghz);
588 587 /* check that ref value is correct, otherwise disable calibration */
589 588 if (sc->tssi_2ghz[4] == 0xff)
590 589 sc->calib_2ghz = 0;
591 590
592 591 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
593 592 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
594 593 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
595 594 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
596 595 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
597 596 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
598 597 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
599 598 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
600 599 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
601 600 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
602 601 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
603 602 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
604 603 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
605 604 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
606 605 sc->step_5ghz = val >> 8;
607 606 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
608 607 "TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
609 608 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
610 609 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
611 610 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
612 611 sc->tssi_5ghz[8], sc->step_5ghz);
613 612 /* check that ref value is correct, otherwise disable calibration */
614 613 if (sc->tssi_5ghz[4] == 0xff)
615 614 sc->calib_5ghz = 0;
616 615
617 616 /* read RSSI offsets and LNA gains from EEPROM */
618 617 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
619 618 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
620 619 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
621 620 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
622 621 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
623 622 sc->lna[2] = val >> 8; /* channel group 2 */
624 623
625 624 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
626 625 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
627 626 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
628 627 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
629 628 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
630 629 sc->lna[3] = val >> 8; /* channel group 3 */
631 630
632 631 val = rt2860_eeprom_read(sc, RT2860_EEPROM_LNA);
633 632 sc->lna[0] = val & 0xff; /* channel group 0 */
634 633 sc->lna[1] = val >> 8; /* channel group 1 */
635 634
636 635 /* fix broken 5GHz LNA entries */
637 636 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
638 637 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
639 638 "invalid LNA for channel group %d\n", 2);
640 639 sc->lna[2] = sc->lna[1];
641 640 }
642 641 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
643 642 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
644 643 "invalid LNA for channel group %d\n", 3);
645 644 sc->lna[3] = sc->lna[1];
646 645 }
647 646
648 647 /* fix broken RSSI offset entries */
649 648 for (ant = 0; ant < 3; ant++) {
650 649 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
651 650 RWN_DEBUG(RT2860_DBG_EEPROM,
652 651 "rwn: rt2860_read_eeprom(): "
653 652 "invalid RSSI%d offset: %d (2GHz)\n",
654 653 ant + 1, sc->rssi_2ghz[ant]);
655 654 sc->rssi_2ghz[ant] = 0;
656 655 }
657 656 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
658 657 RWN_DEBUG(RT2860_DBG_EEPROM,
659 658 "rwn: rt2860_read_eeprom(): "
660 659 "invalid RSSI%d offset: %d (2GHz)\n",
661 660 ant + 1, sc->rssi_5ghz[ant]);
662 661 sc->rssi_5ghz[ant] = 0;
663 662 }
664 663 }
665 664
666 665 return (RT2860_SUCCESS);
667 666 }
668 667
669 668 /*
670 669 * Allocate an DMA memory and a DMA handle for accessing it
671 670 */
672 671 static int
673 672 rt2860_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr,
674 673 size_t memsize, ddi_device_acc_attr_t *attr_p, uint_t alloc_flags,
675 674 uint_t bind_flags, struct dma_area *dma_p)
676 675 {
677 676 int err;
678 677
679 678 /*
680 679 * Allocate handle
681 680 */
682 681 err = ddi_dma_alloc_handle(devinfo, dma_attr,
683 682 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
684 683 if (err != DDI_SUCCESS) {
685 684 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_allo_dma_mem(): "
686 685 "failed to alloc handle\n");
687 686 goto fail1;
688 687 }
689 688
690 689 /*
691 690 * Allocate memory
692 691 */
693 692 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
694 693 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va,
695 694 &dma_p->alength, &dma_p->acc_hdl);
696 695 if (err != DDI_SUCCESS) {
697 696 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
698 697 "failed to alloc mem\n");
699 698 goto fail2;
700 699 }
701 700
702 701 /*
703 702 * Bind the two together
704 703 */
705 704 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
706 705 dma_p->mem_va, dma_p->alength, bind_flags,
707 706 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies);
708 707 if (err != DDI_DMA_MAPPED) {
709 708 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
710 709 "failed to bind handle\n");
711 710 goto fail3;
712 711 }
713 712
714 713 if (dma_p->ncookies != 1) {
715 714 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
716 715 "failed to alloc cookies\n");
717 716 goto fail4;
718 717 }
719 718
720 719 dma_p->nslots = ~0U;
721 720 dma_p->size = ~0U;
722 721 dma_p->token = ~0U;
723 722 dma_p->offset = 0;
724 723 return (DDI_SUCCESS);
725 724
726 725 fail4:
727 726 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
728 727 fail3:
729 728 ddi_dma_mem_free(&dma_p->acc_hdl);
730 729 fail2:
731 730 ddi_dma_free_handle(&dma_p->dma_hdl);
732 731 fail1:
733 732 return (err);
734 733 }
735 734
736 735 static void
737 736 rt2860_free_dma_mem(struct dma_area *dma_p)
738 737 {
739 738 if (dma_p->dma_hdl != NULL) {
740 739 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
741 740 if (dma_p->acc_hdl != NULL) {
742 741 ddi_dma_mem_free(&dma_p->acc_hdl);
743 742 dma_p->acc_hdl = NULL;
744 743 }
745 744 ddi_dma_free_handle(&dma_p->dma_hdl);
746 745 dma_p->ncookies = 0;
747 746 dma_p->dma_hdl = NULL;
748 747 }
749 748 }
750 749
751 750 /*ARGSUSED*/
752 751 static int
753 752 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
754 753 {
755 754 int size, err;
756 755
757 756 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
758 757
759 758 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
760 759 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
761 760 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
762 761 &ring->txdesc_dma);
763 762 if (err != DDI_SUCCESS) {
764 763 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_tx_ring(): "
765 764 "failed to alloc dma mem\n");
766 765 goto fail1;
767 766 }
768 767
769 768 ring->txd = (struct rt2860_txd *)ring->txdesc_dma.mem_va;
770 769 ring->paddr = ring->txdesc_dma.cookie.dmac_address;
771 770
772 771 ring->cur = 0;
773 772 ring->next = 0;
774 773 ring->queued = 0;
775 774
776 775 (void) bzero(ring->txd, size);
777 776 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
778 777 return (DDI_SUCCESS);
779 778 fail1:
780 779 return (err);
781 780 }
782 781
783 782 void
784 783 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
785 784 {
786 785 struct rt2860_tx_data *data;
787 786 int i;
788 787
789 788 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
790 789 ring->txd[i].sdl0 &= ~LE_16(RT2860_TX_DDONE);
791 790
792 791 if ((data = ring->data[i]) == NULL)
793 792 continue; /* nothing mapped in this slot */
794 793
795 794 /* by pass if it's quiesced */
796 795 if (!(sc->sc_flags & RT2860_F_QUIESCE))
797 796 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
798 797
799 798 if (data->ni != NULL) {
800 799 ieee80211_free_node(data->ni);
801 800 data->ni = NULL; /* node already freed */
802 801 }
803 802
804 803 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
805 804 ring->data[i] = NULL;
806 805 }
807 806
808 807 /* by pass if it's quiesced */
809 808 if (!(sc->sc_flags & RT2860_F_QUIESCE))
810 809 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
811 810
812 811 ring->queued = 0;
813 812 ring->cur = ring->next = 0;
814 813 }
815 814
816 815 /*ARGSUSED*/
817 816 static void
818 817 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
819 818 {
820 819 if (ring->txd != NULL) {
821 820 rt2860_free_dma_mem(&ring->txdesc_dma);
822 821 }
823 822 }
824 823
825 824 static int
826 825 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
827 826 {
828 827 struct rt2860_rx_data *data;
829 828 struct rt2860_rxd *rxd;
830 829 int i, err, size, datalen;
831 830
832 831 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
833 832
834 833 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
835 834 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
836 835 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
837 836 &ring->rxdesc_dma);
838 837 if (err != DDI_SUCCESS) {
839 838 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_rx_ring(): "
840 839 "failed to alloc dma mem\n");
841 840 goto fail1;
842 841 }
843 842
844 843 ring->rxd = (struct rt2860_rxd *)ring->rxdesc_dma.mem_va;
845 844 ring->paddr = ring->rxdesc_dma.cookie.dmac_address;
846 845 bzero(ring->rxd, size);
847 846
848 847 /*
849 848 * Pre-allocate Rx buffers and populate Rx ring.
850 849 */
851 850 datalen = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rx_data);
852 851 bzero(ring->data, datalen);
853 852 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
854 853 rxd = &ring->rxd[i];
855 854 data = &ring->data[i];
856 855 /* alloc DMA memory */
857 856 (void) rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr,
858 857 sc->sc_dmabuf_size,
859 858 &rt2860_buf_accattr,
860 859 DDI_DMA_STREAMING,
861 860 DDI_DMA_READ | DDI_DMA_STREAMING,
862 861 &data->rxbuf_dma);
863 862 rxd->sdp0 = LE_32(data->rxbuf_dma.cookie.dmac_address);
864 863 rxd->sdl0 = LE_16(sc->sc_dmabuf_size);
865 864 }
866 865
867 866 ring->cur = 0;
868 867
869 868 RT2860_DMA_SYNC(ring->rxdesc_dma, DDI_DMA_SYNC_FORDEV);
870 869 return (DDI_SUCCESS);
871 870 fail2:
872 871 rt2860_free_dma_mem(&ring->rxdesc_dma);
873 872 fail1:
874 873 return (err);
875 874 }
876 875
877 876 /*ARGSUSED*/
878 877 void
879 878 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
880 879 {
881 880 int i;
882 881
883 882 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
884 883 ring->rxd[i].sdl0 &= ~LE_16(RT2860_RX_DDONE);
885 884
886 885 RT2860_DMA_SYNC(ring->rxdesc_dma, DDI_DMA_SYNC_FORDEV);
887 886
888 887 ring->cur = 0;
889 888 }
890 889
891 890 /*ARGSUSED*/
892 891 static void
893 892 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
894 893 {
895 894 struct rt2860_rx_data *data;
896 895 int i, count;
897 896
898 897 if (ring->rxd != NULL)
899 898 rt2860_free_dma_mem(&ring->rxdesc_dma);
900 899
901 900 count = RT2860_RX_RING_COUNT;
902 901 if (ring->data != NULL) {
903 902 for (i = 0; i < count; i++) {
904 903 data = &ring->data[i];
905 904 rt2860_free_dma_mem(&data->rxbuf_dma);
906 905 }
907 906 }
908 907 }
909 908
910 909 static int
911 910 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
912 911 {
913 912 struct rt2860_tx_data *data;
914 913 int i, err, size;
915 914
916 915 size = RT2860_TX_POOL_COUNT * sizeof (struct rt2860_txwi);
917 916
918 917 /* init data_pool early in case of failure.. */
919 918 SLIST_INIT(&sc->data_pool);
920 919
921 920 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
922 921 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
923 922 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
924 923 &sc->txpool_dma);
925 924 if (err != DDI_SUCCESS) {
926 925 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_tx_pool(): "
927 926 "failed to alloc dma mem\n");
928 927 goto fail1;
929 928 }
930 929
931 930 sc->txwi = (struct rt2860_txwi *)sc->txpool_dma.mem_va;
932 931 (void) bzero(sc->txwi, size);
933 932 RT2860_DMA_SYNC(sc->txpool_dma, DDI_DMA_SYNC_FORDEV);
934 933
935 934 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
936 935 data = &sc->data[i];
937 936
938 937 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr,
939 938 sc->sc_dmabuf_size,
940 939 &rt2860_buf_accattr, DDI_DMA_CONSISTENT,
941 940 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
942 941 &data->txbuf_dma);
943 942 if (err != DDI_SUCCESS) {
944 943 RWN_DEBUG(RT2860_DBG_DMA,
945 944 "rwn: rt2860_alloc_tx_pool(): "
946 945 "failed to alloc dma mem\n");
947 946 goto fail2;
948 947 }
949 948 data->txwi = &sc->txwi[i];
950 949 data->paddr = sc->txpool_dma.cookie.dmac_address +
951 950 i * sizeof (struct rt2860_txwi);
952 951
953 952 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
954 953 }
955 954 return (DDI_SUCCESS);
956 955 fail2:
957 956 rt2860_free_dma_mem(&sc->txpool_dma);
958 957 fail1:
959 958 return (err);
960 959 }
961 960
962 961 static void
963 962 rt2860_free_tx_pool(struct rt2860_softc *sc)
964 963 {
965 964 struct rt2860_tx_data *data;
966 965 int i;
967 966
968 967 if (sc->txwi != NULL) {
969 968 rt2860_free_dma_mem(&sc->txpool_dma);
970 969 }
971 970
972 971 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
973 972 data = &sc->data[i];
974 973 rt2860_free_dma_mem(&data->txbuf_dma);
975 974 }
976 975 }
977 976
978 977 /* quickly determine if a given rate is CCK or OFDM */
979 978 #define RT2860_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
980 979
981 980 #define RT2860_ACK_SIZE 14 /* 10 + 4(FCS) */
982 981 #define RT2860_SIFS_TIME 10
983 982
984 983 static uint8_t
985 984 rt2860_rate2mcs(uint8_t rate)
986 985 {
987 986 switch (rate) {
988 987 /* CCK rates */
989 988 case 2:
990 989 return (0);
991 990 case 4:
992 991 return (1);
993 992 case 11:
994 993 return (2);
995 994 case 22:
996 995 return (3);
997 996 /* OFDM rates */
998 997 case 12:
999 998 return (0);
1000 999 case 18:
1001 1000 return (1);
1002 1001 case 24:
1003 1002 return (2);
1004 1003 case 36:
1005 1004 return (3);
1006 1005 case 48:
1007 1006 return (4);
1008 1007 case 72:
1009 1008 return (5);
1010 1009 case 96:
1011 1010 return (6);
1012 1011 case 108:
1013 1012 return (7);
1014 1013 }
1015 1014
1016 1015 return (0); /* shouldn't get there */
1017 1016 }
1018 1017
1019 1018 /*
1020 1019 * Return the expected ack rate for a frame transmitted at rate `rate'.
1021 1020 */
1022 1021 static int
1023 1022 rt2860_ack_rate(struct ieee80211com *ic, int rate)
1024 1023 {
1025 1024 switch (rate) {
1026 1025 /* CCK rates */
1027 1026 case 2:
1028 1027 return (2);
1029 1028 case 4:
1030 1029 case 11:
1031 1030 case 22:
1032 1031 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
1033 1032
1034 1033 /* OFDM rates */
1035 1034 case 12:
1036 1035 case 18:
1037 1036 return (12);
1038 1037 case 24:
1039 1038 case 36:
1040 1039 return (24);
1041 1040 case 48:
1042 1041 case 72:
1043 1042 case 96:
1044 1043 case 108:
1045 1044 return (48);
1046 1045 }
1047 1046
1048 1047 /* default to 1Mbps */
1049 1048 return (2);
1050 1049 }
1051 1050
1052 1051
1053 1052 /*
1054 1053 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
1055 1054 * The function automatically determines the operating mode depending on the
1056 1055 * given rate. `flags' indicates whether short preamble is in use or not.
1057 1056 */
1058 1057 static uint16_t
1059 1058 rt2860_txtime(int len, int rate, uint32_t flags)
1060 1059 {
1061 1060 uint16_t txtime;
1062 1061
1063 1062 if (RT2860_RATE_IS_OFDM(rate)) {
1064 1063 /* IEEE Std 802.11g-2003, pp. 44 */
1065 1064 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
1066 1065 txtime = 16 + 4 + 4 * txtime + 6;
1067 1066 } else {
1068 1067 /* IEEE Std 802.11b-1999, pp. 28 */
1069 1068 txtime = (16 * len + rate - 1) / rate;
1070 1069 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
1071 1070 txtime += 72 + 24;
1072 1071 else
1073 1072 txtime += 144 + 48;
1074 1073 }
1075 1074 return (txtime);
1076 1075 }
1077 1076
1078 1077 static int
1079 1078 rt2860_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
1080 1079 {
1081 1080 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1082 1081 struct rt2860_tx_ring *ring;
1083 1082 struct rt2860_tx_data *data;
1084 1083 struct rt2860_txd *txd;
1085 1084 struct rt2860_txwi *txwi;
1086 1085 struct ieee80211_frame *wh;
1087 1086 struct ieee80211_node *ni;
1088 1087 int qid, off, rate, err;
1089 1088 int mblen, pktlen;
1090 1089 uint_t hdrlen;
1091 1090 uint8_t mcs, pid, qsel;
1092 1091 uint16_t dur;
1093 1092 mblk_t *m, *m0;
1094 1093
1095 1094 err = DDI_SUCCESS;
1096 1095
1097 1096 mutex_enter(&sc->sc_txlock);
1098 1097 if (RT2860_IS_SUSPEND(sc)) {
1099 1098 err = ENXIO;
1100 1099 goto fail1;
1101 1100 }
1102 1101
1103 1102 if ((type & IEEE80211_FC0_TYPE_MASK) !=
1104 1103 IEEE80211_FC0_TYPE_DATA)
1105 1104 qid = sc->mgtqid;
1106 1105 else
1107 1106 qid = EDCA_AC_BE;
1108 1107 ring = &sc->txq[qid];
1109 1108
1110 1109 if (SLIST_EMPTY(&sc->data_pool) || (ring->queued > 15)) {
1111 1110 sc->sc_need_sched = 1;
1112 1111 sc->sc_tx_nobuf++;
1113 1112 err = ENOMEM;
1114 1113 goto fail1;
1115 1114 }
1116 1115
1117 1116 /* the data pool contains at least one element, pick the first */
1118 1117 data = SLIST_FIRST(&sc->data_pool);
1119 1118
1120 1119 m = allocb(msgdsize(mp) + 32, BPRI_MED);
1121 1120 if (m == NULL) {
1122 1121 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_send():"
1123 1122 "rt2860_mgmt_send: can't alloc mblk.\n");
1124 1123 err = DDI_FAILURE;
1125 1124 goto fail1;
1126 1125 }
1127 1126
1128 1127 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
1129 1128 mblen = MBLKL(m0);
1130 1129 (void) bcopy(m0->b_rptr, m->b_rptr + off, mblen);
1131 1130 off += mblen;
1132 1131 }
1133 1132 m->b_wptr += off;
1134 1133
1135 1134 wh = (struct ieee80211_frame *)m->b_rptr;
1136 1135 ni = ieee80211_find_txnode(ic, wh->i_addr1);
1137 1136 if (ni == NULL) {
1138 1137 err = DDI_FAILURE;
1139 1138 sc->sc_tx_err++;
1140 1139 goto fail2;
1141 1140 }
1142 1141
1143 1142 if ((type & IEEE80211_FC0_TYPE_MASK) ==
1144 1143 IEEE80211_FC0_TYPE_DATA)
1145 1144 (void) ieee80211_encap(ic, m, ni);
1146 1145
1147 1146 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1148 1147 struct ieee80211_key *k;
1149 1148 k = ieee80211_crypto_encap(ic, m);
1150 1149 if (k == NULL) {
1151 1150 sc->sc_tx_err++;
1152 1151 err = DDI_FAILURE;
1153 1152 goto fail3;
1154 1153 }
1155 1154 /* packet header may have moved, reset our local pointer */
1156 1155 wh = (struct ieee80211_frame *)m->b_rptr;
1157 1156 }
1158 1157 pktlen = msgdsize(m);
1159 1158 hdrlen = sizeof (*wh);
1160 1159
1161 1160 /* pickup a rate */
1162 1161 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
1163 1162 ((type & IEEE80211_FC0_TYPE_MASK) !=
1164 1163 IEEE80211_FC0_TYPE_DATA))
1165 1164 rate = ni->in_rates.ir_rates[0];
1166 1165 else {
1167 1166 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE)
1168 1167 rate = ic->ic_fixed_rate;
1169 1168 else
1170 1169 rate = ni->in_rates.ir_rates[ni->in_txrate];
1171 1170 }
1172 1171 rate &= IEEE80211_RATE_VAL;
1173 1172
1174 1173 /* get MCS code from rate */
1175 1174 mcs = rt2860_rate2mcs(rate);
1176 1175
1177 1176 /* setup TX Wireless Information */
1178 1177 txwi = data->txwi;
1179 1178 (void) bzero(txwi, sizeof (struct rt2860_txwi));
1180 1179 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ?
1181 1180 RT2860_AID2WCID(ni->in_associd) : 0xff;
1182 1181 txwi->len = LE_16(pktlen);
1183 1182 if (!RT2860_RATE_IS_OFDM(rate)) {
1184 1183 txwi->phy = LE_16(RT2860_PHY_CCK);
1185 1184 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1186 1185 mcs |= RT2860_PHY_SHPRE;
1187 1186 } else
1188 1187 txwi->phy = LE_16(RT2860_PHY_OFDM);
1189 1188 txwi->phy |= LE_16(mcs);
1190 1189
1191 1190 /*
1192 1191 * We store the MCS code into the driver-private PacketID field.
1193 1192 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1194 1193 * that we know at which initial rate the frame was transmitted.
1195 1194 * We add 1 to the MCS code because setting the PacketID field to
1196 1195 * 0 means that we don't want feedback in TX_STAT_FIFO.
1197 1196 */
1198 1197 pid = (mcs + 1) & 0xf;
1199 1198 txwi->len |= LE_16(pid << RT2860_TX_PID_SHIFT);
1200 1199
1201 1200 /* check if RTS/CTS or CTS-to-self protection is required */
1202 1201 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1203 1202 (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold ||
1204 1203 ((ic->ic_flags &
1205 1204 IEEE80211_F_USEPROT) && RT2860_RATE_IS_OFDM(rate))))
1206 1205 txwi->txop = RT2860_TX_TXOP_HT;
1207 1206 else
1208 1207 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1209 1208
1210 1209 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1211 1210 txwi->xflags |= RT2860_TX_ACK;
1212 1211
1213 1212 dur = rt2860_txtime(RT2860_ACK_SIZE, rt2860_ack_rate(ic, rate),
1214 1213 ic->ic_flags) + sc->sifs;
1215 1214 *(uint16_t *)wh->i_dur = LE_16(dur);
1216 1215 }
1217 1216
1218 1217 /* copy and trim 802.11 header */
1219 1218 bcopy(wh, &txwi->wh, hdrlen);
1220 1219 m->b_rptr += hdrlen;
1221 1220 bcopy(m->b_rptr, data->txbuf_dma.mem_va, pktlen - hdrlen);
1222 1221
1223 1222 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1224 1223
1225 1224 /* first segment is TXWI + 802.11 header */
1226 1225 txd = &ring->txd[ring->cur];
1227 1226 txd->sdp0 = LE_32(data->paddr);
1228 1227 txd->sdl0 = LE_16(16 + hdrlen);
1229 1228 txd->flags = qsel;
1230 1229
1231 1230 /* finalize last segment */
1232 1231 txd->sdp1 = LE_32(data->txbuf_dma.cookie.dmac_address);
1233 1232 txd->sdl1 = LE_16(pktlen - hdrlen | RT2860_TX_LS1);
1234 1233
1235 1234 /* remove from the free pool and link it into the SW Tx slot */
1236 1235 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1237 1236 data->ni = ieee80211_ref_node(ni);
1238 1237 ring->data[ring->cur] = data;
1239 1238
1240 1239 (void) ddi_dma_sync(sc->txpool_dma.dma_hdl,
1241 1240 _PTRDIFF(txwi, sc->txwi),
1242 1241 (hdrlen + 16 + 2),
1243 1242 DDI_DMA_SYNC_FORDEV);
1244 1243 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
1245 1244 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
1246 1245
1247 1246 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_send():"
1248 1247 "sending frame qid=%d wcid=%d rate=%d cur = %x\n",
1249 1248 qid, txwi->wcid, rate, ring->cur);
1250 1249
1251 1250 ring->queued++;
1252 1251 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1253 1252
1254 1253 /* kick Tx */
1255 1254 RT2860_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1256 1255
1257 1256 sc->sc_tx_timer = 5;
1258 1257
1259 1258 ic->ic_stats.is_tx_frags++;
1260 1259 ic->ic_stats.is_tx_bytes += pktlen;
1261 1260
1262 1261 fail3:
1263 1262 ieee80211_free_node(ni);
1264 1263 fail2:
1265 1264 freemsg(m);
1266 1265 fail1:
1267 1266 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA ||
1268 1267 err == DDI_SUCCESS)
1269 1268 freemsg(mp);
1270 1269 mutex_exit(&sc->sc_txlock);
1271 1270 return (err);
1272 1271 }
1273 1272
1274 1273 /*
1275 1274 * This function is called periodically (every 200ms) during scanning to
1276 1275 * switch from one channel to another.
1277 1276 */
1278 1277 static void
1279 1278 rt2860_next_scan(void *arg)
1280 1279 {
1281 1280 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1282 1281 struct ieee80211com *ic = &sc->sc_ic;
1283 1282
1284 1283 if (ic->ic_state == IEEE80211_S_SCAN)
1285 1284 (void) ieee80211_next_scan(ic);
1286 1285 }
1287 1286
1288 1287 static void
1289 1288 rt2860_updateslot(struct rt2860_softc *sc)
1290 1289 {
1291 1290 struct ieee80211com *ic = &sc->sc_ic;
1292 1291 uint32_t tmp;
1293 1292
1294 1293 tmp = RT2860_READ(sc, RT2860_BKOFF_SLOT_CFG);
1295 1294 tmp &= ~0xff;
1296 1295 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1297 1296 RT2860_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
1298 1297 }
1299 1298
1300 1299 static void
1301 1300 rt2860_iter_func(void *arg, struct ieee80211_node *ni)
1302 1301 {
1303 1302 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1304 1303 uint8_t wcid;
1305 1304
1306 1305 wcid = RT2860_AID2WCID(ni->in_associd);
1307 1306 rt2860_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]);
1308 1307 }
1309 1308
1310 1309 static void
1311 1310 rt2860_updatestats(void *arg)
1312 1311 {
1313 1312 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1314 1313 struct ieee80211com *ic = &sc->sc_ic;
1315 1314
1316 1315 if (ic->ic_opmode == IEEE80211_M_STA)
1317 1316 rt2860_iter_func(sc, ic->ic_bss);
1318 1317 else
1319 1318 ieee80211_iterate_nodes(&ic->ic_sta, rt2860_iter_func, arg);
1320 1319
1321 1320 sc->sc_rssadapt_id = timeout(rt2860_updatestats, (void *)sc,
1322 1321 drv_usectohz(500 * 1000));
1323 1322 }
1324 1323
1325 1324 static void
1326 1325 rt2860_enable_mrr(struct rt2860_softc *sc)
1327 1326 {
1328 1327 #define CCK(mcs) (mcs)
1329 1328 #define OFDM(mcs) ((uint32_t)1 << 3 | (mcs))
1330 1329 RT2860_WRITE(sc, RT2860_LG_FBK_CFG0,
1331 1330 OFDM(6) << 28 | /* 54->48 */
1332 1331 OFDM(5) << 24 | /* 48->36 */
1333 1332 OFDM(4) << 20 | /* 36->24 */
1334 1333 OFDM(3) << 16 | /* 24->18 */
1335 1334 OFDM(2) << 12 | /* 18->12 */
1336 1335 OFDM(1) << 8 | /* 12-> 9 */
1337 1336 OFDM(0) << 4 | /* 9-> 6 */
1338 1337 OFDM(0)); /* 6-> 6 */
1339 1338
1340 1339 RT2860_WRITE(sc, RT2860_LG_FBK_CFG1,
1341 1340 CCK(2) << 12 | /* 11->5.5 */
1342 1341 CCK(1) << 8 | /* 5.5-> 2 */
1343 1342 CCK(0) << 4 | /* 2-> 1 */
1344 1343 CCK(0)); /* 1-> 1 */
1345 1344 #undef OFDM
1346 1345 #undef CCK
1347 1346 }
1348 1347
1349 1348 static void
1350 1349 rt2860_set_txpreamble(struct rt2860_softc *sc)
1351 1350 {
1352 1351 uint32_t tmp;
1353 1352
1354 1353 tmp = RT2860_READ(sc, RT2860_AUTO_RSP_CFG);
1355 1354 tmp &= ~RT2860_CCK_SHORT_EN;
1356 1355 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1357 1356 tmp |= RT2860_CCK_SHORT_EN;
1358 1357 RT2860_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
1359 1358 }
1360 1359
1361 1360 static void
1362 1361 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
1363 1362 {
1364 1363 RT2860_WRITE(sc, RT2860_MAC_BSSID_DW0,
1365 1364 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
1366 1365 RT2860_WRITE(sc, RT2860_MAC_BSSID_DW1,
1367 1366 bssid[4] | bssid[5] << 8);
1368 1367 }
1369 1368
1370 1369 static void
1371 1370 rt2860_set_basicrates(struct rt2860_softc *sc)
1372 1371 {
1373 1372 struct ieee80211com *ic = &sc->sc_ic;
1374 1373
1375 1374 /* set basic rates mask */
1376 1375 if (ic->ic_curmode == IEEE80211_MODE_11B)
1377 1376 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003);
1378 1377 else if (ic->ic_curmode == IEEE80211_MODE_11A)
1379 1378 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150);
1380 1379 else /* 11g */
1381 1380 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f);
1382 1381 }
1383 1382
1384 1383 static void
1385 1384 rt2860_amrr_node_init(const struct rt2860_amrr *amrr,
1386 1385 struct rt2860_amrr_node *amn)
1387 1386 {
1388 1387 amn->amn_success = 0;
1389 1388 amn->amn_recovery = 0;
1390 1389 amn->amn_txcnt = amn->amn_retrycnt = 0;
1391 1390 amn->amn_success_threshold = amrr->amrr_min_success_threshold;
1392 1391 }
1393 1392
1394 1393 static void
1395 1394 rt2860_amrr_choose(struct rt2860_amrr *amrr, struct ieee80211_node *ni,
1396 1395 struct rt2860_amrr_node *amn)
1397 1396 {
1398 1397 #define RV(rate) ((rate) & IEEE80211_RATE_VAL)
1399 1398 #define is_success(amn) \
1400 1399 ((amn)->amn_retrycnt < (amn)->amn_txcnt / 10)
1401 1400 #define is_failure(amn) \
1402 1401 ((amn)->amn_retrycnt > (amn)->amn_txcnt / 3)
1403 1402 #define is_enough(amn) \
1404 1403 ((amn)->amn_txcnt > 10)
1405 1404 #define is_min_rate(ni) \
1406 1405 ((ni)->in_txrate == 0)
1407 1406 #define is_max_rate(ni) \
1408 1407 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1)
1409 1408 #define increase_rate(ni) \
1410 1409 ((ni)->in_txrate++)
1411 1410 #define decrease_rate(ni) \
1412 1411 ((ni)->in_txrate--)
1413 1412 #define reset_cnt(amn) \
1414 1413 { (amn)->amn_txcnt = (amn)->amn_retrycnt = 0; }
1415 1414
1416 1415 int need_change = 0;
1417 1416
1418 1417 if (is_success(amn) && is_enough(amn)) {
1419 1418 amn->amn_success++;
1420 1419 if (amn->amn_success >= amn->amn_success_threshold &&
1421 1420 !is_max_rate(ni)) {
1422 1421 amn->amn_recovery = 1;
1423 1422 amn->amn_success = 0;
1424 1423 increase_rate(ni);
1425 1424 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_amrr_choose(): "
1426 1425 "increase rate = %d, #tx = %d, #retries = %d\n",
1427 1426 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1428 1427 amn->amn_txcnt, amn->amn_retrycnt);
1429 1428 need_change = 1;
1430 1429 } else {
1431 1430 amn->amn_recovery = 0;
1432 1431 }
1433 1432 } else if (is_failure(amn)) {
1434 1433 amn->amn_success = 0;
1435 1434 if (!is_min_rate(ni)) {
1436 1435 if (amn->amn_recovery) {
1437 1436 amn->amn_success_threshold *= 2;
1438 1437 if (amn->amn_success_threshold >
1439 1438 amrr->amrr_max_success_threshold)
1440 1439 amn->amn_success_threshold =
1441 1440 amrr->amrr_max_success_threshold;
1442 1441 } else {
1443 1442 amn->amn_success_threshold =
1444 1443 amrr->amrr_min_success_threshold;
1445 1444 }
1446 1445 decrease_rate(ni);
1447 1446 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_amrr_choose(): "
1448 1447 "decrease rate = %d, #tx = %d, #retries = %d\n",
1449 1448 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1450 1449 amn->amn_txcnt, amn->amn_retrycnt);
1451 1450 need_change = 1;
1452 1451 }
1453 1452 amn->amn_recovery = 0;
1454 1453 }
1455 1454
1456 1455 if (is_enough(amn) || need_change)
1457 1456 reset_cnt(amn);
1458 1457 #undef RV
1459 1458 }
1460 1459
1461 1460 static void
1462 1461 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *in, int isnew)
1463 1462 {
1464 1463 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1465 1464 uint32_t off;
1466 1465 uint8_t *fptr, wcid = 0;
1467 1466 int i;
1468 1467
1469 1468 if (isnew && in->in_associd != 0) {
1470 1469 /* only interested in true associations */
1471 1470 wcid = RT2860_AID2WCID(in->in_associd);
1472 1471
1473 1472 /* init WCID table entry */
1474 1473 off = RT2860_WCID_ENTRY(wcid);
1475 1474 fptr = in->in_macaddr;
1476 1475 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
1477 1476 rt2860_mem_write1(sc, off++, *fptr++);
1478 1477 }
1479 1478 rt2860_amrr_node_init(&sc->amrr, &sc->amn[wcid]);
1480 1479
1481 1480 /* set rate to some reasonable initial value */
1482 1481 i = in->in_rates.ir_nrates - 1;
1483 1482 for (; i > 0 && (in->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72; )
1484 1483 i--;
1485 1484 in->in_txrate = i;
1486 1485
1487 1486 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newassoc(): "
1488 1487 "new assoc isnew=%d WCID=%d, initial rate=%d\n",
1489 1488 isnew, wcid,
1490 1489 in->in_rates.ir_rates[i] & IEEE80211_RATE_VAL);
1491 1490 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newassoc(): "
1492 1491 "addr=%x:%x:%x:%x:%x:%x\n",
1493 1492 in->in_macaddr[0], in->in_macaddr[1], in->in_macaddr[2],
1494 1493 in->in_macaddr[3], in->in_macaddr[4], in->in_macaddr[5]);
1495 1494 }
1496 1495
1497 1496 void
1498 1497 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
1499 1498 {
1500 1499 struct ieee80211com *ic = &sc->sc_ic;
1501 1500 uint32_t tmp;
1502 1501
1503 1502 tmp = RT2860_READ(sc, RT2860_BCN_TIME_CFG);
1504 1503
1505 1504 tmp &= ~0x1fffff;
1506 1505 tmp |= ic->ic_bss->in_intval * 16;
1507 1506 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
1508 1507 if (ic->ic_opmode == IEEE80211_M_STA) {
1509 1508 /*
1510 1509 * Local TSF is always updated with remote TSF on beacon
1511 1510 * reception.
1512 1511 */
1513 1512 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
1514 1513 }
1515 1514
1516 1515 RT2860_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
1517 1516 }
1518 1517
1519 1518 static int
1520 1519 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1521 1520 {
1522 1521 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1523 1522 enum ieee80211_state ostate;
1524 1523 int err;
1525 1524 uint32_t tmp;
1526 1525
1527 1526 ostate = ic->ic_state;
1528 1527 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newstate(): "
1529 1528 "%x -> %x!\n", ostate, nstate);
1530 1529
1531 1530 RT2860_GLOCK(sc);
1532 1531 if (sc->sc_scan_id != 0) {
1533 1532 (void) untimeout(sc->sc_scan_id);
1534 1533 sc->sc_scan_id = 0;
1535 1534 }
1536 1535 if (sc->sc_rssadapt_id != 0) {
1537 1536 (void) untimeout(sc->sc_rssadapt_id);
1538 1537 sc->sc_rssadapt_id = 0;
1539 1538 }
1540 1539 if (ostate == IEEE80211_S_RUN) {
1541 1540 /* turn link LED off */
1542 1541 rt2860_set_leds(sc, RT2860_LED_RADIO);
1543 1542 }
1544 1543
1545 1544 switch (nstate) {
1546 1545 case IEEE80211_S_INIT:
1547 1546 if (ostate == IEEE80211_S_RUN) {
1548 1547 /* abort TSF synchronization */
1549 1548 tmp = RT2860_READ(sc, RT2860_BCN_TIME_CFG);
1550 1549 RT2860_WRITE(sc, RT2860_BCN_TIME_CFG,
1551 1550 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
1552 1551 RT2860_TBTT_TIMER_EN));
1553 1552 }
1554 1553 break;
1555 1554
1556 1555 case IEEE80211_S_SCAN:
1557 1556 rt2860_set_chan(sc, ic->ic_curchan);
1558 1557 sc->sc_scan_id = timeout(rt2860_next_scan, (void *)sc,
1559 1558 drv_usectohz(200000));
1560 1559 break;
1561 1560
1562 1561 case IEEE80211_S_AUTH:
1563 1562 case IEEE80211_S_ASSOC:
1564 1563 rt2860_set_chan(sc, ic->ic_curchan);
1565 1564 break;
1566 1565
1567 1566 case IEEE80211_S_RUN:
1568 1567 rt2860_set_chan(sc, ic->ic_curchan);
1569 1568
1570 1569 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1571 1570 rt2860_updateslot(sc);
1572 1571 rt2860_enable_mrr(sc);
1573 1572 rt2860_set_txpreamble(sc);
1574 1573 rt2860_set_basicrates(sc);
1575 1574 rt2860_set_bssid(sc, ic->ic_bss->in_bssid);
1576 1575 }
1577 1576 if (ic->ic_opmode == IEEE80211_M_STA) {
1578 1577 /* fake a join to init the tx rate */
1579 1578 rt2860_newassoc(ic, ic->ic_bss, 1);
1580 1579 }
1581 1580
1582 1581 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1583 1582 rt2860_enable_tsf_sync(sc);
1584 1583 sc->sc_rssadapt_id = timeout(rt2860_updatestats,
1585 1584 (void *)sc, drv_usectohz(500 * 1000));
1586 1585 }
1587 1586
1588 1587 /* turn link LED on */
1589 1588 rt2860_set_leds(sc, RT2860_LED_RADIO |
1590 1589 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ?
1591 1590 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
1592 1591 break;
1593 1592 }
1594 1593
1595 1594 RT2860_GUNLOCK(sc);
1596 1595
1597 1596 err = sc->sc_newstate(ic, nstate, arg);
1598 1597
1599 1598 return (err);
1600 1599 }
1601 1600
1602 1601 /*
1603 1602 * Return the Rx chain with the highest RSSI for a given frame.
1604 1603 */
1605 1604 static uint8_t
1606 1605 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1607 1606 {
1608 1607 uint8_t rxchain = 0;
1609 1608
1610 1609 if (sc->nrxchains > 1)
1611 1610 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1612 1611 rxchain = 1;
1613 1612 if (sc->nrxchains > 2)
1614 1613 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1615 1614 rxchain = 2;
1616 1615
1617 1616 return (rxchain);
1618 1617 }
1619 1618
1620 1619 static void
1621 1620 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1622 1621 {
1623 1622 struct rt2860_amrr_node *amn;
1624 1623 uint32_t stat;
1625 1624 uint8_t wcid, mcs, pid;
1626 1625
1627 1626 /* drain Tx status FIFO (maxsize = 16) */
1628 1627 while ((stat = RT2860_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1629 1628 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_drain_stats_fifo(): "
1630 1629 "tx stat 0x%08\n", stat);
1631 1630
1632 1631 wcid = (stat >> 8) & 0xff;
1633 1632
1634 1633 /* if no ACK was requested, no feedback is available */
1635 1634 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff)
1636 1635 continue;
1637 1636 /* update per-STA AMRR stats */
1638 1637 amn = &sc->amn[wcid];
1639 1638 amn->amn_txcnt++;
1640 1639 if (stat & RT2860_TXQ_OK) {
1641 1640 /*
1642 1641 * Check if there were retries, ie if the Tx success
1643 1642 * rate is different from the requested rate. Note
1644 1643 * that it works only because we do not allow rate
1645 1644 * fallback from OFDM to CCK.
1646 1645 */
1647 1646 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1648 1647 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1649 1648 if (mcs + 1 != pid)
1650 1649 amn->amn_retrycnt++;
1651 1650 } else
1652 1651 amn->amn_retrycnt++;
1653 1652 }
1654 1653 }
1655 1654
1656 1655 /*ARGSUSED*/
1657 1656 static void
1658 1657 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1659 1658 {
1660 1659 struct rt2860_tx_ring *ring = &sc->txq[qid];
1661 1660 struct ieee80211com *ic = &sc->sc_ic;
1662 1661 uint32_t hw;
1663 1662
1664 1663 rt2860_drain_stats_fifo(sc);
1665 1664
1666 1665 mutex_enter(&sc->sc_txlock);
1667 1666 hw = RT2860_READ(sc, RT2860_TX_DTX_IDX(qid));
1668 1667 RWN_DEBUG(RT2860_DBG_TX, "rwn: rwn_tx_intr():"
1669 1668 "hw = %x, ring->next = %x, queued = %d\n",
1670 1669 hw, ring->next, ring->queued);
1671 1670 while (ring->next != hw) {
1672 1671 struct rt2860_txd *txd = &ring->txd[ring->next];
1673 1672 struct rt2860_tx_data *data = ring->data[ring->next];
1674 1673
1675 1674 if (data != NULL) {
1676 1675 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
1677 1676 if (data->ni != NULL) {
1678 1677 ieee80211_free_node(data->ni);
1679 1678 data->ni = NULL;
1680 1679 }
1681 1680 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1682 1681 ring->data[ring->next] = NULL;
1683 1682 }
1684 1683
1685 1684 txd->sdl0 &= ~LE_16(RT2860_TX_DDONE);
1686 1685
1687 1686 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
1688 1687 ring->next * sizeof (struct rt2860_txd),
1689 1688 sizeof (struct rt2860_txd),
1690 1689 DDI_DMA_SYNC_FORDEV);
1691 1690
1692 1691 ring->queued--;
1693 1692 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1694 1693
1695 1694 if (sc->sc_need_sched &&
1696 1695 (ring->queued < RT2860_TX_RING_COUNT)) {
1697 1696 sc->sc_need_sched = 0;
1698 1697 mac_tx_update(ic->ic_mach);
1699 1698 }
1700 1699 }
1701 1700 sc->sc_tx_timer = 0;
1702 1701 mutex_exit(&sc->sc_txlock);
1703 1702 }
1704 1703
1705 1704 static void
1706 1705 rt2860_rx_intr(struct rt2860_softc *sc)
1707 1706 {
1708 1707 struct ieee80211com *ic = &sc->sc_ic;
1709 1708 struct ieee80211_node *ni;
1710 1709 struct ieee80211_frame *wh;
1711 1710 int pktlen;
1712 1711 uint8_t ant, rssi, *rxbuf;
1713 1712 mblk_t *mp0;
1714 1713
1715 1714 mutex_enter(&sc->sc_rxlock);
1716 1715 for (;;) {
1717 1716 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1718 1717 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1719 1718 struct rt2860_rxwi *rxwi;
1720 1719
1721 1720 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl,
1722 1721 sc->rxq.cur * sizeof (struct rt2860_rxd),
1723 1722 sizeof (struct rt2860_rxd),
1724 1723 DDI_DMA_SYNC_FORKERNEL);
1725 1724
1726 1725 if (!(rxd->sdl0 & LE_16(RT2860_RX_DDONE))) {
1727 1726 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1728 1727 "rx done!\n");
1729 1728 break;
1730 1729 }
1731 1730
1732 1731 if (rxd->flags &
1733 1732 LE_32(RT2860_RX_CRCERR | RT2860_RX_ICVERR)) {
1734 1733 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1735 1734 "rx crc error & rx icv error!\n");
1736 1735 sc->sc_rx_err++;
1737 1736 goto skip;
1738 1737 }
1739 1738
1740 1739 if (rxd->flags & LE_32(RT2860_RX_MICERR)) {
1741 1740 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1742 1741 "rx mic error!\n");
1743 1742 sc->sc_rx_err++;
1744 1743 goto skip;
1745 1744 }
1746 1745
1747 1746 (void) ddi_dma_sync(data->rxbuf_dma.dma_hdl,
1748 1747 data->rxbuf_dma.offset,
1749 1748 data->rxbuf_dma.alength,
1750 1749 DDI_DMA_SYNC_FORCPU);
1751 1750
1752 1751 rxbuf = (uint8_t *)data->rxbuf_dma.mem_va;
1753 1752 rxd->sdp0 = LE_32(data->rxbuf_dma.cookie.dmac_address);
1754 1753 rxwi = (struct rt2860_rxwi *)rxbuf;
1755 1754 rxbuf = (uint8_t *)(rxwi + 1);
1756 1755 pktlen = LE_16(rxwi->len) & 0xfff;
1757 1756
1758 1757 mp0 = allocb(sc->sc_dmabuf_size, BPRI_MED);
1759 1758 if (mp0 == NULL) {
1760 1759 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr():"
1761 1760 "alloc mblk error\n");
1762 1761 sc->sc_rx_nobuf++;
1763 1762 goto skip;
1764 1763 }
1765 1764 bcopy(rxbuf, mp0->b_rptr, pktlen);
1766 1765 mp0->b_wptr += pktlen;
1767 1766
1768 1767 wh = (struct ieee80211_frame *)mp0->b_rptr;
1769 1768
1770 1769 /* HW may insert 2 padding bytes after 802.11 header */
1771 1770 if (rxd->flags & LE_32(RT2860_RX_L2PAD)) {
1772 1771 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr():"
1773 1772 "2 padding bytes after 80211 header!\n");
1774 1773 }
1775 1774
1776 1775 ant = rt2860_maxrssi_chain(sc, rxwi);
1777 1776 rssi = RT2860_RSSI_OFFSET - rxwi->rssi[ant];
1778 1777 /* grab a reference to the source node */
1779 1778 ni = ieee80211_find_rxnode(ic, wh);
1780 1779
1781 1780 (void) ieee80211_input(ic, mp0, ni, rssi, 0);
1782 1781
1783 1782 /* node is no longer needed */
1784 1783 ieee80211_free_node(ni);
1785 1784 skip:
1786 1785 rxd->sdl0 &= ~LE_16(RT2860_RX_DDONE);
1787 1786
1788 1787 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl,
1789 1788 sc->rxq.cur * sizeof (struct rt2860_rxd),
1790 1789 sizeof (struct rt2860_rxd),
1791 1790 DDI_DMA_SYNC_FORDEV);
1792 1791
1793 1792 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1794 1793 }
1795 1794 mutex_exit(&sc->sc_rxlock);
1796 1795
1797 1796 /* tell HW what we have processed */
1798 1797 RT2860_WRITE(sc, RT2860_RX_CALC_IDX,
1799 1798 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1800 1799 }
1801 1800
1802 1801 static uint_t
1803 1802 rt2860_softintr(caddr_t data)
1804 1803 {
1805 1804 struct rt2860_softc *sc = (struct rt2860_softc *)data;
1806 1805
1807 1806 /*
1808 1807 * Check if the soft interrupt is triggered by another
1809 1808 * driver at the same level.
1810 1809 */
1811 1810 RT2860_GLOCK(sc);
1812 1811 if (sc->sc_rx_pend) {
1813 1812 sc->sc_rx_pend = 0;
1814 1813 RT2860_GUNLOCK(sc);
1815 1814 rt2860_rx_intr(sc);
1816 1815 return (DDI_INTR_CLAIMED);
1817 1816 }
1818 1817 RT2860_GUNLOCK(sc);
1819 1818
1820 1819 return (DDI_INTR_UNCLAIMED);
1821 1820 }
1822 1821
1823 1822 static uint_t
1824 1823 rt2860_intr(caddr_t arg)
1825 1824 {
1826 1825 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1827 1826 uint32_t r;
1828 1827
1829 1828 RT2860_GLOCK(sc);
1830 1829
1831 1830 if ((!RT2860_IS_RUNNING(sc)) || RT2860_IS_SUSPEND(sc)) {
1832 1831 /*
1833 1832 * The hardware is not ready/present, don't touch anything.
1834 1833 * Note this can happen early on if the IRQ is shared.
1835 1834 */
1836 1835 RT2860_GUNLOCK(sc);
1837 1836 return (DDI_INTR_UNCLAIMED);
1838 1837 }
1839 1838
1840 1839 r = RT2860_READ(sc, RT2860_INT_STATUS);
1841 1840 if (r == 0xffffffff) {
1842 1841 RT2860_GUNLOCK(sc);
1843 1842 return (DDI_INTR_UNCLAIMED);
1844 1843 }
1845 1844 if (r == 0) {
1846 1845 RT2860_GUNLOCK(sc);
1847 1846 return (DDI_INTR_UNCLAIMED);
1848 1847 }
1849 1848
1850 1849 /* acknowledge interrupts */
1851 1850 RT2860_WRITE(sc, RT2860_INT_STATUS, r);
1852 1851
1853 1852 if (r & RT2860_TX_COHERENT)
1854 1853 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1855 1854 "RT2860_TX_COHERENT\n");
1856 1855
1857 1856 if (r & RT2860_RX_COHERENT)
1858 1857 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1859 1858 "RT2860_RX_COHERENT\n");
1860 1859
1861 1860 if (r & RT2860_MAC_INT_2) {
1862 1861 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1863 1862 "RT2860_MAC_INT_2\n");
1864 1863 rt2860_drain_stats_fifo(sc);
1865 1864 }
1866 1865
1867 1866 if (r & RT2860_TX_DONE_INT5) {
1868 1867 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1869 1868 "RT2860_TX_DONE_INT5\n");
1870 1869 rt2860_tx_intr(sc, 5);
1871 1870 }
1872 1871
1873 1872 if (r & RT2860_RX_DONE_INT) {
1874 1873 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1875 1874 "RT2860_RX_INT\n");
1876 1875 sc->sc_rx_pend = 1;
1877 1876 ddi_trigger_softintr(sc->sc_softintr_hdl);
1878 1877 }
1879 1878
1880 1879 if (r & RT2860_TX_DONE_INT4) {
1881 1880 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1882 1881 "RT2860_TX_DONE_INT4\n");
1883 1882 rt2860_tx_intr(sc, 4);
1884 1883 }
1885 1884
1886 1885 if (r & RT2860_TX_DONE_INT3) {
1887 1886 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1888 1887 "RT2860_TX_DONE_INT3\n");
1889 1888 rt2860_tx_intr(sc, 3);
1890 1889 }
1891 1890
1892 1891 if (r & RT2860_TX_DONE_INT2) {
1893 1892 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1894 1893 "RT2860_TX_DONE_INT2\n");
1895 1894 rt2860_tx_intr(sc, 2);
1896 1895 }
1897 1896
1898 1897 if (r & RT2860_TX_DONE_INT1) {
1899 1898 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1900 1899 "RT2860_TX_DONE_INT1\n");
1901 1900 rt2860_tx_intr(sc, 1);
1902 1901 }
1903 1902
1904 1903 if (r & RT2860_TX_DONE_INT0) {
1905 1904 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1906 1905 "RT2860_TX_DONE_INT0\n");
1907 1906 rt2860_tx_intr(sc, 0);
1908 1907 }
1909 1908
1910 1909 if (r & RT2860_MAC_INT_0) {
1911 1910 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1912 1911 "RT2860_MAC_INT_0\n");
1913 1912 struct ieee80211com *ic = &sc->sc_ic;
1914 1913 /* check if protection mode has changed */
1915 1914 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1916 1915 rt2860_updateprot(ic);
1917 1916 sc->sc_ic_flags = ic->ic_flags;
1918 1917 }
1919 1918 }
1920 1919
1921 1920 if (r & RT2860_MAC_INT_3)
1922 1921 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1923 1922 "RT2860_MAC_INT_3\n");
1924 1923
1925 1924 RT2860_GUNLOCK(sc);
1926 1925
1927 1926 return (DDI_INTR_CLAIMED);
1928 1927 }
1929 1928
1930 1929 static void
1931 1930 rt2860_set_region_4(struct rt2860_softc *sc,
1932 1931 uint32_t addr, uint32_t data, int size)
1933 1932 {
1934 1933 for (; size > 0; size--, data++, addr += 4)
1935 1934 ddi_put32((sc)->sc_io_handle,
1936 1935 (uint32_t *)((uintptr_t)(sc)->sc_io_base + addr), data);
1937 1936 }
1938 1937
1939 1938 static int
1940 1939 rt2860_load_microcode(struct rt2860_softc *sc)
1941 1940 {
1942 1941 int ntries;
1943 1942 size_t size;
1944 1943 uint8_t *ucode, *fptr;
1945 1944 uint32_t off, i;
1946 1945
1947 1946 ucode = rt2860_fw_bin;
1948 1947 size = sizeof (rt2860_fw_bin);
1949 1948 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_load_microcode(): "
1950 1949 "The size of ucode is: %x\n", size);
1951 1950
1952 1951 /* set "host program ram write selection" bit */
1953 1952 RT2860_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
1954 1953 /* write microcode image */
1955 1954 fptr = ucode;
1956 1955 off = RT2860_FW_BASE;
1957 1956 for (i = 0; i < size; i++) {
1958 1957 rt2860_mem_write1(sc, off++, *fptr++);
1959 1958 }
1960 1959 /* kick microcontroller unit */
1961 1960 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0);
1962 1961 RT2860_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
1963 1962
1964 1963 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
1965 1964 RT2860_WRITE(sc, RT2860_H2M_MAILBOX, 0);
1966 1965
1967 1966 /* wait until microcontroller is ready */
1968 1967 for (ntries = 0; ntries < 1000; ntries++) {
1969 1968 if (RT2860_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
1970 1969 break;
1971 1970 DELAY(1000);
1972 1971 }
1973 1972 if (ntries == 1000) {
1974 1973 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_load_microcode(): "
1975 1974 "timeout waiting for MCU to initialie\n");
1976 1975 return (ETIMEDOUT);
1977 1976 }
1978 1977
1979 1978 return (0);
1980 1979 }
1981 1980
1982 1981 static void
1983 1982 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
1984 1983 {
1985 1984 RT2860_WRITE(sc, RT2860_MAC_ADDR_DW0,
1986 1985 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
1987 1986 RT2860_WRITE(sc, RT2860_MAC_ADDR_DW1,
1988 1987 addr[4] | addr[5] << 8);
1989 1988 }
1990 1989
1991 1990 /*
1992 1991 * Send a command to the 8051 microcontroller unit.
1993 1992 */
1994 1993 static int
1995 1994 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg)
1996 1995 {
1997 1996 int ntries;
1998 1997
1999 1998 for (ntries = 0; ntries < 100; ntries++) {
2000 1999 if (!(RT2860_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2001 2000 break;
2002 2001 DELAY(2);
2003 2002 }
2004 2003 if (ntries == 100)
2005 2004 return (EIO);
2006 2005
2007 2006 RT2860_WRITE(sc, RT2860_H2M_MAILBOX,
2008 2007 RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg);
2009 2008 RT2860_WRITE(sc, RT2860_HOST_CMD, cmd);
2010 2009
2011 2010 return (RT2860_SUCCESS);
2012 2011 }
2013 2012
2014 2013 /*
2015 2014 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
2016 2015 * We access the BBP through the 8051 microcontroller unit which means that
2017 2016 * the microcode must be loaded first.
2018 2017 */
2019 2018 static uint8_t
2020 2019 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
2021 2020 {
2022 2021 uint32_t val;
2023 2022 int ntries;
2024 2023
2025 2024 for (ntries = 0; ntries < 100; ntries++) {
2026 2025 if (!(RT2860_READ(sc,
2027 2026 RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2028 2027 break;
2029 2028 DELAY(1);
2030 2029 }
2031 2030 if (ntries == 100) {
2032 2031 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_read():"
2033 2032 "could not read from BBP through MCU\n");
2034 2033 return (0);
2035 2034 }
2036 2035
2037 2036 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2038 2037 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
2039 2038
2040 2039 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0);
2041 2040 DELAY(1000);
2042 2041
2043 2042 for (ntries = 0; ntries < 100; ntries++) {
2044 2043 val = RT2860_READ(sc, RT2860_H2M_BBPAGENT);
2045 2044 if (!(val & RT2860_BBP_CSR_KICK))
2046 2045 return (val & 0xff);
2047 2046 DELAY(1);
2048 2047 }
2049 2048 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_read():"
2050 2049 "could not read from BBP through MCU\n");
2051 2050
2052 2051 return (0);
2053 2052 }
2054 2053
2055 2054 static void
2056 2055 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2057 2056 {
2058 2057 int ntries;
2059 2058
2060 2059 for (ntries = 0; ntries < 100; ntries++) {
2061 2060 if (!(RT2860_READ(sc,
2062 2061 RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2063 2062 break;
2064 2063 DELAY(1);
2065 2064 }
2066 2065 if (ntries == 100) {
2067 2066 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_write():"
2068 2067 "could not write to BBP through MCU\n");
2069 2068 return;
2070 2069 }
2071 2070
2072 2071 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2073 2072 RT2860_BBP_CSR_KICK | reg << 8 | val);
2074 2073
2075 2074 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0);
2076 2075 DELAY(1000);
2077 2076 }
2078 2077
2079 2078 static int
2080 2079 rt2860_bbp_init(struct rt2860_softc *sc)
2081 2080 {
2082 2081 int i, ntries;
2083 2082
2084 2083 /* wait for BBP to wake up */
2085 2084 for (ntries = 0; ntries < 20; ntries++) {
2086 2085 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
2087 2086 if (bbp0 != 0 && bbp0 != 0xff)
2088 2087 break;
2089 2088 }
2090 2089 if (ntries == 20) {
2091 2090 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_bbp_init():"
2092 2091 "timeout waiting for BBP to wake up\n");
2093 2092 return (ETIMEDOUT);
2094 2093 }
2095 2094
2096 2095 /* initialize BBP registers to default values */
2097 2096 for (i = 0; i < 12; i++) {
2098 2097 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
2099 2098 rt2860_def_bbp[i].val);
2100 2099 }
2101 2100
2102 2101 /* fix BBP69 and BBP73 for RT2860C */
2103 2102 if (sc->mac_rev == 0x28600100) {
2104 2103 rt2860_mcu_bbp_write(sc, 69, 0x16);
2105 2104 rt2860_mcu_bbp_write(sc, 73, 0x12);
2106 2105 }
2107 2106
2108 2107 return (0);
2109 2108 }
2110 2109
2111 2110 static void
2112 2111 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
2113 2112 {
2114 2113 uint32_t tmp;
2115 2114 int ntries;
2116 2115
2117 2116 for (ntries = 0; ntries < 100; ntries++) {
2118 2117 if (!(RT2860_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
2119 2118 break;
2120 2119 DELAY(1);
2121 2120 }
2122 2121 if (ntries == 100) {
2123 2122 RWN_DEBUG(RT2860_DBG_FW, "rwn: rwn_init()"
2124 2123 "could not write to RF\n");
2125 2124 return;
2126 2125 }
2127 2126
2128 2127 /* RF registers are 24-bit on the RT2860 */
2129 2128 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
2130 2129 (val & 0x3fffff) << 2 | (reg & 3);
2131 2130 RT2860_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
2132 2131 }
2133 2132
2134 2133 static void
2135 2134 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2136 2135 {
2137 2136 uint32_t tmp;
2138 2137
2139 2138 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2140 2139 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2141 2140 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2142 2141 rt2860_mcu_bbp_write(sc, 82, (group == 0) ? 0x62 : 0xf2);
2143 2142
2144 2143 tmp = RT2860_READ(sc, RT2860_TX_BAND_CFG);
2145 2144 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2146 2145 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2147 2146 RT2860_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2148 2147
2149 2148 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2150 2149 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN;
2151 2150 if (group == 0) { /* 2GHz */
2152 2151 tmp |= RT2860_PA_PE_G0_EN | RT2860_LNA_PE_G0_EN;
2153 2152 if (sc->ntxchains > 1)
2154 2153 tmp |= RT2860_PA_PE_G1_EN;
2155 2154 if (sc->nrxchains > 1)
2156 2155 tmp |= RT2860_LNA_PE_G1_EN;
2157 2156 } else { /* 5GHz */
2158 2157 tmp |= RT2860_PA_PE_A0_EN | RT2860_LNA_PE_A0_EN;
2159 2158 if (sc->ntxchains > 1)
2160 2159 tmp |= RT2860_PA_PE_A1_EN;
2161 2160 if (sc->nrxchains > 1)
2162 2161 tmp |= RT2860_LNA_PE_A1_EN;
2163 2162 }
2164 2163 RT2860_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2165 2164
2166 2165 rt2860_mcu_bbp_write(sc, 66, 0x2e + sc->lna[group]);
2167 2166 }
2168 2167 static void
2169 2168 rt2860_set_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
2170 2169 {
2171 2170 struct ieee80211com *ic = &sc->sc_ic;
2172 2171 const struct rfprog *rfprog = rt2860_rf2850;
2173 2172 uint_t i, chan, group;
2174 2173 uint8_t txpow1, txpow2;
2175 2174 uint32_t r2, r3, r4;
2176 2175
2177 2176 chan = ieee80211_chan2ieee(ic, c);
2178 2177 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
2179 2178 RWN_DEBUG(RT2860_DBG_FW, "Unkonwn channel!\n");
2180 2179 return;
2181 2180 }
2182 2181
2183 2182 /* find the settings for this channel (we know it exists) */
2184 2183 for (i = 0; rfprog[i].chan != chan; )
2185 2184 i++;
2186 2185
2187 2186 r2 = rfprog[i].r2;
2188 2187 if (sc->ntxchains == 1)
2189 2188 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2190 2189 if (sc->nrxchains == 1)
2191 2190 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2192 2191 else if (sc->nrxchains == 2)
2193 2192 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2194 2193
2195 2194 /* use Tx power values from EEPROM */
2196 2195 txpow1 = sc->txpow1[i];
2197 2196 txpow2 = sc->txpow2[i];
2198 2197 if (IEEE80211_IS_CHAN_5GHZ(c)) {
2199 2198 txpow1 = txpow1 << 1 | 1;
2200 2199 txpow2 = txpow2 << 1 | 1;
2201 2200 }
2202 2201 r3 = rfprog[i].r3 | txpow1 << 7;
2203 2202 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2204 2203
2205 2204 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2206 2205 rt2860_rf_write(sc, RAL_RF2, r2);
2207 2206 rt2860_rf_write(sc, RAL_RF3, r3);
2208 2207 rt2860_rf_write(sc, RAL_RF4, r4);
2209 2208
2210 2209 DELAY(200);
2211 2210
2212 2211 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2213 2212 rt2860_rf_write(sc, RAL_RF2, r2);
2214 2213 rt2860_rf_write(sc, RAL_RF3, r3 | 1);
2215 2214 rt2860_rf_write(sc, RAL_RF4, r4);
2216 2215
2217 2216 DELAY(200);
2218 2217
2219 2218 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2220 2219 rt2860_rf_write(sc, RAL_RF2, r2);
2221 2220 rt2860_rf_write(sc, RAL_RF3, r3);
2222 2221 rt2860_rf_write(sc, RAL_RF4, r4);
2223 2222
2224 2223 /* 802.11a uses a 16 microseconds short interframe space */
2225 2224 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10;
2226 2225
2227 2226 /* determine channel group */
2228 2227 if (chan <= 14)
2229 2228 group = 0;
2230 2229 else if (chan <= 64)
2231 2230 group = 1;
2232 2231 else if (chan <= 128)
2233 2232 group = 2;
2234 2233 else
2235 2234 group = 3;
2236 2235
2237 2236 /* XXX necessary only when group has changed! */
2238 2237 rt2860_select_chan_group(sc, group);
2239 2238
2240 2239 DELAY(1000);
2241 2240 }
2242 2241
2243 2242 static void
2244 2243 rt2860_updateprot(struct ieee80211com *ic)
2245 2244 {
2246 2245 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
2247 2246 uint32_t tmp;
2248 2247
2249 2248 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
2250 2249 /* setup protection frame rate (MCS code) */
2251 2250 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 0 : 3;
2252 2251
2253 2252 /* CCK frames don't require protection */
2254 2253 RT2860_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
2255 2254
2256 2255 if (ic->ic_flags & IEEE80211_F_USEPROT) {
2257 2256 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2258 2257 tmp |= RT2860_PROT_CTRL_RTS_CTS;
2259 2258 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2260 2259 tmp |= RT2860_PROT_CTRL_CTS;
2261 2260 }
2262 2261 RT2860_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
2263 2262 }
2264 2263
2265 2264 static void
2266 2265 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
2267 2266 {
2268 2267 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
2269 2268 which | (sc->leds & 0x7f));
2270 2269 }
2271 2270
2272 2271 static int
2273 2272 rt2860_init(struct rt2860_softc *sc)
2274 2273 {
2275 2274 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2276 2275 struct ieee80211com *ic;
2277 2276 int i, err, qid, ridx, ntries;
2278 2277 uint8_t bbp1, bbp3;
2279 2278 uint32_t tmp;
2280 2279
2281 2280 ic = &sc->sc_ic;
2282 2281
2283 2282 rt2860_stop(sc);
2284 2283 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2285 2284 tmp &= 0xff0;
2286 2285 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2287 2286
2288 2287 RT2860_WRITE(sc, RT2860_WPDMA_RST_IDX, 0xffffffff);
2289 2288
2290 2289 /* PBF hardware reset */
2291 2290 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
2292 2291 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
2293 2292
2294 2293 if (!(sc->sc_flags & RT2860_FWLOADED)) {
2295 2294 if ((err = rt2860_load_microcode(sc)) != 0) {
2296 2295 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_init(): "
2297 2296 "could not load 8051 microcode\n");
2298 2297 rt2860_stop(sc);
2299 2298 return (err);
2300 2299 }
2301 2300 RT2860_GLOCK(sc);
2302 2301 sc->sc_flags |= RT2860_FWLOADED;
2303 2302 RT2860_GUNLOCK(sc);
2304 2303 }
2305 2304
2306 2305 rt2860_set_macaddr(sc, ic->ic_macaddr);
2307 2306
2308 2307 /* init Tx power for all Tx rates (from EEPROM) */
2309 2308 for (ridx = 0; ridx < 5; ridx++) {
2310 2309 if (sc->txpow20mhz[ridx] == 0xffffffff)
2311 2310 continue;
2312 2311 RT2860_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
2313 2312 }
2314 2313
2315 2314 for (ntries = 0; ntries < 100; ntries++) {
2316 2315 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2317 2316 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2318 2317 break;
2319 2318 DELAY(1000);
2320 2319 }
2321 2320 if (ntries == 100) {
2322 2321 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_init():"
2323 2322 "timeout waiting for DMA engine\n");
2324 2323 rt2860_stop(sc);
2325 2324 return (ETIMEDOUT);
2326 2325 }
2327 2326 tmp &= 0xff0;
2328 2327 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2329 2328
2330 2329 /* reset Rx ring and all 6 Tx rings */
2331 2330 RT2860_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
2332 2331
2333 2332 /* PBF hardware reset */
2334 2333 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
2335 2334 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
2336 2335
2337 2336 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2338 2337 RT2860_BBP_HRST | RT2860_MAC_SRST);
2339 2338 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
2340 2339
2341 2340 for (i = 0; i < N(rt2860_def_mac); i++)
2342 2341 RT2860_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
2343 2342
2344 2343 /* wait while MAC is busy */
2345 2344 for (ntries = 0; ntries < 100; ntries++) {
2346 2345 if (!(RT2860_READ(sc, RT2860_MAC_STATUS_REG) &
2347 2346 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
2348 2347 break;
2349 2348 DELAY(1000);
2350 2349 }
2351 2350 if (ntries == 100) {
2352 2351 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_init():"
2353 2352 "timeout waiting for MAC\n");
2354 2353 rt2860_stop(sc);
2355 2354 return (ETIMEDOUT);
2356 2355 }
2357 2356
2358 2357 /* clear Host to MCU mailbox */
2359 2358 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
2360 2359 RT2860_WRITE(sc, RT2860_H2M_MAILBOX, 0);
2361 2360
2362 2361 if ((err = rt2860_bbp_init(sc)) != 0) {
2363 2362 rt2860_stop(sc);
2364 2363 return (err);
2365 2364 }
2366 2365
2367 2366 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
2368 2367 for (qid = 0; qid < 6; qid++) {
2369 2368 RT2860_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
2370 2369 RT2860_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
2371 2370 RT2860_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
2372 2371 }
2373 2372
2374 2373 /* init Rx ring */
2375 2374 RT2860_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
2376 2375 RT2860_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
2377 2376 RT2860_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
2378 2377
2379 2378 /* setup maximum buffer sizes */
2380 2379 RT2860_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
2381 2380 (sc->sc_dmabuf_size - sizeof (struct rt2860_rxwi) - 2));
2382 2381
2383 2382 for (ntries = 0; ntries < 100; ntries++) {
2384 2383 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2385 2384 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2386 2385 break;
2387 2386 DELAY(1000);
2388 2387 }
2389 2388 if (ntries == 100) {
2390 2389 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_init():"
2391 2390 "timeout waiting for DMA engine\n");
2392 2391 rt2860_stop(sc);
2393 2392 return (ETIMEDOUT);
2394 2393 }
2395 2394 tmp &= 0xff0;
2396 2395 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2397 2396
2398 2397 /* disable interrupts mitigation */
2399 2398 RT2860_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
2400 2399
2401 2400 /* write vendor-specific BBP values (from EEPROM) */
2402 2401 for (i = 0; i < 8; i++) {
2403 2402 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
2404 2403 continue;
2405 2404 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
2406 2405 }
2407 2406
2408 2407 /* send LEDs operating mode to microcontroller */
2409 2408 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]);
2410 2409 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]);
2411 2410 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]);
2412 2411
2413 2412 /* disable non-existing Rx chains */
2414 2413 bbp3 = rt2860_mcu_bbp_read(sc, 3);
2415 2414 bbp3 &= ~(1 << 3 | 1 << 4);
2416 2415 if (sc->nrxchains == 2)
2417 2416 bbp3 |= 1 << 3;
2418 2417 else if (sc->nrxchains == 3)
2419 2418 bbp3 |= 1 << 4;
2420 2419 rt2860_mcu_bbp_write(sc, 3, bbp3);
2421 2420
2422 2421 /* disable non-existing Tx chains */
2423 2422 bbp1 = rt2860_mcu_bbp_read(sc, 1);
2424 2423 if (sc->ntxchains == 1)
2425 2424 bbp1 &= ~(1 << 3 | 1 << 4);
2426 2425 rt2860_mcu_bbp_write(sc, 1, bbp1);
2427 2426
2428 2427 /* select default channel */
2429 2428 rt2860_set_chan(sc, ic->ic_curchan);
2430 2429
2431 2430 /* XXX not clear what the following 8051 command does.. */
2432 2431 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BOOT, 0);
2433 2432
2434 2433 /* set RTS threshold */
2435 2434 tmp = RT2860_READ(sc, RT2860_TX_RTS_CFG);
2436 2435 tmp &= ~0xffff00;
2437 2436 tmp |= ic->ic_rtsthreshold << 8;
2438 2437
2439 2438 /* setup initial protection mode */
2440 2439 sc->sc_ic_flags = ic->ic_flags;
2441 2440 rt2860_updateprot(ic);
2442 2441
2443 2442 /* enable Tx/Rx DMA engine */
2444 2443 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
2445 2444 for (ntries = 0; ntries < 200; ntries++) {
2446 2445 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2447 2446 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2448 2447 break;
2449 2448 DELAY(1000);
2450 2449 }
2451 2450 if (ntries == 200) {
2452 2451 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_int():"
2453 2452 "timeout waiting for DMA engine\n");
2454 2453 rt2860_stop(sc);
2455 2454 return (ETIMEDOUT);
2456 2455 }
2457 2456
2458 2457 DELAY(50);
2459 2458
2460 2459 tmp |= RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
2461 2460 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
2462 2461 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
2463 2462
2464 2463 /* turn radio LED on */
2465 2464 rt2860_set_leds(sc, RT2860_LED_RADIO);
2466 2465
2467 2466 /* set Rx filter */
2468 2467 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
2469 2468 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2470 2469 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
2471 2470 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
2472 2471 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
2473 2472 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
2474 2473 if (ic->ic_opmode == IEEE80211_M_STA)
2475 2474 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
2476 2475 }
2477 2476 RT2860_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
2478 2477
2479 2478 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2480 2479 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
2481 2480
2482 2481 /* clear pending interrupts */
2483 2482 RT2860_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
2484 2483 /* enable interrupts */
2485 2484 RT2860_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
2486 2485
2487 2486 if (sc->sc_flags & RT2860_ADVANCED_PS)
2488 2487 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel);
2489 2488
2490 2489 return (DDI_SUCCESS);
2491 2490 }
2492 2491
2493 2492 static int
2494 2493 rt2860_quiesce(dev_info_t *dip)
2495 2494 {
2496 2495 struct rt2860_softc *sc;
2497 2496
2498 2497 sc = ddi_get_soft_state(rt2860_soft_state_p, ddi_get_instance(dip));
2499 2498 if (sc == NULL)
2500 2499 return (DDI_FAILURE);
2501 2500
2502 2501 #ifdef DEBUG
2503 2502 rt2860_dbg_flags = 0;
2504 2503 #endif
2505 2504
2506 2505 /*
2507 2506 * No more blocking is allowed while we are in quiesce(9E) entry point
2508 2507 */
2509 2508 sc->sc_flags |= RT2860_F_QUIESCE;
2510 2509
2511 2510 /*
2512 2511 * Disable and mask all interrupts
2513 2512 */
2514 2513 rt2860_stop(sc);
2515 2514 return (DDI_SUCCESS);
2516 2515 }
2517 2516
2518 2517 static void
2519 2518 rt2860_stop(struct rt2860_softc *sc)
2520 2519 {
2521 2520 int qid;
2522 2521 uint32_t tmp;
2523 2522
2524 2523 /* by pass if it's quiesced */
2525 2524 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2526 2525 RT2860_GLOCK(sc);
2527 2526 if (sc->sc_flags == RT2860_F_RUNNING)
2528 2527 rt2860_set_leds(sc, 0); /* turn all LEDs off */
2529 2528 sc->sc_tx_timer = 0;
2530 2529 /* by pass if it's quiesced */
2531 2530 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2532 2531 RT2860_GUNLOCK(sc);
2533 2532
2534 2533 /* clear RX WCID search table */
2535 2534 rt2860_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
2536 2535 /* clear pairwise key table */
2537 2536 rt2860_set_region_4(sc, RT2860_PKEY(0), 0, 2048);
2538 2537 /* clear IV/EIV table */
2539 2538 rt2860_set_region_4(sc, RT2860_IVEIV(0), 0, 512);
2540 2539 /* clear WCID attribute table */
2541 2540 rt2860_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 256);
2542 2541 /* clear shared key table */
2543 2542 rt2860_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
2544 2543 /* clear shared key mode */
2545 2544 rt2860_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
2546 2545
2547 2546 /* disable interrupts */
2548 2547 RT2860_WRITE(sc, RT2860_INT_MASK, 0);
2549 2548
2550 2549 /* disable Rx */
2551 2550 tmp = RT2860_READ(sc, RT2860_MAC_SYS_CTRL);
2552 2551 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
2553 2552 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
2554 2553
2555 2554 /* reset adapter */
2556 2555 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2557 2556 RT2860_BBP_HRST | RT2860_MAC_SRST);
2558 2557 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
2559 2558
2560 2559 /* reset Tx and Rx rings (and reclaim TXWIs) */
2561 2560 for (qid = 0; qid < 6; qid++)
2562 2561 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
2563 2562 rt2860_reset_rx_ring(sc, &sc->rxq);
2564 2563
2565 2564 /* by pass if it's quiesced */
2566 2565 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2567 2566 RT2860_GLOCK(sc);
2568 2567 sc->sc_flags &= ~RT2860_UPD_BEACON;
2569 2568 /* by pass if it's quiesced */
2570 2569 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2571 2570 RT2860_GUNLOCK(sc);
2572 2571 }
2573 2572
2574 2573 static int
2575 2574 rt2860_m_start(void *arg)
2576 2575 {
2577 2576 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2578 2577 struct ieee80211com *ic = &sc->sc_ic;
2579 2578 int err;
2580 2579
2581 2580 err = rt2860_init(sc);
2582 2581 if (err != DDI_SUCCESS) {
2583 2582 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_m_start():"
2584 2583 "Hardware initialization failed\n");
2585 2584 goto fail1;
2586 2585 }
2587 2586
2588 2587 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2589 2588
2590 2589 RT2860_GLOCK(sc);
2591 2590 sc->sc_flags |= RT2860_F_RUNNING;
2592 2591 RT2860_GUNLOCK(sc);
2593 2592
2594 2593 return (err);
2595 2594 fail1:
2596 2595 rt2860_stop(sc);
2597 2596 return (err);
2598 2597 }
2599 2598
2600 2599 static void
2601 2600 rt2860_m_stop(void *arg)
2602 2601 {
2603 2602 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2604 2603
2605 2604 (void) rt2860_stop(sc);
2606 2605
2607 2606 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2608 2607
2609 2608 RT2860_GLOCK(sc);
2610 2609 sc->sc_flags &= ~RT2860_F_RUNNING;
2611 2610 RT2860_GUNLOCK(sc);
2612 2611 }
2613 2612
2614 2613 static void
2615 2614 rt2860_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2616 2615 {
2617 2616 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2618 2617 struct ieee80211com *ic = &sc->sc_ic;
2619 2618 int err;
2620 2619
2621 2620 err = ieee80211_ioctl(ic, wq, mp);
2622 2621 RT2860_GLOCK(sc);
2623 2622 if (err == ENETRESET) {
2624 2623 if (ic->ic_des_esslen) {
2625 2624 if (RT2860_IS_RUNNING(sc)) {
2626 2625 RT2860_GUNLOCK(sc);
2627 2626 (void) rt2860_init(sc);
2628 2627 (void) ieee80211_new_state(ic,
2629 2628 IEEE80211_S_SCAN, -1);
2630 2629 RT2860_GLOCK(sc);
2631 2630 }
2632 2631 }
2633 2632 }
2634 2633 RT2860_GUNLOCK(sc);
2635 2634 }
2636 2635
2637 2636 /*
2638 2637 * Call back function for get/set proporty
2639 2638 */
2640 2639 static int
2641 2640 rt2860_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2642 2641 uint_t wldp_length, void *wldp_buf)
2643 2642 {
2644 2643 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2645 2644 int err = 0;
2646 2645
2647 2646 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2648 2647 wldp_length, wldp_buf);
2649 2648
2650 2649 return (err);
2651 2650 }
2652 2651
2653 2652 static void
2654 2653 rt2860_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2655 2654 mac_prop_info_handle_t prh)
2656 2655 {
2657 2656 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2658 2657
2659 2658 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
2660 2659 }
2661 2660
2662 2661 static int
2663 2662 rt2860_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2664 2663 uint_t wldp_length, const void *wldp_buf)
2665 2664 {
2666 2665 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2667 2666 ieee80211com_t *ic = &sc->sc_ic;
2668 2667 int err;
2669 2668
2670 2669 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
2671 2670 wldp_buf);
2672 2671 RT2860_GLOCK(sc);
2673 2672 if (err == ENETRESET) {
2674 2673 if (ic->ic_des_esslen) {
2675 2674 if (RT2860_IS_RUNNING(sc)) {
2676 2675 RT2860_GUNLOCK(sc);
2677 2676 (void) rt2860_init(sc);
2678 2677 (void) ieee80211_new_state(ic,
2679 2678 IEEE80211_S_SCAN, -1);
2680 2679 RT2860_GLOCK(sc);
2681 2680 }
2682 2681 }
2683 2682 err = 0;
2684 2683 }
2685 2684 RT2860_GUNLOCK(sc);
2686 2685 return (err);
2687 2686 }
2688 2687
2689 2688 static mblk_t *
2690 2689 rt2860_m_tx(void *arg, mblk_t *mp)
2691 2690 {
2692 2691 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2693 2692 struct ieee80211com *ic = &sc->sc_ic;
2694 2693 mblk_t *next;
2695 2694
2696 2695 if (RT2860_IS_SUSPEND(sc)) {
2697 2696 freemsgchain(mp);
2698 2697 return (NULL);
2699 2698 }
2700 2699
2701 2700 /*
2702 2701 * No data frames go out unless we're associated; this
2703 2702 * should not happen as the 802.11 layer does not enable
2704 2703 * the xmit queue until we enter the RUN state.
2705 2704 */
2706 2705 if (ic->ic_state != IEEE80211_S_RUN) {
2707 2706 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_tx_data(): "
2708 2707 "discard, state %u\n", ic->ic_state);
2709 2708 freemsgchain(mp);
2710 2709 return (NULL);
2711 2710 }
2712 2711
2713 2712 while (mp != NULL) {
2714 2713 next = mp->b_next;
2715 2714 mp->b_next = NULL;
2716 2715 if (rt2860_send(ic, mp, IEEE80211_FC0_TYPE_DATA) !=
2717 2716 DDI_SUCCESS) {
2718 2717 mp->b_next = next;
2719 2718 break;
2720 2719 }
2721 2720 mp = next;
2722 2721 }
2723 2722 return (mp);
2724 2723 }
2725 2724
2726 2725 /*ARGSUSED*/
2727 2726 static int
2728 2727 rt2860_m_unicst(void *arg, const uint8_t *macaddr)
2729 2728 {
2730 2729 return (ENOTSUP);
2731 2730 }
2732 2731
2733 2732 /*ARGSUSED*/
2734 2733 static int
2735 2734 rt2860_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
2736 2735 {
2737 2736 return (ENOTSUP);
2738 2737 }
2739 2738
2740 2739 /*ARGSUSED*/
2741 2740 static int
2742 2741 rt2860_m_promisc(void *arg, boolean_t on)
2743 2742 {
2744 2743 return (0);
2745 2744 }
2746 2745
2747 2746 static int
2748 2747 rt2860_m_stat(void *arg, uint_t stat, uint64_t *val)
2749 2748 {
2750 2749 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2751 2750 ieee80211com_t *ic = &sc->sc_ic;
2752 2751 ieee80211_node_t *ni = ic->ic_bss;
2753 2752 struct ieee80211_rateset *rs = &ni->in_rates;
2754 2753
2755 2754 RT2860_GLOCK(sc);
2756 2755 switch (stat) {
2757 2756 case MAC_STAT_IFSPEED:
2758 2757 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
2759 2758 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
2760 2759 : ic->ic_fixed_rate) / 2 * 1000000;
2761 2760 break;
2762 2761 case MAC_STAT_NOXMTBUF:
2763 2762 *val = sc->sc_tx_nobuf;
2764 2763 break;
2765 2764 case MAC_STAT_NORCVBUF:
2766 2765 *val = sc->sc_rx_nobuf;
2767 2766 break;
2768 2767 case MAC_STAT_IERRORS:
2769 2768 *val = sc->sc_rx_err;
2770 2769 break;
2771 2770 case MAC_STAT_RBYTES:
2772 2771 *val = ic->ic_stats.is_rx_bytes;
2773 2772 break;
2774 2773 case MAC_STAT_IPACKETS:
2775 2774 *val = ic->ic_stats.is_rx_frags;
2776 2775 break;
2777 2776 case MAC_STAT_OBYTES:
2778 2777 *val = ic->ic_stats.is_tx_bytes;
2779 2778 break;
2780 2779 case MAC_STAT_OPACKETS:
2781 2780 *val = ic->ic_stats.is_tx_frags;
2782 2781 break;
2783 2782 case MAC_STAT_OERRORS:
2784 2783 case WIFI_STAT_TX_FAILED:
2785 2784 *val = sc->sc_tx_err;
2786 2785 break;
2787 2786 case WIFI_STAT_TX_RETRANS:
2788 2787 *val = sc->sc_tx_retries;
2789 2788 break;
2790 2789 case WIFI_STAT_FCS_ERRORS:
2791 2790 case WIFI_STAT_WEP_ERRORS:
2792 2791 case WIFI_STAT_TX_FRAGS:
2793 2792 case WIFI_STAT_MCAST_TX:
2794 2793 case WIFI_STAT_RTS_SUCCESS:
2795 2794 case WIFI_STAT_RTS_FAILURE:
2796 2795 case WIFI_STAT_ACK_FAILURE:
2797 2796 case WIFI_STAT_RX_FRAGS:
2798 2797 case WIFI_STAT_MCAST_RX:
2799 2798 case WIFI_STAT_RX_DUPS:
2800 2799 RT2860_GUNLOCK(sc);
2801 2800 return (ieee80211_stat(ic, stat, val));
2802 2801 default:
2803 2802 RT2860_GUNLOCK(sc);
2804 2803 return (ENOTSUP);
2805 2804 }
2806 2805 RT2860_GUNLOCK(sc);
2807 2806
2808 2807 return (0);
2809 2808 }
2810 2809
2811 2810 static int
2812 2811 rt2860_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2813 2812 {
2814 2813 struct rt2860_softc *sc;
2815 2814 struct ieee80211com *ic;
2816 2815 int i, err, qid, ntries, instance;
2817 2816 uint8_t cachelsz;
2818 2817 uint16_t command, vendor_id, device_id;
2819 2818 char strbuf[32];
2820 2819 wifi_data_t wd = { 0 };
2821 2820 mac_register_t *macp;
2822 2821
2823 2822 switch (cmd) {
2824 2823 case DDI_ATTACH:
2825 2824 break;
2826 2825 case DDI_RESUME:
2827 2826 sc = ddi_get_soft_state(rt2860_soft_state_p,
2828 2827 ddi_get_instance(devinfo));
2829 2828 ASSERT(sc != NULL);
2830 2829 RT2860_GLOCK(sc);
2831 2830 sc->sc_flags &= ~RT2860_F_SUSPEND;
2832 2831 RT2860_GUNLOCK(sc);
2833 2832 if (RT2860_IS_RUNNING(sc))
2834 2833 (void) rt2860_init(sc);
2835 2834 RWN_DEBUG(RT2860_DBG_RESUME, "rwn: rt2860_attach(): "
2836 2835 "resume now\n");
2837 2836 return (DDI_SUCCESS);
2838 2837 default:
2839 2838 return (DDI_FAILURE);
2840 2839 }
2841 2840
2842 2841 instance = ddi_get_instance(devinfo);
2843 2842
2844 2843 err = ddi_soft_state_zalloc(rt2860_soft_state_p, instance);
2845 2844 if (err != DDI_SUCCESS) {
2846 2845 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2847 2846 "unable to alloc soft_state_p\n");
2848 2847 return (err);
2849 2848 }
2850 2849
2851 2850 sc = ddi_get_soft_state(rt2860_soft_state_p, instance);
2852 2851 ic = (ieee80211com_t *)&sc->sc_ic;
2853 2852 sc->sc_dev = devinfo;
2854 2853
2855 2854 /* pci configuration */
2856 2855 err = ddi_regs_map_setup(devinfo, 0, &sc->sc_cfg_base, 0, 0,
2857 2856 &rwn_csr_accattr, &sc->sc_cfg_handle);
2858 2857 if (err != DDI_SUCCESS) {
2859 2858 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2860 2859 "ddi_regs_map_setup() failed");
2861 2860 goto fail1;
2862 2861 }
2863 2862
2864 2863 cachelsz = ddi_get8(sc->sc_cfg_handle,
2865 2864 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
2866 2865 if (cachelsz == 0)
2867 2866 cachelsz = 0x10;
2868 2867 sc->sc_cachelsz = cachelsz << 2;
2869 2868 sc->sc_dmabuf_size = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
2870 2869
2871 2870 vendor_id = ddi_get16(sc->sc_cfg_handle,
2872 2871 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_VENID));
2873 2872 device_id = ddi_get16(sc->sc_cfg_handle,
2874 2873 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_DEVID));
2875 2874 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2876 2875 "vendor 0x%x, device id 0x%x, cache size %d\n",
2877 2876 vendor_id, device_id, cachelsz);
2878 2877
2879 2878 /*
2880 2879 * Enable response to memory space accesses,
2881 2880 * and enabe bus master.
2882 2881 */
2883 2882 command = PCI_COMM_MAE | PCI_COMM_ME;
2884 2883 ddi_put16(sc->sc_cfg_handle,
2885 2884 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM),
2886 2885 command);
2887 2886 ddi_put8(sc->sc_cfg_handle,
2888 2887 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8);
2889 2888 ddi_put8(sc->sc_cfg_handle,
2890 2889 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10);
2891 2890
2892 2891 /* pci i/o space */
2893 2892 err = ddi_regs_map_setup(devinfo, 1,
2894 2893 &sc->sc_io_base, 0, 0, &rwn_csr_accattr, &sc->sc_io_handle);
2895 2894 if (err != DDI_SUCCESS) {
2896 2895 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2897 2896 "ddi_regs_map_setup() failed");
2898 2897 goto fail2;
2899 2898 }
2900 2899 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2901 2900 "PCI configuration is done successfully\n");
2902 2901
2903 2902 sc->amrr.amrr_min_success_threshold = 1;
2904 2903 sc->amrr.amrr_max_success_threshold = 15;
2905 2904
2906 2905 /* wait for NIC to initialize */
2907 2906 for (ntries = 0; ntries < 100; ntries++) {
2908 2907 sc->mac_rev = RT2860_READ(sc, RT2860_ASIC_VER_ID);
2909 2908 if (sc->mac_rev != 0 && sc->mac_rev != 0xffffffff)
2910 2909 break;
2911 2910 DELAY(10);
2912 2911 }
2913 2912 if (ntries == 100) {
2914 2913 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2915 2914 "timeout waiting for NIC initialize\n");
2916 2915 return (DDI_FAILURE);
2917 2916 }
2918 2917
2919 2918 if ((sc->mac_rev >> 16) != 0x2860 &&
2920 2919 (device_id == PRODUCT_RALINK_RT2890 ||
2921 2920 device_id == PRODUCT_RALINK_RT2790 ||
2922 2921 device_id == PRODUCT_AWT_RT2890))
2923 2922 sc->sc_flags |= RT2860_ADVANCED_PS;
2924 2923
2925 2924 /* retrieve RF rev. no and various other things from EEPROM */
2926 2925 (void) rt2860_read_eeprom(sc);
2927 2926 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2928 2927 "MAC/BBP RT%X (rev 0x%04X), RF %s (%dT%dR)\n",
2929 2928 sc->mac_rev >> 16, sc->mac_rev & 0xffff,
2930 2929 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains);
2931 2930
2932 2931 /*
2933 2932 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
2934 2933 */
2935 2934 for (qid = 0; qid < 6; qid++) {
2936 2935 if ((err = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
2937 2936 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2938 2937 "could not allocate Tx ring %d\n", qid);
2939 2938 goto fail3;
2940 2939 }
2941 2940 }
2942 2941
2943 2942 if ((err = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
2944 2943 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2945 2944 "could not allocte Rx ring\n");
2946 2945 goto fail4;
2947 2946 }
2948 2947
2949 2948 if ((err = rt2860_alloc_tx_pool(sc)) != 0) {
2950 2949 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2951 2950 "could not allocte Tx pool\n");
2952 2951 goto fail5;
2953 2952 }
2954 2953
2955 2954 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
2956 2955 mutex_init(&sc->sc_txlock, NULL, MUTEX_DRIVER, NULL);
2957 2956 mutex_init(&sc->sc_rxlock, NULL, MUTEX_DRIVER, NULL);
2958 2957
2959 2958 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
2960 2959 sc->mgtqid = (sc->mac_rev == 0x28600100) ? EDCA_AC_VO : 5;
2961 2960 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach():"
2962 2961 "mgtqid = %x\n", sc->mgtqid);
2963 2962
2964 2963 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
2965 2964 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
2966 2965 ic->ic_state = IEEE80211_S_INIT;
2967 2966
2968 2967 /* set device capabilities */
2969 2968 ic->ic_caps =
2970 2969 IEEE80211_C_TXPMGT | /* tx power management */
2971 2970 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
2972 2971 IEEE80211_C_SHSLOT; /* short slot time supported */
2973 2972
2974 2973 /* WPA/WPA2 support */
2975 2974 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
2976 2975
2977 2976 /* set supported .11b and .11g rates */
2978 2977 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2860_rateset_11b;
2979 2978 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2860_rateset_11g;
2980 2979
2981 2980 /* set supported .11b and .11g channels (1 through 14) */
2982 2981 for (i = 1; i <= 14; i++) {
2983 2982 ic->ic_sup_channels[i].ich_freq =
2984 2983 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
2985 2984 ic->ic_sup_channels[i].ich_flags =
2986 2985 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
2987 2986 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
2988 2987 }
2989 2988
2990 2989 ic->ic_maxrssi = 63;
2991 2990 ic->ic_xmit = rt2860_send;
2992 2991
2993 2992 ieee80211_attach(ic);
2994 2993
2995 2994 /* register WPA door */
2996 2995 ieee80211_register_door(ic, ddi_driver_name(devinfo),
2997 2996 ddi_get_instance(devinfo));
2998 2997
2999 2998 /* override state transition machine */
3000 2999 sc->sc_newstate = ic->ic_newstate;
3001 3000 ic->ic_newstate = rt2860_newstate;
3002 3001 ieee80211_media_init(ic);
3003 3002 ic->ic_def_txkey = 0;
3004 3003
3005 3004 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW,
3006 3005 &sc->sc_softintr_hdl, NULL, 0, rt2860_softintr, (caddr_t)sc);
3007 3006 if (err != DDI_SUCCESS) {
3008 3007 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3009 3008 "ddi_add_softintr() failed");
3010 3009 goto fail8;
3011 3010 }
3012 3011
3013 3012 err = ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock);
3014 3013 if (err != DDI_SUCCESS) {
3015 3014 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3016 3015 "Can not get iblock cookie for INT\n");
3017 3016 goto fail7;
3018 3017 }
3019 3018
3020 3019 err = ddi_add_intr(devinfo, 0, NULL, NULL, rt2860_intr, (caddr_t)sc);
3021 3020 if (err != DDI_SUCCESS) {
3022 3021 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3023 3022 "unable to add device interrupt handler\n");
3024 3023 goto fail7;
3025 3024 }
3026 3025
3027 3026 /*
3028 3027 * Provide initial settings for the WiFi plugin; whenever this
3029 3028 * information changes, we need to call mac_plugindata_update()
3030 3029 */
3031 3030 wd.wd_opmode = ic->ic_opmode;
3032 3031 wd.wd_secalloc = WIFI_SEC_NONE;
3033 3032 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
3034 3033
3035 3034 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
3036 3035 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3037 3036 "MAC version mismatch\n");
3038 3037 goto fail9;
3039 3038 }
3040 3039
3041 3040 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
3042 3041 macp->m_driver = sc;
3043 3042 macp->m_dip = devinfo;
3044 3043 macp->m_src_addr = ic->ic_macaddr;
3045 3044 macp->m_callbacks = &rt2860_m_callbacks;
3046 3045 macp->m_min_sdu = 0;
3047 3046 macp->m_max_sdu = IEEE80211_MTU;
3048 3047 macp->m_pdata = &wd;
3049 3048 macp->m_pdata_size = sizeof (wd);
3050 3049
3051 3050 err = mac_register(macp, &ic->ic_mach);
3052 3051 mac_free(macp);
3053 3052 if (err != 0) {
3054 3053 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3055 3054 "mac_register err %x\n", err);
3056 3055 goto fail9;
3057 3056 }
3058 3057
3059 3058 /*
3060 3059 * Create minor node of type DDI_NT_NET_WIFI
3061 3060 */
3062 3061 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
3063 3062 "rwn", instance);
3064 3063 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
3065 3064 instance + 1, DDI_NT_NET_WIFI, 0);
3066 3065
3067 3066 /*
3068 3067 * Notify link is down now
3069 3068 */
3070 3069 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
3071 3070
3072 3071 sc->sc_flags &= ~RT2860_F_RUNNING;
3073 3072
3074 3073 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach() successfully.\n");
3075 3074 return (DDI_SUCCESS);
3076 3075 fail9:
3077 3076 ddi_remove_softintr(sc->sc_softintr_hdl);
3078 3077 fail8:
3079 3078 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
3080 3079 fail7:
3081 3080 mutex_destroy(&sc->sc_genlock);
3082 3081 mutex_destroy(&sc->sc_txlock);
3083 3082 mutex_destroy(&sc->sc_rxlock);
3084 3083 fail6:
3085 3084 rt2860_free_tx_pool(sc);
3086 3085 fail5:
3087 3086 rt2860_free_rx_ring(sc, &sc->rxq);
3088 3087 fail4:
3089 3088 while (--qid >= 0)
3090 3089 rt2860_free_tx_ring(sc, &sc->txq[qid]);
3091 3090 fail3:
3092 3091 ddi_regs_map_free(&sc->sc_io_handle);
3093 3092 fail2:
3094 3093 ddi_regs_map_free(&sc->sc_cfg_handle);
3095 3094 fail1:
3096 3095 return (err);
3097 3096 }
3098 3097
3099 3098 static int
3100 3099 rt2860_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
3101 3100 {
3102 3101 struct rt2860_softc *sc;
3103 3102 int qid;
3104 3103
3105 3104 sc = ddi_get_soft_state(rt2860_soft_state_p, ddi_get_instance(devinfo));
3106 3105
3107 3106 switch (cmd) {
3108 3107 case DDI_DETACH:
3109 3108 break;
3110 3109 case DDI_SUSPEND:
3111 3110 if (RT2860_IS_RUNNING(sc))
3112 3111 rt2860_stop(sc);
3113 3112 RT2860_GLOCK(sc);
3114 3113 sc->sc_flags &= ~RT2860_FWLOADED;
3115 3114 sc->sc_flags |= RT2860_F_SUSPEND;
3116 3115 RT2860_GUNLOCK(sc);
3117 3116 RWN_DEBUG(RT2860_DBG_RESUME, "rwn: rt2860_detach(): "
3118 3117 "suspend now\n");
3119 3118 return (DDI_SUCCESS);
3120 3119 default:
3121 3120 return (DDI_FAILURE);
3122 3121 }
3123 3122
3124 3123 if (mac_disable(sc->sc_ic.ic_mach) != 0)
3125 3124 return (DDI_FAILURE);
3126 3125
3127 3126 rt2860_stop(sc);
3128 3127
3129 3128 /*
3130 3129 * Unregister from the MAC layer subsystem
3131 3130 */
3132 3131 (void) mac_unregister(sc->sc_ic.ic_mach);
3133 3132
3134 3133 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
3135 3134 ddi_remove_softintr(sc->sc_softintr_hdl);
3136 3135
3137 3136 /*
3138 3137 * detach ieee80211 layer
3139 3138 */
3140 3139 ieee80211_detach(&sc->sc_ic);
3141 3140
3142 3141 rt2860_free_tx_pool(sc);
3143 3142 rt2860_free_rx_ring(sc, &sc->rxq);
3144 3143 for (qid = 0; qid < 6; qid++)
3145 3144 rt2860_free_tx_ring(sc, &sc->txq[qid]);
3146 3145
3147 3146 ddi_regs_map_free(&sc->sc_io_handle);
3148 3147
3149 3148 mutex_destroy(&sc->sc_genlock);
3150 3149 mutex_destroy(&sc->sc_txlock);
3151 3150 mutex_destroy(&sc->sc_rxlock);
3152 3151
3153 3152 ddi_remove_minor_node(devinfo, NULL);
3154 3153 ddi_soft_state_free(rt2860_soft_state_p, ddi_get_instance(devinfo));
3155 3154
3156 3155 return (DDI_SUCCESS);
3157 3156 }
3158 3157
3159 3158 int
3160 3159 _info(struct modinfo *modinfop)
3161 3160 {
3162 3161 return (mod_info(&modlinkage, modinfop));
3163 3162 }
3164 3163
3165 3164 int
3166 3165 _init(void)
3167 3166 {
3168 3167 int status;
3169 3168
3170 3169 status = ddi_soft_state_init(&rt2860_soft_state_p,
3171 3170 sizeof (struct rt2860_softc), 1);
3172 3171 if (status != 0)
3173 3172 return (status);
3174 3173
3175 3174 mac_init_ops(&rwn_dev_ops, "rwn");
3176 3175 status = mod_install(&modlinkage);
3177 3176 if (status != 0) {
3178 3177 mac_fini_ops(&rwn_dev_ops);
3179 3178 ddi_soft_state_fini(&rt2860_soft_state_p);
3180 3179 }
3181 3180 return (status);
3182 3181 }
3183 3182
3184 3183 int
3185 3184 _fini(void)
3186 3185 {
3187 3186 int status;
3188 3187
3189 3188 status = mod_remove(&modlinkage);
3190 3189 if (status == 0) {
3191 3190 mac_fini_ops(&rwn_dev_ops);
3192 3191 ddi_soft_state_fini(&rt2860_soft_state_p);
3193 3192 }
3194 3193 return (status);
3195 3194 }
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