1 /*
2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 * Use is subject to license terms.
4 */
5
6 /*
7 * Copyright (c) 2007, 2008
8 * Damien Bergamini <damien.bergamini@free.fr>
9 *
10 * Permission to use, copy, modify, and distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
12 * copyright notice and this permission notice appear in all copies.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 */
22
23 /*
24 * Ralink Technology RT2860 chipset driver
25 * http://www.ralinktech.com/
26 */
27
28 #include <sys/types.h>
29 #include <sys/byteorder.h>
30 #include <sys/conf.h>
31 #include <sys/cmn_err.h>
32 #include <sys/stat.h>
33 #include <sys/ddi.h>
34 #include <sys/sunddi.h>
35 #include <sys/strsubr.h>
36 #include <inet/common.h>
37 #include <sys/note.h>
38 #include <sys/stream.h>
39 #include <sys/strsun.h>
40 #include <sys/modctl.h>
41 #include <sys/devops.h>
42 #include <sys/mac_provider.h>
43 #include <sys/mac_wifi.h>
44 #include <sys/net80211.h>
45 #include <sys/net80211_proto.h>
46 #include <sys/varargs.h>
47 #include <sys/pci.h>
48 #include <sys/crypto/common.h>
49 #include <sys/crypto/api.h>
50 #include <inet/wifi_ioctl.h>
51
52 #include "rt2860_reg.h"
53 #include "rt2860_var.h"
54
55 #define RT2860_DBG_80211 (1 << 0)
56 #define RT2860_DBG_DMA (1 << 1)
57 #define RT2860_DBG_EEPROM (1 << 2)
58 #define RT2860_DBG_FW (1 << 3)
59 #define RT2860_DBG_HW (1 << 4)
60 #define RT2860_DBG_INTR (1 << 5)
61 #define RT2860_DBG_RX (1 << 6)
62 #define RT2860_DBG_SCAN (1 << 7)
63 #define RT2860_DBG_TX (1 << 8)
64 #define RT2860_DBG_RADIO (1 << 9)
65 #define RT2860_DBG_RESUME (1 << 10)
66 #define RT2860_DBG_MSG (1 << 11)
67
68 uint32_t rt2860_dbg_flags = 0x0;
69
70 #ifdef DEBUG
71 #define RWN_DEBUG \
72 rt2860_debug
73 #else
74 #define RWN_DEBUG
75 #endif
76
77 static void *rt2860_soft_state_p = NULL;
78 static uint8_t rt2860_fw_bin [] = {
79 #include "fw-rt2860/rt2860.ucode"
80 };
81
82 static const struct ieee80211_rateset rt2860_rateset_11b =
83 { 4, { 2, 4, 11, 22 } };
84
85 static const struct ieee80211_rateset rt2860_rateset_11g =
86 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
87
88 static const struct {
89 uint32_t reg;
90 uint32_t val;
91 } rt2860_def_mac[] = {
92 RT2860_DEF_MAC
93 };
94
95 static const struct {
96 uint8_t reg;
97 uint8_t val;
98 } rt2860_def_bbp[] = {
99 RT2860_DEF_BBP
100 };
101
102 static const struct rfprog {
103 uint8_t chan;
104 uint32_t r1, r2, r3, r4;
105 } rt2860_rf2850[] = {
106 RT2860_RF2850
107 };
108
109 /*
110 * PIO access attributes for registers
111 */
112 static ddi_device_acc_attr_t rwn_csr_accattr = {
113 DDI_DEVICE_ATTR_V0,
114 DDI_STRUCTURE_LE_ACC,
115 DDI_STRICTORDER_ACC
116 };
117
118 /*
119 * DMA access attributes for descriptors: NOT to be byte swapped.
120 */
121 static ddi_device_acc_attr_t rt2860_desc_accattr = {
122 DDI_DEVICE_ATTR_V0,
123 DDI_STRUCTURE_LE_ACC,
124 DDI_STRICTORDER_ACC
125 };
126
127 static ddi_device_acc_attr_t rt2860_buf_accattr = {
128 DDI_DEVICE_ATTR_V0,
129 DDI_NEVERSWAP_ACC,
130 DDI_STRICTORDER_ACC,
131 DDI_DEFAULT_ACC
132 };
133
134 /*
135 * Describes the chip's DMA engine
136 */
137 static ddi_dma_attr_t rt2860_dma_attr = {
138 DMA_ATTR_V0, /* dma_attr version */
139 0x0, /* dma_attr_addr_lo */
140 0xffffffffU, /* dma_attr_addr_hi */
141 0xffffffffU, /* dma_attr_count_max */
142 16, /* dma_attr_align */
143 0x00000fff, /* dma_attr_burstsizes */
144 1, /* dma_attr_minxfer */
145 0xffffffffU, /* dma_attr_maxxfer */
146 0xffffffffU, /* dma_attr_seg */
147 1, /* dma_attr_sgllen */
148 1, /* dma_attr_granular */
149 0 /* dma_attr_flags */
150 };
151
152 static uint16_t rt2860_eeprom_read(struct rt2860_softc *, uint8_t);
153 static int rt2860_read_eeprom(struct rt2860_softc *);
154 const char *rt2860_get_rf(uint8_t);
155 static int rt2860_alloc_dma_mem(dev_info_t *, ddi_dma_attr_t *, size_t,
156 ddi_device_acc_attr_t *, uint_t, uint_t, struct dma_area *);
157 static void rt2860_free_dma_mem(struct dma_area *);
158 static int rt2860_alloc_tx_ring(struct rt2860_softc *,
159 struct rt2860_tx_ring *);
160 static void rt2860_free_tx_ring(struct rt2860_softc *,
161 struct rt2860_tx_ring *);
162 static int rt2860_alloc_rx_ring(struct rt2860_softc *,
163 struct rt2860_rx_ring *);
164 static void rt2860_free_rx_ring(struct rt2860_softc *,
165 struct rt2860_rx_ring *);
166 static int rt2860_alloc_tx_pool(struct rt2860_softc *);
167 static void rt2860_free_tx_pool(struct rt2860_softc *);
168 static uint16_t rt2860_txtime(int, int, uint32_t);
169 static int rt2860_ack_rate(struct ieee80211com *, int);
170 static int rt2860_send(ieee80211com_t *, mblk_t *, uint8_t);
171 static uint8_t rt2860_maxrssi_chain(struct rt2860_softc *,
172 const struct rt2860_rxwi *);
173 static void rt2860_drain_stats_fifo(struct rt2860_softc *);
174 static void rt2860_tx_intr(struct rt2860_softc *, int);
175 static void rt2860_rx_intr(struct rt2860_softc *);
176 static uint_t rt2860_softintr(caddr_t);
177 static uint_t rt2860_intr(caddr_t);
178 static void rt2860_set_region_4(struct rt2860_softc *,
179 uint32_t, uint32_t, int);
180 static int rt2860_load_microcode(struct rt2860_softc *);
181 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
182 static int rt2860_bbp_init(struct rt2860_softc *);
183 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
184 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
185 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t);
186 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
187 static void rt2860_select_chan_group(struct rt2860_softc *, int);
188 static void rt2860_set_chan(struct rt2860_softc *,
189 struct ieee80211_channel *);
190 static void rt2860_updateprot(struct ieee80211com *);
191 static void rt2860_set_leds(struct rt2860_softc *, uint16_t);
192 static void rt2860_next_scan(void *);
193 static void rt2860_iter_func(void *, struct ieee80211_node *);
194 static void rt2860_updateslot(struct rt2860_softc *);
195 static uint8_t rt2860_rate2mcs(uint8_t);
196 static void rt2860_enable_mrr(struct rt2860_softc *);
197 static void rt2860_set_txpreamble(struct rt2860_softc *);
198 static void rt2860_set_basicrates(struct rt2860_softc *);
199 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
200 static void rt2860_amrr_node_init(const struct rt2860_amrr *,
201 struct rt2860_amrr_node *);
202 static void rt2860_amrr_choose(struct rt2860_amrr *,
203 struct ieee80211_node *, struct rt2860_amrr_node *);
204 static void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *,
205 int);
206 static void rt2860_enable_tsf_sync(struct rt2860_softc *);
207 static int rt2860_newstate(struct ieee80211com *,
208 enum ieee80211_state, int);
209 static int rt2860_init(struct rt2860_softc *);
210 static void rt2860_stop(struct rt2860_softc *);
211 static int rt2860_quiesce(dev_info_t *t);
212
213 /*
214 * device operations
215 */
216 static int rt2860_attach(dev_info_t *, ddi_attach_cmd_t);
217 static int rt2860_detach(dev_info_t *, ddi_detach_cmd_t);
218
219 /*
220 * Module Loading Data & Entry Points
221 */
222 DDI_DEFINE_STREAM_OPS(rwn_dev_ops, nulldev, nulldev, rt2860_attach,
223 rt2860_detach, nodev, NULL, D_MP, NULL, rt2860_quiesce);
224
225 static struct modldrv rwn_modldrv = {
226 &mod_driverops, /* Type of module. This one is a driver */
227 "Ralink RT2700/2800 driver v1.2", /* short description */
228 &rwn_dev_ops /* driver specific ops */
229 };
230
231 static struct modlinkage modlinkage = {
232 MODREV_1,
233 { (void *)&rwn_modldrv, NULL }
234 };
235
236 static int rt2860_m_stat(void *, uint_t, uint64_t *);
237 static int rt2860_m_start(void *);
238 static void rt2860_m_stop(void *);
239 static int rt2860_m_promisc(void *, boolean_t);
240 static int rt2860_m_multicst(void *, boolean_t, const uint8_t *);
241 static int rt2860_m_unicst(void *, const uint8_t *);
242 static mblk_t *rt2860_m_tx(void *, mblk_t *);
243 static void rt2860_m_ioctl(void *, queue_t *, mblk_t *);
244 static int rt2860_m_setprop(void *arg, const char *pr_name,
245 mac_prop_id_t wldp_pr_num,
246 uint_t wldp_length, const void *wldp_buf);
247 static void rt2860_m_propinfo(void *arg, const char *pr_name,
248 mac_prop_id_t wldp_pr_num, mac_prop_info_handle_t prh);
249 static int rt2860_m_getprop(void *arg, const char *pr_name,
250 mac_prop_id_t wldp_pr_num, uint_t wldp_length,
251 void *wldp_buf);
252
253 static mac_callbacks_t rt2860_m_callbacks = {
254 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
255 rt2860_m_stat,
256 rt2860_m_start,
257 rt2860_m_stop,
258 rt2860_m_promisc,
259 rt2860_m_multicst,
260 rt2860_m_unicst,
261 rt2860_m_tx,
262 NULL,
263 rt2860_m_ioctl,
264 NULL,
265 NULL,
266 NULL,
267 rt2860_m_setprop,
268 rt2860_m_getprop,
269 rt2860_m_propinfo
270 };
271
272 #ifdef DEBUG
273 void
274 rt2860_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
275 {
276 va_list args;
277
278 if (dbg_flags & rt2860_dbg_flags) {
279 va_start(args, fmt);
280 vcmn_err(CE_CONT, fmt, args);
281 va_end(args);
282 }
283 }
284 #endif
285
286 const char *
287 rt2860_get_rf(uint8_t rev)
288 {
289 switch (rev) {
290 case RT2860_RF_2820: return "RT2820";
291 case RT2860_RF_2850: return "RT2850";
292 case RT2860_RF_2720: return "RT2720";
293 case RT2860_RF_2750: return "RT2750";
294 default: return "unknown";
295 }
296 }
297
298 /*
299 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
300 * 93C66 or 93C86).
301 */
302 static uint16_t
303 rt2860_eeprom_read(struct rt2860_softc *sc, uint8_t addr)
304 {
305 int n;
306 uint16_t val;
307 uint32_t tmp;
308
309 /* clock C once before the first command */
310 RT2860_EEPROM_CTL(sc, 0);
311
312 RT2860_EEPROM_CTL(sc, RT2860_S);
313 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
314 RT2860_EEPROM_CTL(sc, RT2860_S);
315
316 /* write start bit (1) */
317 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
318 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
319
320 /* write READ opcode (10) */
321 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
322 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
323 RT2860_EEPROM_CTL(sc, RT2860_S);
324 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
325
326 /* write address (A5-A0 or A7-A0) */
327 n = ((RT2860_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
328 for (; n >= 0; n--) {
329 RT2860_EEPROM_CTL(sc, RT2860_S |
330 (((addr >> n) & 1) << RT2860_SHIFT_D));
331 RT2860_EEPROM_CTL(sc, RT2860_S |
332 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
333 }
334
335 RT2860_EEPROM_CTL(sc, RT2860_S);
336
337 /* read data Q15-Q0 */
338 val = 0;
339 for (n = 15; n >= 0; n--) {
340 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
341 tmp = RT2860_READ(sc, RT2860_PCI_EECTRL);
342 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
343 RT2860_EEPROM_CTL(sc, RT2860_S);
344 }
345
346 RT2860_EEPROM_CTL(sc, 0);
347
348 /* clear Chip Select and clock C */
349 RT2860_EEPROM_CTL(sc, RT2860_S);
350 RT2860_EEPROM_CTL(sc, 0);
351 RT2860_EEPROM_CTL(sc, RT2860_C);
352
353 return (val);
354 }
355
356 /*
357 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
358 * Used to adjust per-rate Tx power registers.
359 */
360 static inline uint32_t
361 b4inc(uint32_t b32, int8_t delta)
362 {
363 int8_t i, b4;
364
365 for (i = 0; i < 8; i++) {
366 b4 = b32 & 0xf;
367 b4 += delta;
368 if (b4 < 0)
369 b4 = 0;
370 else if (b4 > 0xf)
371 b4 = 0xf;
372 b32 = b32 >> 4 | b4 << 28;
373 }
374 return (b32);
375 }
376
377 static int
378 rt2860_read_eeprom(struct rt2860_softc *sc)
379 {
380 struct ieee80211com *ic = &sc->sc_ic;
381 int ridx, ant, i;
382 int8_t delta_2ghz, delta_5ghz;
383 uint16_t val;
384
385 /* read EEPROM version */
386 val = rt2860_eeprom_read(sc, RT2860_EEPROM_VERSION);
387 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
388 "EEPROM rev=%d, FAE=%d\n",
389 val & 0xff, val >> 8);
390
391 /* read MAC address */
392 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC01);
393 ic->ic_macaddr[0] = val & 0xff;
394 ic->ic_macaddr[1] = val >> 8;
395 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC23);
396 ic->ic_macaddr[2] = val & 0xff;
397 ic->ic_macaddr[3] = val >> 8;
398 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC45);
399 ic->ic_macaddr[4] = val & 0xff;
400 ic->ic_macaddr[5] = val >> 8;
401 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
402 "MAC address is: %x:%x:%x:%x:%x:%x\n",
403 ic->ic_macaddr[0], ic->ic_macaddr[1],
404 ic->ic_macaddr[2], ic->ic_macaddr[3],
405 ic->ic_macaddr[4], ic->ic_macaddr[5]);
406
407 /* read country code */
408 val = rt2860_eeprom_read(sc, RT2860_EEPROM_COUNTRY);
409 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
410 "EEPROM region code=0x%04x\n", val);
411
412 /* read default BBP settings */
413 for (i = 0; i < 8; i++) {
414 val = rt2860_eeprom_read(sc, RT2860_EEPROM_BBP_BASE + i);
415 sc->bbp[i].val = val & 0xff;
416 sc->bbp[i].reg = val >> 8;
417 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
418 "BBP%d=0x%02x\n",
419 sc->bbp[i].reg, sc->bbp[i].val);
420 }
421
422 /* read RF frequency offset from EEPROM */
423 val = rt2860_eeprom_read(sc, RT2860_EEPROM_FREQ_LEDS);
424 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
425 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
426 "EEPROM freq offset %d\n", sc->freq & 0xff);
427
428 if ((sc->leds = val >> 8) != 0xff) {
429 /* read LEDs operating mode */
430 sc->led[0] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED1);
431 sc->led[1] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED2);
432 sc->led[2] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED3);
433 } else {
434 /* broken EEPROM, use default settings */
435 sc->leds = 0x01;
436 sc->led[0] = 0x5555;
437 sc->led[1] = 0x2221;
438 sc->led[2] = 0xa9f8;
439 }
440 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
441 "EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
442 sc->leds, sc->led[0], sc->led[1], sc->led[2]);
443
444 /* read RF information */
445 val = rt2860_eeprom_read(sc, RT2860_EEPROM_ANTENNA);
446 if (val == 0xffff) {
447 /* broken EEPROM, default to RF2820 1T2R */
448 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
449 "invalid EEPROM antenna info, using default\n");
450 sc->rf_rev = RT2860_RF_2820;
451 sc->ntxchains = 1;
452 sc->nrxchains = 2;
453 } else {
454 sc->rf_rev = (val >> 8) & 0xf;
455 sc->ntxchains = (val >> 4) & 0xf;
456 sc->nrxchains = val & 0xf;
457 }
458 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
459 "EEPROM RF rev=0x%02x chains=%dT%dR\n",
460 sc->rf_rev, sc->ntxchains, sc->nrxchains);
461
462 /* check if RF supports automatic Tx access gain control */
463 val = rt2860_eeprom_read(sc, RT2860_EEPROM_CONFIG);
464 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
465 "EEPROM CFG 0x%04x\n", val);
466 if ((val & 0xff) != 0xff)
467 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */;
468
469 if (sc->sc_flags & RT2860_ADVANCED_PS) {
470 /* read PCIe power save level */
471 val = rt2860_eeprom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
472 if ((val & 0xff) != 0xff) {
473 sc->pslevel = val & 0x3;
474 val = rt2860_eeprom_read(sc, RT2860_EEPROM_REV);
475 if (val >> 8 != 0x92 || !(val & 0x80))
476 sc->pslevel = MIN(sc->pslevel, 1);
477 RWN_DEBUG(RT2860_DBG_EEPROM,
478 "rwn: rt2860_read_eeprom(): "
479 "EEPROM PCIe PS Level=%d\n",
480 sc->pslevel);
481 }
482 }
483 /* read power settings for 2GHz channels */
484 for (i = 0; i < 14; i += 2) {
485 val = rt2860_eeprom_read(sc,
486 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
487 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
488 sc->txpow1[i + 1] = (int8_t)(val >> 8);
489
490 val = rt2860_eeprom_read(sc,
491 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
492 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
493 sc->txpow2[i + 1] = (int8_t)(val >> 8);
494 }
495 /* fix broken Tx power entries */
496 for (i = 0; i < 14; i++) {
497 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31)
498 sc->txpow1[i] = 5;
499 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31)
500 sc->txpow2[i] = 5;
501 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
502 "chan %d: power1=%d, power2=%d\n",
503 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]);
504 }
505 /* read power settings for 5GHz channels */
506 for (i = 0; i < 36; i += 2) {
507 val = rt2860_eeprom_read(sc,
508 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
509 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
510 sc->txpow1[i + 15] = (int8_t)(val >> 8);
511
512 val = rt2860_eeprom_read(sc,
513 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
514 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
515 sc->txpow2[i + 15] = (int8_t)(val >> 8);
516 }
517 /* fix broken Tx power entries */
518 for (i = 0; i < 36; i++) {
519 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
520 sc->txpow1[14 + i] = 5;
521 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
522 sc->txpow2[14 + i] = 5;
523 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
524 "chan %d: power1=%d, power2=%d\n",
525 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
526 sc->txpow2[14 + i]);
527 }
528
529 /* read Tx power compensation for each Tx rate */
530 val = rt2860_eeprom_read(sc, RT2860_EEPROM_DELTAPWR);
531 delta_2ghz = delta_5ghz = 0;
532 if ((val & 0xff) != 0xff && (val & 0x80)) {
533 delta_2ghz = val & 0xf;
534 if (!(val & 0x40)) /* negative number */
535 delta_2ghz = -delta_2ghz;
536 }
537 val >>= 8;
538 if ((val & 0xff) != 0xff && (val & 0x80)) {
539 delta_5ghz = val & 0xf;
540 if (!(val & 0x40)) /* negative number */
541 delta_5ghz = -delta_5ghz;
542 }
543 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
544 "power compensation=%d (2GHz), %d (5GHz) \n",
545 delta_2ghz, delta_5ghz);
546
547 for (ridx = 0; ridx < 5; ridx++) {
548 uint32_t reg;
549
550 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx);
551 reg = (uint32_t)val << 16;
552 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx + 1);
553 reg |= val;
554
555 sc->txpow20mhz[ridx] = reg;
556 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
557 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
558
559 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
560 "ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
561 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
562 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]);
563 }
564
565 /* read factory-calibrated samples for temperature compensation */
566 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
567 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
568 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
569 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
570 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
571 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
572 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
573 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
574 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
575 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
576 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
577 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
578 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
579 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
580 sc->step_2ghz = val >> 8;
581 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
582 "TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
583 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
584 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
585 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
586 sc->tssi_2ghz[8], sc->step_2ghz);
587 /* check that ref value is correct, otherwise disable calibration */
588 if (sc->tssi_2ghz[4] == 0xff)
589 sc->calib_2ghz = 0;
590
591 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
592 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
593 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
594 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
595 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
596 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
597 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
598 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
599 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
600 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
601 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
602 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
603 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
604 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
605 sc->step_5ghz = val >> 8;
606 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
607 "TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
608 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
609 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
610 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
611 sc->tssi_5ghz[8], sc->step_5ghz);
612 /* check that ref value is correct, otherwise disable calibration */
613 if (sc->tssi_5ghz[4] == 0xff)
614 sc->calib_5ghz = 0;
615
616 /* read RSSI offsets and LNA gains from EEPROM */
617 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
618 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
619 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
620 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
621 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
622 sc->lna[2] = val >> 8; /* channel group 2 */
623
624 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
625 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
626 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
627 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
628 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
629 sc->lna[3] = val >> 8; /* channel group 3 */
630
631 val = rt2860_eeprom_read(sc, RT2860_EEPROM_LNA);
632 sc->lna[0] = val & 0xff; /* channel group 0 */
633 sc->lna[1] = val >> 8; /* channel group 1 */
634
635 /* fix broken 5GHz LNA entries */
636 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
637 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
638 "invalid LNA for channel group %d\n", 2);
639 sc->lna[2] = sc->lna[1];
640 }
641 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
642 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
643 "invalid LNA for channel group %d\n", 3);
644 sc->lna[3] = sc->lna[1];
645 }
646
647 /* fix broken RSSI offset entries */
648 for (ant = 0; ant < 3; ant++) {
649 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
650 RWN_DEBUG(RT2860_DBG_EEPROM,
651 "rwn: rt2860_read_eeprom(): "
652 "invalid RSSI%d offset: %d (2GHz)\n",
653 ant + 1, sc->rssi_2ghz[ant]);
654 sc->rssi_2ghz[ant] = 0;
655 }
656 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
657 RWN_DEBUG(RT2860_DBG_EEPROM,
658 "rwn: rt2860_read_eeprom(): "
659 "invalid RSSI%d offset: %d (2GHz)\n",
660 ant + 1, sc->rssi_5ghz[ant]);
661 sc->rssi_5ghz[ant] = 0;
662 }
663 }
664
665 return (RT2860_SUCCESS);
666 }
667
668 /*
669 * Allocate an DMA memory and a DMA handle for accessing it
670 */
671 static int
672 rt2860_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr,
673 size_t memsize, ddi_device_acc_attr_t *attr_p, uint_t alloc_flags,
674 uint_t bind_flags, struct dma_area *dma_p)
675 {
676 int err;
677
678 /*
679 * Allocate handle
680 */
681 err = ddi_dma_alloc_handle(devinfo, dma_attr,
682 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
683 if (err != DDI_SUCCESS) {
684 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_allo_dma_mem(): "
685 "failed to alloc handle\n");
686 goto fail1;
687 }
688
689 /*
690 * Allocate memory
691 */
692 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
693 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va,
694 &dma_p->alength, &dma_p->acc_hdl);
695 if (err != DDI_SUCCESS) {
696 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
697 "failed to alloc mem\n");
698 goto fail2;
699 }
700
701 /*
702 * Bind the two together
703 */
704 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
705 dma_p->mem_va, dma_p->alength, bind_flags,
706 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies);
707 if (err != DDI_DMA_MAPPED) {
708 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
709 "failed to bind handle\n");
710 goto fail3;
711 }
712
713 if (dma_p->ncookies != 1) {
714 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
715 "failed to alloc cookies\n");
716 goto fail4;
717 }
718
719 dma_p->nslots = ~0U;
720 dma_p->size = ~0U;
721 dma_p->token = ~0U;
722 dma_p->offset = 0;
723 return (DDI_SUCCESS);
724
725 fail4:
726 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
727 fail3:
728 ddi_dma_mem_free(&dma_p->acc_hdl);
729 fail2:
730 ddi_dma_free_handle(&dma_p->dma_hdl);
731 fail1:
732 return (err);
733 }
734
735 static void
736 rt2860_free_dma_mem(struct dma_area *dma_p)
737 {
738 if (dma_p->dma_hdl != NULL) {
739 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
740 if (dma_p->acc_hdl != NULL) {
741 ddi_dma_mem_free(&dma_p->acc_hdl);
742 dma_p->acc_hdl = NULL;
743 }
744 ddi_dma_free_handle(&dma_p->dma_hdl);
745 dma_p->ncookies = 0;
746 dma_p->dma_hdl = NULL;
747 }
748 }
749
750 /*ARGSUSED*/
751 static int
752 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
753 {
754 int size, err;
755
756 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
757
758 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
759 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
760 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
761 &ring->txdesc_dma);
762 if (err != DDI_SUCCESS) {
763 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_tx_ring(): "
764 "failed to alloc dma mem\n");
765 goto fail1;
766 }
767
768 ring->txd = (struct rt2860_txd *)ring->txdesc_dma.mem_va;
769 ring->paddr = ring->txdesc_dma.cookie.dmac_address;
770
771 ring->cur = 0;
772 ring->next = 0;
773 ring->queued = 0;
774
775 (void) bzero(ring->txd, size);
776 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
777 return (DDI_SUCCESS);
778 fail1:
779 return (err);
780 }
781
782 void
783 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
784 {
785 struct rt2860_tx_data *data;
786 int i;
787
788 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
789 ring->txd[i].sdl0 &= ~LE_16(RT2860_TX_DDONE);
790
791 if ((data = ring->data[i]) == NULL)
792 continue; /* nothing mapped in this slot */
793
794 /* by pass if it's quiesced */
795 if (!(sc->sc_flags & RT2860_F_QUIESCE))
796 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
797
798 if (data->ni != NULL) {
799 ieee80211_free_node(data->ni);
800 data->ni = NULL; /* node already freed */
801 }
802
803 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
804 ring->data[i] = NULL;
805 }
806
807 /* by pass if it's quiesced */
808 if (!(sc->sc_flags & RT2860_F_QUIESCE))
809 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
810
811 ring->queued = 0;
812 ring->cur = ring->next = 0;
813 }
814
815 /*ARGSUSED*/
816 static void
817 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
818 {
819 if (ring->txd != NULL) {
820 rt2860_free_dma_mem(&ring->txdesc_dma);
821 }
822 }
823
824 static int
825 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
826 {
827 struct rt2860_rx_data *data;
828 struct rt2860_rxd *rxd;
829 int i, err, size, datalen;
830
831 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
832
833 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
834 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
835 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
836 &ring->rxdesc_dma);
837 if (err != DDI_SUCCESS) {
838 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_rx_ring(): "
839 "failed to alloc dma mem\n");
840 goto fail1;
841 }
842
843 ring->rxd = (struct rt2860_rxd *)ring->rxdesc_dma.mem_va;
844 ring->paddr = ring->rxdesc_dma.cookie.dmac_address;
845 bzero(ring->rxd, size);
846
847 /*
848 * Pre-allocate Rx buffers and populate Rx ring.
849 */
850 datalen = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rx_data);
851 bzero(ring->data, datalen);
852 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
853 rxd = &ring->rxd[i];
854 data = &ring->data[i];
855 /* alloc DMA memory */
856 (void) rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr,
857 sc->sc_dmabuf_size,
858 &rt2860_buf_accattr,
859 DDI_DMA_STREAMING,
860 DDI_DMA_READ | DDI_DMA_STREAMING,
861 &data->rxbuf_dma);
862 rxd->sdp0 = LE_32(data->rxbuf_dma.cookie.dmac_address);
863 rxd->sdl0 = LE_16(sc->sc_dmabuf_size);
864 }
865
866 ring->cur = 0;
867
868 RT2860_DMA_SYNC(ring->rxdesc_dma, DDI_DMA_SYNC_FORDEV);
869 return (DDI_SUCCESS);
870 fail2:
871 rt2860_free_dma_mem(&ring->rxdesc_dma);
872 fail1:
873 return (err);
874 }
875
876 /*ARGSUSED*/
877 void
878 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
879 {
880 int i;
881
882 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
883 ring->rxd[i].sdl0 &= ~LE_16(RT2860_RX_DDONE);
884
885 RT2860_DMA_SYNC(ring->rxdesc_dma, DDI_DMA_SYNC_FORDEV);
886
887 ring->cur = 0;
888 }
889
890 /*ARGSUSED*/
891 static void
892 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
893 {
894 struct rt2860_rx_data *data;
895 int i, count;
896
897 if (ring->rxd != NULL)
898 rt2860_free_dma_mem(&ring->rxdesc_dma);
899
900 count = RT2860_RX_RING_COUNT;
901 if (ring->data != NULL) {
902 for (i = 0; i < count; i++) {
903 data = &ring->data[i];
904 rt2860_free_dma_mem(&data->rxbuf_dma);
905 }
906 }
907 }
908
909 static int
910 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
911 {
912 struct rt2860_tx_data *data;
913 int i, err, size;
914
915 size = RT2860_TX_POOL_COUNT * sizeof (struct rt2860_txwi);
916
917 /* init data_pool early in case of failure.. */
918 SLIST_INIT(&sc->data_pool);
919
920 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
921 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
922 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
923 &sc->txpool_dma);
924 if (err != DDI_SUCCESS) {
925 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_tx_pool(): "
926 "failed to alloc dma mem\n");
927 goto fail1;
928 }
929
930 sc->txwi = (struct rt2860_txwi *)sc->txpool_dma.mem_va;
931 (void) bzero(sc->txwi, size);
932 RT2860_DMA_SYNC(sc->txpool_dma, DDI_DMA_SYNC_FORDEV);
933
934 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
935 data = &sc->data[i];
936
937 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr,
938 sc->sc_dmabuf_size,
939 &rt2860_buf_accattr, DDI_DMA_CONSISTENT,
940 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
941 &data->txbuf_dma);
942 if (err != DDI_SUCCESS) {
943 RWN_DEBUG(RT2860_DBG_DMA,
944 "rwn: rt2860_alloc_tx_pool(): "
945 "failed to alloc dma mem\n");
946 goto fail2;
947 }
948 data->txwi = &sc->txwi[i];
949 data->paddr = sc->txpool_dma.cookie.dmac_address +
950 i * sizeof (struct rt2860_txwi);
951
952 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
953 }
954 return (DDI_SUCCESS);
955 fail2:
956 rt2860_free_dma_mem(&sc->txpool_dma);
957 fail1:
958 return (err);
959 }
960
961 static void
962 rt2860_free_tx_pool(struct rt2860_softc *sc)
963 {
964 struct rt2860_tx_data *data;
965 int i;
966
967 if (sc->txwi != NULL) {
968 rt2860_free_dma_mem(&sc->txpool_dma);
969 }
970
971 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
972 data = &sc->data[i];
973 rt2860_free_dma_mem(&data->txbuf_dma);
974 }
975 }
976
977 /* quickly determine if a given rate is CCK or OFDM */
978 #define RT2860_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
979
980 #define RT2860_ACK_SIZE 14 /* 10 + 4(FCS) */
981 #define RT2860_SIFS_TIME 10
982
983 static uint8_t
984 rt2860_rate2mcs(uint8_t rate)
985 {
986 switch (rate) {
987 /* CCK rates */
988 case 2:
989 return (0);
990 case 4:
991 return (1);
992 case 11:
993 return (2);
994 case 22:
995 return (3);
996 /* OFDM rates */
997 case 12:
998 return (0);
999 case 18:
1000 return (1);
1001 case 24:
1002 return (2);
1003 case 36:
1004 return (3);
1005 case 48:
1006 return (4);
1007 case 72:
1008 return (5);
1009 case 96:
1010 return (6);
1011 case 108:
1012 return (7);
1013 }
1014
1015 return (0); /* shouldn't get there */
1016 }
1017
1018 /*
1019 * Return the expected ack rate for a frame transmitted at rate `rate'.
1020 */
1021 static int
1022 rt2860_ack_rate(struct ieee80211com *ic, int rate)
1023 {
1024 switch (rate) {
1025 /* CCK rates */
1026 case 2:
1027 return (2);
1028 case 4:
1029 case 11:
1030 case 22:
1031 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
1032
1033 /* OFDM rates */
1034 case 12:
1035 case 18:
1036 return (12);
1037 case 24:
1038 case 36:
1039 return (24);
1040 case 48:
1041 case 72:
1042 case 96:
1043 case 108:
1044 return (48);
1045 }
1046
1047 /* default to 1Mbps */
1048 return (2);
1049 }
1050
1051
1052 /*
1053 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
1054 * The function automatically determines the operating mode depending on the
1055 * given rate. `flags' indicates whether short preamble is in use or not.
1056 */
1057 static uint16_t
1058 rt2860_txtime(int len, int rate, uint32_t flags)
1059 {
1060 uint16_t txtime;
1061
1062 if (RT2860_RATE_IS_OFDM(rate)) {
1063 /* IEEE Std 802.11g-2003, pp. 44 */
1064 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
1065 txtime = 16 + 4 + 4 * txtime + 6;
1066 } else {
1067 /* IEEE Std 802.11b-1999, pp. 28 */
1068 txtime = (16 * len + rate - 1) / rate;
1069 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
1070 txtime += 72 + 24;
1071 else
1072 txtime += 144 + 48;
1073 }
1074 return (txtime);
1075 }
1076
1077 static int
1078 rt2860_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
1079 {
1080 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1081 struct rt2860_tx_ring *ring;
1082 struct rt2860_tx_data *data;
1083 struct rt2860_txd *txd;
1084 struct rt2860_txwi *txwi;
1085 struct ieee80211_frame *wh;
1086 struct ieee80211_node *ni;
1087 int qid, off, rate, err;
1088 int mblen, pktlen;
1089 uint_t hdrlen;
1090 uint8_t mcs, pid, qsel;
1091 uint16_t dur;
1092 mblk_t *m, *m0;
1093
1094 err = DDI_SUCCESS;
1095
1096 mutex_enter(&sc->sc_txlock);
1097 if (RT2860_IS_SUSPEND(sc)) {
1098 err = ENXIO;
1099 goto fail1;
1100 }
1101
1102 if ((type & IEEE80211_FC0_TYPE_MASK) !=
1103 IEEE80211_FC0_TYPE_DATA)
1104 qid = sc->mgtqid;
1105 else
1106 qid = EDCA_AC_BE;
1107 ring = &sc->txq[qid];
1108
1109 if (SLIST_EMPTY(&sc->data_pool) || (ring->queued > 15)) {
1110 sc->sc_need_sched = 1;
1111 sc->sc_tx_nobuf++;
1112 err = ENOMEM;
1113 goto fail1;
1114 }
1115
1116 /* the data pool contains at least one element, pick the first */
1117 data = SLIST_FIRST(&sc->data_pool);
1118
1119 m = allocb(msgdsize(mp) + 32, BPRI_MED);
1120 if (m == NULL) {
1121 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_send():"
1122 "rt2860_mgmt_send: can't alloc mblk.\n");
1123 err = DDI_FAILURE;
1124 goto fail1;
1125 }
1126
1127 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
1128 mblen = MBLKL(m0);
1129 (void) bcopy(m0->b_rptr, m->b_rptr + off, mblen);
1130 off += mblen;
1131 }
1132 m->b_wptr += off;
1133
1134 wh = (struct ieee80211_frame *)m->b_rptr;
1135 ni = ieee80211_find_txnode(ic, wh->i_addr1);
1136 if (ni == NULL) {
1137 err = DDI_FAILURE;
1138 sc->sc_tx_err++;
1139 goto fail2;
1140 }
1141
1142 if ((type & IEEE80211_FC0_TYPE_MASK) ==
1143 IEEE80211_FC0_TYPE_DATA)
1144 (void) ieee80211_encap(ic, m, ni);
1145
1146 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1147 struct ieee80211_key *k;
1148 k = ieee80211_crypto_encap(ic, m);
1149 if (k == NULL) {
1150 sc->sc_tx_err++;
1151 err = DDI_FAILURE;
1152 goto fail3;
1153 }
1154 /* packet header may have moved, reset our local pointer */
1155 wh = (struct ieee80211_frame *)m->b_rptr;
1156 }
1157 pktlen = msgdsize(m);
1158 hdrlen = sizeof (*wh);
1159
1160 /* pickup a rate */
1161 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
1162 ((type & IEEE80211_FC0_TYPE_MASK) !=
1163 IEEE80211_FC0_TYPE_DATA))
1164 rate = ni->in_rates.ir_rates[0];
1165 else {
1166 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE)
1167 rate = ic->ic_fixed_rate;
1168 else
1169 rate = ni->in_rates.ir_rates[ni->in_txrate];
1170 }
1171 rate &= IEEE80211_RATE_VAL;
1172
1173 /* get MCS code from rate */
1174 mcs = rt2860_rate2mcs(rate);
1175
1176 /* setup TX Wireless Information */
1177 txwi = data->txwi;
1178 (void) bzero(txwi, sizeof (struct rt2860_txwi));
1179 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ?
1180 RT2860_AID2WCID(ni->in_associd) : 0xff;
1181 txwi->len = LE_16(pktlen);
1182 if (!RT2860_RATE_IS_OFDM(rate)) {
1183 txwi->phy = LE_16(RT2860_PHY_CCK);
1184 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1185 mcs |= RT2860_PHY_SHPRE;
1186 } else
1187 txwi->phy = LE_16(RT2860_PHY_OFDM);
1188 txwi->phy |= LE_16(mcs);
1189
1190 /*
1191 * We store the MCS code into the driver-private PacketID field.
1192 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1193 * that we know at which initial rate the frame was transmitted.
1194 * We add 1 to the MCS code because setting the PacketID field to
1195 * 0 means that we don't want feedback in TX_STAT_FIFO.
1196 */
1197 pid = (mcs + 1) & 0xf;
1198 txwi->len |= LE_16(pid << RT2860_TX_PID_SHIFT);
1199
1200 /* check if RTS/CTS or CTS-to-self protection is required */
1201 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1202 (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold ||
1203 ((ic->ic_flags &
1204 IEEE80211_F_USEPROT) && RT2860_RATE_IS_OFDM(rate))))
1205 txwi->txop = RT2860_TX_TXOP_HT;
1206 else
1207 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1208
1209 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1210 txwi->xflags |= RT2860_TX_ACK;
1211
1212 dur = rt2860_txtime(RT2860_ACK_SIZE, rt2860_ack_rate(ic, rate),
1213 ic->ic_flags) + sc->sifs;
1214 *(uint16_t *)wh->i_dur = LE_16(dur);
1215 }
1216
1217 /* copy and trim 802.11 header */
1218 bcopy(wh, &txwi->wh, hdrlen);
1219 m->b_rptr += hdrlen;
1220 bcopy(m->b_rptr, data->txbuf_dma.mem_va, pktlen - hdrlen);
1221
1222 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1223
1224 /* first segment is TXWI + 802.11 header */
1225 txd = &ring->txd[ring->cur];
1226 txd->sdp0 = LE_32(data->paddr);
1227 txd->sdl0 = LE_16(16 + hdrlen);
1228 txd->flags = qsel;
1229
1230 /* finalize last segment */
1231 txd->sdp1 = LE_32(data->txbuf_dma.cookie.dmac_address);
1232 txd->sdl1 = LE_16(pktlen - hdrlen | RT2860_TX_LS1);
1233
1234 /* remove from the free pool and link it into the SW Tx slot */
1235 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1236 data->ni = ieee80211_ref_node(ni);
1237 ring->data[ring->cur] = data;
1238
1239 (void) ddi_dma_sync(sc->txpool_dma.dma_hdl,
1240 _PTRDIFF(txwi, sc->txwi),
1241 (hdrlen + 16 + 2),
1242 DDI_DMA_SYNC_FORDEV);
1243 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
1244 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
1245
1246 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_send():"
1247 "sending frame qid=%d wcid=%d rate=%d cur = %x\n",
1248 qid, txwi->wcid, rate, ring->cur);
1249
1250 ring->queued++;
1251 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1252
1253 /* kick Tx */
1254 RT2860_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1255
1256 sc->sc_tx_timer = 5;
1257
1258 ic->ic_stats.is_tx_frags++;
1259 ic->ic_stats.is_tx_bytes += pktlen;
1260
1261 fail3:
1262 ieee80211_free_node(ni);
1263 fail2:
1264 freemsg(m);
1265 fail1:
1266 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA ||
1267 err == DDI_SUCCESS)
1268 freemsg(mp);
1269 mutex_exit(&sc->sc_txlock);
1270 return (err);
1271 }
1272
1273 /*
1274 * This function is called periodically (every 200ms) during scanning to
1275 * switch from one channel to another.
1276 */
1277 static void
1278 rt2860_next_scan(void *arg)
1279 {
1280 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1281 struct ieee80211com *ic = &sc->sc_ic;
1282
1283 if (ic->ic_state == IEEE80211_S_SCAN)
1284 (void) ieee80211_next_scan(ic);
1285 }
1286
1287 static void
1288 rt2860_updateslot(struct rt2860_softc *sc)
1289 {
1290 struct ieee80211com *ic = &sc->sc_ic;
1291 uint32_t tmp;
1292
1293 tmp = RT2860_READ(sc, RT2860_BKOFF_SLOT_CFG);
1294 tmp &= ~0xff;
1295 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1296 RT2860_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
1297 }
1298
1299 static void
1300 rt2860_iter_func(void *arg, struct ieee80211_node *ni)
1301 {
1302 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1303 uint8_t wcid;
1304
1305 wcid = RT2860_AID2WCID(ni->in_associd);
1306 rt2860_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]);
1307 }
1308
1309 static void
1310 rt2860_updatestats(void *arg)
1311 {
1312 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1313 struct ieee80211com *ic = &sc->sc_ic;
1314
1315 if (ic->ic_opmode == IEEE80211_M_STA)
1316 rt2860_iter_func(sc, ic->ic_bss);
1317 else
1318 ieee80211_iterate_nodes(&ic->ic_sta, rt2860_iter_func, arg);
1319
1320 sc->sc_rssadapt_id = timeout(rt2860_updatestats, (void *)sc,
1321 drv_usectohz(500 * 1000));
1322 }
1323
1324 static void
1325 rt2860_enable_mrr(struct rt2860_softc *sc)
1326 {
1327 #define CCK(mcs) (mcs)
1328 #define OFDM(mcs) ((uint32_t)1 << 3 | (mcs))
1329 RT2860_WRITE(sc, RT2860_LG_FBK_CFG0,
1330 OFDM(6) << 28 | /* 54->48 */
1331 OFDM(5) << 24 | /* 48->36 */
1332 OFDM(4) << 20 | /* 36->24 */
1333 OFDM(3) << 16 | /* 24->18 */
1334 OFDM(2) << 12 | /* 18->12 */
1335 OFDM(1) << 8 | /* 12-> 9 */
1336 OFDM(0) << 4 | /* 9-> 6 */
1337 OFDM(0)); /* 6-> 6 */
1338
1339 RT2860_WRITE(sc, RT2860_LG_FBK_CFG1,
1340 CCK(2) << 12 | /* 11->5.5 */
1341 CCK(1) << 8 | /* 5.5-> 2 */
1342 CCK(0) << 4 | /* 2-> 1 */
1343 CCK(0)); /* 1-> 1 */
1344 #undef OFDM
1345 #undef CCK
1346 }
1347
1348 static void
1349 rt2860_set_txpreamble(struct rt2860_softc *sc)
1350 {
1351 uint32_t tmp;
1352
1353 tmp = RT2860_READ(sc, RT2860_AUTO_RSP_CFG);
1354 tmp &= ~RT2860_CCK_SHORT_EN;
1355 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1356 tmp |= RT2860_CCK_SHORT_EN;
1357 RT2860_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
1358 }
1359
1360 static void
1361 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
1362 {
1363 RT2860_WRITE(sc, RT2860_MAC_BSSID_DW0,
1364 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
1365 RT2860_WRITE(sc, RT2860_MAC_BSSID_DW1,
1366 bssid[4] | bssid[5] << 8);
1367 }
1368
1369 static void
1370 rt2860_set_basicrates(struct rt2860_softc *sc)
1371 {
1372 struct ieee80211com *ic = &sc->sc_ic;
1373
1374 /* set basic rates mask */
1375 if (ic->ic_curmode == IEEE80211_MODE_11B)
1376 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003);
1377 else if (ic->ic_curmode == IEEE80211_MODE_11A)
1378 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150);
1379 else /* 11g */
1380 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f);
1381 }
1382
1383 static void
1384 rt2860_amrr_node_init(const struct rt2860_amrr *amrr,
1385 struct rt2860_amrr_node *amn)
1386 {
1387 amn->amn_success = 0;
1388 amn->amn_recovery = 0;
1389 amn->amn_txcnt = amn->amn_retrycnt = 0;
1390 amn->amn_success_threshold = amrr->amrr_min_success_threshold;
1391 }
1392
1393 static void
1394 rt2860_amrr_choose(struct rt2860_amrr *amrr, struct ieee80211_node *ni,
1395 struct rt2860_amrr_node *amn)
1396 {
1397 #define RV(rate) ((rate) & IEEE80211_RATE_VAL)
1398 #define is_success(amn) \
1399 ((amn)->amn_retrycnt < (amn)->amn_txcnt / 10)
1400 #define is_failure(amn) \
1401 ((amn)->amn_retrycnt > (amn)->amn_txcnt / 3)
1402 #define is_enough(amn) \
1403 ((amn)->amn_txcnt > 10)
1404 #define is_min_rate(ni) \
1405 ((ni)->in_txrate == 0)
1406 #define is_max_rate(ni) \
1407 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1)
1408 #define increase_rate(ni) \
1409 ((ni)->in_txrate++)
1410 #define decrease_rate(ni) \
1411 ((ni)->in_txrate--)
1412 #define reset_cnt(amn) \
1413 { (amn)->amn_txcnt = (amn)->amn_retrycnt = 0; }
1414
1415 int need_change = 0;
1416
1417 if (is_success(amn) && is_enough(amn)) {
1418 amn->amn_success++;
1419 if (amn->amn_success >= amn->amn_success_threshold &&
1420 !is_max_rate(ni)) {
1421 amn->amn_recovery = 1;
1422 amn->amn_success = 0;
1423 increase_rate(ni);
1424 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_amrr_choose(): "
1425 "increase rate = %d, #tx = %d, #retries = %d\n",
1426 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1427 amn->amn_txcnt, amn->amn_retrycnt);
1428 need_change = 1;
1429 } else {
1430 amn->amn_recovery = 0;
1431 }
1432 } else if (is_failure(amn)) {
1433 amn->amn_success = 0;
1434 if (!is_min_rate(ni)) {
1435 if (amn->amn_recovery) {
1436 amn->amn_success_threshold *= 2;
1437 if (amn->amn_success_threshold >
1438 amrr->amrr_max_success_threshold)
1439 amn->amn_success_threshold =
1440 amrr->amrr_max_success_threshold;
1441 } else {
1442 amn->amn_success_threshold =
1443 amrr->amrr_min_success_threshold;
1444 }
1445 decrease_rate(ni);
1446 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_amrr_choose(): "
1447 "decrease rate = %d, #tx = %d, #retries = %d\n",
1448 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1449 amn->amn_txcnt, amn->amn_retrycnt);
1450 need_change = 1;
1451 }
1452 amn->amn_recovery = 0;
1453 }
1454
1455 if (is_enough(amn) || need_change)
1456 reset_cnt(amn);
1457 #undef RV
1458 }
1459
1460 static void
1461 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *in, int isnew)
1462 {
1463 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1464 uint32_t off;
1465 uint8_t *fptr, wcid = 0;
1466 int i;
1467
1468 if (isnew && in->in_associd != 0) {
1469 /* only interested in true associations */
1470 wcid = RT2860_AID2WCID(in->in_associd);
1471
1472 /* init WCID table entry */
1473 off = RT2860_WCID_ENTRY(wcid);
1474 fptr = in->in_macaddr;
1475 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
1476 rt2860_mem_write1(sc, off++, *fptr++);
1477 }
1478 rt2860_amrr_node_init(&sc->amrr, &sc->amn[wcid]);
1479
1480 /* set rate to some reasonable initial value */
1481 i = in->in_rates.ir_nrates - 1;
1482 for (; i > 0 && (in->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72; )
1483 i--;
1484 in->in_txrate = i;
1485
1486 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newassoc(): "
1487 "new assoc isnew=%d WCID=%d, initial rate=%d\n",
1488 isnew, wcid,
1489 in->in_rates.ir_rates[i] & IEEE80211_RATE_VAL);
1490 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newassoc(): "
1491 "addr=%x:%x:%x:%x:%x:%x\n",
1492 in->in_macaddr[0], in->in_macaddr[1], in->in_macaddr[2],
1493 in->in_macaddr[3], in->in_macaddr[4], in->in_macaddr[5]);
1494 }
1495
1496 void
1497 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
1498 {
1499 struct ieee80211com *ic = &sc->sc_ic;
1500 uint32_t tmp;
1501
1502 tmp = RT2860_READ(sc, RT2860_BCN_TIME_CFG);
1503
1504 tmp &= ~0x1fffff;
1505 tmp |= ic->ic_bss->in_intval * 16;
1506 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
1507 if (ic->ic_opmode == IEEE80211_M_STA) {
1508 /*
1509 * Local TSF is always updated with remote TSF on beacon
1510 * reception.
1511 */
1512 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
1513 }
1514
1515 RT2860_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
1516 }
1517
1518 static int
1519 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1520 {
1521 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1522 enum ieee80211_state ostate;
1523 int err;
1524 uint32_t tmp;
1525
1526 ostate = ic->ic_state;
1527 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newstate(): "
1528 "%x -> %x!\n", ostate, nstate);
1529
1530 RT2860_GLOCK(sc);
1531 if (sc->sc_scan_id != 0) {
1532 (void) untimeout(sc->sc_scan_id);
1533 sc->sc_scan_id = 0;
1534 }
1535 if (sc->sc_rssadapt_id != 0) {
1536 (void) untimeout(sc->sc_rssadapt_id);
1537 sc->sc_rssadapt_id = 0;
1538 }
1539 if (ostate == IEEE80211_S_RUN) {
1540 /* turn link LED off */
1541 rt2860_set_leds(sc, RT2860_LED_RADIO);
1542 }
1543
1544 switch (nstate) {
1545 case IEEE80211_S_INIT:
1546 if (ostate == IEEE80211_S_RUN) {
1547 /* abort TSF synchronization */
1548 tmp = RT2860_READ(sc, RT2860_BCN_TIME_CFG);
1549 RT2860_WRITE(sc, RT2860_BCN_TIME_CFG,
1550 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
1551 RT2860_TBTT_TIMER_EN));
1552 }
1553 break;
1554
1555 case IEEE80211_S_SCAN:
1556 rt2860_set_chan(sc, ic->ic_curchan);
1557 sc->sc_scan_id = timeout(rt2860_next_scan, (void *)sc,
1558 drv_usectohz(200000));
1559 break;
1560
1561 case IEEE80211_S_AUTH:
1562 case IEEE80211_S_ASSOC:
1563 rt2860_set_chan(sc, ic->ic_curchan);
1564 break;
1565
1566 case IEEE80211_S_RUN:
1567 rt2860_set_chan(sc, ic->ic_curchan);
1568
1569 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1570 rt2860_updateslot(sc);
1571 rt2860_enable_mrr(sc);
1572 rt2860_set_txpreamble(sc);
1573 rt2860_set_basicrates(sc);
1574 rt2860_set_bssid(sc, ic->ic_bss->in_bssid);
1575 }
1576 if (ic->ic_opmode == IEEE80211_M_STA) {
1577 /* fake a join to init the tx rate */
1578 rt2860_newassoc(ic, ic->ic_bss, 1);
1579 }
1580
1581 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1582 rt2860_enable_tsf_sync(sc);
1583 sc->sc_rssadapt_id = timeout(rt2860_updatestats,
1584 (void *)sc, drv_usectohz(500 * 1000));
1585 }
1586
1587 /* turn link LED on */
1588 rt2860_set_leds(sc, RT2860_LED_RADIO |
1589 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ?
1590 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
1591 break;
1592 }
1593
1594 RT2860_GUNLOCK(sc);
1595
1596 err = sc->sc_newstate(ic, nstate, arg);
1597
1598 return (err);
1599 }
1600
1601 /*
1602 * Return the Rx chain with the highest RSSI for a given frame.
1603 */
1604 static uint8_t
1605 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1606 {
1607 uint8_t rxchain = 0;
1608
1609 if (sc->nrxchains > 1)
1610 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1611 rxchain = 1;
1612 if (sc->nrxchains > 2)
1613 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1614 rxchain = 2;
1615
1616 return (rxchain);
1617 }
1618
1619 static void
1620 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1621 {
1622 struct rt2860_amrr_node *amn;
1623 uint32_t stat;
1624 uint8_t wcid, mcs, pid;
1625
1626 /* drain Tx status FIFO (maxsize = 16) */
1627 while ((stat = RT2860_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1628 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_drain_stats_fifo(): "
1629 "tx stat 0x%08\n", stat);
1630
1631 wcid = (stat >> 8) & 0xff;
1632
1633 /* if no ACK was requested, no feedback is available */
1634 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff)
1635 continue;
1636 /* update per-STA AMRR stats */
1637 amn = &sc->amn[wcid];
1638 amn->amn_txcnt++;
1639 if (stat & RT2860_TXQ_OK) {
1640 /*
1641 * Check if there were retries, ie if the Tx success
1642 * rate is different from the requested rate. Note
1643 * that it works only because we do not allow rate
1644 * fallback from OFDM to CCK.
1645 */
1646 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1647 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1648 if (mcs + 1 != pid)
1649 amn->amn_retrycnt++;
1650 } else
1651 amn->amn_retrycnt++;
1652 }
1653 }
1654
1655 /*ARGSUSED*/
1656 static void
1657 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1658 {
1659 struct rt2860_tx_ring *ring = &sc->txq[qid];
1660 struct ieee80211com *ic = &sc->sc_ic;
1661 uint32_t hw;
1662
1663 rt2860_drain_stats_fifo(sc);
1664
1665 mutex_enter(&sc->sc_txlock);
1666 hw = RT2860_READ(sc, RT2860_TX_DTX_IDX(qid));
1667 RWN_DEBUG(RT2860_DBG_TX, "rwn: rwn_tx_intr():"
1668 "hw = %x, ring->next = %x, queued = %d\n",
1669 hw, ring->next, ring->queued);
1670 while (ring->next != hw) {
1671 struct rt2860_txd *txd = &ring->txd[ring->next];
1672 struct rt2860_tx_data *data = ring->data[ring->next];
1673
1674 if (data != NULL) {
1675 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
1676 if (data->ni != NULL) {
1677 ieee80211_free_node(data->ni);
1678 data->ni = NULL;
1679 }
1680 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1681 ring->data[ring->next] = NULL;
1682 }
1683
1684 txd->sdl0 &= ~LE_16(RT2860_TX_DDONE);
1685
1686 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
1687 ring->next * sizeof (struct rt2860_txd),
1688 sizeof (struct rt2860_txd),
1689 DDI_DMA_SYNC_FORDEV);
1690
1691 ring->queued--;
1692 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1693
1694 if (sc->sc_need_sched &&
1695 (ring->queued < RT2860_TX_RING_COUNT)) {
1696 sc->sc_need_sched = 0;
1697 mac_tx_update(ic->ic_mach);
1698 }
1699 }
1700 sc->sc_tx_timer = 0;
1701 mutex_exit(&sc->sc_txlock);
1702 }
1703
1704 static void
1705 rt2860_rx_intr(struct rt2860_softc *sc)
1706 {
1707 struct ieee80211com *ic = &sc->sc_ic;
1708 struct ieee80211_node *ni;
1709 struct ieee80211_frame *wh;
1710 int pktlen;
1711 uint8_t ant, rssi, *rxbuf;
1712 mblk_t *mp0;
1713
1714 mutex_enter(&sc->sc_rxlock);
1715 for (;;) {
1716 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1717 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1718 struct rt2860_rxwi *rxwi;
1719
1720 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl,
1721 sc->rxq.cur * sizeof (struct rt2860_rxd),
1722 sizeof (struct rt2860_rxd),
1723 DDI_DMA_SYNC_FORKERNEL);
1724
1725 if (!(rxd->sdl0 & LE_16(RT2860_RX_DDONE))) {
1726 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1727 "rx done!\n");
1728 break;
1729 }
1730
1731 if (rxd->flags &
1732 LE_32(RT2860_RX_CRCERR | RT2860_RX_ICVERR)) {
1733 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1734 "rx crc error & rx icv error!\n");
1735 sc->sc_rx_err++;
1736 goto skip;
1737 }
1738
1739 if (rxd->flags & LE_32(RT2860_RX_MICERR)) {
1740 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1741 "rx mic error!\n");
1742 sc->sc_rx_err++;
1743 goto skip;
1744 }
1745
1746 (void) ddi_dma_sync(data->rxbuf_dma.dma_hdl,
1747 data->rxbuf_dma.offset,
1748 data->rxbuf_dma.alength,
1749 DDI_DMA_SYNC_FORCPU);
1750
1751 rxbuf = (uint8_t *)data->rxbuf_dma.mem_va;
1752 rxd->sdp0 = LE_32(data->rxbuf_dma.cookie.dmac_address);
1753 rxwi = (struct rt2860_rxwi *)rxbuf;
1754 rxbuf = (uint8_t *)(rxwi + 1);
1755 pktlen = LE_16(rxwi->len) & 0xfff;
1756
1757 mp0 = allocb(sc->sc_dmabuf_size, BPRI_MED);
1758 if (mp0 == NULL) {
1759 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr():"
1760 "alloc mblk error\n");
1761 sc->sc_rx_nobuf++;
1762 goto skip;
1763 }
1764 bcopy(rxbuf, mp0->b_rptr, pktlen);
1765 mp0->b_wptr += pktlen;
1766
1767 wh = (struct ieee80211_frame *)mp0->b_rptr;
1768
1769 /* HW may insert 2 padding bytes after 802.11 header */
1770 if (rxd->flags & LE_32(RT2860_RX_L2PAD)) {
1771 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr():"
1772 "2 padding bytes after 80211 header!\n");
1773 }
1774
1775 ant = rt2860_maxrssi_chain(sc, rxwi);
1776 rssi = RT2860_RSSI_OFFSET - rxwi->rssi[ant];
1777 /* grab a reference to the source node */
1778 ni = ieee80211_find_rxnode(ic, wh);
1779
1780 (void) ieee80211_input(ic, mp0, ni, rssi, 0);
1781
1782 /* node is no longer needed */
1783 ieee80211_free_node(ni);
1784 skip:
1785 rxd->sdl0 &= ~LE_16(RT2860_RX_DDONE);
1786
1787 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl,
1788 sc->rxq.cur * sizeof (struct rt2860_rxd),
1789 sizeof (struct rt2860_rxd),
1790 DDI_DMA_SYNC_FORDEV);
1791
1792 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1793 }
1794 mutex_exit(&sc->sc_rxlock);
1795
1796 /* tell HW what we have processed */
1797 RT2860_WRITE(sc, RT2860_RX_CALC_IDX,
1798 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1799 }
1800
1801 static uint_t
1802 rt2860_softintr(caddr_t data)
1803 {
1804 struct rt2860_softc *sc = (struct rt2860_softc *)data;
1805
1806 /*
1807 * Check if the soft interrupt is triggered by another
1808 * driver at the same level.
1809 */
1810 RT2860_GLOCK(sc);
1811 if (sc->sc_rx_pend) {
1812 sc->sc_rx_pend = 0;
1813 RT2860_GUNLOCK(sc);
1814 rt2860_rx_intr(sc);
1815 return (DDI_INTR_CLAIMED);
1816 }
1817 RT2860_GUNLOCK(sc);
1818
1819 return (DDI_INTR_UNCLAIMED);
1820 }
1821
1822 static uint_t
1823 rt2860_intr(caddr_t arg)
1824 {
1825 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1826 uint32_t r;
1827
1828 RT2860_GLOCK(sc);
1829
1830 if ((!RT2860_IS_RUNNING(sc)) || RT2860_IS_SUSPEND(sc)) {
1831 /*
1832 * The hardware is not ready/present, don't touch anything.
1833 * Note this can happen early on if the IRQ is shared.
1834 */
1835 RT2860_GUNLOCK(sc);
1836 return (DDI_INTR_UNCLAIMED);
1837 }
1838
1839 r = RT2860_READ(sc, RT2860_INT_STATUS);
1840 if (r == 0xffffffff) {
1841 RT2860_GUNLOCK(sc);
1842 return (DDI_INTR_UNCLAIMED);
1843 }
1844 if (r == 0) {
1845 RT2860_GUNLOCK(sc);
1846 return (DDI_INTR_UNCLAIMED);
1847 }
1848
1849 /* acknowledge interrupts */
1850 RT2860_WRITE(sc, RT2860_INT_STATUS, r);
1851
1852 if (r & RT2860_TX_COHERENT)
1853 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1854 "RT2860_TX_COHERENT\n");
1855
1856 if (r & RT2860_RX_COHERENT)
1857 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1858 "RT2860_RX_COHERENT\n");
1859
1860 if (r & RT2860_MAC_INT_2) {
1861 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1862 "RT2860_MAC_INT_2\n");
1863 rt2860_drain_stats_fifo(sc);
1864 }
1865
1866 if (r & RT2860_TX_DONE_INT5) {
1867 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1868 "RT2860_TX_DONE_INT5\n");
1869 rt2860_tx_intr(sc, 5);
1870 }
1871
1872 if (r & RT2860_RX_DONE_INT) {
1873 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1874 "RT2860_RX_INT\n");
1875 sc->sc_rx_pend = 1;
1876 ddi_trigger_softintr(sc->sc_softintr_hdl);
1877 }
1878
1879 if (r & RT2860_TX_DONE_INT4) {
1880 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1881 "RT2860_TX_DONE_INT4\n");
1882 rt2860_tx_intr(sc, 4);
1883 }
1884
1885 if (r & RT2860_TX_DONE_INT3) {
1886 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1887 "RT2860_TX_DONE_INT3\n");
1888 rt2860_tx_intr(sc, 3);
1889 }
1890
1891 if (r & RT2860_TX_DONE_INT2) {
1892 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1893 "RT2860_TX_DONE_INT2\n");
1894 rt2860_tx_intr(sc, 2);
1895 }
1896
1897 if (r & RT2860_TX_DONE_INT1) {
1898 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1899 "RT2860_TX_DONE_INT1\n");
1900 rt2860_tx_intr(sc, 1);
1901 }
1902
1903 if (r & RT2860_TX_DONE_INT0) {
1904 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1905 "RT2860_TX_DONE_INT0\n");
1906 rt2860_tx_intr(sc, 0);
1907 }
1908
1909 if (r & RT2860_MAC_INT_0) {
1910 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1911 "RT2860_MAC_INT_0\n");
1912 struct ieee80211com *ic = &sc->sc_ic;
1913 /* check if protection mode has changed */
1914 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1915 rt2860_updateprot(ic);
1916 sc->sc_ic_flags = ic->ic_flags;
1917 }
1918 }
1919
1920 if (r & RT2860_MAC_INT_3)
1921 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1922 "RT2860_MAC_INT_3\n");
1923
1924 RT2860_GUNLOCK(sc);
1925
1926 return (DDI_INTR_CLAIMED);
1927 }
1928
1929 static void
1930 rt2860_set_region_4(struct rt2860_softc *sc,
1931 uint32_t addr, uint32_t data, int size)
1932 {
1933 for (; size > 0; size--, data++, addr += 4)
1934 ddi_put32((sc)->sc_io_handle,
1935 (uint32_t *)((uintptr_t)(sc)->sc_io_base + addr), data);
1936 }
1937
1938 static int
1939 rt2860_load_microcode(struct rt2860_softc *sc)
1940 {
1941 int ntries;
1942 size_t size;
1943 uint8_t *ucode, *fptr;
1944 uint32_t off, i;
1945
1946 ucode = rt2860_fw_bin;
1947 size = sizeof (rt2860_fw_bin);
1948 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_load_microcode(): "
1949 "The size of ucode is: %x\n", size);
1950
1951 /* set "host program ram write selection" bit */
1952 RT2860_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
1953 /* write microcode image */
1954 fptr = ucode;
1955 off = RT2860_FW_BASE;
1956 for (i = 0; i < size; i++) {
1957 rt2860_mem_write1(sc, off++, *fptr++);
1958 }
1959 /* kick microcontroller unit */
1960 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0);
1961 RT2860_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
1962
1963 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
1964 RT2860_WRITE(sc, RT2860_H2M_MAILBOX, 0);
1965
1966 /* wait until microcontroller is ready */
1967 for (ntries = 0; ntries < 1000; ntries++) {
1968 if (RT2860_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
1969 break;
1970 DELAY(1000);
1971 }
1972 if (ntries == 1000) {
1973 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_load_microcode(): "
1974 "timeout waiting for MCU to initialie\n");
1975 return (ETIMEDOUT);
1976 }
1977
1978 return (0);
1979 }
1980
1981 static void
1982 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
1983 {
1984 RT2860_WRITE(sc, RT2860_MAC_ADDR_DW0,
1985 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
1986 RT2860_WRITE(sc, RT2860_MAC_ADDR_DW1,
1987 addr[4] | addr[5] << 8);
1988 }
1989
1990 /*
1991 * Send a command to the 8051 microcontroller unit.
1992 */
1993 static int
1994 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg)
1995 {
1996 int ntries;
1997
1998 for (ntries = 0; ntries < 100; ntries++) {
1999 if (!(RT2860_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2000 break;
2001 DELAY(2);
2002 }
2003 if (ntries == 100)
2004 return (EIO);
2005
2006 RT2860_WRITE(sc, RT2860_H2M_MAILBOX,
2007 RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg);
2008 RT2860_WRITE(sc, RT2860_HOST_CMD, cmd);
2009
2010 return (RT2860_SUCCESS);
2011 }
2012
2013 /*
2014 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
2015 * We access the BBP through the 8051 microcontroller unit which means that
2016 * the microcode must be loaded first.
2017 */
2018 static uint8_t
2019 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
2020 {
2021 uint32_t val;
2022 int ntries;
2023
2024 for (ntries = 0; ntries < 100; ntries++) {
2025 if (!(RT2860_READ(sc,
2026 RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2027 break;
2028 DELAY(1);
2029 }
2030 if (ntries == 100) {
2031 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_read():"
2032 "could not read from BBP through MCU\n");
2033 return (0);
2034 }
2035
2036 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2037 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
2038
2039 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0);
2040 DELAY(1000);
2041
2042 for (ntries = 0; ntries < 100; ntries++) {
2043 val = RT2860_READ(sc, RT2860_H2M_BBPAGENT);
2044 if (!(val & RT2860_BBP_CSR_KICK))
2045 return (val & 0xff);
2046 DELAY(1);
2047 }
2048 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_read():"
2049 "could not read from BBP through MCU\n");
2050
2051 return (0);
2052 }
2053
2054 static void
2055 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2056 {
2057 int ntries;
2058
2059 for (ntries = 0; ntries < 100; ntries++) {
2060 if (!(RT2860_READ(sc,
2061 RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2062 break;
2063 DELAY(1);
2064 }
2065 if (ntries == 100) {
2066 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_write():"
2067 "could not write to BBP through MCU\n");
2068 return;
2069 }
2070
2071 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2072 RT2860_BBP_CSR_KICK | reg << 8 | val);
2073
2074 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0);
2075 DELAY(1000);
2076 }
2077
2078 static int
2079 rt2860_bbp_init(struct rt2860_softc *sc)
2080 {
2081 int i, ntries;
2082
2083 /* wait for BBP to wake up */
2084 for (ntries = 0; ntries < 20; ntries++) {
2085 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
2086 if (bbp0 != 0 && bbp0 != 0xff)
2087 break;
2088 }
2089 if (ntries == 20) {
2090 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_bbp_init():"
2091 "timeout waiting for BBP to wake up\n");
2092 return (ETIMEDOUT);
2093 }
2094
2095 /* initialize BBP registers to default values */
2096 for (i = 0; i < 12; i++) {
2097 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
2098 rt2860_def_bbp[i].val);
2099 }
2100
2101 /* fix BBP69 and BBP73 for RT2860C */
2102 if (sc->mac_rev == 0x28600100) {
2103 rt2860_mcu_bbp_write(sc, 69, 0x16);
2104 rt2860_mcu_bbp_write(sc, 73, 0x12);
2105 }
2106
2107 return (0);
2108 }
2109
2110 static void
2111 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
2112 {
2113 uint32_t tmp;
2114 int ntries;
2115
2116 for (ntries = 0; ntries < 100; ntries++) {
2117 if (!(RT2860_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
2118 break;
2119 DELAY(1);
2120 }
2121 if (ntries == 100) {
2122 RWN_DEBUG(RT2860_DBG_FW, "rwn: rwn_init()"
2123 "could not write to RF\n");
2124 return;
2125 }
2126
2127 /* RF registers are 24-bit on the RT2860 */
2128 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
2129 (val & 0x3fffff) << 2 | (reg & 3);
2130 RT2860_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
2131 }
2132
2133 static void
2134 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2135 {
2136 uint32_t tmp;
2137
2138 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2139 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2140 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2141 rt2860_mcu_bbp_write(sc, 82, (group == 0) ? 0x62 : 0xf2);
2142
2143 tmp = RT2860_READ(sc, RT2860_TX_BAND_CFG);
2144 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2145 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2146 RT2860_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2147
2148 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2149 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN;
2150 if (group == 0) { /* 2GHz */
2151 tmp |= RT2860_PA_PE_G0_EN | RT2860_LNA_PE_G0_EN;
2152 if (sc->ntxchains > 1)
2153 tmp |= RT2860_PA_PE_G1_EN;
2154 if (sc->nrxchains > 1)
2155 tmp |= RT2860_LNA_PE_G1_EN;
2156 } else { /* 5GHz */
2157 tmp |= RT2860_PA_PE_A0_EN | RT2860_LNA_PE_A0_EN;
2158 if (sc->ntxchains > 1)
2159 tmp |= RT2860_PA_PE_A1_EN;
2160 if (sc->nrxchains > 1)
2161 tmp |= RT2860_LNA_PE_A1_EN;
2162 }
2163 RT2860_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2164
2165 rt2860_mcu_bbp_write(sc, 66, 0x2e + sc->lna[group]);
2166 }
2167 static void
2168 rt2860_set_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
2169 {
2170 struct ieee80211com *ic = &sc->sc_ic;
2171 const struct rfprog *rfprog = rt2860_rf2850;
2172 uint_t i, chan, group;
2173 uint8_t txpow1, txpow2;
2174 uint32_t r2, r3, r4;
2175
2176 chan = ieee80211_chan2ieee(ic, c);
2177 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
2178 RWN_DEBUG(RT2860_DBG_FW, "Unkonwn channel!\n");
2179 return;
2180 }
2181
2182 /* find the settings for this channel (we know it exists) */
2183 for (i = 0; rfprog[i].chan != chan; )
2184 i++;
2185
2186 r2 = rfprog[i].r2;
2187 if (sc->ntxchains == 1)
2188 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2189 if (sc->nrxchains == 1)
2190 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2191 else if (sc->nrxchains == 2)
2192 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2193
2194 /* use Tx power values from EEPROM */
2195 txpow1 = sc->txpow1[i];
2196 txpow2 = sc->txpow2[i];
2197 if (IEEE80211_IS_CHAN_5GHZ(c)) {
2198 txpow1 = txpow1 << 1 | 1;
2199 txpow2 = txpow2 << 1 | 1;
2200 }
2201 r3 = rfprog[i].r3 | txpow1 << 7;
2202 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2203
2204 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2205 rt2860_rf_write(sc, RAL_RF2, r2);
2206 rt2860_rf_write(sc, RAL_RF3, r3);
2207 rt2860_rf_write(sc, RAL_RF4, r4);
2208
2209 DELAY(200);
2210
2211 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2212 rt2860_rf_write(sc, RAL_RF2, r2);
2213 rt2860_rf_write(sc, RAL_RF3, r3 | 1);
2214 rt2860_rf_write(sc, RAL_RF4, r4);
2215
2216 DELAY(200);
2217
2218 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2219 rt2860_rf_write(sc, RAL_RF2, r2);
2220 rt2860_rf_write(sc, RAL_RF3, r3);
2221 rt2860_rf_write(sc, RAL_RF4, r4);
2222
2223 /* 802.11a uses a 16 microseconds short interframe space */
2224 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10;
2225
2226 /* determine channel group */
2227 if (chan <= 14)
2228 group = 0;
2229 else if (chan <= 64)
2230 group = 1;
2231 else if (chan <= 128)
2232 group = 2;
2233 else
2234 group = 3;
2235
2236 /* XXX necessary only when group has changed! */
2237 rt2860_select_chan_group(sc, group);
2238
2239 DELAY(1000);
2240 }
2241
2242 static void
2243 rt2860_updateprot(struct ieee80211com *ic)
2244 {
2245 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
2246 uint32_t tmp;
2247
2248 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
2249 /* setup protection frame rate (MCS code) */
2250 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 0 : 3;
2251
2252 /* CCK frames don't require protection */
2253 RT2860_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
2254
2255 if (ic->ic_flags & IEEE80211_F_USEPROT) {
2256 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2257 tmp |= RT2860_PROT_CTRL_RTS_CTS;
2258 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2259 tmp |= RT2860_PROT_CTRL_CTS;
2260 }
2261 RT2860_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
2262 }
2263
2264 static void
2265 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
2266 {
2267 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
2268 which | (sc->leds & 0x7f));
2269 }
2270
2271 static int
2272 rt2860_init(struct rt2860_softc *sc)
2273 {
2274 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2275 struct ieee80211com *ic;
2276 int i, err, qid, ridx, ntries;
2277 uint8_t bbp1, bbp3;
2278 uint32_t tmp;
2279
2280 ic = &sc->sc_ic;
2281
2282 rt2860_stop(sc);
2283 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2284 tmp &= 0xff0;
2285 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2286
2287 RT2860_WRITE(sc, RT2860_WPDMA_RST_IDX, 0xffffffff);
2288
2289 /* PBF hardware reset */
2290 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
2291 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
2292
2293 if (!(sc->sc_flags & RT2860_FWLOADED)) {
2294 if ((err = rt2860_load_microcode(sc)) != 0) {
2295 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_init(): "
2296 "could not load 8051 microcode\n");
2297 rt2860_stop(sc);
2298 return (err);
2299 }
2300 RT2860_GLOCK(sc);
2301 sc->sc_flags |= RT2860_FWLOADED;
2302 RT2860_GUNLOCK(sc);
2303 }
2304
2305 rt2860_set_macaddr(sc, ic->ic_macaddr);
2306
2307 /* init Tx power for all Tx rates (from EEPROM) */
2308 for (ridx = 0; ridx < 5; ridx++) {
2309 if (sc->txpow20mhz[ridx] == 0xffffffff)
2310 continue;
2311 RT2860_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
2312 }
2313
2314 for (ntries = 0; ntries < 100; ntries++) {
2315 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2316 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2317 break;
2318 DELAY(1000);
2319 }
2320 if (ntries == 100) {
2321 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_init():"
2322 "timeout waiting for DMA engine\n");
2323 rt2860_stop(sc);
2324 return (ETIMEDOUT);
2325 }
2326 tmp &= 0xff0;
2327 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2328
2329 /* reset Rx ring and all 6 Tx rings */
2330 RT2860_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
2331
2332 /* PBF hardware reset */
2333 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
2334 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
2335
2336 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2337 RT2860_BBP_HRST | RT2860_MAC_SRST);
2338 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
2339
2340 for (i = 0; i < N(rt2860_def_mac); i++)
2341 RT2860_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
2342
2343 /* wait while MAC is busy */
2344 for (ntries = 0; ntries < 100; ntries++) {
2345 if (!(RT2860_READ(sc, RT2860_MAC_STATUS_REG) &
2346 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
2347 break;
2348 DELAY(1000);
2349 }
2350 if (ntries == 100) {
2351 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_init():"
2352 "timeout waiting for MAC\n");
2353 rt2860_stop(sc);
2354 return (ETIMEDOUT);
2355 }
2356
2357 /* clear Host to MCU mailbox */
2358 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
2359 RT2860_WRITE(sc, RT2860_H2M_MAILBOX, 0);
2360
2361 if ((err = rt2860_bbp_init(sc)) != 0) {
2362 rt2860_stop(sc);
2363 return (err);
2364 }
2365
2366 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
2367 for (qid = 0; qid < 6; qid++) {
2368 RT2860_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
2369 RT2860_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
2370 RT2860_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
2371 }
2372
2373 /* init Rx ring */
2374 RT2860_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
2375 RT2860_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
2376 RT2860_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
2377
2378 /* setup maximum buffer sizes */
2379 RT2860_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
2380 (sc->sc_dmabuf_size - sizeof (struct rt2860_rxwi) - 2));
2381
2382 for (ntries = 0; ntries < 100; ntries++) {
2383 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2384 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2385 break;
2386 DELAY(1000);
2387 }
2388 if (ntries == 100) {
2389 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_init():"
2390 "timeout waiting for DMA engine\n");
2391 rt2860_stop(sc);
2392 return (ETIMEDOUT);
2393 }
2394 tmp &= 0xff0;
2395 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2396
2397 /* disable interrupts mitigation */
2398 RT2860_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
2399
2400 /* write vendor-specific BBP values (from EEPROM) */
2401 for (i = 0; i < 8; i++) {
2402 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
2403 continue;
2404 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
2405 }
2406
2407 /* send LEDs operating mode to microcontroller */
2408 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]);
2409 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]);
2410 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]);
2411
2412 /* disable non-existing Rx chains */
2413 bbp3 = rt2860_mcu_bbp_read(sc, 3);
2414 bbp3 &= ~(1 << 3 | 1 << 4);
2415 if (sc->nrxchains == 2)
2416 bbp3 |= 1 << 3;
2417 else if (sc->nrxchains == 3)
2418 bbp3 |= 1 << 4;
2419 rt2860_mcu_bbp_write(sc, 3, bbp3);
2420
2421 /* disable non-existing Tx chains */
2422 bbp1 = rt2860_mcu_bbp_read(sc, 1);
2423 if (sc->ntxchains == 1)
2424 bbp1 &= ~(1 << 3 | 1 << 4);
2425 rt2860_mcu_bbp_write(sc, 1, bbp1);
2426
2427 /* select default channel */
2428 rt2860_set_chan(sc, ic->ic_curchan);
2429
2430 /* XXX not clear what the following 8051 command does.. */
2431 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BOOT, 0);
2432
2433 /* set RTS threshold */
2434 tmp = RT2860_READ(sc, RT2860_TX_RTS_CFG);
2435 tmp &= ~0xffff00;
2436 tmp |= ic->ic_rtsthreshold << 8;
2437
2438 /* setup initial protection mode */
2439 sc->sc_ic_flags = ic->ic_flags;
2440 rt2860_updateprot(ic);
2441
2442 /* enable Tx/Rx DMA engine */
2443 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
2444 for (ntries = 0; ntries < 200; ntries++) {
2445 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2446 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2447 break;
2448 DELAY(1000);
2449 }
2450 if (ntries == 200) {
2451 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_int():"
2452 "timeout waiting for DMA engine\n");
2453 rt2860_stop(sc);
2454 return (ETIMEDOUT);
2455 }
2456
2457 DELAY(50);
2458
2459 tmp |= RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
2460 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
2461 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
2462
2463 /* turn radio LED on */
2464 rt2860_set_leds(sc, RT2860_LED_RADIO);
2465
2466 /* set Rx filter */
2467 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
2468 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2469 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
2470 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
2471 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
2472 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
2473 if (ic->ic_opmode == IEEE80211_M_STA)
2474 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
2475 }
2476 RT2860_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
2477
2478 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2479 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
2480
2481 /* clear pending interrupts */
2482 RT2860_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
2483 /* enable interrupts */
2484 RT2860_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
2485
2486 if (sc->sc_flags & RT2860_ADVANCED_PS)
2487 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel);
2488
2489 return (DDI_SUCCESS);
2490 }
2491
2492 static int
2493 rt2860_quiesce(dev_info_t *dip)
2494 {
2495 struct rt2860_softc *sc;
2496
2497 sc = ddi_get_soft_state(rt2860_soft_state_p, ddi_get_instance(dip));
2498 if (sc == NULL)
2499 return (DDI_FAILURE);
2500
2501 #ifdef DEBUG
2502 rt2860_dbg_flags = 0;
2503 #endif
2504
2505 /*
2506 * No more blocking is allowed while we are in quiesce(9E) entry point
2507 */
2508 sc->sc_flags |= RT2860_F_QUIESCE;
2509
2510 /*
2511 * Disable and mask all interrupts
2512 */
2513 rt2860_stop(sc);
2514 return (DDI_SUCCESS);
2515 }
2516
2517 static void
2518 rt2860_stop(struct rt2860_softc *sc)
2519 {
2520 int qid;
2521 uint32_t tmp;
2522
2523 /* by pass if it's quiesced */
2524 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2525 RT2860_GLOCK(sc);
2526 if (sc->sc_flags == RT2860_F_RUNNING)
2527 rt2860_set_leds(sc, 0); /* turn all LEDs off */
2528 sc->sc_tx_timer = 0;
2529 /* by pass if it's quiesced */
2530 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2531 RT2860_GUNLOCK(sc);
2532
2533 /* clear RX WCID search table */
2534 rt2860_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
2535 /* clear pairwise key table */
2536 rt2860_set_region_4(sc, RT2860_PKEY(0), 0, 2048);
2537 /* clear IV/EIV table */
2538 rt2860_set_region_4(sc, RT2860_IVEIV(0), 0, 512);
2539 /* clear WCID attribute table */
2540 rt2860_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 256);
2541 /* clear shared key table */
2542 rt2860_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
2543 /* clear shared key mode */
2544 rt2860_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
2545
2546 /* disable interrupts */
2547 RT2860_WRITE(sc, RT2860_INT_MASK, 0);
2548
2549 /* disable Rx */
2550 tmp = RT2860_READ(sc, RT2860_MAC_SYS_CTRL);
2551 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
2552 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
2553
2554 /* reset adapter */
2555 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2556 RT2860_BBP_HRST | RT2860_MAC_SRST);
2557 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
2558
2559 /* reset Tx and Rx rings (and reclaim TXWIs) */
2560 for (qid = 0; qid < 6; qid++)
2561 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
2562 rt2860_reset_rx_ring(sc, &sc->rxq);
2563
2564 /* by pass if it's quiesced */
2565 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2566 RT2860_GLOCK(sc);
2567 sc->sc_flags &= ~RT2860_UPD_BEACON;
2568 /* by pass if it's quiesced */
2569 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2570 RT2860_GUNLOCK(sc);
2571 }
2572
2573 static int
2574 rt2860_m_start(void *arg)
2575 {
2576 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2577 struct ieee80211com *ic = &sc->sc_ic;
2578 int err;
2579
2580 err = rt2860_init(sc);
2581 if (err != DDI_SUCCESS) {
2582 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_m_start():"
2583 "Hardware initialization failed\n");
2584 goto fail1;
2585 }
2586
2587 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2588
2589 RT2860_GLOCK(sc);
2590 sc->sc_flags |= RT2860_F_RUNNING;
2591 RT2860_GUNLOCK(sc);
2592
2593 return (err);
2594 fail1:
2595 rt2860_stop(sc);
2596 return (err);
2597 }
2598
2599 static void
2600 rt2860_m_stop(void *arg)
2601 {
2602 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2603
2604 (void) rt2860_stop(sc);
2605
2606 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2607
2608 RT2860_GLOCK(sc);
2609 sc->sc_flags &= ~RT2860_F_RUNNING;
2610 RT2860_GUNLOCK(sc);
2611 }
2612
2613 static void
2614 rt2860_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2615 {
2616 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2617 struct ieee80211com *ic = &sc->sc_ic;
2618 int err;
2619
2620 err = ieee80211_ioctl(ic, wq, mp);
2621 RT2860_GLOCK(sc);
2622 if (err == ENETRESET) {
2623 if (ic->ic_des_esslen) {
2624 if (RT2860_IS_RUNNING(sc)) {
2625 RT2860_GUNLOCK(sc);
2626 (void) rt2860_init(sc);
2627 (void) ieee80211_new_state(ic,
2628 IEEE80211_S_SCAN, -1);
2629 RT2860_GLOCK(sc);
2630 }
2631 }
2632 }
2633 RT2860_GUNLOCK(sc);
2634 }
2635
2636 /*
2637 * Call back function for get/set proporty
2638 */
2639 static int
2640 rt2860_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2641 uint_t wldp_length, void *wldp_buf)
2642 {
2643 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2644 int err = 0;
2645
2646 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2647 wldp_length, wldp_buf);
2648
2649 return (err);
2650 }
2651
2652 static void
2653 rt2860_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2654 mac_prop_info_handle_t prh)
2655 {
2656 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2657
2658 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
2659 }
2660
2661 static int
2662 rt2860_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2663 uint_t wldp_length, const void *wldp_buf)
2664 {
2665 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2666 ieee80211com_t *ic = &sc->sc_ic;
2667 int err;
2668
2669 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
2670 wldp_buf);
2671 RT2860_GLOCK(sc);
2672 if (err == ENETRESET) {
2673 if (ic->ic_des_esslen) {
2674 if (RT2860_IS_RUNNING(sc)) {
2675 RT2860_GUNLOCK(sc);
2676 (void) rt2860_init(sc);
2677 (void) ieee80211_new_state(ic,
2678 IEEE80211_S_SCAN, -1);
2679 RT2860_GLOCK(sc);
2680 }
2681 }
2682 err = 0;
2683 }
2684 RT2860_GUNLOCK(sc);
2685 return (err);
2686 }
2687
2688 static mblk_t *
2689 rt2860_m_tx(void *arg, mblk_t *mp)
2690 {
2691 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2692 struct ieee80211com *ic = &sc->sc_ic;
2693 mblk_t *next;
2694
2695 if (RT2860_IS_SUSPEND(sc)) {
2696 freemsgchain(mp);
2697 return (NULL);
2698 }
2699
2700 /*
2701 * No data frames go out unless we're associated; this
2702 * should not happen as the 802.11 layer does not enable
2703 * the xmit queue until we enter the RUN state.
2704 */
2705 if (ic->ic_state != IEEE80211_S_RUN) {
2706 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_tx_data(): "
2707 "discard, state %u\n", ic->ic_state);
2708 freemsgchain(mp);
2709 return (NULL);
2710 }
2711
2712 while (mp != NULL) {
2713 next = mp->b_next;
2714 mp->b_next = NULL;
2715 if (rt2860_send(ic, mp, IEEE80211_FC0_TYPE_DATA) !=
2716 DDI_SUCCESS) {
2717 mp->b_next = next;
2718 break;
2719 }
2720 mp = next;
2721 }
2722 return (mp);
2723 }
2724
2725 /*ARGSUSED*/
2726 static int
2727 rt2860_m_unicst(void *arg, const uint8_t *macaddr)
2728 {
2729 return (ENOTSUP);
2730 }
2731
2732 /*ARGSUSED*/
2733 static int
2734 rt2860_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
2735 {
2736 return (ENOTSUP);
2737 }
2738
2739 /*ARGSUSED*/
2740 static int
2741 rt2860_m_promisc(void *arg, boolean_t on)
2742 {
2743 return (0);
2744 }
2745
2746 static int
2747 rt2860_m_stat(void *arg, uint_t stat, uint64_t *val)
2748 {
2749 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2750 ieee80211com_t *ic = &sc->sc_ic;
2751 ieee80211_node_t *ni = ic->ic_bss;
2752 struct ieee80211_rateset *rs = &ni->in_rates;
2753
2754 RT2860_GLOCK(sc);
2755 switch (stat) {
2756 case MAC_STAT_IFSPEED:
2757 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
2758 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
2759 : ic->ic_fixed_rate) / 2 * 1000000;
2760 break;
2761 case MAC_STAT_NOXMTBUF:
2762 *val = sc->sc_tx_nobuf;
2763 break;
2764 case MAC_STAT_NORCVBUF:
2765 *val = sc->sc_rx_nobuf;
2766 break;
2767 case MAC_STAT_IERRORS:
2768 *val = sc->sc_rx_err;
2769 break;
2770 case MAC_STAT_RBYTES:
2771 *val = ic->ic_stats.is_rx_bytes;
2772 break;
2773 case MAC_STAT_IPACKETS:
2774 *val = ic->ic_stats.is_rx_frags;
2775 break;
2776 case MAC_STAT_OBYTES:
2777 *val = ic->ic_stats.is_tx_bytes;
2778 break;
2779 case MAC_STAT_OPACKETS:
2780 *val = ic->ic_stats.is_tx_frags;
2781 break;
2782 case MAC_STAT_OERRORS:
2783 case WIFI_STAT_TX_FAILED:
2784 *val = sc->sc_tx_err;
2785 break;
2786 case WIFI_STAT_TX_RETRANS:
2787 *val = sc->sc_tx_retries;
2788 break;
2789 case WIFI_STAT_FCS_ERRORS:
2790 case WIFI_STAT_WEP_ERRORS:
2791 case WIFI_STAT_TX_FRAGS:
2792 case WIFI_STAT_MCAST_TX:
2793 case WIFI_STAT_RTS_SUCCESS:
2794 case WIFI_STAT_RTS_FAILURE:
2795 case WIFI_STAT_ACK_FAILURE:
2796 case WIFI_STAT_RX_FRAGS:
2797 case WIFI_STAT_MCAST_RX:
2798 case WIFI_STAT_RX_DUPS:
2799 RT2860_GUNLOCK(sc);
2800 return (ieee80211_stat(ic, stat, val));
2801 default:
2802 RT2860_GUNLOCK(sc);
2803 return (ENOTSUP);
2804 }
2805 RT2860_GUNLOCK(sc);
2806
2807 return (0);
2808 }
2809
2810 static int
2811 rt2860_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2812 {
2813 struct rt2860_softc *sc;
2814 struct ieee80211com *ic;
2815 int i, err, qid, ntries, instance;
2816 uint8_t cachelsz;
2817 uint16_t command, vendor_id, device_id;
2818 char strbuf[32];
2819 wifi_data_t wd = { 0 };
2820 mac_register_t *macp;
2821
2822 switch (cmd) {
2823 case DDI_ATTACH:
2824 break;
2825 case DDI_RESUME:
2826 sc = ddi_get_soft_state(rt2860_soft_state_p,
2827 ddi_get_instance(devinfo));
2828 ASSERT(sc != NULL);
2829 RT2860_GLOCK(sc);
2830 sc->sc_flags &= ~RT2860_F_SUSPEND;
2831 RT2860_GUNLOCK(sc);
2832 if (RT2860_IS_RUNNING(sc))
2833 (void) rt2860_init(sc);
2834 RWN_DEBUG(RT2860_DBG_RESUME, "rwn: rt2860_attach(): "
2835 "resume now\n");
2836 return (DDI_SUCCESS);
2837 default:
2838 return (DDI_FAILURE);
2839 }
2840
2841 instance = ddi_get_instance(devinfo);
2842
2843 err = ddi_soft_state_zalloc(rt2860_soft_state_p, instance);
2844 if (err != DDI_SUCCESS) {
2845 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2846 "unable to alloc soft_state_p\n");
2847 return (err);
2848 }
2849
2850 sc = ddi_get_soft_state(rt2860_soft_state_p, instance);
2851 ic = (ieee80211com_t *)&sc->sc_ic;
2852 sc->sc_dev = devinfo;
2853
2854 /* pci configuration */
2855 err = ddi_regs_map_setup(devinfo, 0, &sc->sc_cfg_base, 0, 0,
2856 &rwn_csr_accattr, &sc->sc_cfg_handle);
2857 if (err != DDI_SUCCESS) {
2858 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2859 "ddi_regs_map_setup() failed");
2860 goto fail1;
2861 }
2862
2863 cachelsz = ddi_get8(sc->sc_cfg_handle,
2864 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
2865 if (cachelsz == 0)
2866 cachelsz = 0x10;
2867 sc->sc_cachelsz = cachelsz << 2;
2868 sc->sc_dmabuf_size = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
2869
2870 vendor_id = ddi_get16(sc->sc_cfg_handle,
2871 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_VENID));
2872 device_id = ddi_get16(sc->sc_cfg_handle,
2873 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_DEVID));
2874 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2875 "vendor 0x%x, device id 0x%x, cache size %d\n",
2876 vendor_id, device_id, cachelsz);
2877
2878 /*
2879 * Enable response to memory space accesses,
2880 * and enabe bus master.
2881 */
2882 command = PCI_COMM_MAE | PCI_COMM_ME;
2883 ddi_put16(sc->sc_cfg_handle,
2884 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM),
2885 command);
2886 ddi_put8(sc->sc_cfg_handle,
2887 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8);
2888 ddi_put8(sc->sc_cfg_handle,
2889 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10);
2890
2891 /* pci i/o space */
2892 err = ddi_regs_map_setup(devinfo, 1,
2893 &sc->sc_io_base, 0, 0, &rwn_csr_accattr, &sc->sc_io_handle);
2894 if (err != DDI_SUCCESS) {
2895 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2896 "ddi_regs_map_setup() failed");
2897 goto fail2;
2898 }
2899 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2900 "PCI configuration is done successfully\n");
2901
2902 sc->amrr.amrr_min_success_threshold = 1;
2903 sc->amrr.amrr_max_success_threshold = 15;
2904
2905 /* wait for NIC to initialize */
2906 for (ntries = 0; ntries < 100; ntries++) {
2907 sc->mac_rev = RT2860_READ(sc, RT2860_ASIC_VER_ID);
2908 if (sc->mac_rev != 0 && sc->mac_rev != 0xffffffff)
2909 break;
2910 DELAY(10);
2911 }
2912 if (ntries == 100) {
2913 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2914 "timeout waiting for NIC initialize\n");
2915 return (DDI_FAILURE);
2916 }
2917
2918 if ((sc->mac_rev >> 16) != 0x2860 &&
2919 (device_id == PRODUCT_RALINK_RT2890 ||
2920 device_id == PRODUCT_RALINK_RT2790 ||
2921 device_id == PRODUCT_AWT_RT2890))
2922 sc->sc_flags |= RT2860_ADVANCED_PS;
2923
2924 /* retrieve RF rev. no and various other things from EEPROM */
2925 (void) rt2860_read_eeprom(sc);
2926 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2927 "MAC/BBP RT%X (rev 0x%04X), RF %s (%dT%dR)\n",
2928 sc->mac_rev >> 16, sc->mac_rev & 0xffff,
2929 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains);
2930
2931 /*
2932 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
2933 */
2934 for (qid = 0; qid < 6; qid++) {
2935 if ((err = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
2936 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2937 "could not allocate Tx ring %d\n", qid);
2938 goto fail3;
2939 }
2940 }
2941
2942 if ((err = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
2943 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2944 "could not allocte Rx ring\n");
2945 goto fail4;
2946 }
2947
2948 if ((err = rt2860_alloc_tx_pool(sc)) != 0) {
2949 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2950 "could not allocte Tx pool\n");
2951 goto fail5;
2952 }
2953
2954 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
2955 mutex_init(&sc->sc_txlock, NULL, MUTEX_DRIVER, NULL);
2956 mutex_init(&sc->sc_rxlock, NULL, MUTEX_DRIVER, NULL);
2957
2958 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
2959 sc->mgtqid = (sc->mac_rev == 0x28600100) ? EDCA_AC_VO : 5;
2960 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach():"
2961 "mgtqid = %x\n", sc->mgtqid);
2962
2963 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
2964 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
2965 ic->ic_state = IEEE80211_S_INIT;
2966
2967 /* set device capabilities */
2968 ic->ic_caps =
2969 IEEE80211_C_TXPMGT | /* tx power management */
2970 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
2971 IEEE80211_C_SHSLOT; /* short slot time supported */
2972
2973 /* WPA/WPA2 support */
2974 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
2975
2976 /* set supported .11b and .11g rates */
2977 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2860_rateset_11b;
2978 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2860_rateset_11g;
2979
2980 /* set supported .11b and .11g channels (1 through 14) */
2981 for (i = 1; i <= 14; i++) {
2982 ic->ic_sup_channels[i].ich_freq =
2983 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
2984 ic->ic_sup_channels[i].ich_flags =
2985 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
2986 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
2987 }
2988
2989 ic->ic_maxrssi = 63;
2990 ic->ic_xmit = rt2860_send;
2991
2992 ieee80211_attach(ic);
2993
2994 /* register WPA door */
2995 ieee80211_register_door(ic, ddi_driver_name(devinfo),
2996 ddi_get_instance(devinfo));
2997
2998 /* override state transition machine */
2999 sc->sc_newstate = ic->ic_newstate;
3000 ic->ic_newstate = rt2860_newstate;
3001 ieee80211_media_init(ic);
3002 ic->ic_def_txkey = 0;
3003
3004 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW,
3005 &sc->sc_softintr_hdl, NULL, 0, rt2860_softintr, (caddr_t)sc);
3006 if (err != DDI_SUCCESS) {
3007 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3008 "ddi_add_softintr() failed");
3009 goto fail8;
3010 }
3011
3012 err = ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock);
3013 if (err != DDI_SUCCESS) {
3014 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3015 "Can not get iblock cookie for INT\n");
3016 goto fail7;
3017 }
3018
3019 err = ddi_add_intr(devinfo, 0, NULL, NULL, rt2860_intr, (caddr_t)sc);
3020 if (err != DDI_SUCCESS) {
3021 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3022 "unable to add device interrupt handler\n");
3023 goto fail7;
3024 }
3025
3026 /*
3027 * Provide initial settings for the WiFi plugin; whenever this
3028 * information changes, we need to call mac_plugindata_update()
3029 */
3030 wd.wd_opmode = ic->ic_opmode;
3031 wd.wd_secalloc = WIFI_SEC_NONE;
3032 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
3033
3034 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
3035 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3036 "MAC version mismatch\n");
3037 goto fail9;
3038 }
3039
3040 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
3041 macp->m_driver = sc;
3042 macp->m_dip = devinfo;
3043 macp->m_src_addr = ic->ic_macaddr;
3044 macp->m_callbacks = &rt2860_m_callbacks;
3045 macp->m_min_sdu = 0;
3046 macp->m_max_sdu = IEEE80211_MTU;
3047 macp->m_pdata = &wd;
3048 macp->m_pdata_size = sizeof (wd);
3049
3050 err = mac_register(macp, &ic->ic_mach);
3051 mac_free(macp);
3052 if (err != 0) {
3053 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3054 "mac_register err %x\n", err);
3055 goto fail9;
3056 }
3057
3058 /*
3059 * Create minor node of type DDI_NT_NET_WIFI
3060 */
3061 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
3062 "rwn", instance);
3063 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
3064 instance + 1, DDI_NT_NET_WIFI, 0);
3065
3066 /*
3067 * Notify link is down now
3068 */
3069 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
3070
3071 sc->sc_flags &= ~RT2860_F_RUNNING;
3072
3073 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach() successfully.\n");
3074 return (DDI_SUCCESS);
3075 fail9:
3076 ddi_remove_softintr(sc->sc_softintr_hdl);
3077 fail8:
3078 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
3079 fail7:
3080 mutex_destroy(&sc->sc_genlock);
3081 mutex_destroy(&sc->sc_txlock);
3082 mutex_destroy(&sc->sc_rxlock);
3083 fail6:
3084 rt2860_free_tx_pool(sc);
3085 fail5:
3086 rt2860_free_rx_ring(sc, &sc->rxq);
3087 fail4:
3088 while (--qid >= 0)
3089 rt2860_free_tx_ring(sc, &sc->txq[qid]);
3090 fail3:
3091 ddi_regs_map_free(&sc->sc_io_handle);
3092 fail2:
3093 ddi_regs_map_free(&sc->sc_cfg_handle);
3094 fail1:
3095 return (err);
3096 }
3097
3098 static int
3099 rt2860_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
3100 {
3101 struct rt2860_softc *sc;
3102 int qid;
3103
3104 sc = ddi_get_soft_state(rt2860_soft_state_p, ddi_get_instance(devinfo));
3105
3106 switch (cmd) {
3107 case DDI_DETACH:
3108 break;
3109 case DDI_SUSPEND:
3110 if (RT2860_IS_RUNNING(sc))
3111 rt2860_stop(sc);
3112 RT2860_GLOCK(sc);
3113 sc->sc_flags &= ~RT2860_FWLOADED;
3114 sc->sc_flags |= RT2860_F_SUSPEND;
3115 RT2860_GUNLOCK(sc);
3116 RWN_DEBUG(RT2860_DBG_RESUME, "rwn: rt2860_detach(): "
3117 "suspend now\n");
3118 return (DDI_SUCCESS);
3119 default:
3120 return (DDI_FAILURE);
3121 }
3122
3123 if (mac_disable(sc->sc_ic.ic_mach) != 0)
3124 return (DDI_FAILURE);
3125
3126 rt2860_stop(sc);
3127
3128 /*
3129 * Unregister from the MAC layer subsystem
3130 */
3131 (void) mac_unregister(sc->sc_ic.ic_mach);
3132
3133 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
3134 ddi_remove_softintr(sc->sc_softintr_hdl);
3135
3136 /*
3137 * detach ieee80211 layer
3138 */
3139 ieee80211_detach(&sc->sc_ic);
3140
3141 rt2860_free_tx_pool(sc);
3142 rt2860_free_rx_ring(sc, &sc->rxq);
3143 for (qid = 0; qid < 6; qid++)
3144 rt2860_free_tx_ring(sc, &sc->txq[qid]);
3145
3146 ddi_regs_map_free(&sc->sc_io_handle);
3147
3148 mutex_destroy(&sc->sc_genlock);
3149 mutex_destroy(&sc->sc_txlock);
3150 mutex_destroy(&sc->sc_rxlock);
3151
3152 ddi_remove_minor_node(devinfo, NULL);
3153 ddi_soft_state_free(rt2860_soft_state_p, ddi_get_instance(devinfo));
3154
3155 return (DDI_SUCCESS);
3156 }
3157
3158 int
3159 _info(struct modinfo *modinfop)
3160 {
3161 return (mod_info(&modlinkage, modinfop));
3162 }
3163
3164 int
3165 _init(void)
3166 {
3167 int status;
3168
3169 status = ddi_soft_state_init(&rt2860_soft_state_p,
3170 sizeof (struct rt2860_softc), 1);
3171 if (status != 0)
3172 return (status);
3173
3174 mac_init_ops(&rwn_dev_ops, "rwn");
3175 status = mod_install(&modlinkage);
3176 if (status != 0) {
3177 mac_fini_ops(&rwn_dev_ops);
3178 ddi_soft_state_fini(&rt2860_soft_state_p);
3179 }
3180 return (status);
3181 }
3182
3183 int
3184 _fini(void)
3185 {
3186 int status;
3187
3188 status = mod_remove(&modlinkage);
3189 if (status == 0) {
3190 mac_fini_ops(&rwn_dev_ops);
3191 ddi_soft_state_fini(&rt2860_soft_state_p);
3192 }
3193 return (status);
3194 }