Print this page
7127 remove -Wno-missing-braces from Makefile.uts
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/rwd/rt2661.c
+++ new/usr/src/uts/common/io/rwd/rt2661.c
1 1 /*
2 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 3 * Use is subject to license terms.
4 4 */
5 5
6 6 /*
7 7 * Copyright (c) 2006
8 8 * Damien Bergamini <damien.bergamini@free.fr>
9 9 *
10 10 * Permission to use, copy, modify, and distribute this software for any
11 11 * purpose with or without fee is hereby granted, provided that the above
12 12 * copyright notice and this permission notice appear in all copies.
13 13 *
14 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 21 */
22 22
23 23 /*
24 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver
25 25 * http://www.ralinktech.com/
26 26 */
27 27
28 28 #include <sys/types.h>
29 29 #include <sys/byteorder.h>
30 30 #include <sys/conf.h>
31 31 #include <sys/cmn_err.h>
32 32 #include <sys/stat.h>
33 33 #include <sys/ddi.h>
34 34 #include <sys/sunddi.h>
35 35 #include <sys/strsubr.h>
36 36 #include <sys/ethernet.h>
37 37 #include <inet/common.h>
38 38 #include <inet/nd.h>
39 39 #include <inet/mi.h>
40 40 #include <sys/note.h>
41 41 #include <sys/stream.h>
42 42 #include <sys/strsun.h>
43 43 #include <sys/modctl.h>
44 44 #include <sys/devops.h>
45 45 #include <sys/dlpi.h>
46 46 #include <sys/mac_provider.h>
47 47 #include <sys/mac_wifi.h>
48 48 #include <sys/net80211.h>
49 49 #include <sys/net80211_proto.h>
50 50 #include <sys/varargs.h>
51 51 #include <sys/policy.h>
52 52 #include <sys/pci.h>
53 53 #include <sys/crypto/common.h>
54 54 #include <sys/crypto/api.h>
55 55 #include <inet/wifi_ioctl.h>
56 56
57 57 #include "rt2661_reg.h"
58 58 #include "rt2661_var.h"
59 59 #include "rt2661_ucode.h"
60 60
61 61 #define RT2661_DBG_80211 (1 << 0)
62 62 #define RT2661_DBG_DMA (1 << 1)
63 63 #define RT2661_DBG_EEPROM (1 << 2)
64 64 #define RT2661_DBG_FW (1 << 3)
65 65 #define RT2661_DBG_HW (1 << 4)
66 66 #define RT2661_DBG_INTR (1 << 5)
67 67 #define RT2661_DBG_RX (1 << 6)
68 68 #define RT2661_DBG_SCAN (1 << 7)
69 69 #define RT2661_DBG_TX (1 << 8)
70 70 #define RT2661_DBG_RADIO (1 << 9)
71 71 #define RT2661_DBG_RESUME (1 << 10)
72 72 #define RT2661_DBG_MSG (1 << 11)
73 73
74 74 uint32_t rt2661_dbg_flags = 0;
75 75
76 76 #ifdef DEBUG
77 77 #define RWD_DEBUG \
78 78 rt2661_debug
79 79 #else
80 80 #define RWD_DEBUG
81 81 #endif
82 82
83 83 static void *rt2661_soft_state_p = NULL;
84 84
85 85 static const uint8_t *ucode = NULL;
86 86 int usize;
87 87
88 88 static const struct {
89 89 uint32_t reg;
90 90 uint32_t val;
91 91 } rt2661_def_mac[] = {
92 92 RT2661_DEF_MAC
93 93 };
94 94
95 95 static const struct {
96 96 uint8_t reg;
97 97 uint8_t val;
98 98 } rt2661_def_bbp[] = {
99 99 RT2661_DEF_BBP
100 100 };
101 101
102 102 static const struct rfprog {
103 103 uint8_t chan;
104 104 uint32_t r1, r2, r3, r4;
105 105 } rt2661_rf5225_1[] = {
106 106 RT2661_RF5225_1
107 107 }, rt2661_rf5225_2[] = {
108 108 RT2661_RF5225_2
109 109 };
110 110
111 111 /*
112 112 * PIO access attributes for registers
113 113 */
114 114 static ddi_device_acc_attr_t rt2661_csr_accattr = {
115 115 DDI_DEVICE_ATTR_V0,
116 116 DDI_STRUCTURE_LE_ACC,
117 117 DDI_STRICTORDER_ACC
118 118 };
119 119
120 120 /*
121 121 * DMA access attributes for descriptors: NOT to be byte swapped.
122 122 */
123 123 static ddi_device_acc_attr_t rt2661_desc_accattr = {
124 124 DDI_DEVICE_ATTR_V0,
125 125 DDI_STRUCTURE_LE_ACC,
126 126 DDI_STRICTORDER_ACC
127 127 };
128 128
129 129 static ddi_device_acc_attr_t rt2661_buf_accattr = {
130 130 DDI_DEVICE_ATTR_V0,
131 131 DDI_NEVERSWAP_ACC,
132 132 DDI_STRICTORDER_ACC,
133 133 DDI_DEFAULT_ACC
134 134 };
135 135
136 136 /*
137 137 * Describes the chip's DMA engine
138 138 */
139 139 static ddi_dma_attr_t rt2661_dma_attr = {
140 140 DMA_ATTR_V0, /* dma_attr version */
141 141 0x0, /* dma_attr_addr_lo */
142 142 0xffffffffU, /* dma_attr_addr_hi */
143 143 0xffffffffU, /* dma_attr_count_max */
144 144 1, /* dma_attr_align */
145 145 0x00000fff, /* dma_attr_burstsizes */
146 146 1, /* dma_attr_minxfer */
147 147 0xffffffffU, /* dma_attr_maxxfer */
148 148 0xffffffffU, /* dma_attr_seg */
149 149 1, /* dma_attr_sgllen */
150 150 1, /* dma_attr_granular */
151 151 0 /* dma_attr_flags */
152 152 };
153 153
154 154 static const struct ieee80211_rateset rt2661_rateset_11b =
155 155 { 4, { 2, 4, 11, 22 } };
156 156
157 157 static const struct ieee80211_rateset rt2661_rateset_11g =
158 158 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
159 159
160 160
161 161 static const char *rt2661_get_rf(int);
162 162
163 163 static void rt2661_read_eeprom(struct rt2661_softc *);
164 164 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t);
165 165 static int rt2661_load_microcode(struct rt2661_softc *,
166 166 const uint8_t *, int);
167 167
168 168 static int rt2661_alloc_dma_mem(dev_info_t *, ddi_dma_attr_t *, size_t,
169 169 ddi_device_acc_attr_t *, uint_t, uint_t, struct dma_area *);
170 170 static void rt2661_free_dma_mem(struct dma_area *);
171 171 static int rt2661_alloc_tx_ring(struct rt2661_softc *,
172 172 struct rt2661_tx_ring *, int);
173 173 static void rt2661_reset_tx_ring(struct rt2661_softc *,
174 174 struct rt2661_tx_ring *);
175 175 static void rt2661_free_tx_ring(struct rt2661_softc *,
176 176 struct rt2661_tx_ring *);
177 177 static int rt2661_alloc_rx_ring(struct rt2661_softc *,
178 178 struct rt2661_rx_ring *, int);
179 179 static void rt2661_reset_rx_ring(struct rt2661_softc *,
180 180 struct rt2661_rx_ring *);
181 181 static void rt2661_free_rx_ring(struct rt2661_softc *,
182 182 struct rt2661_rx_ring *);
183 183 static void rt2661_tx_dma_intr(struct rt2661_softc *,
184 184 struct rt2661_tx_ring *);
185 185 static void rt2661_tx_intr(struct rt2661_softc *);
186 186 static void rt2661_rx_intr(struct rt2661_softc *);
187 187 static uint_t rt2661_softintr(caddr_t, caddr_t);
188 188 static void rt2661_mcu_wakeup(struct rt2661_softc *);
189 189 static void rt2661_mcu_cmd_intr(struct rt2661_softc *);
190 190 static uint_t rt2661_intr(caddr_t, caddr_t);
191 191
192 192 static uint16_t rt2661_txtime(int, int, uint32_t);
193 193 static int rt2661_ack_rate(struct ieee80211com *, int);
194 194 static uint8_t rt2661_plcp_signal(int);
195 195 static void rt2661_setup_tx_desc(struct rt2661_softc *,
196 196 struct rt2661_tx_desc *, uint32_t, uint16_t, int,
197 197 int, int);
198 198
199 199 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t);
200 200
201 201 static int rt2661_send(ieee80211com_t *, mblk_t *);
202 202 static int rt2661_mgmt_send(ieee80211com_t *, mblk_t *, uint8_t);
203 203
204 204 static void rt2661_amrr_node_init(const struct rt2661_amrr *,
205 205 struct rt2661_amrr_node *);
206 206 static void rt2661_amrr_choose(struct rt2661_amrr *,
207 207 struct ieee80211_node *, struct rt2661_amrr_node *);
208 208
209 209 static void rt2661_update_promisc(struct rt2661_softc *);
210 210 static void rt2661_updateslot(struct ieee80211com *, int);
211 211 static void rt2661_set_slottime(struct rt2661_softc *);
212 212 static void rt2661_enable_mrr(struct rt2661_softc *);
213 213 static void rt2661_set_txpreamble(struct rt2661_softc *);
214 214 static void rt2661_set_basicrates(struct rt2661_softc *);
215 215 static void rt2661_set_bssid(struct rt2661_softc *, const uint8_t *);
216 216 static void rt2661_newassoc(struct ieee80211com *, struct ieee80211_node *);
217 217 static void rt2661_updatestats(void *);
218 218 static void rt2661_rx_tune(struct rt2661_softc *);
219 219 static void rt2661_enable_tsf_sync(struct rt2661_softc *);
220 220 static int rt2661_newstate(struct ieee80211com *,
221 221 enum ieee80211_state, int);
222 222
223 223 static void rt2661_set_macaddr(struct rt2661_softc *, const uint8_t *);
224 224 static int rt2661_bbp_init(struct rt2661_softc *);
225 225 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t);
226 226 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, uint8_t);
227 227 static void rt2661_select_band(struct rt2661_softc *,
228 228 struct ieee80211_channel *);
229 229 static void rt2661_select_antenna(struct rt2661_softc *);
230 230 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t);
231 231 static void rt2661_set_chan(struct rt2661_softc *,
232 232 struct ieee80211_channel *);
233 233
234 234 static void rt2661_stop_locked(struct rt2661_softc *);
235 235 static int rt2661_init(struct rt2661_softc *);
236 236 static void rt2661_stop(struct rt2661_softc *);
237 237 /*
238 238 * device operations
239 239 */
240 240 static int rt2661_attach(dev_info_t *, ddi_attach_cmd_t);
241 241 static int rt2661_detach(dev_info_t *, ddi_detach_cmd_t);
242 242 static int rt2661_quiesce(dev_info_t *);
243 243
244 244 /*
245 245 * Module Loading Data & Entry Points
246 246 */
247 247 DDI_DEFINE_STREAM_OPS(rwd_dev_ops, nulldev, nulldev, rt2661_attach,
|
↓ open down ↓ |
247 lines elided |
↑ open up ↑ |
248 248 rt2661_detach, nodev, NULL, D_MP, NULL, rt2661_quiesce);
249 249
250 250 static struct modldrv rwd_modldrv = {
251 251 &mod_driverops, /* Type of module. This one is a driver */
252 252 "Ralink RT2661 driver v1.1", /* short description */
253 253 &rwd_dev_ops /* driver specific ops */
254 254 };
255 255
256 256 static struct modlinkage modlinkage = {
257 257 MODREV_1,
258 - (void *)&rwd_modldrv,
259 - NULL
258 + { (void *)&rwd_modldrv, NULL }
260 259 };
261 260
262 261 static int rt2661_m_stat(void *, uint_t, uint64_t *);
263 262 static int rt2661_m_start(void *);
264 263 static void rt2661_m_stop(void *);
265 264 static int rt2661_m_promisc(void *, boolean_t);
266 265 static int rt2661_m_multicst(void *, boolean_t, const uint8_t *);
267 266 static int rt2661_m_unicst(void *, const uint8_t *);
268 267 static mblk_t *rt2661_m_tx(void *, mblk_t *);
269 268 static void rt2661_m_ioctl(void *, queue_t *, mblk_t *);
270 269 static int rt2661_m_setprop(void *arg, const char *pr_name,
271 270 mac_prop_id_t wldp_pr_num,
272 271 uint_t wldp_length, const void *wldp_buf);
273 272 static int rt2661_m_getprop(void *arg, const char *pr_name,
274 273 mac_prop_id_t wldp_pr_num, uint_t wldp_length,
275 274 void *wldp_buf);
276 275 static void rt2661_m_propinfo(void *arg, const char *pr_name,
277 276 mac_prop_id_t wldp_pr_num, mac_prop_info_handle_t mph);
278 277
279 278 static mac_callbacks_t rt2661_m_callbacks = {
280 279 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
281 280 rt2661_m_stat,
282 281 rt2661_m_start,
283 282 rt2661_m_stop,
284 283 rt2661_m_promisc,
285 284 rt2661_m_multicst,
286 285 rt2661_m_unicst,
287 286 rt2661_m_tx,
288 287 NULL,
289 288 rt2661_m_ioctl,
290 289 NULL,
291 290 NULL,
292 291 NULL,
293 292 rt2661_m_setprop,
294 293 rt2661_m_getprop,
295 294 rt2661_m_propinfo
296 295 };
297 296
298 297 #ifdef DEBUG
299 298 void
300 299 rt2661_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
301 300 {
302 301 va_list args;
303 302
304 303 if (dbg_flags & rt2661_dbg_flags) {
305 304 va_start(args, fmt);
306 305 vcmn_err(CE_CONT, fmt, args);
307 306 va_end(args);
308 307 }
309 308 }
310 309 #endif
311 310
312 311 /*
313 312 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
314 313 * 93C66).
315 314 */
316 315 static uint16_t
317 316 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
318 317 {
319 318 uint32_t tmp;
320 319 uint16_t val;
321 320 int n;
322 321
323 322 /* clock C once before the first command */
324 323 RT2661_EEPROM_CTL(sc, 0);
325 324
326 325 RT2661_EEPROM_CTL(sc, RT2661_S);
327 326 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
328 327 RT2661_EEPROM_CTL(sc, RT2661_S);
329 328
330 329 /* write start bit (1) */
331 330 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
332 331 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
333 332
334 333 /* write READ opcode (10) */
335 334 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
336 335 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
337 336 RT2661_EEPROM_CTL(sc, RT2661_S);
338 337 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
339 338
340 339 /* write address (A5-A0 or A7-A0) */
341 340 n = (RT2661_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
342 341 for (; n >= 0; n--) {
343 342 RT2661_EEPROM_CTL(sc, RT2661_S |
344 343 (((addr >> n) & 1) << RT2661_SHIFT_D));
345 344 RT2661_EEPROM_CTL(sc, RT2661_S |
346 345 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C);
347 346 }
348 347
349 348 RT2661_EEPROM_CTL(sc, RT2661_S);
350 349
351 350 /* read data Q15-Q0 */
352 351 val = 0;
353 352 for (n = 15; n >= 0; n--) {
354 353 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
355 354 tmp = RT2661_READ(sc, RT2661_E2PROM_CSR);
356 355 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
357 356 RT2661_EEPROM_CTL(sc, RT2661_S);
358 357 }
359 358
360 359 RT2661_EEPROM_CTL(sc, 0);
361 360
362 361 /* clear Chip Select and clock C */
363 362 RT2661_EEPROM_CTL(sc, RT2661_S);
364 363 RT2661_EEPROM_CTL(sc, 0);
365 364 RT2661_EEPROM_CTL(sc, RT2661_C);
366 365
367 366 return (val);
368 367 }
369 368
370 369
371 370 static void
372 371 rt2661_read_eeprom(struct rt2661_softc *sc)
373 372 {
374 373 struct ieee80211com *ic = &sc->sc_ic;
375 374 uint16_t val;
376 375 int i;
377 376
378 377 /* read MAC address */
379 378 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
380 379 ic->ic_macaddr[0] = val & 0xff;
381 380 ic->ic_macaddr[1] = val >> 8;
382 381
383 382 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
384 383 ic->ic_macaddr[2] = val & 0xff;
385 384 ic->ic_macaddr[3] = val >> 8;
386 385
387 386 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
388 387 ic->ic_macaddr[4] = val & 0xff;
389 388 ic->ic_macaddr[5] = val >> 8;
390 389
391 390 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
392 391 /* XXX: test if different from 0xffff? */
393 392 sc->rf_rev = (val >> 11) & 0x1f;
394 393 sc->hw_radio = (val >> 10) & 0x1;
395 394 sc->rx_ant = (val >> 4) & 0x3;
396 395 sc->tx_ant = (val >> 2) & 0x3;
397 396 sc->nb_ant = val & 0x3;
398 397
399 398 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_read_eeprom(): "
400 399 "RF revision=%d\n", sc->rf_rev);
401 400
402 401 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
403 402 sc->ext_5ghz_lna = (val >> 6) & 0x1;
404 403 sc->ext_2ghz_lna = (val >> 4) & 0x1;
405 404
406 405 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_read_eeprom(): "
407 406 "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
408 407 sc->ext_2ghz_lna, sc->ext_5ghz_lna);
409 408
410 409 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
411 410 if ((val & 0xff) != 0xff)
412 411 sc->rssi_2ghz_corr = (int8_t)(val & 0xff);
413 412
414 413 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
415 414 if ((val & 0xff) != 0xff)
416 415 sc->rssi_5ghz_corr = (int8_t)(val & 0xff);
417 416
418 417 /* adjust RSSI correction for external low-noise amplifier */
419 418 if (sc->ext_2ghz_lna)
420 419 sc->rssi_2ghz_corr -= 14;
421 420 if (sc->ext_5ghz_lna)
422 421 sc->rssi_5ghz_corr -= 14;
423 422
424 423 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_read_eeprom(): "
425 424 "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
426 425 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr);
427 426
428 427 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
429 428 if ((val >> 8) != 0xff)
430 429 sc->rfprog = (val >> 8) & 0x3;
431 430 if ((val & 0xff) != 0xff)
432 431 sc->rffreq = val & 0xff;
433 432
434 433 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_read_eeprom(): "
435 434 "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq);
436 435
437 436 /* read Tx power for all a/b/g channels */
438 437 for (i = 0; i < 19; i++) {
439 438 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
440 439 sc->txpow[i * 2] = (int8_t)(val >> 8);
441 440 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_read_eeprom(): "
442 441 "Channel=%d Tx power=%d\n",
443 442 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]);
444 443 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff);
445 444 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_read_eeprom(): "
446 445 "Channel=%d Tx power=%d\n",
447 446 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]);
448 447 }
449 448
450 449 /* read vendor-specific BBP values */
451 450 for (i = 0; i < 16; i++) {
452 451 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
453 452 if (val == 0 || val == 0xffff)
454 453 continue;
455 454 sc->bbp_prom[i].reg = val >> 8;
456 455 sc->bbp_prom[i].val = val & 0xff;
457 456 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_read_eeprom(): "
458 457 "BBP R%d=%02x\n", sc->bbp_prom[i].reg,
459 458 sc->bbp_prom[i].val);
460 459 }
461 460 }
462 461
463 462 static const char *
464 463 rt2661_get_rf(int rev)
465 464 {
466 465 switch (rev) {
467 466 case RT2661_RF_5225: return "RT5225";
468 467 case RT2661_RF_5325: return "RT5325 (MIMO XR)";
469 468 case RT2661_RF_2527: return "RT2527";
470 469 case RT2661_RF_2529: return "RT2529 (MIMO XR)";
471 470 default: return "unknown";
472 471 }
473 472 }
474 473
475 474 static int
476 475 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode_p, int size)
477 476 {
478 477 int ntries;
479 478 uint32_t off, i;
480 479 const uint8_t *fptr;
481 480
482 481 fptr = ucode_p;
483 482 off = RT2661_MCU_CODE_BASE;
484 483
485 484 /* reset 8051 */
486 485 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
487 486
488 487 /* cancel any pending Host to MCU command */
489 488 RT2661_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
490 489 RT2661_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
491 490 RT2661_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
492 491
493 492 /* write 8051's microcode */
494 493 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR,
495 494 RT2661_MCU_RESET | RT2661_MCU_SEL);
496 495 /* RT2661_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); */
497 496
498 497 for (i = 0; i < size; i++) {
499 498 RT2661_MEM_WRITE1(sc, off++, *fptr++);
500 499 }
501 500
502 501 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
503 502
504 503 /* kick 8051's ass */
505 504 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
506 505
507 506 /* wait for 8051 to initialize */
508 507 for (ntries = 0; ntries < 500; ntries++) {
509 508 if (RT2661_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
510 509 break;
511 510 DELAY(100);
512 511 }
513 512 if (ntries == 500) {
514 513 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_load_microcode(): "
515 514 "timeout waiting for MCU to initialize\n");
516 515 return (RT2661_FAILURE);
517 516 }
518 517
519 518 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_load_microcode(): "
520 519 "MCU initialized successfully\n");
521 520 return (RT2661_SUCCESS);
522 521 }
523 522
524 523 /*
525 524 * Allocate an DMA memory and a DMA handle for accessing it
526 525 */
527 526 static int
528 527 rt2661_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr,
529 528 size_t memsize, ddi_device_acc_attr_t *attr_p, uint_t alloc_flags,
530 529 uint_t bind_flags, struct dma_area *dma_p)
531 530 {
532 531 int err;
533 532
534 533 /*
535 534 * Allocate handle
536 535 */
537 536 err = ddi_dma_alloc_handle(devinfo, dma_attr,
538 537 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
539 538 if (err != DDI_SUCCESS) {
540 539 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rwd_allo_dma_mem(): "
541 540 "failed to alloc handle\n");
542 541 goto fail1;
543 542 }
544 543
545 544 /*
546 545 * Allocate memory
547 546 */
548 547 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
549 548 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va,
550 549 &dma_p->alength, &dma_p->acc_hdl);
551 550 if (err != DDI_SUCCESS) {
552 551 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rwd_alloc_dma_mem(): "
553 552 "failed to alloc mem\n");
554 553 goto fail2;
555 554 }
556 555
557 556 /*
558 557 * Bind the two together
559 558 */
560 559 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
561 560 dma_p->mem_va, dma_p->alength, bind_flags,
562 561 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies);
563 562 if (err != DDI_DMA_MAPPED) {
564 563 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rwd_alloc_dma_mem(): "
565 564 "failed to bind handle\n");
566 565 goto fail3;
567 566 }
568 567
569 568 if (dma_p->ncookies != 1) {
570 569 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rwd_alloc_dma_mem(): "
571 570 "failed to alloc cookies\n");
572 571 goto fail4;
573 572 }
574 573
575 574 dma_p->nslots = ~0U;
576 575 dma_p->size = ~0U;
577 576 dma_p->token = ~0U;
578 577 dma_p->offset = 0;
579 578 return (DDI_SUCCESS);
580 579
581 580 fail4:
582 581 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
583 582 fail3:
584 583 ddi_dma_mem_free(&dma_p->acc_hdl);
585 584 fail2:
586 585 ddi_dma_free_handle(&dma_p->dma_hdl);
587 586 fail1:
588 587 return (err);
589 588 }
590 589
591 590 static void
592 591 rt2661_free_dma_mem(struct dma_area *dma_p)
593 592 {
594 593 if (dma_p->dma_hdl != NULL) {
595 594 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
596 595 if (dma_p->acc_hdl != NULL) {
597 596 ddi_dma_mem_free(&dma_p->acc_hdl);
598 597 dma_p->acc_hdl = NULL;
599 598 }
600 599 ddi_dma_free_handle(&dma_p->dma_hdl);
601 600 dma_p->ncookies = 0;
602 601 dma_p->dma_hdl = NULL;
603 602 }
604 603 }
605 604
606 605 /*ARGSUSED*/
607 606 static int
608 607 rt2661_alloc_tx_ring(struct rt2661_softc *sc,
609 608 struct rt2661_tx_ring *ring, int count)
610 609 {
611 610 struct rt2661_tx_desc *desc;
612 611 struct rt2661_tx_data *data;
613 612 int i, err, size, len;
614 613
615 614 size = count * RT2661_TX_DESC_SIZE;
616 615 len = count * sizeof (struct rt2661_tx_data);
617 616
618 617 ring->count = count;
619 618 ring->queued = 0;
620 619 ring->cur = 0;
621 620 ring->next = 0;
622 621 ring->stat = 0;
623 622
624 623 err = rt2661_alloc_dma_mem(sc->sc_dev, &rt2661_dma_attr, size,
625 624 &rt2661_desc_accattr, DDI_DMA_CONSISTENT,
626 625 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
627 626 &ring->txdesc_dma);
628 627 if (err != DDI_SUCCESS) {
629 628 RWD_DEBUG(RT2661_DBG_DMA, "rwd: rt2661_alloc_tx_ring(): "
630 629 "failed to alloc dma mem\n");
631 630 goto fail1;
632 631 }
633 632
634 633 ring->desc = (struct rt2661_tx_desc *)ring->txdesc_dma.mem_va;
635 634 (void) bzero(ring->desc, size);
636 635 ring->paddr = ring->txdesc_dma.cookie.dmac_address;
637 636
638 637 ring->data = kmem_zalloc(len, KM_NOSLEEP);
639 638 if (ring->data == NULL) {
640 639 RWD_DEBUG(RT2661_DBG_DMA, "rwd: rt2661_alloc_tx_ring(): "
641 640 "failed to alloc tx buffer\n");
642 641 goto fail2;
643 642 }
644 643
645 644 for (i = 0; i < count; i++) {
646 645 desc = &ring->desc[i];
647 646 data = &ring->data[i];
648 647 err = rt2661_alloc_dma_mem(sc->sc_dev,
649 648 &rt2661_dma_attr, sc->sc_dmabuf_size,
650 649 &rt2661_buf_accattr, DDI_DMA_CONSISTENT,
651 650 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
652 651 &data->txdata_dma);
653 652 if (err != DDI_SUCCESS) {
654 653 RWD_DEBUG(RT2661_DBG_DMA,
655 654 "rwd: rt2661_alloc_tx_ring(): "
656 655 "failed to alloc tx buffer dma\n");
657 656 while (i >= 0) {
658 657 rt2661_free_dma_mem(&ring->data[i].txdata_dma);
659 658 i--;
660 659 }
661 660 goto fail3;
662 661 }
663 662 desc->addr[0] = data->txdata_dma.cookie.dmac_address;
664 663 data->buf = data->txdata_dma.mem_va;
665 664 data->paddr = data->txdata_dma.cookie.dmac_address;
666 665 }
667 666
668 667 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
669 668 0, size, DDI_DMA_SYNC_FORDEV);
670 669 return (DDI_SUCCESS);
671 670 fail3:
672 671 if (ring->data)
673 672 kmem_free(ring->data,
674 673 count * sizeof (struct rt2661_tx_data));
675 674 fail2:
676 675 rt2661_free_dma_mem(&ring->txdesc_dma);
677 676 fail1:
678 677 return (err);
679 678 }
680 679
681 680 static void
682 681 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
683 682 {
684 683 struct rt2661_tx_desc *desc;
685 684 struct rt2661_tx_data *data;
686 685 int i;
687 686
688 687 for (i = 0; i < ring->count; i++) {
689 688 desc = &ring->desc[i];
690 689 data = &ring->data[i];
691 690
692 691 if (data->ni != NULL) {
693 692 ieee80211_free_node(data->ni);
694 693 data->ni = NULL;
695 694 }
696 695
697 696 desc->flags = 0;
698 697 }
699 698
700 699 if (!RT2661_IS_FASTREBOOT(sc))
701 700 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl, 0,
702 701 ring->count * sizeof (struct rt2661_tx_desc),
703 702 DDI_DMA_SYNC_FORDEV);
704 703
705 704 ring->queued = 0;
706 705 ring->cur = ring->next = ring->stat = 0;
707 706 }
708 707
709 708
710 709 /*ARGSUSED*/
711 710 static void
712 711 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
713 712 {
714 713 struct rt2661_tx_data *data;
715 714 int i;
716 715
717 716 if (ring->desc != NULL) {
718 717 rt2661_free_dma_mem(&ring->txdesc_dma);
719 718 }
720 719
721 720 if (ring->data != NULL) {
722 721 for (i = 0; i < ring->count; i++) {
723 722 data = &ring->data[i];
724 723 rt2661_free_dma_mem(&data->txdata_dma);
725 724 if (data->ni != NULL) {
726 725 ieee80211_free_node(data->ni);
727 726 data->ni = NULL;
728 727 }
729 728 }
730 729 kmem_free(ring->data,
731 730 ring->count * sizeof (struct rt2661_tx_data));
732 731 }
733 732 }
734 733
735 734 /*ARGSUSED*/
736 735 static int
737 736 rt2661_alloc_rx_ring(struct rt2661_softc *sc,
738 737 struct rt2661_rx_ring *ring, int count)
739 738 {
740 739 struct rt2661_rx_desc *desc;
741 740 struct rt2661_rx_data *data;
742 741 int i, err, len, size;
743 742
744 743 size = count * RT2661_RX_DESC_SIZE;
745 744 len = count * sizeof (struct rt2661_rx_data);
746 745
747 746 ring->count = count;
748 747 ring->cur = 0;
749 748 ring->next = 0;
750 749
751 750 err = rt2661_alloc_dma_mem(sc->sc_dev, &rt2661_dma_attr, size,
752 751 &rt2661_desc_accattr, DDI_DMA_CONSISTENT,
753 752 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
754 753 &ring->rxdesc_dma);
755 754 if (err != DDI_SUCCESS) {
756 755 RWD_DEBUG(RT2661_DBG_DMA, "rwd: rt2661_alloc_rx_ring(): "
757 756 "failed to alloc dma mem\n");
758 757 goto fail1;
759 758 }
760 759
761 760 ring->desc = (struct rt2661_rx_desc *)ring->rxdesc_dma.mem_va;
762 761 (void) bzero(ring->desc, size);
763 762 ring->paddr = ring->rxdesc_dma.cookie.dmac_address;
764 763
765 764 ring->data = kmem_zalloc(len, KM_NOSLEEP);
766 765 if (ring->data == NULL) {
767 766 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_alloc_rx_ring(): "
768 767 "failed to alloc rx buffer\n");
769 768 goto fail2;
770 769 }
771 770
772 771 for (i = 0; i < count; i++) {
773 772 desc = &ring->desc[i];
774 773 data = &ring->data[i];
775 774 err = rt2661_alloc_dma_mem(sc->sc_dev,
776 775 &rt2661_dma_attr, sc->sc_dmabuf_size,
777 776 &rt2661_buf_accattr, DDI_DMA_CONSISTENT,
778 777 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
779 778 &data->rxdata_dma);
780 779 if (err != DDI_SUCCESS) {
781 780 RWD_DEBUG(RT2661_DBG_DMA,
782 781 "rwd: rt2661_alloc_rx_ring(): "
783 782 "failed to alloc rx buffer dma\n");
784 783 while (i >= 0) {
785 784 rt2661_free_dma_mem(&ring->data[i].rxdata_dma);
786 785 i--;
787 786 }
788 787 goto fail3;
789 788 }
790 789 data->buf = data->rxdata_dma.mem_va;
791 790 data->paddr = data->rxdata_dma.cookie.dmac_address;
792 791 desc->flags = LE_32(RT2661_RX_BUSY);
793 792 desc->physaddr = LE_32(data->paddr);
794 793 }
795 794
796 795 (void) ddi_dma_sync(ring->rxdesc_dma.dma_hdl,
797 796 0, size, DDI_DMA_SYNC_FORDEV);
798 797 return (DDI_SUCCESS);
799 798 fail3:
800 799 if (ring->data)
801 800 kmem_free(ring->data,
802 801 count * sizeof (struct rt2661_rx_data));
803 802 fail2:
804 803 rt2661_free_dma_mem(&ring->rxdesc_dma);
805 804 fail1:
806 805 return (err);
807 806 }
808 807
809 808 static void
810 809 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
811 810 {
812 811 int i;
813 812
814 813 for (i = 0; i < ring->count; i++)
815 814 ring->desc[i].flags = LE_32(RT2661_RX_BUSY);
816 815
817 816 if (!RT2661_IS_FASTREBOOT(sc))
818 817 (void) ddi_dma_sync(ring->rxdesc_dma.dma_hdl, 0,
819 818 ring->count * sizeof (struct rt2661_rx_ring),
820 819 DDI_DMA_SYNC_FORKERNEL);
821 820
822 821 ring->cur = ring->next = 0;
823 822 }
824 823
825 824 /*ARGSUSED*/
826 825 static void
827 826 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
828 827 {
829 828 struct rt2661_rx_data *data;
830 829 int i;
831 830
832 831 if (ring->desc != NULL) {
833 832 rt2661_free_dma_mem(&ring->rxdesc_dma);
834 833 }
835 834
836 835 if (ring->data != NULL) {
837 836 for (i = 0; i < ring->count; i++) {
838 837 data = &ring->data[i];
839 838 rt2661_free_dma_mem(&data->rxdata_dma);
840 839 }
841 840 kmem_free(ring->data,
842 841 ring->count * sizeof (struct rt2661_rx_data));
843 842 }
844 843 }
845 844
846 845 static void
847 846 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
848 847 {
849 848 struct rt2661_tx_desc *desc;
850 849 struct rt2661_tx_data *data;
851 850
852 851 for (;;) {
853 852 desc = &ring->desc[ring->next];
854 853 data = &ring->data[ring->next];
855 854
856 855 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
857 856 ring->next * RT2661_TX_DESC_SIZE,
858 857 RT2661_TX_DESC_SIZE,
859 858 DDI_DMA_SYNC_FORKERNEL);
860 859
861 860 if ((LE_32(desc->flags) & RT2661_TX_BUSY) ||
862 861 !(LE_32(desc->flags) & RT2661_TX_VALID))
863 862 break;
864 863
865 864 (void) ddi_dma_sync(data->txdata_dma.dma_hdl,
866 865 0, sc->sc_dmabuf_size,
867 866 DDI_DMA_SYNC_FORDEV);
868 867
869 868 /* descriptor is no longer valid */
870 869 desc->flags &= ~LE_32(RT2661_TX_VALID);
871 870
872 871 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
873 872 ring->next * RT2661_TX_DESC_SIZE,
874 873 RT2661_TX_DESC_SIZE,
875 874 DDI_DMA_SYNC_FORDEV);
876 875
877 876 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_tx_dma_intr(): "
878 877 "tx dma done q=%p idx=%u\n", ring, ring->next);
879 878
880 879 if (++ring->next >= ring->count) /* faster than % count */
881 880 ring->next = 0;
882 881 }
883 882 }
884 883
885 884 static void
886 885 rt2661_tx_intr(struct rt2661_softc *sc)
887 886 {
888 887 struct ieee80211com *ic = &sc->sc_ic;
889 888 struct rt2661_tx_ring *ring;
890 889 struct rt2661_tx_data *data;
891 890 struct rt2661_node *rn;
892 891
893 892 uint32_t val;
894 893 int qid, retrycnt;
895 894
896 895 for (;;) {
897 896 val = RT2661_READ(sc, RT2661_STA_CSR4);
898 897 if (!(val & RT2661_TX_STAT_VALID))
899 898 break;
900 899
901 900 /* retrieve the queue in which this frame was send */
902 901 qid = RT2661_TX_QID(val);
903 902 ring = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
904 903
905 904 /* retrieve rate control algorithm context */
906 905 data = &ring->data[ring->stat];
907 906 rn = (struct rt2661_node *)data->ni;
908 907
909 908 /* if no frame has been sent, ignore */
910 909 if (rn == NULL) {
911 910 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_tx_intr(): "
912 911 "no frame has been send, ignore\n");
913 912 continue;
914 913 }
915 914
916 915 switch (RT2661_TX_RESULT(val)) {
917 916 case RT2661_TX_SUCCESS:
918 917 retrycnt = RT2661_TX_RETRYCNT(val);
919 918
920 919 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_tx_intr(): "
921 920 "data frame sent successfully after "
922 921 "%d retries\n", retrycnt);
923 922 rn->amn.amn_txcnt++;
924 923 if (retrycnt > 0) {
925 924 rn->amn.amn_retrycnt++;
926 925 sc->sc_tx_retries++;
927 926 }
928 927 break;
929 928 case RT2661_TX_RETRY_FAIL:
930 929 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_tx_intr(): "
931 930 "sending data frame failed (too much retries)\n");
932 931 rn->amn.amn_txcnt++;
933 932 rn->amn.amn_retrycnt++;
934 933 break;
935 934 default:
936 935 /* other failure */
937 936 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_tx_intr():"
938 937 "sending data frame failed 0x%08x\n", val);
939 938 }
940 939
941 940 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_tx_intr(): "
942 941 "tx done q=%d idx=%u\n", qid, ring->stat);
943 942
944 943 ieee80211_free_node(data->ni);
945 944 data->ni = NULL;
946 945
947 946 ring->queued--;
948 947
949 948 /* faster than % count */
950 949 if (++ring->stat >= ring->count)
951 950 ring->stat = 0;
952 951
953 952 if (sc->sc_need_sched) {
954 953 sc->sc_need_sched = 0;
955 954 mac_tx_update(ic->ic_mach);
956 955 }
957 956 }
958 957 sc->sc_tx_timer = 0;
959 958 }
960 959
961 960 static void
962 961 rt2661_rx_intr(struct rt2661_softc *sc)
963 962 {
964 963 struct ieee80211com *ic = &sc->sc_ic;
965 964 struct rt2661_rx_ring *ring;
966 965 struct rt2661_rx_desc *desc;
967 966 struct rt2661_rx_data *data;
968 967 struct ieee80211_frame *wh;
969 968 struct ieee80211_node *ni;
970 969
971 970 mblk_t *m;
972 971 uint8_t *rxbuf;
973 972 uint32_t pktlen;
974 973
975 974 mutex_enter(&sc->sc_rxlock);
976 975 ring = &sc->rxq;
977 976
978 977 for (;;) {
979 978 int rssi;
980 979
981 980 desc = &ring->desc[ring->cur];
982 981 data = &ring->data[ring->cur];
983 982
984 983 (void) ddi_dma_sync(ring->rxdesc_dma.dma_hdl,
985 984 ring->cur * RT2661_RX_DESC_SIZE,
986 985 RT2661_RX_DESC_SIZE,
987 986 DDI_DMA_SYNC_FORKERNEL);
988 987
989 988
990 989 if (LE_32(desc->flags) & RT2661_RX_BUSY)
991 990 break;
992 991
993 992 if ((LE_32(desc->flags) & RT2661_RX_PHY_ERROR) ||
994 993 (LE_32(desc->flags) & RT2661_RX_CRC_ERROR)) {
995 994 /*
996 995 * This should not happen since we did not request
997 996 * to receive those frames when we filled TXRX_CSR0.
998 997 */
999 998 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_rx_intr(): "
1000 999 "PHY or CRC error flags 0x%08x\n",
1001 1000 LE_32(desc->flags));
1002 1001 sc->sc_rx_err++;
1003 1002 goto skip;
1004 1003 }
1005 1004
1006 1005 if ((LE_32(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) {
1007 1006 sc->sc_rx_err++;
1008 1007 goto skip;
1009 1008 }
1010 1009
1011 1010 (void) ddi_dma_sync(data->rxdata_dma.dma_hdl,
1012 1011 0, sc->sc_dmabuf_size,
1013 1012 DDI_DMA_SYNC_FORCPU);
1014 1013
1015 1014 rxbuf = (uint8_t *)data->rxdata_dma.mem_va;
1016 1015 desc->physaddr = LE_32(data->rxdata_dma.cookie.dmac_address);
1017 1016 pktlen = (LE_32(desc->flags) >> 16) & 0xfff;
1018 1017 if ((pktlen < sizeof (struct ieee80211_frame_min)) ||
1019 1018 (pktlen > sc->sc_dmabuf_size)) {
1020 1019 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_rx_intr(): "
1021 1020 "bad fram length=%u\n", pktlen);
1022 1021 sc->sc_rx_err++;
1023 1022 goto skip;
1024 1023 }
1025 1024
1026 1025 if ((m = allocb(pktlen, BPRI_MED)) == NULL) {
1027 1026 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_rx_intr(): "
1028 1027 "allocate mblk failed.\n");
1029 1028 sc->sc_rx_nobuf++;
1030 1029 goto skip;
1031 1030 }
1032 1031
1033 1032 bcopy(rxbuf, m->b_rptr, pktlen);
1034 1033 m->b_wptr += pktlen;
1035 1034
1036 1035 wh = (struct ieee80211_frame *)m->b_rptr;
1037 1036 ni = ieee80211_find_rxnode(ic, wh);
1038 1037
1039 1038 rssi = rt2661_get_rssi(sc, desc->rssi);
1040 1039 /* send the frame to the 802.11 layer */
1041 1040 (void) ieee80211_input(ic, m, ni, rssi + 95, 0);
1042 1041
1043 1042 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8;
1044 1043
1045 1044 /* node is no longer needed */
1046 1045 ieee80211_free_node(ni);
1047 1046 skip:
1048 1047 desc->flags |= LE_32(RT2661_RX_BUSY);
1049 1048
1050 1049 (void) ddi_dma_sync(ring->rxdesc_dma.dma_hdl,
1051 1050 ring->cur * RT2661_RX_DESC_SIZE,
1052 1051 RT2661_RX_DESC_SIZE,
1053 1052 DDI_DMA_SYNC_FORDEV);
1054 1053
1055 1054 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_rx_intr(): "
1056 1055 "rx intr idx=%u\n", sc->rxq.cur);
1057 1056 ring->cur = (ring->cur + 1) % RT2661_RX_RING_COUNT;
1058 1057 }
1059 1058 mutex_exit(&sc->sc_rxlock);
1060 1059 }
1061 1060
1062 1061 /*ARGSUSED*/
1063 1062 static uint_t
1064 1063 rt2661_softintr(caddr_t data, caddr_t unused)
1065 1064 {
1066 1065 struct rt2661_softc *sc = (struct rt2661_softc *)data;
1067 1066
1068 1067 if (sc->sc_rx_pend) {
1069 1068 sc->sc_rx_pend = 0;
1070 1069 rt2661_rx_intr(sc);
1071 1070 return (DDI_INTR_CLAIMED);
1072 1071 }
1073 1072 return (DDI_INTR_UNCLAIMED);
1074 1073 }
1075 1074
1076 1075 static int
1077 1076 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
1078 1077 {
1079 1078 if (RT2661_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
1080 1079 return (EIO); /* there is already a command pending */
1081 1080
1082 1081 RT2661_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1083 1082 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg);
1084 1083
1085 1084 RT2661_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1086 1085
1087 1086 return (0);
1088 1087 }
1089 1088
1090 1089 static void
1091 1090 rt2661_mcu_wakeup(struct rt2661_softc *sc)
1092 1091 {
1093 1092 RT2661_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1094 1093
1095 1094 RT2661_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1096 1095 RT2661_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1097 1096 RT2661_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1098 1097
1099 1098 /* send wakeup command to MCU */
1100 1099 (void) rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1101 1100 }
1102 1101
1103 1102 static void
1104 1103 rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1105 1104 {
1106 1105 (void) RT2661_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1107 1106 RT2661_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1108 1107 }
1109 1108
1110 1109 /*ARGSUSED*/
1111 1110 static uint_t
1112 1111 rt2661_intr(caddr_t arg, caddr_t unused)
1113 1112 {
1114 1113 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
1115 1114 uint32_t r1, r2;
1116 1115
1117 1116 RT2661_GLOCK(sc);
1118 1117
1119 1118 if (!RT2661_IS_RUNNING(sc) || RT2661_IS_SUSPEND(sc)) {
1120 1119 RT2661_GUNLOCK(sc);
1121 1120 return (DDI_INTR_UNCLAIMED);
1122 1121 }
1123 1122
1124 1123 r1 = RT2661_READ(sc, RT2661_INT_SOURCE_CSR);
1125 1124 r2 = RT2661_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1126 1125 if (r1 == 0 && r2 == 0) {
1127 1126 RT2661_GUNLOCK(sc);
1128 1127 return (DDI_INTR_UNCLAIMED); /* not for us */
1129 1128 }
1130 1129
1131 1130 /* disable MAC and MCU interrupts */
1132 1131 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1133 1132 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1134 1133
1135 1134 /* acknowledge interrupts */
1136 1135 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1137 1136 RT2661_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1138 1137
1139 1138 if (r1 & RT2661_MGT_DONE) {
1140 1139 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1141 1140 "RT2661_MGT_DONE\n");
1142 1141 rt2661_tx_dma_intr(sc, &sc->mgtq);
1143 1142 }
1144 1143
1145 1144 if (r1 & RT2661_RX_DONE) {
1146 1145 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1147 1146 "RT2661_RX_DONE\n");
1148 1147 sc->sc_rx_pend = 1;
1149 1148 (void) ddi_intr_trigger_softint(sc->sc_softintr_hdl, NULL);
1150 1149 }
1151 1150
1152 1151 if (r1 & RT2661_TX0_DMA_DONE) {
1153 1152 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1154 1153 "RT2661_TX0_DMA_DONE\n");
1155 1154 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1156 1155 }
1157 1156
1158 1157 if (r1 & RT2661_TX1_DMA_DONE) {
1159 1158 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1160 1159 "RT2661_TX1_DMA_DONE\n");
1161 1160 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1162 1161 }
1163 1162
1164 1163 if (r1 & RT2661_TX2_DMA_DONE) {
1165 1164 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1166 1165 "RT2661_TX2_DMA_DONE\n");
1167 1166 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1168 1167 }
1169 1168
1170 1169 if (r1 & RT2661_TX3_DMA_DONE) {
1171 1170 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1172 1171 "RT2661_TX3_DMA_DONE\n");
1173 1172 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1174 1173 }
1175 1174
1176 1175 if (r1 & RT2661_TX_DONE) {
1177 1176 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1178 1177 "RT2661_TX_DONE\n");
1179 1178 rt2661_tx_intr(sc);
1180 1179 }
1181 1180
1182 1181 if (r2 & RT2661_MCU_CMD_DONE) {
1183 1182 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1184 1183 "RT2661_MCU_CMD_DONE\n");
1185 1184 rt2661_mcu_cmd_intr(sc);
1186 1185 }
1187 1186
1188 1187 if (r2 & RT2661_MCU_WAKEUP) {
1189 1188 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_intr(): "
1190 1189 "RT2661_MCU_WAKEUP\n");
1191 1190 rt2661_mcu_wakeup(sc);
1192 1191 }
1193 1192
1194 1193 /* re-enable MAC and MCU interrupts */
1195 1194 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1196 1195 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1197 1196
1198 1197 RT2661_GUNLOCK(sc);
1199 1198 return (RT2661_SUCCESS);
1200 1199 }
1201 1200
1202 1201 /*
1203 1202 * Retrieve the "Received Signal Strength Indicator" from the raw values
1204 1203 * contained in Rx descriptors. The computation depends on which band the
1205 1204 * frame was received. Correction values taken from the reference driver.
1206 1205 */
1207 1206 static int
1208 1207 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
1209 1208 {
1210 1209 int lna, agc, rssi;
1211 1210
1212 1211 lna = (raw >> 5) & 0x3;
1213 1212 agc = raw & 0x1f;
1214 1213
1215 1214 rssi = 2 * agc;
1216 1215
1217 1216 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
1218 1217 rssi += sc->rssi_2ghz_corr;
1219 1218
1220 1219 if (lna == 1)
1221 1220 rssi -= 64;
1222 1221 else if (lna == 2)
1223 1222 rssi -= 74;
1224 1223 else if (lna == 3)
1225 1224 rssi -= 90;
1226 1225 } else {
1227 1226 rssi += sc->rssi_5ghz_corr;
1228 1227
1229 1228 if (lna == 1)
1230 1229 rssi -= 64;
1231 1230 else if (lna == 2)
1232 1231 rssi -= 86;
1233 1232 else if (lna == 3)
1234 1233 rssi -= 100;
1235 1234 }
1236 1235 return (rssi);
1237 1236 }
1238 1237
1239 1238 /* quickly determine if a given rate is CCK or OFDM */
1240 1239 #define RT2661_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
1241 1240
1242 1241 #define RT2661_ACK_SIZE 14 /* 10 + 4(FCS) */
1243 1242 #define RT2661_CTS_SIZE 14 /* 10 + 4(FCS) */
1244 1243
1245 1244 #define RT2661_SIFS 10 /* us */
1246 1245
1247 1246 /*
1248 1247 * Return the expected ack rate for a frame transmitted at rate `rate'.
1249 1248 * XXX: this should depend on the destination node basic rate set.
1250 1249 */
1251 1250 static int
1252 1251 rt2661_ack_rate(struct ieee80211com *ic, int rate)
1253 1252 {
1254 1253 switch (rate) {
1255 1254 /* CCK rates */
1256 1255 case 2:
1257 1256 return (2);
1258 1257 case 4:
1259 1258 case 11:
1260 1259 case 22:
1261 1260 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
1262 1261
1263 1262 /* OFDM rates */
1264 1263 case 12:
1265 1264 case 18:
1266 1265 return (12);
1267 1266 case 24:
1268 1267 case 36:
1269 1268 return (24);
1270 1269 case 48:
1271 1270 case 72:
1272 1271 case 96:
1273 1272 case 108:
1274 1273 return (48);
1275 1274 }
1276 1275
1277 1276 /* default to 1Mbps */
1278 1277 return (2);
1279 1278 }
1280 1279
1281 1280 /*
1282 1281 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
1283 1282 * The function automatically determines the operating mode depending on the
1284 1283 * given rate. `flags' indicates whether short preamble is in use or not.
1285 1284 */
1286 1285 static uint16_t
1287 1286 rt2661_txtime(int len, int rate, uint32_t flags)
1288 1287 {
1289 1288 uint16_t txtime;
1290 1289
1291 1290 if (RT2661_RATE_IS_OFDM(rate)) {
1292 1291 /* IEEE Std 802.11a-1999, pp. 37 */
1293 1292 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
1294 1293 txtime = 16 + 4 + 4 * txtime + 6;
1295 1294 } else {
1296 1295 /* IEEE Std 802.11b-1999, pp. 28 */
1297 1296 txtime = (16 * len + rate - 1) / rate;
1298 1297 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
1299 1298 txtime += 72 + 24;
1300 1299 else
1301 1300 txtime += 144 + 48;
1302 1301 }
1303 1302
1304 1303 return (txtime);
1305 1304 }
1306 1305
1307 1306 static uint8_t
1308 1307 rt2661_plcp_signal(int rate)
1309 1308 {
1310 1309 switch (rate) {
1311 1310 /* CCK rates (returned values are device-dependent) */
1312 1311 case 2:
1313 1312 return (0x0);
1314 1313 case 4:
1315 1314 return (0x1);
1316 1315 case 11:
1317 1316 return (0x2);
1318 1317 case 22:
1319 1318 return (0x3);
1320 1319
1321 1320 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1322 1321 case 12:
1323 1322 return (0xb);
1324 1323 case 18:
1325 1324 return (0xf);
1326 1325 case 24:
1327 1326 return (0xa);
1328 1327 case 36:
1329 1328 return (0xe);
1330 1329 case 48:
1331 1330 return (0x9);
1332 1331 case 72:
1333 1332 return (0xd);
1334 1333 case 96:
1335 1334 return (0x8);
1336 1335 case 108:
1337 1336 return (0xc);
1338 1337
1339 1338 /* unsupported rates (should not get there) */
1340 1339 default:
1341 1340 return (0xff);
1342 1341 }
1343 1342 }
1344 1343
1345 1344 static void
1346 1345 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1347 1346 uint32_t flags, uint16_t xflags, int len, int rate, int ac)
1348 1347 {
1349 1348 struct ieee80211com *ic = &sc->sc_ic;
1350 1349 uint16_t plcp_length;
1351 1350 int remainder;
1352 1351
1353 1352 desc->flags = LE_32(flags);
1354 1353 desc->flags |= LE_32(len << 16);
1355 1354 desc->flags |= LE_32(RT2661_TX_BUSY | RT2661_TX_VALID);
1356 1355
1357 1356 desc->xflags = LE_16(xflags);
1358 1357 desc->xflags |= LE_16(1 << 13);
1359 1358
1360 1359 desc->wme = LE_16(
1361 1360 RT2661_QID(ac) |
1362 1361 RT2661_AIFSN(2) |
1363 1362 RT2661_LOGCWMIN(4) |
1364 1363 RT2661_LOGCWMAX(10));
1365 1364
1366 1365 /*
1367 1366 * Remember in which queue this frame was sent. This field is driver
1368 1367 * private data only. It will be made available by the NIC in STA_CSR4
1369 1368 * on Tx interrupts.
1370 1369 */
1371 1370 desc->qid = (uint8_t)ac;
1372 1371
1373 1372 /* setup PLCP fields */
1374 1373 desc->plcp_signal = rt2661_plcp_signal(rate);
1375 1374 desc->plcp_service = 4;
1376 1375
1377 1376 len += IEEE80211_CRC_LEN;
1378 1377
1379 1378 if (RT2661_RATE_IS_OFDM(rate)) {
1380 1379 desc->flags |= LE_32(RT2661_TX_OFDM);
1381 1380
1382 1381 plcp_length = len & 0xfff;
1383 1382 desc->plcp_length_hi = plcp_length >> 6;
1384 1383 desc->plcp_length_lo = plcp_length & 0x3f;
1385 1384 } else {
1386 1385 plcp_length = (16 * len + rate - 1) / rate;
1387 1386 if (rate == 22) {
1388 1387 remainder = (16 * len) % 22;
1389 1388 if (remainder != 0 && remainder < 7)
1390 1389 desc->plcp_service |= RT2661_PLCP_LENGEXT;
1391 1390 }
1392 1391 desc->plcp_length_hi = plcp_length >> 8;
1393 1392 desc->plcp_length_lo = plcp_length & 0xff;
1394 1393
1395 1394 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1396 1395 desc->plcp_signal |= 0x08;
1397 1396 }
1398 1397
1399 1398 /* RT2x61 supports scatter with up to 5 segments */
1400 1399 desc->len [0] = LE_16(len);
1401 1400 }
1402 1401
1403 1402 static int
1404 1403 rt2661_send(ieee80211com_t *ic, mblk_t *mp)
1405 1404 {
1406 1405 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1407 1406 struct rt2661_tx_ring *ring;
1408 1407 struct rt2661_tx_desc *desc;
1409 1408 struct rt2661_tx_data *data;
1410 1409 struct ieee80211_frame *wh;
1411 1410 struct ieee80211_node *ni;
1412 1411
1413 1412 int err, off, rate;
1414 1413 int mblen, pktlen;
1415 1414 mblk_t *m, *m0;
1416 1415 uint16_t dur;
1417 1416 uint32_t flags = 0;
1418 1417
1419 1418 mutex_enter(&sc->sc_txlock);
1420 1419 ring = &sc->txq[0];
1421 1420 err = DDI_SUCCESS;
1422 1421
1423 1422 if (ring->queued > RT2661_TX_RING_COUNT - 8) {
1424 1423 sc->sc_need_sched = 1;
1425 1424 sc->sc_tx_nobuf++;
1426 1425 err = ENOMEM;
1427 1426 goto fail1;
1428 1427 }
1429 1428
1430 1429 m = allocb(msgdsize(mp) + 32, BPRI_MED);
1431 1430 if (m == NULL) {
1432 1431 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_send():"
1433 1432 "can't alloc mblk.\n");
1434 1433 err = DDI_FAILURE;
1435 1434 goto fail1;
1436 1435 }
1437 1436
1438 1437 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
1439 1438 mblen = MBLKL(m0);
1440 1439 (void) bcopy(m0->b_rptr, m->b_rptr + off, mblen);
1441 1440 off += mblen;
1442 1441 }
1443 1442 m->b_wptr += off;
1444 1443
1445 1444 wh = (struct ieee80211_frame *)m->b_rptr;
1446 1445 ni = ieee80211_find_txnode(ic, wh->i_addr1);
1447 1446 if (ni == NULL) {
1448 1447 err = DDI_FAILURE;
1449 1448 sc->sc_tx_err++;
1450 1449 goto fail2;
1451 1450 }
1452 1451
1453 1452 (void) ieee80211_encap(ic, m, ni);
1454 1453
1455 1454 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1456 1455 struct ieee80211_key *k;
1457 1456 k = ieee80211_crypto_encap(ic, m);
1458 1457 if (k == NULL) {
1459 1458 sc->sc_tx_err++;
1460 1459 err = DDI_FAILURE;
1461 1460 goto fail3;
1462 1461 }
1463 1462 /* packet header may have moved, reset our local pointer */
1464 1463 wh = (struct ieee80211_frame *)m->b_rptr;
1465 1464 }
1466 1465
1467 1466 pktlen = msgdsize(m);
1468 1467
1469 1468 desc = &ring->desc[ring->cur];
1470 1469 data = &ring->data[ring->cur];
1471 1470 data->ni = ieee80211_ref_node(ni);
1472 1471
1473 1472 /* pickup a rate */
1474 1473 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1475 1474 /* multicast frames are sent at the lowest avail. rate */
1476 1475 rate = ni->in_rates.ir_rates[0];
1477 1476 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
1478 1477 rate = ic->ic_sup_rates[ic->ic_curmode].
1479 1478 ir_rates[ic->ic_fixed_rate];
1480 1479 } else
1481 1480 rate = ni->in_rates.ir_rates[ni->in_txrate];
1482 1481 if (rate == 0)
1483 1482 rate = 2; /* XXX should not happen */
1484 1483 rate &= IEEE80211_RATE_VAL;
1485 1484
1486 1485 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1487 1486 flags |= RT2661_TX_NEED_ACK;
1488 1487
1489 1488 dur = rt2661_txtime(RT2661_ACK_SIZE,
1490 1489 rt2661_ack_rate(ic, rate), ic->ic_flags) + sc->sifs;
1491 1490 *(uint16_t *)wh->i_dur = LE_16(dur);
1492 1491 }
1493 1492
1494 1493 bcopy(m->b_rptr, data->buf, pktlen);
1495 1494 rt2661_setup_tx_desc(sc, desc, flags, 0, pktlen, rate, 0);
1496 1495
1497 1496 (void) ddi_dma_sync(data->txdata_dma.dma_hdl,
1498 1497 0, pktlen,
1499 1498 DDI_DMA_SYNC_FORDEV);
1500 1499
1501 1500 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
1502 1501 ring->cur * RT2661_TX_DESC_SIZE,
1503 1502 RT2661_TX_DESC_SIZE,
1504 1503 DDI_DMA_SYNC_FORDEV);
1505 1504
1506 1505 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_send(): "
1507 1506 "sending data frame len=%u idx=%u rate=%u\n",
1508 1507 pktlen, ring->cur, rate);
1509 1508
1510 1509 /* kick Tx */
1511 1510 ring->queued++;
1512 1511 ring->cur = (ring->cur + 1) % RT2661_TX_RING_COUNT;
1513 1512 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << 0);
1514 1513
1515 1514 ic->ic_stats.is_tx_frags++;
1516 1515 ic->ic_stats.is_tx_bytes += pktlen;
1517 1516 fail3:
1518 1517 ieee80211_free_node(ni);
1519 1518 fail2:
1520 1519 freemsg(m);
1521 1520 fail1:
1522 1521 if (err == DDI_SUCCESS)
1523 1522 freemsg(mp);
1524 1523 mutex_exit(&sc->sc_txlock);
1525 1524 return (err);
1526 1525 }
1527 1526
1528 1527 /*ARGSUSED*/
1529 1528 static int
1530 1529 rt2661_mgmt_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
1531 1530 {
1532 1531 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1533 1532 struct rt2661_tx_ring *ring;
1534 1533 struct rt2661_tx_desc *desc;
1535 1534 struct rt2661_tx_data *data;
1536 1535 struct ieee80211_frame *wh;
1537 1536 struct ieee80211_node *ni;
1538 1537
1539 1538 int err, off, rate;
1540 1539 int mblen, pktlen;
1541 1540 mblk_t *m, *m0;
1542 1541 uint16_t dur;
1543 1542 uint32_t flags = 0;
1544 1543
1545 1544 if ((!RT2661_IS_RUNNING(sc)) || RT2661_IS_SUSPEND(sc)) {
1546 1545 err = ENXIO;
1547 1546 goto fail1;
1548 1547 }
1549 1548
1550 1549 ring = &sc->mgtq;
1551 1550 err = DDI_SUCCESS;
1552 1551
1553 1552 if (ring->queued >= RT2661_MGT_RING_COUNT) {
1554 1553 sc->sc_tx_nobuf++;
1555 1554 err = ENOMEM;
1556 1555 goto fail1;
1557 1556 }
1558 1557
1559 1558 m = allocb(msgdsize(mp) + 32, BPRI_MED);
1560 1559 if (m == NULL) {
1561 1560 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_mgmt_send():"
1562 1561 "can't alloc mblk.\n");
1563 1562 err = DDI_FAILURE;
1564 1563 goto fail1;
1565 1564 }
1566 1565
1567 1566 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
1568 1567 mblen = MBLKL(m0);
1569 1568 (void) bcopy(m0->b_rptr, m->b_rptr + off, mblen);
1570 1569 off += mblen;
1571 1570 }
1572 1571 m->b_wptr += off;
1573 1572
1574 1573 wh = (struct ieee80211_frame *)m->b_rptr;
1575 1574 ni = ieee80211_find_txnode(ic, wh->i_addr1);
1576 1575 if (ni == NULL) {
1577 1576 err = DDI_FAILURE;
1578 1577 sc->sc_tx_err++;
1579 1578 goto fail2;
1580 1579 }
1581 1580
1582 1581 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1583 1582 struct ieee80211_key *k;
1584 1583 k = ieee80211_crypto_encap(ic, m);
1585 1584 if (k == NULL) {
1586 1585 sc->sc_tx_err++;
1587 1586 err = DDI_FAILURE;
1588 1587 goto fail3;
1589 1588 }
1590 1589 /* packet header may have moved, reset our local pointer */
1591 1590 wh = (struct ieee80211_frame *)m->b_rptr;
1592 1591 }
1593 1592
1594 1593 pktlen = msgdsize(m);
1595 1594
1596 1595 desc = &ring->desc[ring->cur];
1597 1596 data = &ring->data[ring->cur];
1598 1597 data->ni = ieee80211_ref_node(ni);
1599 1598
1600 1599 /* send mgt frames at the lowest available rate */
1601 1600 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
1602 1601
1603 1602 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1604 1603 flags |= RT2661_TX_NEED_ACK;
1605 1604
1606 1605 dur = rt2661_txtime(RT2661_ACK_SIZE,
1607 1606 rate, ic->ic_flags) + sc->sifs;
1608 1607 *(uint16_t *)wh->i_dur = LE_16(dur);
1609 1608
1610 1609 /* tell hardware to add timestamp in probe responses */
1611 1610 if ((wh->i_fc[0] &
1612 1611 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1613 1612 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1614 1613 flags |= RT2661_TX_TIMESTAMP;
1615 1614 }
1616 1615
1617 1616 bcopy(m->b_rptr, data->buf, pktlen);
1618 1617 rt2661_setup_tx_desc(sc, desc, flags, 0, pktlen, rate, RT2661_QID_MGT);
1619 1618
1620 1619 (void) ddi_dma_sync(data->txdata_dma.dma_hdl,
1621 1620 0, pktlen,
1622 1621 DDI_DMA_SYNC_FORDEV);
1623 1622
1624 1623 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
1625 1624 ring->cur * RT2661_TX_DESC_SIZE,
1626 1625 RT2661_TX_DESC_SIZE,
1627 1626 DDI_DMA_SYNC_FORDEV);
1628 1627
1629 1628 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_mgmt_send(): "
1630 1629 "sending mgmt frame len=%u idx=%u rate=%u\n",
1631 1630 pktlen, ring->cur, rate);
1632 1631
1633 1632 /* kick Tx */
1634 1633 ring->queued++;
1635 1634 ring->cur = (ring->cur + 1) % RT2661_MGT_RING_COUNT;
1636 1635 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1637 1636
1638 1637 ic->ic_stats.is_tx_frags++;
1639 1638 ic->ic_stats.is_tx_bytes += pktlen;
1640 1639
1641 1640 fail3:
1642 1641 ieee80211_free_node(ni);
1643 1642 fail2:
1644 1643 freemsg(m);
1645 1644 fail1:
1646 1645 freemsg(mp);
1647 1646 return (err);
1648 1647 }
1649 1648
1650 1649 static void
1651 1650 rt2661_amrr_node_init(const struct rt2661_amrr *amrr,
1652 1651 struct rt2661_amrr_node *amn)
1653 1652 {
1654 1653 amn->amn_success = 0;
1655 1654 amn->amn_recovery = 0;
1656 1655 amn->amn_txcnt = amn->amn_retrycnt = 0;
1657 1656 amn->amn_success_threshold = amrr->amrr_min_success_threshold;
1658 1657 }
1659 1658
1660 1659 static void
1661 1660 rt2661_amrr_choose(struct rt2661_amrr *amrr, struct ieee80211_node *ni,
1662 1661 struct rt2661_amrr_node *amn)
1663 1662 {
1664 1663 #define RV(rate) ((rate) & IEEE80211_RATE_VAL)
1665 1664 #define is_success(amn) \
1666 1665 ((amn)->amn_retrycnt < (amn)->amn_txcnt / 10)
1667 1666 #define is_failure(amn) \
1668 1667 ((amn)->amn_retrycnt > (amn)->amn_txcnt / 3)
1669 1668 #define is_enough(amn) \
1670 1669 ((amn)->amn_txcnt > 10)
1671 1670 #define is_min_rate(ni) \
1672 1671 ((ni)->in_txrate == 0)
1673 1672 #define is_max_rate(ni) \
1674 1673 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1)
1675 1674 #define increase_rate(ni) \
1676 1675 ((ni)->in_txrate++)
1677 1676 #define decrease_rate(ni) \
1678 1677 ((ni)->in_txrate--)
1679 1678 #define reset_cnt(amn) \
1680 1679 { (amn)->amn_txcnt = (amn)->amn_retrycnt = 0; }
1681 1680
1682 1681 int need_change = 0;
1683 1682
1684 1683 if (is_success(amn) && is_enough(amn)) {
1685 1684 amn->amn_success++;
1686 1685 if (amn->amn_success >= amn->amn_success_threshold &&
1687 1686 !is_max_rate(ni)) {
1688 1687 amn->amn_recovery = 1;
1689 1688 amn->amn_success = 0;
1690 1689 increase_rate(ni);
1691 1690 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_amrr_choose(): "
1692 1691 "increase rate = %d, #tx = %d, #retries = %d\n",
1693 1692 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1694 1693 amn->amn_txcnt, amn->amn_retrycnt);
1695 1694 need_change = 1;
1696 1695 } else
1697 1696 amn->amn_recovery = 0;
1698 1697 } else if (is_failure(amn)) {
1699 1698 amn->amn_success = 0;
1700 1699 if (!is_min_rate(ni)) {
1701 1700 if (amn->amn_recovery) {
1702 1701 amn->amn_success_threshold *= 2;
1703 1702 if (amn->amn_success_threshold >
1704 1703 amrr->amrr_max_success_threshold)
1705 1704 amn->amn_success_threshold =
1706 1705 amrr->amrr_max_success_threshold;
1707 1706 } else {
1708 1707 amn->amn_success_threshold =
1709 1708 amrr->amrr_min_success_threshold;
1710 1709 }
1711 1710 decrease_rate(ni);
1712 1711 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_amrr_choose(): "
1713 1712 "decrease rate = %d, #tx = %d, #retries = %d\n",
1714 1713 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1715 1714 amn->amn_txcnt, amn->amn_retrycnt);
1716 1715 need_change = 1;
1717 1716 }
1718 1717 amn->amn_recovery = 0;
1719 1718 }
1720 1719
1721 1720 if (is_enough(amn) || need_change)
1722 1721 reset_cnt(amn);
1723 1722 #undef RV
1724 1723
1725 1724 }
1726 1725
1727 1726 static void
1728 1727 rt2661_update_promisc(struct rt2661_softc *sc)
1729 1728 {
1730 1729 uint32_t tmp;
1731 1730
1732 1731 tmp = RT2661_READ(sc, RT2661_TXRX_CSR0);
1733 1732
1734 1733 tmp &= ~RT2661_DROP_NOT_TO_ME;
1735 1734 if (!(sc->sc_rcr & RT2661_RCR_PROMISC))
1736 1735 tmp |= RT2661_DROP_NOT_TO_ME;
1737 1736
1738 1737 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1739 1738 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_update_promisc(): "
1740 1739 "%s promiscuous mode\n",
1741 1740 (sc->sc_rcr & RT2661_RCR_PROMISC) ? "entering" : "leaving");
1742 1741 }
1743 1742
1744 1743 static void
1745 1744 rt2661_updateslot(struct ieee80211com *ic, int onoff)
1746 1745 {
1747 1746 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1748 1747 uint8_t slottime;
1749 1748 uint32_t tmp;
1750 1749
1751 1750 slottime = (onoff ? 9 : 20);
1752 1751
1753 1752 tmp = RT2661_READ(sc, RT2661_MAC_CSR9);
1754 1753 tmp = (tmp & ~0xff) | slottime;
1755 1754 RT2661_WRITE(sc, RT2661_MAC_CSR9, tmp);
1756 1755
1757 1756 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_updateslot(): "
1758 1757 "setting slot time to %uus\n", slottime);
1759 1758 }
1760 1759
1761 1760 static void
1762 1761 rt2661_set_slottime(struct rt2661_softc *sc)
1763 1762 {
1764 1763 struct ieee80211com *ic = &sc->sc_ic;
1765 1764 uint8_t slottime;
1766 1765 uint32_t tmp;
1767 1766
1768 1767 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1769 1768
1770 1769 tmp = RT2661_READ(sc, RT2661_MAC_CSR9);
1771 1770 tmp = (tmp & ~0xff) | slottime;
1772 1771 RT2661_WRITE(sc, RT2661_MAC_CSR9, tmp);
1773 1772
1774 1773 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_set_slottime(): "
1775 1774 "setting slot time to %uus\n", slottime);
1776 1775 }
1777 1776
1778 1777
1779 1778 /*
1780 1779 * Enable multi-rate retries for frames sent at OFDM rates.
1781 1780 * In 802.11b/g mode, allow fallback to CCK rates.
1782 1781 */
1783 1782 static void
1784 1783 rt2661_enable_mrr(struct rt2661_softc *sc)
1785 1784 {
1786 1785 struct ieee80211com *ic = &sc->sc_ic;
1787 1786 uint32_t tmp;
1788 1787
1789 1788 tmp = RT2661_READ(sc, RT2661_TXRX_CSR4);
1790 1789
1791 1790 tmp &= ~RT2661_MRR_CCK_FALLBACK;
1792 1791 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
1793 1792 tmp |= RT2661_MRR_CCK_FALLBACK;
1794 1793 tmp |= RT2661_MRR_ENABLED;
1795 1794
1796 1795 RT2661_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1797 1796 }
1798 1797
1799 1798 static void
1800 1799 rt2661_set_txpreamble(struct rt2661_softc *sc)
1801 1800 {
1802 1801 uint32_t tmp;
1803 1802
1804 1803 tmp = RT2661_READ(sc, RT2661_TXRX_CSR4);
1805 1804
1806 1805 tmp &= ~RT2661_SHORT_PREAMBLE;
1807 1806 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1808 1807 tmp |= RT2661_SHORT_PREAMBLE;
1809 1808
1810 1809 RT2661_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1811 1810 }
1812 1811
1813 1812 static void
1814 1813 rt2661_set_basicrates(struct rt2661_softc *sc)
1815 1814 {
1816 1815 struct ieee80211com *ic = &sc->sc_ic;
1817 1816
1818 1817 /* update basic rate set */
1819 1818 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1820 1819 /* 11b basic rates: 1, 2Mbps */
1821 1820 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0x3);
1822 1821 } else if (ic->ic_curmode == IEEE80211_MODE_11A) {
1823 1822 /* 11a basic rates: 6, 12, 24Mbps */
1824 1823 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0x150);
1825 1824 } else {
1826 1825 /* 11b/g basic rates: 1, 2, 5.5, 11Mbps */
1827 1826 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0xf);
1828 1827 }
1829 1828 }
1830 1829
1831 1830 static void
1832 1831 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
1833 1832 {
1834 1833 uint32_t tmp;
1835 1834
1836 1835 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
1837 1836 RT2661_WRITE(sc, RT2661_MAC_CSR4, tmp);
1838 1837
1839 1838 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
1840 1839 RT2661_WRITE(sc, RT2661_MAC_CSR5, tmp);
1841 1840 }
1842 1841
1843 1842 /*
1844 1843 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
1845 1844 * and HostAP operating modes.
1846 1845 */
1847 1846 static void
1848 1847 rt2661_enable_tsf_sync(struct rt2661_softc *sc)
1849 1848 {
1850 1849 struct ieee80211com *ic = &sc->sc_ic;
1851 1850 uint32_t tmp;
1852 1851
1853 1852 tmp = RT2661_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
1854 1853
1855 1854 /* set beacon interval (in 1/16ms unit) */
1856 1855 tmp |= ic->ic_bss->in_intval * 16;
1857 1856
1858 1857 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
1859 1858 if (ic->ic_opmode == IEEE80211_M_STA)
1860 1859 tmp |= RT2661_TSF_MODE(1);
1861 1860
1862 1861 RT2661_WRITE(sc, RT2661_TXRX_CSR9, tmp);
1863 1862 }
1864 1863
1865 1864
1866 1865 static void
1867 1866 rt2661_next_scan(void *arg)
1868 1867 {
1869 1868 struct rt2661_softc *sc = arg;
1870 1869 struct ieee80211com *ic = &sc->sc_ic;
1871 1870
1872 1871 if (ic->ic_state == IEEE80211_S_SCAN)
1873 1872 (void) ieee80211_next_scan(ic);
1874 1873 }
1875 1874
1876 1875 static void
1877 1876 rt2661_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni)
1878 1877 {
1879 1878 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1880 1879 int i;
1881 1880
1882 1881 rt2661_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn);
1883 1882
1884 1883 /* set rate to some reasonable initial value */
1885 1884 i = ni->in_rates.ir_nrates - 1;
1886 1885 while (i > 0 && ((ni->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72))
1887 1886 i--;
1888 1887
1889 1888 ni->in_txrate = i;
1890 1889 }
1891 1890
1892 1891 static void
1893 1892 rt2661_iter_func(void *arg, struct ieee80211_node *ni)
1894 1893 {
1895 1894 struct rt2661_softc *sc = arg;
1896 1895 struct rt2661_node *rn = (struct rt2661_node *)ni;
1897 1896
1898 1897 rt2661_amrr_choose(&sc->amrr, ni, &rn->amn);
1899 1898
1900 1899 }
1901 1900
1902 1901 /*
1903 1902 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and
1904 1903 * false CCA count. This function is called periodically (every seconds) when
1905 1904 * in the RUN state. Values taken from the reference driver.
1906 1905 */
1907 1906 static void
1908 1907 rt2661_rx_tune(struct rt2661_softc *sc)
1909 1908 {
1910 1909 uint8_t bbp17;
1911 1910 uint16_t cca;
1912 1911 int lo, hi, dbm;
1913 1912
1914 1913 /*
1915 1914 * Tuning range depends on operating band and on the presence of an
1916 1915 * external low-noise amplifier.
1917 1916 */
1918 1917 lo = 0x20;
1919 1918 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
1920 1919 lo += 0x08;
1921 1920 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
1922 1921 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
1923 1922 lo += 0x10;
1924 1923 hi = lo + 0x20;
1925 1924
1926 1925 dbm = sc->avg_rssi;
1927 1926 /* retrieve false CCA count since last call (clear on read) */
1928 1927 cca = RT2661_READ(sc, RT2661_STA_CSR1) & 0xffff;
1929 1928
1930 1929 RWD_DEBUG(RT2661_DBG_INTR, "rwd: rt2661_rx_tune(): "
1931 1930 "RSSI=%ddBm false CCA=%d\n", dbm, cca);
1932 1931
1933 1932 if (dbm < -74) {
1934 1933 /* very bad RSSI, tune using false CCA count */
1935 1934 bbp17 = sc->bbp17; /* current value */
1936 1935
1937 1936 hi -= 2 * (-74 - dbm);
1938 1937 if (hi < lo)
1939 1938 hi = lo;
1940 1939
1941 1940 if (bbp17 > hi)
1942 1941 bbp17 = (uint8_t)hi;
1943 1942 else if (cca > 512)
1944 1943 bbp17 = (uint8_t)min(bbp17 + 1, hi);
1945 1944 else if (cca < 100)
1946 1945 bbp17 = (uint8_t)max(bbp17 - 1, lo);
1947 1946
1948 1947 } else if (dbm < -66) {
1949 1948 bbp17 = lo + 0x08;
1950 1949 } else if (dbm < -58) {
1951 1950 bbp17 = lo + 0x10;
1952 1951 } else if (dbm < -35) {
1953 1952 bbp17 = (uint8_t)hi;
1954 1953 } else { /* very good RSSI >= -35dBm */
1955 1954 bbp17 = 0x60; /* very low sensitivity */
1956 1955 }
1957 1956
1958 1957 if (bbp17 != sc->bbp17) {
1959 1958 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_rx_tune(): "
1960 1959 "BBP17 %x->%x\n", sc->bbp17, bbp17);
1961 1960 rt2661_bbp_write(sc, 17, bbp17);
1962 1961 sc->bbp17 = bbp17;
1963 1962 }
1964 1963 }
1965 1964
1966 1965 /*
1967 1966 * This function is called periodically (every 500ms) in RUN state to update
1968 1967 * various settings like rate control statistics or Rx sensitivity.
1969 1968 */
1970 1969 static void
1971 1970 rt2661_updatestats(void *arg)
1972 1971 {
1973 1972 struct rt2661_softc *sc = arg;
1974 1973 struct ieee80211com *ic = &sc->sc_ic;
1975 1974
1976 1975 if (ic->ic_opmode == IEEE80211_M_STA)
1977 1976 rt2661_iter_func(sc, ic->ic_bss);
1978 1977 else
1979 1978 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg);
1980 1979
1981 1980 /* update rx sensitivity every 1 sec */
1982 1981 if (++sc->ncalls & 1)
1983 1982 rt2661_rx_tune(sc);
1984 1983
1985 1984 sc->sc_rssadapt_id = timeout(rt2661_updatestats, (void *)sc,
1986 1985 drv_usectohz(200 * 1000));
1987 1986 }
1988 1987
1989 1988 static int
1990 1989 rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1991 1990 {
1992 1991 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1993 1992 enum ieee80211_state ostate;
1994 1993 struct ieee80211_node *ni;
1995 1994 uint32_t tmp;
1996 1995 int err;
1997 1996
1998 1997 RT2661_GLOCK(sc);
1999 1998
2000 1999 ostate = ic->ic_state;
2001 2000 sc->sc_ostate = ostate;
2002 2001
2003 2002 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt26661_newstate(): "
2004 2003 "%x -> %x\n", ostate, nstate);
2005 2004
2006 2005 if (sc->sc_scan_id != 0) {
2007 2006 (void) untimeout(sc->sc_scan_id);
2008 2007 sc->sc_scan_id = 0;
2009 2008 }
2010 2009
2011 2010 if (sc->sc_rssadapt_id) {
2012 2011 (void) untimeout(sc->sc_rssadapt_id);
2013 2012 sc->sc_rssadapt_id = 0;
2014 2013 }
2015 2014
2016 2015 switch (nstate) {
2017 2016 case IEEE80211_S_INIT:
2018 2017 if (ostate == IEEE80211_S_RUN) {
2019 2018 /* abort TSF synchronization */
2020 2019 tmp = RT2661_READ(sc, RT2661_TXRX_CSR9);
2021 2020 RT2661_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
2022 2021 }
2023 2022 break;
2024 2023 case IEEE80211_S_SCAN:
2025 2024 rt2661_set_chan(sc, ic->ic_curchan);
2026 2025 sc->sc_scan_id = timeout(rt2661_next_scan, (void *)sc,
2027 2026 drv_usectohz(200000));
2028 2027 break;
2029 2028 case IEEE80211_S_AUTH:
2030 2029 case IEEE80211_S_ASSOC:
2031 2030 rt2661_set_chan(sc, ic->ic_curchan);
2032 2031 break;
2033 2032 case IEEE80211_S_RUN:
2034 2033 rt2661_set_chan(sc, ic->ic_curchan);
2035 2034
2036 2035 ni = ic->ic_bss;
2037 2036 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2038 2037 rt2661_set_slottime(sc);
2039 2038 rt2661_enable_mrr(sc);
2040 2039 rt2661_set_txpreamble(sc);
2041 2040 rt2661_set_basicrates(sc);
2042 2041 rt2661_set_bssid(sc, ni->in_bssid);
2043 2042 }
2044 2043
2045 2044 if (ic->ic_opmode == IEEE80211_M_STA) {
2046 2045 /* fake a join to init the tx rate */
2047 2046 rt2661_newassoc(ic, ni);
2048 2047 }
2049 2048
2050 2049 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2051 2050 sc->ncalls = 0;
2052 2051 sc->avg_rssi = -95; /* reset EMA */
2053 2052 sc->sc_rssadapt_id = timeout(rt2661_updatestats,
2054 2053 (void *)sc, drv_usectohz(200 * 1000));
2055 2054 rt2661_enable_tsf_sync(sc);
2056 2055 }
2057 2056 break;
2058 2057 default:
2059 2058 break;
2060 2059 }
2061 2060
2062 2061 RT2661_GUNLOCK(sc);
2063 2062
2064 2063 err = sc->sc_newstate(ic, nstate, arg);
2065 2064 return (err);
2066 2065 }
2067 2066
2068 2067 /*ARGSUSED*/
2069 2068 static struct ieee80211_node *
2070 2069 rt2661_node_alloc(ieee80211com_t *ic)
2071 2070 {
2072 2071 struct rt2661_node *rn;
2073 2072
2074 2073 rn = kmem_zalloc(sizeof (struct rt2661_node), KM_SLEEP);
2075 2074 return ((rn != NULL) ? &rn->ni : NULL);
2076 2075 }
2077 2076
2078 2077 static void
2079 2078 rt2661_node_free(struct ieee80211_node *in)
2080 2079 {
2081 2080 struct ieee80211com *ic = in->in_ic;
2082 2081
2083 2082 ic->ic_node_cleanup(in);
2084 2083 if (in->in_wpa_ie != NULL)
2085 2084 ieee80211_free(in->in_wpa_ie);
2086 2085 kmem_free(in, sizeof (struct rt2661_node));
2087 2086 }
2088 2087
2089 2088 static void
2090 2089 rt2661_stop_locked(struct rt2661_softc *sc)
2091 2090 {
2092 2091 uint32_t tmp;
2093 2092
2094 2093 if (RT2661_IS_RUNNING(sc)) {
2095 2094 sc->sc_tx_timer = 0;
2096 2095
2097 2096 /* abort Tx (for all 5 Tx rings) */
2098 2097 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2099 2098
2100 2099 /* disable Rx (value remains after reset!) */
2101 2100 tmp = RT2661_READ(sc, RT2661_TXRX_CSR0);
2102 2101 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2103 2102
2104 2103 /* reset ASIC */
2105 2104 RT2661_WRITE(sc, RT2661_MAC_CSR1, 3);
2106 2105 RT2661_WRITE(sc, RT2661_MAC_CSR1, 0);
2107 2106
2108 2107 /* disable interrupts */
2109 2108 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
2110 2109 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2111 2110
2112 2111 /* clear any pending interrupt */
2113 2112 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2114 2113 RT2661_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2115 2114
2116 2115 /* reset Tx and Rx rings */
2117 2116 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2118 2117 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2119 2118 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2120 2119 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2121 2120 rt2661_reset_tx_ring(sc, &sc->mgtq);
2122 2121 rt2661_reset_rx_ring(sc, &sc->rxq);
2123 2122 }
2124 2123 }
2125 2124
2126 2125 static void
2127 2126 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
2128 2127 {
2129 2128 uint32_t tmp;
2130 2129
2131 2130 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
2132 2131 RT2661_WRITE(sc, RT2661_MAC_CSR2, tmp);
2133 2132
2134 2133 tmp = addr[4] | addr[5] << 8 | 0xff << 16;
2135 2134 RT2661_WRITE(sc, RT2661_MAC_CSR3, tmp);
2136 2135 }
2137 2136
2138 2137 static uint8_t
2139 2138 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
2140 2139 {
2141 2140 uint32_t val;
2142 2141 int ntries;
2143 2142
2144 2143 for (ntries = 0; ntries < 100; ntries++) {
2145 2144 if (!(RT2661_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
2146 2145 break;
2147 2146 DELAY(1);
2148 2147 }
2149 2148 if (ntries == 100) {
2150 2149 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_bbp_read(): "
2151 2150 "could not read from BBP\n");
2152 2151 return (0);
2153 2152 }
2154 2153
2155 2154 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
2156 2155 RT2661_WRITE(sc, RT2661_PHY_CSR3, val);
2157 2156
2158 2157 for (ntries = 0; ntries < 100; ntries++) {
2159 2158 val = RT2661_READ(sc, RT2661_PHY_CSR3);
2160 2159 if (!(val & RT2661_BBP_BUSY))
2161 2160 return (val & 0xff);
2162 2161 DELAY(1);
2163 2162 }
2164 2163
2165 2164 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_bbp_read(): "
2166 2165 "could not read from BBP\n");
2167 2166 return (0);
2168 2167 }
2169 2168
2170 2169 static int
2171 2170 rt2661_bbp_init(struct rt2661_softc *sc)
2172 2171 {
2173 2172 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2174 2173
2175 2174 int i, ntries;
2176 2175 uint8_t val;
2177 2176
2178 2177 /* wait for BBP to be ready */
2179 2178 for (ntries = 0; ntries < 100; ntries++) {
2180 2179 val = rt2661_bbp_read(sc, 0);
2181 2180 if (val != 0 && val != 0xff)
2182 2181 break;
2183 2182 DELAY(100);
2184 2183 }
2185 2184 if (ntries == 100) {
2186 2185 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_bbp_init(): "
2187 2186 "timeout waiting for BBP\n");
2188 2187 return (RT2661_FAILURE);
2189 2188 }
2190 2189
2191 2190 /* initialize BBP registers to default values */
2192 2191 for (i = 0; i < N(rt2661_def_bbp); i++) {
2193 2192 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2194 2193 rt2661_def_bbp[i].val);
2195 2194 }
2196 2195
2197 2196 /* write vendor-specific BBP values (from EEPROM) */
2198 2197 for (i = 0; i < 16; i++) {
2199 2198 if (sc->bbp_prom[i].reg == 0)
2200 2199 continue;
2201 2200 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2202 2201 }
2203 2202
2204 2203 return (RT2661_SUCCESS);
2205 2204 #undef N
2206 2205 }
2207 2206
2208 2207 static void
2209 2208 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
2210 2209 {
2211 2210 uint32_t tmp;
2212 2211 int ntries;
2213 2212
2214 2213 for (ntries = 0; ntries < 100; ntries++) {
2215 2214 if (!(RT2661_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
2216 2215 break;
2217 2216 DELAY(1);
2218 2217 }
2219 2218 if (ntries == 100) {
2220 2219 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_bbp_write(): "
2221 2220 "could not write to BBP\n");
2222 2221 return;
2223 2222 }
2224 2223
2225 2224 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
2226 2225 RT2661_WRITE(sc, RT2661_PHY_CSR3, tmp);
2227 2226
2228 2227 RWD_DEBUG(RT2661_DBG_HW, "rwd: rt2661_bbp_write(): "
2229 2228 "BBP R%u <- 0x%02x\n", reg, val);
2230 2229 }
2231 2230
2232 2231 /*
2233 2232 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
2234 2233 * driver.
2235 2234 */
2236 2235 static void
2237 2236 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
2238 2237 {
2239 2238 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
2240 2239 uint32_t tmp;
2241 2240
2242 2241 /* update all BBP registers that depend on the band */
2243 2242 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
2244 2243 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
2245 2244 if (IEEE80211_IS_CHAN_5GHZ(c)) {
2246 2245 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
2247 2246 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
2248 2247 }
2249 2248 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2250 2249 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2251 2250 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
2252 2251 }
2253 2252
2254 2253 sc->bbp17 = bbp17;
2255 2254 rt2661_bbp_write(sc, 17, bbp17);
2256 2255 rt2661_bbp_write(sc, 96, bbp96);
2257 2256 rt2661_bbp_write(sc, 104, bbp104);
2258 2257
2259 2258 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2260 2259 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2261 2260 rt2661_bbp_write(sc, 75, 0x80);
2262 2261 rt2661_bbp_write(sc, 86, 0x80);
2263 2262 rt2661_bbp_write(sc, 88, 0x80);
2264 2263 }
2265 2264
2266 2265 rt2661_bbp_write(sc, 35, bbp35);
2267 2266 rt2661_bbp_write(sc, 97, bbp97);
2268 2267 rt2661_bbp_write(sc, 98, bbp98);
2269 2268
2270 2269 tmp = RT2661_READ(sc, RT2661_PHY_CSR0);
2271 2270 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
2272 2271 if (IEEE80211_IS_CHAN_2GHZ(c))
2273 2272 tmp |= RT2661_PA_PE_2GHZ;
2274 2273 else
2275 2274 tmp |= RT2661_PA_PE_5GHZ;
2276 2275 RT2661_WRITE(sc, RT2661_PHY_CSR0, tmp);
2277 2276
2278 2277 /* 802.11a uses a 16 microseconds short interframe space */
2279 2278 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10;
2280 2279 }
2281 2280
2282 2281 static void
2283 2282 rt2661_select_antenna(struct rt2661_softc *sc)
2284 2283 {
2285 2284 uint8_t bbp4, bbp77;
2286 2285 uint32_t tmp;
2287 2286
2288 2287 bbp4 = rt2661_bbp_read(sc, 4);
2289 2288 bbp77 = rt2661_bbp_read(sc, 77);
2290 2289
2291 2290 /* TBD */
2292 2291
2293 2292 /* make sure Rx is disabled before switching antenna */
2294 2293 tmp = RT2661_READ(sc, RT2661_TXRX_CSR0);
2295 2294 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2296 2295
2297 2296 rt2661_bbp_write(sc, 4, bbp4);
2298 2297 rt2661_bbp_write(sc, 77, bbp77);
2299 2298
2300 2299 /* restore Rx filter */
2301 2300 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2302 2301 }
2303 2302
2304 2303 static void
2305 2304 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
2306 2305 {
2307 2306 uint32_t tmp;
2308 2307 int ntries;
2309 2308
2310 2309 for (ntries = 0; ntries < 100; ntries++) {
2311 2310 if (!(RT2661_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
2312 2311 break;
2313 2312 DELAY(1);
2314 2313 }
2315 2314 if (ntries == 100) {
2316 2315 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_rf_write(): "
2317 2316 "could not write to RF\n");
2318 2317 return;
2319 2318 }
2320 2319
2321 2320 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
2322 2321 (reg & 3);
2323 2322 RT2661_WRITE(sc, RT2661_PHY_CSR4, tmp);
2324 2323
2325 2324 /* remember last written value in sc */
2326 2325 sc->rf_regs[reg] = val;
2327 2326
2328 2327 RWD_DEBUG(RT2661_DBG_FW, "rwd: rt2661_rf_write(): "
2329 2328 "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);
2330 2329 }
2331 2330
2332 2331 static void
2333 2332 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
2334 2333 {
2335 2334 struct ieee80211com *ic = &sc->sc_ic;
2336 2335 const struct rfprog *rfprog;
2337 2336 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT;
2338 2337 int8_t power;
2339 2338 uint_t i, chan;
2340 2339
2341 2340 chan = ieee80211_chan2ieee(ic, c);
2342 2341 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
2343 2342 return;
2344 2343
2345 2344 /* select the appropriate RF settings based on what EEPROM says */
2346 2345 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
2347 2346
2348 2347 /* find the settings for this channel (we know it exists) */
2349 2348 i = 0;
2350 2349 while (rfprog[i].chan != chan)
2351 2350 i++;
2352 2351
2353 2352 power = sc->txpow[i];
2354 2353 if (power < 0) {
2355 2354 bbp94 += power;
2356 2355 power = 0;
2357 2356 } else if (power > 31) {
2358 2357 bbp94 += power - 31;
2359 2358 power = 31;
2360 2359 }
2361 2360
2362 2361 /*
2363 2362 * If we are switching from the 2GHz band to the 5GHz band or
2364 2363 * vice-versa, BBP registers need to be reprogrammed.
2365 2364 */
2366 2365 if (ic->ic_flags != sc->sc_curchan->ich_flags) {
2367 2366 rt2661_select_band(sc, c);
2368 2367 rt2661_select_antenna(sc);
2369 2368 }
2370 2369 sc->sc_curchan = c;
2371 2370
2372 2371 rt2661_rf_write(sc, RT2661_RF1, rfprog[i].r1);
2373 2372 rt2661_rf_write(sc, RT2661_RF2, rfprog[i].r2);
2374 2373 rt2661_rf_write(sc, RT2661_RF3, rfprog[i].r3 | power << 7);
2375 2374 rt2661_rf_write(sc, RT2661_RF4, rfprog[i].r4 | sc->rffreq << 10);
2376 2375
2377 2376 DELAY(200);
2378 2377
2379 2378 rt2661_rf_write(sc, RT2661_RF1, rfprog[i].r1);
2380 2379 rt2661_rf_write(sc, RT2661_RF2, rfprog[i].r2);
2381 2380 rt2661_rf_write(sc, RT2661_RF3, rfprog[i].r3 | power << 7 | 1);
2382 2381 rt2661_rf_write(sc, RT2661_RF4, rfprog[i].r4 | sc->rffreq << 10);
2383 2382
2384 2383 DELAY(200);
2385 2384
2386 2385 rt2661_rf_write(sc, RT2661_RF1, rfprog[i].r1);
2387 2386 rt2661_rf_write(sc, RT2661_RF2, rfprog[i].r2);
2388 2387 rt2661_rf_write(sc, RT2661_RF3, rfprog[i].r3 | power << 7);
2389 2388 rt2661_rf_write(sc, RT2661_RF4, rfprog[i].r4 | sc->rffreq << 10);
2390 2389
2391 2390 /* enable smart mode for MIMO-capable RFs */
2392 2391 bbp3 = rt2661_bbp_read(sc, 3);
2393 2392
2394 2393 bbp3 &= ~RT2661_SMART_MODE;
2395 2394 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
2396 2395 bbp3 |= RT2661_SMART_MODE;
2397 2396
2398 2397 rt2661_bbp_write(sc, 3, bbp3);
2399 2398
2400 2399 if (bbp94 != RT2661_BBPR94_DEFAULT)
2401 2400 rt2661_bbp_write(sc, 94, bbp94);
2402 2401
2403 2402 /* 5GHz radio needs a 1ms delay here */
2404 2403 if (IEEE80211_IS_CHAN_5GHZ(c))
2405 2404 DELAY(1000);
2406 2405 }
2407 2406
2408 2407 static int
2409 2408 rt2661_init(struct rt2661_softc *sc)
2410 2409 {
2411 2410 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2412 2411
2413 2412 struct ieee80211com *ic = &sc->sc_ic;
2414 2413 uint32_t tmp, sta[3], *fptr;
2415 2414 int i, err, off, ntries;
2416 2415
2417 2416 RT2661_GLOCK(sc);
2418 2417
2419 2418 rt2661_stop_locked(sc);
2420 2419
2421 2420 if (!RT2661_IS_FWLOADED(sc)) {
2422 2421 err = rt2661_load_microcode(sc, ucode, usize);
2423 2422 if (err != RT2661_SUCCESS) {
2424 2423 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2425 2424 "could not load 8051 microcode\n");
2426 2425 return (DDI_FAILURE);
2427 2426 }
2428 2427 sc->sc_flags |= RT2661_F_FWLOADED;
2429 2428 }
2430 2429
2431 2430 /* initialize Tx rings */
2432 2431 RT2661_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].paddr);
2433 2432 RT2661_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].paddr);
2434 2433 RT2661_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].paddr);
2435 2434 RT2661_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].paddr);
2436 2435
2437 2436 /* initialize Mgt ring */
2438 2437 RT2661_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.paddr);
2439 2438
2440 2439 /* initialize Rx ring */
2441 2440 RT2661_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.paddr);
2442 2441
2443 2442 /* initialize Tx rings sizes */
2444 2443 RT2661_WRITE(sc, RT2661_TX_RING_CSR0,
2445 2444 RT2661_TX_RING_COUNT << 24 |
2446 2445 RT2661_TX_RING_COUNT << 16 |
2447 2446 RT2661_TX_RING_COUNT << 8 |
2448 2447 RT2661_TX_RING_COUNT);
2449 2448
2450 2449 RT2661_WRITE(sc, RT2661_TX_RING_CSR1,
2451 2450 RT2661_TX_DESC_WSIZE << 16 |
2452 2451 RT2661_TX_RING_COUNT << 8 |
2453 2452 RT2661_MGT_RING_COUNT);
2454 2453
2455 2454 /* initialize Rx rings */
2456 2455 RT2661_WRITE(sc, RT2661_RX_RING_CSR,
2457 2456 RT2661_RX_DESC_BACK << 16 |
2458 2457 RT2661_RX_DESC_WSIZE << 8 |
2459 2458 RT2661_RX_RING_COUNT);
2460 2459
2461 2460 /* XXX: some magic here */
2462 2461 RT2661_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2463 2462
2464 2463 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */
2465 2464 RT2661_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2466 2465
2467 2466 /* load base address of Rx ring */
2468 2467 RT2661_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2469 2468
2470 2469 /* initialize MAC registers to default values */
2471 2470 for (i = 0; i < N(rt2661_def_mac); i++)
2472 2471 RT2661_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2473 2472
2474 2473 rt2661_set_macaddr(sc, ic->ic_macaddr);
2475 2474
2476 2475 /* set host ready */
2477 2476 RT2661_WRITE(sc, RT2661_MAC_CSR1, 3);
2478 2477 RT2661_WRITE(sc, RT2661_MAC_CSR1, 0);
2479 2478
2480 2479 /* wait for BBP/RF to wakeup */
2481 2480 for (ntries = 0; ntries < 1000; ntries++) {
2482 2481 if (RT2661_READ(sc, RT2661_MAC_CSR12) & 8)
2483 2482 break;
2484 2483 DELAY(1000);
2485 2484 }
2486 2485 if (ntries == 1000) {
2487 2486 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2488 2487 "timeout waiting for BBP/RF to wakeup\n");
2489 2488 rt2661_stop_locked(sc);
2490 2489 RT2661_GUNLOCK(sc);
2491 2490 return (DDI_FAILURE);
2492 2491 }
2493 2492
2494 2493 if (rt2661_bbp_init(sc) != RT2661_SUCCESS) {
2495 2494 rt2661_stop_locked(sc);
2496 2495 RT2661_GUNLOCK(sc);
2497 2496 return (DDI_FAILURE);
2498 2497 }
2499 2498
2500 2499 /* select default channel */
2501 2500 sc->sc_curchan = ic->ic_bss->in_chan = ic->ic_curchan;
2502 2501 rt2661_select_band(sc, sc->sc_curchan);
2503 2502 rt2661_select_antenna(sc);
2504 2503 rt2661_set_chan(sc, sc->sc_curchan);
2505 2504
2506 2505 /* update Rx filter */
2507 2506 tmp = RT2661_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2508 2507
2509 2508 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
2510 2509 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2511 2510 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
2512 2511 RT2661_DROP_ACKCTS;
2513 2512 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
2514 2513 tmp |= RT2661_DROP_TODS;
2515 2514 if (!(sc->sc_rcr & RT2661_RCR_PROMISC))
2516 2515 tmp |= RT2661_DROP_NOT_TO_ME;
2517 2516 }
2518 2517
2519 2518 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2520 2519
2521 2520 /* clear STA registers */
2522 2521 off = RT2661_STA_CSR0;
2523 2522 fptr = sta;
2524 2523 for (i = 0; i < N(sta); i++) {
2525 2524 *fptr = RT2661_MEM_READ1(sc, off++);
2526 2525 }
2527 2526
2528 2527 /* initialize ASIC */
2529 2528 RT2661_WRITE(sc, RT2661_MAC_CSR1, 4);
2530 2529
2531 2530 /* clear any pending interrupt */
2532 2531 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2533 2532
2534 2533 /* enable interrupts */
2535 2534 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2536 2535 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2537 2536
2538 2537 /* kick Rx */
2539 2538 RT2661_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2540 2539 RT2661_GUNLOCK(sc);
2541 2540
2542 2541 #undef N
2543 2542 return (DDI_SUCCESS);
2544 2543 }
2545 2544
2546 2545 static void
2547 2546 rt2661_stop(struct rt2661_softc *sc)
2548 2547 {
2549 2548 if (!RT2661_IS_FASTREBOOT(sc))
2550 2549 RT2661_GLOCK(sc);
2551 2550 rt2661_stop_locked(sc);
2552 2551 if (!RT2661_IS_FASTREBOOT(sc))
2553 2552 RT2661_GUNLOCK(sc);
2554 2553 }
2555 2554
2556 2555 static int
2557 2556 rt2661_m_start(void *arg)
2558 2557 {
2559 2558 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2560 2559 struct ieee80211com *ic = &sc->sc_ic;
2561 2560 int err;
2562 2561
2563 2562 err = rt2661_init(sc);
2564 2563 if (err != DDI_SUCCESS) {
2565 2564 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_m_start():"
2566 2565 "Hardware initialization failed\n");
2567 2566 goto fail1;
2568 2567 }
2569 2568
2570 2569 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2571 2570
2572 2571 RT2661_GLOCK(sc);
2573 2572 sc->sc_flags |= RT2661_F_RUNNING;
2574 2573 RT2661_GUNLOCK(sc);
2575 2574
2576 2575 return (DDI_SUCCESS);
2577 2576 fail1:
2578 2577 rt2661_stop(sc);
2579 2578 return (err);
2580 2579 }
2581 2580
2582 2581 static void
2583 2582 rt2661_m_stop(void *arg)
2584 2583 {
2585 2584 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2586 2585
2587 2586 (void) rt2661_stop(sc);
2588 2587
2589 2588 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2590 2589
2591 2590 RT2661_GLOCK(sc);
2592 2591 sc->sc_flags &= ~RT2661_F_RUNNING;
2593 2592 RT2661_GUNLOCK(sc);
2594 2593 }
2595 2594
2596 2595 static void
2597 2596 rt2661_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2598 2597 {
2599 2598 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2600 2599 struct ieee80211com *ic = &sc->sc_ic;
2601 2600 int err;
2602 2601
2603 2602 err = ieee80211_ioctl(ic, wq, mp);
2604 2603 RT2661_GLOCK(sc);
2605 2604 if (err == ENETRESET) {
2606 2605 if (ic->ic_des_esslen) {
2607 2606 if (RT2661_IS_RUNNING(sc)) {
2608 2607 RT2661_GUNLOCK(sc);
2609 2608 (void) rt2661_init(sc);
2610 2609 (void) ieee80211_new_state(ic,
2611 2610 IEEE80211_S_SCAN, -1);
2612 2611 RT2661_GLOCK(sc);
2613 2612 }
2614 2613 }
2615 2614 }
2616 2615 RT2661_GUNLOCK(sc);
2617 2616 }
2618 2617
2619 2618 /*
2620 2619 * Call back function for get/set proporty
2621 2620 */
2622 2621 static int
2623 2622 rt2661_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2624 2623 uint_t wldp_length, void *wldp_buf)
2625 2624 {
2626 2625 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2627 2626 int err = 0;
2628 2627
2629 2628 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2630 2629 wldp_length, wldp_buf);
2631 2630
2632 2631 return (err);
2633 2632 }
2634 2633
2635 2634 static void
2636 2635 rt2661_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2637 2636 mac_prop_info_handle_t mph)
2638 2637 {
2639 2638 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2640 2639
2641 2640 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, mph);
2642 2641 }
2643 2642
2644 2643 static int
2645 2644 rt2661_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2646 2645 uint_t wldp_length, const void *wldp_buf)
2647 2646 {
2648 2647 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2649 2648 ieee80211com_t *ic = &sc->sc_ic;
2650 2649 int err;
2651 2650
2652 2651 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
2653 2652 wldp_buf);
2654 2653 RT2661_GLOCK(sc);
2655 2654 if (err == ENETRESET) {
2656 2655 if (ic->ic_des_esslen) {
2657 2656 if (RT2661_IS_RUNNING(sc)) {
2658 2657 RT2661_GUNLOCK(sc);
2659 2658 (void) rt2661_init(sc);
2660 2659 (void) ieee80211_new_state(ic,
2661 2660 IEEE80211_S_SCAN, -1);
2662 2661 RT2661_GLOCK(sc);
2663 2662 }
2664 2663 }
2665 2664 err = 0;
2666 2665 }
2667 2666 RT2661_GUNLOCK(sc);
2668 2667 return (err);
2669 2668 }
2670 2669
2671 2670 static mblk_t *
2672 2671 rt2661_m_tx(void *arg, mblk_t *mp)
2673 2672 {
2674 2673 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2675 2674 struct ieee80211com *ic = &sc->sc_ic;
2676 2675 mblk_t *next;
2677 2676
2678 2677 if (RT2661_IS_SUSPEND(sc)) {
2679 2678 freemsgchain(mp);
2680 2679 return (NULL);
2681 2680 }
2682 2681
2683 2682 /*
2684 2683 * No data frames go out unless we're associated; this
2685 2684 * should not happen as the 802.11 layer does not enable
2686 2685 * the xmit queue until we enter the RUN state.
2687 2686 */
2688 2687 if (ic->ic_state != IEEE80211_S_RUN) {
2689 2688 RWD_DEBUG(RT2661_DBG_TX, "rwd: rt2661_tx_data(): "
2690 2689 "discard, state %u\n", ic->ic_state);
2691 2690 freemsgchain(mp);
2692 2691 return (NULL);
2693 2692 }
2694 2693
2695 2694 while (mp != NULL) {
2696 2695 next = mp->b_next;
2697 2696 mp->b_next = NULL;
2698 2697 if (rt2661_send(ic, mp) !=
2699 2698 DDI_SUCCESS) {
2700 2699 mp->b_next = next;
2701 2700 break;
2702 2701 }
2703 2702 mp = next;
2704 2703 }
2705 2704 return (mp);
2706 2705 }
2707 2706
2708 2707 /*ARGSUSED*/
2709 2708 static int
2710 2709 rt2661_m_unicst(void *arg, const uint8_t *macaddr)
2711 2710 {
2712 2711 return (ENOTSUP);
2713 2712 }
2714 2713
2715 2714 /*ARGSUSED*/
2716 2715 static int
2717 2716 rt2661_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
2718 2717 {
2719 2718 return (ENOTSUP);
2720 2719 }
2721 2720
2722 2721 /*ARGSUSED*/
2723 2722 static int
2724 2723 rt2661_m_promisc(void *arg, boolean_t on)
2725 2724 {
2726 2725 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2727 2726
2728 2727 if (on) {
2729 2728 sc->sc_rcr |= RT2661_RCR_PROMISC;
2730 2729 sc->sc_rcr |= RT2661_RCR_MULTI;
2731 2730 } else {
2732 2731 sc->sc_rcr &= ~RT2661_RCR_PROMISC;
2733 2732 sc->sc_rcr &= ~RT2661_RCR_MULTI;
2734 2733 }
2735 2734
2736 2735 rt2661_update_promisc(sc);
2737 2736 return (0);
2738 2737 }
2739 2738
2740 2739 static int
2741 2740 rt2661_m_stat(void *arg, uint_t stat, uint64_t *val)
2742 2741 {
2743 2742 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2744 2743 struct ieee80211com *ic = &sc->sc_ic;
2745 2744 struct ieee80211_node *ni = ic->ic_bss;
2746 2745 struct ieee80211_rateset *rs = &ni->in_rates;
2747 2746
2748 2747 RT2661_GLOCK(sc);
2749 2748 switch (stat) {
2750 2749 case MAC_STAT_IFSPEED:
2751 2750 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
2752 2751 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
2753 2752 : ic->ic_fixed_rate) / 2 * 1000000;
2754 2753 break;
2755 2754 case MAC_STAT_NOXMTBUF:
2756 2755 *val = sc->sc_tx_nobuf;
2757 2756 break;
2758 2757 case MAC_STAT_NORCVBUF:
2759 2758 *val = sc->sc_rx_nobuf;
2760 2759 break;
2761 2760 case MAC_STAT_IERRORS:
2762 2761 *val = sc->sc_rx_err;
2763 2762 break;
2764 2763 case MAC_STAT_RBYTES:
2765 2764 *val = ic->ic_stats.is_rx_bytes;
2766 2765 break;
2767 2766 case MAC_STAT_IPACKETS:
2768 2767 *val = ic->ic_stats.is_rx_frags;
2769 2768 break;
2770 2769 case MAC_STAT_OBYTES:
2771 2770 *val = ic->ic_stats.is_tx_bytes;
2772 2771 break;
2773 2772 case MAC_STAT_OPACKETS:
2774 2773 *val = ic->ic_stats.is_tx_frags;
2775 2774 break;
2776 2775 case MAC_STAT_OERRORS:
2777 2776 case WIFI_STAT_TX_FAILED:
2778 2777 *val = sc->sc_tx_err;
2779 2778 break;
2780 2779 case WIFI_STAT_TX_RETRANS:
2781 2780 *val = sc->sc_tx_retries;
2782 2781 break;
2783 2782 case WIFI_STAT_FCS_ERRORS:
2784 2783 case WIFI_STAT_WEP_ERRORS:
2785 2784 case WIFI_STAT_TX_FRAGS:
2786 2785 case WIFI_STAT_MCAST_TX:
2787 2786 case WIFI_STAT_RTS_SUCCESS:
2788 2787 case WIFI_STAT_RTS_FAILURE:
2789 2788 case WIFI_STAT_ACK_FAILURE:
2790 2789 case WIFI_STAT_RX_FRAGS:
2791 2790 case WIFI_STAT_MCAST_RX:
2792 2791 case WIFI_STAT_RX_DUPS:
2793 2792 RT2661_GUNLOCK(sc);
2794 2793 return (ieee80211_stat(ic, stat, val));
2795 2794 default:
2796 2795 RT2661_GUNLOCK(sc);
2797 2796 return (ENOTSUP);
2798 2797 }
2799 2798 RT2661_GUNLOCK(sc);
2800 2799
2801 2800 return (0);
2802 2801 }
2803 2802
2804 2803 static int
2805 2804 rt2661_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2806 2805 {
2807 2806 struct rt2661_softc *sc;
2808 2807 struct ieee80211com *ic;
2809 2808
2810 2809 int i, ac, err, ntries, instance;
2811 2810 int intr_type, intr_count, intr_actual;
2812 2811 char strbuf[32];
2813 2812 uint8_t cachelsz;
2814 2813 uint16_t command, vendor_id, device_id;
2815 2814 uint32_t val;
2816 2815
2817 2816 wifi_data_t wd = { 0 };
2818 2817 mac_register_t *macp;
2819 2818
2820 2819 switch (cmd) {
2821 2820 case DDI_ATTACH:
2822 2821 break;
2823 2822 case DDI_RESUME:
2824 2823 sc = ddi_get_soft_state(rt2661_soft_state_p,
2825 2824 ddi_get_instance(devinfo));
2826 2825 ASSERT(sc != NULL);
2827 2826 RT2661_GLOCK(sc);
2828 2827 sc->sc_flags &= ~RT2661_F_SUSPEND;
2829 2828 RT2661_GUNLOCK(sc);
2830 2829 if (RT2661_IS_RUNNING(sc))
2831 2830 (void) rt2661_init(sc);
2832 2831 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2833 2832 "resume now\n");
2834 2833 return (DDI_SUCCESS);
2835 2834 default:
2836 2835 return (DDI_FAILURE);
2837 2836 }
2838 2837
2839 2838 instance = ddi_get_instance(devinfo);
2840 2839
2841 2840 err = ddi_soft_state_zalloc(rt2661_soft_state_p, instance);
2842 2841 if (err != DDI_SUCCESS) {
2843 2842 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2844 2843 "unable to alloc soft_state_p\n");
2845 2844 return (err);
2846 2845 }
2847 2846
2848 2847 sc = ddi_get_soft_state(rt2661_soft_state_p, instance);
2849 2848 ic = (struct ieee80211com *)&sc->sc_ic;
2850 2849 sc->sc_dev = devinfo;
2851 2850
2852 2851 /* PCI configuration */
2853 2852 err = ddi_regs_map_setup(devinfo, 0, &sc->sc_cfg_base, 0, 0,
2854 2853 &rt2661_csr_accattr, &sc->sc_cfg_handle);
2855 2854 if (err != DDI_SUCCESS) {
2856 2855 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2857 2856 "ddi_regs_map_setup() failed");
2858 2857 goto fail1;
2859 2858 }
2860 2859
2861 2860 cachelsz = ddi_get8(sc->sc_cfg_handle,
2862 2861 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
2863 2862 if (cachelsz == 0)
2864 2863 cachelsz = 0x10;
2865 2864 sc->sc_cachelsz = cachelsz << 2;
2866 2865 sc->sc_dmabuf_size = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
2867 2866
2868 2867 vendor_id = ddi_get16(sc->sc_cfg_handle,
2869 2868 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_VENID));
2870 2869 device_id = ddi_get16(sc->sc_cfg_handle,
2871 2870 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_DEVID));
2872 2871 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2873 2872 "vendor 0x%x, device id 0x%x, cache size %d\n",
2874 2873 vendor_id, device_id, cachelsz);
2875 2874
2876 2875 /*
2877 2876 * Enable response to memory space accesses,
2878 2877 * and enabe bus master.
2879 2878 */
2880 2879 command = PCI_COMM_MAE | PCI_COMM_ME;
2881 2880 ddi_put16(sc->sc_cfg_handle,
2882 2881 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM),
2883 2882 command);
2884 2883 ddi_put8(sc->sc_cfg_handle,
2885 2884 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8);
2886 2885 ddi_put8(sc->sc_cfg_handle,
2887 2886 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10);
2888 2887
2889 2888 /* pci i/o space */
2890 2889 err = ddi_regs_map_setup(devinfo, 1,
2891 2890 &sc->sc_io_base, 0, 0, &rt2661_csr_accattr, &sc->sc_io_handle);
2892 2891 if (err != DDI_SUCCESS) {
2893 2892 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2894 2893 "ddi_regs_map_setup() failed");
2895 2894 goto fail2;
2896 2895 }
2897 2896 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2898 2897 "PCI configuration is done successfully\n");
2899 2898
2900 2899 err = ddi_intr_get_supported_types(devinfo, &intr_type);
2901 2900 if ((err != DDI_SUCCESS) || (!(intr_type & DDI_INTR_TYPE_FIXED))) {
2902 2901 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2903 2902 "fixed type interrupt is not supported\n");
2904 2903 goto fail3;
2905 2904 }
2906 2905
2907 2906 err = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &intr_count);
2908 2907 if ((err != DDI_SUCCESS) || (intr_count != 1)) {
2909 2908 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2910 2909 "no fixed interrupts\n");
2911 2910 goto fail3;
2912 2911 }
2913 2912
2914 2913 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
2915 2914
2916 2915 err = ddi_intr_alloc(devinfo, sc->sc_intr_htable,
2917 2916 DDI_INTR_TYPE_FIXED, 0, intr_count, &intr_actual, 0);
2918 2917 if ((err != DDI_SUCCESS) || (intr_actual != 1)) {
2919 2918 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2920 2919 "ddi_intr_alloc() failed 0x%x\n", err);
2921 2920 goto faili4;
2922 2921 }
2923 2922
2924 2923 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
2925 2924 if (err != DDI_SUCCESS) {
2926 2925 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2927 2926 "ddi_intr_get_pri() failed 0x%x\n", err);
2928 2927 goto faili5;
2929 2928 }
2930 2929
2931 2930 sc->amrr.amrr_min_success_threshold = 1;
2932 2931 sc->amrr.amrr_max_success_threshold = 15;
2933 2932
2934 2933 /* wait for NIC to initialize */
2935 2934 for (ntries = 0; ntries < 1000; ntries++) {
2936 2935 if ((val = RT2661_READ(sc, RT2661_MAC_CSR0)) != 0)
2937 2936 break;
2938 2937 DELAY(1000);
2939 2938 }
2940 2939 if (ntries == 1000) {
2941 2940 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2942 2941 "timeout waiting for NIC to initialize\n");
2943 2942 goto faili5;
2944 2943 }
2945 2944
2946 2945 /* retrieve RF rev. no and various other things from EEPROM */
2947 2946 rt2661_read_eeprom(sc);
2948 2947
2949 2948 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2950 2949 "MAC/BBP RT%X, RF %s\n"
2951 2950 "MAC address is: %x:%x:%x:%x:%x:%x\n", val,
2952 2951 rt2661_get_rf(sc->rf_rev),
2953 2952 ic->ic_macaddr[0], ic->ic_macaddr[1], ic->ic_macaddr[2],
2954 2953 ic->ic_macaddr[3], ic->ic_macaddr[4], ic->ic_macaddr[5]);
2955 2954
2956 2955 /*
2957 2956 * Load 8051 microcode into NIC.
2958 2957 */
2959 2958 switch (device_id) {
2960 2959 case 0x0301:
2961 2960 ucode = rt2561s_ucode;
2962 2961 usize = sizeof (rt2561s_ucode);
2963 2962 break;
2964 2963 case 0x0302:
2965 2964 ucode = rt2561_ucode;
2966 2965 usize = sizeof (rt2561_ucode);
2967 2966 break;
2968 2967 case 0x0401:
2969 2968 ucode = rt2661_ucode;
2970 2969 usize = sizeof (rt2661_ucode);
2971 2970 break;
2972 2971 }
2973 2972
2974 2973 err = rt2661_load_microcode(sc, ucode, usize);
2975 2974 if (err != RT2661_SUCCESS) {
2976 2975 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
2977 2976 "could not load 8051 microcode\n");
2978 2977 goto faili5;
2979 2978 }
2980 2979
2981 2980 sc->sc_flags = 0;
2982 2981 sc->sc_flags |= RT2661_F_FWLOADED;
2983 2982
2984 2983 /*
2985 2984 * Allocate Tx and Rx rings.
2986 2985 */
2987 2986 for (ac = 0; ac < 4; ac++) {
2988 2987 err = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
2989 2988 RT2661_TX_RING_COUNT);
2990 2989 if (err != RT2661_SUCCESS) {
2991 2990 RWD_DEBUG(RT2661_DBG_DMA, "rwd: rt2661_attach(): "
2992 2991 "could not allocate Tx ring %d\n", ac);
2993 2992 goto fail4;
2994 2993 }
2995 2994 }
2996 2995
2997 2996 err = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
2998 2997 if (err != RT2661_SUCCESS) {
2999 2998 RWD_DEBUG(RT2661_DBG_DMA, "rwd: rt2661_attach(): "
3000 2999 "could not allocate Mgt ring\n");
3001 3000 goto fail5;
3002 3001 }
3003 3002
3004 3003 err = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
3005 3004 if (err != RT2661_SUCCESS) {
3006 3005 RWD_DEBUG(RT2661_DBG_DMA, "rwd: rt2661_attach(): "
3007 3006 "could not allocate Rx ring\n");
3008 3007 goto fail6;
3009 3008 }
3010 3009
3011 3010 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
3012 3011 mutex_init(&sc->sc_txlock, NULL, MUTEX_DRIVER, NULL);
3013 3012 mutex_init(&sc->sc_rxlock, NULL, MUTEX_DRIVER, NULL);
3014 3013
3015 3014 ic->ic_phytype = IEEE80211_T_OFDM;
3016 3015 ic->ic_opmode = IEEE80211_M_STA;
3017 3016 ic->ic_state = IEEE80211_S_INIT;
3018 3017
3019 3018 /* set device capabilities */
3020 3019 ic->ic_caps =
3021 3020 IEEE80211_C_TXPMGT |
3022 3021 IEEE80211_C_SHPREAMBLE |
3023 3022 IEEE80211_C_SHSLOT;
3024 3023
3025 3024 /* WPA/WPA2 support */
3026 3025 ic->ic_caps |= IEEE80211_C_WPA;
3027 3026
3028 3027 /* set supported .11b and .11g rates */
3029 3028 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b;
3030 3029 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g;
3031 3030
3032 3031 /* set supported .11b and .11g channels (1 through 14) */
3033 3032 for (i = 1; i <= 14; i++) {
3034 3033 ic->ic_sup_channels[i].ich_freq =
3035 3034 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
3036 3035 ic->ic_sup_channels[i].ich_flags =
3037 3036 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
3038 3037 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
3039 3038 }
3040 3039
3041 3040 ic->ic_maxrssi = 63;
3042 3041 ic->ic_xmit = rt2661_mgmt_send;
3043 3042
3044 3043 ieee80211_attach(ic);
3045 3044
3046 3045 /* register WPA door */
3047 3046 ieee80211_register_door(ic, ddi_driver_name(devinfo),
3048 3047 ddi_get_instance(devinfo));
3049 3048
3050 3049 ic->ic_node_alloc = rt2661_node_alloc;
3051 3050 ic->ic_node_free = rt2661_node_free;
3052 3051 ic->ic_set_shortslot = rt2661_updateslot;
3053 3052
3054 3053 /* override state transition machine */
3055 3054 sc->sc_newstate = ic->ic_newstate;
3056 3055 ic->ic_newstate = rt2661_newstate;
3057 3056 ieee80211_media_init(ic);
3058 3057 ic->ic_def_txkey = 0;
3059 3058
3060 3059 err = ddi_intr_add_softint(devinfo, &sc->sc_softintr_hdl,
3061 3060 DDI_INTR_SOFTPRI_MAX, rt2661_softintr, (caddr_t)sc);
3062 3061 if (err != DDI_SUCCESS) {
3063 3062 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
3064 3063 "ddi_add_softintr() failed");
3065 3064 goto fail7;
3066 3065 }
3067 3066
3068 3067 err = ddi_intr_add_handler(sc->sc_intr_htable[0], rt2661_intr,
3069 3068 (caddr_t)sc, NULL);
3070 3069 if (err != DDI_SUCCESS) {
3071 3070 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
3072 3071 "ddi_intr_addr_handle() failed\n");
3073 3072 goto fail8;
3074 3073 }
3075 3074
3076 3075 err = ddi_intr_enable(sc->sc_intr_htable[0]);
3077 3076 if (err != DDI_SUCCESS) {
3078 3077 RWD_DEBUG(RT2661_DBG_MSG, "rwd; rt2661_attach(): "
3079 3078 "ddi_intr_enable() failed\n");
3080 3079 goto fail9;
3081 3080 }
3082 3081
3083 3082 /*
3084 3083 * Provide initial settings for the WiFi plugin; whenever this
3085 3084 * information changes, we need to call mac_plugindata_update()
3086 3085 */
3087 3086 wd.wd_opmode = ic->ic_opmode;
3088 3087 wd.wd_secalloc = WIFI_SEC_NONE;
3089 3088 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
3090 3089
3091 3090 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
3092 3091 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
3093 3092 "MAC version mismatch\n");
3094 3093 goto fail10;
3095 3094 }
3096 3095
3097 3096 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
3098 3097 macp->m_driver = sc;
3099 3098 macp->m_dip = devinfo;
3100 3099 macp->m_src_addr = ic->ic_macaddr;
3101 3100 macp->m_callbacks = &rt2661_m_callbacks;
3102 3101 macp->m_min_sdu = 0;
3103 3102 macp->m_max_sdu = IEEE80211_MTU;
3104 3103 macp->m_pdata = &wd;
3105 3104 macp->m_pdata_size = sizeof (wd);
3106 3105
3107 3106 err = mac_register(macp, &ic->ic_mach);
3108 3107 mac_free(macp);
3109 3108 if (err != 0) {
3110 3109 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
3111 3110 "mac_register err %x\n", err);
3112 3111 goto fail10;
3113 3112 }
3114 3113
3115 3114 /*
3116 3115 * Create minor node of type DDI_NT_NET_WIFI
3117 3116 */
3118 3117 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
3119 3118 "rwd", instance);
3120 3119 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
3121 3120 instance + 1, DDI_NT_NET_WIFI, 0);
3122 3121
3123 3122 /*
3124 3123 * Notify link is down now
3125 3124 */
3126 3125 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
3127 3126
3128 3127 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_attach(): "
3129 3128 "attach successfully\n");
3130 3129 return (DDI_SUCCESS);
3131 3130
3132 3131 fail10:
3133 3132 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
3134 3133 fail9:
3135 3134 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
3136 3135 fail8:
3137 3136 (void) ddi_intr_remove_softint(sc->sc_softintr_hdl);
3138 3137 sc->sc_softintr_hdl = NULL;
3139 3138 fail7:
3140 3139 mutex_destroy(&sc->sc_genlock);
3141 3140 mutex_destroy(&sc->sc_txlock);
3142 3141 mutex_destroy(&sc->sc_rxlock);
3143 3142 fail6:
3144 3143 rt2661_free_rx_ring(sc, &sc->rxq);
3145 3144 fail5:
3146 3145 rt2661_free_tx_ring(sc, &sc->mgtq);
3147 3146 fail4:
3148 3147 while (--ac >= 0)
3149 3148 rt2661_free_tx_ring(sc, &sc->txq[ac]);
3150 3149 faili5:
3151 3150 (void) ddi_intr_free(sc->sc_intr_htable[0]);
3152 3151 faili4:
3153 3152 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
3154 3153 fail3:
3155 3154 ddi_regs_map_free(&sc->sc_io_handle);
3156 3155 fail2:
3157 3156 ddi_regs_map_free(&sc->sc_cfg_handle);
3158 3157 fail1:
3159 3158 return (DDI_FAILURE);
3160 3159 }
3161 3160
3162 3161 static int
3163 3162 rt2661_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
3164 3163 {
3165 3164
3166 3165 struct rt2661_softc *sc;
3167 3166
3168 3167 sc = ddi_get_soft_state(rt2661_soft_state_p, ddi_get_instance(devinfo));
3169 3168
3170 3169 switch (cmd) {
3171 3170 case DDI_DETACH:
3172 3171 break;
3173 3172 case DDI_SUSPEND:
3174 3173 if (RT2661_IS_RUNNING(sc))
3175 3174 rt2661_stop(sc);
3176 3175 RT2661_GLOCK(sc);
3177 3176 sc->sc_flags |= RT2661_F_SUSPEND;
3178 3177 sc->sc_flags &= ~RT2661_F_FWLOADED;
3179 3178 RT2661_GUNLOCK(sc);
3180 3179 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_detach(): "
3181 3180 "suspend now\n");
3182 3181 return (DDI_SUCCESS);
3183 3182 default:
3184 3183 return (DDI_FAILURE);
3185 3184 }
3186 3185
3187 3186 if (mac_disable(sc->sc_ic.ic_mach) != 0)
3188 3187 return (DDI_FAILURE);
3189 3188
3190 3189 /*
3191 3190 * Unregister from the MAC layer subsystem
3192 3191 */
3193 3192 (void) mac_unregister(sc->sc_ic.ic_mach);
3194 3193
3195 3194 (void) ddi_intr_remove_softint(sc->sc_softintr_hdl);
3196 3195 sc->sc_softintr_hdl = NULL;
3197 3196 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
3198 3197 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
3199 3198 (void) ddi_intr_free(sc->sc_intr_htable[0]);
3200 3199 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
3201 3200
3202 3201 /*
3203 3202 * detach ieee80211 layer
3204 3203 */
3205 3204 ieee80211_detach(&sc->sc_ic);
3206 3205
3207 3206 mutex_destroy(&sc->sc_genlock);
3208 3207 mutex_destroy(&sc->sc_txlock);
3209 3208 mutex_destroy(&sc->sc_rxlock);
3210 3209
3211 3210 rt2661_free_tx_ring(sc, &sc->txq[0]);
3212 3211 rt2661_free_tx_ring(sc, &sc->txq[1]);
3213 3212 rt2661_free_tx_ring(sc, &sc->txq[2]);
3214 3213 rt2661_free_tx_ring(sc, &sc->txq[3]);
3215 3214 rt2661_free_tx_ring(sc, &sc->mgtq);
3216 3215 rt2661_free_rx_ring(sc, &sc->rxq);
3217 3216
3218 3217 ddi_regs_map_free(&sc->sc_io_handle);
3219 3218 ddi_regs_map_free(&sc->sc_cfg_handle);
3220 3219
3221 3220 ddi_remove_minor_node(devinfo, NULL);
3222 3221 ddi_soft_state_free(rt2661_soft_state_p, ddi_get_instance(devinfo));
3223 3222
3224 3223 RWD_DEBUG(RT2661_DBG_MSG, "rwd: rt2661_detach(): "
3225 3224 "detach successfully\n");
3226 3225 return (DDI_SUCCESS);
3227 3226 }
3228 3227
3229 3228 static int
3230 3229 rt2661_quiesce(dev_info_t *dip)
3231 3230 {
3232 3231 struct rt2661_softc *sc;
3233 3232
3234 3233 sc = ddi_get_soft_state(rt2661_soft_state_p, ddi_get_instance(dip));
3235 3234 if (sc == NULL)
3236 3235 return (DDI_FAILURE);
3237 3236
3238 3237 #ifdef DEBUG
3239 3238 rt2661_dbg_flags = 0;
3240 3239 #endif
3241 3240
3242 3241 /*
3243 3242 * No more blocking is allowed while we are in quiesce(9E) entry point
3244 3243 */
3245 3244 sc->sc_flags |= RT2661_F_QUIESCE;
3246 3245
3247 3246 /*
3248 3247 * Disable all interrupts
3249 3248 */
3250 3249 rt2661_stop(sc);
3251 3250 return (DDI_SUCCESS);
3252 3251 }
3253 3252
3254 3253 int
3255 3254 _info(struct modinfo *modinfop)
3256 3255 {
3257 3256 return (mod_info(&modlinkage, modinfop));
3258 3257 }
3259 3258
3260 3259 int
3261 3260 _init(void)
3262 3261 {
3263 3262 int status;
3264 3263
3265 3264 status = ddi_soft_state_init(&rt2661_soft_state_p,
3266 3265 sizeof (struct rt2661_softc), 1);
3267 3266 if (status != 0)
3268 3267 return (status);
3269 3268
3270 3269 mac_init_ops(&rwd_dev_ops, "rwd");
3271 3270 status = mod_install(&modlinkage);
3272 3271 if (status != 0) {
3273 3272 mac_fini_ops(&rwd_dev_ops);
3274 3273 ddi_soft_state_fini(&rt2661_soft_state_p);
3275 3274 }
3276 3275 return (status);
3277 3276 }
3278 3277
3279 3278 int
3280 3279 _fini(void)
3281 3280 {
3282 3281 int status;
3283 3282
3284 3283 status = mod_remove(&modlinkage);
3285 3284 if (status == 0) {
3286 3285 mac_fini_ops(&rwd_dev_ops);
3287 3286 ddi_soft_state_fini(&rt2661_soft_state_p);
3288 3287 }
3289 3288 return (status);
3290 3289 }
|
↓ open down ↓ |
3021 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX