1 /*
2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 * Use is subject to license terms.
4 */
5
6 /*
7 * Copyright (c) 2005-2007 Damien Bergamini <damien.bergamini@free.fr>
8 * Copyright (c) 2006 Niall O'Higgins <niallo@openbsd.org>
9 *
10 * Permission to use, copy, modify, and distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
12 * copyright notice and this permission notice appear in all copies.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 */
22
23 /*
24 * Ralink Technology RT2501USB/RT2601USB chipset driver
25 * http://www.ralinktech.com.tw/
26 */
27 #include <sys/types.h>
28 #include <sys/cmn_err.h>
29 #include <sys/strsubr.h>
30 #include <sys/modctl.h>
31 #include <sys/devops.h>
32 #include <sys/mac_provider.h>
33 #include <sys/mac_wifi.h>
34 #include <sys/net80211.h>
35 #include <sys/byteorder.h>
36
37 #define USBDRV_MAJOR_VER 2
38 #define USBDRV_MINOR_VER 0
39 #include <sys/usb/usba.h>
40 #include <sys/usb/usba/usba_types.h>
41
42 #include "rum_reg.h"
43 #include "rum_var.h"
44 #include "rt2573_ucode.h"
45
46 static void *rum_soft_state_p = NULL;
47
48 #define RAL_TXBUF_SIZE (IEEE80211_MAX_LEN)
49 #define RAL_RXBUF_SIZE (IEEE80211_MAX_LEN)
50
51 /* quickly determine if a given rate is CCK or OFDM */
52 #define RUM_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
53 #define RUM_ACK_SIZE 14 /* 10 + 4(FCS) */
54 #define RUM_CTS_SIZE 14 /* 10 + 4(FCS) */
55
56 #define RUM_N(a) (sizeof (a) / sizeof ((a)[0]))
57
58 /*
59 * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
60 */
61 static const struct ieee80211_rateset rum_rateset_11a =
62 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } };
63
64 static const struct ieee80211_rateset rum_rateset_11b =
65 { 4, { 2, 4, 11, 22 } };
66
67 static const struct ieee80211_rateset rum_rateset_11g =
68 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
69
70 static const struct {
71 uint32_t reg;
72 uint32_t val;
73 } rum_def_mac[] = {
74 { RT2573_TXRX_CSR0, 0x025fb032 },
75 { RT2573_TXRX_CSR1, 0x9eaa9eaf },
76 { RT2573_TXRX_CSR2, 0x8a8b8c8d },
77 { RT2573_TXRX_CSR3, 0x00858687 },
78 { RT2573_TXRX_CSR7, 0x2e31353b },
79 { RT2573_TXRX_CSR8, 0x2a2a2a2c },
80 { RT2573_TXRX_CSR15, 0x0000000f },
81 { RT2573_MAC_CSR6, 0x00000fff },
82 { RT2573_MAC_CSR8, 0x016c030a },
83 { RT2573_MAC_CSR10, 0x00000718 },
84 { RT2573_MAC_CSR12, 0x00000004 },
85 { RT2573_MAC_CSR13, 0x00007f00 },
86 { RT2573_SEC_CSR0, 0x00000000 },
87 { RT2573_SEC_CSR1, 0x00000000 },
88 { RT2573_SEC_CSR5, 0x00000000 },
89 { RT2573_PHY_CSR1, 0x000023b0 },
90 { RT2573_PHY_CSR5, 0x00040a06 },
91 { RT2573_PHY_CSR6, 0x00080606 },
92 { RT2573_PHY_CSR7, 0x00000408 },
93 { RT2573_AIFSN_CSR, 0x00002273 },
94 { RT2573_CWMIN_CSR, 0x00002344 },
95 { RT2573_CWMAX_CSR, 0x000034aa }
96 };
97
98 static const struct {
99 uint8_t reg;
100 uint8_t val;
101 } rum_def_bbp[] = {
102 { 3, 0x80 },
103 { 15, 0x30 },
104 { 17, 0x20 },
105 { 21, 0xc8 },
106 { 22, 0x38 },
107 { 23, 0x06 },
108 { 24, 0xfe },
109 { 25, 0x0a },
110 { 26, 0x0d },
111 { 32, 0x0b },
112 { 34, 0x12 },
113 { 37, 0x07 },
114 { 39, 0xf8 },
115 { 41, 0x60 },
116 { 53, 0x10 },
117 { 54, 0x18 },
118 { 60, 0x10 },
119 { 61, 0x04 },
120 { 62, 0x04 },
121 { 75, 0xfe },
122 { 86, 0xfe },
123 { 88, 0xfe },
124 { 90, 0x0f },
125 { 99, 0x00 },
126 { 102, 0x16 },
127 { 107, 0x04 }
128 };
129
130 static const struct rfprog {
131 uint8_t chan;
132 uint32_t r1, r2, r3, r4;
133 } rum_rf5226[] = {
134 { 1, 0x00b03, 0x001e1, 0x1a014, 0x30282 },
135 { 2, 0x00b03, 0x001e1, 0x1a014, 0x30287 },
136 { 3, 0x00b03, 0x001e2, 0x1a014, 0x30282 },
137 { 4, 0x00b03, 0x001e2, 0x1a014, 0x30287 },
138 { 5, 0x00b03, 0x001e3, 0x1a014, 0x30282 },
139 { 6, 0x00b03, 0x001e3, 0x1a014, 0x30287 },
140 { 7, 0x00b03, 0x001e4, 0x1a014, 0x30282 },
141 { 8, 0x00b03, 0x001e4, 0x1a014, 0x30287 },
142 { 9, 0x00b03, 0x001e5, 0x1a014, 0x30282 },
143 { 10, 0x00b03, 0x001e5, 0x1a014, 0x30287 },
144 { 11, 0x00b03, 0x001e6, 0x1a014, 0x30282 },
145 { 12, 0x00b03, 0x001e6, 0x1a014, 0x30287 },
146 { 13, 0x00b03, 0x001e7, 0x1a014, 0x30282 },
147 { 14, 0x00b03, 0x001e8, 0x1a014, 0x30284 },
148
149 { 34, 0x00b03, 0x20266, 0x36014, 0x30282 },
150 { 38, 0x00b03, 0x20267, 0x36014, 0x30284 },
151 { 42, 0x00b03, 0x20268, 0x36014, 0x30286 },
152 { 46, 0x00b03, 0x20269, 0x36014, 0x30288 },
153
154 { 36, 0x00b03, 0x00266, 0x26014, 0x30288 },
155 { 40, 0x00b03, 0x00268, 0x26014, 0x30280 },
156 { 44, 0x00b03, 0x00269, 0x26014, 0x30282 },
157 { 48, 0x00b03, 0x0026a, 0x26014, 0x30284 },
158 { 52, 0x00b03, 0x0026b, 0x26014, 0x30286 },
159 { 56, 0x00b03, 0x0026c, 0x26014, 0x30288 },
160 { 60, 0x00b03, 0x0026e, 0x26014, 0x30280 },
161 { 64, 0x00b03, 0x0026f, 0x26014, 0x30282 },
162
163 { 100, 0x00b03, 0x0028a, 0x2e014, 0x30280 },
164 { 104, 0x00b03, 0x0028b, 0x2e014, 0x30282 },
165 { 108, 0x00b03, 0x0028c, 0x2e014, 0x30284 },
166 { 112, 0x00b03, 0x0028d, 0x2e014, 0x30286 },
167 { 116, 0x00b03, 0x0028e, 0x2e014, 0x30288 },
168 { 120, 0x00b03, 0x002a0, 0x2e014, 0x30280 },
169 { 124, 0x00b03, 0x002a1, 0x2e014, 0x30282 },
170 { 128, 0x00b03, 0x002a2, 0x2e014, 0x30284 },
171 { 132, 0x00b03, 0x002a3, 0x2e014, 0x30286 },
172 { 136, 0x00b03, 0x002a4, 0x2e014, 0x30288 },
173 { 140, 0x00b03, 0x002a6, 0x2e014, 0x30280 },
174
175 { 149, 0x00b03, 0x002a8, 0x2e014, 0x30287 },
176 { 153, 0x00b03, 0x002a9, 0x2e014, 0x30289 },
177 { 157, 0x00b03, 0x002ab, 0x2e014, 0x30281 },
178 { 161, 0x00b03, 0x002ac, 0x2e014, 0x30283 },
179 { 165, 0x00b03, 0x002ad, 0x2e014, 0x30285 }
180 }, rum_rf5225[] = {
181 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 },
182 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 },
183 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 },
184 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 },
185 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 },
186 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 },
187 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 },
188 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 },
189 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 },
190 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 },
191 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 },
192 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 },
193 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 },
194 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 },
195
196 { 34, 0x00b33, 0x01266, 0x26014, 0x30282 },
197 { 38, 0x00b33, 0x01267, 0x26014, 0x30284 },
198 { 42, 0x00b33, 0x01268, 0x26014, 0x30286 },
199 { 46, 0x00b33, 0x01269, 0x26014, 0x30288 },
200
201 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 },
202 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 },
203 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 },
204 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 },
205 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 },
206 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 },
207 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 },
208 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 },
209
210 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 },
211 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 },
212 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 },
213 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 },
214 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 },
215 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 },
216 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 },
217 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 },
218 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 },
219 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 },
220 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 },
221
222 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 },
223 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 },
224 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 },
225 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 },
226 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
227 };
228
229 /*
230 * device operations
231 */
232 static int rum_attach(dev_info_t *, ddi_attach_cmd_t);
233 static int rum_detach(dev_info_t *, ddi_detach_cmd_t);
234
235 /*
236 * Module Loading Data & Entry Points
237 */
238 DDI_DEFINE_STREAM_OPS(rum_dev_ops, nulldev, nulldev, rum_attach,
239 rum_detach, nodev, NULL, D_MP, NULL, ddi_quiesce_not_needed);
240
241 static struct modldrv rum_modldrv = {
242 &mod_driverops, /* Type of module. This one is a driver */
243 "rum driver v1.2", /* short description */
244 &rum_dev_ops /* driver specific ops */
245 };
246
247 static struct modlinkage modlinkage = {
248 MODREV_1,
249 { (void *)&rum_modldrv, NULL }
250 };
251
252 static int rum_m_stat(void *, uint_t, uint64_t *);
253 static int rum_m_start(void *);
254 static void rum_m_stop(void *);
255 static int rum_m_promisc(void *, boolean_t);
256 static int rum_m_multicst(void *, boolean_t, const uint8_t *);
257 static int rum_m_unicst(void *, const uint8_t *);
258 static mblk_t *rum_m_tx(void *, mblk_t *);
259 static void rum_m_ioctl(void *, queue_t *, mblk_t *);
260 static int rum_m_setprop(void *, const char *, mac_prop_id_t,
261 uint_t, const void *);
262 static int rum_m_getprop(void *, const char *, mac_prop_id_t,
263 uint_t, void *);
264 static void rum_m_propinfo(void *, const char *, mac_prop_id_t,
265 mac_prop_info_handle_t);
266
267 static mac_callbacks_t rum_m_callbacks = {
268 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
269 rum_m_stat,
270 rum_m_start,
271 rum_m_stop,
272 rum_m_promisc,
273 rum_m_multicst,
274 rum_m_unicst,
275 rum_m_tx,
276 NULL,
277 rum_m_ioctl,
278 NULL, /* mc_getcapab */
279 NULL,
280 NULL,
281 rum_m_setprop,
282 rum_m_getprop,
283 rum_m_propinfo
284 };
285
286 static void rum_amrr_start(struct rum_softc *, struct ieee80211_node *);
287 static int rum_tx_trigger(struct rum_softc *, mblk_t *);
288 static int rum_rx_trigger(struct rum_softc *);
289
290 uint32_t rum_dbg_flags = 0;
291
292 void
293 ral_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
294 {
295 va_list args;
296
297 if (dbg_flags & rum_dbg_flags) {
298 va_start(args, fmt);
299 vcmn_err(CE_CONT, fmt, args);
300 va_end(args);
301 }
302 }
303
304 static void
305 rum_read_multi(struct rum_softc *sc, uint16_t reg, void *buf, int len)
306 {
307 usb_ctrl_setup_t req;
308 usb_cr_t cr;
309 usb_cb_flags_t cf;
310 mblk_t *mp;
311 int err;
312
313 bzero(&req, sizeof (req));
314 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST;
315 req.bRequest = RT2573_READ_MULTI_MAC;
316 req.wValue = 0;
317 req.wIndex = reg;
318 req.wLength = (uint16_t)len;
319 req.attrs = USB_ATTRS_AUTOCLEARING;
320
321 mp = NULL;
322 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
323 &cr, &cf, 0);
324
325 if (err != USB_SUCCESS) {
326 ral_debug(RAL_DBG_ERR,
327 "rum_read_multi(): could not read MAC register:"
328 "cr:%s(%d), cf:(%x)\n",
329 usb_str_cr(cr), cr, cf);
330 return;
331 }
332
333 bcopy(mp->b_rptr, buf, len);
334 freemsg(mp);
335 }
336
337 static uint32_t
338 rum_read(struct rum_softc *sc, uint16_t reg)
339 {
340 uint32_t val;
341
342 rum_read_multi(sc, reg, &val, sizeof (val));
343
344 return (LE_32(val));
345 }
346
347 static void
348 rum_write_multi(struct rum_softc *sc, uint16_t reg, void *buf, size_t len)
349 {
350 usb_ctrl_setup_t req;
351 usb_cr_t cr;
352 usb_cb_flags_t cf;
353 mblk_t *mp;
354 int err;
355
356 bzero(&req, sizeof (req));
357 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_HOST_TO_DEV;
358 req.bRequest = RT2573_WRITE_MULTI_MAC;
359 req.wValue = 0;
360 req.wIndex = reg;
361 req.wLength = (uint16_t)len;
362 req.attrs = USB_ATTRS_NONE;
363
364 if ((mp = allocb(len, BPRI_HI)) == NULL) {
365 ral_debug(RAL_DBG_ERR, "rum_write_multi(): failed alloc mblk.");
366 return;
367 }
368
369 bcopy(buf, mp->b_wptr, len);
370 mp->b_wptr += len;
371
372 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
373 &cr, &cf, 0);
374
375 if (err != USB_SUCCESS) {
376 ral_debug(RAL_DBG_USB,
377 "rum_write_multi(): could not write MAC register:"
378 "cr:%s(%d), cf:(%x)\n",
379 usb_str_cr(cr), cr, cf);
380 }
381
382 freemsg(mp);
383 }
384
385 static void
386 rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)
387 {
388 uint32_t tmp = LE_32(val);
389
390 rum_write_multi(sc, reg, &tmp, sizeof (tmp));
391 }
392
393 #define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
394
395 static int
396 rum_load_microcode(struct rum_softc *sc)
397 {
398 usb_ctrl_setup_t req;
399 usb_cr_t cr;
400 usb_cb_flags_t cf;
401 int err;
402
403 const uint8_t *ucode;
404 int size;
405 uint16_t reg = RT2573_MCU_CODE_BASE;
406
407 ucode = rt2573_ucode;
408 size = sizeof (rt2573_ucode);
409
410 /* copy firmware image into NIC */
411 for (; size >= 4; reg += 4, ucode += 4, size -= 4) {
412 rum_write(sc, reg, UGETDW(ucode));
413 /* rum_write(sc, reg, *(uint32_t *)(ucode)); */
414 }
415
416 bzero(&req, sizeof (req));
417 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_HOST_TO_DEV;
418 req.bRequest = RT2573_MCU_CNTL;
419 req.wValue = RT2573_MCU_RUN;
420 req.wIndex = 0;
421 req.wLength = 0;
422 req.attrs = USB_ATTRS_NONE;
423
424 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL,
425 &cr, &cf, 0);
426
427 if (err != USB_SUCCESS) {
428 ral_debug(RAL_DBG_ERR,
429 "rum_load_microcode(): could not run firmware: "
430 "cr:%s(%d), cf:(%x)\n",
431 usb_str_cr(cr), cr, cf);
432 }
433
434 ral_debug(RAL_DBG_MSG,
435 "rum_load_microcode(%d): done\n", sizeof (rt2573_ucode));
436
437 return (err);
438 }
439
440 static void
441 rum_eeprom_read(struct rum_softc *sc, uint16_t addr, void *buf, int len)
442 {
443 usb_ctrl_setup_t req;
444 usb_cr_t cr;
445 usb_cb_flags_t cf;
446 mblk_t *mp;
447 int err;
448
449 bzero(&req, sizeof (req));
450 req.bmRequestType = USB_DEV_REQ_TYPE_VENDOR | USB_DEV_REQ_DEV_TO_HOST;
451 req.bRequest = RT2573_READ_EEPROM;
452 req.wValue = 0;
453 req.wIndex = addr;
454 req.wLength = (uint16_t)len;
455
456 mp = NULL;
457 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
458 &cr, &cf, 0);
459
460 if (err != USB_SUCCESS) {
461 ral_debug(RAL_DBG_USB,
462 "rum_eeprom_read(): could not read EEPROM:"
463 "cr:%s(%d), cf:(%x)\n",
464 usb_str_cr(cr), cr, cf);
465 return;
466 }
467
468 bcopy(mp->b_rptr, buf, len);
469 freemsg(mp);
470 }
471
472 /* ARGSUSED */
473 static void
474 rum_txeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req)
475 {
476 struct rum_softc *sc = (struct rum_softc *)req->bulk_client_private;
477 struct ieee80211com *ic = &sc->sc_ic;
478
479 ral_debug(RAL_DBG_TX,
480 "rum_txeof(): cr:%s(%d), flags:0x%x, tx_queued:%d",
481 usb_str_cr(req->bulk_completion_reason),
482 req->bulk_completion_reason,
483 req->bulk_cb_flags,
484 sc->tx_queued);
485
486 if (req->bulk_completion_reason != USB_CR_OK)
487 sc->sc_tx_err++;
488
489 mutex_enter(&sc->tx_lock);
490
491 sc->tx_queued--;
492 sc->sc_tx_timer = 0;
493
494 if (sc->sc_need_sched) {
495 sc->sc_need_sched = 0;
496 mac_tx_update(ic->ic_mach);
497 }
498
499 mutex_exit(&sc->tx_lock);
500 usb_free_bulk_req(req);
501 }
502
503 /* ARGSUSED */
504 static void
505 rum_rxeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req)
506 {
507 struct rum_softc *sc = (struct rum_softc *)req->bulk_client_private;
508 struct ieee80211com *ic = &sc->sc_ic;
509
510 struct rum_rx_desc *desc;
511 struct ieee80211_frame *wh;
512 struct ieee80211_node *ni;
513
514 mblk_t *m, *mp;
515 int len, pktlen;
516 char *rxbuf;
517
518 mp = req->bulk_data;
519 req->bulk_data = NULL;
520
521 ral_debug(RAL_DBG_RX,
522 "rum_rxeof(): cr:%s(%d), flags:0x%x, rx_queued:%d",
523 usb_str_cr(req->bulk_completion_reason),
524 req->bulk_completion_reason,
525 req->bulk_cb_flags,
526 sc->rx_queued);
527
528 if (req->bulk_completion_reason != USB_CR_OK) {
529 sc->sc_rx_err++;
530 goto fail;
531 }
532
533 len = msgdsize(mp);
534 rxbuf = (char *)mp->b_rptr;
535
536
537 if (len < RT2573_RX_DESC_SIZE + sizeof (struct ieee80211_frame_min)) {
538 ral_debug(RAL_DBG_ERR,
539 "rum_rxeof(): xfer too short %d\n", len);
540 sc->sc_rx_err++;
541 goto fail;
542 }
543
544 /* rx descriptor is located at the head, different from RT2500USB */
545 desc = (struct rum_rx_desc *)rxbuf;
546
547 if (LE_32(desc->flags) & RT2573_RX_CRC_ERROR) {
548 /*
549 * This should not happen since we did not request to receive
550 * those frames when we filled RT2573_TXRX_CSR0.
551 */
552 ral_debug(RAL_DBG_ERR, "CRC error\n");
553 sc->sc_rx_err++;
554 goto fail;
555 }
556
557 pktlen = (LE_32(desc->flags) >> 16) & 0xfff;
558
559 if (pktlen > (len - RT2573_RX_DESC_SIZE)) {
560 ral_debug(RAL_DBG_ERR,
561 "rum_rxeof(): pktlen mismatch <%d, %d>.\n", pktlen, len);
562 goto fail;
563 }
564
565 if ((m = allocb(pktlen, BPRI_MED)) == NULL) {
566 ral_debug(RAL_DBG_ERR,
567 "rum_rxeof(): allocate mblk failed.\n");
568 sc->sc_rx_nobuf++;
569 goto fail;
570 }
571
572 bcopy(rxbuf + RT2573_RX_DESC_SIZE, m->b_rptr, pktlen);
573 m->b_wptr += pktlen;
574
575 wh = (struct ieee80211_frame *)m->b_rptr;
576 ni = ieee80211_find_rxnode(ic, wh);
577
578 /* send the frame to the 802.11 layer */
579 (void) ieee80211_input(ic, m, ni, desc->rssi, 0);
580
581 /* node is no longer needed */
582 ieee80211_free_node(ni);
583
584 fail:
585 mutex_enter(&sc->rx_lock);
586 sc->rx_queued--;
587 mutex_exit(&sc->rx_lock);
588
589 freemsg(mp);
590 usb_free_bulk_req(req);
591
592 if (RAL_IS_RUNNING(sc))
593 (void) rum_rx_trigger(sc);
594 }
595
596 /*
597 * Return the expected ack rate for a frame transmitted at rate `rate'.
598 */
599 static int
600 rum_ack_rate(struct ieee80211com *ic, int rate)
601 {
602 switch (rate) {
603 /* CCK rates */
604 case 2:
605 return (2);
606 case 4:
607 case 11:
608 case 22:
609 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
610
611 /* OFDM rates */
612 case 12:
613 case 18:
614 return (12);
615 case 24:
616 case 36:
617 return (24);
618 case 48:
619 case 72:
620 case 96:
621 case 108:
622 return (48);
623 }
624
625 /* default to 1Mbps */
626 return (2);
627 }
628
629 /*
630 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
631 * The function automatically determines the operating mode depending on the
632 * given rate. `flags' indicates whether short preamble is in use or not.
633 */
634 static uint16_t
635 rum_txtime(int len, int rate, uint32_t flags)
636 {
637 uint16_t txtime;
638
639 if (RUM_RATE_IS_OFDM(rate)) {
640 /* IEEE Std 802.11a-1999, pp. 37 */
641 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
642 txtime = 16 + 4 + 4 * txtime + 6;
643 } else {
644 /* IEEE Std 802.11b-1999, pp. 28 */
645 txtime = (16 * len + rate - 1) / rate;
646 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
647 txtime += 72 + 24;
648 else
649 txtime += 144 + 48;
650 }
651 return (txtime);
652 }
653
654 static uint8_t
655 rum_plcp_signal(int rate)
656 {
657 switch (rate) {
658 /* CCK rates (returned values are device-dependent) */
659 case 2: return (0x0);
660 case 4: return (0x1);
661 case 11: return (0x2);
662 case 22: return (0x3);
663
664 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
665 case 12: return (0xb);
666 case 18: return (0xf);
667 case 24: return (0xa);
668 case 36: return (0xe);
669 case 48: return (0x9);
670 case 72: return (0xd);
671 case 96: return (0x8);
672 case 108: return (0xc);
673
674 /* unsupported rates (should not get there) */
675 default: return (0xff);
676 }
677 }
678
679 static void
680 rum_setup_tx_desc(struct rum_softc *sc, struct rum_tx_desc *desc,
681 uint32_t flags, uint16_t xflags, int len, int rate)
682 {
683 struct ieee80211com *ic = &sc->sc_ic;
684 uint16_t plcp_length;
685 int remainder;
686
687 desc->flags = LE_32(flags);
688 desc->flags |= LE_32(RT2573_TX_VALID);
689 desc->flags |= LE_32(len << 16);
690
691 desc->xflags = LE_16(xflags);
692
693 desc->wme = LE_16(RT2573_QID(0) | RT2573_AIFSN(2) |
694 RT2573_LOGCWMIN(4) | RT2573_LOGCWMAX(10));
695
696 /* setup PLCP fields */
697 desc->plcp_signal = rum_plcp_signal(rate);
698 desc->plcp_service = 4;
699
700 len += IEEE80211_CRC_LEN;
701 if (RUM_RATE_IS_OFDM(rate)) {
702 desc->flags |= LE_32(RT2573_TX_OFDM);
703
704 plcp_length = len & 0xfff;
705 desc->plcp_length_hi = plcp_length >> 6;
706 desc->plcp_length_lo = plcp_length & 0x3f;
707 } else {
708 plcp_length = (16 * len + rate - 1) / rate;
709 if (rate == 22) {
710 remainder = (16 * len) % 22;
711 if (remainder != 0 && remainder < 7)
712 desc->plcp_service |= RT2573_PLCP_LENGEXT;
713 }
714 desc->plcp_length_hi = plcp_length >> 8;
715 desc->plcp_length_lo = plcp_length & 0xff;
716
717 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
718 desc->plcp_signal |= 0x08;
719 }
720 }
721
722 #define RUM_TX_TIMEOUT 5
723
724 static int
725 rum_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
726 {
727 struct rum_softc *sc = (struct rum_softc *)ic;
728 struct rum_tx_desc *desc;
729
730 struct ieee80211_frame *wh;
731 struct ieee80211_key *k;
732
733 uint16_t dur;
734 uint32_t flags = 0;
735 int rate, err = DDI_SUCCESS, rv;
736
737 struct ieee80211_node *ni = NULL;
738 mblk_t *m, *m0;
739 int off, mblen, pktlen, xferlen;
740
741 /* discard packets while suspending or not inited */
742 if (!RAL_IS_RUNNING(sc)) {
743 freemsg(mp);
744 return (ENXIO);
745 }
746
747 mutex_enter(&sc->tx_lock);
748
749 if (sc->tx_queued > RAL_TX_LIST_COUNT) {
750 ral_debug(RAL_DBG_TX, "rum_send(): "
751 "no TX buffer available!\n");
752 if ((type & IEEE80211_FC0_TYPE_MASK) ==
753 IEEE80211_FC0_TYPE_DATA) {
754 sc->sc_need_sched = 1;
755 }
756 sc->sc_tx_nobuf++;
757 err = ENOMEM;
758 goto fail;
759 }
760
761 m = allocb(RAL_TXBUF_SIZE + RT2573_TX_DESC_SIZE, BPRI_MED);
762 if (m == NULL) {
763 ral_debug(RAL_DBG_ERR, "rum_send(): can't alloc mblk.\n");
764 err = DDI_FAILURE;
765 goto fail;
766 }
767
768 m->b_rptr += RT2573_TX_DESC_SIZE; /* skip TX descriptor */
769 m->b_wptr += RT2573_TX_DESC_SIZE;
770
771 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
772 mblen = (uintptr_t)m0->b_wptr - (uintptr_t)m0->b_rptr;
773 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen);
774 off += mblen;
775 }
776 m->b_wptr += off;
777
778 wh = (struct ieee80211_frame *)m->b_rptr;
779
780 ni = ieee80211_find_txnode(ic, wh->i_addr1);
781 if (ni == NULL) {
782 err = DDI_FAILURE;
783 sc->sc_tx_err++;
784 freemsg(m);
785 goto fail;
786 }
787
788 if ((type & IEEE80211_FC0_TYPE_MASK) ==
789 IEEE80211_FC0_TYPE_DATA) {
790 (void) ieee80211_encap(ic, m, ni);
791 }
792
793 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
794 k = ieee80211_crypto_encap(ic, m);
795 if (k == NULL) {
796 sc->sc_tx_err++;
797 err = DDI_FAILURE;
798 freemsg(m);
799 goto fail;
800 }
801 /* packet header may have moved, reset our local pointer */
802 wh = (struct ieee80211_frame *)m->b_rptr;
803 }
804
805 m->b_rptr -= RT2573_TX_DESC_SIZE; /* restore */
806 desc = (struct rum_tx_desc *)m->b_rptr;
807
808 if ((type & IEEE80211_FC0_TYPE_MASK) ==
809 IEEE80211_FC0_TYPE_DATA) { /* DATA */
810 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE)
811 rate = ic->ic_bss->in_rates.ir_rates[ic->ic_fixed_rate];
812 else
813 rate = ni->in_rates.ir_rates[ni->in_txrate];
814
815 rate &= IEEE80211_RATE_VAL;
816 if (rate <= 0) {
817 rate = 2; /* basic rate */
818 }
819
820
821 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
822 flags |= RT2573_TX_NEED_ACK;
823 flags |= RT2573_TX_MORE_FRAG;
824
825 dur = rum_txtime(RUM_ACK_SIZE, rum_ack_rate(ic, rate),
826 ic->ic_flags) + sc->sifs;
827 *(uint16_t *)(uintptr_t)wh->i_dur = LE_16(dur);
828 }
829 } else { /* MGMT */
830 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
831
832 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
833 flags |= RT2573_TX_NEED_ACK;
834
835 dur = rum_txtime(RUM_ACK_SIZE, rum_ack_rate(ic, rate),
836 ic->ic_flags) + sc->sifs;
837 *(uint16_t *)(uintptr_t)wh->i_dur = LE_16(dur);
838
839 /* tell hardware to add timestamp for probe responses */
840 if ((wh->i_fc[0] &
841 (IEEE80211_FC0_TYPE_MASK |
842 IEEE80211_FC0_SUBTYPE_MASK)) ==
843 (IEEE80211_FC0_TYPE_MGT |
844 IEEE80211_FC0_SUBTYPE_PROBE_RESP))
845 flags |= RT2573_TX_TIMESTAMP;
846 }
847 }
848
849 pktlen = msgdsize(m) - RT2573_TX_DESC_SIZE;
850 rum_setup_tx_desc(sc, desc, flags, 0, pktlen, rate);
851
852 /* align end on a 4-bytes boundary */
853 xferlen = (RT2573_TX_DESC_SIZE + pktlen + 3) & ~3;
854
855 /*
856 * No space left in the last URB to store the extra 4 bytes, force
857 * sending of another URB.
858 */
859 if ((xferlen % 64) == 0)
860 xferlen += 4;
861
862 m->b_wptr = m->b_rptr + xferlen;
863
864 ral_debug(RAL_DBG_TX, "sending data frame len=%u rate=%u xfer len=%u\n",
865 pktlen, rate, xferlen);
866
867 rv = rum_tx_trigger(sc, m);
868
869 if (rv == 0) {
870 ic->ic_stats.is_tx_frags++;
871 ic->ic_stats.is_tx_bytes += pktlen;
872 }
873
874 fail:
875 if (ni != NULL)
876 ieee80211_free_node(ni);
877
878 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA ||
879 err == 0) {
880 freemsg(mp);
881 }
882
883 mutex_exit(&sc->tx_lock);
884
885 return (err);
886 }
887
888 static mblk_t *
889 rum_m_tx(void *arg, mblk_t *mp)
890 {
891 struct rum_softc *sc = (struct rum_softc *)arg;
892 struct ieee80211com *ic = &sc->sc_ic;
893 mblk_t *next;
894
895 /*
896 * No data frames go out unless we're associated; this
897 * should not happen as the 802.11 layer does not enable
898 * the xmit queue until we enter the RUN state.
899 */
900 if (ic->ic_state != IEEE80211_S_RUN) {
901 ral_debug(RAL_DBG_ERR, "rum_m_tx(): "
902 "discard, state %u\n", ic->ic_state);
903 freemsgchain(mp);
904 return (NULL);
905 }
906
907 while (mp != NULL) {
908 next = mp->b_next;
909 mp->b_next = NULL;
910 if (rum_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != DDI_SUCCESS) {
911 mp->b_next = next;
912 freemsgchain(mp);
913 return (NULL);
914 }
915 mp = next;
916 }
917 return (mp);
918 }
919
920 static void
921 rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)
922 {
923 uint32_t tmp;
924 int ntries;
925
926 for (ntries = 0; ntries < 5; ntries++) {
927 if (!(rum_read(sc, RT2573_PHY_CSR3) & RT2573_BBP_BUSY))
928 break;
929 }
930 if (ntries == 5) {
931 ral_debug(RAL_DBG_ERR,
932 "rum_bbp_write(): could not write to BBP\n");
933 return;
934 }
935
936 tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;
937 rum_write(sc, RT2573_PHY_CSR3, tmp);
938 }
939
940 static uint8_t
941 rum_bbp_read(struct rum_softc *sc, uint8_t reg)
942 {
943 uint32_t val;
944 int ntries;
945
946 for (ntries = 0; ntries < 5; ntries++) {
947 if (!(rum_read(sc, RT2573_PHY_CSR3) & RT2573_BBP_BUSY))
948 break;
949 }
950 if (ntries == 5) {
951 ral_debug(RAL_DBG_ERR, "rum_bbp_read(): could not read BBP\n");
952 return (0);
953 }
954
955 val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;
956 rum_write(sc, RT2573_PHY_CSR3, val);
957
958 for (ntries = 0; ntries < 100; ntries++) {
959 val = rum_read(sc, RT2573_PHY_CSR3);
960 if (!(val & RT2573_BBP_BUSY))
961 return (val & 0xff);
962 drv_usecwait(1);
963 }
964
965 ral_debug(RAL_DBG_ERR, "rum_bbp_read(): could not read BBP\n");
966 return (0);
967 }
968
969 static void
970 rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)
971 {
972 uint32_t tmp;
973 int ntries;
974
975 for (ntries = 0; ntries < 5; ntries++) {
976 if (!(rum_read(sc, RT2573_PHY_CSR4) & RT2573_RF_BUSY))
977 break;
978 }
979 if (ntries == 5) {
980 ral_debug(RAL_DBG_ERR,
981 "rum_rf_write(): could not write to RF\n");
982 return;
983 }
984
985 tmp = RT2573_RF_BUSY | RT2573_RF_20BIT | (val & 0xfffff) << 2 |
986 (reg & 3);
987 rum_write(sc, RT2573_PHY_CSR4, tmp);
988
989 /* remember last written value in sc */
990 sc->rf_regs[reg] = val;
991
992 ral_debug(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff);
993 }
994
995 static void
996 rum_select_antenna(struct rum_softc *sc)
997 {
998 uint8_t bbp4, bbp77;
999 uint32_t tmp;
1000
1001 bbp4 = rum_bbp_read(sc, 4);
1002 bbp77 = rum_bbp_read(sc, 77);
1003
1004 /* make sure Rx is disabled before switching antenna */
1005 tmp = rum_read(sc, RT2573_TXRX_CSR0);
1006 rum_write(sc, RT2573_TXRX_CSR0, tmp | RT2573_DISABLE_RX);
1007
1008 rum_bbp_write(sc, 4, bbp4);
1009 rum_bbp_write(sc, 77, bbp77);
1010
1011 rum_write(sc, RT2573_TXRX_CSR0, tmp);
1012 }
1013
1014 /*
1015 * Enable multi-rate retries for frames sent at OFDM rates.
1016 * In 802.11b/g mode, allow fallback to CCK rates.
1017 */
1018 static void
1019 rum_enable_mrr(struct rum_softc *sc)
1020 {
1021 struct ieee80211com *ic = &sc->sc_ic;
1022 uint32_t tmp;
1023
1024 tmp = rum_read(sc, RT2573_TXRX_CSR4);
1025
1026 tmp &= ~RT2573_MRR_CCK_FALLBACK;
1027 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
1028 tmp |= RT2573_MRR_CCK_FALLBACK;
1029 tmp |= RT2573_MRR_ENABLED;
1030
1031 rum_write(sc, RT2573_TXRX_CSR4, tmp);
1032 }
1033
1034 static void
1035 rum_set_txpreamble(struct rum_softc *sc)
1036 {
1037 uint32_t tmp;
1038
1039 tmp = rum_read(sc, RT2573_TXRX_CSR4);
1040
1041 tmp &= ~RT2573_SHORT_PREAMBLE;
1042 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1043 tmp |= RT2573_SHORT_PREAMBLE;
1044
1045 rum_write(sc, RT2573_TXRX_CSR4, tmp);
1046 }
1047
1048 static void
1049 rum_set_basicrates(struct rum_softc *sc)
1050 {
1051 struct ieee80211com *ic = &sc->sc_ic;
1052
1053 /* update basic rate set */
1054 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1055 /* 11b basic rates: 1, 2Mbps */
1056 rum_write(sc, RT2573_TXRX_CSR5, 0x3);
1057 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->in_chan)) {
1058 /* 11a basic rates: 6, 12, 24Mbps */
1059 rum_write(sc, RT2573_TXRX_CSR5, 0x150);
1060 } else {
1061 /* 11b/g basic rates: 1, 2, 5.5, 11Mbps */
1062 rum_write(sc, RT2573_TXRX_CSR5, 0xf);
1063 }
1064 }
1065
1066 /*
1067 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
1068 * driver.
1069 */
1070 static void
1071 rum_select_band(struct rum_softc *sc, struct ieee80211_channel *c)
1072 {
1073 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
1074 uint32_t tmp;
1075
1076 /* update all BBP registers that depend on the band */
1077 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
1078 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
1079 if (IEEE80211_IS_CHAN_5GHZ(c)) {
1080 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
1081 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
1082 }
1083 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1084 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1085 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
1086 }
1087
1088 sc->bbp17 = bbp17;
1089 rum_bbp_write(sc, 17, bbp17);
1090 rum_bbp_write(sc, 96, bbp96);
1091 rum_bbp_write(sc, 104, bbp104);
1092
1093 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1094 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1095 rum_bbp_write(sc, 75, 0x80);
1096 rum_bbp_write(sc, 86, 0x80);
1097 rum_bbp_write(sc, 88, 0x80);
1098 }
1099
1100 rum_bbp_write(sc, 35, bbp35);
1101 rum_bbp_write(sc, 97, bbp97);
1102 rum_bbp_write(sc, 98, bbp98);
1103
1104 tmp = rum_read(sc, RT2573_PHY_CSR0);
1105 tmp &= ~(RT2573_PA_PE_2GHZ | RT2573_PA_PE_5GHZ);
1106 if (IEEE80211_IS_CHAN_2GHZ(c))
1107 tmp |= RT2573_PA_PE_2GHZ;
1108 else
1109 tmp |= RT2573_PA_PE_5GHZ;
1110 rum_write(sc, RT2573_PHY_CSR0, tmp);
1111
1112 /* 802.11a uses a 16 microseconds short interframe space */
1113 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10;
1114 }
1115
1116 static void
1117 rum_set_chan(struct rum_softc *sc, struct ieee80211_channel *c)
1118 {
1119 struct ieee80211com *ic = &sc->sc_ic;
1120 const struct rfprog *rfprog;
1121 uint8_t bbp3, bbp94 = RT2573_BBPR94_DEFAULT;
1122 int8_t power;
1123 uint_t i, chan;
1124
1125 chan = ieee80211_chan2ieee(ic, c);
1126 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
1127 return;
1128
1129 /* select the appropriate RF settings based on what EEPROM says */
1130 rfprog = (sc->rf_rev == RT2573_RF_5225 ||
1131 sc->rf_rev == RT2573_RF_2527) ? rum_rf5225 : rum_rf5226;
1132
1133 /* find the settings for this channel (we know it exists) */
1134 for (i = 0; rfprog[i].chan != chan; i++) {
1135 }
1136
1137 power = sc->txpow[i];
1138 if (power < 0) {
1139 bbp94 += power;
1140 power = 0;
1141 } else if (power > 31) {
1142 bbp94 += power - 31;
1143 power = 31;
1144 }
1145
1146 /*
1147 * If we are switching from the 2GHz band to the 5GHz band or
1148 * vice-versa, BBP registers need to be reprogrammed.
1149 */
1150 if (c->ich_flags != ic->ic_curchan->ich_flags) {
1151 rum_select_band(sc, c);
1152 rum_select_antenna(sc);
1153 }
1154 ic->ic_curchan = c;
1155
1156 rum_rf_write(sc, RT2573_RF1, rfprog[i].r1);
1157 rum_rf_write(sc, RT2573_RF2, rfprog[i].r2);
1158 rum_rf_write(sc, RT2573_RF3, rfprog[i].r3 | power << 7);
1159 rum_rf_write(sc, RT2573_RF4, rfprog[i].r4 | sc->rffreq << 10);
1160
1161 rum_rf_write(sc, RT2573_RF1, rfprog[i].r1);
1162 rum_rf_write(sc, RT2573_RF2, rfprog[i].r2);
1163 rum_rf_write(sc, RT2573_RF3, rfprog[i].r3 | power << 7 | 1);
1164 rum_rf_write(sc, RT2573_RF4, rfprog[i].r4 | sc->rffreq << 10);
1165
1166 rum_rf_write(sc, RT2573_RF1, rfprog[i].r1);
1167 rum_rf_write(sc, RT2573_RF2, rfprog[i].r2);
1168 rum_rf_write(sc, RT2573_RF3, rfprog[i].r3 | power << 7);
1169 rum_rf_write(sc, RT2573_RF4, rfprog[i].r4 | sc->rffreq << 10);
1170
1171 drv_usecwait(10);
1172
1173 /* enable smart mode for MIMO-capable RFs */
1174 bbp3 = rum_bbp_read(sc, 3);
1175
1176 bbp3 &= ~RT2573_SMART_MODE;
1177 if (sc->rf_rev == RT2573_RF_5225 || sc->rf_rev == RT2573_RF_2527)
1178 bbp3 |= RT2573_SMART_MODE;
1179
1180 rum_bbp_write(sc, 3, bbp3);
1181
1182 if (bbp94 != RT2573_BBPR94_DEFAULT)
1183 rum_bbp_write(sc, 94, bbp94);
1184 }
1185
1186 /*
1187 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
1188 * and HostAP operating modes.
1189 */
1190 static void
1191 rum_enable_tsf_sync(struct rum_softc *sc)
1192 {
1193 struct ieee80211com *ic = &sc->sc_ic;
1194 uint32_t tmp;
1195
1196 if (ic->ic_opmode != IEEE80211_M_STA) {
1197 /*
1198 * Change default 16ms TBTT adjustment to 8ms.
1199 * Must be done before enabling beacon generation.
1200 */
1201 rum_write(sc, RT2573_TXRX_CSR10, 1 << 12 | 8);
1202 }
1203
1204 tmp = rum_read(sc, RT2573_TXRX_CSR9) & 0xff000000;
1205
1206 /* set beacon interval (in 1/16ms unit) */
1207 tmp |= ic->ic_bss->in_intval * 16;
1208
1209 tmp |= RT2573_TSF_TICKING | RT2573_ENABLE_TBTT;
1210 if (ic->ic_opmode == IEEE80211_M_STA)
1211 tmp |= RT2573_TSF_MODE(1);
1212 else
1213 tmp |= RT2573_TSF_MODE(2) | RT2573_GENERATE_BEACON;
1214
1215 rum_write(sc, RT2573_TXRX_CSR9, tmp);
1216 }
1217
1218 /* ARGSUSED */
1219 static void
1220 rum_update_slot(struct ieee80211com *ic, int onoff)
1221 {
1222 struct rum_softc *sc = (struct rum_softc *)ic;
1223 uint8_t slottime;
1224 uint32_t tmp;
1225
1226 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1227
1228 tmp = rum_read(sc, RT2573_MAC_CSR9);
1229 tmp = (tmp & ~0xff) | slottime;
1230 rum_write(sc, RT2573_MAC_CSR9, tmp);
1231
1232 ral_debug(RAL_DBG_HW, "setting slot time to %uus\n", slottime);
1233 }
1234
1235 static void
1236 rum_set_bssid(struct rum_softc *sc, const uint8_t *bssid)
1237 {
1238 uint32_t tmp;
1239
1240 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
1241 rum_write(sc, RT2573_MAC_CSR4, tmp);
1242
1243 tmp = bssid[4] | bssid[5] << 8 | RT2573_ONE_BSSID << 16;
1244 rum_write(sc, RT2573_MAC_CSR5, tmp);
1245 }
1246
1247 static void
1248 rum_set_macaddr(struct rum_softc *sc, const uint8_t *addr)
1249 {
1250 uint32_t tmp;
1251
1252 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
1253 rum_write(sc, RT2573_MAC_CSR2, tmp);
1254
1255 tmp = addr[4] | addr[5] << 8 | 0xff << 16;
1256 rum_write(sc, RT2573_MAC_CSR3, tmp);
1257
1258 ral_debug(RAL_DBG_HW,
1259 "setting MAC address to " MACSTR "\n", MAC2STR(addr));
1260 }
1261
1262 static void
1263 rum_update_promisc(struct rum_softc *sc)
1264 {
1265 uint32_t tmp;
1266
1267 tmp = rum_read(sc, RT2573_TXRX_CSR0);
1268
1269 tmp &= ~RT2573_DROP_NOT_TO_ME;
1270 if (!(sc->sc_rcr & RAL_RCR_PROMISC))
1271 tmp |= RT2573_DROP_NOT_TO_ME;
1272
1273 rum_write(sc, RT2573_TXRX_CSR0, tmp);
1274
1275 ral_debug(RAL_DBG_HW, "%s promiscuous mode\n",
1276 (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving");
1277 }
1278
1279 static const char *
1280 rum_get_rf(int rev)
1281 {
1282 switch (rev) {
1283 case RT2573_RF_2527: return ("RT2527 (MIMO XR)");
1284 case RT2573_RF_2528: return ("RT2528");
1285 case RT2573_RF_5225: return ("RT5225 (MIMO XR)");
1286 case RT2573_RF_5226: return ("RT5226");
1287 default: return ("unknown");
1288 }
1289 }
1290
1291 static void
1292 rum_read_eeprom(struct rum_softc *sc)
1293 {
1294 struct ieee80211com *ic = &sc->sc_ic;
1295 uint16_t val;
1296
1297 /* read MAC address */
1298 rum_eeprom_read(sc, RT2573_EEPROM_ADDRESS, ic->ic_macaddr, 6);
1299
1300 rum_eeprom_read(sc, RT2573_EEPROM_ANTENNA, &val, 2);
1301 val = LE_16(val);
1302 sc->rf_rev = (val >> 11) & 0x1f;
1303 sc->hw_radio = (val >> 10) & 0x1;
1304 sc->rx_ant = (val >> 4) & 0x3;
1305 sc->tx_ant = (val >> 2) & 0x3;
1306 sc->nb_ant = val & 0x3;
1307
1308 ral_debug(RAL_DBG_HW, "RF revision=%d\n", sc->rf_rev);
1309
1310 rum_eeprom_read(sc, RT2573_EEPROM_CONFIG2, &val, 2);
1311 val = LE_16(val);
1312 sc->ext_5ghz_lna = (val >> 6) & 0x1;
1313 sc->ext_2ghz_lna = (val >> 4) & 0x1;
1314
1315 ral_debug(RAL_DBG_HW, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
1316 sc->ext_2ghz_lna, sc->ext_5ghz_lna);
1317
1318 rum_eeprom_read(sc, RT2573_EEPROM_RSSI_2GHZ_OFFSET, &val, 2);
1319 val = LE_16(val);
1320 if ((val & 0xff) != 0xff)
1321 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
1322
1323 rum_eeprom_read(sc, RT2573_EEPROM_RSSI_5GHZ_OFFSET, &val, 2);
1324 val = LE_16(val);
1325 if ((val & 0xff) != 0xff)
1326 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
1327
1328 ral_debug(RAL_DBG_HW, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
1329 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr);
1330
1331 rum_eeprom_read(sc, RT2573_EEPROM_FREQ_OFFSET, &val, 2);
1332 val = LE_16(val);
1333 if ((val & 0xff) != 0xff)
1334 sc->rffreq = val & 0xff;
1335
1336 ral_debug(RAL_DBG_HW, "RF freq=%d\n", sc->rffreq);
1337
1338 /* read Tx power for all a/b/g channels */
1339 rum_eeprom_read(sc, RT2573_EEPROM_TXPOWER, sc->txpow, 14);
1340 /* default Tx power for 802.11a channels */
1341 (void) memset(sc->txpow + 14, 24, sizeof (sc->txpow) - 14);
1342
1343 /* read default values for BBP registers */
1344 rum_eeprom_read(sc, RT2573_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16);
1345 }
1346
1347 static int
1348 rum_bbp_init(struct rum_softc *sc)
1349 {
1350 int i, ntries;
1351
1352 /* wait for BBP to be ready */
1353 for (ntries = 0; ntries < 100; ntries++) {
1354 const uint8_t val = rum_bbp_read(sc, 0);
1355 if (val != 0 && val != 0xff)
1356 break;
1357 drv_usecwait(1000);
1358 }
1359 if (ntries == 100) {
1360 ral_debug(RAL_DBG_ERR, "timeout waiting for BBP\n");
1361 return (EIO);
1362 }
1363
1364 /* initialize BBP registers to default values */
1365 for (i = 0; i < RUM_N(rum_def_bbp); i++)
1366 rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);
1367
1368 /* write vendor-specific BBP values (from EEPROM) */
1369 for (i = 0; i < 16; i++) {
1370 if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)
1371 continue;
1372 rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
1373 }
1374
1375 return (0);
1376 }
1377
1378 /*
1379 * This function is called periodically (every 200ms) during scanning to
1380 * switch from one channel to another.
1381 */
1382 static void
1383 rum_next_scan(void *arg)
1384 {
1385 struct rum_softc *sc = arg;
1386 struct ieee80211com *ic = &sc->sc_ic;
1387
1388 if (ic->ic_state == IEEE80211_S_SCAN)
1389 ieee80211_next_scan(ic);
1390 }
1391
1392 static int
1393 rum_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1394 {
1395 struct rum_softc *sc = (struct rum_softc *)ic;
1396 enum ieee80211_state ostate;
1397 struct ieee80211_node *ni;
1398 int err;
1399 uint32_t tmp;
1400
1401 RAL_LOCK(sc);
1402
1403 ostate = ic->ic_state;
1404
1405 if (sc->sc_scan_id != 0) {
1406 (void) untimeout(sc->sc_scan_id);
1407 sc->sc_scan_id = 0;
1408 }
1409
1410 if (sc->sc_amrr_id != 0) {
1411 (void) untimeout(sc->sc_amrr_id);
1412 sc->sc_amrr_id = 0;
1413 }
1414
1415 switch (nstate) {
1416 case IEEE80211_S_INIT:
1417 if (ostate == IEEE80211_S_RUN) {
1418 /* abort TSF synchronization */
1419 tmp = rum_read(sc, RT2573_TXRX_CSR9);
1420 rum_write(sc, RT2573_TXRX_CSR9, tmp & ~0x00ffffff);
1421 }
1422 break;
1423
1424 case IEEE80211_S_SCAN:
1425 rum_set_chan(sc, ic->ic_curchan);
1426 sc->sc_scan_id = timeout(rum_next_scan, (void *)sc,
1427 drv_usectohz(sc->dwelltime * 1000));
1428 break;
1429
1430 case IEEE80211_S_AUTH:
1431 rum_set_chan(sc, ic->ic_curchan);
1432 break;
1433
1434 case IEEE80211_S_ASSOC:
1435 rum_set_chan(sc, ic->ic_curchan);
1436 break;
1437
1438 case IEEE80211_S_RUN:
1439 rum_set_chan(sc, ic->ic_curchan);
1440
1441 ni = ic->ic_bss;
1442
1443 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1444 rum_update_slot(ic, 1);
1445 rum_enable_mrr(sc);
1446 rum_set_txpreamble(sc);
1447 rum_set_basicrates(sc);
1448 rum_set_bssid(sc, ni->in_bssid);
1449 }
1450
1451 if (ic->ic_opmode != IEEE80211_M_MONITOR)
1452 rum_enable_tsf_sync(sc);
1453
1454 /* enable automatic rate adaptation in STA mode */
1455 if (ic->ic_opmode == IEEE80211_M_STA &&
1456 ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE)
1457 rum_amrr_start(sc, ni);
1458 break;
1459 }
1460
1461 RAL_UNLOCK(sc);
1462
1463 err = sc->sc_newstate(ic, nstate, arg);
1464 /*
1465 * Finally, start any timers.
1466 */
1467 if (nstate == IEEE80211_S_RUN)
1468 ieee80211_start_watchdog(ic, 1);
1469
1470 return (err);
1471 }
1472
1473 static void
1474 rum_close_pipes(struct rum_softc *sc)
1475 {
1476 usb_flags_t flags = USB_FLAGS_SLEEP;
1477
1478 if (sc->sc_rx_pipeh != NULL) {
1479 usb_pipe_reset(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0);
1480 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0);
1481 sc->sc_rx_pipeh = NULL;
1482 }
1483
1484 if (sc->sc_tx_pipeh != NULL) {
1485 usb_pipe_reset(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0);
1486 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0);
1487 sc->sc_tx_pipeh = NULL;
1488 }
1489 }
1490
1491 static int
1492 rum_open_pipes(struct rum_softc *sc)
1493 {
1494 usb_ep_data_t *ep_node;
1495 usb_pipe_policy_t policy;
1496 int err;
1497
1498 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0,
1499 USB_EP_ATTR_BULK, USB_EP_DIR_OUT);
1500
1501 bzero(&policy, sizeof (usb_pipe_policy_t));
1502 policy.pp_max_async_reqs = RAL_TX_LIST_COUNT;
1503
1504 if ((err = usb_pipe_open(sc->sc_dev,
1505 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP,
1506 &sc->sc_tx_pipeh)) != USB_SUCCESS) {
1507 ral_debug(RAL_DBG_ERR,
1508 "rum_open_pipes(): %x failed to open tx pipe\n", err);
1509 goto fail;
1510 }
1511
1512 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0,
1513 USB_EP_ATTR_BULK, USB_EP_DIR_IN);
1514
1515 bzero(&policy, sizeof (usb_pipe_policy_t));
1516 policy.pp_max_async_reqs = RAL_RX_LIST_COUNT + 32;
1517
1518 if ((err = usb_pipe_open(sc->sc_dev,
1519 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP,
1520 &sc->sc_rx_pipeh)) != USB_SUCCESS) {
1521 ral_debug(RAL_DBG_ERR,
1522 "rum_open_pipes(): %x failed to open rx pipe\n", err);
1523 goto fail;
1524 }
1525
1526 return (USB_SUCCESS);
1527
1528 fail:
1529 if (sc->sc_rx_pipeh != NULL) {
1530 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh,
1531 USB_FLAGS_SLEEP, NULL, 0);
1532 sc->sc_rx_pipeh = NULL;
1533 }
1534
1535 if (sc->sc_tx_pipeh != NULL) {
1536 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh,
1537 USB_FLAGS_SLEEP, NULL, 0);
1538 sc->sc_tx_pipeh = NULL;
1539 }
1540
1541 return (USB_FAILURE);
1542 }
1543
1544 static int
1545 rum_tx_trigger(struct rum_softc *sc, mblk_t *mp)
1546 {
1547 usb_bulk_req_t *req;
1548 int err;
1549
1550 sc->sc_tx_timer = RUM_TX_TIMEOUT;
1551
1552 req = usb_alloc_bulk_req(sc->sc_dev, 0, USB_FLAGS_SLEEP);
1553 if (req == NULL) {
1554 ral_debug(RAL_DBG_ERR,
1555 "rum_tx_trigger(): failed to allocate req");
1556 freemsg(mp);
1557 return (-1);
1558 }
1559
1560 req->bulk_len = msgdsize(mp);
1561 req->bulk_data = mp;
1562 req->bulk_client_private = (usb_opaque_t)sc;
1563 req->bulk_timeout = RUM_TX_TIMEOUT;
1564 req->bulk_attributes = USB_ATTRS_AUTOCLEARING;
1565 req->bulk_cb = rum_txeof;
1566 req->bulk_exc_cb = rum_txeof;
1567 req->bulk_completion_reason = 0;
1568 req->bulk_cb_flags = 0;
1569
1570 if ((err = usb_pipe_bulk_xfer(sc->sc_tx_pipeh, req, 0))
1571 != USB_SUCCESS) {
1572
1573 ral_debug(RAL_DBG_ERR, "rum_tx_trigger(): "
1574 "failed to do tx xfer, %d", err);
1575 usb_free_bulk_req(req);
1576 return (-1);
1577 }
1578
1579 sc->tx_queued++;
1580
1581 return (0);
1582 }
1583
1584 static int
1585 rum_rx_trigger(struct rum_softc *sc)
1586 {
1587 usb_bulk_req_t *req;
1588 int err;
1589
1590 req = usb_alloc_bulk_req(sc->sc_dev, RAL_RXBUF_SIZE, USB_FLAGS_SLEEP);
1591 if (req == NULL) {
1592 ral_debug(RAL_DBG_ERR,
1593 "rum_rx_trigger(): failed to allocate req");
1594 return (-1);
1595 }
1596
1597 req->bulk_len = RAL_RXBUF_SIZE;
1598 req->bulk_client_private = (usb_opaque_t)sc;
1599 req->bulk_timeout = 0;
1600 req->bulk_attributes = USB_ATTRS_SHORT_XFER_OK
1601 | USB_ATTRS_AUTOCLEARING;
1602 req->bulk_cb = rum_rxeof;
1603 req->bulk_exc_cb = rum_rxeof;
1604 req->bulk_completion_reason = 0;
1605 req->bulk_cb_flags = 0;
1606
1607 err = usb_pipe_bulk_xfer(sc->sc_rx_pipeh, req, 0);
1608
1609 if (err != USB_SUCCESS) {
1610 ral_debug(RAL_DBG_ERR, "rum_rx_trigger(): "
1611 "failed to do rx xfer, %d", err);
1612 usb_free_bulk_req(req);
1613
1614 return (-1);
1615 }
1616
1617 mutex_enter(&sc->rx_lock);
1618 sc->rx_queued++;
1619 mutex_exit(&sc->rx_lock);
1620
1621 return (0);
1622 }
1623
1624 static void
1625 rum_init_tx_queue(struct rum_softc *sc)
1626 {
1627 sc->tx_queued = 0;
1628 }
1629
1630 static int
1631 rum_init_rx_queue(struct rum_softc *sc)
1632 {
1633 int i;
1634
1635 sc->rx_queued = 0;
1636
1637 for (i = 0; i < RAL_RX_LIST_COUNT; i++) {
1638 if (rum_rx_trigger(sc) != 0) {
1639 return (USB_FAILURE);
1640 }
1641 }
1642
1643 return (USB_SUCCESS);
1644 }
1645
1646 static void
1647 rum_stop(struct rum_softc *sc)
1648 {
1649 struct ieee80211com *ic = &sc->sc_ic;
1650 uint32_t tmp;
1651
1652 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1653 ieee80211_stop_watchdog(ic); /* stop the watchdog */
1654
1655 RAL_LOCK(sc);
1656
1657 sc->sc_tx_timer = 0;
1658 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
1659
1660 /* disable Rx */
1661 tmp = rum_read(sc, RT2573_TXRX_CSR0);
1662 rum_write(sc, RT2573_TXRX_CSR0, tmp | RT2573_DISABLE_RX);
1663
1664 /* reset ASIC */
1665 rum_write(sc, RT2573_MAC_CSR1, 3);
1666 rum_write(sc, RT2573_MAC_CSR1, 0);
1667
1668 rum_close_pipes(sc);
1669
1670 RAL_UNLOCK(sc);
1671 }
1672
1673 static int
1674 rum_init(struct rum_softc *sc)
1675 {
1676 struct ieee80211com *ic = &sc->sc_ic;
1677 uint32_t tmp;
1678 int i, ntries;
1679
1680 rum_stop(sc);
1681
1682 /* initialize MAC registers to default values */
1683 for (i = 0; i < RUM_N(rum_def_mac); i++)
1684 rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);
1685
1686 /* set host ready */
1687 rum_write(sc, RT2573_MAC_CSR1, 3);
1688 rum_write(sc, RT2573_MAC_CSR1, 0);
1689
1690 /* wait for BBP/RF to wakeup */
1691 for (ntries = 0; ntries < 1000; ntries++) {
1692 if (rum_read(sc, RT2573_MAC_CSR12) & 8)
1693 break;
1694 rum_write(sc, RT2573_MAC_CSR12, 4); /* force wakeup */
1695 drv_usecwait(1000);
1696 }
1697 if (ntries == 1000) {
1698 ral_debug(RAL_DBG_ERR,
1699 "rum_init(): timeout waiting for BBP/RF to wakeup\n");
1700 goto fail;
1701 }
1702
1703 if (rum_bbp_init(sc) != 0)
1704 goto fail;
1705
1706 /* select default channel */
1707 rum_select_band(sc, ic->ic_curchan);
1708 rum_select_antenna(sc);
1709 rum_set_chan(sc, ic->ic_curchan);
1710
1711 /* clear STA registers */
1712 rum_read_multi(sc, RT2573_STA_CSR0, sc->sta, sizeof (sc->sta));
1713
1714 rum_set_macaddr(sc, ic->ic_macaddr);
1715
1716 /* initialize ASIC */
1717 rum_write(sc, RT2573_MAC_CSR1, 4);
1718
1719 if (rum_open_pipes(sc) != USB_SUCCESS) {
1720 ral_debug(RAL_DBG_ERR, "rum_init(): "
1721 "could not open pipes.\n");
1722 goto fail;
1723 }
1724
1725 rum_init_tx_queue(sc);
1726
1727 if (rum_init_rx_queue(sc) != USB_SUCCESS)
1728 goto fail;
1729
1730 /* update Rx filter */
1731 tmp = rum_read(sc, RT2573_TXRX_CSR0) & 0xffff;
1732 tmp |= RT2573_DROP_PHY_ERROR | RT2573_DROP_CRC_ERROR;
1733 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1734 tmp |= RT2573_DROP_CTL | RT2573_DROP_VER_ERROR |
1735 RT2573_DROP_ACKCTS;
1736 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
1737 tmp |= RT2573_DROP_TODS;
1738 if (!(sc->sc_rcr & RAL_RCR_PROMISC))
1739 tmp |= RT2573_DROP_NOT_TO_ME;
1740 }
1741
1742 rum_write(sc, RT2573_TXRX_CSR0, tmp);
1743 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */
1744
1745 return (DDI_SUCCESS);
1746 fail:
1747 rum_stop(sc);
1748 return (DDI_FAILURE);
1749 }
1750
1751 static int
1752 rum_disconnect(dev_info_t *devinfo)
1753 {
1754 struct rum_softc *sc;
1755 struct ieee80211com *ic;
1756
1757 /*
1758 * We can't call rum_stop() here, since the hardware is removed,
1759 * we can't access the register anymore.
1760 */
1761 sc = ddi_get_soft_state(rum_soft_state_p, ddi_get_instance(devinfo));
1762 ASSERT(sc != NULL);
1763
1764 if (!RAL_IS_RUNNING(sc)) /* different device or not inited */
1765 return (DDI_SUCCESS);
1766
1767 ic = &sc->sc_ic;
1768 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1769 ieee80211_stop_watchdog(ic); /* stop the watchdog */
1770
1771 RAL_LOCK(sc);
1772
1773 sc->sc_tx_timer = 0;
1774 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
1775
1776 rum_close_pipes(sc);
1777
1778 RAL_UNLOCK(sc);
1779
1780 return (DDI_SUCCESS);
1781 }
1782
1783 static int
1784 rum_reconnect(dev_info_t *devinfo)
1785 {
1786 struct rum_softc *sc;
1787 int err;
1788
1789 sc = ddi_get_soft_state(rum_soft_state_p, ddi_get_instance(devinfo));
1790 ASSERT(sc != NULL);
1791
1792 /* check device changes after disconnect */
1793 if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1,
1794 USB_CHK_BASIC | USB_CHK_CFG, NULL) != USB_SUCCESS) {
1795 ral_debug(RAL_DBG_ERR, "different device connected\n");
1796 return (DDI_FAILURE);
1797 }
1798
1799 err = rum_load_microcode(sc);
1800 if (err != USB_SUCCESS) {
1801 ral_debug(RAL_DBG_ERR, "could not load 8051 microcode\n");
1802 goto fail;
1803 }
1804
1805 err = rum_init(sc);
1806 fail:
1807 return (err);
1808 }
1809
1810 static void
1811 rum_resume(struct rum_softc *sc)
1812 {
1813 int err;
1814
1815 /* check device changes after suspend */
1816 if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1,
1817 USB_CHK_BASIC | USB_CHK_CFG, NULL) != USB_SUCCESS) {
1818 ral_debug(RAL_DBG_ERR, "no or different device connected\n");
1819 return;
1820 }
1821
1822 err = rum_load_microcode(sc);
1823 if (err != USB_SUCCESS) {
1824 ral_debug(RAL_DBG_ERR, "could not load 8051 microcode\n");
1825 return;
1826 }
1827
1828 (void) rum_init(sc);
1829 }
1830
1831 #define RUM_AMRR_MIN_SUCCESS_THRESHOLD 1
1832 #define RUM_AMRR_MAX_SUCCESS_THRESHOLD 10
1833
1834 /*
1835 * Naive implementation of the Adaptive Multi Rate Retry algorithm:
1836 * "IEEE 802.11 Rate Adaptation: A Practical Approach"
1837 * Mathieu Lacage, Hossein Manshaei, Thierry Turletti
1838 * INRIA Sophia - Projet Planete
1839 * http://www-sop.inria.fr/rapports/sophia/RR-5208.html
1840 *
1841 * This algorithm is particularly well suited for rum since it does not
1842 * require per-frame retry statistics. Note however that since h/w does
1843 * not provide per-frame stats, we can't do per-node rate adaptation and
1844 * thus automatic rate adaptation is only enabled in STA operating mode.
1845 */
1846 #define is_success(amrr) \
1847 ((amrr)->retrycnt < (amrr)->txcnt / 10)
1848 #define is_failure(amrr) \
1849 ((amrr)->retrycnt > (amrr)->txcnt / 3)
1850 #define is_enough(amrr) \
1851 ((amrr)->txcnt > 10)
1852 #define is_min_rate(ni) \
1853 ((ni)->in_txrate == 0)
1854 #define is_max_rate(ni) \
1855 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1)
1856 #define increase_rate(ni) \
1857 ((ni)->in_txrate++)
1858 #define decrease_rate(ni) \
1859 ((ni)->in_txrate--)
1860 #define reset_cnt(amrr) do { \
1861 (amrr)->txcnt = (amrr)->retrycnt = 0; \
1862 _NOTE(CONSTCOND) \
1863 } while (/* CONSTCOND */0)
1864
1865 static void
1866 rum_ratectl(struct rum_amrr *amrr, struct ieee80211_node *ni)
1867 {
1868 int need_change = 0;
1869
1870 if (is_success(amrr) && is_enough(amrr)) {
1871 amrr->success++;
1872 if (amrr->success >= amrr->success_threshold &&
1873 !is_max_rate(ni)) {
1874 amrr->recovery = 1;
1875 amrr->success = 0;
1876 increase_rate(ni);
1877 need_change = 1;
1878 } else {
1879 amrr->recovery = 0;
1880 }
1881 } else if (is_failure(amrr)) {
1882 amrr->success = 0;
1883 if (!is_min_rate(ni)) {
1884 if (amrr->recovery) {
1885 amrr->success_threshold *= 2;
1886 if (amrr->success_threshold >
1887 RUM_AMRR_MAX_SUCCESS_THRESHOLD)
1888 amrr->success_threshold =
1889 RUM_AMRR_MAX_SUCCESS_THRESHOLD;
1890 } else {
1891 amrr->success_threshold =
1892 RUM_AMRR_MIN_SUCCESS_THRESHOLD;
1893 }
1894 decrease_rate(ni);
1895 need_change = 1;
1896 }
1897 amrr->recovery = 0; /* original paper was incorrect */
1898 }
1899
1900 if (is_enough(amrr) || need_change)
1901 reset_cnt(amrr);
1902 }
1903
1904 static void
1905 rum_amrr_timeout(void *arg)
1906 {
1907 struct rum_softc *sc = (struct rum_softc *)arg;
1908 struct rum_amrr *amrr = &sc->amrr;
1909
1910 rum_read_multi(sc, RT2573_STA_CSR0, sc->sta, sizeof (sc->sta));
1911
1912 /* count TX retry-fail as Tx errors */
1913 sc->sc_tx_err += LE_32(sc->sta[5]) >> 16;
1914 sc->sc_tx_retries += ((LE_32(sc->sta[4]) >> 16) +
1915 (LE_32(sc->sta[5]) & 0xffff));
1916
1917 amrr->retrycnt =
1918 (LE_32(sc->sta[4]) >> 16) + /* TX one-retry ok count */
1919 (LE_32(sc->sta[5]) & 0xffff) + /* TX more-retry ok count */
1920 (LE_32(sc->sta[5]) >> 16); /* TX retry-fail count */
1921
1922 amrr->txcnt =
1923 amrr->retrycnt +
1924 (LE_32(sc->sta[4]) & 0xffff); /* TX no-retry ok count */
1925
1926 rum_ratectl(amrr, sc->sc_ic.ic_bss);
1927
1928 sc->sc_amrr_id = timeout(rum_amrr_timeout, (void *)sc,
1929 drv_usectohz(1000 * 1000)); /* 1 second */
1930 }
1931
1932 static void
1933 rum_amrr_start(struct rum_softc *sc, struct ieee80211_node *ni)
1934 {
1935 struct rum_amrr *amrr = &sc->amrr;
1936 int i;
1937
1938 /* clear statistic registers (STA_CSR0 to STA_CSR5) */
1939 rum_read_multi(sc, RT2573_STA_CSR0, sc->sta, sizeof (sc->sta));
1940
1941 amrr->success = 0;
1942 amrr->recovery = 0;
1943 amrr->txcnt = amrr->retrycnt = 0;
1944 amrr->success_threshold = RUM_AMRR_MIN_SUCCESS_THRESHOLD;
1945
1946 /* set rate to some reasonable initial value */
1947 for (i = ni->in_rates.ir_nrates - 1;
1948 i > 0 && (ni->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72;
1949 i--) {
1950 }
1951
1952 ni->in_txrate = i;
1953
1954 sc->sc_amrr_id = timeout(rum_amrr_timeout, (void *)sc,
1955 drv_usectohz(1000 * 1000)); /* 1 second */
1956 }
1957
1958 void
1959 rum_watchdog(void *arg)
1960 {
1961 struct rum_softc *sc = arg;
1962 struct ieee80211com *ic = &sc->sc_ic;
1963 int ntimer = 0;
1964
1965 RAL_LOCK(sc);
1966 ic->ic_watchdog_timer = 0;
1967
1968 if (!RAL_IS_RUNNING(sc)) {
1969 RAL_UNLOCK(sc);
1970 return;
1971 }
1972
1973 if (sc->sc_tx_timer > 0) {
1974 if (--sc->sc_tx_timer == 0) {
1975 ral_debug(RAL_DBG_ERR, "tx timer timeout\n");
1976 RAL_UNLOCK(sc);
1977 (void) rum_init(sc);
1978 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1979 return;
1980 }
1981 }
1982
1983 if (ic->ic_state == IEEE80211_S_RUN)
1984 ntimer = 1;
1985
1986 RAL_UNLOCK(sc);
1987
1988 ieee80211_watchdog(ic);
1989
1990 if (ntimer)
1991 ieee80211_start_watchdog(ic, ntimer);
1992 }
1993
1994 static int
1995 rum_m_start(void *arg)
1996 {
1997 struct rum_softc *sc = (struct rum_softc *)arg;
1998 int err;
1999
2000 /*
2001 * initialize RT2501USB hardware
2002 */
2003 err = rum_init(sc);
2004 if (err != DDI_SUCCESS) {
2005 ral_debug(RAL_DBG_ERR, "device configuration failed\n");
2006 goto fail;
2007 }
2008 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */
2009 return (err);
2010
2011 fail:
2012 rum_stop(sc);
2013 return (err);
2014 }
2015
2016 static void
2017 rum_m_stop(void *arg)
2018 {
2019 struct rum_softc *sc = (struct rum_softc *)arg;
2020
2021 (void) rum_stop(sc);
2022 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
2023 }
2024
2025 static int
2026 rum_m_unicst(void *arg, const uint8_t *macaddr)
2027 {
2028 struct rum_softc *sc = (struct rum_softc *)arg;
2029 struct ieee80211com *ic = &sc->sc_ic;
2030
2031 ral_debug(RAL_DBG_MSG, "rum_m_unicst(): " MACSTR "\n",
2032 MAC2STR(macaddr));
2033
2034 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr);
2035 (void) rum_set_macaddr(sc, (uint8_t *)macaddr);
2036 (void) rum_init(sc);
2037
2038 return (0);
2039 }
2040
2041 /*ARGSUSED*/
2042 static int
2043 rum_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
2044 {
2045 return (0);
2046 }
2047
2048 static int
2049 rum_m_promisc(void *arg, boolean_t on)
2050 {
2051 struct rum_softc *sc = (struct rum_softc *)arg;
2052
2053 if (on) {
2054 sc->sc_rcr |= RAL_RCR_PROMISC;
2055 sc->sc_rcr |= RAL_RCR_MULTI;
2056 } else {
2057 sc->sc_rcr &= ~RAL_RCR_PROMISC;
2058 sc->sc_rcr &= ~RAL_RCR_MULTI;
2059 }
2060
2061 rum_update_promisc(sc);
2062 return (0);
2063 }
2064
2065 /*
2066 * callback functions for /get/set properties
2067 */
2068 static int
2069 rum_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2070 uint_t wldp_length, const void *wldp_buf)
2071 {
2072 struct rum_softc *sc = (struct rum_softc *)arg;
2073 struct ieee80211com *ic = &sc->sc_ic;
2074 int err;
2075
2076 err = ieee80211_setprop(ic, pr_name, wldp_pr_num,
2077 wldp_length, wldp_buf);
2078 RAL_LOCK(sc);
2079 if (err == ENETRESET) {
2080 if (RAL_IS_RUNNING(sc)) {
2081 RAL_UNLOCK(sc);
2082 (void) rum_init(sc);
2083 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2084 RAL_LOCK(sc);
2085 }
2086 err = 0;
2087 }
2088 RAL_UNLOCK(sc);
2089
2090 return (err);
2091 }
2092
2093 static int
2094 rum_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2095 uint_t wldp_length, void *wldp_buf)
2096 {
2097 struct rum_softc *sc = (struct rum_softc *)arg;
2098 int err;
2099
2100 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2101 wldp_length, wldp_buf);
2102
2103 return (err);
2104 }
2105
2106 static void
2107 rum_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2108 mac_prop_info_handle_t prh)
2109 {
2110 struct rum_softc *sc = (struct rum_softc *)arg;
2111
2112 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
2113 }
2114
2115 static void
2116 rum_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2117 {
2118 struct rum_softc *sc = (struct rum_softc *)arg;
2119 struct ieee80211com *ic = &sc->sc_ic;
2120 int err;
2121
2122 err = ieee80211_ioctl(ic, wq, mp);
2123 RAL_LOCK(sc);
2124 if (err == ENETRESET) {
2125 if (RAL_IS_RUNNING(sc)) {
2126 RAL_UNLOCK(sc);
2127 (void) rum_init(sc);
2128 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2129 RAL_LOCK(sc);
2130 }
2131 }
2132 RAL_UNLOCK(sc);
2133 }
2134
2135 static int
2136 rum_m_stat(void *arg, uint_t stat, uint64_t *val)
2137 {
2138 struct rum_softc *sc = (struct rum_softc *)arg;
2139 ieee80211com_t *ic = &sc->sc_ic;
2140 ieee80211_node_t *ni;
2141 struct ieee80211_rateset *rs;
2142
2143 RAL_LOCK(sc);
2144
2145 ni = ic->ic_bss;
2146 rs = &ni->in_rates;
2147
2148 switch (stat) {
2149 case MAC_STAT_IFSPEED:
2150 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
2151 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
2152 : ic->ic_fixed_rate) * 500000ull;
2153 break;
2154 case MAC_STAT_NOXMTBUF:
2155 *val = sc->sc_tx_nobuf;
2156 break;
2157 case MAC_STAT_NORCVBUF:
2158 *val = sc->sc_rx_nobuf;
2159 break;
2160 case MAC_STAT_IERRORS:
2161 *val = sc->sc_rx_err;
2162 break;
2163 case MAC_STAT_RBYTES:
2164 *val = ic->ic_stats.is_rx_bytes;
2165 break;
2166 case MAC_STAT_IPACKETS:
2167 *val = ic->ic_stats.is_rx_frags;
2168 break;
2169 case MAC_STAT_OBYTES:
2170 *val = ic->ic_stats.is_tx_bytes;
2171 break;
2172 case MAC_STAT_OPACKETS:
2173 *val = ic->ic_stats.is_tx_frags;
2174 break;
2175 case MAC_STAT_OERRORS:
2176 case WIFI_STAT_TX_FAILED:
2177 *val = sc->sc_tx_err;
2178 break;
2179 case WIFI_STAT_TX_RETRANS:
2180 *val = sc->sc_tx_retries;
2181 break;
2182 case WIFI_STAT_FCS_ERRORS:
2183 case WIFI_STAT_WEP_ERRORS:
2184 case WIFI_STAT_TX_FRAGS:
2185 case WIFI_STAT_MCAST_TX:
2186 case WIFI_STAT_RTS_SUCCESS:
2187 case WIFI_STAT_RTS_FAILURE:
2188 case WIFI_STAT_ACK_FAILURE:
2189 case WIFI_STAT_RX_FRAGS:
2190 case WIFI_STAT_MCAST_RX:
2191 case WIFI_STAT_RX_DUPS:
2192 RAL_UNLOCK(sc);
2193 return (ieee80211_stat(ic, stat, val));
2194 default:
2195 RAL_UNLOCK(sc);
2196 return (ENOTSUP);
2197 }
2198 RAL_UNLOCK(sc);
2199
2200 return (0);
2201 }
2202
2203 static int
2204 rum_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2205 {
2206 struct rum_softc *sc;
2207 struct ieee80211com *ic;
2208 int err, i, ntries;
2209 uint32_t tmp;
2210 int instance;
2211
2212 char strbuf[32];
2213
2214 wifi_data_t wd = { 0 };
2215 mac_register_t *macp;
2216
2217 switch (cmd) {
2218 case DDI_ATTACH:
2219 break;
2220 case DDI_RESUME:
2221 sc = ddi_get_soft_state(rum_soft_state_p,
2222 ddi_get_instance(devinfo));
2223 ASSERT(sc != NULL);
2224 rum_resume(sc);
2225 return (DDI_SUCCESS);
2226 default:
2227 return (DDI_FAILURE);
2228 }
2229
2230 instance = ddi_get_instance(devinfo);
2231
2232 if (ddi_soft_state_zalloc(rum_soft_state_p, instance) != DDI_SUCCESS) {
2233 ral_debug(RAL_DBG_MSG, "rum_attach(): "
2234 "unable to alloc soft_state_p\n");
2235 return (DDI_FAILURE);
2236 }
2237
2238 sc = ddi_get_soft_state(rum_soft_state_p, instance);
2239 ic = (ieee80211com_t *)&sc->sc_ic;
2240 sc->sc_dev = devinfo;
2241
2242 if (usb_client_attach(devinfo, USBDRV_VERSION, 0) != USB_SUCCESS) {
2243 ral_debug(RAL_DBG_ERR,
2244 "rum_attach(): usb_client_attach failed\n");
2245 goto fail1;
2246 }
2247
2248 if (usb_get_dev_data(devinfo, &sc->sc_udev,
2249 USB_PARSE_LVL_ALL, 0) != USB_SUCCESS) {
2250 sc->sc_udev = NULL;
2251 goto fail2;
2252 }
2253
2254 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
2255 mutex_init(&sc->tx_lock, NULL, MUTEX_DRIVER, NULL);
2256 mutex_init(&sc->rx_lock, NULL, MUTEX_DRIVER, NULL);
2257
2258 /* retrieve RT2573 rev. no */
2259 for (ntries = 0; ntries < 1000; ntries++) {
2260 if ((tmp = rum_read(sc, RT2573_MAC_CSR0)) != 0)
2261 break;
2262 drv_usecwait(1000);
2263 }
2264 if (ntries == 1000) {
2265 ral_debug(RAL_DBG_ERR,
2266 "rum_attach(): timeout waiting for chip to settle\n");
2267 goto fail3;
2268 }
2269
2270 /* retrieve MAC address and various other things from EEPROM */
2271 rum_read_eeprom(sc);
2272
2273 ral_debug(RAL_DBG_MSG, "rum: MAC/BBP RT2573 (rev 0x%05x), RF %s\n",
2274 tmp, rum_get_rf(sc->rf_rev));
2275
2276 err = rum_load_microcode(sc);
2277 if (err != USB_SUCCESS) {
2278 ral_debug(RAL_DBG_ERR, "could not load 8051 microcode\n");
2279 goto fail3;
2280 }
2281
2282 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
2283 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
2284 ic->ic_state = IEEE80211_S_INIT;
2285
2286 ic->ic_maxrssi = 63;
2287 ic->ic_set_shortslot = rum_update_slot;
2288 ic->ic_xmit = rum_send;
2289
2290 /* set device capabilities */
2291 ic->ic_caps =
2292 IEEE80211_C_TXPMGT | /* tx power management */
2293 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
2294 IEEE80211_C_SHSLOT; /* short slot time supported */
2295
2296 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
2297
2298 #define IEEE80211_CHAN_A \
2299 (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM)
2300
2301 if (sc->rf_rev == RT2573_RF_5225 || sc->rf_rev == RT2573_RF_5226) {
2302 /* set supported .11a rates */
2303 ic->ic_sup_rates[IEEE80211_MODE_11A] = rum_rateset_11a;
2304
2305 /* set supported .11a channels */
2306 for (i = 34; i <= 46; i += 4) {
2307 ic->ic_sup_channels[i].ich_freq =
2308 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2309 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2310 }
2311 for (i = 36; i <= 64; i += 4) {
2312 ic->ic_sup_channels[i].ich_freq =
2313 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2314 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2315 }
2316 for (i = 100; i <= 140; i += 4) {
2317 ic->ic_sup_channels[i].ich_freq =
2318 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2319 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2320 }
2321 for (i = 149; i <= 165; i += 4) {
2322 ic->ic_sup_channels[i].ich_freq =
2323 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2324 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2325 }
2326 }
2327
2328 /* set supported .11b and .11g rates */
2329 ic->ic_sup_rates[IEEE80211_MODE_11B] = rum_rateset_11b;
2330 ic->ic_sup_rates[IEEE80211_MODE_11G] = rum_rateset_11g;
2331
2332 /* set supported .11b and .11g channels (1 through 14) */
2333 for (i = 1; i <= 14; i++) {
2334 ic->ic_sup_channels[i].ich_freq =
2335 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
2336 ic->ic_sup_channels[i].ich_flags =
2337 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
2338 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
2339 }
2340
2341 ieee80211_attach(ic);
2342
2343 /* register WPA door */
2344 ieee80211_register_door(ic, ddi_driver_name(devinfo),
2345 ddi_get_instance(devinfo));
2346
2347 /* override state transition machine */
2348 sc->sc_newstate = ic->ic_newstate;
2349 ic->ic_newstate = rum_newstate;
2350 ic->ic_watchdog = rum_watchdog;
2351 ieee80211_media_init(ic);
2352 ic->ic_def_txkey = 0;
2353
2354 sc->sc_rcr = 0;
2355 sc->dwelltime = 300;
2356 sc->sc_flags = 0;
2357
2358 /*
2359 * Provide initial settings for the WiFi plugin; whenever this
2360 * information changes, we need to call mac_plugindata_update()
2361 */
2362 wd.wd_opmode = ic->ic_opmode;
2363 wd.wd_secalloc = WIFI_SEC_NONE;
2364 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
2365
2366 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
2367 ral_debug(RAL_DBG_ERR, "rum_attach(): "
2368 "MAC version mismatch\n");
2369 goto fail3;
2370 }
2371
2372 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
2373 macp->m_driver = sc;
2374 macp->m_dip = devinfo;
2375 macp->m_src_addr = ic->ic_macaddr;
2376 macp->m_callbacks = &rum_m_callbacks;
2377 macp->m_min_sdu = 0;
2378 macp->m_max_sdu = IEEE80211_MTU;
2379 macp->m_pdata = &wd;
2380 macp->m_pdata_size = sizeof (wd);
2381
2382 err = mac_register(macp, &ic->ic_mach);
2383 mac_free(macp);
2384 if (err != 0) {
2385 ral_debug(RAL_DBG_ERR, "rum_attach(): "
2386 "mac_register() err %x\n", err);
2387 goto fail3;
2388 }
2389
2390 if (usb_register_hotplug_cbs(devinfo, rum_disconnect,
2391 rum_reconnect) != USB_SUCCESS) {
2392 ral_debug(RAL_DBG_ERR,
2393 "rum_attach() failed to register events");
2394 goto fail4;
2395 }
2396
2397 /*
2398 * Create minor node of type DDI_NT_NET_WIFI
2399 */
2400 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
2401 "rum", instance);
2402 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
2403 instance + 1, DDI_NT_NET_WIFI, 0);
2404
2405 if (err != DDI_SUCCESS)
2406 ral_debug(RAL_DBG_ERR, "ddi_create_minor_node() failed\n");
2407
2408 /*
2409 * Notify link is down now
2410 */
2411 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
2412 return (DDI_SUCCESS);
2413
2414 fail4:
2415 (void) mac_unregister(ic->ic_mach);
2416 fail3:
2417 mutex_destroy(&sc->sc_genlock);
2418 mutex_destroy(&sc->tx_lock);
2419 mutex_destroy(&sc->rx_lock);
2420 fail2:
2421 usb_client_detach(sc->sc_dev, sc->sc_udev);
2422 fail1:
2423 ddi_soft_state_free(rum_soft_state_p, ddi_get_instance(devinfo));
2424
2425 return (DDI_FAILURE);
2426 }
2427
2428 static int
2429 rum_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
2430 {
2431 struct rum_softc *sc;
2432
2433 sc = ddi_get_soft_state(rum_soft_state_p, ddi_get_instance(devinfo));
2434 ASSERT(sc != NULL);
2435
2436 switch (cmd) {
2437 case DDI_DETACH:
2438 break;
2439 case DDI_SUSPEND:
2440 if (RAL_IS_RUNNING(sc))
2441 (void) rum_stop(sc);
2442 return (DDI_SUCCESS);
2443 default:
2444 return (DDI_FAILURE);
2445 }
2446
2447 rum_stop(sc);
2448 usb_unregister_hotplug_cbs(devinfo);
2449
2450 /*
2451 * Unregister from the MAC layer subsystem
2452 */
2453 if (mac_unregister(sc->sc_ic.ic_mach) != 0)
2454 return (DDI_FAILURE);
2455
2456 /*
2457 * detach ieee80211 layer
2458 */
2459 ieee80211_detach(&sc->sc_ic);
2460
2461 mutex_destroy(&sc->sc_genlock);
2462 mutex_destroy(&sc->tx_lock);
2463 mutex_destroy(&sc->rx_lock);
2464
2465 /* pipes will be closed in rum_stop() */
2466 usb_client_detach(devinfo, sc->sc_udev);
2467 sc->sc_udev = NULL;
2468
2469 ddi_remove_minor_node(devinfo, NULL);
2470 ddi_soft_state_free(rum_soft_state_p, ddi_get_instance(devinfo));
2471
2472 return (DDI_SUCCESS);
2473 }
2474
2475 int
2476 _info(struct modinfo *modinfop)
2477 {
2478 return (mod_info(&modlinkage, modinfop));
2479 }
2480
2481 int
2482 _init(void)
2483 {
2484 int status;
2485
2486 status = ddi_soft_state_init(&rum_soft_state_p,
2487 sizeof (struct rum_softc), 1);
2488 if (status != 0)
2489 return (status);
2490
2491 mac_init_ops(&rum_dev_ops, "rum");
2492 status = mod_install(&modlinkage);
2493 if (status != 0) {
2494 mac_fini_ops(&rum_dev_ops);
2495 ddi_soft_state_fini(&rum_soft_state_p);
2496 }
2497 return (status);
2498 }
2499
2500 int
2501 _fini(void)
2502 {
2503 int status;
2504
2505 status = mod_remove(&modlinkage);
2506 if (status == 0) {
2507 mac_fini_ops(&rum_dev_ops);
2508 ddi_soft_state_fini(&rum_soft_state_p);
2509 }
2510 return (status);
2511 }