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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/common/io/iwh/iwh.c
+++ new/usr/src/uts/common/io/iwh/iwh.c
1 1 /*
2 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 3 * Use is subject to license terms.
4 4 */
5 5
6 6 /*
7 7 * Copyright (c) 2009, Intel Corporation
8 8 * All rights reserved.
9 9 */
10 10
11 11 /*
12 12 * Copyright (c) 2006
13 13 * Copyright (c) 2007
14 14 * Damien Bergamini <damien.bergamini@free.fr>
15 15 *
16 16 * Permission to use, copy, modify, and distribute this software for any
17 17 * purpose with or without fee is hereby granted, provided that the above
18 18 * copyright notice and this permission notice appear in all copies.
19 19 *
20 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
21 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
22 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
23 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
24 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
25 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
26 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
27 27 */
28 28
29 29 /*
30 30 * Intel(R) WiFi Link 5100/5300 Driver
31 31 */
32 32
33 33 #include <sys/types.h>
34 34 #include <sys/byteorder.h>
35 35 #include <sys/conf.h>
36 36 #include <sys/cmn_err.h>
37 37 #include <sys/stat.h>
38 38 #include <sys/ddi.h>
39 39 #include <sys/sunddi.h>
40 40 #include <sys/strsubr.h>
41 41 #include <sys/ethernet.h>
42 42 #include <inet/common.h>
43 43 #include <inet/nd.h>
44 44 #include <inet/mi.h>
45 45 #include <sys/note.h>
46 46 #include <sys/stream.h>
47 47 #include <sys/strsun.h>
48 48 #include <sys/modctl.h>
49 49 #include <sys/devops.h>
50 50 #include <sys/dlpi.h>
51 51 #include <sys/mac_provider.h>
52 52 #include <sys/mac_wifi.h>
53 53 #include <sys/net80211.h>
54 54 #include <sys/net80211_proto.h>
55 55 #include <sys/net80211_ht.h>
56 56 #include <sys/varargs.h>
57 57 #include <sys/policy.h>
58 58 #include <sys/pci.h>
59 59
60 60 #include "iwh_calibration.h"
61 61 #include "iwh_hw.h"
62 62 #include "iwh_eeprom.h"
63 63 #include "iwh_var.h"
64 64 #include <inet/wifi_ioctl.h>
65 65
66 66 #ifdef DEBUG
67 67 #define IWH_DEBUG_80211 (1 << 0)
68 68 #define IWH_DEBUG_CMD (1 << 1)
69 69 #define IWH_DEBUG_DMA (1 << 2)
70 70 #define IWH_DEBUG_EEPROM (1 << 3)
71 71 #define IWH_DEBUG_FW (1 << 4)
72 72 #define IWH_DEBUG_HW (1 << 5)
73 73 #define IWH_DEBUG_INTR (1 << 6)
74 74 #define IWH_DEBUG_MRR (1 << 7)
75 75 #define IWH_DEBUG_PIO (1 << 8)
76 76 #define IWH_DEBUG_RX (1 << 9)
77 77 #define IWH_DEBUG_SCAN (1 << 10)
78 78 #define IWH_DEBUG_TX (1 << 11)
79 79 #define IWH_DEBUG_RATECTL (1 << 12)
80 80 #define IWH_DEBUG_RADIO (1 << 13)
81 81 #define IWH_DEBUG_RESUME (1 << 14)
82 82 #define IWH_DEBUG_CALIBRATION (1 << 15)
83 83 #define IWH_DEBUG_BA (1 << 16)
84 84 #define IWH_DEBUG_RXON (1 << 17)
85 85 #define IWH_DEBUG_HWRATE (1 << 18)
86 86 #define IWH_DEBUG_HTRATE (1 << 19)
87 87 #define IWH_DEBUG_QOS (1 << 20)
88 88 /*
89 89 * if want to see debug message of a given section,
90 90 * please set this flag to one of above values
91 91 */
92 92 uint32_t iwh_dbg_flags = 0;
93 93 #define IWH_DBG(x) \
94 94 iwh_dbg x
95 95 #else
96 96 #define IWH_DBG(x)
97 97 #endif
98 98
99 99 #define MS(v, f) (((v) & f) >> f##_S)
100 100
101 101 static void *iwh_soft_state_p = NULL;
102 102
103 103 /*
104 104 * ucode will be compiled into driver image
105 105 */
106 106 static uint8_t iwh_fw_5000_bin[] = {
107 107 #include "fw-iw/fw_5000/iwh_5000.ucode"
108 108 };
109 109
110 110 static uint8_t iwh_fw_5150_bin[] = {
111 111 #include "fw-iw/fw_5150/iwh_5150.ucode"
112 112 };
113 113
114 114 /*
115 115 * DMA attributes for a shared page
116 116 */
117 117 static ddi_dma_attr_t sh_dma_attr = {
118 118 DMA_ATTR_V0, /* version of this structure */
119 119 0, /* lowest usable address */
120 120 0xffffffffU, /* highest usable address */
121 121 0xffffffffU, /* maximum DMAable byte count */
122 122 0x1000, /* alignment in bytes */
123 123 0x1000, /* burst sizes (any?) */
124 124 1, /* minimum transfer */
125 125 0xffffffffU, /* maximum transfer */
126 126 0xffffffffU, /* maximum segment length */
127 127 1, /* maximum number of segments */
128 128 1, /* granularity */
129 129 0, /* flags (reserved) */
130 130 };
131 131
132 132 /*
133 133 * DMA attributes for a keep warm DRAM descriptor
134 134 */
135 135 static ddi_dma_attr_t kw_dma_attr = {
136 136 DMA_ATTR_V0, /* version of this structure */
137 137 0, /* lowest usable address */
138 138 0xffffffffU, /* highest usable address */
139 139 0xffffffffU, /* maximum DMAable byte count */
140 140 0x1000, /* alignment in bytes */
141 141 0x1000, /* burst sizes (any?) */
142 142 1, /* minimum transfer */
143 143 0xffffffffU, /* maximum transfer */
144 144 0xffffffffU, /* maximum segment length */
145 145 1, /* maximum number of segments */
146 146 1, /* granularity */
147 147 0, /* flags (reserved) */
148 148 };
149 149
150 150 /*
151 151 * DMA attributes for a ring descriptor
152 152 */
153 153 static ddi_dma_attr_t ring_desc_dma_attr = {
154 154 DMA_ATTR_V0, /* version of this structure */
155 155 0, /* lowest usable address */
156 156 0xffffffffU, /* highest usable address */
157 157 0xffffffffU, /* maximum DMAable byte count */
158 158 0x100, /* alignment in bytes */
159 159 0x100, /* burst sizes (any?) */
160 160 1, /* minimum transfer */
161 161 0xffffffffU, /* maximum transfer */
162 162 0xffffffffU, /* maximum segment length */
163 163 1, /* maximum number of segments */
164 164 1, /* granularity */
165 165 0, /* flags (reserved) */
166 166 };
167 167
168 168 /*
169 169 * DMA attributes for a cmd
170 170 */
171 171 static ddi_dma_attr_t cmd_dma_attr = {
172 172 DMA_ATTR_V0, /* version of this structure */
173 173 0, /* lowest usable address */
174 174 0xffffffffU, /* highest usable address */
175 175 0xffffffffU, /* maximum DMAable byte count */
176 176 4, /* alignment in bytes */
177 177 0x100, /* burst sizes (any?) */
178 178 1, /* minimum transfer */
179 179 0xffffffffU, /* maximum transfer */
180 180 0xffffffffU, /* maximum segment length */
181 181 1, /* maximum number of segments */
182 182 1, /* granularity */
183 183 0, /* flags (reserved) */
184 184 };
185 185
186 186 /*
187 187 * DMA attributes for a rx buffer
188 188 */
189 189 static ddi_dma_attr_t rx_buffer_dma_attr = {
190 190 DMA_ATTR_V0, /* version of this structure */
191 191 0, /* lowest usable address */
192 192 0xffffffffU, /* highest usable address */
193 193 0xffffffffU, /* maximum DMAable byte count */
194 194 0x100, /* alignment in bytes */
195 195 0x100, /* burst sizes (any?) */
196 196 1, /* minimum transfer */
197 197 0xffffffffU, /* maximum transfer */
198 198 0xffffffffU, /* maximum segment length */
199 199 1, /* maximum number of segments */
200 200 1, /* granularity */
201 201 0, /* flags (reserved) */
202 202 };
203 203
204 204 /*
205 205 * DMA attributes for a tx buffer.
206 206 * the maximum number of segments is 4 for the hardware.
207 207 * now all the wifi drivers put the whole frame in a single
208 208 * descriptor, so we define the maximum number of segments 1,
209 209 * just the same as the rx_buffer. we consider leverage the HW
210 210 * ability in the future, that is why we don't define rx and tx
211 211 * buffer_dma_attr as the same.
212 212 */
213 213 static ddi_dma_attr_t tx_buffer_dma_attr = {
214 214 DMA_ATTR_V0, /* version of this structure */
215 215 0, /* lowest usable address */
216 216 0xffffffffU, /* highest usable address */
217 217 0xffffffffU, /* maximum DMAable byte count */
218 218 4, /* alignment in bytes */
219 219 0x100, /* burst sizes (any?) */
220 220 1, /* minimum transfer */
221 221 0xffffffffU, /* maximum transfer */
222 222 0xffffffffU, /* maximum segment length */
223 223 1, /* maximum number of segments */
224 224 1, /* granularity */
225 225 0, /* flags (reserved) */
226 226 };
227 227
228 228 /*
229 229 * DMA attributes for text and data part in the firmware
230 230 */
231 231 static ddi_dma_attr_t fw_dma_attr = {
232 232 DMA_ATTR_V0, /* version of this structure */
233 233 0, /* lowest usable address */
234 234 0xffffffffU, /* highest usable address */
235 235 0x7fffffff, /* maximum DMAable byte count */
236 236 0x10, /* alignment in bytes */
237 237 0x100, /* burst sizes (any?) */
238 238 1, /* minimum transfer */
239 239 0xffffffffU, /* maximum transfer */
240 240 0xffffffffU, /* maximum segment length */
241 241 1, /* maximum number of segments */
242 242 1, /* granularity */
243 243 0, /* flags (reserved) */
244 244 };
245 245
246 246 /*
247 247 * regs access attributes
248 248 */
249 249 static ddi_device_acc_attr_t iwh_reg_accattr = {
250 250 DDI_DEVICE_ATTR_V0,
251 251 DDI_STRUCTURE_LE_ACC,
252 252 DDI_STRICTORDER_ACC,
253 253 DDI_DEFAULT_ACC
254 254 };
255 255
256 256 /*
257 257 * DMA access attributes for descriptor
258 258 */
259 259 static ddi_device_acc_attr_t iwh_dma_descattr = {
260 260 DDI_DEVICE_ATTR_V0,
261 261 DDI_STRUCTURE_LE_ACC,
262 262 DDI_STRICTORDER_ACC,
263 263 DDI_DEFAULT_ACC
264 264 };
265 265
266 266 /*
267 267 * DMA access attributes
268 268 */
269 269 static ddi_device_acc_attr_t iwh_dma_accattr = {
270 270 DDI_DEVICE_ATTR_V0,
271 271 DDI_NEVERSWAP_ACC,
272 272 DDI_STRICTORDER_ACC,
273 273 DDI_DEFAULT_ACC
274 274 };
275 275
276 276 static int iwh_ring_init(iwh_sc_t *);
277 277 static void iwh_ring_free(iwh_sc_t *);
278 278 static int iwh_alloc_shared(iwh_sc_t *);
279 279 static void iwh_free_shared(iwh_sc_t *);
280 280 static int iwh_alloc_kw(iwh_sc_t *);
281 281 static void iwh_free_kw(iwh_sc_t *);
282 282 static int iwh_alloc_fw_dma(iwh_sc_t *);
283 283 static void iwh_free_fw_dma(iwh_sc_t *);
284 284 static int iwh_alloc_rx_ring(iwh_sc_t *);
285 285 static void iwh_reset_rx_ring(iwh_sc_t *);
286 286 static void iwh_free_rx_ring(iwh_sc_t *);
287 287 static int iwh_alloc_tx_ring(iwh_sc_t *, iwh_tx_ring_t *,
288 288 int, int);
289 289 static void iwh_reset_tx_ring(iwh_sc_t *, iwh_tx_ring_t *);
290 290 static void iwh_free_tx_ring(iwh_tx_ring_t *);
291 291 static ieee80211_node_t *iwh_node_alloc(ieee80211com_t *);
292 292 static void iwh_node_free(ieee80211_node_t *);
293 293 static int iwh_newstate(ieee80211com_t *, enum ieee80211_state, int);
294 294 static void iwh_mac_access_enter(iwh_sc_t *);
295 295 static void iwh_mac_access_exit(iwh_sc_t *);
296 296 static uint32_t iwh_reg_read(iwh_sc_t *, uint32_t);
297 297 static void iwh_reg_write(iwh_sc_t *, uint32_t, uint32_t);
298 298 static int iwh_load_init_firmware(iwh_sc_t *);
299 299 static int iwh_load_run_firmware(iwh_sc_t *);
300 300 static void iwh_tx_intr(iwh_sc_t *, iwh_rx_desc_t *);
301 301 static void iwh_cmd_intr(iwh_sc_t *, iwh_rx_desc_t *);
302 302 static uint_t iwh_intr(caddr_t, caddr_t);
303 303 static int iwh_eep_load(iwh_sc_t *);
304 304 static void iwh_get_mac_from_eep(iwh_sc_t *);
305 305 static int iwh_eep_sem_down(iwh_sc_t *);
306 306 static void iwh_eep_sem_up(iwh_sc_t *);
307 307 static uint_t iwh_rx_softintr(caddr_t, caddr_t);
308 308 static uint8_t iwh_rate_to_plcp(int);
309 309 static int iwh_cmd(iwh_sc_t *, int, const void *, int, int);
310 310 static void iwh_set_led(iwh_sc_t *, uint8_t, uint8_t, uint8_t);
311 311 static int iwh_hw_set_before_auth(iwh_sc_t *);
312 312 static int iwh_scan(iwh_sc_t *);
313 313 static int iwh_config(iwh_sc_t *);
314 314 static void iwh_stop_master(iwh_sc_t *);
315 315 static int iwh_power_up(iwh_sc_t *);
316 316 static int iwh_preinit(iwh_sc_t *);
317 317 static int iwh_init(iwh_sc_t *);
318 318 static void iwh_stop(iwh_sc_t *);
319 319 static int iwh_quiesce(dev_info_t *t);
320 320 static void iwh_amrr_init(iwh_amrr_t *);
321 321 static void iwh_amrr_timeout(iwh_sc_t *);
322 322 static void iwh_amrr_ratectl(void *, ieee80211_node_t *);
323 323 static void iwh_ucode_alive(iwh_sc_t *, iwh_rx_desc_t *);
324 324 static void iwh_rx_phy_intr(iwh_sc_t *, iwh_rx_desc_t *);
325 325 static void iwh_rx_mpdu_intr(iwh_sc_t *, iwh_rx_desc_t *);
326 326 static void iwh_release_calib_buffer(iwh_sc_t *);
327 327 static int iwh_init_common(iwh_sc_t *);
328 328 static uint8_t *iwh_eep_addr_trans(iwh_sc_t *, uint32_t);
329 329 static int iwh_put_seg_fw(iwh_sc_t *, uint32_t, uint32_t, uint32_t);
330 330 static int iwh_alive_common(iwh_sc_t *);
331 331 static void iwh_save_calib_result(iwh_sc_t *, iwh_rx_desc_t *);
332 332 static int iwh_tx_power_table(iwh_sc_t *, int);
333 333 static int iwh_attach(dev_info_t *, ddi_attach_cmd_t);
334 334 static int iwh_detach(dev_info_t *, ddi_detach_cmd_t);
335 335 static void iwh_destroy_locks(iwh_sc_t *);
336 336 static int iwh_send(ieee80211com_t *, mblk_t *, uint8_t);
337 337 static void iwh_thread(iwh_sc_t *);
338 338 static int iwh_run_state_config(iwh_sc_t *);
339 339 static int iwh_fast_recover(iwh_sc_t *);
340 340 static int iwh_wme_update(ieee80211com_t *);
341 341 static int iwh_qosparam_to_hw(iwh_sc_t *, int);
342 342 static int iwh_wme_to_qos_ac(int);
343 343 static uint16_t iwh_cw_e_to_cw(uint8_t);
344 344 static int iwh_wmeparam_check(struct wmeParams *);
345 345 static inline int iwh_wme_tid_qos_ac(int);
346 346 static inline int iwh_qos_ac_to_txq(int);
347 347 static int iwh_wme_tid_to_txq(int);
348 348 static void iwh_init_ht_conf(iwh_sc_t *);
349 349 static void iwh_overwrite_11n_rateset(iwh_sc_t *);
350 350 static void iwh_overwrite_ic_default(iwh_sc_t *);
351 351 static void iwh_config_rxon_chain(iwh_sc_t *);
352 352 static int iwh_add_ap_sta(iwh_sc_t *);
353 353 static int iwh_ap_lq(iwh_sc_t *);
354 354 static void iwh_recv_action(struct ieee80211_node *,
355 355 const uint8_t *, const uint8_t *);
356 356 static int iwh_send_action(struct ieee80211_node *,
357 357 int, int, uint16_t[4]);
358 358 static int iwh_is_max_rate(ieee80211_node_t *);
359 359 static int iwh_is_min_rate(ieee80211_node_t *);
360 360 static void iwh_increase_rate(ieee80211_node_t *);
361 361 static void iwh_decrease_rate(ieee80211_node_t *);
362 362 static int iwh_alloc_dma_mem(iwh_sc_t *, size_t,
363 363 ddi_dma_attr_t *, ddi_device_acc_attr_t *,
364 364 uint_t, iwh_dma_t *);
365 365 static void iwh_free_dma_mem(iwh_dma_t *);
366 366 static int iwh_reset_hw(iwh_sc_t *);
367 367
368 368 /*
369 369 * GLD specific operations
370 370 */
371 371 static int iwh_m_stat(void *, uint_t, uint64_t *);
372 372 static int iwh_m_start(void *);
373 373 static void iwh_m_stop(void *);
374 374 static int iwh_m_unicst(void *, const uint8_t *);
375 375 static int iwh_m_multicst(void *, boolean_t, const uint8_t *);
376 376 static int iwh_m_promisc(void *, boolean_t);
377 377 static mblk_t *iwh_m_tx(void *, mblk_t *);
378 378 static void iwh_m_ioctl(void *, queue_t *, mblk_t *);
379 379 static int iwh_m_setprop(void *arg, const char *pr_name,
380 380 mac_prop_id_t wldp_pr_num, uint_t wldp_length, const void *wldp_buf);
381 381 static int iwh_m_getprop(void *arg, const char *pr_name,
382 382 mac_prop_id_t wldp_pr_num, uint_t wldp_length,
383 383 void *wldp_buf);
384 384 static void iwh_m_propinfo(void *arg, const char *pr_name,
385 385 mac_prop_id_t wldp_pr_num, mac_prop_info_handle_t mph);
386 386
387 387 /*
388 388 * Supported rates for 802.11b/g modes (in 500Kbps unit).
389 389 */
390 390 static const struct ieee80211_rateset iwh_rateset_11b =
391 391 { 4, { 2, 4, 11, 22 } };
392 392
393 393 static const struct ieee80211_rateset iwh_rateset_11g =
394 394 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
395 395
396 396 /*
397 397 * Default 11n reates supported by this station.
398 398 */
399 399 extern struct ieee80211_htrateset ieee80211_rateset_11n;
400 400
401 401 /*
402 402 * For mfthread only
403 403 */
404 404 extern pri_t minclsyspri;
405 405
406 406 #define DRV_NAME_SP "iwh"
407 407
408 408 /*
409 409 * Module Loading Data & Entry Points
410 410 */
411 411 DDI_DEFINE_STREAM_OPS(iwh_devops, nulldev, nulldev, iwh_attach,
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412 412 iwh_detach, nodev, NULL, D_MP, NULL, iwh_quiesce);
413 413
414 414 static struct modldrv iwh_modldrv = {
415 415 &mod_driverops,
416 416 "Intel(R) ShirleyPeak/EchoPeak driver(N)",
417 417 &iwh_devops
418 418 };
419 419
420 420 static struct modlinkage iwh_modlinkage = {
421 421 MODREV_1,
422 - &iwh_modldrv,
423 - NULL
422 + { &iwh_modldrv, NULL }
424 423 };
425 424
426 425 int
427 426 _init(void)
428 427 {
429 428 int status;
430 429
431 430 status = ddi_soft_state_init(&iwh_soft_state_p,
432 431 sizeof (iwh_sc_t), 1);
433 432 if (status != DDI_SUCCESS) {
434 433 return (status);
435 434 }
436 435
437 436 mac_init_ops(&iwh_devops, DRV_NAME_SP);
438 437 status = mod_install(&iwh_modlinkage);
439 438 if (status != DDI_SUCCESS) {
440 439 mac_fini_ops(&iwh_devops);
441 440 ddi_soft_state_fini(&iwh_soft_state_p);
442 441 }
443 442
444 443 return (status);
445 444 }
446 445
447 446 int
448 447 _fini(void)
449 448 {
450 449 int status;
451 450
452 451 status = mod_remove(&iwh_modlinkage);
453 452 if (DDI_SUCCESS == status) {
454 453 mac_fini_ops(&iwh_devops);
455 454 ddi_soft_state_fini(&iwh_soft_state_p);
456 455 }
457 456
458 457 return (status);
459 458 }
460 459
461 460 int
462 461 _info(struct modinfo *mip)
463 462 {
464 463 return (mod_info(&iwh_modlinkage, mip));
465 464 }
466 465
467 466 /*
468 467 * Mac Call Back entries
469 468 */
470 469 mac_callbacks_t iwh_m_callbacks = {
471 470 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
472 471 iwh_m_stat,
473 472 iwh_m_start,
474 473 iwh_m_stop,
475 474 iwh_m_promisc,
476 475 iwh_m_multicst,
477 476 iwh_m_unicst,
478 477 iwh_m_tx,
479 478 NULL,
480 479 iwh_m_ioctl,
481 480 NULL,
482 481 NULL,
483 482 NULL,
484 483 iwh_m_setprop,
485 484 iwh_m_getprop,
486 485 iwh_m_propinfo
487 486 };
488 487
489 488 #ifdef DEBUG
490 489 void
491 490 iwh_dbg(uint32_t flags, const char *fmt, ...)
492 491 {
493 492 va_list ap;
494 493
495 494 if (flags & iwh_dbg_flags) {
496 495 va_start(ap, fmt);
497 496 vcmn_err(CE_NOTE, fmt, ap);
498 497 va_end(ap);
499 498 }
500 499 }
501 500 #endif /* DEBUG */
502 501
503 502 /*
504 503 * device operations
505 504 */
506 505 int
507 506 iwh_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
508 507 {
509 508 iwh_sc_t *sc;
510 509 ieee80211com_t *ic;
511 510 int instance, i;
512 511 char strbuf[32];
513 512 wifi_data_t wd = { 0 };
514 513 mac_register_t *macp;
515 514 int intr_type;
516 515 int intr_count;
517 516 int intr_actual;
518 517 int err = DDI_FAILURE;
519 518
520 519 switch (cmd) {
521 520 case DDI_ATTACH:
522 521 break;
523 522
524 523 case DDI_RESUME:
525 524 instance = ddi_get_instance(dip);
526 525 sc = ddi_get_soft_state(iwh_soft_state_p,
527 526 instance);
528 527 ASSERT(sc != NULL);
529 528
530 529 if (sc->sc_flags & IWH_F_RUNNING) {
531 530 (void) iwh_init(sc);
532 531 }
533 532
534 533 atomic_and_32(&sc->sc_flags, ~IWH_F_SUSPEND);
535 534
536 535 IWH_DBG((IWH_DEBUG_RESUME, "iwh_attach(): "
537 536 "resume\n"));
538 537 return (DDI_SUCCESS);
539 538
540 539 default:
541 540 goto attach_fail1;
542 541 }
543 542
544 543 instance = ddi_get_instance(dip);
545 544 err = ddi_soft_state_zalloc(iwh_soft_state_p, instance);
546 545 if (err != DDI_SUCCESS) {
547 546 cmn_err(CE_WARN, "iwh_attach(): "
548 547 "failed to allocate soft state\n");
549 548 goto attach_fail1;
550 549 }
551 550
552 551 sc = ddi_get_soft_state(iwh_soft_state_p, instance);
553 552 ASSERT(sc != NULL);
554 553
555 554 sc->sc_dip = dip;
556 555
557 556 /*
558 557 * map configure space
559 558 */
560 559 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0,
561 560 &iwh_reg_accattr, &sc->sc_cfg_handle);
562 561 if (err != DDI_SUCCESS) {
563 562 cmn_err(CE_WARN, "iwh_attach(): "
564 563 "failed to map config spaces regs\n");
565 564 goto attach_fail2;
566 565 }
567 566
568 567 sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle,
569 568 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID));
570 569 if ((sc->sc_dev_id != 0x4232) &&
571 570 (sc->sc_dev_id != 0x4235) &&
572 571 (sc->sc_dev_id != 0x4236) &&
573 572 (sc->sc_dev_id != 0x4237) &&
574 573 (sc->sc_dev_id != 0x423a) &&
575 574 (sc->sc_dev_id != 0x423b) &&
576 575 (sc->sc_dev_id != 0x423c) &&
577 576 (sc->sc_dev_id != 0x423d)) {
578 577 cmn_err(CE_WARN, "iwh_attach(): "
579 578 "Do not support this device\n");
580 579 goto attach_fail3;
581 580 }
582 581
583 582 iwh_init_ht_conf(sc);
584 583 iwh_overwrite_11n_rateset(sc);
585 584
586 585 sc->sc_rev = ddi_get8(sc->sc_cfg_handle,
587 586 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID));
588 587
589 588 /*
590 589 * keep from disturbing C3 state of CPU
591 590 */
592 591 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base +
593 592 PCI_CFG_RETRY_TIMEOUT), 0);
594 593
595 594 /*
596 595 * determine the size of buffer for frame and command to ucode
597 596 */
598 597 sc->sc_clsz = ddi_get16(sc->sc_cfg_handle,
599 598 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
600 599 if (!sc->sc_clsz) {
601 600 sc->sc_clsz = 16;
602 601 }
603 602 sc->sc_clsz = (sc->sc_clsz << 2);
604 603
605 604 sc->sc_dmabuf_sz = roundup(0x2000 + sizeof (struct ieee80211_frame) +
606 605 IEEE80211_MTU + IEEE80211_CRC_LEN +
607 606 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN +
608 607 IEEE80211_WEP_CRCLEN), sc->sc_clsz);
609 608
610 609 /*
611 610 * Map operating registers
612 611 */
613 612 err = ddi_regs_map_setup(dip, 1, &sc->sc_base,
614 613 0, 0, &iwh_reg_accattr, &sc->sc_handle);
615 614 if (err != DDI_SUCCESS) {
616 615 cmn_err(CE_WARN, "iwh_attach(): "
617 616 "failed to map device regs\n");
618 617 goto attach_fail3;
619 618 }
620 619
621 620 /*
622 621 * this is used to differentiate type of hardware
623 622 */
624 623 sc->sc_hw_rev = IWH_READ(sc, CSR_HW_REV);
625 624
626 625 err = ddi_intr_get_supported_types(dip, &intr_type);
627 626 if ((err != DDI_SUCCESS) || (!(intr_type & DDI_INTR_TYPE_FIXED))) {
628 627 cmn_err(CE_WARN, "iwh_attach(): "
629 628 "fixed type interrupt is not supported\n");
630 629 goto attach_fail4;
631 630 }
632 631
633 632 err = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &intr_count);
634 633 if ((err != DDI_SUCCESS) || (intr_count != 1)) {
635 634 cmn_err(CE_WARN, "iwh_attach(): "
636 635 "no fixed interrupts\n");
637 636 goto attach_fail4;
638 637 }
639 638
640 639 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
641 640
642 641 err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0,
643 642 intr_count, &intr_actual, 0);
644 643 if ((err != DDI_SUCCESS) || (intr_actual != 1)) {
645 644 cmn_err(CE_WARN, "iwh_attach(): "
646 645 "ddi_intr_alloc() failed 0x%x\n", err);
647 646 goto attach_fail5;
648 647 }
649 648
650 649 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
651 650 if (err != DDI_SUCCESS) {
652 651 cmn_err(CE_WARN, "iwh_attach(): "
653 652 "ddi_intr_get_pri() failed 0x%x\n", err);
654 653 goto attach_fail6;
655 654 }
656 655
657 656 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER,
658 657 DDI_INTR_PRI(sc->sc_intr_pri));
659 658 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER,
660 659 DDI_INTR_PRI(sc->sc_intr_pri));
661 660 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER,
662 661 DDI_INTR_PRI(sc->sc_intr_pri));
663 662
664 663 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL);
665 664 cv_init(&sc->sc_put_seg_cv, NULL, CV_DRIVER, NULL);
666 665 cv_init(&sc->sc_ucode_cv, NULL, CV_DRIVER, NULL);
667 666
668 667 /*
669 668 * initialize the mfthread
670 669 */
671 670 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL);
672 671 sc->sc_mf_thread = NULL;
673 672 sc->sc_mf_thread_switch = 0;
674 673
675 674 /*
676 675 * Allocate shared buffer for communication between driver and ucode.
677 676 */
678 677 err = iwh_alloc_shared(sc);
679 678 if (err != DDI_SUCCESS) {
680 679 cmn_err(CE_WARN, "iwh_attach(): "
681 680 "failed to allocate shared page\n");
682 681 goto attach_fail7;
683 682 }
684 683
685 684 (void) memset(sc->sc_shared, 0, sizeof (iwh_shared_t));
686 685
687 686 /*
688 687 * Allocate keep warm page.
689 688 */
690 689 err = iwh_alloc_kw(sc);
691 690 if (err != DDI_SUCCESS) {
692 691 cmn_err(CE_WARN, "iwh_attach(): "
693 692 "failed to allocate keep warm page\n");
694 693 goto attach_fail8;
695 694 }
696 695
697 696 err = iwh_reset_hw(sc);
698 697 if (err != IWH_SUCCESS) {
699 698 cmn_err(CE_WARN, "iwh_attach(): "
700 699 "failed to reset hardware\n");
701 700 goto attach_fail9;
702 701 }
703 702
704 703 /*
705 704 * Do some necessary hardware initializations.
706 705 */
707 706 err = iwh_preinit(sc);
708 707 if (err != IWH_SUCCESS) {
709 708 cmn_err(CE_WARN, "iwh_attach(): "
710 709 "failed to initialize hardware\n");
711 710 goto attach_fail9;
712 711 }
713 712
714 713 /*
715 714 * get hardware configurations from eeprom
716 715 */
717 716 err = iwh_eep_load(sc);
718 717 if (err != IWH_SUCCESS) {
719 718 cmn_err(CE_WARN, "iwh_attach(): "
720 719 "failed to load eeprom\n");
721 720 goto attach_fail9;
722 721 }
723 722
724 723 if (IWH_READ_EEP_SHORT(sc, EEP_VERSION) < 0x011a) {
725 724 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_attach(): "
726 725 "unsupported eeprom detected\n"));
727 726 goto attach_fail9;
728 727 }
729 728
730 729 /*
731 730 * get MAC address of this chipset
732 731 */
733 732 iwh_get_mac_from_eep(sc);
734 733
735 734 /*
736 735 * calibration information from EEPROM
737 736 */
738 737 sc->sc_eep_calib = (struct iwh_eep_calibration *)
739 738 iwh_eep_addr_trans(sc, EEP_CALIBRATION);
740 739
741 740 /*
742 741 * initialize TX and RX ring buffers
743 742 */
744 743 err = iwh_ring_init(sc);
745 744 if (err != DDI_SUCCESS) {
746 745 cmn_err(CE_WARN, "iwh_attach(): "
747 746 "failed to allocate and initialize ring\n");
748 747 goto attach_fail9;
749 748 }
750 749
751 750 if ((0x423c == sc->sc_dev_id) || (0x423d == sc->sc_dev_id)) {
752 751 sc->sc_hdr = (iwh_firmware_hdr_t *)iwh_fw_5150_bin;
753 752 } else {
754 753 sc->sc_hdr = (iwh_firmware_hdr_t *)iwh_fw_5000_bin;
755 754 }
756 755
757 756 /*
758 757 * copy ucode to dma buffer
759 758 */
760 759 err = iwh_alloc_fw_dma(sc);
761 760 if (err != DDI_SUCCESS) {
762 761 cmn_err(CE_WARN, "iwh_attach(): "
763 762 "failed to allocate firmware dma\n");
764 763 goto attach_fail10;
765 764 }
766 765
767 766 /*
768 767 * Initialize the wifi part, which will be used by
769 768 * 802.11 module
770 769 */
771 770 ic = &sc->sc_ic;
772 771 ic->ic_phytype = IEEE80211_T_HT;
773 772 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
774 773 ic->ic_state = IEEE80211_S_INIT;
775 774 ic->ic_maxrssi = 100; /* experimental number */
776 775 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT |
777 776 IEEE80211_C_PMGT | IEEE80211_C_SHSLOT;
778 777
779 778 /*
780 779 * Support WPA/WPA2
781 780 */
782 781 ic->ic_caps |= IEEE80211_C_WPA;
783 782
784 783 /*
785 784 * Support QoS/WME
786 785 */
787 786 ic->ic_caps |= IEEE80211_C_WME;
788 787 ic->ic_wme.wme_update = iwh_wme_update;
789 788
790 789 /*
791 790 * Support 802.11n/HT
792 791 */
793 792 if (sc->sc_ht_conf.ht_support) {
794 793 ic->ic_htcaps = IEEE80211_HTC_HT |
795 794 IEEE80211_HTC_AMSDU;
796 795 ic->ic_htcaps |= IEEE80211_HTCAP_MAXAMSDU_7935;
797 796 }
798 797
799 798 /*
800 799 * set supported .11b and .11g rates
801 800 */
802 801 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwh_rateset_11b;
803 802 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwh_rateset_11g;
804 803
805 804 /*
806 805 * set supported .11b and .11g channels (1 through 11)
807 806 */
808 807 for (i = 1; i <= 11; i++) {
809 808 ic->ic_sup_channels[i].ich_freq =
810 809 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
811 810 ic->ic_sup_channels[i].ich_flags =
812 811 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
813 812 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ |
814 813 IEEE80211_CHAN_PASSIVE;
815 814
816 815 if (sc->sc_ht_conf.cap & HT_CAP_SUP_WIDTH) {
817 816 ic->ic_sup_channels[i].ich_flags |=
818 817 IEEE80211_CHAN_HT40;
819 818 } else {
820 819 ic->ic_sup_channels[i].ich_flags |=
821 820 IEEE80211_CHAN_HT20;
822 821 }
823 822 }
824 823
825 824 ic->ic_ibss_chan = &ic->ic_sup_channels[0];
826 825 ic->ic_xmit = iwh_send;
827 826
828 827 /*
829 828 * attach to 802.11 module
830 829 */
831 830 ieee80211_attach(ic);
832 831
833 832 /*
834 833 * different instance has different WPA door
835 834 */
836 835 (void) snprintf(ic->ic_wpadoor, MAX_IEEE80211STR, "%s_%s%d", WPA_DOOR,
837 836 ddi_driver_name(dip),
838 837 ddi_get_instance(dip));
839 838
840 839 /*
841 840 * Overwrite 80211 default configurations.
842 841 */
843 842 iwh_overwrite_ic_default(sc);
844 843
845 844 /*
846 845 * initialize 802.11 module
847 846 */
848 847 ieee80211_media_init(ic);
849 848
850 849 /*
851 850 * initialize default tx key
852 851 */
853 852 ic->ic_def_txkey = 0;
854 853
855 854 err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX,
856 855 iwh_rx_softintr, (caddr_t)sc);
857 856 if (err != DDI_SUCCESS) {
858 857 cmn_err(CE_WARN, "iwh_attach(): "
859 858 "add soft interrupt failed\n");
860 859 goto attach_fail12;
861 860 }
862 861
863 862 err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwh_intr,
864 863 (caddr_t)sc, NULL);
865 864 if (err != DDI_SUCCESS) {
866 865 cmn_err(CE_WARN, "iwh_attach(): "
867 866 "ddi_intr_add_handle() failed\n");
868 867 goto attach_fail13;
869 868 }
870 869
871 870 err = ddi_intr_enable(sc->sc_intr_htable[0]);
872 871 if (err != DDI_SUCCESS) {
873 872 cmn_err(CE_WARN, "iwh_attach(): "
874 873 "ddi_intr_enable() failed\n");
875 874 goto attach_fail14;
876 875 }
877 876
878 877 /*
879 878 * Initialize pointer to device specific functions
880 879 */
881 880 wd.wd_secalloc = WIFI_SEC_NONE;
882 881 wd.wd_opmode = ic->ic_opmode;
883 882 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_macaddr);
884 883
885 884 /*
886 885 * create relation to GLD
887 886 */
888 887 macp = mac_alloc(MAC_VERSION);
889 888 if (NULL == macp) {
890 889 cmn_err(CE_WARN, "iwh_attach(): "
891 890 "failed to do mac_alloc()\n");
892 891 goto attach_fail15;
893 892 }
894 893
895 894 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
896 895 macp->m_driver = sc;
897 896 macp->m_dip = dip;
898 897 macp->m_src_addr = ic->ic_macaddr;
899 898 macp->m_callbacks = &iwh_m_callbacks;
900 899 macp->m_min_sdu = 0;
901 900 macp->m_max_sdu = IEEE80211_MTU;
902 901 macp->m_pdata = &wd;
903 902 macp->m_pdata_size = sizeof (wd);
904 903
905 904 /*
906 905 * Register the macp to mac
907 906 */
908 907 err = mac_register(macp, &ic->ic_mach);
909 908 mac_free(macp);
910 909 if (err != DDI_SUCCESS) {
911 910 cmn_err(CE_WARN, "iwh_attach(): "
912 911 "failed to do mac_register()\n");
913 912 goto attach_fail15;
914 913 }
915 914
916 915 /*
917 916 * Create minor node of type DDI_NT_NET_WIFI
918 917 */
919 918 (void) snprintf(strbuf, sizeof (strbuf), DRV_NAME_SP"%d", instance);
920 919 err = ddi_create_minor_node(dip, strbuf, S_IFCHR,
921 920 instance + 1, DDI_NT_NET_WIFI, 0);
922 921 if (err != DDI_SUCCESS) {
923 922 cmn_err(CE_WARN, "iwh_attach(): "
924 923 "failed to do ddi_create_minor_node()\n");
925 924 }
926 925
927 926 /*
928 927 * Notify link is down now
929 928 */
930 929 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
931 930
932 931 /*
933 932 * create the mf thread to handle the link status,
934 933 * recovery fatal error, etc.
935 934 */
936 935 sc->sc_mf_thread_switch = 1;
937 936 if (NULL == sc->sc_mf_thread) {
938 937 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0,
939 938 iwh_thread, sc, 0, &p0, TS_RUN, minclsyspri);
940 939 }
941 940
942 941 atomic_or_32(&sc->sc_flags, IWH_F_ATTACHED);
943 942
944 943 return (DDI_SUCCESS);
945 944
946 945 attach_fail15:
947 946 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
948 947
949 948 attach_fail14:
950 949 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
951 950
952 951 attach_fail13:
953 952 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
954 953 sc->sc_soft_hdl = NULL;
955 954
956 955 attach_fail12:
957 956 ieee80211_detach(ic);
958 957
959 958 attach_fail11:
960 959 iwh_free_fw_dma(sc);
961 960
962 961 attach_fail10:
963 962 iwh_ring_free(sc);
964 963
965 964 attach_fail9:
966 965 iwh_free_kw(sc);
967 966
968 967 attach_fail8:
969 968 iwh_free_shared(sc);
970 969
971 970 attach_fail7:
972 971 iwh_destroy_locks(sc);
973 972
974 973 attach_fail6:
975 974 (void) ddi_intr_free(sc->sc_intr_htable[0]);
976 975
977 976 attach_fail5:
978 977 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
979 978
980 979 attach_fail4:
981 980 ddi_regs_map_free(&sc->sc_handle);
982 981
983 982 attach_fail3:
984 983 ddi_regs_map_free(&sc->sc_cfg_handle);
985 984
986 985 attach_fail2:
987 986 ddi_soft_state_free(iwh_soft_state_p, instance);
988 987
989 988 attach_fail1:
990 989 return (DDI_FAILURE);
991 990 }
992 991
993 992 int
994 993 iwh_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
995 994 {
996 995 iwh_sc_t *sc;
997 996 ieee80211com_t *ic;
998 997 int err;
999 998
1000 999 sc = ddi_get_soft_state(iwh_soft_state_p, ddi_get_instance(dip));
1001 1000 ASSERT(sc != NULL);
1002 1001 ic = &sc->sc_ic;
1003 1002
1004 1003 switch (cmd) {
1005 1004 case DDI_DETACH:
1006 1005 break;
1007 1006
1008 1007 case DDI_SUSPEND:
1009 1008 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
1010 1009 atomic_and_32(&sc->sc_flags, ~IWH_F_RATE_AUTO_CTL);
1011 1010
1012 1011 atomic_or_32(&sc->sc_flags, IWH_F_SUSPEND);
1013 1012
1014 1013 if (sc->sc_flags & IWH_F_RUNNING) {
1015 1014 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1016 1015 iwh_stop(sc);
1017 1016 }
1018 1017
1019 1018 IWH_DBG((IWH_DEBUG_RESUME, "iwh_detach(): "
1020 1019 "suspend\n"));
1021 1020 return (DDI_SUCCESS);
1022 1021
1023 1022 default:
1024 1023 return (DDI_FAILURE);
1025 1024 }
1026 1025
1027 1026 if (!(sc->sc_flags & IWH_F_ATTACHED)) {
1028 1027 return (DDI_FAILURE);
1029 1028 }
1030 1029
1031 1030 /*
1032 1031 * Destroy the mf_thread
1033 1032 */
1034 1033 sc->sc_mf_thread_switch = 0;
1035 1034
1036 1035 mutex_enter(&sc->sc_mt_lock);
1037 1036 while (sc->sc_mf_thread != NULL) {
1038 1037 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0) {
1039 1038 break;
1040 1039 }
1041 1040 }
1042 1041 mutex_exit(&sc->sc_mt_lock);
1043 1042
1044 1043 err = mac_disable(sc->sc_ic.ic_mach);
1045 1044 if (err != DDI_SUCCESS) {
1046 1045 return (err);
1047 1046 }
1048 1047
1049 1048 /*
1050 1049 * stop chipset
1051 1050 */
1052 1051 iwh_stop(sc);
1053 1052
1054 1053 DELAY(500000);
1055 1054
1056 1055 /*
1057 1056 * release buffer for calibration
1058 1057 */
1059 1058 iwh_release_calib_buffer(sc);
1060 1059
1061 1060 /*
1062 1061 * Unregiste from GLD
1063 1062 */
1064 1063 (void) mac_unregister(sc->sc_ic.ic_mach);
1065 1064
1066 1065 mutex_enter(&sc->sc_glock);
1067 1066 iwh_free_fw_dma(sc);
1068 1067 iwh_ring_free(sc);
1069 1068 iwh_free_kw(sc);
1070 1069 iwh_free_shared(sc);
1071 1070 mutex_exit(&sc->sc_glock);
1072 1071
1073 1072 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
1074 1073 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
1075 1074 (void) ddi_intr_free(sc->sc_intr_htable[0]);
1076 1075 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
1077 1076
1078 1077 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
1079 1078 sc->sc_soft_hdl = NULL;
1080 1079
1081 1080 /*
1082 1081 * detach from 80211 module
1083 1082 */
1084 1083 ieee80211_detach(&sc->sc_ic);
1085 1084
1086 1085 iwh_destroy_locks(sc);
1087 1086
1088 1087 ddi_regs_map_free(&sc->sc_handle);
1089 1088 ddi_regs_map_free(&sc->sc_cfg_handle);
1090 1089 ddi_remove_minor_node(dip, NULL);
1091 1090 ddi_soft_state_free(iwh_soft_state_p, ddi_get_instance(dip));
1092 1091
1093 1092 return (DDI_SUCCESS);
1094 1093 }
1095 1094
1096 1095 /*
1097 1096 * destroy all locks
1098 1097 */
1099 1098 static void
1100 1099 iwh_destroy_locks(iwh_sc_t *sc)
1101 1100 {
1102 1101 cv_destroy(&sc->sc_mt_cv);
1103 1102 cv_destroy(&sc->sc_cmd_cv);
1104 1103 cv_destroy(&sc->sc_put_seg_cv);
1105 1104 cv_destroy(&sc->sc_ucode_cv);
1106 1105 mutex_destroy(&sc->sc_mt_lock);
1107 1106 mutex_destroy(&sc->sc_tx_lock);
1108 1107 mutex_destroy(&sc->sc_glock);
1109 1108 }
1110 1109
1111 1110 /*
1112 1111 * Allocate an area of memory and a DMA handle for accessing it
1113 1112 */
1114 1113 static int
1115 1114 iwh_alloc_dma_mem(iwh_sc_t *sc, size_t memsize,
1116 1115 ddi_dma_attr_t *dma_attr_p, ddi_device_acc_attr_t *acc_attr_p,
1117 1116 uint_t dma_flags, iwh_dma_t *dma_p)
1118 1117 {
1119 1118 caddr_t vaddr;
1120 1119 int err = DDI_FAILURE;
1121 1120
1122 1121 /*
1123 1122 * Allocate handle
1124 1123 */
1125 1124 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p,
1126 1125 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
1127 1126 if (err != DDI_SUCCESS) {
1128 1127 dma_p->dma_hdl = NULL;
1129 1128 return (DDI_FAILURE);
1130 1129 }
1131 1130
1132 1131 /*
1133 1132 * Allocate memory
1134 1133 */
1135 1134 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, acc_attr_p,
1136 1135 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING),
1137 1136 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl);
1138 1137 if (err != DDI_SUCCESS) {
1139 1138 ddi_dma_free_handle(&dma_p->dma_hdl);
1140 1139 dma_p->dma_hdl = NULL;
1141 1140 dma_p->acc_hdl = NULL;
1142 1141 return (DDI_FAILURE);
1143 1142 }
1144 1143
1145 1144 /*
1146 1145 * Bind the two together
1147 1146 */
1148 1147 dma_p->mem_va = vaddr;
1149 1148 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
1150 1149 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL,
1151 1150 &dma_p->cookie, &dma_p->ncookies);
1152 1151 if (err != DDI_DMA_MAPPED) {
1153 1152 ddi_dma_mem_free(&dma_p->acc_hdl);
1154 1153 ddi_dma_free_handle(&dma_p->dma_hdl);
1155 1154 dma_p->acc_hdl = NULL;
1156 1155 dma_p->dma_hdl = NULL;
1157 1156 return (DDI_FAILURE);
1158 1157 }
1159 1158
1160 1159 dma_p->nslots = ~0U;
1161 1160 dma_p->size = ~0U;
1162 1161 dma_p->token = ~0U;
1163 1162 dma_p->offset = 0;
1164 1163 return (DDI_SUCCESS);
1165 1164 }
1166 1165
1167 1166 /*
1168 1167 * Free one allocated area of DMAable memory
1169 1168 */
1170 1169 static void
1171 1170 iwh_free_dma_mem(iwh_dma_t *dma_p)
1172 1171 {
1173 1172 if (dma_p->dma_hdl != NULL) {
1174 1173 if (dma_p->ncookies) {
1175 1174 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
1176 1175 dma_p->ncookies = 0;
1177 1176 }
1178 1177 ddi_dma_free_handle(&dma_p->dma_hdl);
1179 1178 dma_p->dma_hdl = NULL;
1180 1179 }
1181 1180
1182 1181 if (dma_p->acc_hdl != NULL) {
1183 1182 ddi_dma_mem_free(&dma_p->acc_hdl);
1184 1183 dma_p->acc_hdl = NULL;
1185 1184 }
1186 1185 }
1187 1186
1188 1187 /*
1189 1188 * copy ucode into dma buffers
1190 1189 */
1191 1190 static int
1192 1191 iwh_alloc_fw_dma(iwh_sc_t *sc)
1193 1192 {
1194 1193 int err = DDI_FAILURE;
1195 1194 iwh_dma_t *dma_p;
1196 1195 char *t;
1197 1196
1198 1197 /*
1199 1198 * firmware image layout:
1200 1199 * |HDR|<-TEXT->|<-DATA->|<-INIT_TEXT->|<-INIT_DATA->|<-BOOT->|
1201 1200 */
1202 1201
1203 1202 /*
1204 1203 * copy text of runtime ucode
1205 1204 */
1206 1205 t = (char *)(sc->sc_hdr + 1);
1207 1206 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz),
1208 1207 &fw_dma_attr, &iwh_dma_accattr,
1209 1208 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1210 1209 &sc->sc_dma_fw_text);
1211 1210 if (err != DDI_SUCCESS) {
1212 1211 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1213 1212 "failed to allocate text dma memory.\n");
1214 1213 goto fail;
1215 1214 }
1216 1215
1217 1216 dma_p = &sc->sc_dma_fw_text;
1218 1217
1219 1218 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1220 1219 "text[ncookies:%d addr:%lx size:%lx]\n",
1221 1220 dma_p->ncookies, dma_p->cookie.dmac_address,
1222 1221 dma_p->cookie.dmac_size));
1223 1222
1224 1223 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->textsz));
1225 1224
1226 1225 /*
1227 1226 * copy data and bak-data of runtime ucode
1228 1227 */
1229 1228 t += LE_32(sc->sc_hdr->textsz);
1230 1229 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1231 1230 &fw_dma_attr, &iwh_dma_accattr,
1232 1231 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1233 1232 &sc->sc_dma_fw_data);
1234 1233 if (err != DDI_SUCCESS) {
1235 1234 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1236 1235 "failed to allocate data dma memory\n");
1237 1236 goto fail;
1238 1237 }
1239 1238
1240 1239 dma_p = &sc->sc_dma_fw_data;
1241 1240
1242 1241 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1243 1242 "data[ncookies:%d addr:%lx size:%lx]\n",
1244 1243 dma_p->ncookies, dma_p->cookie.dmac_address,
1245 1244 dma_p->cookie.dmac_size));
1246 1245
1247 1246 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->datasz));
1248 1247
1249 1248 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1250 1249 &fw_dma_attr, &iwh_dma_accattr,
1251 1250 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1252 1251 &sc->sc_dma_fw_data_bak);
1253 1252 if (err != DDI_SUCCESS) {
1254 1253 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1255 1254 "failed to allocate data bakup dma memory\n");
1256 1255 goto fail;
1257 1256 }
1258 1257
1259 1258 dma_p = &sc->sc_dma_fw_data_bak;
1260 1259
1261 1260 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1262 1261 "data_bak[ncookies:%d addr:%lx "
1263 1262 "size:%lx]\n",
1264 1263 dma_p->ncookies, dma_p->cookie.dmac_address,
1265 1264 dma_p->cookie.dmac_size));
1266 1265
1267 1266 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->datasz));
1268 1267
1269 1268 /*
1270 1269 * copy text of init ucode
1271 1270 */
1272 1271 t += LE_32(sc->sc_hdr->datasz);
1273 1272 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz),
1274 1273 &fw_dma_attr, &iwh_dma_accattr,
1275 1274 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1276 1275 &sc->sc_dma_fw_init_text);
1277 1276 if (err != DDI_SUCCESS) {
1278 1277 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1279 1278 "failed to allocate init text dma memory\n");
1280 1279 goto fail;
1281 1280 }
1282 1281
1283 1282 dma_p = &sc->sc_dma_fw_init_text;
1284 1283
1285 1284 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1286 1285 "init_text[ncookies:%d addr:%lx "
1287 1286 "size:%lx]\n",
1288 1287 dma_p->ncookies, dma_p->cookie.dmac_address,
1289 1288 dma_p->cookie.dmac_size));
1290 1289
1291 1290 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->init_textsz));
1292 1291
1293 1292 /*
1294 1293 * copy data of init ucode
1295 1294 */
1296 1295 t += LE_32(sc->sc_hdr->init_textsz);
1297 1296 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz),
1298 1297 &fw_dma_attr, &iwh_dma_accattr,
1299 1298 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1300 1299 &sc->sc_dma_fw_init_data);
1301 1300 if (err != DDI_SUCCESS) {
1302 1301 cmn_err(CE_WARN, "iwh_alloc_fw_dma(): "
1303 1302 "failed to allocate init data dma memory\n");
1304 1303 goto fail;
1305 1304 }
1306 1305
1307 1306 dma_p = &sc->sc_dma_fw_init_data;
1308 1307
1309 1308 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_fw_dma(): "
1310 1309 "init_data[ncookies:%d addr:%lx "
1311 1310 "size:%lx]\n",
1312 1311 dma_p->ncookies, dma_p->cookie.dmac_address,
1313 1312 dma_p->cookie.dmac_size));
1314 1313
1315 1314 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->init_datasz));
1316 1315
1317 1316 sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz);
1318 1317
1319 1318 fail:
1320 1319 return (err);
1321 1320 }
1322 1321
1323 1322 static void
1324 1323 iwh_free_fw_dma(iwh_sc_t *sc)
1325 1324 {
1326 1325 iwh_free_dma_mem(&sc->sc_dma_fw_text);
1327 1326 iwh_free_dma_mem(&sc->sc_dma_fw_data);
1328 1327 iwh_free_dma_mem(&sc->sc_dma_fw_data_bak);
1329 1328 iwh_free_dma_mem(&sc->sc_dma_fw_init_text);
1330 1329 iwh_free_dma_mem(&sc->sc_dma_fw_init_data);
1331 1330 }
1332 1331
1333 1332 /*
1334 1333 * Allocate a shared buffer between host and NIC.
1335 1334 */
1336 1335 static int
1337 1336 iwh_alloc_shared(iwh_sc_t *sc)
1338 1337 {
1339 1338 #ifdef DEBUG
1340 1339 iwh_dma_t *dma_p;
1341 1340 #endif
1342 1341 int err = DDI_FAILURE;
1343 1342
1344 1343 /*
1345 1344 * must be aligned on a 4K-page boundary
1346 1345 */
1347 1346 err = iwh_alloc_dma_mem(sc, sizeof (iwh_shared_t),
1348 1347 &sh_dma_attr, &iwh_dma_descattr,
1349 1348 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1350 1349 &sc->sc_dma_sh);
1351 1350 if (err != DDI_SUCCESS) {
1352 1351 goto fail;
1353 1352 }
1354 1353
1355 1354 sc->sc_shared = (iwh_shared_t *)sc->sc_dma_sh.mem_va;
1356 1355
1357 1356 #ifdef DEBUG
1358 1357 dma_p = &sc->sc_dma_sh;
1359 1358 #endif
1360 1359 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_shared(): "
1361 1360 "sh[ncookies:%d addr:%lx size:%lx]\n",
1362 1361 dma_p->ncookies, dma_p->cookie.dmac_address,
1363 1362 dma_p->cookie.dmac_size));
1364 1363
1365 1364 return (err);
1366 1365
1367 1366 fail:
1368 1367 iwh_free_shared(sc);
1369 1368 return (err);
1370 1369 }
1371 1370
1372 1371 static void
1373 1372 iwh_free_shared(iwh_sc_t *sc)
1374 1373 {
1375 1374 iwh_free_dma_mem(&sc->sc_dma_sh);
1376 1375 }
1377 1376
1378 1377 /*
1379 1378 * Allocate a keep warm page.
1380 1379 */
1381 1380 static int
1382 1381 iwh_alloc_kw(iwh_sc_t *sc)
1383 1382 {
1384 1383 #ifdef DEBUG
1385 1384 iwh_dma_t *dma_p;
1386 1385 #endif
1387 1386 int err = DDI_FAILURE;
1388 1387
1389 1388 /*
1390 1389 * must be aligned on a 4K-page boundary
1391 1390 */
1392 1391 err = iwh_alloc_dma_mem(sc, IWH_KW_SIZE,
1393 1392 &kw_dma_attr, &iwh_dma_descattr,
1394 1393 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1395 1394 &sc->sc_dma_kw);
1396 1395 if (err != DDI_SUCCESS) {
1397 1396 goto fail;
1398 1397 }
1399 1398
1400 1399 #ifdef DEBUG
1401 1400 dma_p = &sc->sc_dma_kw;
1402 1401 #endif
1403 1402 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_kw(): "
1404 1403 "kw[ncookies:%d addr:%lx size:%lx]\n",
1405 1404 dma_p->ncookies, dma_p->cookie.dmac_address,
1406 1405 dma_p->cookie.dmac_size));
1407 1406
1408 1407 return (err);
1409 1408
1410 1409 fail:
1411 1410 iwh_free_kw(sc);
1412 1411 return (err);
1413 1412 }
1414 1413
1415 1414 static void
1416 1415 iwh_free_kw(iwh_sc_t *sc)
1417 1416 {
1418 1417 iwh_free_dma_mem(&sc->sc_dma_kw);
1419 1418 }
1420 1419
1421 1420 /*
1422 1421 * initialize RX ring buffers
1423 1422 */
1424 1423 static int
1425 1424 iwh_alloc_rx_ring(iwh_sc_t *sc)
1426 1425 {
1427 1426 iwh_rx_ring_t *ring;
1428 1427 iwh_rx_data_t *data;
1429 1428 #ifdef DEBUG
1430 1429 iwh_dma_t *dma_p;
1431 1430 #endif
1432 1431 int i, err = DDI_FAILURE;
1433 1432
1434 1433 ring = &sc->sc_rxq;
1435 1434 ring->cur = 0;
1436 1435
1437 1436 /*
1438 1437 * allocate RX description ring buffer
1439 1438 */
1440 1439 err = iwh_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t),
1441 1440 &ring_desc_dma_attr, &iwh_dma_descattr,
1442 1441 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1443 1442 &ring->dma_desc);
1444 1443 if (err != DDI_SUCCESS) {
1445 1444 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_rx_ring(): "
1446 1445 "dma alloc rx ring desc "
1447 1446 "failed\n"));
1448 1447 goto fail;
1449 1448 }
1450 1449
1451 1450 ring->desc = (uint32_t *)ring->dma_desc.mem_va;
1452 1451 #ifdef DEBUG
1453 1452 dma_p = &ring->dma_desc;
1454 1453 #endif
1455 1454 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_rx_ring(): "
1456 1455 "rx bd[ncookies:%d addr:%lx size:%lx]\n",
1457 1456 dma_p->ncookies, dma_p->cookie.dmac_address,
1458 1457 dma_p->cookie.dmac_size));
1459 1458
1460 1459 /*
1461 1460 * Allocate Rx frame buffers.
1462 1461 */
1463 1462 for (i = 0; i < RX_QUEUE_SIZE; i++) {
1464 1463 data = &ring->data[i];
1465 1464 err = iwh_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1466 1465 &rx_buffer_dma_attr, &iwh_dma_accattr,
1467 1466 DDI_DMA_READ | DDI_DMA_STREAMING,
1468 1467 &data->dma_data);
1469 1468 if (err != DDI_SUCCESS) {
1470 1469 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_rx_ring(): "
1471 1470 "dma alloc rx ring "
1472 1471 "buf[%d] failed\n", i));
1473 1472 goto fail;
1474 1473 }
1475 1474 /*
1476 1475 * the physical address bit [8-36] are used,
1477 1476 * instead of bit [0-31] in 3945.
1478 1477 */
1479 1478 ring->desc[i] = (uint32_t)
1480 1479 (data->dma_data.cookie.dmac_address >> 8);
1481 1480 }
1482 1481
1483 1482 #ifdef DEBUG
1484 1483 dma_p = &ring->data[0].dma_data;
1485 1484 #endif
1486 1485 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_rx_ring(): "
1487 1486 "rx buffer[0][ncookies:%d addr:%lx "
1488 1487 "size:%lx]\n",
1489 1488 dma_p->ncookies, dma_p->cookie.dmac_address,
1490 1489 dma_p->cookie.dmac_size));
1491 1490
1492 1491 IWH_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
1493 1492
1494 1493 return (err);
1495 1494
1496 1495 fail:
1497 1496 iwh_free_rx_ring(sc);
1498 1497 return (err);
1499 1498 }
1500 1499
1501 1500 /*
1502 1501 * disable RX ring
1503 1502 */
1504 1503 static void
1505 1504 iwh_reset_rx_ring(iwh_sc_t *sc)
1506 1505 {
1507 1506 int n;
1508 1507
1509 1508 iwh_mac_access_enter(sc);
1510 1509 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
1511 1510 for (n = 0; n < 2000; n++) {
1512 1511 if (IWH_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24)) {
1513 1512 break;
1514 1513 }
1515 1514 DELAY(1000);
1516 1515 }
1517 1516 #ifdef DEBUG
1518 1517 if (2000 == n) {
1519 1518 IWH_DBG((IWH_DEBUG_DMA, "iwh_reset_rx_ring(): "
1520 1519 "timeout resetting Rx ring\n"));
1521 1520 }
1522 1521 #endif
1523 1522 iwh_mac_access_exit(sc);
1524 1523
1525 1524 sc->sc_rxq.cur = 0;
1526 1525 }
1527 1526
1528 1527 static void
1529 1528 iwh_free_rx_ring(iwh_sc_t *sc)
1530 1529 {
1531 1530 int i;
1532 1531
1533 1532 for (i = 0; i < RX_QUEUE_SIZE; i++) {
1534 1533 if (sc->sc_rxq.data[i].dma_data.dma_hdl) {
1535 1534 IWH_DMA_SYNC(sc->sc_rxq.data[i].dma_data,
1536 1535 DDI_DMA_SYNC_FORCPU);
1537 1536 }
1538 1537
1539 1538 iwh_free_dma_mem(&sc->sc_rxq.data[i].dma_data);
1540 1539 }
1541 1540
1542 1541 if (sc->sc_rxq.dma_desc.dma_hdl) {
1543 1542 IWH_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV);
1544 1543 }
1545 1544
1546 1545 iwh_free_dma_mem(&sc->sc_rxq.dma_desc);
1547 1546 }
1548 1547
1549 1548 /*
1550 1549 * initialize TX ring buffers
1551 1550 */
1552 1551 static int
1553 1552 iwh_alloc_tx_ring(iwh_sc_t *sc, iwh_tx_ring_t *ring,
1554 1553 int slots, int qid)
1555 1554 {
1556 1555 iwh_tx_data_t *data;
1557 1556 iwh_tx_desc_t *desc_h;
1558 1557 uint32_t paddr_desc_h;
1559 1558 iwh_cmd_t *cmd_h;
1560 1559 uint32_t paddr_cmd_h;
1561 1560 #ifdef DEBUG
1562 1561 iwh_dma_t *dma_p;
1563 1562 #endif
1564 1563 int i, err = DDI_FAILURE;
1565 1564
1566 1565 ring->qid = qid;
1567 1566 ring->count = TFD_QUEUE_SIZE_MAX;
1568 1567 ring->window = slots;
1569 1568 ring->queued = 0;
1570 1569 ring->cur = 0;
1571 1570 ring->desc_cur = 0;
1572 1571
1573 1572 /*
1574 1573 * allocate buffer for TX descriptor ring
1575 1574 */
1576 1575 err = iwh_alloc_dma_mem(sc,
1577 1576 TFD_QUEUE_SIZE_MAX * sizeof (iwh_tx_desc_t),
1578 1577 &ring_desc_dma_attr, &iwh_dma_descattr,
1579 1578 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1580 1579 &ring->dma_desc);
1581 1580 if (err != DDI_SUCCESS) {
1582 1581 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1583 1582 "dma alloc tx ring desc[%d] "
1584 1583 "failed\n", qid));
1585 1584 goto fail;
1586 1585 }
1587 1586
1588 1587 #ifdef DEBUG
1589 1588 dma_p = &ring->dma_desc;
1590 1589 #endif
1591 1590 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1592 1591 "tx bd[ncookies:%d addr:%lx size:%lx]\n",
1593 1592 dma_p->ncookies, dma_p->cookie.dmac_address,
1594 1593 dma_p->cookie.dmac_size));
1595 1594
1596 1595 desc_h = (iwh_tx_desc_t *)ring->dma_desc.mem_va;
1597 1596 paddr_desc_h = ring->dma_desc.cookie.dmac_address;
1598 1597
1599 1598 /*
1600 1599 * allocate buffer for ucode command
1601 1600 */
1602 1601 err = iwh_alloc_dma_mem(sc,
1603 1602 TFD_QUEUE_SIZE_MAX * sizeof (iwh_cmd_t),
1604 1603 &cmd_dma_attr, &iwh_dma_accattr,
1605 1604 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1606 1605 &ring->dma_cmd);
1607 1606 if (err != DDI_SUCCESS) {
1608 1607 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1609 1608 "dma alloc tx ring cmd[%d]"
1610 1609 " failed\n", qid));
1611 1610 goto fail;
1612 1611 }
1613 1612
1614 1613 #ifdef DEBUG
1615 1614 dma_p = &ring->dma_cmd;
1616 1615 #endif
1617 1616 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1618 1617 "tx cmd[ncookies:%d addr:%lx size:%lx]\n",
1619 1618 dma_p->ncookies, dma_p->cookie.dmac_address,
1620 1619 dma_p->cookie.dmac_size));
1621 1620
1622 1621 cmd_h = (iwh_cmd_t *)ring->dma_cmd.mem_va;
1623 1622 paddr_cmd_h = ring->dma_cmd.cookie.dmac_address;
1624 1623
1625 1624 /*
1626 1625 * Allocate Tx frame buffers.
1627 1626 */
1628 1627 ring->data = kmem_zalloc(sizeof (iwh_tx_data_t) * TFD_QUEUE_SIZE_MAX,
1629 1628 KM_NOSLEEP);
1630 1629 if (NULL == ring->data) {
1631 1630 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1632 1631 "could not allocate "
1633 1632 "tx data slots\n"));
1634 1633 goto fail;
1635 1634 }
1636 1635
1637 1636 for (i = 0; i < TFD_QUEUE_SIZE_MAX; i++) {
1638 1637 data = &ring->data[i];
1639 1638 err = iwh_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1640 1639 &tx_buffer_dma_attr, &iwh_dma_accattr,
1641 1640 DDI_DMA_WRITE | DDI_DMA_STREAMING,
1642 1641 &data->dma_data);
1643 1642 if (err != DDI_SUCCESS) {
1644 1643 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1645 1644 "dma alloc tx "
1646 1645 "ring buf[%d] failed\n", i));
1647 1646 goto fail;
1648 1647 }
1649 1648
1650 1649 data->desc = desc_h + i;
1651 1650 data->paddr_desc = paddr_desc_h +
1652 1651 _PTRDIFF(data->desc, desc_h);
1653 1652 data->cmd = cmd_h + i;
1654 1653 data->paddr_cmd = paddr_cmd_h +
1655 1654 _PTRDIFF(data->cmd, cmd_h);
1656 1655 }
1657 1656 #ifdef DEBUG
1658 1657 dma_p = &ring->data[0].dma_data;
1659 1658 #endif
1660 1659 IWH_DBG((IWH_DEBUG_DMA, "iwh_alloc_tx_ring(): "
1661 1660 "tx buffer[0][ncookies:%d addr:%lx "
1662 1661 "size:%lx]\n",
1663 1662 dma_p->ncookies, dma_p->cookie.dmac_address,
1664 1663 dma_p->cookie.dmac_size));
1665 1664
1666 1665 return (err);
1667 1666
1668 1667 fail:
1669 1668 iwh_free_tx_ring(ring);
1670 1669
1671 1670 return (err);
1672 1671 }
1673 1672
1674 1673 /*
1675 1674 * disable TX ring
1676 1675 */
1677 1676 static void
1678 1677 iwh_reset_tx_ring(iwh_sc_t *sc, iwh_tx_ring_t *ring)
1679 1678 {
1680 1679 iwh_tx_data_t *data;
1681 1680 int i, n;
1682 1681
1683 1682 iwh_mac_access_enter(sc);
1684 1683
1685 1684 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);
1686 1685 for (n = 0; n < 200; n++) {
1687 1686 if (IWH_READ(sc, IWH_FH_TSSR_TX_STATUS_REG) &
1688 1687 IWH_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ring->qid)) {
1689 1688 break;
1690 1689 }
1691 1690 DELAY(10);
1692 1691 }
1693 1692
1694 1693 #ifdef DEBUG
1695 1694 if (200 == n) {
1696 1695 IWH_DBG((IWH_DEBUG_DMA, "iwh_reset_tx_ring(): "
1697 1696 "timeout reset tx ring %d\n",
1698 1697 ring->qid));
1699 1698 }
1700 1699 #endif
1701 1700
1702 1701 iwh_mac_access_exit(sc);
1703 1702
1704 1703 /*
1705 1704 * by pass, if it's quiesce
1706 1705 */
1707 1706 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
1708 1707 for (i = 0; i < ring->count; i++) {
1709 1708 data = &ring->data[i];
1710 1709 IWH_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV);
1711 1710 }
1712 1711 }
1713 1712
1714 1713 ring->queued = 0;
1715 1714 ring->cur = 0;
1716 1715 ring->desc_cur = 0;
1717 1716 }
1718 1717
1719 1718 static void
1720 1719 iwh_free_tx_ring(iwh_tx_ring_t *ring)
1721 1720 {
1722 1721 int i;
1723 1722
1724 1723 if (ring->dma_desc.dma_hdl != NULL) {
1725 1724 IWH_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
1726 1725 }
1727 1726 iwh_free_dma_mem(&ring->dma_desc);
1728 1727
1729 1728 if (ring->dma_cmd.dma_hdl != NULL) {
1730 1729 IWH_DMA_SYNC(ring->dma_cmd, DDI_DMA_SYNC_FORDEV);
1731 1730 }
1732 1731 iwh_free_dma_mem(&ring->dma_cmd);
1733 1732
1734 1733 if (ring->data != NULL) {
1735 1734 for (i = 0; i < ring->count; i++) {
1736 1735 if (ring->data[i].dma_data.dma_hdl) {
1737 1736 IWH_DMA_SYNC(ring->data[i].dma_data,
1738 1737 DDI_DMA_SYNC_FORDEV);
1739 1738 }
1740 1739 iwh_free_dma_mem(&ring->data[i].dma_data);
1741 1740 }
1742 1741 kmem_free(ring->data, ring->count * sizeof (iwh_tx_data_t));
1743 1742 }
1744 1743 }
1745 1744
1746 1745 /*
1747 1746 * initialize TX and RX ring
1748 1747 */
1749 1748 static int
1750 1749 iwh_ring_init(iwh_sc_t *sc)
1751 1750 {
1752 1751 int i, err = DDI_FAILURE;
1753 1752
1754 1753 for (i = 0; i < IWH_NUM_QUEUES; i++) {
1755 1754 if (IWH_CMD_QUEUE_NUM == i) {
1756 1755 continue;
1757 1756 }
1758 1757
1759 1758 err = iwh_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS,
1760 1759 i);
1761 1760 if (err != DDI_SUCCESS) {
1762 1761 goto fail;
1763 1762 }
1764 1763 }
1765 1764
1766 1765 /*
1767 1766 * initialize command queue
1768 1767 */
1769 1768 err = iwh_alloc_tx_ring(sc, &sc->sc_txq[IWH_CMD_QUEUE_NUM],
1770 1769 TFD_CMD_SLOTS, IWH_CMD_QUEUE_NUM);
1771 1770 if (err != DDI_SUCCESS) {
1772 1771 goto fail;
1773 1772 }
1774 1773
1775 1774 err = iwh_alloc_rx_ring(sc);
1776 1775 if (err != DDI_SUCCESS) {
1777 1776 goto fail;
1778 1777 }
1779 1778
1780 1779 fail:
1781 1780 return (err);
1782 1781 }
1783 1782
1784 1783 static void
1785 1784 iwh_ring_free(iwh_sc_t *sc)
1786 1785 {
1787 1786 int i = IWH_NUM_QUEUES;
1788 1787
1789 1788 iwh_free_rx_ring(sc);
1790 1789 while (--i >= 0) {
1791 1790 iwh_free_tx_ring(&sc->sc_txq[i]);
1792 1791 }
1793 1792 }
1794 1793
1795 1794 /* ARGSUSED */
1796 1795 static ieee80211_node_t *
1797 1796 iwh_node_alloc(ieee80211com_t *ic)
1798 1797 {
1799 1798 iwh_amrr_t *amrr;
1800 1799
1801 1800 amrr = kmem_zalloc(sizeof (iwh_amrr_t), KM_SLEEP);
1802 1801 if (NULL == amrr) {
1803 1802 cmn_err(CE_WARN, "iwh_node_alloc(): "
1804 1803 "failed to allocate memory for amrr structure\n");
1805 1804 return (NULL);
1806 1805 }
1807 1806
1808 1807 iwh_amrr_init(amrr);
1809 1808
1810 1809 return (&amrr->in);
1811 1810 }
1812 1811
1813 1812 static void
1814 1813 iwh_node_free(ieee80211_node_t *in)
1815 1814 {
1816 1815 ieee80211com_t *ic;
1817 1816
1818 1817 if ((NULL == in) ||
1819 1818 (NULL == in->in_ic)) {
1820 1819 cmn_err(CE_WARN, "iwh_node_free() "
1821 1820 "Got a NULL point from Net80211 module\n");
1822 1821 return;
1823 1822 }
1824 1823 ic = in->in_ic;
1825 1824
1826 1825 if (ic->ic_node_cleanup != NULL) {
1827 1826 ic->ic_node_cleanup(in);
1828 1827 }
1829 1828
1830 1829 if (in->in_wpa_ie != NULL) {
1831 1830 ieee80211_free(in->in_wpa_ie);
1832 1831 }
1833 1832
1834 1833 if (in->in_wme_ie != NULL) {
1835 1834 ieee80211_free(in->in_wme_ie);
1836 1835 }
1837 1836
1838 1837 if (in->in_htcap_ie != NULL) {
1839 1838 ieee80211_free(in->in_htcap_ie);
1840 1839 }
1841 1840
1842 1841 kmem_free(in, sizeof (iwh_amrr_t));
1843 1842 }
1844 1843
1845 1844 /*
1846 1845 * change station's state. this function will be invoked by 80211 module
1847 1846 * when need to change staton's state.
1848 1847 */
1849 1848 static int
1850 1849 iwh_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg)
1851 1850 {
1852 1851 iwh_sc_t *sc;
1853 1852 ieee80211_node_t *in;
1854 1853 enum ieee80211_state ostate;
1855 1854 iwh_add_sta_t node;
1856 1855 iwh_amrr_t *amrr;
1857 1856 uint8_t r;
1858 1857 int i, err = IWH_FAIL;
1859 1858
1860 1859 if (NULL == ic) {
1861 1860 return (err);
1862 1861 }
1863 1862 sc = (iwh_sc_t *)ic;
1864 1863 in = ic->ic_bss;
1865 1864 ostate = ic->ic_state;
1866 1865
1867 1866 mutex_enter(&sc->sc_glock);
1868 1867
1869 1868 switch (nstate) {
1870 1869 case IEEE80211_S_SCAN:
1871 1870 switch (ostate) {
1872 1871 case IEEE80211_S_INIT:
1873 1872 atomic_or_32(&sc->sc_flags, IWH_F_SCANNING);
1874 1873 iwh_set_led(sc, 2, 10, 2);
1875 1874
1876 1875 /*
1877 1876 * clear association to receive beacons from
1878 1877 * all BSS'es
1879 1878 */
1880 1879 sc->sc_config.assoc_id = 0;
1881 1880 sc->sc_config.filter_flags &=
1882 1881 ~LE_32(RXON_FILTER_ASSOC_MSK);
1883 1882
1884 1883 IWH_DBG((IWH_DEBUG_80211, "iwh_newstate(): "
1885 1884 "config chan %d "
1886 1885 "flags %x filter_flags %x\n",
1887 1886 LE_16(sc->sc_config.chan),
1888 1887 LE_32(sc->sc_config.flags),
1889 1888 LE_32(sc->sc_config.filter_flags)));
1890 1889
1891 1890 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
1892 1891 sizeof (iwh_rxon_cmd_t), 1);
1893 1892 if (err != IWH_SUCCESS) {
1894 1893 cmn_err(CE_WARN, "iwh_newstate(): "
1895 1894 "could not clear association\n");
1896 1895 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1897 1896 mutex_exit(&sc->sc_glock);
1898 1897 return (err);
1899 1898 }
1900 1899
1901 1900 /*
1902 1901 * add broadcast node to send probe request
1903 1902 */
1904 1903 (void) memset(&node, 0, sizeof (node));
1905 1904 (void) memset(&node.sta.addr, 0xff, IEEE80211_ADDR_LEN);
1906 1905 node.sta.sta_id = IWH_BROADCAST_ID;
1907 1906 err = iwh_cmd(sc, REPLY_ADD_STA, &node,
1908 1907 sizeof (node), 1);
1909 1908 if (err != IWH_SUCCESS) {
1910 1909 cmn_err(CE_WARN, "iwh_newstate(): "
1911 1910 "could not add broadcast node\n");
1912 1911 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1913 1912 mutex_exit(&sc->sc_glock);
1914 1913 return (err);
1915 1914 }
1916 1915 break;
1917 1916 case IEEE80211_S_SCAN:
1918 1917 mutex_exit(&sc->sc_glock);
1919 1918 /* step to next channel before actual FW scan */
1920 1919 err = sc->sc_newstate(ic, nstate, arg);
1921 1920 mutex_enter(&sc->sc_glock);
1922 1921 if ((err != 0) || ((err = iwh_scan(sc)) != 0)) {
1923 1922 cmn_err(CE_WARN, "iwh_newstate(): "
1924 1923 "could not initiate scan\n");
1925 1924 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1926 1925 ieee80211_cancel_scan(ic);
1927 1926 }
1928 1927 mutex_exit(&sc->sc_glock);
1929 1928 return (err);
1930 1929 default:
1931 1930 break;
1932 1931 }
1933 1932 sc->sc_clk = 0;
1934 1933 break;
1935 1934
1936 1935 case IEEE80211_S_AUTH:
1937 1936 if (ostate == IEEE80211_S_SCAN) {
1938 1937 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1939 1938 }
1940 1939
1941 1940 /*
1942 1941 * reset state to handle reassociations correctly
1943 1942 */
1944 1943 sc->sc_config.assoc_id = 0;
1945 1944 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
1946 1945
1947 1946 /*
1948 1947 * before sending authentication and association request frame,
1949 1948 * we need do something in the hardware, such as setting the
1950 1949 * channel same to the target AP...
1951 1950 */
1952 1951 if ((err = iwh_hw_set_before_auth(sc)) != 0) {
1953 1952 IWH_DBG((IWH_DEBUG_80211, "iwh_newstate(): "
1954 1953 "could not send authentication request\n"));
1955 1954 mutex_exit(&sc->sc_glock);
1956 1955 return (err);
1957 1956 }
1958 1957 break;
1959 1958
1960 1959 case IEEE80211_S_RUN:
1961 1960 if (ostate == IEEE80211_S_SCAN) {
1962 1961 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1963 1962 }
1964 1963
1965 1964 if (IEEE80211_M_MONITOR == ic->ic_opmode) {
1966 1965 /*
1967 1966 * let LED blink when monitoring
1968 1967 */
1969 1968 iwh_set_led(sc, 2, 10, 10);
1970 1969 break;
1971 1970 }
1972 1971
1973 1972 IWH_DBG((IWH_DEBUG_80211, "iwh_newstate(): "
1974 1973 "associated.\n"));
1975 1974
1976 1975 err = iwh_run_state_config(sc);
1977 1976 if (err != IWH_SUCCESS) {
1978 1977 cmn_err(CE_WARN, "iwh_newstate(): "
1979 1978 "failed to set up association\n");
1980 1979 mutex_exit(&sc->sc_glock);
1981 1980 return (err);
1982 1981 }
1983 1982
1984 1983 /*
1985 1984 * start automatic rate control
1986 1985 */
1987 1986 if ((in->in_flags & IEEE80211_NODE_HT) &&
1988 1987 (sc->sc_ht_conf.ht_support) &&
1989 1988 (in->in_htrates.rs_nrates > 0) &&
1990 1989 (in->in_htrates.rs_nrates <= IEEE80211_HTRATE_MAXSIZE)) {
1991 1990 amrr = (iwh_amrr_t *)in;
1992 1991
1993 1992 for (i = in->in_htrates.rs_nrates - 1; i > 0; i--) {
1994 1993
1995 1994 r = in->in_htrates.rs_rates[i] &
1996 1995 IEEE80211_RATE_VAL;
1997 1996 if ((r != 0) && (r <= 0xd) &&
1998 1997 (sc->sc_ht_conf.tx_support_mcs[r/8] &
1999 1998 (1 << (r%8)))) {
2000 1999 amrr->ht_mcs_idx = r;
2001 2000 atomic_or_32(&sc->sc_flags,
2002 2001 IWH_F_RATE_AUTO_CTL);
2003 2002 break;
2004 2003 }
2005 2004 }
2006 2005 } else {
2007 2006 if (IEEE80211_FIXED_RATE_NONE == ic->ic_fixed_rate) {
2008 2007 atomic_or_32(&sc->sc_flags,
2009 2008 IWH_F_RATE_AUTO_CTL);
2010 2009
2011 2010 /*
2012 2011 * set rate to some reasonable initial value
2013 2012 */
2014 2013 i = in->in_rates.ir_nrates - 1;
2015 2014 while (i > 0 && IEEE80211_RATE(i) > 72) {
2016 2015 i--;
2017 2016 }
2018 2017 in->in_txrate = i;
2019 2018
2020 2019 } else {
2021 2020 atomic_and_32(&sc->sc_flags,
2022 2021 ~IWH_F_RATE_AUTO_CTL);
2023 2022 }
2024 2023 }
2025 2024
2026 2025 /*
2027 2026 * set LED on after associated
2028 2027 */
2029 2028 iwh_set_led(sc, 2, 0, 1);
2030 2029 break;
2031 2030
2032 2031 case IEEE80211_S_INIT:
2033 2032 if (ostate == IEEE80211_S_SCAN) {
2034 2033 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
2035 2034 }
2036 2035 /*
2037 2036 * set LED off after init
2038 2037 */
2039 2038 iwh_set_led(sc, 2, 1, 0);
2040 2039 break;
2041 2040
2042 2041 case IEEE80211_S_ASSOC:
2043 2042 if (ostate == IEEE80211_S_SCAN) {
2044 2043 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
2045 2044 }
2046 2045 break;
2047 2046 }
2048 2047
2049 2048 mutex_exit(&sc->sc_glock);
2050 2049
2051 2050 return (sc->sc_newstate(ic, nstate, arg));
2052 2051 }
2053 2052
2054 2053 /*
2055 2054 * exclusive access to mac begin.
2056 2055 */
2057 2056 static void
2058 2057 iwh_mac_access_enter(iwh_sc_t *sc)
2059 2058 {
2060 2059 uint32_t tmp;
2061 2060 int n;
2062 2061
2063 2062 tmp = IWH_READ(sc, CSR_GP_CNTRL);
2064 2063 IWH_WRITE(sc, CSR_GP_CNTRL,
2065 2064 tmp | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2066 2065
2067 2066 /*
2068 2067 * wait until we succeed
2069 2068 */
2070 2069 for (n = 0; n < 1000; n++) {
2071 2070 if ((IWH_READ(sc, CSR_GP_CNTRL) &
2072 2071 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2073 2072 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP)) ==
2074 2073 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN) {
2075 2074 break;
2076 2075 }
2077 2076 DELAY(10);
2078 2077 }
2079 2078
2080 2079 #ifdef DEBUG
2081 2080 if (1000 == n) {
2082 2081 IWH_DBG((IWH_DEBUG_PIO, "iwh_mac_access_enter(): "
2083 2082 "could not lock memory\n"));
2084 2083 }
2085 2084 #endif
2086 2085 }
2087 2086
2088 2087 /*
2089 2088 * exclusive access to mac end.
2090 2089 */
2091 2090 static void
2092 2091 iwh_mac_access_exit(iwh_sc_t *sc)
2093 2092 {
2094 2093 uint32_t tmp = IWH_READ(sc, CSR_GP_CNTRL);
2095 2094 IWH_WRITE(sc, CSR_GP_CNTRL,
2096 2095 tmp & ~CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2097 2096 }
2098 2097
2099 2098 /*
2100 2099 * this function defined here for future use.
2101 2100 * static uint32_t
2102 2101 * iwh_mem_read(iwh_sc_t *sc, uint32_t addr)
2103 2102 * {
2104 2103 * IWH_WRITE(sc, HBUS_TARG_MEM_RADDR, addr);
2105 2104 * return (IWH_READ(sc, HBUS_TARG_MEM_RDAT));
2106 2105 * }
2107 2106 */
2108 2107
2109 2108 /*
2110 2109 * write mac memory
2111 2110 */
2112 2111 static void
2113 2112 iwh_mem_write(iwh_sc_t *sc, uint32_t addr, uint32_t data)
2114 2113 {
2115 2114 IWH_WRITE(sc, HBUS_TARG_MEM_WADDR, addr);
2116 2115 IWH_WRITE(sc, HBUS_TARG_MEM_WDAT, data);
2117 2116 }
2118 2117
2119 2118 /*
2120 2119 * read mac register
2121 2120 */
2122 2121 static uint32_t
2123 2122 iwh_reg_read(iwh_sc_t *sc, uint32_t addr)
2124 2123 {
2125 2124 IWH_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24));
2126 2125 return (IWH_READ(sc, HBUS_TARG_PRPH_RDAT));
2127 2126 }
2128 2127
2129 2128 /*
2130 2129 * write mac register
2131 2130 */
2132 2131 static void
2133 2132 iwh_reg_write(iwh_sc_t *sc, uint32_t addr, uint32_t data)
2134 2133 {
2135 2134 IWH_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24));
2136 2135 IWH_WRITE(sc, HBUS_TARG_PRPH_WDAT, data);
2137 2136 }
2138 2137
2139 2138
2140 2139 /*
2141 2140 * steps of loading ucode:
2142 2141 * load init ucode=>init alive=>calibrate=>
2143 2142 * receive calibration result=>reinitialize NIC=>
2144 2143 * load runtime ucode=>runtime alive=>
2145 2144 * send calibration result=>running.
2146 2145 */
2147 2146 static int
2148 2147 iwh_load_init_firmware(iwh_sc_t *sc)
2149 2148 {
2150 2149 int err = IWH_FAIL;
2151 2150 clock_t clk;
2152 2151
2153 2152 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2154 2153
2155 2154 /*
2156 2155 * load init_text section of uCode to hardware
2157 2156 */
2158 2157 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address,
2159 2158 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size);
2160 2159 if (err != IWH_SUCCESS) {
2161 2160 cmn_err(CE_WARN, "iwh_load_init_firmware(): "
2162 2161 "failed to write init uCode.\n");
2163 2162 return (err);
2164 2163 }
2165 2164
2166 2165 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2167 2166
2168 2167 /*
2169 2168 * wait loading init_text until completed or timeout
2170 2169 */
2171 2170 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2172 2171 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2173 2172 break;
2174 2173 }
2175 2174 }
2176 2175
2177 2176 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2178 2177 cmn_err(CE_WARN, "iwh_load_init_firmware(): "
2179 2178 "timeout waiting for init uCode load.\n");
2180 2179 return (IWH_FAIL);
2181 2180 }
2182 2181
2183 2182 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2184 2183
2185 2184 /*
2186 2185 * load init_data section of uCode to hardware
2187 2186 */
2188 2187 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address,
2189 2188 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size);
2190 2189 if (err != IWH_SUCCESS) {
2191 2190 cmn_err(CE_WARN, "iwh_load_init_firmware(): "
2192 2191 "failed to write init_data uCode.\n");
2193 2192 return (err);
2194 2193 }
2195 2194
2196 2195 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2197 2196
2198 2197 /*
2199 2198 * wait loading init_data until completed or timeout
2200 2199 */
2201 2200 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2202 2201 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2203 2202 break;
2204 2203 }
2205 2204 }
2206 2205
2207 2206 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2208 2207 cmn_err(CE_WARN, "iwh_load_init_firmware(): "
2209 2208 "timeout waiting for init_data uCode load.\n");
2210 2209 return (IWH_FAIL);
2211 2210 }
2212 2211
2213 2212 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2214 2213
2215 2214 return (err);
2216 2215 }
2217 2216
2218 2217 static int
2219 2218 iwh_load_run_firmware(iwh_sc_t *sc)
2220 2219 {
2221 2220 int err = IWH_FAIL;
2222 2221 clock_t clk;
2223 2222
2224 2223 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2225 2224
2226 2225 /*
2227 2226 * load init_text section of uCode to hardware
2228 2227 */
2229 2228 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address,
2230 2229 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size);
2231 2230 if (err != IWH_SUCCESS) {
2232 2231 cmn_err(CE_WARN, "iwh_load_run_firmware(): "
2233 2232 "failed to write run uCode.\n");
2234 2233 return (err);
2235 2234 }
2236 2235
2237 2236 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2238 2237
2239 2238 /*
2240 2239 * wait loading run_text until completed or timeout
2241 2240 */
2242 2241 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2243 2242 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2244 2243 break;
2245 2244 }
2246 2245 }
2247 2246
2248 2247 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2249 2248 cmn_err(CE_WARN, "iwh_load_run_firmware(): "
2250 2249 "timeout waiting for run uCode load.\n");
2251 2250 return (IWH_FAIL);
2252 2251 }
2253 2252
2254 2253 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2255 2254
2256 2255 /*
2257 2256 * load run_data section of uCode to hardware
2258 2257 */
2259 2258 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address,
2260 2259 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size);
2261 2260 if (err != IWH_SUCCESS) {
2262 2261 cmn_err(CE_WARN, "iwh_load_run_firmware(): "
2263 2262 "failed to write run_data uCode.\n");
2264 2263 return (err);
2265 2264 }
2266 2265
2267 2266 clk = ddi_get_lbolt() + drv_usectohz(1000000);
2268 2267
2269 2268 /*
2270 2269 * wait loading run_data until completed or timeout
2271 2270 */
2272 2271 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2273 2272 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2274 2273 break;
2275 2274 }
2276 2275 }
2277 2276
2278 2277 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2279 2278 cmn_err(CE_WARN, "iwh_load_run_firmware(): "
2280 2279 "timeout waiting for run_data uCode load.\n");
2281 2280 return (IWH_FAIL);
2282 2281 }
2283 2282
2284 2283 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2285 2284
2286 2285 return (err);
2287 2286 }
2288 2287
2289 2288 /*
2290 2289 * this function will be invoked to receive phy information
2291 2290 * when a frame is received.
2292 2291 */
2293 2292 static void
2294 2293 iwh_rx_phy_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2295 2294 {
2296 2295
2297 2296 sc->sc_rx_phy_res.flag = 1;
2298 2297
2299 2298 bcopy((uint8_t *)(desc + 1), sc->sc_rx_phy_res.buf,
2300 2299 sizeof (iwh_rx_phy_res_t));
2301 2300 }
2302 2301
2303 2302 /*
2304 2303 * this function will be invoked to receive body of frame when
2305 2304 * a frame is received.
2306 2305 */
2307 2306 static void
2308 2307 iwh_rx_mpdu_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2309 2308 {
2310 2309 ieee80211com_t *ic = &sc->sc_ic;
2311 2310 #ifdef DEBUG
2312 2311 iwh_rx_ring_t *ring = &sc->sc_rxq;
2313 2312 #endif
2314 2313 struct ieee80211_frame *wh;
2315 2314 struct iwh_rx_non_cfg_phy *phyinfo;
2316 2315 struct iwh_rx_mpdu_body_size *mpdu_size;
2317 2316 mblk_t *mp;
2318 2317 int16_t t;
2319 2318 uint16_t len, rssi, agc;
2320 2319 uint32_t temp, crc, *tail;
2321 2320 uint32_t arssi, brssi, crssi, mrssi;
2322 2321 iwh_rx_phy_res_t *stat;
2323 2322 ieee80211_node_t *in;
2324 2323
2325 2324 /*
2326 2325 * assuming not 11n here. cope with 11n in phase-II
2327 2326 */
2328 2327 mpdu_size = (struct iwh_rx_mpdu_body_size *)(desc + 1);
2329 2328 stat = (iwh_rx_phy_res_t *)sc->sc_rx_phy_res.buf;
2330 2329 if (stat->cfg_phy_cnt > 20) {
2331 2330 return;
2332 2331 }
2333 2332
2334 2333 phyinfo = (struct iwh_rx_non_cfg_phy *)stat->non_cfg_phy;
2335 2334 temp = LE_32(phyinfo->non_cfg_phy[IWH_RX_RES_AGC_IDX]);
2336 2335 agc = (temp & IWH_OFDM_AGC_MSK) >> IWH_OFDM_AGC_BIT_POS;
2337 2336
2338 2337 temp = LE_32(phyinfo->non_cfg_phy[IWH_RX_RES_RSSI_AB_IDX]);
2339 2338 arssi = (temp & IWH_OFDM_RSSI_A_MSK) >> IWH_OFDM_RSSI_A_BIT_POS;
2340 2339 brssi = (temp & IWH_OFDM_RSSI_B_MSK) >> IWH_OFDM_RSSI_B_BIT_POS;
2341 2340
2342 2341 temp = LE_32(phyinfo->non_cfg_phy[IWH_RX_RES_RSSI_C_IDX]);
2343 2342 crssi = (temp & IWH_OFDM_RSSI_C_MSK) >> IWH_OFDM_RSSI_C_BIT_POS;
2344 2343
2345 2344 mrssi = MAX(arssi, brssi);
2346 2345 mrssi = MAX(mrssi, crssi);
2347 2346
2348 2347 t = mrssi - agc - IWH_RSSI_OFFSET;
2349 2348 /*
2350 2349 * convert dBm to percentage
2351 2350 */
2352 2351 rssi = (100 * 75 * 75 - (-20 - t) * (15 * 75 + 62 * (-20 - t)))
2353 2352 / (75 * 75);
2354 2353 if (rssi > 100) {
2355 2354 rssi = 100;
2356 2355 }
2357 2356 if (rssi < 1) {
2358 2357 rssi = 1;
2359 2358 }
2360 2359
2361 2360 /*
2362 2361 * size of frame, not include FCS
2363 2362 */
2364 2363 len = LE_16(mpdu_size->byte_count);
2365 2364 tail = (uint32_t *)((uint8_t *)(desc + 1) +
2366 2365 sizeof (struct iwh_rx_mpdu_body_size) + len);
2367 2366 bcopy(tail, &crc, 4);
2368 2367
2369 2368 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2370 2369 "rx intr: idx=%d phy_len=%x len=%d "
2371 2370 "rate=%x chan=%d tstamp=%x non_cfg_phy_count=%x "
2372 2371 "cfg_phy_count=%x tail=%x", ring->cur, sizeof (*stat),
2373 2372 len, stat->rate.r.s.rate, stat->channel,
2374 2373 LE_32(stat->timestampl), stat->non_cfg_phy_cnt,
2375 2374 stat->cfg_phy_cnt, LE_32(crc)));
2376 2375
2377 2376 if ((len < 16) || (len > sc->sc_dmabuf_sz)) {
2378 2377 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2379 2378 "rx frame oversize\n"));
2380 2379 return;
2381 2380 }
2382 2381
2383 2382 /*
2384 2383 * discard Rx frames with bad CRC
2385 2384 */
2386 2385 if ((LE_32(crc) &
2387 2386 (RX_RES_STATUS_NO_CRC32_ERROR | RX_RES_STATUS_NO_RXE_OVERFLOW)) !=
2388 2387 (RX_RES_STATUS_NO_CRC32_ERROR | RX_RES_STATUS_NO_RXE_OVERFLOW)) {
2389 2388 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2390 2389 "rx crc error tail: %x\n",
2391 2390 LE_32(crc)));
2392 2391 sc->sc_rx_err++;
2393 2392 return;
2394 2393 }
2395 2394
2396 2395 wh = (struct ieee80211_frame *)
2397 2396 ((uint8_t *)(desc + 1)+ sizeof (struct iwh_rx_mpdu_body_size));
2398 2397
2399 2398 if (IEEE80211_FC0_SUBTYPE_ASSOC_RESP == *(uint8_t *)wh) {
2400 2399 sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2);
2401 2400 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2402 2401 "rx : association id = %x\n",
2403 2402 sc->sc_assoc_id));
2404 2403 }
2405 2404
2406 2405 #ifdef DEBUG
2407 2406 if (iwh_dbg_flags & IWH_DEBUG_RX) {
2408 2407 ieee80211_dump_pkt((uint8_t *)wh, len, 0, 0);
2409 2408 }
2410 2409 #endif
2411 2410
2412 2411 in = ieee80211_find_rxnode(ic, wh);
2413 2412 mp = allocb(len, BPRI_MED);
2414 2413 if (mp) {
2415 2414 bcopy(wh, mp->b_wptr, len);
2416 2415 mp->b_wptr += len;
2417 2416
2418 2417 /*
2419 2418 * send the frame to the 802.11 layer
2420 2419 */
2421 2420 (void) ieee80211_input(ic, mp, in, rssi, 0);
2422 2421 } else {
2423 2422 sc->sc_rx_nobuf++;
2424 2423 IWH_DBG((IWH_DEBUG_RX, "iwh_rx_mpdu_intr(): "
2425 2424 "alloc rx buf failed\n"));
2426 2425 }
2427 2426
2428 2427 /*
2429 2428 * release node reference
2430 2429 */
2431 2430 ieee80211_free_node(in);
2432 2431 }
2433 2432
2434 2433 /*
2435 2434 * process correlative affairs after a frame is sent.
2436 2435 */
2437 2436 static void
2438 2437 iwh_tx_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2439 2438 {
2440 2439 ieee80211com_t *ic = &sc->sc_ic;
2441 2440 iwh_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3];
2442 2441 iwh_tx_stat_t *stat = (iwh_tx_stat_t *)(desc + 1);
2443 2442 iwh_amrr_t *amrr;
2444 2443
2445 2444 if (NULL == ic->ic_bss) {
2446 2445 return;
2447 2446 }
2448 2447
2449 2448 amrr = (iwh_amrr_t *)ic->ic_bss;
2450 2449
2451 2450 amrr->txcnt++;
2452 2451 IWH_DBG((IWH_DEBUG_RATECTL, "iwh_tx_intr(): "
2453 2452 "tx: %d cnt\n", amrr->txcnt));
2454 2453
2455 2454 if (stat->ntries > 0) {
2456 2455 amrr->retrycnt++;
2457 2456 sc->sc_tx_retries++;
2458 2457 IWH_DBG((IWH_DEBUG_TX, "iwh_tx_intr(): "
2459 2458 "tx: %d retries\n",
2460 2459 sc->sc_tx_retries));
2461 2460 }
2462 2461
2463 2462 mutex_enter(&sc->sc_mt_lock);
2464 2463 sc->sc_tx_timer = 0;
2465 2464 mutex_exit(&sc->sc_mt_lock);
2466 2465
2467 2466 mutex_enter(&sc->sc_tx_lock);
2468 2467
2469 2468 ring->queued--;
2470 2469 if (ring->queued < 0) {
2471 2470 ring->queued = 0;
2472 2471 }
2473 2472
2474 2473 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count >> 3))) {
2475 2474 sc->sc_need_reschedule = 0;
2476 2475 mutex_exit(&sc->sc_tx_lock);
2477 2476 mac_tx_update(ic->ic_mach);
2478 2477 mutex_enter(&sc->sc_tx_lock);
2479 2478 }
2480 2479
2481 2480 mutex_exit(&sc->sc_tx_lock);
2482 2481 }
2483 2482
2484 2483 /*
2485 2484 * inform a given command has been executed
2486 2485 */
2487 2486 static void
2488 2487 iwh_cmd_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2489 2488 {
2490 2489 if ((desc->hdr.qid & 7) != 4) {
2491 2490 return;
2492 2491 }
2493 2492
2494 2493 if (sc->sc_cmd_accum > 0) {
2495 2494 sc->sc_cmd_accum--;
2496 2495 return;
2497 2496 }
2498 2497
2499 2498 mutex_enter(&sc->sc_glock);
2500 2499
2501 2500 sc->sc_cmd_flag = SC_CMD_FLG_DONE;
2502 2501
2503 2502 cv_signal(&sc->sc_cmd_cv);
2504 2503
2505 2504 mutex_exit(&sc->sc_glock);
2506 2505
2507 2506 IWH_DBG((IWH_DEBUG_CMD, "iwh_cmd_intr(): "
2508 2507 "qid=%x idx=%d flags=%x type=0x%x\n",
2509 2508 desc->hdr.qid, desc->hdr.idx, desc->hdr.flags,
2510 2509 desc->hdr.type));
2511 2510 }
2512 2511
2513 2512 /*
2514 2513 * this function will be invoked when alive notification occur.
2515 2514 */
2516 2515 static void
2517 2516 iwh_ucode_alive(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2518 2517 {
2519 2518 uint32_t rv;
2520 2519 struct iwh_calib_cfg_cmd cmd;
2521 2520 struct iwh_alive_resp *ar =
2522 2521 (struct iwh_alive_resp *)(desc + 1);
2523 2522 struct iwh_calib_results *res_p = &sc->sc_calib_results;
2524 2523
2525 2524 /*
2526 2525 * the microcontroller is ready
2527 2526 */
2528 2527 IWH_DBG((IWH_DEBUG_FW, "iwh_ucode_alive(): "
2529 2528 "microcode alive notification minor: %x major: %x type: "
2530 2529 "%x subtype: %x\n",
2531 2530 ar->ucode_minor, ar->ucode_minor, ar->ver_type, ar->ver_subtype));
2532 2531
2533 2532 #ifdef DEBUG
2534 2533 if (LE_32(ar->is_valid) != UCODE_VALID_OK) {
2535 2534 IWH_DBG((IWH_DEBUG_FW, "iwh_ucode_alive(): "
2536 2535 "microcontroller initialization failed\n"));
2537 2536 }
2538 2537 #endif
2539 2538
2540 2539 /*
2541 2540 * determine if init alive or runtime alive.
2542 2541 */
2543 2542 if (INITIALIZE_SUBTYPE == ar->ver_subtype) {
2544 2543 IWH_DBG((IWH_DEBUG_FW, "iwh_ucode_alive(): "
2545 2544 "initialization alive received.\n"));
2546 2545
2547 2546 bcopy(ar, &sc->sc_card_alive_init,
2548 2547 sizeof (struct iwh_init_alive_resp));
2549 2548
2550 2549 /*
2551 2550 * necessary configuration to NIC
2552 2551 */
2553 2552 mutex_enter(&sc->sc_glock);
2554 2553
2555 2554 rv = iwh_alive_common(sc);
2556 2555 if (rv != IWH_SUCCESS) {
2557 2556 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2558 2557 "common alive process failed in init alive.\n");
2559 2558 mutex_exit(&sc->sc_glock);
2560 2559 return;
2561 2560 }
2562 2561
2563 2562 (void) memset(&cmd, 0, sizeof (cmd));
2564 2563
2565 2564 cmd.ucd_calib_cfg.once.is_enable = IWH_CALIB_INIT_CFG_ALL;
2566 2565 cmd.ucd_calib_cfg.once.start = IWH_CALIB_INIT_CFG_ALL;
2567 2566 cmd.ucd_calib_cfg.once.send_res = IWH_CALIB_INIT_CFG_ALL;
2568 2567 cmd.ucd_calib_cfg.flags = IWH_CALIB_INIT_CFG_ALL;
2569 2568
2570 2569 /*
2571 2570 * require ucode execute calibration
2572 2571 */
2573 2572 rv = iwh_cmd(sc, CALIBRATION_CFG_CMD, &cmd, sizeof (cmd), 1);
2574 2573 if (rv != IWH_SUCCESS) {
2575 2574 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2576 2575 "failed to send calibration configure command.\n");
2577 2576 mutex_exit(&sc->sc_glock);
2578 2577 return;
2579 2578 }
2580 2579
2581 2580 mutex_exit(&sc->sc_glock);
2582 2581
2583 2582 } else { /* runtime alive */
2584 2583
2585 2584 IWH_DBG((IWH_DEBUG_FW, "iwh_ucode_alive(): "
2586 2585 "runtime alive received.\n"));
2587 2586
2588 2587 bcopy(ar, &sc->sc_card_alive_run,
2589 2588 sizeof (struct iwh_alive_resp));
2590 2589
2591 2590 mutex_enter(&sc->sc_glock);
2592 2591
2593 2592 /*
2594 2593 * necessary configuration to NIC
2595 2594 */
2596 2595 rv = iwh_alive_common(sc);
2597 2596 if (rv != IWH_SUCCESS) {
2598 2597 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2599 2598 "common alive process failed in run alive.\n");
2600 2599 mutex_exit(&sc->sc_glock);
2601 2600 return;
2602 2601 }
2603 2602
2604 2603 /*
2605 2604 * send the result of local oscilator calibration to uCode.
2606 2605 */
2607 2606 if (res_p->lo_res != NULL) {
2608 2607 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2609 2608 res_p->lo_res, res_p->lo_res_len, 1);
2610 2609 if (rv != IWH_SUCCESS) {
2611 2610 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2612 2611 "failed to send local"
2613 2612 "oscilator calibration command.\n");
2614 2613 mutex_exit(&sc->sc_glock);
2615 2614 return;
2616 2615 }
2617 2616
2618 2617 DELAY(1000);
2619 2618 }
2620 2619
2621 2620 /*
2622 2621 * send the result of TX IQ calibration to uCode.
2623 2622 */
2624 2623 if (res_p->tx_iq_res != NULL) {
2625 2624 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2626 2625 res_p->tx_iq_res, res_p->tx_iq_res_len, 1);
2627 2626 if (rv != IWH_SUCCESS) {
2628 2627 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2629 2628 "failed to send TX IQ"
2630 2629 "calibration command.\n");
2631 2630 mutex_exit(&sc->sc_glock);
2632 2631 return;
2633 2632 }
2634 2633
2635 2634 DELAY(1000);
2636 2635 }
2637 2636
2638 2637 /*
2639 2638 * sned the result of TX IQ perd calibration to uCode.
2640 2639 */
2641 2640 if (res_p->tx_iq_perd_res != NULL) {
2642 2641 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2643 2642 res_p->tx_iq_perd_res,
2644 2643 res_p->tx_iq_perd_res_len, 1);
2645 2644 if (rv != IWH_SUCCESS) {
2646 2645 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2647 2646 "failed to send TX IQ perd"
2648 2647 "calibration command.\n");
2649 2648 mutex_exit(&sc->sc_glock);
2650 2649 return;
2651 2650 }
2652 2651
2653 2652 DELAY(1000);
2654 2653 }
2655 2654
2656 2655 /*
2657 2656 * send the result of DC calibration to uCode.
2658 2657 */
2659 2658 if (res_p->dc_res != NULL) {
2660 2659 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2661 2660 res_p->dc_res,
2662 2661 res_p->dc_res_len, 1);
2663 2662 if (rv != IWH_SUCCESS) {
2664 2663 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2665 2664 "failed to send DC"
2666 2665 "calibration command.\n");
2667 2666 mutex_exit(&sc->sc_glock);
2668 2667 return;
2669 2668 }
2670 2669
2671 2670 DELAY(1000);
2672 2671 }
2673 2672
2674 2673 /*
2675 2674 * send the result of BASE BAND calibration to uCode.
2676 2675 */
2677 2676 if (res_p->base_band_res != NULL) {
2678 2677 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2679 2678 res_p->base_band_res,
2680 2679 res_p->base_band_res_len, 1);
2681 2680 if (rv != IWH_SUCCESS) {
2682 2681 cmn_err(CE_WARN, "iwh_ucode_alive(): "
2683 2682 "failed to send BASE BAND"
2684 2683 "calibration command.\n");
2685 2684 mutex_exit(&sc->sc_glock);
2686 2685 return;
2687 2686 }
2688 2687
2689 2688 DELAY(1000);
2690 2689 }
2691 2690
2692 2691 atomic_or_32(&sc->sc_flags, IWH_F_FW_INIT);
2693 2692 cv_signal(&sc->sc_ucode_cv);
2694 2693
2695 2694 mutex_exit(&sc->sc_glock);
2696 2695 }
2697 2696
2698 2697 }
2699 2698
2700 2699 /*
2701 2700 * deal with receiving frames, command response
2702 2701 * and all notifications from ucode.
2703 2702 */
2704 2703 /* ARGSUSED */
2705 2704 static uint_t
2706 2705 iwh_rx_softintr(caddr_t arg, caddr_t unused)
2707 2706 {
2708 2707 iwh_sc_t *sc;
2709 2708 ieee80211com_t *ic;
2710 2709 iwh_rx_desc_t *desc;
2711 2710 iwh_rx_data_t *data;
2712 2711 uint32_t index;
2713 2712
2714 2713 if (NULL == arg) {
2715 2714 return (DDI_INTR_UNCLAIMED);
2716 2715 }
2717 2716 sc = (iwh_sc_t *)arg;
2718 2717 ic = &sc->sc_ic;
2719 2718
2720 2719 /*
2721 2720 * firmware has moved the index of the rx queue, driver get it,
2722 2721 * and deal with it.
2723 2722 */
2724 2723 index = (sc->sc_shared->val0) & 0xfff;
2725 2724
2726 2725 while (sc->sc_rxq.cur != index) {
2727 2726 data = &sc->sc_rxq.data[sc->sc_rxq.cur];
2728 2727 desc = (iwh_rx_desc_t *)data->dma_data.mem_va;
2729 2728
2730 2729 IWH_DBG((IWH_DEBUG_INTR, "iwh_rx_softintr(): "
2731 2730 "rx notification index = %d"
2732 2731 " cur = %d qid=%x idx=%d flags=%x type=%x len=%d\n",
2733 2732 index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx,
2734 2733 desc->hdr.flags, desc->hdr.type, LE_32(desc->len)));
2735 2734
2736 2735 /*
2737 2736 * a command other than a tx need to be replied
2738 2737 */
2739 2738 if (!(desc->hdr.qid & 0x80) &&
2740 2739 (desc->hdr.type != REPLY_SCAN_CMD) &&
2741 2740 (desc->hdr.type != REPLY_TX)) {
2742 2741 iwh_cmd_intr(sc, desc);
2743 2742 }
2744 2743
2745 2744 switch (desc->hdr.type) {
2746 2745 case REPLY_RX_PHY_CMD:
2747 2746 iwh_rx_phy_intr(sc, desc);
2748 2747 break;
2749 2748
2750 2749 case REPLY_RX_MPDU_CMD:
2751 2750 iwh_rx_mpdu_intr(sc, desc);
2752 2751 break;
2753 2752
2754 2753 case REPLY_TX:
2755 2754 iwh_tx_intr(sc, desc);
2756 2755 break;
2757 2756
2758 2757 case REPLY_ALIVE:
2759 2758 iwh_ucode_alive(sc, desc);
2760 2759 break;
2761 2760
2762 2761 case CARD_STATE_NOTIFICATION:
2763 2762 {
2764 2763 uint32_t *status = (uint32_t *)(desc + 1);
2765 2764
2766 2765 IWH_DBG((IWH_DEBUG_RADIO, "iwh_rx_softintr(): "
2767 2766 "state changed to %x\n",
2768 2767 LE_32(*status)));
2769 2768
2770 2769 if (LE_32(*status) & 1) {
2771 2770 /*
2772 2771 * the radio button has to be pushed(OFF). It
2773 2772 * is considered as a hw error, the
2774 2773 * iwh_thread() tries to recover it after the
2775 2774 * button is pushed again(ON)
2776 2775 */
2777 2776 cmn_err(CE_NOTE, "iwh_rx_softintr(): "
2778 2777 "radio transmitter is off\n");
2779 2778 sc->sc_ostate = sc->sc_ic.ic_state;
2780 2779 ieee80211_new_state(&sc->sc_ic,
2781 2780 IEEE80211_S_INIT, -1);
2782 2781 atomic_or_32(&sc->sc_flags,
2783 2782 (IWH_F_HW_ERR_RECOVER | IWH_F_RADIO_OFF));
2784 2783 }
2785 2784
2786 2785 break;
2787 2786 }
2788 2787
2789 2788 case SCAN_START_NOTIFICATION:
2790 2789 {
2791 2790 iwh_start_scan_t *scan =
2792 2791 (iwh_start_scan_t *)(desc + 1);
2793 2792
2794 2793 IWH_DBG((IWH_DEBUG_SCAN, "iwh_rx_softintr(): "
2795 2794 "scanning channel %d status %x\n",
2796 2795 scan->chan, LE_32(scan->status)));
2797 2796
2798 2797 ic->ic_curchan = &ic->ic_sup_channels[scan->chan];
2799 2798 break;
2800 2799 }
2801 2800
2802 2801 case SCAN_COMPLETE_NOTIFICATION:
2803 2802 {
2804 2803 #ifdef DEBUG
2805 2804 iwh_stop_scan_t *scan =
2806 2805 (iwh_stop_scan_t *)(desc + 1);
2807 2806
2808 2807 IWH_DBG((IWH_DEBUG_SCAN, "iwh_rx_softintr(): "
2809 2808 "completed channel %d (burst of %d) status %02x\n",
2810 2809 scan->chan, scan->nchan, scan->status));
2811 2810 #endif
2812 2811
2813 2812 sc->sc_scan_pending++;
2814 2813 break;
2815 2814 }
2816 2815
2817 2816 case STATISTICS_NOTIFICATION:
2818 2817 {
2819 2818 /*
2820 2819 * handle statistics notification
2821 2820 */
2822 2821 break;
2823 2822 }
2824 2823
2825 2824 case CALIBRATION_RES_NOTIFICATION:
2826 2825 iwh_save_calib_result(sc, desc);
2827 2826 break;
2828 2827
2829 2828 case CALIBRATION_COMPLETE_NOTIFICATION:
2830 2829 mutex_enter(&sc->sc_glock);
2831 2830 atomic_or_32(&sc->sc_flags, IWH_F_FW_INIT);
2832 2831 cv_signal(&sc->sc_ucode_cv);
2833 2832 mutex_exit(&sc->sc_glock);
2834 2833 break;
2835 2834
2836 2835 case MISSED_BEACONS_NOTIFICATION:
2837 2836 /* handle beacon miss by software mechanism */
2838 2837 break;
2839 2838 }
2840 2839
2841 2840 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE;
2842 2841 }
2843 2842
2844 2843 /*
2845 2844 * driver dealt with what received in rx queue and tell the information
2846 2845 * to the firmware.
2847 2846 */
2848 2847 index = (0 == index) ? RX_QUEUE_SIZE - 1 : index - 1;
2849 2848 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7));
2850 2849
2851 2850 /*
2852 2851 * re-enable interrupts
2853 2852 */
2854 2853 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2855 2854
2856 2855 return (DDI_INTR_CLAIMED);
2857 2856 }
2858 2857
2859 2858 /*
2860 2859 * the handle of interrupt
2861 2860 */
2862 2861 /* ARGSUSED */
2863 2862 static uint_t
2864 2863 iwh_intr(caddr_t arg, caddr_t unused)
2865 2864 {
2866 2865 iwh_sc_t *sc;
2867 2866 uint32_t r, rfh;
2868 2867
2869 2868 if (NULL == arg) {
2870 2869 return (DDI_INTR_UNCLAIMED);
2871 2870 }
2872 2871 sc = (iwh_sc_t *)arg;
2873 2872
2874 2873 r = IWH_READ(sc, CSR_INT);
2875 2874 if (0 == r || 0xffffffff == r) {
2876 2875 return (DDI_INTR_UNCLAIMED);
2877 2876 }
2878 2877
2879 2878 IWH_DBG((IWH_DEBUG_INTR, "iwh_intr(): "
2880 2879 "interrupt reg %x\n", r));
2881 2880
2882 2881 rfh = IWH_READ(sc, CSR_FH_INT_STATUS);
2883 2882
2884 2883 IWH_DBG((IWH_DEBUG_INTR, "iwh_intr(): "
2885 2884 "FH interrupt reg %x\n", rfh));
2886 2885
2887 2886 /*
2888 2887 * disable interrupts
2889 2888 */
2890 2889 IWH_WRITE(sc, CSR_INT_MASK, 0);
2891 2890
2892 2891 /*
2893 2892 * ack interrupts
2894 2893 */
2895 2894 IWH_WRITE(sc, CSR_INT, r);
2896 2895 IWH_WRITE(sc, CSR_FH_INT_STATUS, rfh);
2897 2896
2898 2897 if (r & (BIT_INT_SWERROR | BIT_INT_ERR)) {
2899 2898 IWH_DBG((IWH_DEBUG_FW, "iwh_intr(): "
2900 2899 "fatal firmware error\n"));
2901 2900 iwh_stop(sc);
2902 2901 sc->sc_ostate = sc->sc_ic.ic_state;
2903 2902
2904 2903 /*
2905 2904 * notify upper layer
2906 2905 */
2907 2906 if (!IWH_CHK_FAST_RECOVER(sc)) {
2908 2907 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2909 2908 }
2910 2909
2911 2910 atomic_or_32(&sc->sc_flags, IWH_F_HW_ERR_RECOVER);
2912 2911 return (DDI_INTR_CLAIMED);
2913 2912 }
2914 2913
2915 2914 if (r & BIT_INT_RF_KILL) {
2916 2915 uint32_t tmp = IWH_READ(sc, CSR_GP_CNTRL);
2917 2916 if (tmp & (1 << 27)) {
2918 2917 cmn_err(CE_NOTE, "RF switch: radio on\n");
2919 2918 }
2920 2919 }
2921 2920
2922 2921 if ((r & (BIT_INT_FH_RX | BIT_INT_SW_RX)) ||
2923 2922 (rfh & FH_INT_RX_MASK)) {
2924 2923 (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL);
2925 2924 return (DDI_INTR_CLAIMED);
2926 2925 }
2927 2926
2928 2927 if (r & BIT_INT_FH_TX) {
2929 2928 mutex_enter(&sc->sc_glock);
2930 2929 atomic_or_32(&sc->sc_flags, IWH_F_PUT_SEG);
2931 2930 cv_signal(&sc->sc_put_seg_cv);
2932 2931 mutex_exit(&sc->sc_glock);
2933 2932 }
2934 2933
2935 2934 #ifdef DEBUG
2936 2935 if (r & BIT_INT_ALIVE) {
2937 2936 IWH_DBG((IWH_DEBUG_FW, "iwh_intr(): "
2938 2937 "firmware initialized.\n"));
2939 2938 }
2940 2939 #endif
2941 2940
2942 2941 /*
2943 2942 * re-enable interrupts
2944 2943 */
2945 2944 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2946 2945
2947 2946 return (DDI_INTR_CLAIMED);
2948 2947 }
2949 2948
2950 2949 static uint8_t
2951 2950 iwh_rate_to_plcp(int rate)
2952 2951 {
2953 2952 uint8_t ret;
2954 2953
2955 2954 switch (rate) {
2956 2955 /*
2957 2956 * CCK rates
2958 2957 */
2959 2958 case 2:
2960 2959 ret = 0xa;
2961 2960 break;
2962 2961
2963 2962 case 4:
2964 2963 ret = 0x14;
2965 2964 break;
2966 2965
2967 2966 case 11:
2968 2967 ret = 0x37;
2969 2968 break;
2970 2969
2971 2970 case 22:
2972 2971 ret = 0x6e;
2973 2972 break;
2974 2973
2975 2974 /*
2976 2975 * OFDM rates
2977 2976 */
2978 2977 case 12:
2979 2978 ret = 0xd;
2980 2979 break;
2981 2980
2982 2981 case 18:
2983 2982 ret = 0xf;
2984 2983 break;
2985 2984
2986 2985 case 24:
2987 2986 ret = 0x5;
2988 2987 break;
2989 2988
2990 2989 case 36:
2991 2990 ret = 0x7;
2992 2991 break;
2993 2992
2994 2993 case 48:
2995 2994 ret = 0x9;
2996 2995 break;
2997 2996
2998 2997 case 72:
2999 2998 ret = 0xb;
3000 2999 break;
3001 3000
3002 3001 case 96:
3003 3002 ret = 0x1;
3004 3003 break;
3005 3004
3006 3005 case 108:
3007 3006 ret = 0x3;
3008 3007 break;
3009 3008
3010 3009 default:
3011 3010 ret = 0;
3012 3011 break;
3013 3012 }
3014 3013
3015 3014 return (ret);
3016 3015 }
3017 3016
3018 3017 /*
3019 3018 * invoked by GLD send frames
3020 3019 */
3021 3020 static mblk_t *
3022 3021 iwh_m_tx(void *arg, mblk_t *mp)
3023 3022 {
3024 3023 iwh_sc_t *sc;
3025 3024 ieee80211com_t *ic;
3026 3025 mblk_t *next;
3027 3026
3028 3027 if (NULL == arg) {
3029 3028 return (NULL);
3030 3029 }
3031 3030 sc = (iwh_sc_t *)arg;
3032 3031 ic = &sc->sc_ic;
3033 3032
3034 3033 if (sc->sc_flags & IWH_F_SUSPEND) {
3035 3034 freemsgchain(mp);
3036 3035 return (NULL);
3037 3036 }
3038 3037
3039 3038 if (ic->ic_state != IEEE80211_S_RUN) {
3040 3039 freemsgchain(mp);
3041 3040 return (NULL);
3042 3041 }
3043 3042
3044 3043 if ((sc->sc_flags & IWH_F_HW_ERR_RECOVER) &&
3045 3044 IWH_CHK_FAST_RECOVER(sc)) {
3046 3045 IWH_DBG((IWH_DEBUG_FW, "iwh_m_tx(): "
3047 3046 "hold queue\n"));
3048 3047 return (mp);
3049 3048 }
3050 3049
3051 3050 while (mp != NULL) {
3052 3051 next = mp->b_next;
3053 3052 mp->b_next = NULL;
3054 3053 if (iwh_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != 0) {
3055 3054 mp->b_next = next;
3056 3055 break;
3057 3056 }
3058 3057 mp = next;
3059 3058 }
3060 3059
3061 3060 return (mp);
3062 3061 }
3063 3062
3064 3063 /*
3065 3064 * send frames
3066 3065 */
3067 3066 static int
3068 3067 iwh_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
3069 3068 {
3070 3069 iwh_sc_t *sc;
3071 3070 iwh_tx_ring_t *ring;
3072 3071 iwh_tx_desc_t *desc;
3073 3072 iwh_tx_data_t *data;
3074 3073 iwh_tx_data_t *desc_data;
3075 3074 iwh_cmd_t *cmd;
3076 3075 iwh_tx_cmd_t *tx;
3077 3076 ieee80211_node_t *in;
3078 3077 struct ieee80211_frame *wh, *mp_wh;
3079 3078 struct ieee80211_key *k = NULL;
3080 3079 mblk_t *m, *m0;
3081 3080 int hdrlen, len, len0, mblen, off, err = IWH_SUCCESS;
3082 3081 uint16_t masks = 0;
3083 3082 uint32_t rate, s_id = 0;
3084 3083 int txq_id = NON_QOS_TXQ;
3085 3084 struct ieee80211_qosframe *qwh = NULL;
3086 3085 int tid = WME_TID_INVALID;
3087 3086
3088 3087 if (NULL == ic) {
3089 3088 return (IWH_FAIL);
3090 3089 }
3091 3090 sc = (iwh_sc_t *)ic;
3092 3091
3093 3092 if (sc->sc_flags & IWH_F_SUSPEND) {
3094 3093 if ((type & IEEE80211_FC0_TYPE_MASK) !=
3095 3094 IEEE80211_FC0_TYPE_DATA) {
3096 3095 freemsg(mp);
3097 3096 }
3098 3097 err = IWH_FAIL;
3099 3098 goto exit;
3100 3099 }
3101 3100
3102 3101 if ((NULL == mp) || (MBLKL(mp) <= 0)) {
3103 3102 return (IWH_FAIL);
3104 3103 }
3105 3104
3106 3105 mp_wh = (struct ieee80211_frame *)mp->b_rptr;
3107 3106
3108 3107 /*
3109 3108 * Determine send which AP or station in IBSS
3110 3109 */
3111 3110 in = ieee80211_find_txnode(ic, mp_wh->i_addr1);
3112 3111 if (NULL == in) {
3113 3112 cmn_err(CE_WARN, "iwh_send(): "
3114 3113 "failed to find tx node\n");
3115 3114 freemsg(mp);
3116 3115 sc->sc_tx_err++;
3117 3116 err = IWH_SUCCESS;
3118 3117 goto exit;
3119 3118 }
3120 3119
3121 3120 /*
3122 3121 * Determine TX queue according to traffic ID in frame
3123 3122 * if working in QoS mode.
3124 3123 */
3125 3124 if (in->in_flags & IEEE80211_NODE_QOS) {
3126 3125
3127 3126 if ((type & IEEE80211_FC0_TYPE_MASK) ==
3128 3127 IEEE80211_FC0_TYPE_DATA) {
3129 3128
3130 3129 if (mp_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
3131 3130 qwh = (struct ieee80211_qosframe *)mp_wh;
3132 3131
3133 3132 tid = qwh->i_qos[0] & IEEE80211_QOS_TID;
3134 3133 txq_id = iwh_wme_tid_to_txq(tid);
3135 3134
3136 3135 if (txq_id < TXQ_FOR_AC_MIN ||
3137 3136 (txq_id > TXQ_FOR_AC_MAX)) {
3138 3137 freemsg(mp);
3139 3138 sc->sc_tx_err++;
3140 3139 err = IWH_SUCCESS;
3141 3140 goto exit;
3142 3141 }
3143 3142
3144 3143 } else {
3145 3144 txq_id = NON_QOS_TXQ;
3146 3145 }
3147 3146
3148 3147 } else if ((type & IEEE80211_FC0_TYPE_MASK) ==
3149 3148 IEEE80211_FC0_TYPE_MGT) {
3150 3149 txq_id = QOS_TXQ_FOR_MGT;
3151 3150 } else {
3152 3151 txq_id = NON_QOS_TXQ;
3153 3152 }
3154 3153
3155 3154 } else {
3156 3155 txq_id = NON_QOS_TXQ;
3157 3156 }
3158 3157
3159 3158 mutex_enter(&sc->sc_tx_lock);
3160 3159 ring = &sc->sc_txq[txq_id];
3161 3160 data = &ring->data[ring->cur];
3162 3161 cmd = data->cmd;
3163 3162 bzero(cmd, sizeof (*cmd));
3164 3163
3165 3164 ring->cur = (ring->cur + 1) % ring->count;
3166 3165
3167 3166 /*
3168 3167 * Need reschedule TX if TX buffer is full.
3169 3168 */
3170 3169 if (ring->queued > ring->count - IWH_MAX_WIN_SIZE) {
3171 3170 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3172 3171 "no txbuf\n"));
3173 3172
3174 3173 sc->sc_need_reschedule = 1;
3175 3174 mutex_exit(&sc->sc_tx_lock);
3176 3175
3177 3176 if ((type & IEEE80211_FC0_TYPE_MASK) !=
3178 3177 IEEE80211_FC0_TYPE_DATA) {
3179 3178 freemsg(mp);
3180 3179 }
3181 3180 sc->sc_tx_nobuf++;
3182 3181 err = IWH_FAIL;
3183 3182 goto exit;
3184 3183 }
3185 3184
3186 3185 ring->queued++;
3187 3186
3188 3187 mutex_exit(&sc->sc_tx_lock);
3189 3188
3190 3189 hdrlen = ieee80211_hdrspace(ic, mp->b_rptr);
3191 3190
3192 3191 m = allocb(msgdsize(mp) + 32, BPRI_MED);
3193 3192 if (NULL == m) { /* can not alloc buf, drop this package */
3194 3193 cmn_err(CE_WARN, "iwh_send(): "
3195 3194 "failed to allocate msgbuf\n");
3196 3195 freemsg(mp);
3197 3196
3198 3197 mutex_enter(&sc->sc_tx_lock);
3199 3198 ring->queued--;
3200 3199 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3201 3200 sc->sc_need_reschedule = 0;
3202 3201 mutex_exit(&sc->sc_tx_lock);
3203 3202 mac_tx_update(ic->ic_mach);
3204 3203 mutex_enter(&sc->sc_tx_lock);
3205 3204 }
3206 3205 mutex_exit(&sc->sc_tx_lock);
3207 3206
3208 3207 err = IWH_SUCCESS;
3209 3208 goto exit;
3210 3209 }
3211 3210
3212 3211 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
3213 3212 mblen = MBLKL(m0);
3214 3213 bcopy(m0->b_rptr, m->b_rptr + off, mblen);
3215 3214 off += mblen;
3216 3215 }
3217 3216
3218 3217 m->b_wptr += off;
3219 3218
3220 3219 wh = (struct ieee80211_frame *)m->b_rptr;
3221 3220
3222 3221 /*
3223 3222 * Net80211 module encapsulate outbound data frames.
3224 3223 * Add some feilds of 80211 frame.
3225 3224 */
3226 3225 if ((type & IEEE80211_FC0_TYPE_MASK) ==
3227 3226 IEEE80211_FC0_TYPE_DATA) {
3228 3227 (void) ieee80211_encap(ic, m, in);
3229 3228 }
3230 3229
3231 3230 freemsg(mp);
3232 3231
3233 3232 cmd->hdr.type = REPLY_TX;
3234 3233 cmd->hdr.flags = 0;
3235 3234 cmd->hdr.qid = ring->qid;
3236 3235
3237 3236 tx = (iwh_tx_cmd_t *)cmd->data;
3238 3237 tx->tx_flags = 0;
3239 3238
3240 3239 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3241 3240 tx->tx_flags &= ~(LE_32(TX_CMD_FLG_ACK_MSK));
3242 3241 } else {
3243 3242 tx->tx_flags |= LE_32(TX_CMD_FLG_ACK_MSK);
3244 3243 }
3245 3244
3246 3245 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
3247 3246 k = ieee80211_crypto_encap(ic, m);
3248 3247 if (NULL == k) {
3249 3248 freemsg(m);
3250 3249 sc->sc_tx_err++;
3251 3250
3252 3251 mutex_enter(&sc->sc_tx_lock);
3253 3252 ring->queued--;
3254 3253 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3255 3254 sc->sc_need_reschedule = 0;
3256 3255 mutex_exit(&sc->sc_tx_lock);
3257 3256 mac_tx_update(ic->ic_mach);
3258 3257 mutex_enter(&sc->sc_tx_lock);
3259 3258 }
3260 3259 mutex_exit(&sc->sc_tx_lock);
3261 3260
3262 3261 err = IWH_SUCCESS;
3263 3262 goto exit;
3264 3263 }
3265 3264
3266 3265 /*
3267 3266 * packet header may have moved, reset our local pointer
3268 3267 */
3269 3268 wh = (struct ieee80211_frame *)m->b_rptr;
3270 3269 }
3271 3270
3272 3271 len = msgdsize(m);
3273 3272
3274 3273 #ifdef DEBUG
3275 3274 if (iwh_dbg_flags & IWH_DEBUG_TX) {
3276 3275 ieee80211_dump_pkt((uint8_t *)wh, hdrlen, 0, 0);
3277 3276 }
3278 3277 #endif
3279 3278
3280 3279 tx->rts_retry_limit = IWH_TX_RTS_RETRY_LIMIT;
3281 3280 tx->data_retry_limit = IWH_TX_DATA_RETRY_LIMIT;
3282 3281
3283 3282 /*
3284 3283 * specific TX parameters for management frames
3285 3284 */
3286 3285 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3287 3286 IEEE80211_FC0_TYPE_MGT) {
3288 3287 /*
3289 3288 * mgmt frames are sent at 1M
3290 3289 */
3291 3290 if ((in->in_rates.ir_rates[0] &
3292 3291 IEEE80211_RATE_VAL) != 0) {
3293 3292 rate = in->in_rates.ir_rates[0] & IEEE80211_RATE_VAL;
3294 3293 } else {
3295 3294 rate = 2;
3296 3295 }
3297 3296
3298 3297 tx->tx_flags |= LE_32(TX_CMD_FLG_SEQ_CTL_MSK);
3299 3298
3300 3299 /*
3301 3300 * tell h/w to set timestamp in probe responses
3302 3301 */
3303 3302 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3304 3303 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
3305 3304 tx->tx_flags |= LE_32(TX_CMD_FLG_TSF_MSK);
3306 3305
3307 3306 tx->data_retry_limit = 3;
3308 3307 if (tx->data_retry_limit < tx->rts_retry_limit) {
3309 3308 tx->rts_retry_limit = tx->data_retry_limit;
3310 3309 }
3311 3310 }
3312 3311
3313 3312 if (((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3314 3313 IEEE80211_FC0_SUBTYPE_ASSOC_REQ) ||
3315 3314 ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3316 3315 IEEE80211_FC0_SUBTYPE_REASSOC_REQ)) {
3317 3316 tx->timeout.pm_frame_timeout = LE_16(3);
3318 3317 } else {
3319 3318 tx->timeout.pm_frame_timeout = LE_16(2);
3320 3319 }
3321 3320
3322 3321 } else {
3323 3322 /*
3324 3323 * do it here for the software way rate scaling.
3325 3324 * later for rate scaling in hardware.
3326 3325 *
3327 3326 * now the txrate is determined in tx cmd flags, set to the
3328 3327 * max value 54M for 11g and 11M for 11b and 96M for 11n
3329 3328 * originally.
3330 3329 */
3331 3330 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
3332 3331 rate = ic->ic_fixed_rate;
3333 3332 } else {
3334 3333 if ((in->in_flags & IEEE80211_NODE_HT) &&
3335 3334 (sc->sc_ht_conf.ht_support)) {
3336 3335 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
3337 3336 rate = amrr->ht_mcs_idx;
3338 3337 } else {
3339 3338 if ((in->in_rates.ir_rates[in->in_txrate] &
3340 3339 IEEE80211_RATE_VAL) != 0) {
3341 3340 rate = in->in_rates.
3342 3341 ir_rates[in->in_txrate] &
3343 3342 IEEE80211_RATE_VAL;
3344 3343 }
3345 3344 }
3346 3345 }
3347 3346
3348 3347 if (tid != WME_TID_INVALID) {
3349 3348 tx->tid_tspec = (uint8_t)tid;
3350 3349 tx->tx_flags &= LE_32(~TX_CMD_FLG_SEQ_CTL_MSK);
3351 3350 } else {
3352 3351 tx->tx_flags |= LE_32(TX_CMD_FLG_SEQ_CTL_MSK);
3353 3352 }
3354 3353
3355 3354 tx->timeout.pm_frame_timeout = 0;
3356 3355 }
3357 3356
3358 3357 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3359 3358 "tx rate[%d of %d] = %x",
3360 3359 in->in_txrate, in->in_rates.ir_nrates, rate));
3361 3360
3362 3361 len0 = roundup(4 + sizeof (iwh_tx_cmd_t) + hdrlen, 4);
3363 3362 if (len0 != (4 + sizeof (iwh_tx_cmd_t) + hdrlen)) {
3364 3363 tx->tx_flags |= LE_32(TX_CMD_FLG_MH_PAD_MSK);
3365 3364 }
3366 3365
3367 3366 /*
3368 3367 * retrieve destination node's id
3369 3368 */
3370 3369 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3371 3370 tx->sta_id = IWH_BROADCAST_ID;
3372 3371 } else {
3373 3372 tx->sta_id = IWH_AP_ID;
3374 3373 }
3375 3374
3376 3375 if ((in->in_flags & IEEE80211_NODE_HT) &&
3377 3376 (sc->sc_ht_conf.ht_support) &&
3378 3377 ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3379 3378 IEEE80211_FC0_TYPE_DATA)) {
3380 3379 if (rate >= HT_2CHAIN_RATE_MIN_IDX) {
3381 3380 rate |= LE_32(RATE_MCS_ANT_AB_MSK);
3382 3381 } else {
3383 3382 rate |= LE_32(RATE_MCS_ANT_B_MSK);
3384 3383 }
3385 3384
3386 3385 rate |= LE_32((1 << RATE_MCS_HT_POS));
3387 3386
3388 3387 tx->rate.r.rate_n_flags = rate;
3389 3388
3390 3389 } else {
3391 3390 if (2 == rate || 4 == rate || 11 == rate || 22 == rate) {
3392 3391 masks |= RATE_MCS_CCK_MSK;
3393 3392 }
3394 3393
3395 3394 masks |= RATE_MCS_ANT_B_MSK;
3396 3395 tx->rate.r.rate_n_flags = LE_32(iwh_rate_to_plcp(rate) | masks);
3397 3396 }
3398 3397
3399 3398 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3400 3399 "tx flag = %x",
3401 3400 tx->tx_flags));
3402 3401
3403 3402 tx->stop_time.life_time = LE_32(0xffffffff);
3404 3403
3405 3404 tx->len = LE_16(len);
3406 3405
3407 3406 tx->dram_lsb_ptr =
3408 3407 LE_32(data->paddr_cmd + 4 + offsetof(iwh_tx_cmd_t, scratch));
3409 3408 tx->dram_msb_ptr = 0;
3410 3409 tx->driver_txop = 0;
3411 3410 tx->next_frame_len = 0;
3412 3411
3413 3412 bcopy(m->b_rptr, tx + 1, hdrlen);
3414 3413 m->b_rptr += hdrlen;
3415 3414 bcopy(m->b_rptr, data->dma_data.mem_va, (len - hdrlen));
3416 3415
3417 3416 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3418 3417 "sending data: qid=%d idx=%d len=%d",
3419 3418 ring->qid, ring->cur, len));
3420 3419
3421 3420 /*
3422 3421 * first segment includes the tx cmd plus the 802.11 header,
3423 3422 * the second includes the remaining of the 802.11 frame.
3424 3423 */
3425 3424
3426 3425 mutex_enter(&sc->sc_tx_lock);
3427 3426 cmd->hdr.idx = ring->desc_cur;
3428 3427 desc_data = &ring->data[ring->desc_cur];
3429 3428 desc = desc_data->desc;
3430 3429 bzero(desc, sizeof (*desc));
3431 3430 desc->val0 = 2 << 24;
3432 3431 desc->pa[0].tb1_addr = data->paddr_cmd;
3433 3432 desc->pa[0].val1 = ((len0 << 4) & 0xfff0) |
3434 3433 ((data->dma_data.cookie.dmac_address & 0xffff) << 16);
3435 3434 desc->pa[0].val2 =
3436 3435 ((data->dma_data.cookie.dmac_address & 0xffff0000) >> 16) |
3437 3436 ((len - hdrlen) << 20);
3438 3437 IWH_DBG((IWH_DEBUG_TX, "iwh_send(): "
3439 3438 "phy addr1 = 0x%x phy addr2 = 0x%x "
3440 3439 "len1 = 0x%x, len2 = 0x%x val1 = 0x%x val2 = 0x%x",
3441 3440 data->paddr_cmd, data->dma_data.cookie.dmac_address,
3442 3441 len0, len - hdrlen, desc->pa[0].val1, desc->pa[0].val2));
3443 3442
3444 3443 /*
3445 3444 * kick ring
3446 3445 */
3447 3446 s_id = tx->sta_id;
3448 3447
3449 3448 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3450 3449 tfd_offset[ring->desc_cur].val =
3451 3450 (8 + len) | (s_id << 12);
3452 3451 if (ring->desc_cur < IWH_MAX_WIN_SIZE) {
3453 3452 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3454 3453 tfd_offset[IWH_QUEUE_SIZE + ring->desc_cur].val =
3455 3454 (8 + len) | (s_id << 12);
3456 3455 }
3457 3456
3458 3457 IWH_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV);
3459 3458 IWH_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
3460 3459
3461 3460 ring->desc_cur = (ring->desc_cur + 1) % ring->count;
3462 3461 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur);
3463 3462
3464 3463 mutex_exit(&sc->sc_tx_lock);
3465 3464 freemsg(m);
3466 3465
3467 3466 /*
3468 3467 * release node reference
3469 3468 */
3470 3469 ieee80211_free_node(in);
3471 3470
3472 3471 ic->ic_stats.is_tx_bytes += len;
3473 3472 ic->ic_stats.is_tx_frags++;
3474 3473
3475 3474 mutex_enter(&sc->sc_mt_lock);
3476 3475 if (0 == sc->sc_tx_timer) {
3477 3476 sc->sc_tx_timer = 4;
3478 3477 }
3479 3478 mutex_exit(&sc->sc_mt_lock);
3480 3479
3481 3480 exit:
3482 3481 return (err);
3483 3482 }
3484 3483
3485 3484 /*
3486 3485 * invoked by GLD to deal with IOCTL affaires
3487 3486 */
3488 3487 static void
3489 3488 iwh_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
3490 3489 {
3491 3490 iwh_sc_t *sc;
3492 3491 ieee80211com_t *ic;
3493 3492 int err = EINVAL;
3494 3493
3495 3494 if (NULL == arg) {
3496 3495 return;
3497 3496 }
3498 3497 sc = (iwh_sc_t *)arg;
3499 3498 ic = &sc->sc_ic;
3500 3499
3501 3500 err = ieee80211_ioctl(ic, wq, mp);
3502 3501 if (ENETRESET == err) {
3503 3502 /*
3504 3503 * This is special for the hidden AP connection.
3505 3504 * In any case, we should make sure only one 'scan'
3506 3505 * in the driver for a 'connect' CLI command. So
3507 3506 * when connecting to a hidden AP, the scan is just
3508 3507 * sent out to the air when we know the desired
3509 3508 * essid of the AP we want to connect.
3510 3509 */
3511 3510 if (ic->ic_des_esslen) {
3512 3511 if (sc->sc_flags & IWH_F_RUNNING) {
3513 3512 iwh_m_stop(sc);
3514 3513 (void) iwh_m_start(sc);
3515 3514 (void) ieee80211_new_state(ic,
3516 3515 IEEE80211_S_SCAN, -1);
3517 3516 }
3518 3517 }
3519 3518 }
3520 3519 }
3521 3520
3522 3521 /*
3523 3522 * Call back functions for get/set proporty
3524 3523 */
3525 3524 static int
3526 3525 iwh_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3527 3526 uint_t wldp_length, void *wldp_buf)
3528 3527 {
3529 3528 iwh_sc_t *sc;
3530 3529 int err = EINVAL;
3531 3530
3532 3531 if (NULL == arg) {
3533 3532 return (EINVAL);
3534 3533 }
3535 3534 sc = (iwh_sc_t *)arg;
3536 3535
3537 3536 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
3538 3537 wldp_length, wldp_buf);
3539 3538
3540 3539 return (err);
3541 3540 }
3542 3541
3543 3542 static void
3544 3543 iwh_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3545 3544 mac_prop_info_handle_t mph)
3546 3545 {
3547 3546 iwh_sc_t *sc = (iwh_sc_t *)arg;
3548 3547
3549 3548 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, mph);
3550 3549 }
3551 3550
3552 3551 static int
3553 3552 iwh_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3554 3553 uint_t wldp_length, const void *wldp_buf)
3555 3554 {
3556 3555 iwh_sc_t *sc;
3557 3556 ieee80211com_t *ic;
3558 3557 int err = EINVAL;
3559 3558
3560 3559 if (NULL == arg) {
3561 3560 return (EINVAL);
3562 3561 }
3563 3562 sc = (iwh_sc_t *)arg;
3564 3563 ic = &sc->sc_ic;
3565 3564
3566 3565 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
3567 3566 wldp_buf);
3568 3567
3569 3568 if (err == ENETRESET) {
3570 3569 if (ic->ic_des_esslen) {
3571 3570 if (sc->sc_flags & IWH_F_RUNNING) {
3572 3571 iwh_m_stop(sc);
3573 3572 (void) iwh_m_start(sc);
3574 3573 (void) ieee80211_new_state(ic,
3575 3574 IEEE80211_S_SCAN, -1);
3576 3575 }
3577 3576 }
3578 3577 err = 0;
3579 3578 }
3580 3579 return (err);
3581 3580 }
3582 3581
3583 3582 /*
3584 3583 * invoked by GLD supply statistics NIC and driver
3585 3584 */
3586 3585 static int
3587 3586 iwh_m_stat(void *arg, uint_t stat, uint64_t *val)
3588 3587 {
3589 3588 iwh_sc_t *sc;
3590 3589 ieee80211com_t *ic;
3591 3590 ieee80211_node_t *in;
3592 3591
3593 3592 if (NULL == arg) {
3594 3593 return (EINVAL);
3595 3594 }
3596 3595 sc = (iwh_sc_t *)arg;
3597 3596 ic = &sc->sc_ic;
3598 3597
3599 3598 mutex_enter(&sc->sc_glock);
3600 3599
3601 3600 switch (stat) {
3602 3601 case MAC_STAT_IFSPEED:
3603 3602 in = ic->ic_bss;
3604 3603 *val = ((IEEE80211_FIXED_RATE_NONE == ic->ic_fixed_rate) ?
3605 3604 IEEE80211_RATE(in->in_txrate) :
3606 3605 ic->ic_fixed_rate) / 2 * 1000000;
3607 3606 break;
3608 3607
3609 3608 case MAC_STAT_NOXMTBUF:
3610 3609 *val = sc->sc_tx_nobuf;
3611 3610 break;
3612 3611
3613 3612 case MAC_STAT_NORCVBUF:
3614 3613 *val = sc->sc_rx_nobuf;
3615 3614 break;
3616 3615
3617 3616 case MAC_STAT_IERRORS:
3618 3617 *val = sc->sc_rx_err;
3619 3618 break;
3620 3619
3621 3620 case MAC_STAT_RBYTES:
3622 3621 *val = ic->ic_stats.is_rx_bytes;
3623 3622 break;
3624 3623
3625 3624 case MAC_STAT_IPACKETS:
3626 3625 *val = ic->ic_stats.is_rx_frags;
3627 3626 break;
3628 3627
3629 3628 case MAC_STAT_OBYTES:
3630 3629 *val = ic->ic_stats.is_tx_bytes;
3631 3630 break;
3632 3631
3633 3632 case MAC_STAT_OPACKETS:
3634 3633 *val = ic->ic_stats.is_tx_frags;
3635 3634 break;
3636 3635
3637 3636 case MAC_STAT_OERRORS:
3638 3637 case WIFI_STAT_TX_FAILED:
3639 3638 *val = sc->sc_tx_err;
3640 3639 break;
3641 3640
3642 3641 case WIFI_STAT_TX_RETRANS:
3643 3642 *val = sc->sc_tx_retries;
3644 3643 break;
3645 3644
3646 3645 case WIFI_STAT_FCS_ERRORS:
3647 3646 case WIFI_STAT_WEP_ERRORS:
3648 3647 case WIFI_STAT_TX_FRAGS:
3649 3648 case WIFI_STAT_MCAST_TX:
3650 3649 case WIFI_STAT_RTS_SUCCESS:
3651 3650 case WIFI_STAT_RTS_FAILURE:
3652 3651 case WIFI_STAT_ACK_FAILURE:
3653 3652 case WIFI_STAT_RX_FRAGS:
3654 3653 case WIFI_STAT_MCAST_RX:
3655 3654 case WIFI_STAT_RX_DUPS:
3656 3655 mutex_exit(&sc->sc_glock);
3657 3656 return (ieee80211_stat(ic, stat, val));
3658 3657
3659 3658 default:
3660 3659 mutex_exit(&sc->sc_glock);
3661 3660 return (ENOTSUP);
3662 3661 }
3663 3662
3664 3663 mutex_exit(&sc->sc_glock);
3665 3664
3666 3665 return (IWH_SUCCESS);
3667 3666 }
3668 3667
3669 3668 /*
3670 3669 * invoked by GLD to start or open NIC
3671 3670 */
3672 3671 static int
3673 3672 iwh_m_start(void *arg)
3674 3673 {
3675 3674 iwh_sc_t *sc;
3676 3675 ieee80211com_t *ic;
3677 3676 int err = IWH_FAIL;
3678 3677
3679 3678 if (NULL == arg) {
3680 3679 return (EINVAL);
3681 3680 }
3682 3681 sc = (iwh_sc_t *)arg;
3683 3682 ic = &sc->sc_ic;
3684 3683
3685 3684 err = iwh_init(sc);
3686 3685 if (err != IWH_SUCCESS) {
3687 3686 /*
3688 3687 * The hw init err(eg. RF is OFF). Return Success to make
3689 3688 * the 'plumb' succeed. The iwh_thread() tries to re-init
3690 3689 * background.
3691 3690 */
3692 3691 atomic_or_32(&sc->sc_flags, IWH_F_HW_ERR_RECOVER);
3693 3692 return (IWH_SUCCESS);
3694 3693 }
3695 3694
3696 3695 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3697 3696
3698 3697 atomic_or_32(&sc->sc_flags, IWH_F_RUNNING);
3699 3698
3700 3699 return (IWH_SUCCESS);
3701 3700 }
3702 3701
3703 3702 /*
3704 3703 * invoked by GLD to stop or down NIC
3705 3704 */
3706 3705 static void
3707 3706 iwh_m_stop(void *arg)
3708 3707 {
3709 3708 iwh_sc_t *sc;
3710 3709 ieee80211com_t *ic;
3711 3710
3712 3711 if (NULL == arg) {
3713 3712 return;
3714 3713 }
3715 3714 sc = (iwh_sc_t *)arg;
3716 3715 ic = &sc->sc_ic;
3717 3716
3718 3717 iwh_stop(sc);
3719 3718
3720 3719 /*
3721 3720 * release buffer for calibration
3722 3721 */
3723 3722 iwh_release_calib_buffer(sc);
3724 3723
3725 3724 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3726 3725
3727 3726 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
3728 3727 atomic_and_32(&sc->sc_flags, ~IWH_F_RATE_AUTO_CTL);
3729 3728
3730 3729 atomic_and_32(&sc->sc_flags, ~IWH_F_RUNNING);
3731 3730 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
3732 3731 }
3733 3732
3734 3733 /*
3735 3734 * invoked by GLD to configure NIC
3736 3735 */
3737 3736 static int
3738 3737 iwh_m_unicst(void *arg, const uint8_t *macaddr)
3739 3738 {
3740 3739 iwh_sc_t *sc;
3741 3740 ieee80211com_t *ic;
3742 3741 int err = IWH_SUCCESS;
3743 3742
3744 3743 if (NULL == arg) {
3745 3744 return (EINVAL);
3746 3745 }
3747 3746 sc = (iwh_sc_t *)arg;
3748 3747 ic = &sc->sc_ic;
3749 3748
3750 3749 if (!IEEE80211_ADDR_EQ(ic->ic_macaddr, macaddr)) {
3751 3750 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr);
3752 3751 mutex_enter(&sc->sc_glock);
3753 3752 err = iwh_config(sc);
3754 3753 mutex_exit(&sc->sc_glock);
3755 3754 if (err != IWH_SUCCESS) {
3756 3755 cmn_err(CE_WARN, "iwh_m_unicst(): "
3757 3756 "failed to configure device\n");
3758 3757 goto fail;
3759 3758 }
3760 3759 }
3761 3760
3762 3761 fail:
3763 3762 return (err);
3764 3763 }
3765 3764
3766 3765 /* ARGSUSED */
3767 3766 static int
3768 3767 iwh_m_multicst(void *arg, boolean_t add, const uint8_t *m)
3769 3768 {
3770 3769 return (IWH_SUCCESS);
3771 3770 }
3772 3771
3773 3772 /* ARGSUSED */
3774 3773 static int
3775 3774 iwh_m_promisc(void *arg, boolean_t on)
3776 3775 {
3777 3776 return (IWH_SUCCESS);
3778 3777 }
3779 3778
3780 3779 /*
3781 3780 * kernel thread to deal with exceptional situation
3782 3781 */
3783 3782 static void
3784 3783 iwh_thread(iwh_sc_t *sc)
3785 3784 {
3786 3785 ieee80211com_t *ic = &sc->sc_ic;
3787 3786 clock_t clk;
3788 3787 int err, n = 0, timeout = 0;
3789 3788 uint32_t tmp;
3790 3789 #ifdef DEBUG
3791 3790 int times = 0;
3792 3791 #endif
3793 3792
3794 3793 while (sc->sc_mf_thread_switch) {
3795 3794 tmp = IWH_READ(sc, CSR_GP_CNTRL);
3796 3795 if (tmp & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) {
3797 3796 atomic_and_32(&sc->sc_flags, ~IWH_F_RADIO_OFF);
3798 3797 } else {
3799 3798 atomic_or_32(&sc->sc_flags, IWH_F_RADIO_OFF);
3800 3799 }
3801 3800
3802 3801 /*
3803 3802 * If in SUSPEND or the RF is OFF, do nothing.
3804 3803 */
3805 3804 if (sc->sc_flags & IWH_F_RADIO_OFF) {
3806 3805 delay(drv_usectohz(100000));
3807 3806 continue;
3808 3807 }
3809 3808
3810 3809 /*
3811 3810 * recovery fatal error
3812 3811 */
3813 3812 if (ic->ic_mach &&
3814 3813 (sc->sc_flags & IWH_F_HW_ERR_RECOVER)) {
3815 3814
3816 3815 IWH_DBG((IWH_DEBUG_FW, "iwh_thread(): "
3817 3816 "try to recover fatal hw error: %d\n", times++));
3818 3817
3819 3818 iwh_stop(sc);
3820 3819
3821 3820 if (IWH_CHK_FAST_RECOVER(sc)) {
3822 3821 /*
3823 3822 * save runtime configuration
3824 3823 */
3825 3824 bcopy(&sc->sc_config, &sc->sc_config_save,
3826 3825 sizeof (sc->sc_config));
3827 3826 } else {
3828 3827 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3829 3828 delay(drv_usectohz(2000000 + n*500000));
3830 3829 }
3831 3830
3832 3831 err = iwh_init(sc);
3833 3832 if (err != IWH_SUCCESS) {
3834 3833 n++;
3835 3834 if (n < 20) {
3836 3835 continue;
3837 3836 }
3838 3837 }
3839 3838
3840 3839 n = 0;
3841 3840 if (!err) {
3842 3841 atomic_or_32(&sc->sc_flags, IWH_F_RUNNING);
3843 3842 }
3844 3843
3845 3844
3846 3845 if (!IWH_CHK_FAST_RECOVER(sc) ||
3847 3846 iwh_fast_recover(sc) != IWH_SUCCESS) {
3848 3847 atomic_and_32(&sc->sc_flags,
3849 3848 ~IWH_F_HW_ERR_RECOVER);
3850 3849
3851 3850 delay(drv_usectohz(2000000));
3852 3851 if (sc->sc_ostate != IEEE80211_S_INIT) {
3853 3852 ieee80211_new_state(ic,
3854 3853 IEEE80211_S_SCAN, 0);
3855 3854 }
3856 3855 }
3857 3856 }
3858 3857
3859 3858 if (ic->ic_mach &&
3860 3859 (sc->sc_flags & IWH_F_SCANNING) && sc->sc_scan_pending) {
3861 3860 IWH_DBG((IWH_DEBUG_SCAN, "iwh_thread(): "
3862 3861 "wait for probe response\n"));
3863 3862
3864 3863 sc->sc_scan_pending--;
3865 3864 delay(drv_usectohz(200000));
3866 3865 ieee80211_next_scan(ic);
3867 3866 }
3868 3867
3869 3868 /*
3870 3869 * rate ctl
3871 3870 */
3872 3871 if (ic->ic_mach &&
3873 3872 (sc->sc_flags & IWH_F_RATE_AUTO_CTL)) {
3874 3873 clk = ddi_get_lbolt();
3875 3874 if (clk > sc->sc_clk + drv_usectohz(1000000)) {
3876 3875 iwh_amrr_timeout(sc);
3877 3876 }
3878 3877 }
3879 3878
3880 3879 if ((ic->ic_state == IEEE80211_S_RUN) &&
3881 3880 (ic->ic_beaconmiss++ > 100)) { /* 10 seconds */
3882 3881 cmn_err(CE_WARN, "iwh: beacon missed for 10 seconds\n");
3883 3882 (void) ieee80211_new_state(ic,
3884 3883 IEEE80211_S_INIT, -1);
3885 3884 }
3886 3885
3887 3886 delay(drv_usectohz(100000));
3888 3887
3889 3888 mutex_enter(&sc->sc_mt_lock);
3890 3889 if (sc->sc_tx_timer) {
3891 3890 timeout++;
3892 3891 if (10 == timeout) {
3893 3892 sc->sc_tx_timer--;
3894 3893 if (0 == sc->sc_tx_timer) {
3895 3894 atomic_or_32(&sc->sc_flags,
3896 3895 IWH_F_HW_ERR_RECOVER);
3897 3896 sc->sc_ostate = IEEE80211_S_RUN;
3898 3897 IWH_DBG((IWH_DEBUG_FW, "iwh_thread(): "
3899 3898 "try to recover from "
3900 3899 "send fail\n"));
3901 3900 }
3902 3901 timeout = 0;
3903 3902 }
3904 3903 }
3905 3904 mutex_exit(&sc->sc_mt_lock);
3906 3905 }
3907 3906
3908 3907 mutex_enter(&sc->sc_mt_lock);
3909 3908 sc->sc_mf_thread = NULL;
3910 3909 cv_signal(&sc->sc_mt_cv);
3911 3910 mutex_exit(&sc->sc_mt_lock);
3912 3911 }
3913 3912
3914 3913 /*
3915 3914 * Send a command to the ucode.
3916 3915 */
3917 3916 static int
3918 3917 iwh_cmd(iwh_sc_t *sc, int code, const void *buf, int size, int async)
3919 3918 {
3920 3919 iwh_tx_ring_t *ring = &sc->sc_txq[IWH_CMD_QUEUE_NUM];
3921 3920 iwh_tx_desc_t *desc;
3922 3921 iwh_cmd_t *cmd;
3923 3922
3924 3923 ASSERT(size <= sizeof (cmd->data));
3925 3924 ASSERT(mutex_owned(&sc->sc_glock));
3926 3925
3927 3926 IWH_DBG((IWH_DEBUG_CMD, "iwh_cmd() "
3928 3927 "code[%d]", code));
3929 3928 desc = ring->data[ring->cur].desc;
3930 3929 cmd = ring->data[ring->cur].cmd;
3931 3930
3932 3931 cmd->hdr.type = (uint8_t)code;
3933 3932 cmd->hdr.flags = 0;
3934 3933 cmd->hdr.qid = ring->qid;
3935 3934 cmd->hdr.idx = ring->cur;
3936 3935 bcopy(buf, cmd->data, size);
3937 3936 (void) memset(desc, 0, sizeof (*desc));
3938 3937
3939 3938 desc->val0 = 1 << 24;
3940 3939 desc->pa[0].tb1_addr =
3941 3940 (uint32_t)(ring->data[ring->cur].paddr_cmd & 0xffffffff);
3942 3941 desc->pa[0].val1 = ((4 + size) << 4) & 0xfff0;
3943 3942
3944 3943 if (async) {
3945 3944 sc->sc_cmd_accum++;
3946 3945 }
3947 3946
3948 3947 /*
3949 3948 * kick cmd ring XXX
3950 3949 */
3951 3950 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3952 3951 tfd_offset[ring->cur].val = 8;
3953 3952 if (ring->cur < IWH_MAX_WIN_SIZE) {
3954 3953 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3955 3954 tfd_offset[IWH_QUEUE_SIZE + ring->cur].val = 8;
3956 3955 }
3957 3956 ring->cur = (ring->cur + 1) % ring->count;
3958 3957 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3959 3958
3960 3959 if (async) {
3961 3960 return (IWH_SUCCESS);
3962 3961 } else {
3963 3962 clock_t clk;
3964 3963
3965 3964 clk = ddi_get_lbolt() + drv_usectohz(2000000);
3966 3965 while (sc->sc_cmd_flag != SC_CMD_FLG_DONE) {
3967 3966 if (cv_timedwait(&sc->sc_cmd_cv,
3968 3967 &sc->sc_glock, clk) < 0) {
3969 3968 break;
3970 3969 }
3971 3970 }
3972 3971
3973 3972 if (SC_CMD_FLG_DONE == sc->sc_cmd_flag) {
3974 3973 sc->sc_cmd_flag = SC_CMD_FLG_NONE;
3975 3974 return (IWH_SUCCESS);
3976 3975 } else {
3977 3976 sc->sc_cmd_flag = SC_CMD_FLG_NONE;
3978 3977 return (IWH_FAIL);
3979 3978 }
3980 3979 }
3981 3980 }
3982 3981
3983 3982 /*
3984 3983 * require ucode seting led of NIC
3985 3984 */
3986 3985 static void
3987 3986 iwh_set_led(iwh_sc_t *sc, uint8_t id, uint8_t off, uint8_t on)
3988 3987 {
3989 3988 iwh_led_cmd_t led;
3990 3989
3991 3990 led.interval = LE_32(100000); /* unit: 100ms */
3992 3991 led.id = id;
3993 3992 led.off = off;
3994 3993 led.on = on;
3995 3994
3996 3995 (void) iwh_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1);
3997 3996 }
3998 3997
3999 3998 /*
4000 3999 * necessary setting to NIC before authentication
4001 4000 */
4002 4001 static int
4003 4002 iwh_hw_set_before_auth(iwh_sc_t *sc)
4004 4003 {
4005 4004 ieee80211com_t *ic = &sc->sc_ic;
4006 4005 ieee80211_node_t *in = ic->ic_bss;
4007 4006 int err = IWH_FAIL;
4008 4007
4009 4008 /*
4010 4009 * update adapter's configuration according
4011 4010 * the info of target AP
4012 4011 */
4013 4012 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid);
4014 4013 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan));
4015 4014
4016 4015 if (ic->ic_curmode != IEEE80211_MODE_11NG) {
4017 4016
4018 4017 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0;
4019 4018 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0;
4020 4019 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0;
4021 4020
4022 4021 if (IEEE80211_MODE_11B == ic->ic_curmode) {
4023 4022 sc->sc_config.cck_basic_rates = 0x03;
4024 4023 sc->sc_config.ofdm_basic_rates = 0;
4025 4024 } else if ((in->in_chan != IEEE80211_CHAN_ANYC) &&
4026 4025 (IEEE80211_IS_CHAN_5GHZ(in->in_chan))) {
4027 4026 sc->sc_config.cck_basic_rates = 0;
4028 4027 sc->sc_config.ofdm_basic_rates = 0x15;
4029 4028 } else { /* assume 802.11b/g */
4030 4029 sc->sc_config.cck_basic_rates = 0x0f;
4031 4030 sc->sc_config.ofdm_basic_rates = 0xff;
4032 4031 }
4033 4032 }
4034 4033
4035 4034 sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
4036 4035 RXON_FLG_SHORT_SLOT_MSK);
4037 4036
4038 4037 if (ic->ic_flags & IEEE80211_F_SHSLOT) {
4039 4038 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK);
4040 4039 } else {
4041 4040 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK);
4042 4041 }
4043 4042
4044 4043 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) {
4045 4044 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
4046 4045 } else {
4047 4046 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK);
4048 4047 }
4049 4048
4050 4049 IWH_DBG((IWH_DEBUG_80211, "iwh_hw_set_before_auth(): "
4051 4050 "config chan %d flags %x "
4052 4051 "filter_flags %x cck %x ofdm %x"
4053 4052 " bssid:%02x:%02x:%02x:%02x:%02x:%2x\n",
4054 4053 LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags),
4055 4054 LE_32(sc->sc_config.filter_flags),
4056 4055 sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates,
4057 4056 sc->sc_config.bssid[0], sc->sc_config.bssid[1],
4058 4057 sc->sc_config.bssid[2], sc->sc_config.bssid[3],
4059 4058 sc->sc_config.bssid[4], sc->sc_config.bssid[5]));
4060 4059
4061 4060 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
4062 4061 sizeof (iwh_rxon_cmd_t), 1);
4063 4062 if (err != IWH_SUCCESS) {
4064 4063 cmn_err(CE_WARN, "iwh_hw_set_before_auth(): "
4065 4064 "failed to config chan%d\n", sc->sc_config.chan);
4066 4065 return (err);
4067 4066 }
4068 4067
4069 4068 if ((sc->sc_dev_id != 0x423c) &&
4070 4069 (sc->sc_dev_id != 0x423d)) {
4071 4070 err = iwh_tx_power_table(sc, 1);
4072 4071 if (err != IWH_SUCCESS) {
4073 4072 return (err);
4074 4073 }
4075 4074 }
4076 4075
4077 4076 /*
4078 4077 * add default AP node
4079 4078 */
4080 4079 err = iwh_add_ap_sta(sc);
4081 4080 if (err != IWH_SUCCESS) {
4082 4081 return (err);
4083 4082 }
4084 4083
4085 4084 if ((sc->sc_dev_id != 0x423c) &&
4086 4085 (sc->sc_dev_id != 0x423d)) {
4087 4086 /*
4088 4087 * set up retry rate table for AP node
4089 4088 */
4090 4089 err = iwh_ap_lq(sc);
4091 4090 if (err != IWH_SUCCESS) {
4092 4091 return (err);
4093 4092 }
4094 4093 }
4095 4094
4096 4095 return (err);
4097 4096 }
4098 4097
4099 4098 /*
4100 4099 * Send a scan request(assembly scan cmd) to the firmware.
4101 4100 */
4102 4101 static int
4103 4102 iwh_scan(iwh_sc_t *sc)
4104 4103 {
4105 4104 ieee80211com_t *ic = &sc->sc_ic;
4106 4105 iwh_tx_ring_t *ring = &sc->sc_txq[IWH_CMD_QUEUE_NUM];
4107 4106 iwh_tx_desc_t *desc;
4108 4107 iwh_tx_data_t *data;
4109 4108 iwh_cmd_t *cmd;
4110 4109 iwh_scan_hdr_t *hdr;
4111 4110 iwh_scan_chan_t chan;
4112 4111 struct ieee80211_frame *wh;
4113 4112 ieee80211_node_t *in = ic->ic_bss;
4114 4113 uint8_t essid[IEEE80211_NWID_LEN+1];
4115 4114 struct ieee80211_rateset *rs;
4116 4115 enum ieee80211_phymode mode;
4117 4116 uint8_t *frm;
4118 4117 int i, pktlen, nrates;
4119 4118
4120 4119 data = &ring->data[ring->cur];
4121 4120 desc = data->desc;
4122 4121 cmd = (iwh_cmd_t *)data->dma_data.mem_va;
4123 4122
4124 4123 cmd->hdr.type = REPLY_SCAN_CMD;
4125 4124 cmd->hdr.flags = 0;
4126 4125 cmd->hdr.qid = ring->qid;
4127 4126 cmd->hdr.idx = ring->cur | 0x40;
4128 4127
4129 4128 hdr = (iwh_scan_hdr_t *)cmd->data;
4130 4129 (void) memset(hdr, 0, sizeof (iwh_scan_hdr_t));
4131 4130 hdr->nchan = 1;
4132 4131 hdr->quiet_time = LE_16(50);
4133 4132 hdr->quiet_plcp_th = LE_16(1);
4134 4133
4135 4134 hdr->flags = LE_32(RXON_FLG_BAND_24G_MSK);
4136 4135 hdr->rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK |
4137 4136 (0x7 << RXON_RX_CHAIN_VALID_POS) |
4138 4137 (0x2 << RXON_RX_CHAIN_FORCE_SEL_POS) |
4139 4138 (0x2 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
4140 4139
4141 4140 hdr->tx_cmd.tx_flags = LE_32(TX_CMD_FLG_SEQ_CTL_MSK);
4142 4141 hdr->tx_cmd.sta_id = IWH_BROADCAST_ID;
4143 4142 hdr->tx_cmd.stop_time.life_time = LE_32(0xffffffff);
4144 4143 hdr->tx_cmd.rate.r.rate_n_flags = LE_32(iwh_rate_to_plcp(2));
4145 4144 hdr->tx_cmd.rate.r.rate_n_flags |=
4146 4145 LE_32(RATE_MCS_ANT_B_MSK |RATE_MCS_CCK_MSK);
4147 4146 hdr->direct_scan[0].len = ic->ic_des_esslen;
4148 4147 hdr->direct_scan[0].id = IEEE80211_ELEMID_SSID;
4149 4148
4150 4149 hdr->filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4151 4150 RXON_FILTER_BCON_AWARE_MSK);
4152 4151
4153 4152 if (ic->ic_des_esslen) {
4154 4153 bcopy(ic->ic_des_essid, essid, ic->ic_des_esslen);
4155 4154 essid[ic->ic_des_esslen] = '\0';
4156 4155 IWH_DBG((IWH_DEBUG_SCAN, "iwh_scan(): "
4157 4156 "directed scan %s\n", essid));
4158 4157
4159 4158 bcopy(ic->ic_des_essid, hdr->direct_scan[0].ssid,
4160 4159 ic->ic_des_esslen);
4161 4160 } else {
4162 4161 bzero(hdr->direct_scan[0].ssid,
4163 4162 sizeof (hdr->direct_scan[0].ssid));
4164 4163 }
4165 4164
4166 4165 /*
4167 4166 * a probe request frame is required after the REPLY_SCAN_CMD
4168 4167 */
4169 4168 wh = (struct ieee80211_frame *)(hdr + 1);
4170 4169 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
4171 4170 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
4172 4171 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
4173 4172 (void) memset(wh->i_addr1, 0xff, 6);
4174 4173 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_macaddr);
4175 4174 (void) memset(wh->i_addr3, 0xff, 6);
4176 4175 *(uint16_t *)&wh->i_dur[0] = 0;
4177 4176 *(uint16_t *)&wh->i_seq[0] = 0;
4178 4177
4179 4178 frm = (uint8_t *)(wh + 1);
4180 4179
4181 4180 /*
4182 4181 * essid IE
4183 4182 */
4184 4183 if (in->in_esslen) {
4185 4184 bcopy(in->in_essid, essid, in->in_esslen);
4186 4185 essid[in->in_esslen] = '\0';
4187 4186 IWH_DBG((IWH_DEBUG_SCAN, "iwh_scan(): "
4188 4187 "probe with ESSID %s\n",
4189 4188 essid));
4190 4189 }
4191 4190 *frm++ = IEEE80211_ELEMID_SSID;
4192 4191 *frm++ = in->in_esslen;
4193 4192 bcopy(in->in_essid, frm, in->in_esslen);
4194 4193 frm += in->in_esslen;
4195 4194
4196 4195 mode = ieee80211_chan2mode(ic, ic->ic_curchan);
4197 4196 rs = &ic->ic_sup_rates[mode];
4198 4197
4199 4198 /*
4200 4199 * supported rates IE
4201 4200 */
4202 4201 *frm++ = IEEE80211_ELEMID_RATES;
4203 4202 nrates = rs->ir_nrates;
4204 4203 if (nrates > IEEE80211_RATE_SIZE) {
4205 4204 nrates = IEEE80211_RATE_SIZE;
4206 4205 }
4207 4206
4208 4207 *frm++ = (uint8_t)nrates;
4209 4208 bcopy(rs->ir_rates, frm, nrates);
4210 4209 frm += nrates;
4211 4210
4212 4211 /*
4213 4212 * supported xrates IE
4214 4213 */
4215 4214 if (rs->ir_nrates > IEEE80211_RATE_SIZE) {
4216 4215 nrates = rs->ir_nrates - IEEE80211_RATE_SIZE;
4217 4216 *frm++ = IEEE80211_ELEMID_XRATES;
4218 4217 *frm++ = (uint8_t)nrates;
4219 4218 bcopy(rs->ir_rates + IEEE80211_RATE_SIZE, frm, nrates);
4220 4219 frm += nrates;
4221 4220 }
4222 4221
4223 4222 /*
4224 4223 * optionnal IE (usually for wpa)
4225 4224 */
4226 4225 if (ic->ic_opt_ie != NULL) {
4227 4226 bcopy(ic->ic_opt_ie, frm, ic->ic_opt_ie_len);
4228 4227 frm += ic->ic_opt_ie_len;
4229 4228 }
4230 4229
4231 4230 /* setup length of probe request */
4232 4231 hdr->tx_cmd.len = LE_16(_PTRDIFF(frm, wh));
4233 4232 hdr->len = LE_16(hdr->nchan * sizeof (iwh_scan_chan_t) +
4234 4233 LE_16(hdr->tx_cmd.len) + sizeof (iwh_scan_hdr_t));
4235 4234
4236 4235 /*
4237 4236 * the attribute of the scan channels are required after the probe
4238 4237 * request frame.
4239 4238 */
4240 4239 for (i = 1; i <= hdr->nchan; i++) {
4241 4240 if (ic->ic_des_esslen) {
4242 4241 chan.type = LE_32(3);
4243 4242 } else {
4244 4243 chan.type = LE_32(1);
4245 4244 }
4246 4245
4247 4246 chan.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
4248 4247 chan.tpc.tx_gain = 0x28;
4249 4248 chan.tpc.dsp_atten = 110;
4250 4249 chan.active_dwell = LE_16(50);
4251 4250 chan.passive_dwell = LE_16(120);
4252 4251
4253 4252 bcopy(&chan, frm, sizeof (iwh_scan_chan_t));
4254 4253 frm += sizeof (iwh_scan_chan_t);
4255 4254 }
4256 4255
4257 4256 pktlen = _PTRDIFF(frm, cmd);
4258 4257
4259 4258 (void) memset(desc, 0, sizeof (*desc));
4260 4259 desc->val0 = 1 << 24;
4261 4260 desc->pa[0].tb1_addr =
4262 4261 (uint32_t)(data->dma_data.cookie.dmac_address & 0xffffffff);
4263 4262 desc->pa[0].val1 = (pktlen << 4) & 0xfff0;
4264 4263
4265 4264 /*
4266 4265 * maybe for cmd, filling the byte cnt table is not necessary.
4267 4266 * anyway, we fill it here.
4268 4267 */
4269 4268 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]
4270 4269 .tfd_offset[ring->cur].val = 8;
4271 4270 if (ring->cur < IWH_MAX_WIN_SIZE) {
4272 4271 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
4273 4272 tfd_offset[IWH_QUEUE_SIZE + ring->cur].val = 8;
4274 4273 }
4275 4274
4276 4275 /*
4277 4276 * kick cmd ring
4278 4277 */
4279 4278 ring->cur = (ring->cur + 1) % ring->count;
4280 4279 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4281 4280
4282 4281 return (IWH_SUCCESS);
4283 4282 }
4284 4283
4285 4284 /*
4286 4285 * configure NIC by using ucode commands after loading ucode.
4287 4286 */
4288 4287 static int
4289 4288 iwh_config(iwh_sc_t *sc)
4290 4289 {
4291 4290 ieee80211com_t *ic = &sc->sc_ic;
4292 4291 iwh_powertable_cmd_t powertable;
4293 4292 iwh_bt_cmd_t bt;
4294 4293 iwh_add_sta_t node;
4295 4294 iwh_rem_sta_t rm_sta;
4296 4295 const uint8_t bcast[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
4297 4296 iwh_link_quality_cmd_t link_quality;
4298 4297 int i, err = IWH_FAIL;
4299 4298 uint16_t masks = 0;
4300 4299
4301 4300 /*
4302 4301 * set power mode. Disable power management at present, do it later
4303 4302 */
4304 4303 (void) memset(&powertable, 0, sizeof (powertable));
4305 4304 powertable.flags = LE_16(0x8);
4306 4305 err = iwh_cmd(sc, POWER_TABLE_CMD, &powertable,
4307 4306 sizeof (powertable), 0);
4308 4307 if (err != IWH_SUCCESS) {
4309 4308 cmn_err(CE_WARN, "iwh_config(): "
4310 4309 "failed to set power mode\n");
4311 4310 return (err);
4312 4311 }
4313 4312
4314 4313 /*
4315 4314 * configure bt coexistence
4316 4315 */
4317 4316 (void) memset(&bt, 0, sizeof (bt));
4318 4317 bt.flags = 3;
4319 4318 bt.lead_time = 0xaa;
4320 4319 bt.max_kill = 1;
4321 4320 err = iwh_cmd(sc, REPLY_BT_CONFIG, &bt,
4322 4321 sizeof (bt), 0);
4323 4322 if (err != IWH_SUCCESS) {
4324 4323 cmn_err(CE_WARN, "iwh_config(): "
4325 4324 "failed to configurate bt coexistence\n");
4326 4325 return (err);
4327 4326 }
4328 4327
4329 4328 /*
4330 4329 * configure rxon
4331 4330 */
4332 4331 (void) memset(&sc->sc_config, 0, sizeof (iwh_rxon_cmd_t));
4333 4332 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr);
4334 4333 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr);
4335 4334 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
4336 4335 sc->sc_config.flags = LE_32(RXON_FLG_BAND_24G_MSK);
4337 4336 sc->sc_config.flags &= LE_32(~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4338 4337 RXON_FLG_CHANNEL_MODE_PURE_40_MSK));
4339 4338
4340 4339 switch (ic->ic_opmode) {
4341 4340 case IEEE80211_M_STA:
4342 4341 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS;
4343 4342 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4344 4343 RXON_FILTER_DIS_DECRYPT_MSK |
4345 4344 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
4346 4345 break;
4347 4346
4348 4347 case IEEE80211_M_IBSS:
4349 4348 case IEEE80211_M_AHDEMO:
4350 4349 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
4351 4350
4352 4351 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
4353 4352 sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4354 4353 RXON_FILTER_DIS_DECRYPT_MSK |
4355 4354 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
4356 4355 break;
4357 4356
4358 4357 case IEEE80211_M_HOSTAP:
4359 4358 sc->sc_config.dev_type = RXON_DEV_TYPE_AP;
4360 4359 break;
4361 4360
4362 4361 case IEEE80211_M_MONITOR:
4363 4362 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER;
4364 4363 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4365 4364 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
4366 4365 break;
4367 4366 }
4368 4367
4369 4368 /*
4370 4369 * Support all CCK rates.
4371 4370 */
4372 4371 sc->sc_config.cck_basic_rates = 0x0f;
4373 4372
4374 4373 /*
4375 4374 * Support all OFDM rates.
4376 4375 */
4377 4376 sc->sc_config.ofdm_basic_rates = 0xff;
4378 4377
4379 4378 /*
4380 4379 * Determine HT supported rates.
4381 4380 */
4382 4381 switch (sc->sc_ht_conf.rx_stream_count) {
4383 4382 case 3:
4384 4383 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0xff;
4385 4384 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
4386 4385 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4387 4386 break;
4388 4387 case 2:
4389 4388 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
4390 4389 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4391 4390 break;
4392 4391 case 1:
4393 4392 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4394 4393 break;
4395 4394 default:
4396 4395 cmn_err(CE_WARN, "iwh_config(): "
4397 4396 "RX stream count %d is not in suitable range\n",
4398 4397 sc->sc_ht_conf.rx_stream_count);
4399 4398 return (IWH_FAIL);
4400 4399 }
4401 4400
4402 4401 /*
4403 4402 * set RX chains/antennas.
4404 4403 */
4405 4404 iwh_config_rxon_chain(sc);
4406 4405
4407 4406 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
4408 4407 sizeof (iwh_rxon_cmd_t), 0);
4409 4408 if (err != IWH_SUCCESS) {
4410 4409 cmn_err(CE_WARN, "iwh_config(): "
4411 4410 "failed to set configure command\n");
4412 4411 return (err);
4413 4412 }
4414 4413
4415 4414 /*
4416 4415 * remove all nodes in NIC
4417 4416 */
4418 4417 (void) memset(&rm_sta, 0, sizeof (rm_sta));
4419 4418 rm_sta.num_sta = 1;
4420 4419 bcopy(bcast, rm_sta.addr, 6);
4421 4420
4422 4421 err = iwh_cmd(sc, REPLY_REMOVE_STA, &rm_sta, sizeof (iwh_rem_sta_t), 0);
4423 4422 if (err != IWH_SUCCESS) {
4424 4423 cmn_err(CE_WARN, "iwh_config(): "
4425 4424 "failed to remove broadcast node in hardware.\n");
4426 4425 return (err);
4427 4426 }
4428 4427
4429 4428 if ((sc->sc_dev_id != 0x423c) &&
4430 4429 (sc->sc_dev_id != 0x423d)) {
4431 4430 /*
4432 4431 * configure TX power table
4433 4432 */
4434 4433 err = iwh_tx_power_table(sc, 0);
4435 4434 if (err != IWH_SUCCESS) {
4436 4435 return (err);
4437 4436 }
4438 4437 }
4439 4438
4440 4439 /*
4441 4440 * add broadcast node so that we can send broadcast frame
4442 4441 */
4443 4442 (void) memset(&node, 0, sizeof (node));
4444 4443 (void) memset(node.sta.addr, 0xff, 6);
4445 4444 node.mode = 0;
4446 4445 node.sta.sta_id = IWH_BROADCAST_ID;
4447 4446 node.station_flags = 0;
4448 4447
4449 4448 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0);
4450 4449 if (err != IWH_SUCCESS) {
4451 4450 cmn_err(CE_WARN, "iwh_config(): "
4452 4451 "failed to add broadcast node\n");
4453 4452 return (err);
4454 4453 }
4455 4454
4456 4455 if ((sc->sc_dev_id != 0x423c) &&
4457 4456 (sc->sc_dev_id != 0x423d)) {
4458 4457 /*
4459 4458 * TX_LINK_QUALITY cmd
4460 4459 */
4461 4460 (void) memset(&link_quality, 0, sizeof (link_quality));
4462 4461 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4463 4462 masks |= RATE_MCS_CCK_MSK;
4464 4463 masks |= RATE_MCS_ANT_B_MSK;
4465 4464 masks &= ~RATE_MCS_ANT_A_MSK;
4466 4465 link_quality.rate_n_flags[i] =
4467 4466 LE_32(iwh_rate_to_plcp(2) | masks);
4468 4467 }
4469 4468
4470 4469 link_quality.general_params.single_stream_ant_msk = 2;
4471 4470 link_quality.general_params.dual_stream_ant_msk = 3;
4472 4471 link_quality.agg_params.agg_dis_start_th = 3;
4473 4472 link_quality.agg_params.agg_time_limit = LE_16(4000);
4474 4473 link_quality.sta_id = IWH_BROADCAST_ID;
4475 4474 err = iwh_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
4476 4475 sizeof (link_quality), 0);
4477 4476 if (err != IWH_SUCCESS) {
4478 4477 cmn_err(CE_WARN, "iwh_config(): "
4479 4478 "failed to config link quality table\n");
4480 4479 return (err);
4481 4480 }
4482 4481 }
4483 4482
4484 4483 return (err);
4485 4484 }
4486 4485
4487 4486 /*
4488 4487 * quiesce(9E) entry point.
4489 4488 * This function is called when the system is single-threaded at high
4490 4489 * PIL with preemption disabled. Therefore, this function must not be
4491 4490 * blocked.
4492 4491 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
4493 4492 * DDI_FAILURE indicates an error condition and should almost never happen.
4494 4493 */
4495 4494 static int
4496 4495 iwh_quiesce(dev_info_t *dip)
4497 4496 {
4498 4497 iwh_sc_t *sc;
4499 4498
4500 4499 sc = ddi_get_soft_state(iwh_soft_state_p, ddi_get_instance(dip));
4501 4500 if (sc == NULL) {
4502 4501 return (DDI_FAILURE);
4503 4502 }
4504 4503
4505 4504 #ifdef DEBUG
4506 4505 /*
4507 4506 * by pass any messages, if it's quiesce
4508 4507 */
4509 4508 iwh_dbg_flags = 0;
4510 4509 #endif
4511 4510
4512 4511 /*
4513 4512 * No more blocking is allowed while we are in the
4514 4513 * quiesce(9E) entry point.
4515 4514 */
4516 4515 atomic_or_32(&sc->sc_flags, IWH_F_QUIESCED);
4517 4516
4518 4517 /*
4519 4518 * Disable and mask all interrupts.
4520 4519 */
4521 4520 iwh_stop(sc);
4522 4521
4523 4522 return (DDI_SUCCESS);
4524 4523 }
4525 4524
4526 4525 static void
4527 4526 iwh_stop_master(iwh_sc_t *sc)
4528 4527 {
4529 4528 uint32_t tmp;
4530 4529 int n;
4531 4530
4532 4531 tmp = IWH_READ(sc, CSR_RESET);
4533 4532 IWH_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER);
4534 4533
4535 4534 tmp = IWH_READ(sc, CSR_GP_CNTRL);
4536 4535 if ((tmp & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE) ==
4537 4536 CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE) {
4538 4537 return;
4539 4538 }
4540 4539
4541 4540 for (n = 0; n < 2000; n++) {
4542 4541 if (IWH_READ(sc, CSR_RESET) &
4543 4542 CSR_RESET_REG_FLAG_MASTER_DISABLED) {
4544 4543 break;
4545 4544 }
4546 4545 DELAY(1000);
4547 4546 }
4548 4547
4549 4548 #ifdef DEBUG
4550 4549 if (2000 == n) {
4551 4550 IWH_DBG((IWH_DEBUG_HW, "iwh_stop_master(): "
4552 4551 "timeout waiting for master stop\n"));
4553 4552 }
4554 4553 #endif
4555 4554 }
4556 4555
4557 4556 static int
4558 4557 iwh_power_up(iwh_sc_t *sc)
4559 4558 {
4560 4559 uint32_t tmp;
4561 4560
4562 4561 iwh_mac_access_enter(sc);
4563 4562 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4564 4563 tmp &= ~APMG_PS_CTRL_REG_MSK_POWER_SRC;
4565 4564 tmp |= APMG_PS_CTRL_REG_VAL_POWER_SRC_VMAIN;
4566 4565 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4567 4566 iwh_mac_access_exit(sc);
4568 4567
4569 4568 DELAY(5000);
4570 4569 return (IWH_SUCCESS);
4571 4570 }
4572 4571
4573 4572 /*
4574 4573 * hardware initialization
4575 4574 */
4576 4575 static int
4577 4576 iwh_preinit(iwh_sc_t *sc)
4578 4577 {
4579 4578 int n;
4580 4579 uint8_t vlink;
4581 4580 uint16_t radio_cfg;
4582 4581 uint32_t tmp;
4583 4582
4584 4583 /*
4585 4584 * clear any pending interrupts
4586 4585 */
4587 4586 IWH_WRITE(sc, CSR_INT, 0xffffffff);
4588 4587
4589 4588 tmp = IWH_READ(sc, CSR_GIO_CHICKEN_BITS);
4590 4589 IWH_WRITE(sc, CSR_GIO_CHICKEN_BITS,
4591 4590 tmp | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
4592 4591
4593 4592 tmp = IWH_READ(sc, CSR_ANA_PLL_CFG);
4594 4593 IWH_WRITE(sc, CSR_ANA_PLL_CFG, tmp | IWH_CSR_ANA_PLL_CFG);
4595 4594
4596 4595 tmp = IWH_READ(sc, CSR_GP_CNTRL);
4597 4596 IWH_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4598 4597
4599 4598 /*
4600 4599 * wait for clock ready
4601 4600 */
4602 4601 for (n = 0; n < 1000; n++) {
4603 4602 if (IWH_READ(sc, CSR_GP_CNTRL) &
4604 4603 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY) {
4605 4604 break;
4606 4605 }
4607 4606 DELAY(10);
4608 4607 }
4609 4608
4610 4609 if (1000 == n) {
4611 4610 return (ETIMEDOUT);
4612 4611 }
4613 4612
4614 4613 iwh_mac_access_enter(sc);
4615 4614
4616 4615 iwh_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4617 4616
4618 4617 DELAY(20);
4619 4618 tmp = iwh_reg_read(sc, ALM_APMG_PCIDEV_STT);
4620 4619 iwh_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp |
4621 4620 APMG_DEV_STATE_REG_VAL_L1_ACTIVE_DISABLE);
4622 4621 iwh_mac_access_exit(sc);
4623 4622
4624 4623 radio_cfg = IWH_READ_EEP_SHORT(sc, EEP_SP_RADIO_CONFIGURATION);
4625 4624 if (SP_RADIO_TYPE_MSK(radio_cfg) < SP_RADIO_TYPE_MAX) {
4626 4625 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4627 4626 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4628 4627 tmp | SP_RADIO_TYPE_MSK(radio_cfg) |
4629 4628 SP_RADIO_STEP_MSK(radio_cfg) |
4630 4629 SP_RADIO_DASH_MSK(radio_cfg));
4631 4630 } else {
4632 4631 cmn_err(CE_WARN, "iwh_preinit(): "
4633 4632 "radio configuration information in eeprom is wrong\n");
4634 4633 return (IWH_FAIL);
4635 4634 }
4636 4635
4637 4636
4638 4637 IWH_WRITE(sc, CSR_INT_COALESCING, 512 / 32);
4639 4638
4640 4639 (void) iwh_power_up(sc);
4641 4640
4642 4641 if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) {
4643 4642 tmp = ddi_get32(sc->sc_cfg_handle,
4644 4643 (uint32_t *)(sc->sc_cfg_base + 0xe8));
4645 4644 ddi_put32(sc->sc_cfg_handle,
4646 4645 (uint32_t *)(sc->sc_cfg_base + 0xe8),
4647 4646 tmp & ~(1 << 11));
4648 4647 }
4649 4648
4650 4649 vlink = ddi_get8(sc->sc_cfg_handle,
4651 4650 (uint8_t *)(sc->sc_cfg_base + 0xf0));
4652 4651 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0),
4653 4652 vlink & ~2);
4654 4653
4655 4654 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4656 4655 tmp |= CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
4657 4656 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI;
4658 4657 IWH_WRITE(sc, CSR_SW_VER, tmp);
4659 4658
4660 4659 /*
4661 4660 * make sure power supply on each part of the hardware
4662 4661 */
4663 4662 iwh_mac_access_enter(sc);
4664 4663 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4665 4664 tmp |= APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ;
4666 4665 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4667 4666 DELAY(5);
4668 4667
4669 4668 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4670 4669 tmp &= ~APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ;
4671 4670 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4672 4671 iwh_mac_access_exit(sc);
4673 4672
4674 4673 return (IWH_SUCCESS);
4675 4674 }
4676 4675
4677 4676 /*
4678 4677 * set up semphore flag to own EEPROM
4679 4678 */
4680 4679 static int
4681 4680 iwh_eep_sem_down(iwh_sc_t *sc)
4682 4681 {
4683 4682 int count1, count2;
4684 4683 uint32_t tmp;
4685 4684
4686 4685 for (count1 = 0; count1 < 1000; count1++) {
4687 4686 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4688 4687 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4689 4688 tmp | CSR_HW_IF_CONFIG_REG_EEP_SEM);
4690 4689
4691 4690 for (count2 = 0; count2 < 2; count2++) {
4692 4691 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
4693 4692 CSR_HW_IF_CONFIG_REG_EEP_SEM) {
4694 4693 return (IWH_SUCCESS);
4695 4694 }
4696 4695 DELAY(10000);
4697 4696 }
4698 4697 }
4699 4698
4700 4699 return (IWH_FAIL);
4701 4700 }
4702 4701
4703 4702 /*
4704 4703 * reset semphore flag to release EEPROM
4705 4704 */
4706 4705 static void
4707 4706 iwh_eep_sem_up(iwh_sc_t *sc)
4708 4707 {
4709 4708 uint32_t tmp;
4710 4709
4711 4710 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4712 4711 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4713 4712 tmp & (~CSR_HW_IF_CONFIG_REG_EEP_SEM));
4714 4713 }
4715 4714
4716 4715 /*
4717 4716 * This function read all infomation from eeprom
4718 4717 */
4719 4718 static int
4720 4719 iwh_eep_load(iwh_sc_t *sc)
4721 4720 {
4722 4721 int i, rr;
4723 4722 uint32_t rv, tmp, eep_gp;
4724 4723 uint16_t addr, eep_sz = sizeof (sc->sc_eep_map);
4725 4724 uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map;
4726 4725
4727 4726 /*
4728 4727 * read eeprom gp register in CSR
4729 4728 */
4730 4729 eep_gp = IWH_READ(sc, CSR_EEPROM_GP);
4731 4730 if ((eep_gp & CSR_EEPROM_GP_VALID_MSK) ==
4732 4731 CSR_EEPROM_GP_BAD_SIGNATURE) {
4733 4732 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_eep_load(): "
4734 4733 "not find eeprom\n"));
4735 4734 return (IWH_FAIL);
4736 4735 }
4737 4736
4738 4737 rr = iwh_eep_sem_down(sc);
4739 4738 if (rr != 0) {
4740 4739 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_eep_load(): "
4741 4740 "driver failed to own EEPROM\n"));
4742 4741 return (IWH_FAIL);
4743 4742 }
4744 4743
4745 4744 for (addr = 0; addr < eep_sz; addr += 2) {
4746 4745 IWH_WRITE(sc, CSR_EEPROM_REG, addr<<1);
4747 4746 tmp = IWH_READ(sc, CSR_EEPROM_REG);
4748 4747 IWH_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2));
4749 4748
4750 4749 for (i = 0; i < 10; i++) {
4751 4750 rv = IWH_READ(sc, CSR_EEPROM_REG);
4752 4751 if (rv & 1) {
4753 4752 break;
4754 4753 }
4755 4754 DELAY(10);
4756 4755 }
4757 4756
4758 4757 if (!(rv & 1)) {
4759 4758 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_eep_load(): "
4760 4759 "time out when read eeprome\n"));
4761 4760 iwh_eep_sem_up(sc);
4762 4761 return (IWH_FAIL);
4763 4762 }
4764 4763
4765 4764 eep_p[addr/2] = LE_16(rv >> 16);
4766 4765 }
4767 4766
4768 4767 iwh_eep_sem_up(sc);
4769 4768 return (IWH_SUCCESS);
4770 4769 }
4771 4770
4772 4771 /*
4773 4772 * initialize mac address in ieee80211com_t struct
4774 4773 */
4775 4774 static void
4776 4775 iwh_get_mac_from_eep(iwh_sc_t *sc)
4777 4776 {
4778 4777 ieee80211com_t *ic = &sc->sc_ic;
4779 4778
4780 4779 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->sc_eep_map[EEP_MAC_ADDRESS]);
4781 4780
4782 4781 IWH_DBG((IWH_DEBUG_EEPROM, "iwh_get_mac_from_eep(): "
4783 4782 "mac:%2x:%2x:%2x:%2x:%2x:%2x\n",
4784 4783 ic->ic_macaddr[0], ic->ic_macaddr[1], ic->ic_macaddr[2],
4785 4784 ic->ic_macaddr[3], ic->ic_macaddr[4], ic->ic_macaddr[5]));
4786 4785 }
4787 4786
4788 4787 /*
4789 4788 * main initialization function
4790 4789 */
4791 4790 static int
4792 4791 iwh_init(iwh_sc_t *sc)
4793 4792 {
4794 4793 int err = IWH_FAIL;
4795 4794 clock_t clk;
4796 4795
4797 4796 /*
4798 4797 * release buffer for calibration
4799 4798 */
4800 4799 iwh_release_calib_buffer(sc);
4801 4800
4802 4801 mutex_enter(&sc->sc_glock);
4803 4802 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4804 4803
4805 4804 err = iwh_init_common(sc);
4806 4805 if (err != IWH_SUCCESS) {
4807 4806 mutex_exit(&sc->sc_glock);
4808 4807 return (IWH_FAIL);
4809 4808 }
4810 4809
4811 4810 /*
4812 4811 * backup ucode data part for future use.
4813 4812 */
4814 4813 bcopy(sc->sc_dma_fw_data.mem_va,
4815 4814 sc->sc_dma_fw_data_bak.mem_va,
4816 4815 sc->sc_dma_fw_data.alength);
4817 4816
4818 4817 /* load firmware init segment into NIC */
4819 4818 err = iwh_load_init_firmware(sc);
4820 4819 if (err != IWH_SUCCESS) {
4821 4820 cmn_err(CE_WARN, "iwh_init(): "
4822 4821 "failed to setup init firmware\n");
4823 4822 mutex_exit(&sc->sc_glock);
4824 4823 return (IWH_FAIL);
4825 4824 }
4826 4825
4827 4826 /*
4828 4827 * now press "execute" start running
4829 4828 */
4830 4829 IWH_WRITE(sc, CSR_RESET, 0);
4831 4830
4832 4831 clk = ddi_get_lbolt() + drv_usectohz(1000000);
4833 4832 while (!(sc->sc_flags & IWH_F_FW_INIT)) {
4834 4833 if (cv_timedwait(&sc->sc_ucode_cv,
4835 4834 &sc->sc_glock, clk) < 0) {
4836 4835 break;
4837 4836 }
4838 4837 }
4839 4838
4840 4839 if (!(sc->sc_flags & IWH_F_FW_INIT)) {
4841 4840 cmn_err(CE_WARN, "iwh_init(): "
4842 4841 "failed to process init alive.\n");
4843 4842 mutex_exit(&sc->sc_glock);
4844 4843 return (IWH_FAIL);
4845 4844 }
4846 4845
4847 4846 mutex_exit(&sc->sc_glock);
4848 4847
4849 4848 /*
4850 4849 * stop chipset for initializing chipset again
4851 4850 */
4852 4851 iwh_stop(sc);
4853 4852
4854 4853 mutex_enter(&sc->sc_glock);
4855 4854 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4856 4855
4857 4856 err = iwh_init_common(sc);
4858 4857 if (err != IWH_SUCCESS) {
4859 4858 mutex_exit(&sc->sc_glock);
4860 4859 return (IWH_FAIL);
4861 4860 }
4862 4861
4863 4862 /*
4864 4863 * load firmware run segment into NIC
4865 4864 */
4866 4865 err = iwh_load_run_firmware(sc);
4867 4866 if (err != IWH_SUCCESS) {
4868 4867 cmn_err(CE_WARN, "iwh_init(): "
4869 4868 "failed to setup run firmware\n");
4870 4869 mutex_exit(&sc->sc_glock);
4871 4870 return (IWH_FAIL);
4872 4871 }
4873 4872
4874 4873 /*
4875 4874 * now press "execute" start running
4876 4875 */
4877 4876 IWH_WRITE(sc, CSR_RESET, 0);
4878 4877
4879 4878 clk = ddi_get_lbolt() + drv_usectohz(1000000);
4880 4879 while (!(sc->sc_flags & IWH_F_FW_INIT)) {
4881 4880 if (cv_timedwait(&sc->sc_ucode_cv,
4882 4881 &sc->sc_glock, clk) < 0) {
4883 4882 break;
4884 4883 }
4885 4884 }
4886 4885
4887 4886 if (!(sc->sc_flags & IWH_F_FW_INIT)) {
4888 4887 cmn_err(CE_WARN, "iwh_init(): "
4889 4888 "failed to process runtime alive.\n");
4890 4889 mutex_exit(&sc->sc_glock);
4891 4890 return (IWH_FAIL);
4892 4891 }
4893 4892
4894 4893 mutex_exit(&sc->sc_glock);
4895 4894
4896 4895 DELAY(1000);
4897 4896
4898 4897 mutex_enter(&sc->sc_glock);
4899 4898 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4900 4899
4901 4900 /*
4902 4901 * at this point, the firmware is loaded OK, then config the hardware
4903 4902 * with the ucode API, including rxon, txpower, etc.
4904 4903 */
4905 4904 err = iwh_config(sc);
4906 4905 if (err) {
4907 4906 cmn_err(CE_WARN, "iwh_init(): "
4908 4907 "failed to configure device\n");
4909 4908 mutex_exit(&sc->sc_glock);
4910 4909 return (IWH_FAIL);
4911 4910 }
4912 4911
4913 4912 /*
4914 4913 * at this point, hardware may receive beacons :)
4915 4914 */
4916 4915 mutex_exit(&sc->sc_glock);
4917 4916 return (IWH_SUCCESS);
4918 4917 }
4919 4918
4920 4919 /*
4921 4920 * stop or disable NIC
4922 4921 */
4923 4922 static void
4924 4923 iwh_stop(iwh_sc_t *sc)
4925 4924 {
4926 4925 uint32_t tmp;
4927 4926 int i;
4928 4927
4929 4928 /*
4930 4929 * by pass if it's quiesced
4931 4930 */
4932 4931 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
4933 4932 mutex_enter(&sc->sc_glock);
4934 4933 }
4935 4934
4936 4935 IWH_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4937 4936 /*
4938 4937 * disable interrupts
4939 4938 */
4940 4939 IWH_WRITE(sc, CSR_INT_MASK, 0);
4941 4940 IWH_WRITE(sc, CSR_INT, CSR_INI_SET_MASK);
4942 4941 IWH_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff);
4943 4942
4944 4943 /*
4945 4944 * reset all Tx rings
4946 4945 */
4947 4946 for (i = 0; i < IWH_NUM_QUEUES; i++) {
4948 4947 iwh_reset_tx_ring(sc, &sc->sc_txq[i]);
4949 4948 }
4950 4949
4951 4950 /*
4952 4951 * reset Rx ring
4953 4952 */
4954 4953 iwh_reset_rx_ring(sc);
4955 4954
4956 4955 iwh_mac_access_enter(sc);
4957 4956 iwh_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4958 4957 iwh_mac_access_exit(sc);
4959 4958
4960 4959 DELAY(5);
4961 4960
4962 4961 iwh_stop_master(sc);
4963 4962
4964 4963 mutex_enter(&sc->sc_mt_lock);
4965 4964 sc->sc_tx_timer = 0;
4966 4965 mutex_exit(&sc->sc_mt_lock);
4967 4966
4968 4967 tmp = IWH_READ(sc, CSR_RESET);
4969 4968 IWH_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET);
4970 4969
4971 4970 /*
4972 4971 * by pass if it's quiesced
4973 4972 */
4974 4973 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
4975 4974 mutex_exit(&sc->sc_glock);
4976 4975 }
4977 4976 }
4978 4977
4979 4978 /*
4980 4979 * Naive implementation of the Adaptive Multi Rate Retry algorithm:
4981 4980 * "IEEE 802.11 Rate Adaptation: A Practical Approach"
4982 4981 * Mathieu Lacage, Hossein Manshaei, Thierry Turletti
4983 4982 * INRIA Sophia - Projet Planete
4984 4983 * http://www-sop.inria.fr/rapports/sophia/RR-5208.html
4985 4984 */
4986 4985 #define is_success(amrr) \
4987 4986 ((amrr)->retrycnt < (amrr)->txcnt / 10)
4988 4987 #define is_failure(amrr) \
4989 4988 ((amrr)->retrycnt > (amrr)->txcnt / 3)
4990 4989 #define is_enough(amrr) \
4991 4990 ((amrr)->txcnt > 200)
4992 4991 #define not_very_few(amrr) \
4993 4992 ((amrr)->txcnt > 40)
4994 4993 #define is_min_rate(in) \
4995 4994 (0 == (in)->in_txrate)
4996 4995 #define is_max_rate(in) \
4997 4996 ((in)->in_rates.ir_nrates - 1 == (in)->in_txrate)
4998 4997 #define increase_rate(in) \
4999 4998 ((in)->in_txrate++)
5000 4999 #define decrease_rate(in) \
5001 5000 ((in)->in_txrate--)
5002 5001 #define reset_cnt(amrr) \
5003 5002 { (amrr)->txcnt = (amrr)->retrycnt = 0; }
5004 5003
5005 5004 #define IWH_AMRR_MIN_SUCCESS_THRESHOLD 1
5006 5005 #define IWH_AMRR_MAX_SUCCESS_THRESHOLD 15
5007 5006
5008 5007 static void
5009 5008 iwh_amrr_init(iwh_amrr_t *amrr)
5010 5009 {
5011 5010 amrr->success = 0;
5012 5011 amrr->recovery = 0;
5013 5012 amrr->txcnt = amrr->retrycnt = 0;
5014 5013 amrr->success_threshold = IWH_AMRR_MIN_SUCCESS_THRESHOLD;
5015 5014 amrr->ht_mcs_idx = 0; /* 6Mbps */
5016 5015 }
5017 5016
5018 5017 static void
5019 5018 iwh_amrr_timeout(iwh_sc_t *sc)
5020 5019 {
5021 5020 ieee80211com_t *ic = &sc->sc_ic;
5022 5021
5023 5022 IWH_DBG((IWH_DEBUG_RATECTL, "iwh_amrr_timeout(): "
5024 5023 "enter\n"));
5025 5024
5026 5025 if (IEEE80211_M_STA == ic->ic_opmode) {
5027 5026 iwh_amrr_ratectl(NULL, ic->ic_bss);
5028 5027 } else {
5029 5028 ieee80211_iterate_nodes(&ic->ic_sta, iwh_amrr_ratectl, NULL);
5030 5029 }
5031 5030
5032 5031 sc->sc_clk = ddi_get_lbolt();
5033 5032 }
5034 5033
5035 5034 static int
5036 5035 iwh_is_max_rate(ieee80211_node_t *in)
5037 5036 {
5038 5037 int i;
5039 5038 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5040 5039 uint8_t r = (uint8_t)amrr->ht_mcs_idx;
5041 5040 ieee80211com_t *ic = in->in_ic;
5042 5041 iwh_sc_t *sc = (iwh_sc_t *)ic;
5043 5042
5044 5043 if (in->in_flags & IEEE80211_NODE_HT) {
5045 5044 for (i = in->in_htrates.rs_nrates - 1; i >= 0; i--) {
5046 5045 r = in->in_htrates.rs_rates[i] &
5047 5046 IEEE80211_RATE_VAL;
5048 5047 if (sc->sc_ht_conf.tx_support_mcs[r/8] &
5049 5048 (1 << (r%8))) {
5050 5049 break;
5051 5050 }
5052 5051 }
5053 5052
5054 5053 return (r == (uint8_t)amrr->ht_mcs_idx);
5055 5054 } else {
5056 5055 return (is_max_rate(in));
5057 5056 }
5058 5057 }
5059 5058
5060 5059 static int
5061 5060 iwh_is_min_rate(ieee80211_node_t *in)
5062 5061 {
5063 5062 int i;
5064 5063 uint8_t r = 0;
5065 5064 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5066 5065 ieee80211com_t *ic = in->in_ic;
5067 5066 iwh_sc_t *sc = (iwh_sc_t *)ic;
5068 5067
5069 5068 if (in->in_flags & IEEE80211_NODE_HT) {
5070 5069 for (i = 0; i < in->in_htrates.rs_nrates; i++) {
5071 5070 r = in->in_htrates.rs_rates[i] &
5072 5071 IEEE80211_RATE_VAL;
5073 5072 if (sc->sc_ht_conf.tx_support_mcs[r/8] &
5074 5073 (1 << (r%8))) {
5075 5074 break;
5076 5075 }
5077 5076 }
5078 5077
5079 5078 return (r == (uint8_t)amrr->ht_mcs_idx);
5080 5079 } else {
5081 5080 return (is_min_rate(in));
5082 5081 }
5083 5082 }
5084 5083
5085 5084 static void
5086 5085 iwh_increase_rate(ieee80211_node_t *in)
5087 5086 {
5088 5087 int i;
5089 5088 uint8_t r;
5090 5089 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5091 5090 ieee80211com_t *ic = in->in_ic;
5092 5091 iwh_sc_t *sc = (iwh_sc_t *)ic;
5093 5092
5094 5093 if (in->in_flags & IEEE80211_NODE_HT) {
5095 5094 again:
5096 5095 amrr->ht_mcs_idx++;
5097 5096
5098 5097 for (i = 0; i < in->in_htrates.rs_nrates; i++) {
5099 5098 r = in->in_htrates.rs_rates[i] &
5100 5099 IEEE80211_RATE_VAL;
5101 5100 if ((r == (uint8_t)amrr->ht_mcs_idx) &&
5102 5101 (sc->sc_ht_conf.tx_support_mcs[r/8] &
5103 5102 (1 << (r%8)))) {
5104 5103 break;
5105 5104 }
5106 5105 }
5107 5106
5108 5107 if (i >= in->in_htrates.rs_nrates) {
5109 5108 goto again;
5110 5109 }
5111 5110 } else {
5112 5111 increase_rate(in);
5113 5112 }
5114 5113 }
5115 5114
5116 5115 static void
5117 5116 iwh_decrease_rate(ieee80211_node_t *in)
5118 5117 {
5119 5118 int i;
5120 5119 uint8_t r;
5121 5120 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5122 5121 ieee80211com_t *ic = in->in_ic;
5123 5122 iwh_sc_t *sc = (iwh_sc_t *)ic;
5124 5123
5125 5124 if (in->in_flags & IEEE80211_NODE_HT) {
5126 5125 again:
5127 5126 amrr->ht_mcs_idx--;
5128 5127
5129 5128 for (i = 0; i < in->in_htrates.rs_nrates; i++) {
5130 5129 r = in->in_htrates.rs_rates[i] &
5131 5130 IEEE80211_RATE_VAL;
5132 5131 if ((r == (uint8_t)amrr->ht_mcs_idx) &&
5133 5132 (sc->sc_ht_conf.tx_support_mcs[r/8] &
5134 5133 (1 << (r%8)))) {
5135 5134 break;
5136 5135 }
5137 5136 }
5138 5137
5139 5138 if (i >= in->in_htrates.rs_nrates) {
5140 5139 goto again;
5141 5140 }
5142 5141 } else {
5143 5142 decrease_rate(in);
5144 5143 }
5145 5144 }
5146 5145
5147 5146 /* ARGSUSED */
5148 5147 static void
5149 5148 iwh_amrr_ratectl(void *arg, ieee80211_node_t *in)
5150 5149 {
5151 5150 iwh_amrr_t *amrr = (iwh_amrr_t *)in;
5152 5151 int need_change = 0;
5153 5152
5154 5153 if (is_success(amrr) && is_enough(amrr)) {
5155 5154 amrr->success++;
5156 5155 if (amrr->success >= amrr->success_threshold &&
5157 5156 !iwh_is_max_rate(in)) {
5158 5157 amrr->recovery = 1;
5159 5158 amrr->success = 0;
5160 5159 iwh_increase_rate(in);
5161 5160 IWH_DBG((IWH_DEBUG_RATECTL, "iwh_amrr_ratectl(): "
5162 5161 "AMRR increasing rate %d "
5163 5162 "(txcnt=%d retrycnt=%d), mcs_idx=%d\n",
5164 5163 in->in_txrate, amrr->txcnt,
5165 5164 amrr->retrycnt, amrr->ht_mcs_idx));
5166 5165 need_change = 1;
5167 5166 } else {
5168 5167 amrr->recovery = 0;
5169 5168 }
5170 5169 } else if (not_very_few(amrr) && is_failure(amrr)) {
5171 5170 amrr->success = 0;
5172 5171 if (!iwh_is_min_rate(in)) {
5173 5172 if (amrr->recovery) {
5174 5173 amrr->success_threshold++;
5175 5174 if (amrr->success_threshold >
5176 5175 IWH_AMRR_MAX_SUCCESS_THRESHOLD) {
5177 5176 amrr->success_threshold =
5178 5177 IWH_AMRR_MAX_SUCCESS_THRESHOLD;
5179 5178 }
5180 5179 } else {
5181 5180 amrr->success_threshold =
5182 5181 IWH_AMRR_MIN_SUCCESS_THRESHOLD;
5183 5182 }
5184 5183 iwh_decrease_rate(in);
5185 5184 IWH_DBG((IWH_DEBUG_RATECTL, "iwh_amrr_ratectl(): "
5186 5185 "AMRR decreasing rate %d "
5187 5186 "(txcnt=%d retrycnt=%d), mcs_idx=%d\n",
5188 5187 in->in_txrate, amrr->txcnt,
5189 5188 amrr->retrycnt, amrr->ht_mcs_idx));
5190 5189 need_change = 1;
5191 5190 }
5192 5191 amrr->recovery = 0; /* paper is incorrect */
5193 5192 }
5194 5193
5195 5194 if (is_enough(amrr) || need_change) {
5196 5195 reset_cnt(amrr);
5197 5196 }
5198 5197 }
5199 5198
5200 5199 /*
5201 5200 * translate indirect address in eeprom to direct address
5202 5201 * in eeprom and return address of entry whos indirect address
5203 5202 * is indi_addr
5204 5203 */
5205 5204 static uint8_t *
5206 5205 iwh_eep_addr_trans(iwh_sc_t *sc, uint32_t indi_addr)
5207 5206 {
5208 5207 uint32_t di_addr;
5209 5208 uint16_t temp;
5210 5209
5211 5210 if (!(indi_addr & INDIRECT_ADDRESS)) {
5212 5211 di_addr = indi_addr;
5213 5212 return (&sc->sc_eep_map[di_addr]);
5214 5213 }
5215 5214
5216 5215 switch (indi_addr & INDIRECT_TYPE_MSK) {
5217 5216 case INDIRECT_GENERAL:
5218 5217 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_GENERAL);
5219 5218 break;
5220 5219
5221 5220 case INDIRECT_HOST:
5222 5221 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_HOST);
5223 5222 break;
5224 5223
5225 5224 case INDIRECT_REGULATORY:
5226 5225 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_REGULATORY);
5227 5226 break;
5228 5227
5229 5228 case INDIRECT_CALIBRATION:
5230 5229 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_CALIBRATION);
5231 5230 break;
5232 5231
5233 5232 case INDIRECT_PROCESS_ADJST:
5234 5233 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_PROCESS_ADJST);
5235 5234 break;
5236 5235
5237 5236 case INDIRECT_OTHERS:
5238 5237 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_OTHERS);
5239 5238 break;
5240 5239
5241 5240 default:
5242 5241 temp = 0;
5243 5242 cmn_err(CE_WARN, "iwh_eep_addr_trans(): "
5244 5243 "incorrect indirect eeprom address.\n");
5245 5244 break;
5246 5245 }
5247 5246
5248 5247 di_addr = (indi_addr & ADDRESS_MSK) + (temp << 1);
5249 5248
5250 5249 return (&sc->sc_eep_map[di_addr]);
5251 5250 }
5252 5251
5253 5252 /*
5254 5253 * loade a section of ucode into NIC
5255 5254 */
5256 5255 static int
5257 5256 iwh_put_seg_fw(iwh_sc_t *sc, uint32_t addr_s, uint32_t addr_d, uint32_t len)
5258 5257 {
5259 5258
5260 5259 iwh_mac_access_enter(sc);
5261 5260
5262 5261 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(IWH_FH_SRVC_CHNL),
5263 5262 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
5264 5263
5265 5264 IWH_WRITE(sc, IWH_FH_SRVC_CHNL_SRAM_ADDR_REG(IWH_FH_SRVC_CHNL), addr_d);
5266 5265
5267 5266 IWH_WRITE(sc, IWH_FH_TFDIB_CTRL0_REG(IWH_FH_SRVC_CHNL),
5268 5267 (addr_s & FH_MEM_TFDIB_DRAM_ADDR_LSB_MASK));
5269 5268
5270 5269 IWH_WRITE(sc, IWH_FH_TFDIB_CTRL1_REG(IWH_FH_SRVC_CHNL), len);
5271 5270
5272 5271 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_BUF_STS_REG(IWH_FH_SRVC_CHNL),
5273 5272 (1 << IWH_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
5274 5273 (1 << IWH_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
5275 5274 IWH_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
5276 5275
5277 5276 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(IWH_FH_SRVC_CHNL),
5278 5277 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5279 5278 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
5280 5279 IWH_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
5281 5280
5282 5281 iwh_mac_access_exit(sc);
5283 5282
5284 5283 return (IWH_SUCCESS);
5285 5284 }
5286 5285
5287 5286 /*
5288 5287 * necessary setting during alive notification
5289 5288 */
5290 5289 static int
5291 5290 iwh_alive_common(iwh_sc_t *sc)
5292 5291 {
5293 5292 uint32_t base;
5294 5293 uint32_t i;
5295 5294 iwh_wimax_coex_cmd_t w_cmd;
5296 5295 iwh_calibration_crystal_cmd_t c_cmd;
5297 5296 uint32_t rv = IWH_FAIL;
5298 5297
5299 5298 /*
5300 5299 * initialize SCD related registers to make TX work.
5301 5300 */
5302 5301 iwh_mac_access_enter(sc);
5303 5302
5304 5303 /*
5305 5304 * read sram address of data base.
5306 5305 */
5307 5306 sc->sc_scd_base = iwh_reg_read(sc, IWH_SCD_SRAM_BASE_ADDR);
5308 5307
5309 5308 for (base = sc->sc_scd_base + IWH_SCD_CONTEXT_DATA_OFFSET;
5310 5309 base < sc->sc_scd_base + IWH_SCD_TX_STTS_BITMAP_OFFSET;
5311 5310 base += 4) {
5312 5311 iwh_mem_write(sc, base, 0);
5313 5312 }
5314 5313
5315 5314 for (; base < sc->sc_scd_base + IWH_SCD_TRANSLATE_TBL_OFFSET;
5316 5315 base += 4) {
5317 5316 iwh_mem_write(sc, base, 0);
5318 5317 }
5319 5318
5320 5319 for (i = 0; i < sizeof (uint16_t) * IWH_NUM_QUEUES; i += 4) {
5321 5320 iwh_mem_write(sc, base + i, 0);
5322 5321 }
5323 5322
5324 5323 iwh_reg_write(sc, IWH_SCD_DRAM_BASE_ADDR,
5325 5324 sc->sc_dma_sh.cookie.dmac_address >> 10);
5326 5325
5327 5326 iwh_reg_write(sc, IWH_SCD_QUEUECHAIN_SEL,
5328 5327 IWH_SCD_QUEUECHAIN_SEL_ALL(IWH_NUM_QUEUES));
5329 5328
5330 5329 iwh_reg_write(sc, IWH_SCD_AGGR_SEL, 0);
5331 5330
5332 5331 for (i = 0; i < IWH_NUM_QUEUES; i++) {
5333 5332 iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(i), 0);
5334 5333 IWH_WRITE(sc, HBUS_TARG_WRPTR, 0 | (i << 8));
5335 5334 iwh_mem_write(sc, sc->sc_scd_base +
5336 5335 IWH_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
5337 5336 iwh_mem_write(sc, sc->sc_scd_base +
5338 5337 IWH_SCD_CONTEXT_QUEUE_OFFSET(i) +
5339 5338 sizeof (uint32_t),
5340 5339 ((SCD_WIN_SIZE << IWH_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
5341 5340 IWH_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
5342 5341 ((SCD_FRAME_LIMIT <<
5343 5342 IWH_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5344 5343 IWH_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
5345 5344 }
5346 5345
5347 5346 iwh_reg_write(sc, IWH_SCD_INTERRUPT_MASK, (1 << IWH_NUM_QUEUES) - 1);
5348 5347
5349 5348 iwh_reg_write(sc, (IWH_SCD_BASE + 0x10),
5350 5349 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
5351 5350
5352 5351 IWH_WRITE(sc, HBUS_TARG_WRPTR, (IWH_CMD_QUEUE_NUM << 8));
5353 5352 iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(IWH_CMD_QUEUE_NUM), 0);
5354 5353
5355 5354 /*
5356 5355 * queue 0-7 map to FIFO 0-7 and
5357 5356 * all queues work under FIFO mode(none-scheduler_ack)
5358 5357 */
5359 5358 for (i = 0; i < 4; i++) {
5360 5359 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(i),
5361 5360 (1 << IWH_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
5362 5361 ((3-i) << IWH_SCD_QUEUE_STTS_REG_POS_TXF) |
5363 5362 (1 << IWH_SCD_QUEUE_STTS_REG_POS_WSL) |
5364 5363 IWH_SCD_QUEUE_STTS_REG_MSK);
5365 5364 }
5366 5365
5367 5366 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(IWH_CMD_QUEUE_NUM),
5368 5367 (1 << IWH_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
5369 5368 (IWH_CMD_FIFO_NUM << IWH_SCD_QUEUE_STTS_REG_POS_TXF) |
5370 5369 (1 << IWH_SCD_QUEUE_STTS_REG_POS_WSL) |
5371 5370 IWH_SCD_QUEUE_STTS_REG_MSK);
5372 5371
5373 5372 for (i = 5; i < 7; i++) {
5374 5373 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(i),
5375 5374 (1 << IWH_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
5376 5375 (i << IWH_SCD_QUEUE_STTS_REG_POS_TXF) |
5377 5376 (1 << IWH_SCD_QUEUE_STTS_REG_POS_WSL) |
5378 5377 IWH_SCD_QUEUE_STTS_REG_MSK);
5379 5378 }
5380 5379
5381 5380 iwh_mac_access_exit(sc);
5382 5381
5383 5382 (void) memset(&w_cmd, 0, sizeof (w_cmd));
5384 5383
5385 5384 rv = iwh_cmd(sc, COEX_PRIORITY_TABLE_CMD, &w_cmd, sizeof (w_cmd), 1);
5386 5385 if (rv != IWH_SUCCESS) {
5387 5386 cmn_err(CE_WARN, "iwh_alive_common(): "
5388 5387 "failed to send wimax coexist command.\n");
5389 5388 return (rv);
5390 5389 }
5391 5390
5392 5391 if ((sc->sc_dev_id != 0x423c) &&
5393 5392 (sc->sc_dev_id != 0x423d)) {
5394 5393 (void) memset(&c_cmd, 0, sizeof (c_cmd));
5395 5394
5396 5395 c_cmd.opCode = PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
5397 5396 c_cmd.data.cap_pin1 = LE_16(sc->sc_eep_calib->xtal_calib[0]);
5398 5397 c_cmd.data.cap_pin2 = LE_16(sc->sc_eep_calib->xtal_calib[1]);
5399 5398
5400 5399 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
5401 5400 &c_cmd, sizeof (c_cmd), 1);
5402 5401 if (rv != IWH_SUCCESS) {
5403 5402 cmn_err(CE_WARN, "iwh_alive_common(): "
5404 5403 "failed to send crystal"
5405 5404 "frq calibration command.\n");
5406 5405 return (rv);
5407 5406 }
5408 5407
5409 5408 /*
5410 5409 * make sure crystal frequency calibration ready
5411 5410 * before next operations.
5412 5411 */
5413 5412 DELAY(1000);
5414 5413 }
5415 5414
5416 5415 return (IWH_SUCCESS);
5417 5416 }
5418 5417
5419 5418 /*
5420 5419 * save results of calibration from ucode
5421 5420 */
5422 5421 static void
5423 5422 iwh_save_calib_result(iwh_sc_t *sc, iwh_rx_desc_t *desc)
5424 5423 {
5425 5424 struct iwh_calib_results *res_p = &sc->sc_calib_results;
5426 5425 struct iwh_calib_hdr *calib_hdr = (struct iwh_calib_hdr *)(desc + 1);
5427 5426 int len = LE_32(desc->len);
5428 5427
5429 5428 /*
5430 5429 * ensure the size of buffer is not too big
5431 5430 */
5432 5431 len = (len & FH_RSCSR_FRAME_SIZE_MASK) - 4;
5433 5432
5434 5433 switch (calib_hdr->op_code) {
5435 5434 case PHY_CALIBRATE_LO_CMD:
5436 5435 if (NULL == res_p->lo_res) {
5437 5436 res_p->lo_res = kmem_alloc(len, KM_NOSLEEP);
5438 5437 }
5439 5438
5440 5439 if (NULL == res_p->lo_res) {
5441 5440 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5442 5441 "failed to allocate memory.\n");
5443 5442 return;
5444 5443 }
5445 5444
5446 5445 res_p->lo_res_len = len;
5447 5446 bcopy(calib_hdr, res_p->lo_res, len);
5448 5447 break;
5449 5448
5450 5449 case PHY_CALIBRATE_TX_IQ_CMD:
5451 5450 if (NULL == res_p->tx_iq_res) {
5452 5451 res_p->tx_iq_res = kmem_alloc(len, KM_NOSLEEP);
5453 5452 }
5454 5453
5455 5454 if (NULL == res_p->tx_iq_res) {
5456 5455 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5457 5456 "failed to allocate memory.\n");
5458 5457 return;
5459 5458 }
5460 5459
5461 5460 res_p->tx_iq_res_len = len;
5462 5461 bcopy(calib_hdr, res_p->tx_iq_res, len);
5463 5462 break;
5464 5463
5465 5464 case PHY_CALIBRATE_TX_IQ_PERD_CMD:
5466 5465 if (NULL == res_p->tx_iq_perd_res) {
5467 5466 res_p->tx_iq_perd_res = kmem_alloc(len, KM_NOSLEEP);
5468 5467 }
5469 5468
5470 5469 if (NULL == res_p->tx_iq_perd_res) {
5471 5470 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5472 5471 "failed to allocate memory.\n");
5473 5472 return;
5474 5473 }
5475 5474
5476 5475 res_p->tx_iq_perd_res_len = len;
5477 5476 bcopy(calib_hdr, res_p->tx_iq_perd_res, len);
5478 5477 break;
5479 5478
5480 5479 case PHY_CALIBRATE_DC_CMD:
5481 5480 if (NULL == res_p->dc_res) {
5482 5481 res_p->dc_res = kmem_alloc(len, KM_NOSLEEP);
5483 5482 }
5484 5483
5485 5484 if (NULL == res_p->dc_res) {
5486 5485 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5487 5486 "failed to allocate memory.\n");
5488 5487 return;
5489 5488 }
5490 5489
5491 5490 res_p->dc_res_len = len;
5492 5491 bcopy(calib_hdr, res_p->dc_res, len);
5493 5492 break;
5494 5493
5495 5494 case PHY_CALIBRATE_BASE_BAND_CMD:
5496 5495 if (NULL == res_p->base_band_res) {
5497 5496 res_p->base_band_res = kmem_alloc(len, KM_NOSLEEP);
5498 5497 }
5499 5498
5500 5499 if (NULL == res_p->base_band_res) {
5501 5500 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5502 5501 "failed to allocate memory.\n");
5503 5502 return;
5504 5503 }
5505 5504
5506 5505 res_p->base_band_res_len = len;
5507 5506 bcopy(calib_hdr, res_p->base_band_res, len);
5508 5507 break;
5509 5508
5510 5509 default:
5511 5510 cmn_err(CE_WARN, "iwh_save_calib_result(): "
5512 5511 "incorrect calibration type(%d).\n", calib_hdr->op_code);
5513 5512 break;
5514 5513 }
5515 5514
5516 5515 }
5517 5516
5518 5517 /*
5519 5518 * configure TX pwoer table
5520 5519 */
5521 5520 static int
5522 5521 iwh_tx_power_table(iwh_sc_t *sc, int async)
5523 5522 {
5524 5523 iwh_tx_power_table_cmd_t txpower;
5525 5524 int i, err = IWH_FAIL;
5526 5525
5527 5526 (void) memset(&txpower, 0, sizeof (txpower));
5528 5527
5529 5528 txpower.band = 1; /* for 2.4G */
5530 5529 txpower.channel = (uint8_t)LE_16(sc->sc_config.chan);
5531 5530 txpower.pa_measurements = 1;
5532 5531 txpower.max_mcs = 23;
5533 5532
5534 5533 for (i = 0; i < 24; i++) {
5535 5534 txpower.db.ht_ofdm_power[i].s.radio_tx_gain[0] = 0x16;
5536 5535 txpower.db.ht_ofdm_power[i].s.radio_tx_gain[1] = 0x16;
5537 5536 txpower.db.ht_ofdm_power[i].s.radio_tx_gain[2] = 0x16;
5538 5537 txpower.db.ht_ofdm_power[i].s.dsp_predis_atten[0] = 0x6E;
5539 5538 txpower.db.ht_ofdm_power[i].s.dsp_predis_atten[1] = 0x6E;
5540 5539 txpower.db.ht_ofdm_power[i].s.dsp_predis_atten[2] = 0x6E;
5541 5540 }
5542 5541
5543 5542 for (i = 0; i < 2; i++) {
5544 5543 txpower.db.cck_power[i].s.radio_tx_gain[0] = 0x16;
5545 5544 txpower.db.cck_power[i].s.radio_tx_gain[1] = 0x16;
5546 5545 txpower.db.cck_power[i].s.radio_tx_gain[2] = 0x16;
5547 5546 txpower.db.cck_power[i].s.dsp_predis_atten[0] = 0x6E;
5548 5547 txpower.db.cck_power[i].s.dsp_predis_atten[1] = 0x6E;
5549 5548 txpower.db.cck_power[i].s.dsp_predis_atten[2] = 0x6E;
5550 5549 }
5551 5550
5552 5551 err = iwh_cmd(sc, REPLY_TX_PWR_TABLE_CMD, &txpower,
5553 5552 sizeof (txpower), async);
5554 5553 if (err != IWH_SUCCESS) {
5555 5554 cmn_err(CE_WARN, "iwh_tx_power_table(): "
5556 5555 "failed to set tx power table.\n");
5557 5556 return (err);
5558 5557 }
5559 5558
5560 5559 return (err);
5561 5560 }
5562 5561
5563 5562 static void
5564 5563 iwh_release_calib_buffer(iwh_sc_t *sc)
5565 5564 {
5566 5565 if (sc->sc_calib_results.lo_res != NULL) {
5567 5566 kmem_free(sc->sc_calib_results.lo_res,
5568 5567 sc->sc_calib_results.lo_res_len);
5569 5568 sc->sc_calib_results.lo_res = NULL;
5570 5569 }
5571 5570
5572 5571 if (sc->sc_calib_results.tx_iq_res != NULL) {
5573 5572 kmem_free(sc->sc_calib_results.tx_iq_res,
5574 5573 sc->sc_calib_results.tx_iq_res_len);
5575 5574 sc->sc_calib_results.tx_iq_res = NULL;
5576 5575 }
5577 5576
5578 5577 if (sc->sc_calib_results.tx_iq_perd_res != NULL) {
5579 5578 kmem_free(sc->sc_calib_results.tx_iq_perd_res,
5580 5579 sc->sc_calib_results.tx_iq_perd_res_len);
5581 5580 sc->sc_calib_results.tx_iq_perd_res = NULL;
5582 5581 }
5583 5582
5584 5583 if (sc->sc_calib_results.dc_res != NULL) {
5585 5584 kmem_free(sc->sc_calib_results.dc_res,
5586 5585 sc->sc_calib_results.dc_res_len);
5587 5586 sc->sc_calib_results.dc_res = NULL;
5588 5587 }
5589 5588
5590 5589 if (sc->sc_calib_results.base_band_res != NULL) {
5591 5590 kmem_free(sc->sc_calib_results.base_band_res,
5592 5591 sc->sc_calib_results.base_band_res_len);
5593 5592 sc->sc_calib_results.base_band_res = NULL;
5594 5593 }
5595 5594 }
5596 5595
5597 5596 /*
5598 5597 * common section of intialization
5599 5598 */
5600 5599 static int
5601 5600 iwh_init_common(iwh_sc_t *sc)
5602 5601 {
5603 5602 int32_t qid;
5604 5603 uint32_t tmp;
5605 5604
5606 5605 if (iwh_reset_hw(sc) != IWH_SUCCESS) {
5607 5606 cmn_err(CE_WARN, "iwh_init_common(): "
5608 5607 "failed to reset hardware\n");
5609 5608 return (IWH_FAIL);
5610 5609 }
5611 5610
5612 5611 (void) iwh_preinit(sc);
5613 5612
5614 5613 tmp = IWH_READ(sc, CSR_GP_CNTRL);
5615 5614 if (!(tmp & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) {
5616 5615 cmn_err(CE_NOTE, "iwh_init_common(): "
5617 5616 "radio transmitter is off\n");
5618 5617 return (IWH_FAIL);
5619 5618 }
5620 5619
5621 5620 /*
5622 5621 * init Rx ring
5623 5622 */
5624 5623 iwh_mac_access_enter(sc);
5625 5624 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
5626 5625
5627 5626 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
5628 5627 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
5629 5628 sc->sc_rxq.dma_desc.cookie.dmac_address >> 8);
5630 5629
5631 5630 IWH_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG,
5632 5631 ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address +
5633 5632 offsetof(struct iwh_shared, val0)) >> 4));
5634 5633
5635 5634 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG,
5636 5635 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
5637 5636 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
5638 5637 IWH_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K |
5639 5638 (RX_QUEUE_SIZE_LOG <<
5640 5639 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
5641 5640 iwh_mac_access_exit(sc);
5642 5641 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG,
5643 5642 (RX_QUEUE_SIZE - 1) & ~0x7);
5644 5643
5645 5644 /*
5646 5645 * init Tx rings
5647 5646 */
5648 5647 iwh_mac_access_enter(sc);
5649 5648 iwh_reg_write(sc, IWH_SCD_TXFACT, 0);
5650 5649
5651 5650 /*
5652 5651 * keep warm page
5653 5652 */
5654 5653 IWH_WRITE(sc, IWH_FH_KW_MEM_ADDR_REG,
5655 5654 sc->sc_dma_kw.cookie.dmac_address >> 4);
5656 5655
5657 5656 for (qid = 0; qid < IWH_NUM_QUEUES; qid++) {
5658 5657 IWH_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),
5659 5658 sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8);
5660 5659 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(qid),
5661 5660 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5662 5661 IWH_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
5663 5662 }
5664 5663
5665 5664 iwh_mac_access_exit(sc);
5666 5665
5667 5666 /*
5668 5667 * clear "radio off" and "disable command" bits
5669 5668 */
5670 5669 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5671 5670 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR,
5672 5671 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5673 5672
5674 5673 /*
5675 5674 * clear any pending interrupts
5676 5675 */
5677 5676 IWH_WRITE(sc, CSR_INT, 0xffffffff);
5678 5677
5679 5678 /*
5680 5679 * enable interrupts
5681 5680 */
5682 5681 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
5683 5682
5684 5683 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5685 5684 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5686 5685
5687 5686 return (IWH_SUCCESS);
5688 5687 }
5689 5688
5690 5689 static int
5691 5690 iwh_fast_recover(iwh_sc_t *sc)
5692 5691 {
5693 5692 ieee80211com_t *ic = &sc->sc_ic;
5694 5693 int err = IWH_FAIL;
5695 5694
5696 5695 mutex_enter(&sc->sc_glock);
5697 5696
5698 5697 /*
5699 5698 * restore runtime configuration
5700 5699 */
5701 5700 bcopy(&sc->sc_config_save, &sc->sc_config,
5702 5701 sizeof (sc->sc_config));
5703 5702
5704 5703 sc->sc_config.assoc_id = 0;
5705 5704 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
5706 5705
5707 5706 if ((err = iwh_hw_set_before_auth(sc)) != IWH_SUCCESS) {
5708 5707 cmn_err(CE_WARN, "iwh_fast_recover(): "
5709 5708 "could not setup authentication\n");
5710 5709 mutex_exit(&sc->sc_glock);
5711 5710 return (err);
5712 5711 }
5713 5712
5714 5713 bcopy(&sc->sc_config_save, &sc->sc_config,
5715 5714 sizeof (sc->sc_config));
5716 5715
5717 5716 /*
5718 5717 * update adapter's configuration
5719 5718 */
5720 5719 err = iwh_run_state_config(sc);
5721 5720 if (err != IWH_SUCCESS) {
5722 5721 cmn_err(CE_WARN, "iwh_fast_recover(): "
5723 5722 "failed to setup association\n");
5724 5723 mutex_exit(&sc->sc_glock);
5725 5724 return (err);
5726 5725 }
5727 5726
5728 5727 /*
5729 5728 * set LED on
5730 5729 */
5731 5730 iwh_set_led(sc, 2, 0, 1);
5732 5731
5733 5732 mutex_exit(&sc->sc_glock);
5734 5733
5735 5734 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
5736 5735
5737 5736 /*
5738 5737 * start queue
5739 5738 */
5740 5739 IWH_DBG((IWH_DEBUG_FW, "iwh_fast_recover(): "
5741 5740 "resume xmit\n"));
5742 5741 mac_tx_update(ic->ic_mach);
5743 5742
5744 5743 return (IWH_SUCCESS);
5745 5744 }
5746 5745
5747 5746 static int
5748 5747 iwh_run_state_config(iwh_sc_t *sc)
5749 5748 {
5750 5749 struct ieee80211com *ic = &sc->sc_ic;
5751 5750 ieee80211_node_t *in = ic->ic_bss;
5752 5751 uint32_t ht_protec = (uint32_t)(-1);
5753 5752 int err = IWH_FAIL;
5754 5753
5755 5754 /*
5756 5755 * update adapter's configuration
5757 5756 */
5758 5757 sc->sc_config.assoc_id = in->in_associd & 0x3fff;
5759 5758
5760 5759 /*
5761 5760 * short preamble/slot time are
5762 5761 * negotiated when associating
5763 5762 */
5764 5763 sc->sc_config.flags &=
5765 5764 ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
5766 5765 RXON_FLG_SHORT_SLOT_MSK);
5767 5766
5768 5767 if (ic->ic_flags & IEEE80211_F_SHSLOT) {
5769 5768 sc->sc_config.flags |=
5770 5769 LE_32(RXON_FLG_SHORT_SLOT_MSK);
5771 5770 }
5772 5771
5773 5772 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) {
5774 5773 sc->sc_config.flags |=
5775 5774 LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
5776 5775 }
5777 5776
5778 5777 if (in->in_flags & IEEE80211_NODE_HT) {
5779 5778 ht_protec = in->in_htopmode;
5780 5779 if (ht_protec > 3) {
5781 5780 cmn_err(CE_WARN, "iwh_run_state_config(): "
5782 5781 "HT protection mode is not correct.\n");
5783 5782 return (IWH_FAIL);
5784 5783 } else if (NO_HT_PROT == ht_protec) {
5785 5784 ht_protec = sc->sc_ht_conf.ht_protection;
5786 5785 }
5787 5786
5788 5787 sc->sc_config.flags |=
5789 5788 LE_32(ht_protec << RXON_FLG_HT_OPERATING_MODE_POS);
5790 5789 }
5791 5790
5792 5791 /*
5793 5792 * set RX chains/antennas.
5794 5793 */
5795 5794 iwh_config_rxon_chain(sc);
5796 5795
5797 5796 sc->sc_config.filter_flags |=
5798 5797 LE_32(RXON_FILTER_ASSOC_MSK);
5799 5798
5800 5799 if (ic->ic_opmode != IEEE80211_M_STA) {
5801 5800 sc->sc_config.filter_flags |=
5802 5801 LE_32(RXON_FILTER_BCON_AWARE_MSK);
5803 5802 }
5804 5803
5805 5804 IWH_DBG((IWH_DEBUG_80211, "iwh_run_state_config(): "
5806 5805 "config chan %d flags %x"
5807 5806 " filter_flags %x\n",
5808 5807 sc->sc_config.chan, sc->sc_config.flags,
5809 5808 sc->sc_config.filter_flags));
5810 5809
5811 5810 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
5812 5811 sizeof (iwh_rxon_cmd_t), 1);
5813 5812 if (err != IWH_SUCCESS) {
5814 5813 cmn_err(CE_WARN, "iwh_run_state_config(): "
5815 5814 "could not update configuration\n");
5816 5815 return (err);
5817 5816 }
5818 5817
5819 5818 if ((sc->sc_dev_id != 0x423c) &&
5820 5819 (sc->sc_dev_id != 0x423d)) {
5821 5820 /*
5822 5821 * send tx power table command
5823 5822 */
5824 5823 err = iwh_tx_power_table(sc, 1);
5825 5824 if (err != IWH_SUCCESS) {
5826 5825 return (err);
5827 5826 }
5828 5827 }
5829 5828
5830 5829 /*
5831 5830 * Not need to update retry rate table for AP node
5832 5831 */
5833 5832 err = iwh_qosparam_to_hw(sc, 1);
5834 5833 if (err != IWH_SUCCESS) {
5835 5834 return (err);
5836 5835 }
5837 5836
5838 5837 return (err);
5839 5838 }
5840 5839
5841 5840 /*
5842 5841 * This function is only for compatibility with Net80211 module.
5843 5842 * iwh_qosparam_to_hw() is the actual function updating EDCA
5844 5843 * parameters to hardware.
5845 5844 */
5846 5845 /* ARGSUSED */
5847 5846 static int
5848 5847 iwh_wme_update(ieee80211com_t *ic)
5849 5848 {
5850 5849 return (0);
5851 5850 }
5852 5851
5853 5852 static int
5854 5853 iwh_wme_to_qos_ac(int wme_ac)
5855 5854 {
5856 5855 int qos_ac = QOS_AC_INVALID;
5857 5856
5858 5857 if (wme_ac < WME_AC_BE || wme_ac > WME_AC_VO) {
5859 5858 cmn_err(CE_WARN, "iwh_wme_to_qos_ac(): "
5860 5859 "WME AC index is not in suitable range.\n");
5861 5860 return (qos_ac);
5862 5861 }
5863 5862
5864 5863 switch (wme_ac) {
5865 5864 case WME_AC_BE:
5866 5865 qos_ac = QOS_AC_BK;
5867 5866 break;
5868 5867 case WME_AC_BK:
5869 5868 qos_ac = QOS_AC_BE;
5870 5869 break;
5871 5870 case WME_AC_VI:
5872 5871 qos_ac = QOS_AC_VI;
5873 5872 break;
5874 5873 case WME_AC_VO:
5875 5874 qos_ac = QOS_AC_VO;
5876 5875 break;
5877 5876 }
5878 5877
5879 5878 return (qos_ac);
5880 5879 }
5881 5880
5882 5881 static uint16_t
5883 5882 iwh_cw_e_to_cw(uint8_t cw_e)
5884 5883 {
5885 5884 uint16_t cw = 1;
5886 5885
5887 5886 while (cw_e > 0) {
5888 5887 cw <<= 1;
5889 5888 cw_e--;
5890 5889 }
5891 5890
5892 5891 cw -= 1;
5893 5892 return (cw);
5894 5893 }
5895 5894
5896 5895 static int
5897 5896 iwh_wmeparam_check(struct wmeParams *wmeparam)
5898 5897 {
5899 5898 int i;
5900 5899
5901 5900 for (i = 0; i < WME_NUM_AC; i++) {
5902 5901
5903 5902 if ((wmeparam[i].wmep_logcwmax > QOS_CW_RANGE_MAX) ||
5904 5903 (wmeparam[i].wmep_logcwmin >= wmeparam[i].wmep_logcwmax)) {
5905 5904 cmn_err(CE_WARN, "iwh_wmeparam_check(): "
5906 5905 "Contention window is not in suitable range.\n");
5907 5906 return (IWH_FAIL);
5908 5907 }
5909 5908
5910 5909 if ((wmeparam[i].wmep_aifsn < QOS_AIFSN_MIN) ||
5911 5910 (wmeparam[i].wmep_aifsn > QOS_AIFSN_MAX)) {
5912 5911 cmn_err(CE_WARN, "iwh_wmeparam_check(): "
5913 5912 "Arbitration interframe space number"
5914 5913 "is not in suitable range.\n");
5915 5914 return (IWH_FAIL);
5916 5915 }
5917 5916 }
5918 5917
5919 5918 return (IWH_SUCCESS);
5920 5919 }
5921 5920
5922 5921 /*
5923 5922 * This function updates EDCA parameters into hardware.
5924 5923 * FIFO0-background, FIFO1-best effort, FIFO2-viedo, FIFO3-voice.
5925 5924 */
5926 5925 static int
5927 5926 iwh_qosparam_to_hw(iwh_sc_t *sc, int async)
5928 5927 {
5929 5928 ieee80211com_t *ic = &sc->sc_ic;
5930 5929 ieee80211_node_t *in = ic->ic_bss;
5931 5930 struct wmeParams *wmeparam;
5932 5931 iwh_qos_param_cmd_t qosparam_cmd;
5933 5932 int i, j;
5934 5933 int err = IWH_FAIL;
5935 5934
5936 5935 if ((in->in_flags & IEEE80211_NODE_QOS) &&
5937 5936 (IEEE80211_M_STA == ic->ic_opmode)) {
5938 5937 wmeparam = ic->ic_wme.wme_chanParams.cap_wmeParams;
5939 5938 } else {
5940 5939 return (IWH_SUCCESS);
5941 5940 }
5942 5941
5943 5942 (void) memset(&qosparam_cmd, 0, sizeof (qosparam_cmd));
5944 5943
5945 5944 err = iwh_wmeparam_check(wmeparam);
5946 5945 if (err != IWH_SUCCESS) {
5947 5946 return (err);
5948 5947 }
5949 5948
5950 5949 if (in->in_flags & IEEE80211_NODE_QOS) {
5951 5950 qosparam_cmd.flags |= QOS_PARAM_FLG_UPDATE_EDCA;
5952 5951 }
5953 5952
5954 5953 if (in->in_flags & (IEEE80211_NODE_QOS | IEEE80211_NODE_HT)) {
5955 5954 qosparam_cmd.flags |= QOS_PARAM_FLG_TGN;
5956 5955 }
5957 5956
5958 5957 for (i = 0; i < WME_NUM_AC; i++) {
5959 5958
5960 5959 j = iwh_wme_to_qos_ac(i);
5961 5960 if (j < QOS_AC_BK || j > QOS_AC_VO) {
5962 5961 return (IWH_FAIL);
5963 5962 }
5964 5963
5965 5964 qosparam_cmd.ac[j].cw_min =
5966 5965 iwh_cw_e_to_cw(wmeparam[i].wmep_logcwmin);
5967 5966 qosparam_cmd.ac[j].cw_max =
5968 5967 iwh_cw_e_to_cw(wmeparam[i].wmep_logcwmax);
5969 5968 qosparam_cmd.ac[j].aifsn =
5970 5969 wmeparam[i].wmep_aifsn;
5971 5970 qosparam_cmd.ac[j].txop =
5972 5971 (uint16_t)(wmeparam[i].wmep_txopLimit * 32);
5973 5972 }
5974 5973
5975 5974 err = iwh_cmd(sc, REPLY_QOS_PARAM, &qosparam_cmd,
5976 5975 sizeof (qosparam_cmd), async);
5977 5976 if (err != IWH_SUCCESS) {
5978 5977 cmn_err(CE_WARN, "iwh_qosparam_to_hw(): "
5979 5978 "failed to update QoS parameters into hardware.\n");
5980 5979 return (err);
5981 5980 }
5982 5981
5983 5982 #ifdef DEBUG
5984 5983 IWH_DBG((IWH_DEBUG_QOS, "iwh_qosparam_to_hw(): "
5985 5984 "EDCA parameters are as follows:\n"));
5986 5985
5987 5986 IWH_DBG((IWH_DEBUG_QOS, "BK parameters are: "
5988 5987 "cw_min = %d, cw_max = %d, aifsn = %d, txop = %d\n",
5989 5988 qosparam_cmd.ac[0].cw_min, qosparam_cmd.ac[0].cw_max,
5990 5989 qosparam_cmd.ac[0].aifsn, qosparam_cmd.ac[0].txop));
5991 5990
5992 5991 IWH_DBG((IWH_DEBUG_QOS, "BE parameters are: "
5993 5992 "cw_min = %d, cw_max = %d, aifsn = %d, txop = %d\n",
5994 5993 qosparam_cmd.ac[1].cw_min, qosparam_cmd.ac[1].cw_max,
5995 5994 qosparam_cmd.ac[1].aifsn, qosparam_cmd.ac[1].txop));
5996 5995
5997 5996 IWH_DBG((IWH_DEBUG_QOS, "VI parameters are: "
5998 5997 "cw_min = %d, cw_max = %d, aifsn = %d, txop = %d\n",
5999 5998 qosparam_cmd.ac[2].cw_min, qosparam_cmd.ac[2].cw_max,
6000 5999 qosparam_cmd.ac[2].aifsn, qosparam_cmd.ac[2].txop));
6001 6000
6002 6001 IWH_DBG((IWH_DEBUG_QOS, "VO parameters are: "
6003 6002 "cw_min = %d, cw_max = %d, aifsn = %d, txop = %d\n",
6004 6003 qosparam_cmd.ac[3].cw_min, qosparam_cmd.ac[3].cw_max,
6005 6004 qosparam_cmd.ac[3].aifsn, qosparam_cmd.ac[3].txop));
6006 6005 #endif
6007 6006 return (err);
6008 6007 }
6009 6008
6010 6009 static inline int
6011 6010 iwh_wme_tid_qos_ac(int tid)
6012 6011 {
6013 6012 switch (tid) {
6014 6013 case 1:
6015 6014 case 2:
6016 6015 return (QOS_AC_BK);
6017 6016 case 0:
6018 6017 case 3:
6019 6018 return (QOS_AC_BE);
6020 6019 case 4:
6021 6020 case 5:
6022 6021 return (QOS_AC_VI);
6023 6022 case 6:
6024 6023 case 7:
6025 6024 return (QOS_AC_VO);
6026 6025 }
6027 6026
6028 6027 return (QOS_AC_BE);
6029 6028 }
6030 6029
6031 6030 static inline int
6032 6031 iwh_qos_ac_to_txq(int qos_ac)
6033 6032 {
6034 6033 switch (qos_ac) {
6035 6034 case QOS_AC_BK:
6036 6035 return (QOS_AC_BK_TO_TXQ);
6037 6036 case QOS_AC_BE:
6038 6037 return (QOS_AC_BE_TO_TXQ);
6039 6038 case QOS_AC_VI:
6040 6039 return (QOS_AC_VI_TO_TXQ);
6041 6040 case QOS_AC_VO:
6042 6041 return (QOS_AC_VO_TO_TXQ);
6043 6042 }
6044 6043
6045 6044 return (QOS_AC_BE_TO_TXQ);
6046 6045 }
6047 6046
6048 6047 static int
6049 6048 iwh_wme_tid_to_txq(int tid)
6050 6049 {
6051 6050 int queue_n = TXQ_FOR_AC_INVALID;
6052 6051 int qos_ac;
6053 6052
6054 6053 if (tid < WME_TID_MIN ||
6055 6054 tid > WME_TID_MAX) {
6056 6055 cmn_err(CE_WARN, "wme_tid_to_txq(): "
6057 6056 "TID is not in suitable range.\n");
6058 6057 return (queue_n);
6059 6058 }
6060 6059
6061 6060 qos_ac = iwh_wme_tid_qos_ac(tid);
6062 6061 queue_n = iwh_qos_ac_to_txq(qos_ac);
6063 6062
6064 6063 return (queue_n);
6065 6064 }
6066 6065
6067 6066 /*
6068 6067 * This function is used for intializing HT relevant configurations.
6069 6068 */
6070 6069 static void
6071 6070 iwh_init_ht_conf(iwh_sc_t *sc)
6072 6071 {
6073 6072 (void) memset(&sc->sc_ht_conf, 0, sizeof (iwh_ht_conf_t));
6074 6073
6075 6074 if ((0x4235 == sc->sc_dev_id) ||
6076 6075 (0x4236 == sc->sc_dev_id) ||
6077 6076 (0x423a == sc->sc_dev_id)) {
6078 6077 sc->sc_ht_conf.ht_support = 1;
6079 6078
6080 6079 sc->sc_ht_conf.valid_chains = 3;
6081 6080 sc->sc_ht_conf.tx_stream_count = 2;
6082 6081 sc->sc_ht_conf.rx_stream_count = 2;
6083 6082
6084 6083 sc->sc_ht_conf.tx_support_mcs[0] = 0xff;
6085 6084 sc->sc_ht_conf.tx_support_mcs[1] = 0xff;
6086 6085 sc->sc_ht_conf.rx_support_mcs[0] = 0xff;
6087 6086 sc->sc_ht_conf.rx_support_mcs[1] = 0xff;
6088 6087 } else {
6089 6088 sc->sc_ht_conf.ht_support = 1;
6090 6089
6091 6090 sc->sc_ht_conf.valid_chains = 2;
6092 6091 sc->sc_ht_conf.tx_stream_count = 1;
6093 6092 sc->sc_ht_conf.rx_stream_count = 2;
6094 6093
6095 6094 sc->sc_ht_conf.tx_support_mcs[0] = 0xff;
6096 6095 sc->sc_ht_conf.rx_support_mcs[0] = 0xff;
6097 6096 sc->sc_ht_conf.rx_support_mcs[1] = 0xff;
6098 6097 }
6099 6098
6100 6099 if (sc->sc_ht_conf.ht_support) {
6101 6100 sc->sc_ht_conf.cap |= HT_CAP_GRN_FLD;
6102 6101 sc->sc_ht_conf.cap |= HT_CAP_SGI_20;
6103 6102 sc->sc_ht_conf.cap |= HT_CAP_MAX_AMSDU;
6104 6103 /* should disable MIMO */
6105 6104 sc->sc_ht_conf.cap |= HT_CAP_MIMO_PS;
6106 6105
6107 6106 sc->sc_ht_conf.ampdu_p.factor = HT_RX_AMPDU_FACTOR;
6108 6107 sc->sc_ht_conf.ampdu_p.density = HT_MPDU_DENSITY;
6109 6108
6110 6109 sc->sc_ht_conf.ht_protection = HT_PROT_CHAN_NON_HT;
6111 6110 }
6112 6111 }
6113 6112
6114 6113 /*
6115 6114 * This function overwrites default ieee80211_rateset_11n struc.
6116 6115 */
6117 6116 static void
6118 6117 iwh_overwrite_11n_rateset(iwh_sc_t *sc)
6119 6118 {
6120 6119 uint8_t *ht_rs = sc->sc_ht_conf.rx_support_mcs;
6121 6120 int mcs_idx, mcs_count = 0;
6122 6121 int i, j;
6123 6122
6124 6123 for (i = 0; i < HT_RATESET_NUM; i++) {
6125 6124 for (j = 0; j < 8; j++) {
6126 6125 if (ht_rs[i] & (1 << j)) {
6127 6126 mcs_idx = i * 8 + j;
6128 6127 if (mcs_idx >= IEEE80211_HTRATE_MAXSIZE) {
6129 6128 break;
6130 6129 }
6131 6130
6132 6131 ieee80211_rateset_11n.rs_rates[mcs_idx] =
6133 6132 (uint8_t)mcs_idx;
6134 6133 mcs_count++;
6135 6134 }
6136 6135 }
6137 6136 }
6138 6137
6139 6138 ieee80211_rateset_11n.rs_nrates = (uint8_t)mcs_count;
6140 6139
6141 6140 #ifdef DEBUG
6142 6141 IWH_DBG((IWH_DEBUG_HTRATE, "iwh_overwrite_11n_rateset(): "
6143 6142 "HT rates supported by this station is as follows:\n"));
6144 6143
6145 6144 for (i = 0; i < ieee80211_rateset_11n.rs_nrates; i++) {
6146 6145 IWH_DBG((IWH_DEBUG_HTRATE, "Rate %d is %d\n",
6147 6146 i, ieee80211_rateset_11n.rs_rates[i]));
6148 6147 }
6149 6148 #endif
6150 6149 }
6151 6150
6152 6151 /*
6153 6152 * This function overwrites default configurations of
6154 6153 * ieee80211com structure in Net80211 module.
6155 6154 */
6156 6155 static void
6157 6156 iwh_overwrite_ic_default(iwh_sc_t *sc)
6158 6157 {
6159 6158 ieee80211com_t *ic = &sc->sc_ic;
6160 6159
6161 6160 sc->sc_newstate = ic->ic_newstate;
6162 6161 ic->ic_newstate = iwh_newstate;
6163 6162 ic->ic_node_alloc = iwh_node_alloc;
6164 6163 ic->ic_node_free = iwh_node_free;
6165 6164
6166 6165 if (sc->sc_ht_conf.ht_support) {
6167 6166 sc->sc_recv_action = ic->ic_recv_action;
6168 6167 ic->ic_recv_action = iwh_recv_action;
6169 6168 sc->sc_send_action = ic->ic_send_action;
6170 6169 ic->ic_send_action = iwh_send_action;
6171 6170
6172 6171 ic->ic_ampdu_rxmax = sc->sc_ht_conf.ampdu_p.factor;
6173 6172 ic->ic_ampdu_density = sc->sc_ht_conf.ampdu_p.density;
6174 6173 ic->ic_ampdu_limit = ic->ic_ampdu_rxmax;
6175 6174 }
6176 6175 }
6177 6176
6178 6177 /*
6179 6178 * This function sets "RX chain selection" feild
6180 6179 * in RXON command during plumb driver.
6181 6180 */
6182 6181 static void
6183 6182 iwh_config_rxon_chain(iwh_sc_t *sc)
6184 6183 {
6185 6184 ieee80211com_t *ic = &sc->sc_ic;
6186 6185 ieee80211_node_t *in = ic->ic_bss;
6187 6186
6188 6187 if (3 == sc->sc_ht_conf.valid_chains) {
6189 6188 sc->sc_config.rx_chain = LE_16((RXON_RX_CHAIN_A_MSK |
6190 6189 RXON_RX_CHAIN_B_MSK | RXON_RX_CHAIN_C_MSK) <<
6191 6190 RXON_RX_CHAIN_VALID_POS);
6192 6191
6193 6192 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6194 6193 RXON_RX_CHAIN_B_MSK | RXON_RX_CHAIN_C_MSK) <<
6195 6194 RXON_RX_CHAIN_FORCE_SEL_POS);
6196 6195
6197 6196 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6198 6197 RXON_RX_CHAIN_B_MSK | RXON_RX_CHAIN_C_MSK) <<
6199 6198 RXON_RX_CHAIN_FORCE_MIMO_SEL_POS);
6200 6199 } else {
6201 6200 sc->sc_config.rx_chain = LE_16((RXON_RX_CHAIN_A_MSK |
6202 6201 RXON_RX_CHAIN_B_MSK) << RXON_RX_CHAIN_VALID_POS);
6203 6202
6204 6203 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6205 6204 RXON_RX_CHAIN_B_MSK) << RXON_RX_CHAIN_FORCE_SEL_POS);
6206 6205
6207 6206 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6208 6207 RXON_RX_CHAIN_B_MSK) <<
6209 6208 RXON_RX_CHAIN_FORCE_MIMO_SEL_POS);
6210 6209 }
6211 6210
6212 6211 sc->sc_config.rx_chain |= LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK);
6213 6212
6214 6213 if ((in != NULL) &&
6215 6214 (in->in_flags & IEEE80211_NODE_HT) &&
6216 6215 sc->sc_ht_conf.ht_support) {
6217 6216 if (3 == sc->sc_ht_conf.valid_chains) {
6218 6217 sc->sc_config.rx_chain |= LE_16(3 <<
6219 6218 RXON_RX_CHAIN_CNT_POS);
6220 6219 sc->sc_config.rx_chain |= LE_16(3 <<
6221 6220 RXON_RX_CHAIN_MIMO_CNT_POS);
6222 6221 } else {
6223 6222 sc->sc_config.rx_chain |= LE_16(2 <<
6224 6223 RXON_RX_CHAIN_CNT_POS);
6225 6224 sc->sc_config.rx_chain |= LE_16(2 <<
6226 6225 RXON_RX_CHAIN_MIMO_CNT_POS);
6227 6226 }
6228 6227
6229 6228 sc->sc_config.rx_chain |= LE_16(1 <<
6230 6229 RXON_RX_CHAIN_MIMO_FORCE_POS);
6231 6230 }
6232 6231
6233 6232 IWH_DBG((IWH_DEBUG_RXON, "iwh_config_rxon_chain(): "
6234 6233 "rxon->rx_chain = %x\n", sc->sc_config.rx_chain));
6235 6234 }
6236 6235
6237 6236 /*
6238 6237 * This function adds AP station into hardware.
6239 6238 */
6240 6239 static int
6241 6240 iwh_add_ap_sta(iwh_sc_t *sc)
6242 6241 {
6243 6242 ieee80211com_t *ic = &sc->sc_ic;
6244 6243 ieee80211_node_t *in = ic->ic_bss;
6245 6244 iwh_add_sta_t node;
6246 6245 uint32_t ampdu_factor, ampdu_density;
6247 6246 int err = IWH_FAIL;
6248 6247
6249 6248 /*
6250 6249 * Add AP node into hardware.
6251 6250 */
6252 6251 (void) memset(&node, 0, sizeof (node));
6253 6252 IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid);
6254 6253 node.mode = STA_MODE_ADD_MSK;
6255 6254 node.sta.sta_id = IWH_AP_ID;
6256 6255
6257 6256 if (sc->sc_ht_conf.ht_support &&
6258 6257 (in->in_htcap_ie != NULL) &&
6259 6258 (in->in_htcap != 0) &&
6260 6259 (in->in_htparam != 0)) {
6261 6260
6262 6261 if (((in->in_htcap & HT_CAP_MIMO_PS) >> 2)
6263 6262 == HT_CAP_MIMO_PS_DYNAMIC) {
6264 6263 node.station_flags |= LE_32(STA_FLG_RTS_MIMO_PROT);
6265 6264 }
6266 6265
6267 6266 ampdu_factor = in->in_htparam & HT_RX_AMPDU_FACTOR_MSK;
6268 6267 node.station_flags |=
6269 6268 LE_32(ampdu_factor << STA_FLG_MAX_AMPDU_POS);
6270 6269
6271 6270 ampdu_density = (in->in_htparam & HT_MPDU_DENSITY_MSK) >>
6272 6271 HT_MPDU_DENSITY_POS;
6273 6272 node.station_flags |=
6274 6273 LE_32(ampdu_density << STA_FLG_AMPDU_DENSITY_POS);
6275 6274
6276 6275 if (in->in_htcap & LE_16(HT_CAP_SUP_WIDTH)) {
6277 6276 node.station_flags |=
6278 6277 LE_32(STA_FLG_FAT_EN);
6279 6278 }
6280 6279 }
6281 6280
6282 6281 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6283 6282 if (err != IWH_SUCCESS) {
6284 6283 cmn_err(CE_WARN, "iwh_add_ap_lq(): "
6285 6284 "failed to add AP node\n");
6286 6285 return (err);
6287 6286 }
6288 6287
6289 6288 return (err);
6290 6289 }
6291 6290
6292 6291 /*
6293 6292 * Each station in the Shirley Peak's internal station table has
6294 6293 * its own table of 16 TX rates and modulation modes for retrying
6295 6294 * TX when an ACK is not received. This function replaces the entire
6296 6295 * table for one station.Station must already be in Shirley Peak's
6297 6296 * station talbe.
6298 6297 */
6299 6298 static int
6300 6299 iwh_ap_lq(iwh_sc_t *sc)
6301 6300 {
6302 6301 ieee80211com_t *ic = &sc->sc_ic;
6303 6302 ieee80211_node_t *in = ic->ic_bss;
6304 6303 iwh_link_quality_cmd_t link_quality;
6305 6304 const struct ieee80211_rateset *rs_sup = NULL;
6306 6305 uint32_t masks = 0, rate;
6307 6306 int i, err = IWH_FAIL;
6308 6307
6309 6308 /*
6310 6309 * TX_LINK_QUALITY cmd
6311 6310 */
6312 6311 (void) memset(&link_quality, 0, sizeof (link_quality));
6313 6312 if (in->in_chan == IEEE80211_CHAN_ANYC) /* skip null node */
6314 6313 return (err);
6315 6314 rs_sup = ieee80211_get_suprates(ic, in->in_chan);
6316 6315
6317 6316 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
6318 6317 if (i < rs_sup->ir_nrates) {
6319 6318 rate = rs_sup->ir_rates[rs_sup->ir_nrates - i] &
6320 6319 IEEE80211_RATE_VAL;
6321 6320 } else {
6322 6321 rate = 2;
6323 6322 }
6324 6323
6325 6324 if (2 == rate || 4 == rate ||
6326 6325 11 == rate || 22 == rate) {
6327 6326 masks |= LE_32(RATE_MCS_CCK_MSK);
6328 6327 }
6329 6328
6330 6329 masks |= LE_32(RATE_MCS_ANT_B_MSK);
6331 6330
6332 6331 link_quality.rate_n_flags[i] =
6333 6332 LE_32(iwh_rate_to_plcp(rate) | masks);
6334 6333 }
6335 6334
6336 6335 link_quality.general_params.single_stream_ant_msk = LINK_QUAL_ANT_B_MSK;
6337 6336 link_quality.general_params.dual_stream_ant_msk = LINK_QUAL_ANT_MSK;
6338 6337 link_quality.agg_params.agg_dis_start_th = 3;
6339 6338 link_quality.agg_params.agg_time_limit = LE_16(4000);
6340 6339 link_quality.sta_id = IWH_AP_ID;
6341 6340 err = iwh_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
6342 6341 sizeof (link_quality), 1);
6343 6342 if (err != IWH_SUCCESS) {
6344 6343 cmn_err(CE_WARN, "iwh_ap_lq(): "
6345 6344 "failed to config link quality table\n");
6346 6345 return (err);
6347 6346 }
6348 6347
6349 6348 #ifdef DEBUG
6350 6349 IWH_DBG((IWH_DEBUG_HWRATE, "iwh_ap_lq(): "
6351 6350 "Rates in HW are as follows:\n"));
6352 6351
6353 6352 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
6354 6353 IWH_DBG((IWH_DEBUG_HWRATE,
6355 6354 "Rate %d in HW is %x\n", i, link_quality.rate_n_flags[i]));
6356 6355 }
6357 6356 #endif
6358 6357
6359 6358 return (err);
6360 6359 }
6361 6360
6362 6361 /*
6363 6362 * When block ACK agreement has been set up between station and AP,
6364 6363 * Net80211 module will call this function to inform hardware about
6365 6364 * informations of this BA agreement.
6366 6365 * When AP wants to delete BA agreement that was originated by it,
6367 6366 * Net80211 modele will call this function to clean up relevant
6368 6367 * information in hardware.
6369 6368 */
6370 6369 static void
6371 6370 iwh_recv_action(struct ieee80211_node *in,
6372 6371 const uint8_t *frm, const uint8_t *efrm)
6373 6372 {
6374 6373 struct ieee80211com *ic;
6375 6374 iwh_sc_t *sc;
6376 6375 const struct ieee80211_action *ia;
6377 6376 uint16_t baparamset, baseqctl;
6378 6377 uint32_t tid, ssn;
6379 6378 iwh_add_sta_t node;
6380 6379 int err = IWH_FAIL;
6381 6380
6382 6381 if ((NULL == in) || (NULL == frm)) {
6383 6382 return;
6384 6383 }
6385 6384
6386 6385 ic = in->in_ic;
6387 6386 if (NULL == ic) {
6388 6387 return;
6389 6388 }
6390 6389
6391 6390 sc = (iwh_sc_t *)ic;
6392 6391
6393 6392 sc->sc_recv_action(in, frm, efrm);
6394 6393
6395 6394 ia = (const struct ieee80211_action *)frm;
6396 6395 if (ia->ia_category != IEEE80211_ACTION_CAT_BA) {
6397 6396 return;
6398 6397 }
6399 6398
6400 6399 switch (ia->ia_action) {
6401 6400 case IEEE80211_ACTION_BA_ADDBA_REQUEST:
6402 6401 baparamset = *(uint16_t *)(frm + 3);
6403 6402 baseqctl = *(uint16_t *)(frm + 7);
6404 6403
6405 6404 tid = MS(baparamset, IEEE80211_BAPS_TID);
6406 6405 ssn = MS(baseqctl, IEEE80211_BASEQ_START);
6407 6406
6408 6407 (void) memset(&node, 0, sizeof (node));
6409 6408 IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid);
6410 6409 node.mode = STA_MODE_MODIFY_MSK;
6411 6410 node.sta.sta_id = IWH_AP_ID;
6412 6411
6413 6412 node.station_flags_msk = 0;
6414 6413 node.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
6415 6414 node.add_immediate_ba_tid = (uint8_t)tid;
6416 6415 node.add_immediate_ba_ssn = LE_16(ssn);
6417 6416
6418 6417 mutex_enter(&sc->sc_glock);
6419 6418 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6420 6419 if (err != IWH_SUCCESS) {
6421 6420 cmn_err(CE_WARN, "iwh_recv_action(): "
6422 6421 "failed to setup RX block ACK\n");
6423 6422 mutex_exit(&sc->sc_glock);
6424 6423 return;
6425 6424 }
6426 6425 mutex_exit(&sc->sc_glock);
6427 6426
6428 6427 IWH_DBG((IWH_DEBUG_BA, "iwh_recv_action(): "
6429 6428 "RX block ACK "
6430 6429 "was setup on TID %d and SSN is %d.\n", tid, ssn));
6431 6430
6432 6431 return;
6433 6432
6434 6433 case IEEE80211_ACTION_BA_DELBA:
6435 6434 baparamset = *(uint16_t *)(frm + 2);
6436 6435
6437 6436 if ((baparamset & IEEE80211_DELBAPS_INIT) == 0) {
6438 6437 return;
6439 6438 }
6440 6439
6441 6440 tid = MS(baparamset, IEEE80211_DELBAPS_TID);
6442 6441
6443 6442 (void) memset(&node, 0, sizeof (node));
6444 6443 IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid);
6445 6444 node.mode = STA_MODE_MODIFY_MSK;
6446 6445 node.sta.sta_id = IWH_AP_ID;
6447 6446
6448 6447 node.station_flags_msk = 0;
6449 6448 node.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
6450 6449 node.add_immediate_ba_tid = (uint8_t)tid;
6451 6450
6452 6451 mutex_enter(&sc->sc_glock);
6453 6452 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6454 6453 if (err != IWH_SUCCESS) {
6455 6454 cmn_err(CE_WARN, "iwh_recv_action(): "
6456 6455 "failed to delete RX block ACK\n");
6457 6456 mutex_exit(&sc->sc_glock);
6458 6457 return;
6459 6458 }
6460 6459 mutex_exit(&sc->sc_glock);
6461 6460
6462 6461 IWH_DBG((IWH_DEBUG_BA, "iwh_recv_action(): "
6463 6462 "RX block ACK "
6464 6463 "was deleted on TID %d.\n", tid));
6465 6464
6466 6465 return;
6467 6466 }
6468 6467 }
6469 6468
6470 6469 /*
6471 6470 * When local station wants to delete BA agreement that was originated by AP,
6472 6471 * Net80211 module will call this function to clean up relevant information
6473 6472 * in hardware.
6474 6473 */
6475 6474 static int
6476 6475 iwh_send_action(struct ieee80211_node *in,
6477 6476 int category, int action, uint16_t args[4])
6478 6477 {
6479 6478 struct ieee80211com *ic;
6480 6479 iwh_sc_t *sc;
6481 6480 uint32_t tid;
6482 6481 iwh_add_sta_t node;
6483 6482 int ret = EIO;
6484 6483 int err = IWH_FAIL;
6485 6484
6486 6485
6487 6486 if (NULL == in) {
6488 6487 return (ret);
6489 6488 }
6490 6489
6491 6490 ic = in->in_ic;
6492 6491 if (NULL == ic) {
6493 6492 return (ret);
6494 6493 }
6495 6494
6496 6495 sc = (iwh_sc_t *)ic;
6497 6496
6498 6497 ret = sc->sc_send_action(in, category, action, args);
6499 6498
6500 6499 if (category != IEEE80211_ACTION_CAT_BA) {
6501 6500 return (ret);
6502 6501 }
6503 6502
6504 6503 switch (action) {
6505 6504 case IEEE80211_ACTION_BA_DELBA:
6506 6505 if (IEEE80211_DELBAPS_INIT == args[1]) {
6507 6506 return (ret);
6508 6507 }
6509 6508
6510 6509 tid = args[0];
6511 6510
6512 6511 (void) memset(&node, 0, sizeof (node));
6513 6512 IEEE80211_ADDR_COPY(node.sta.addr, in->in_bssid);
6514 6513 node.mode = STA_MODE_MODIFY_MSK;
6515 6514 node.sta.sta_id = IWH_AP_ID;
6516 6515
6517 6516 node.station_flags_msk = 0;
6518 6517 node.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
6519 6518 node.add_immediate_ba_tid = (uint8_t)tid;
6520 6519
6521 6520 mutex_enter(&sc->sc_glock);
6522 6521 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6523 6522 if (err != IWH_SUCCESS) {
6524 6523 cmn_err(CE_WARN, "iwh_send_action(): "
6525 6524 "failed to delete RX balock ACK\n");
6526 6525 mutex_exit(&sc->sc_glock);
6527 6526 return (EIO);
6528 6527 }
6529 6528 mutex_exit(&sc->sc_glock);
6530 6529
6531 6530 IWH_DBG((IWH_DEBUG_BA, "iwh_send_action(): "
6532 6531 "RX block ACK "
6533 6532 "was deleted on TID %d.\n", tid));
6534 6533
6535 6534 break;
6536 6535 }
6537 6536
6538 6537 return (ret);
6539 6538 }
6540 6539
6541 6540 static int
6542 6541 iwh_reset_hw(iwh_sc_t *sc)
6543 6542 {
6544 6543 uint32_t tmp;
6545 6544 int n;
6546 6545
6547 6546 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6548 6547 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6549 6548 tmp | CSR_HW_IF_CONFIG_REG_BITS_NIC_READY);
6550 6549
6551 6550 /*
6552 6551 * wait for HW ready
6553 6552 */
6554 6553 for (n = 0; n < 5; n++) {
6555 6554 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
6556 6555 CSR_HW_IF_CONFIG_REG_BITS_NIC_READY) {
6557 6556 break;
6558 6557 }
6559 6558 DELAY(10);
6560 6559 }
6561 6560
6562 6561 if (n != 5) {
6563 6562 return (IWH_SUCCESS);
6564 6563 }
6565 6564
6566 6565 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6567 6566 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6568 6567 tmp | CSR_HW_IF_CONFIG_REG_BITS_PREPARE);
6569 6568
6570 6569 for (n = 0; n < 15000; n++) {
6571 6570 if (0 == (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
6572 6571 CSR_HW_IF_CONFIG_REG_BITS_NIC_PREPARE_DONE)) {
6573 6572 break;
6574 6573 }
6575 6574 DELAY(10);
6576 6575 }
6577 6576
6578 6577 if (15000 == n) {
6579 6578 return (ETIMEDOUT);
6580 6579 }
6581 6580
6582 6581 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6583 6582 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6584 6583 tmp | CSR_HW_IF_CONFIG_REG_BITS_NIC_READY);
6585 6584
6586 6585 /*
6587 6586 * wait for HW ready
6588 6587 */
6589 6588 for (n = 0; n < 5; n++) {
6590 6589 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
6591 6590 CSR_HW_IF_CONFIG_REG_BITS_NIC_READY) {
6592 6591 break;
6593 6592 }
6594 6593 DELAY(10);
6595 6594 }
6596 6595
6597 6596 if (n != 5) {
6598 6597 return (IWH_SUCCESS);
6599 6598 } else {
6600 6599 return (ETIMEDOUT);
6601 6600 }
6602 6601 }
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