Print this page
7127 remove -Wno-missing-braces from Makefile.uts
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/igb/igb_main.c
+++ new/usr/src/uts/common/io/igb/igb_main.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 * Copyright 2013, Nexenta Systems, Inc. All rights reserved.
29 29 * Copyright 2016 Joyent, Inc.
30 30 */
31 31
32 32 #include "igb_sw.h"
33 33
34 34 static char ident[] = "Intel 1Gb Ethernet";
35 35 static char igb_version[] = "igb 2.3.8-ish";
36 36
37 37 /*
38 38 * Local function protoypes
39 39 */
40 40 static int igb_register_mac(igb_t *);
41 41 static int igb_identify_hardware(igb_t *);
42 42 static int igb_regs_map(igb_t *);
43 43 static void igb_init_properties(igb_t *);
44 44 static int igb_init_driver_settings(igb_t *);
45 45 static void igb_init_locks(igb_t *);
46 46 static void igb_destroy_locks(igb_t *);
47 47 static int igb_init_mac_address(igb_t *);
48 48 static int igb_init(igb_t *);
49 49 static int igb_init_adapter(igb_t *);
50 50 static void igb_stop_adapter(igb_t *);
51 51 static int igb_reset(igb_t *);
52 52 static void igb_tx_clean(igb_t *);
53 53 static boolean_t igb_tx_drain(igb_t *);
54 54 static boolean_t igb_rx_drain(igb_t *);
55 55 static int igb_alloc_rings(igb_t *);
56 56 static int igb_alloc_rx_data(igb_t *);
57 57 static void igb_free_rx_data(igb_t *);
58 58 static void igb_free_rings(igb_t *);
59 59 static void igb_setup_rings(igb_t *);
60 60 static void igb_setup_rx(igb_t *);
61 61 static void igb_setup_tx(igb_t *);
62 62 static void igb_setup_rx_ring(igb_rx_ring_t *);
63 63 static void igb_setup_tx_ring(igb_tx_ring_t *);
64 64 static void igb_setup_rss(igb_t *);
65 65 static void igb_setup_mac_rss_classify(igb_t *);
66 66 static void igb_setup_mac_classify(igb_t *);
67 67 static void igb_init_unicst(igb_t *);
68 68 static void igb_setup_multicst(igb_t *);
69 69 static void igb_get_phy_state(igb_t *);
70 70 static void igb_param_sync(igb_t *);
71 71 static void igb_get_conf(igb_t *);
72 72 static int igb_get_prop(igb_t *, char *, int, int, int);
73 73 static boolean_t igb_is_link_up(igb_t *);
74 74 static boolean_t igb_link_check(igb_t *);
75 75 static void igb_local_timer(void *);
76 76 static void igb_link_timer(void *);
77 77 static void igb_arm_watchdog_timer(igb_t *);
78 78 static void igb_start_watchdog_timer(igb_t *);
79 79 static void igb_restart_watchdog_timer(igb_t *);
80 80 static void igb_stop_watchdog_timer(igb_t *);
81 81 static void igb_start_link_timer(igb_t *);
82 82 static void igb_stop_link_timer(igb_t *);
83 83 static void igb_disable_adapter_interrupts(igb_t *);
84 84 static void igb_enable_adapter_interrupts_82575(igb_t *);
85 85 static void igb_enable_adapter_interrupts_82576(igb_t *);
86 86 static void igb_enable_adapter_interrupts_82580(igb_t *);
87 87 static boolean_t is_valid_mac_addr(uint8_t *);
88 88 static boolean_t igb_stall_check(igb_t *);
89 89 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t);
90 90 static void igb_set_external_loopback(igb_t *);
91 91 static void igb_set_internal_phy_loopback(igb_t *);
92 92 static void igb_set_internal_serdes_loopback(igb_t *);
93 93 static boolean_t igb_find_mac_address(igb_t *);
94 94 static int igb_alloc_intrs(igb_t *);
95 95 static int igb_alloc_intr_handles(igb_t *, int);
96 96 static int igb_add_intr_handlers(igb_t *);
97 97 static void igb_rem_intr_handlers(igb_t *);
98 98 static void igb_rem_intrs(igb_t *);
99 99 static int igb_enable_intrs(igb_t *);
100 100 static int igb_disable_intrs(igb_t *);
101 101 static void igb_setup_msix_82575(igb_t *);
102 102 static void igb_setup_msix_82576(igb_t *);
103 103 static void igb_setup_msix_82580(igb_t *);
104 104 static uint_t igb_intr_legacy(void *, void *);
105 105 static uint_t igb_intr_msi(void *, void *);
106 106 static uint_t igb_intr_rx(void *, void *);
107 107 static uint_t igb_intr_tx(void *, void *);
108 108 static uint_t igb_intr_tx_other(void *, void *);
109 109 static void igb_intr_rx_work(igb_rx_ring_t *);
110 110 static void igb_intr_tx_work(igb_tx_ring_t *);
111 111 static void igb_intr_link_work(igb_t *);
112 112 static void igb_get_driver_control(struct e1000_hw *);
113 113 static void igb_release_driver_control(struct e1000_hw *);
114 114
115 115 static int igb_attach(dev_info_t *, ddi_attach_cmd_t);
116 116 static int igb_detach(dev_info_t *, ddi_detach_cmd_t);
117 117 static int igb_resume(dev_info_t *);
118 118 static int igb_suspend(dev_info_t *);
119 119 static int igb_quiesce(dev_info_t *);
120 120 static void igb_unconfigure(dev_info_t *, igb_t *);
121 121 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
122 122 const void *);
123 123 static void igb_fm_init(igb_t *);
124 124 static void igb_fm_fini(igb_t *);
125 125 static void igb_release_multicast(igb_t *);
126 126
127 127 char *igb_priv_props[] = {
128 128 "_eee_support",
129 129 "_tx_copy_thresh",
130 130 "_tx_recycle_thresh",
131 131 "_tx_overload_thresh",
132 132 "_tx_resched_thresh",
133 133 "_rx_copy_thresh",
134 134 "_rx_limit_per_intr",
135 135 "_intr_throttling",
136 136 "_adv_pause_cap",
137 137 "_adv_asym_pause_cap",
138 138 NULL
139 139 };
140 140
141 141 static struct cb_ops igb_cb_ops = {
142 142 nulldev, /* cb_open */
143 143 nulldev, /* cb_close */
144 144 nodev, /* cb_strategy */
145 145 nodev, /* cb_print */
146 146 nodev, /* cb_dump */
147 147 nodev, /* cb_read */
148 148 nodev, /* cb_write */
149 149 nodev, /* cb_ioctl */
150 150 nodev, /* cb_devmap */
151 151 nodev, /* cb_mmap */
152 152 nodev, /* cb_segmap */
153 153 nochpoll, /* cb_chpoll */
154 154 ddi_prop_op, /* cb_prop_op */
155 155 NULL, /* cb_stream */
156 156 D_MP | D_HOTPLUG, /* cb_flag */
157 157 CB_REV, /* cb_rev */
158 158 nodev, /* cb_aread */
159 159 nodev /* cb_awrite */
160 160 };
161 161
162 162 static struct dev_ops igb_dev_ops = {
163 163 DEVO_REV, /* devo_rev */
164 164 0, /* devo_refcnt */
165 165 NULL, /* devo_getinfo */
166 166 nulldev, /* devo_identify */
167 167 nulldev, /* devo_probe */
168 168 igb_attach, /* devo_attach */
169 169 igb_detach, /* devo_detach */
170 170 nodev, /* devo_reset */
171 171 &igb_cb_ops, /* devo_cb_ops */
172 172 NULL, /* devo_bus_ops */
173 173 ddi_power, /* devo_power */
|
↓ open down ↓ |
173 lines elided |
↑ open up ↑ |
174 174 igb_quiesce, /* devo_quiesce */
175 175 };
176 176
177 177 static struct modldrv igb_modldrv = {
178 178 &mod_driverops, /* Type of module. This one is a driver */
179 179 ident, /* Discription string */
180 180 &igb_dev_ops, /* driver ops */
181 181 };
182 182
183 183 static struct modlinkage igb_modlinkage = {
184 - MODREV_1, &igb_modldrv, NULL
184 + MODREV_1, { &igb_modldrv, NULL }
185 185 };
186 186
187 187 /* Access attributes for register mapping */
188 188 ddi_device_acc_attr_t igb_regs_acc_attr = {
189 189 DDI_DEVICE_ATTR_V1,
190 190 DDI_STRUCTURE_LE_ACC,
191 191 DDI_STRICTORDER_ACC,
192 192 DDI_FLAGERR_ACC
193 193 };
194 194
195 195 #define IGB_M_CALLBACK_FLAGS \
196 196 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
197 197
198 198 static mac_callbacks_t igb_m_callbacks = {
199 199 IGB_M_CALLBACK_FLAGS,
200 200 igb_m_stat,
201 201 igb_m_start,
202 202 igb_m_stop,
203 203 igb_m_promisc,
204 204 igb_m_multicst,
205 205 NULL,
206 206 NULL,
207 207 NULL,
208 208 igb_m_ioctl,
209 209 igb_m_getcapab,
210 210 NULL,
211 211 NULL,
212 212 igb_m_setprop,
213 213 igb_m_getprop,
214 214 igb_m_propinfo
215 215 };
216 216
217 217 /*
218 218 * Initialize capabilities of each supported adapter type
219 219 */
220 220 static adapter_info_t igb_82575_cap = {
221 221 /* limits */
222 222 4, /* maximum number of rx queues */
223 223 1, /* minimum number of rx queues */
224 224 4, /* default number of rx queues */
225 225 4, /* maximum number of tx queues */
226 226 1, /* minimum number of tx queues */
227 227 4, /* default number of tx queues */
228 228 65535, /* maximum interrupt throttle rate */
229 229 0, /* minimum interrupt throttle rate */
230 230 200, /* default interrupt throttle rate */
231 231
232 232 /* function pointers */
233 233 igb_enable_adapter_interrupts_82575,
234 234 igb_setup_msix_82575,
235 235
236 236 /* capabilities */
237 237 (IGB_FLAG_HAS_DCA | /* capability flags */
238 238 IGB_FLAG_VMDQ_POOL),
239 239
240 240 0xffc00000 /* mask for RXDCTL register */
241 241 };
242 242
243 243 static adapter_info_t igb_82576_cap = {
244 244 /* limits */
245 245 16, /* maximum number of rx queues */
246 246 1, /* minimum number of rx queues */
247 247 4, /* default number of rx queues */
248 248 16, /* maximum number of tx queues */
249 249 1, /* minimum number of tx queues */
250 250 4, /* default number of tx queues */
251 251 65535, /* maximum interrupt throttle rate */
252 252 0, /* minimum interrupt throttle rate */
253 253 200, /* default interrupt throttle rate */
254 254
255 255 /* function pointers */
256 256 igb_enable_adapter_interrupts_82576,
257 257 igb_setup_msix_82576,
258 258
259 259 /* capabilities */
260 260 (IGB_FLAG_HAS_DCA | /* capability flags */
261 261 IGB_FLAG_VMDQ_POOL |
262 262 IGB_FLAG_NEED_CTX_IDX),
263 263
264 264 0xffe00000 /* mask for RXDCTL register */
265 265 };
266 266
267 267 static adapter_info_t igb_82580_cap = {
268 268 /* limits */
269 269 8, /* maximum number of rx queues */
270 270 1, /* minimum number of rx queues */
271 271 4, /* default number of rx queues */
272 272 8, /* maximum number of tx queues */
273 273 1, /* minimum number of tx queues */
274 274 4, /* default number of tx queues */
275 275 65535, /* maximum interrupt throttle rate */
276 276 0, /* minimum interrupt throttle rate */
277 277 200, /* default interrupt throttle rate */
278 278
279 279 /* function pointers */
280 280 igb_enable_adapter_interrupts_82580,
281 281 igb_setup_msix_82580,
282 282
283 283 /* capabilities */
284 284 (IGB_FLAG_HAS_DCA | /* capability flags */
285 285 IGB_FLAG_VMDQ_POOL |
286 286 IGB_FLAG_NEED_CTX_IDX),
287 287
288 288 0xffe00000 /* mask for RXDCTL register */
289 289 };
290 290
291 291 static adapter_info_t igb_i350_cap = {
292 292 /* limits */
293 293 8, /* maximum number of rx queues */
294 294 1, /* minimum number of rx queues */
295 295 4, /* default number of rx queues */
296 296 8, /* maximum number of tx queues */
297 297 1, /* minimum number of tx queues */
298 298 4, /* default number of tx queues */
299 299 65535, /* maximum interrupt throttle rate */
300 300 0, /* minimum interrupt throttle rate */
301 301 200, /* default interrupt throttle rate */
302 302
303 303 /* function pointers */
304 304 igb_enable_adapter_interrupts_82580,
305 305 igb_setup_msix_82580,
306 306
307 307 /* capabilities */
308 308 (IGB_FLAG_HAS_DCA | /* capability flags */
309 309 IGB_FLAG_VMDQ_POOL |
310 310 IGB_FLAG_NEED_CTX_IDX),
311 311
312 312 0xffe00000 /* mask for RXDCTL register */
313 313 };
314 314
315 315 static adapter_info_t igb_i210_cap = {
316 316 /* limits */
317 317 4, /* maximum number of rx queues */
318 318 1, /* minimum number of rx queues */
319 319 4, /* default number of rx queues */
320 320 4, /* maximum number of tx queues */
321 321 1, /* minimum number of tx queues */
322 322 4, /* default number of tx queues */
323 323 65535, /* maximum interrupt throttle rate */
324 324 0, /* minimum interrupt throttle rate */
325 325 200, /* default interrupt throttle rate */
326 326
327 327 /* function pointers */
328 328 igb_enable_adapter_interrupts_82580,
329 329 igb_setup_msix_82580,
330 330
331 331 /* capabilities */
332 332 (IGB_FLAG_HAS_DCA | /* capability flags */
333 333 IGB_FLAG_VMDQ_POOL |
334 334 IGB_FLAG_NEED_CTX_IDX),
335 335
336 336 0xfff00000 /* mask for RXDCTL register */
337 337 };
338 338
339 339 static adapter_info_t igb_i354_cap = {
340 340 /* limits */
341 341 8, /* maximum number of rx queues */
342 342 1, /* minimum number of rx queues */
343 343 4, /* default number of rx queues */
344 344 8, /* maximum number of tx queues */
345 345 1, /* minimum number of tx queues */
346 346 4, /* default number of tx queues */
347 347 65535, /* maximum interrupt throttle rate */
348 348 0, /* minimum interrupt throttle rate */
349 349 200, /* default interrupt throttle rate */
350 350
351 351 /* function pointers */
352 352 igb_enable_adapter_interrupts_82580,
353 353 igb_setup_msix_82580,
354 354
355 355 /* capabilities */
356 356 (IGB_FLAG_HAS_DCA | /* capability flags */
357 357 IGB_FLAG_VMDQ_POOL |
358 358 IGB_FLAG_NEED_CTX_IDX),
359 359
360 360 0xfff00000 /* mask for RXDCTL register */
361 361 };
362 362
363 363 /*
364 364 * Module Initialization Functions
365 365 */
366 366
367 367 int
368 368 _init(void)
369 369 {
370 370 int status;
371 371
372 372 mac_init_ops(&igb_dev_ops, MODULE_NAME);
373 373
374 374 status = mod_install(&igb_modlinkage);
375 375
376 376 if (status != DDI_SUCCESS) {
377 377 mac_fini_ops(&igb_dev_ops);
378 378 }
379 379
380 380 return (status);
381 381 }
382 382
383 383 int
384 384 _fini(void)
385 385 {
386 386 int status;
387 387
388 388 status = mod_remove(&igb_modlinkage);
389 389
390 390 if (status == DDI_SUCCESS) {
391 391 mac_fini_ops(&igb_dev_ops);
392 392 }
393 393
394 394 return (status);
395 395
396 396 }
397 397
398 398 int
399 399 _info(struct modinfo *modinfop)
400 400 {
401 401 int status;
402 402
403 403 status = mod_info(&igb_modlinkage, modinfop);
404 404
405 405 return (status);
406 406 }
407 407
408 408 /*
409 409 * igb_attach - driver attach
410 410 *
411 411 * This function is the device specific initialization entry
412 412 * point. This entry point is required and must be written.
413 413 * The DDI_ATTACH command must be provided in the attach entry
414 414 * point. When attach() is called with cmd set to DDI_ATTACH,
415 415 * all normal kernel services (such as kmem_alloc(9F)) are
416 416 * available for use by the driver.
417 417 *
418 418 * The attach() function will be called once for each instance
419 419 * of the device on the system with cmd set to DDI_ATTACH.
420 420 * Until attach() succeeds, the only driver entry points which
421 421 * may be called are open(9E) and getinfo(9E).
422 422 */
423 423 static int
424 424 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
425 425 {
426 426 igb_t *igb;
427 427 struct igb_osdep *osdep;
428 428 struct e1000_hw *hw;
429 429 int instance;
430 430
431 431 /*
432 432 * Check the command and perform corresponding operations
433 433 */
434 434 switch (cmd) {
435 435 default:
436 436 return (DDI_FAILURE);
437 437
438 438 case DDI_RESUME:
439 439 return (igb_resume(devinfo));
440 440
441 441 case DDI_ATTACH:
442 442 break;
443 443 }
444 444
445 445 /* Get the device instance */
446 446 instance = ddi_get_instance(devinfo);
447 447
448 448 /* Allocate memory for the instance data structure */
449 449 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP);
450 450
451 451 igb->dip = devinfo;
452 452 igb->instance = instance;
453 453
454 454 hw = &igb->hw;
455 455 osdep = &igb->osdep;
456 456 hw->back = osdep;
457 457 osdep->igb = igb;
458 458
459 459 /* Attach the instance pointer to the dev_info data structure */
460 460 ddi_set_driver_private(devinfo, igb);
461 461
462 462
463 463 /* Initialize for fma support */
464 464 igb->fm_capabilities = igb_get_prop(igb, "fm-capable",
465 465 0, 0x0f,
466 466 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
467 467 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
468 468 igb_fm_init(igb);
469 469 igb->attach_progress |= ATTACH_PROGRESS_FMINIT;
470 470
471 471 /*
472 472 * Map PCI config space registers
473 473 */
474 474 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
475 475 igb_log(igb, IGB_LOG_ERROR, "Failed to map PCI configurations");
476 476 goto attach_fail;
477 477 }
478 478 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
479 479
480 480 /*
481 481 * Identify the chipset family
482 482 */
483 483 if (igb_identify_hardware(igb) != IGB_SUCCESS) {
484 484 igb_log(igb, IGB_LOG_ERROR, "Failed to identify hardware");
485 485 goto attach_fail;
486 486 }
487 487
488 488 /*
489 489 * Map device registers
490 490 */
491 491 if (igb_regs_map(igb) != IGB_SUCCESS) {
492 492 igb_log(igb, IGB_LOG_ERROR, "Failed to map device registers");
493 493 goto attach_fail;
494 494 }
495 495 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
496 496
497 497 /*
498 498 * Initialize driver parameters
499 499 */
500 500 igb_init_properties(igb);
501 501 igb->attach_progress |= ATTACH_PROGRESS_PROPS;
502 502
503 503 /*
504 504 * Allocate interrupts
505 505 */
506 506 if (igb_alloc_intrs(igb) != IGB_SUCCESS) {
507 507 igb_log(igb, IGB_LOG_ERROR, "Failed to allocate interrupts");
508 508 goto attach_fail;
509 509 }
510 510 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
511 511
512 512 /*
513 513 * Allocate rx/tx rings based on the ring numbers.
514 514 * The actual numbers of rx/tx rings are decided by the number of
515 515 * allocated interrupt vectors, so we should allocate the rings after
516 516 * interrupts are allocated.
517 517 */
518 518 if (igb_alloc_rings(igb) != IGB_SUCCESS) {
519 519 igb_log(igb, IGB_LOG_ERROR,
520 520 "Failed to allocate rx/tx rings or groups");
521 521 goto attach_fail;
522 522 }
523 523 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS;
524 524
525 525 /*
526 526 * Add interrupt handlers
527 527 */
528 528 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) {
529 529 igb_log(igb, IGB_LOG_ERROR, "Failed to add interrupt handlers");
530 530 goto attach_fail;
531 531 }
532 532 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
533 533
534 534 /*
535 535 * Initialize driver parameters
536 536 */
537 537 if (igb_init_driver_settings(igb) != IGB_SUCCESS) {
538 538 igb_log(igb, IGB_LOG_ERROR,
539 539 "Failed to initialize driver settings");
540 540 goto attach_fail;
541 541 }
542 542
543 543 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) {
544 544 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
545 545 goto attach_fail;
546 546 }
547 547
548 548 /*
549 549 * Initialize mutexes for this device.
550 550 * Do this before enabling the interrupt handler and
551 551 * register the softint to avoid the condition where
552 552 * interrupt handler can try using uninitialized mutex
553 553 */
554 554 igb_init_locks(igb);
555 555 igb->attach_progress |= ATTACH_PROGRESS_LOCKS;
556 556
557 557 /*
558 558 * Initialize the adapter
559 559 */
560 560 if (igb_init(igb) != IGB_SUCCESS) {
561 561 igb_log(igb, IGB_LOG_ERROR, "Failed to initialize adapter");
562 562 goto attach_fail;
563 563 }
564 564 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
565 565
566 566 /*
567 567 * Initialize statistics
568 568 */
569 569 if (igb_init_stats(igb) != IGB_SUCCESS) {
570 570 igb_log(igb, IGB_LOG_ERROR, "Failed to initialize statistics");
571 571 goto attach_fail;
572 572 }
573 573 igb->attach_progress |= ATTACH_PROGRESS_STATS;
574 574
575 575 /*
576 576 * Register the driver to the MAC
577 577 */
578 578 if (igb_register_mac(igb) != IGB_SUCCESS) {
579 579 igb_log(igb, IGB_LOG_ERROR, "Failed to register MAC");
580 580 goto attach_fail;
581 581 }
582 582 igb->attach_progress |= ATTACH_PROGRESS_MAC;
583 583
584 584 /*
585 585 * Now that mutex locks are initialized, and the chip is also
586 586 * initialized, enable interrupts.
587 587 */
588 588 if (igb_enable_intrs(igb) != IGB_SUCCESS) {
589 589 igb_log(igb, IGB_LOG_ERROR, "Failed to enable DDI interrupts");
590 590 goto attach_fail;
591 591 }
592 592 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
593 593
594 594 igb_log(igb, IGB_LOG_INFO, "%s", igb_version);
595 595 atomic_or_32(&igb->igb_state, IGB_INITIALIZED);
596 596
597 597 /*
598 598 * Newer models have Energy Efficient Ethernet, let's disable this by
599 599 * default.
600 600 */
601 601 if (igb->hw.mac.type == e1000_i350)
602 602 (void) e1000_set_eee_i350(&igb->hw, B_FALSE, B_FALSE);
603 603 else if (igb->hw.mac.type == e1000_i354)
604 604 (void) e1000_set_eee_i354(&igb->hw, B_FALSE, B_FALSE);
605 605
606 606 return (DDI_SUCCESS);
607 607
608 608 attach_fail:
609 609 igb_unconfigure(devinfo, igb);
610 610 return (DDI_FAILURE);
611 611 }
612 612
613 613 /*
614 614 * igb_detach - driver detach
615 615 *
616 616 * The detach() function is the complement of the attach routine.
617 617 * If cmd is set to DDI_DETACH, detach() is used to remove the
618 618 * state associated with a given instance of a device node
619 619 * prior to the removal of that instance from the system.
620 620 *
621 621 * The detach() function will be called once for each instance
622 622 * of the device for which there has been a successful attach()
623 623 * once there are no longer any opens on the device.
624 624 *
625 625 * Interrupts routine are disabled, All memory allocated by this
626 626 * driver are freed.
627 627 */
628 628 static int
629 629 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
630 630 {
631 631 igb_t *igb;
632 632
633 633 /*
634 634 * Check detach command
635 635 */
636 636 switch (cmd) {
637 637 default:
638 638 return (DDI_FAILURE);
639 639
640 640 case DDI_SUSPEND:
641 641 return (igb_suspend(devinfo));
642 642
643 643 case DDI_DETACH:
644 644 break;
645 645 }
646 646
647 647
648 648 /*
649 649 * Get the pointer to the driver private data structure
650 650 */
651 651 igb = (igb_t *)ddi_get_driver_private(devinfo);
652 652 if (igb == NULL)
653 653 return (DDI_FAILURE);
654 654
655 655 /*
656 656 * Unregister MAC. If failed, we have to fail the detach
657 657 */
658 658 if (mac_unregister(igb->mac_hdl) != 0) {
659 659 igb_log(igb, IGB_LOG_ERROR, "Failed to unregister MAC");
660 660 return (DDI_FAILURE);
661 661 }
662 662 igb->attach_progress &= ~ATTACH_PROGRESS_MAC;
663 663
664 664 /*
665 665 * If the device is still running, it needs to be stopped first.
666 666 * This check is necessary because under some specific circumstances,
667 667 * the detach routine can be called without stopping the interface
668 668 * first.
669 669 */
670 670 mutex_enter(&igb->gen_lock);
671 671 if (igb->igb_state & IGB_STARTED) {
672 672 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
673 673 igb_stop(igb, B_TRUE);
674 674 mutex_exit(&igb->gen_lock);
675 675 /* Disable and stop the watchdog timer */
676 676 igb_disable_watchdog_timer(igb);
677 677 } else
678 678 mutex_exit(&igb->gen_lock);
679 679
680 680 /*
681 681 * Check if there are still rx buffers held by the upper layer.
682 682 * If so, fail the detach.
683 683 */
684 684 if (!igb_rx_drain(igb))
685 685 return (DDI_FAILURE);
686 686
687 687 /*
688 688 * Do the remaining unconfigure routines
689 689 */
690 690 igb_unconfigure(devinfo, igb);
691 691
692 692 return (DDI_SUCCESS);
693 693 }
694 694
695 695 /*
696 696 * quiesce(9E) entry point.
697 697 *
698 698 * This function is called when the system is single-threaded at high
699 699 * PIL with preemption disabled. Therefore, this function must not be
700 700 * blocked.
701 701 *
702 702 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
703 703 * DDI_FAILURE indicates an error condition and should almost never happen.
704 704 */
705 705 static int
706 706 igb_quiesce(dev_info_t *devinfo)
707 707 {
708 708 igb_t *igb;
709 709 struct e1000_hw *hw;
710 710
711 711 igb = (igb_t *)ddi_get_driver_private(devinfo);
712 712
713 713 if (igb == NULL)
714 714 return (DDI_FAILURE);
715 715
716 716 hw = &igb->hw;
717 717
718 718 /*
719 719 * Disable the adapter interrupts
720 720 */
721 721 igb_disable_adapter_interrupts(igb);
722 722
723 723 /* Tell firmware driver is no longer in control */
724 724 igb_release_driver_control(hw);
725 725
726 726 /*
727 727 * Reset the chipset
728 728 */
729 729 (void) e1000_reset_hw(hw);
730 730
731 731 /*
732 732 * Reset PHY if possible
733 733 */
734 734 if (e1000_check_reset_block(hw) == E1000_SUCCESS)
735 735 (void) e1000_phy_hw_reset(hw);
736 736
737 737 return (DDI_SUCCESS);
738 738 }
739 739
740 740 /*
741 741 * igb_unconfigure - release all resources held by this instance
742 742 */
743 743 static void
744 744 igb_unconfigure(dev_info_t *devinfo, igb_t *igb)
745 745 {
746 746 /*
747 747 * Disable interrupt
748 748 */
749 749 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
750 750 (void) igb_disable_intrs(igb);
751 751 }
752 752
753 753 /*
754 754 * Unregister MAC
755 755 */
756 756 if (igb->attach_progress & ATTACH_PROGRESS_MAC) {
757 757 (void) mac_unregister(igb->mac_hdl);
758 758 }
759 759
760 760 /*
761 761 * Free statistics
762 762 */
763 763 if (igb->attach_progress & ATTACH_PROGRESS_STATS) {
764 764 kstat_delete((kstat_t *)igb->igb_ks);
765 765 }
766 766
767 767 /*
768 768 * Remove interrupt handlers
769 769 */
770 770 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
771 771 igb_rem_intr_handlers(igb);
772 772 }
773 773
774 774 /*
775 775 * Remove interrupts
776 776 */
777 777 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) {
778 778 igb_rem_intrs(igb);
779 779 }
780 780
781 781 /*
782 782 * Remove driver properties
783 783 */
784 784 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) {
785 785 (void) ddi_prop_remove_all(devinfo);
786 786 }
787 787
788 788 /*
789 789 * Stop the adapter
790 790 */
791 791 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) {
792 792 mutex_enter(&igb->gen_lock);
793 793 igb_stop_adapter(igb);
794 794 mutex_exit(&igb->gen_lock);
795 795 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
796 796 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED);
797 797 }
798 798
799 799 /*
800 800 * Free multicast table
801 801 */
802 802 igb_release_multicast(igb);
803 803
804 804 /*
805 805 * Free register handle
806 806 */
807 807 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
808 808 if (igb->osdep.reg_handle != NULL)
809 809 ddi_regs_map_free(&igb->osdep.reg_handle);
810 810 }
811 811
812 812 /*
813 813 * Free PCI config handle
814 814 */
815 815 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
816 816 if (igb->osdep.cfg_handle != NULL)
817 817 pci_config_teardown(&igb->osdep.cfg_handle);
818 818 }
819 819
820 820 /*
821 821 * Free locks
822 822 */
823 823 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) {
824 824 igb_destroy_locks(igb);
825 825 }
826 826
827 827 /*
828 828 * Free the rx/tx rings
829 829 */
830 830 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) {
831 831 igb_free_rings(igb);
832 832 }
833 833
834 834 /*
835 835 * Remove FMA
836 836 */
837 837 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) {
838 838 igb_fm_fini(igb);
839 839 }
840 840
841 841 /*
842 842 * Free the driver data structure
843 843 */
844 844 kmem_free(igb, sizeof (igb_t));
845 845
846 846 ddi_set_driver_private(devinfo, NULL);
847 847 }
848 848
849 849 /*
850 850 * igb_register_mac - Register the driver and its function pointers with
851 851 * the GLD interface
852 852 */
853 853 static int
854 854 igb_register_mac(igb_t *igb)
855 855 {
856 856 struct e1000_hw *hw = &igb->hw;
857 857 mac_register_t *mac;
858 858 int status;
859 859
860 860 if ((mac = mac_alloc(MAC_VERSION)) == NULL)
861 861 return (IGB_FAILURE);
862 862
863 863 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
864 864 mac->m_driver = igb;
865 865 mac->m_dip = igb->dip;
866 866 mac->m_src_addr = hw->mac.addr;
867 867 mac->m_callbacks = &igb_m_callbacks;
868 868 mac->m_min_sdu = 0;
869 869 mac->m_max_sdu = igb->max_frame_size -
870 870 sizeof (struct ether_vlan_header) - ETHERFCSL;
871 871 mac->m_margin = VLAN_TAGSZ;
872 872 mac->m_priv_props = igb_priv_props;
873 873 mac->m_v12n = MAC_VIRT_LEVEL1;
874 874
875 875 status = mac_register(mac, &igb->mac_hdl);
876 876
877 877 mac_free(mac);
878 878
879 879 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE);
880 880 }
881 881
882 882 /*
883 883 * igb_identify_hardware - Identify the type of the chipset
884 884 */
885 885 static int
886 886 igb_identify_hardware(igb_t *igb)
887 887 {
888 888 struct e1000_hw *hw = &igb->hw;
889 889 struct igb_osdep *osdep = &igb->osdep;
890 890
891 891 /*
892 892 * Get the device id
893 893 */
894 894 hw->vendor_id =
895 895 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
896 896 hw->device_id =
897 897 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
898 898 hw->revision_id =
899 899 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
900 900 hw->subsystem_device_id =
901 901 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
902 902 hw->subsystem_vendor_id =
903 903 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
904 904
905 905 /*
906 906 * Set the mac type of the adapter based on the device id
907 907 */
908 908 if (e1000_set_mac_type(hw) != E1000_SUCCESS) {
909 909 return (IGB_FAILURE);
910 910 }
911 911
912 912 /*
913 913 * Install adapter capabilities based on mac type
914 914 */
915 915 switch (hw->mac.type) {
916 916 case e1000_82575:
917 917 igb->capab = &igb_82575_cap;
918 918 break;
919 919 case e1000_82576:
920 920 igb->capab = &igb_82576_cap;
921 921 break;
922 922 case e1000_82580:
923 923 igb->capab = &igb_82580_cap;
924 924 break;
925 925 case e1000_i350:
926 926 igb->capab = &igb_i350_cap;
927 927 break;
928 928 case e1000_i210:
929 929 case e1000_i211:
930 930 igb->capab = &igb_i210_cap;
931 931 break;
932 932 case e1000_i354:
933 933 igb->capab = &igb_i354_cap;
934 934 break;
935 935 default:
936 936 return (IGB_FAILURE);
937 937 }
938 938
939 939 return (IGB_SUCCESS);
940 940 }
941 941
942 942 /*
943 943 * igb_regs_map - Map the device registers
944 944 */
945 945 static int
946 946 igb_regs_map(igb_t *igb)
947 947 {
948 948 dev_info_t *devinfo = igb->dip;
949 949 struct e1000_hw *hw = &igb->hw;
950 950 struct igb_osdep *osdep = &igb->osdep;
951 951 off_t mem_size;
952 952
953 953 /*
954 954 * First get the size of device registers to be mapped.
955 955 */
956 956 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) !=
957 957 DDI_SUCCESS) {
958 958 return (IGB_FAILURE);
959 959 }
960 960
961 961 /*
962 962 * Call ddi_regs_map_setup() to map registers
963 963 */
964 964 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET,
965 965 (caddr_t *)&hw->hw_addr, 0,
966 966 mem_size, &igb_regs_acc_attr,
967 967 &osdep->reg_handle)) != DDI_SUCCESS) {
968 968 return (IGB_FAILURE);
969 969 }
970 970
971 971 return (IGB_SUCCESS);
972 972 }
973 973
974 974 /*
975 975 * igb_init_properties - Initialize driver properties
976 976 */
977 977 static void
978 978 igb_init_properties(igb_t *igb)
979 979 {
980 980 /*
981 981 * Get conf file properties, including link settings
982 982 * jumbo frames, ring number, descriptor number, etc.
983 983 */
984 984 igb_get_conf(igb);
985 985 }
986 986
987 987 /*
988 988 * igb_init_driver_settings - Initialize driver settings
989 989 *
990 990 * The settings include hardware function pointers, bus information,
991 991 * rx/tx rings settings, link state, and any other parameters that
992 992 * need to be setup during driver initialization.
993 993 */
994 994 static int
995 995 igb_init_driver_settings(igb_t *igb)
996 996 {
997 997 struct e1000_hw *hw = &igb->hw;
998 998 igb_rx_ring_t *rx_ring;
999 999 igb_tx_ring_t *tx_ring;
1000 1000 uint32_t rx_size;
1001 1001 uint32_t tx_size;
1002 1002 int i;
1003 1003
1004 1004 /*
1005 1005 * Initialize chipset specific hardware function pointers
1006 1006 */
1007 1007 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
1008 1008 return (IGB_FAILURE);
1009 1009 }
1010 1010
1011 1011 /*
1012 1012 * Get bus information
1013 1013 */
1014 1014 if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
1015 1015 return (IGB_FAILURE);
1016 1016 }
1017 1017
1018 1018 /*
1019 1019 * Get the system page size
1020 1020 */
1021 1021 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1);
1022 1022
1023 1023 /*
1024 1024 * Set rx buffer size
1025 1025 * The IP header alignment room is counted in the calculation.
1026 1026 * The rx buffer size is in unit of 1K that is required by the
1027 1027 * chipset hardware.
1028 1028 */
1029 1029 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM;
1030 1030 igb->rx_buf_size = ((rx_size >> 10) +
1031 1031 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
1032 1032
1033 1033 /*
1034 1034 * Set tx buffer size
1035 1035 */
1036 1036 tx_size = igb->max_frame_size;
1037 1037 igb->tx_buf_size = ((tx_size >> 10) +
1038 1038 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
1039 1039
1040 1040 /*
1041 1041 * Initialize rx/tx rings parameters
1042 1042 */
1043 1043 for (i = 0; i < igb->num_rx_rings; i++) {
1044 1044 rx_ring = &igb->rx_rings[i];
1045 1045 rx_ring->index = i;
1046 1046 rx_ring->igb = igb;
1047 1047 }
1048 1048
1049 1049 for (i = 0; i < igb->num_tx_rings; i++) {
1050 1050 tx_ring = &igb->tx_rings[i];
1051 1051 tx_ring->index = i;
1052 1052 tx_ring->igb = igb;
1053 1053 if (igb->tx_head_wb_enable)
1054 1054 tx_ring->tx_recycle = igb_tx_recycle_head_wb;
1055 1055 else
1056 1056 tx_ring->tx_recycle = igb_tx_recycle_legacy;
1057 1057
1058 1058 tx_ring->ring_size = igb->tx_ring_size;
1059 1059 tx_ring->free_list_size = igb->tx_ring_size +
1060 1060 (igb->tx_ring_size >> 1);
1061 1061 }
1062 1062
1063 1063 /*
1064 1064 * Initialize values of interrupt throttling rates
1065 1065 */
1066 1066 for (i = 1; i < MAX_NUM_EITR; i++)
1067 1067 igb->intr_throttling[i] = igb->intr_throttling[0];
1068 1068
1069 1069 /*
1070 1070 * The initial link state should be "unknown"
1071 1071 */
1072 1072 igb->link_state = LINK_STATE_UNKNOWN;
1073 1073
1074 1074 return (IGB_SUCCESS);
1075 1075 }
1076 1076
1077 1077 /*
1078 1078 * igb_init_locks - Initialize locks
1079 1079 */
1080 1080 static void
1081 1081 igb_init_locks(igb_t *igb)
1082 1082 {
1083 1083 igb_rx_ring_t *rx_ring;
1084 1084 igb_tx_ring_t *tx_ring;
1085 1085 int i;
1086 1086
1087 1087 for (i = 0; i < igb->num_rx_rings; i++) {
1088 1088 rx_ring = &igb->rx_rings[i];
1089 1089 mutex_init(&rx_ring->rx_lock, NULL,
1090 1090 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1091 1091 }
1092 1092
1093 1093 for (i = 0; i < igb->num_tx_rings; i++) {
1094 1094 tx_ring = &igb->tx_rings[i];
1095 1095 mutex_init(&tx_ring->tx_lock, NULL,
1096 1096 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1097 1097 mutex_init(&tx_ring->recycle_lock, NULL,
1098 1098 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1099 1099 mutex_init(&tx_ring->tcb_head_lock, NULL,
1100 1100 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1101 1101 mutex_init(&tx_ring->tcb_tail_lock, NULL,
1102 1102 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1103 1103 }
1104 1104
1105 1105 mutex_init(&igb->gen_lock, NULL,
1106 1106 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1107 1107
1108 1108 mutex_init(&igb->watchdog_lock, NULL,
1109 1109 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1110 1110
1111 1111 mutex_init(&igb->link_lock, NULL,
1112 1112 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1113 1113 }
1114 1114
1115 1115 /*
1116 1116 * igb_destroy_locks - Destroy locks
1117 1117 */
1118 1118 static void
1119 1119 igb_destroy_locks(igb_t *igb)
1120 1120 {
1121 1121 igb_rx_ring_t *rx_ring;
1122 1122 igb_tx_ring_t *tx_ring;
1123 1123 int i;
1124 1124
1125 1125 for (i = 0; i < igb->num_rx_rings; i++) {
1126 1126 rx_ring = &igb->rx_rings[i];
1127 1127 mutex_destroy(&rx_ring->rx_lock);
1128 1128 }
1129 1129
1130 1130 for (i = 0; i < igb->num_tx_rings; i++) {
1131 1131 tx_ring = &igb->tx_rings[i];
1132 1132 mutex_destroy(&tx_ring->tx_lock);
1133 1133 mutex_destroy(&tx_ring->recycle_lock);
1134 1134 mutex_destroy(&tx_ring->tcb_head_lock);
1135 1135 mutex_destroy(&tx_ring->tcb_tail_lock);
1136 1136 }
1137 1137
1138 1138 mutex_destroy(&igb->gen_lock);
1139 1139 mutex_destroy(&igb->watchdog_lock);
1140 1140 mutex_destroy(&igb->link_lock);
1141 1141 }
1142 1142
1143 1143 static int
1144 1144 igb_resume(dev_info_t *devinfo)
1145 1145 {
1146 1146 igb_t *igb;
1147 1147
1148 1148 igb = (igb_t *)ddi_get_driver_private(devinfo);
1149 1149 if (igb == NULL)
1150 1150 return (DDI_FAILURE);
1151 1151
1152 1152 mutex_enter(&igb->gen_lock);
1153 1153
1154 1154 /*
1155 1155 * Enable interrupts
1156 1156 */
1157 1157 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1158 1158 if (igb_enable_intrs(igb) != IGB_SUCCESS) {
1159 1159 igb_log(igb, IGB_LOG_ERROR,
1160 1160 "Failed to enable DDI interrupts");
1161 1161 mutex_exit(&igb->gen_lock);
1162 1162 return (DDI_FAILURE);
1163 1163 }
1164 1164 }
1165 1165
1166 1166 if (igb->igb_state & IGB_STARTED) {
1167 1167 if (igb_start(igb, B_FALSE) != IGB_SUCCESS) {
1168 1168 mutex_exit(&igb->gen_lock);
1169 1169 return (DDI_FAILURE);
1170 1170 }
1171 1171
1172 1172 /*
1173 1173 * Enable and start the watchdog timer
1174 1174 */
1175 1175 igb_enable_watchdog_timer(igb);
1176 1176 }
1177 1177
1178 1178 atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED);
1179 1179
1180 1180 mutex_exit(&igb->gen_lock);
1181 1181
1182 1182 return (DDI_SUCCESS);
1183 1183 }
1184 1184
1185 1185 static int
1186 1186 igb_suspend(dev_info_t *devinfo)
1187 1187 {
1188 1188 igb_t *igb;
1189 1189
1190 1190 igb = (igb_t *)ddi_get_driver_private(devinfo);
1191 1191 if (igb == NULL)
1192 1192 return (DDI_FAILURE);
1193 1193
1194 1194 mutex_enter(&igb->gen_lock);
1195 1195
1196 1196 atomic_or_32(&igb->igb_state, IGB_SUSPENDED);
1197 1197
1198 1198 /*
1199 1199 * Disable interrupts
1200 1200 */
1201 1201 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1202 1202 (void) igb_disable_intrs(igb);
1203 1203 }
1204 1204
1205 1205 if (!(igb->igb_state & IGB_STARTED)) {
1206 1206 mutex_exit(&igb->gen_lock);
1207 1207 return (DDI_SUCCESS);
1208 1208 }
1209 1209
1210 1210 igb_stop(igb, B_FALSE);
1211 1211
1212 1212 mutex_exit(&igb->gen_lock);
1213 1213
1214 1214 /*
1215 1215 * Disable and stop the watchdog timer
1216 1216 */
1217 1217 igb_disable_watchdog_timer(igb);
1218 1218
1219 1219 return (DDI_SUCCESS);
1220 1220 }
1221 1221
1222 1222 static int
1223 1223 igb_init(igb_t *igb)
1224 1224 {
1225 1225 mutex_enter(&igb->gen_lock);
1226 1226
1227 1227 /*
1228 1228 * Initilize the adapter
1229 1229 */
1230 1230 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1231 1231 mutex_exit(&igb->gen_lock);
1232 1232 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1233 1233 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1234 1234 return (IGB_FAILURE);
1235 1235 }
1236 1236
1237 1237 mutex_exit(&igb->gen_lock);
1238 1238
1239 1239 return (IGB_SUCCESS);
1240 1240 }
1241 1241
1242 1242 /*
1243 1243 * igb_init_mac_address - Initialize the default MAC address
1244 1244 *
1245 1245 * On success, the MAC address is entered in the igb->hw.mac.addr
1246 1246 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive
1247 1247 * address register.
1248 1248 *
1249 1249 * Important side effects:
1250 1250 * 1. adapter is reset - this is required to put it in a known state.
1251 1251 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where
1252 1252 * MAC address and all default settings are stored, so a valid checksum
1253 1253 * is required.
1254 1254 */
1255 1255 static int
1256 1256 igb_init_mac_address(igb_t *igb)
1257 1257 {
1258 1258 struct e1000_hw *hw = &igb->hw;
1259 1259
1260 1260 ASSERT(mutex_owned(&igb->gen_lock));
1261 1261
1262 1262 /*
1263 1263 * Reset chipset to put the hardware in a known state
1264 1264 * before we try to get MAC address from NVM.
1265 1265 */
1266 1266 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1267 1267 igb_log(igb, IGB_LOG_ERROR, "Adapter reset failed.");
1268 1268 goto init_mac_fail;
1269 1269 }
1270 1270
1271 1271 /*
1272 1272 * NVM validation
1273 1273 */
1274 1274 if (((igb->hw.mac.type != e1000_i210) &&
1275 1275 (igb->hw.mac.type != e1000_i211)) &&
1276 1276 (e1000_validate_nvm_checksum(hw) < 0)) {
1277 1277 /*
1278 1278 * Some PCI-E parts fail the first check due to
1279 1279 * the link being in sleep state. Call it again,
1280 1280 * if it fails a second time its a real issue.
1281 1281 */
1282 1282 if (e1000_validate_nvm_checksum(hw) < 0) {
1283 1283 igb_log(igb, IGB_LOG_ERROR,
1284 1284 "Invalid NVM checksum. Please contact "
1285 1285 "the vendor to update the NVM.");
1286 1286 goto init_mac_fail;
1287 1287 }
1288 1288 }
1289 1289
1290 1290 /*
1291 1291 * Get the mac address
1292 1292 * This function should handle SPARC case correctly.
1293 1293 */
1294 1294 if (!igb_find_mac_address(igb)) {
1295 1295 igb_log(igb, IGB_LOG_ERROR, "Failed to get the mac address");
1296 1296 goto init_mac_fail;
1297 1297 }
1298 1298
1299 1299 /* Validate mac address */
1300 1300 if (!is_valid_mac_addr(hw->mac.addr)) {
1301 1301 igb_log(igb, IGB_LOG_ERROR, "Invalid mac address");
1302 1302 goto init_mac_fail;
1303 1303 }
1304 1304
1305 1305 return (IGB_SUCCESS);
1306 1306
1307 1307 init_mac_fail:
1308 1308 return (IGB_FAILURE);
1309 1309 }
1310 1310
1311 1311 /*
1312 1312 * igb_init_adapter - Initialize the adapter
1313 1313 */
1314 1314 static int
1315 1315 igb_init_adapter(igb_t *igb)
1316 1316 {
1317 1317 struct e1000_hw *hw = &igb->hw;
1318 1318 uint32_t pba;
1319 1319 int oemid[2];
1320 1320 uint16_t nvmword;
1321 1321 uint32_t hwm;
1322 1322 uint32_t default_mtu;
1323 1323 u8 pbanum[E1000_PBANUM_LENGTH];
1324 1324 char eepromver[5]; /* f.ff */
1325 1325 int i;
1326 1326
1327 1327 ASSERT(mutex_owned(&igb->gen_lock));
1328 1328
1329 1329 /*
1330 1330 * In order to obtain the default MAC address, this will reset the
1331 1331 * adapter and validate the NVM that the address and many other
1332 1332 * default settings come from.
1333 1333 */
1334 1334 if (igb_init_mac_address(igb) != IGB_SUCCESS) {
1335 1335 igb_log(igb, IGB_LOG_ERROR, "Failed to initialize MAC address");
1336 1336 goto init_adapter_fail;
1337 1337 }
1338 1338
1339 1339 /*
1340 1340 * Packet Buffer Allocation (PBA)
1341 1341 * Writing PBA sets the receive portion of the buffer
1342 1342 * the remainder is used for the transmit buffer.
1343 1343 */
1344 1344 switch (hw->mac.type) {
1345 1345 case e1000_82575:
1346 1346 pba = E1000_PBA_32K;
1347 1347 break;
1348 1348 case e1000_82576:
1349 1349 pba = E1000_READ_REG(hw, E1000_RXPBS);
1350 1350 pba &= E1000_RXPBS_SIZE_MASK_82576;
1351 1351 break;
1352 1352 case e1000_82580:
1353 1353 case e1000_i350:
1354 1354 case e1000_i354:
1355 1355 pba = E1000_READ_REG(hw, E1000_RXPBS);
1356 1356 pba = e1000_rxpbs_adjust_82580(pba);
1357 1357 break;
1358 1358 case e1000_i210:
1359 1359 case e1000_i211:
1360 1360 pba = E1000_PBA_34K;
1361 1361 default:
1362 1362 break;
1363 1363 }
1364 1364
1365 1365 /* Special needs in case of Jumbo frames */
1366 1366 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU,
1367 1367 MIN_MTU, MAX_MTU, DEFAULT_MTU);
1368 1368 if ((hw->mac.type == e1000_82575) && (default_mtu > ETHERMTU)) {
1369 1369 u32 tx_space, min_tx, min_rx;
1370 1370 pba = E1000_READ_REG(hw, E1000_PBA);
1371 1371 tx_space = pba >> 16;
1372 1372 pba &= 0xffff;
1373 1373 min_tx = (igb->max_frame_size +
1374 1374 sizeof (struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
1375 1375 min_tx = roundup(min_tx, 1024);
1376 1376 min_tx >>= 10;
1377 1377 min_rx = igb->max_frame_size;
1378 1378 min_rx = roundup(min_rx, 1024);
1379 1379 min_rx >>= 10;
1380 1380 if (tx_space < min_tx &&
1381 1381 ((min_tx - tx_space) < pba)) {
1382 1382 pba = pba - (min_tx - tx_space);
1383 1383 /*
1384 1384 * if short on rx space, rx wins
1385 1385 * and must trump tx adjustment
1386 1386 */
1387 1387 if (pba < min_rx)
1388 1388 pba = min_rx;
1389 1389 }
1390 1390 E1000_WRITE_REG(hw, E1000_PBA, pba);
1391 1391 }
1392 1392
1393 1393 DEBUGOUT1("igb_init: pba=%dK", pba);
1394 1394
1395 1395 /*
1396 1396 * These parameters control the automatic generation (Tx) and
1397 1397 * response (Rx) to Ethernet PAUSE frames.
1398 1398 * - High water mark should allow for at least two frames to be
1399 1399 * received after sending an XOFF.
1400 1400 * - Low water mark works best when it is very near the high water mark.
1401 1401 * This allows the receiver to restart by sending XON when it has
1402 1402 * drained a bit.
1403 1403 */
1404 1404 hwm = min(((pba << 10) * 9 / 10),
1405 1405 ((pba << 10) - 2 * igb->max_frame_size));
1406 1406
1407 1407 if (hw->mac.type < e1000_82576) {
1408 1408 hw->fc.high_water = hwm & 0xFFF8; /* 8-byte granularity */
1409 1409 hw->fc.low_water = hw->fc.high_water - 8;
1410 1410 } else {
1411 1411 hw->fc.high_water = hwm & 0xFFF0; /* 16-byte granularity */
1412 1412 hw->fc.low_water = hw->fc.high_water - 16;
1413 1413 }
1414 1414
1415 1415 hw->fc.pause_time = E1000_FC_PAUSE_TIME;
1416 1416 hw->fc.send_xon = B_TRUE;
1417 1417
1418 1418 (void) e1000_validate_mdi_setting(hw);
1419 1419
1420 1420 /*
1421 1421 * Reset the chipset hardware the second time to put PBA settings
1422 1422 * into effect.
1423 1423 */
1424 1424 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1425 1425 igb_log(igb, IGB_LOG_ERROR, "Second reset failed");
1426 1426 goto init_adapter_fail;
1427 1427 }
1428 1428
1429 1429 /*
1430 1430 * Don't wait for auto-negotiation to complete
1431 1431 */
1432 1432 hw->phy.autoneg_wait_to_complete = B_FALSE;
1433 1433
1434 1434 /*
1435 1435 * Copper options
1436 1436 */
1437 1437 if (hw->phy.media_type == e1000_media_type_copper) {
1438 1438 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
1439 1439 hw->phy.disable_polarity_correction = B_FALSE;
1440 1440 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */
1441 1441 }
1442 1442
1443 1443 /*
1444 1444 * Initialize link settings
1445 1445 */
1446 1446 (void) igb_setup_link(igb, B_FALSE);
1447 1447
1448 1448 /*
1449 1449 * Configure/Initialize hardware
1450 1450 */
1451 1451 if (e1000_init_hw(hw) != E1000_SUCCESS) {
1452 1452 igb_log(igb, IGB_LOG_ERROR, "Failed to initialize hardware");
1453 1453 goto init_adapter_fail;
1454 1454 }
1455 1455
1456 1456 /*
1457 1457 * Start the link setup timer
1458 1458 */
1459 1459 igb_start_link_timer(igb);
1460 1460
1461 1461 /*
1462 1462 * Disable wakeup control by default
1463 1463 */
1464 1464 E1000_WRITE_REG(hw, E1000_WUC, 0);
1465 1465
1466 1466 /*
1467 1467 * Record phy info in hw struct
1468 1468 */
1469 1469 (void) e1000_get_phy_info(hw);
1470 1470
1471 1471 /*
1472 1472 * Make sure driver has control
1473 1473 */
1474 1474 igb_get_driver_control(hw);
1475 1475
1476 1476 /*
1477 1477 * Restore LED settings to the default from EEPROM
1478 1478 * to meet the standard for Sun platforms.
1479 1479 */
1480 1480 (void) e1000_cleanup_led(hw);
1481 1481
1482 1482 /*
1483 1483 * Setup MSI-X interrupts
1484 1484 */
1485 1485 if (igb->intr_type == DDI_INTR_TYPE_MSIX)
1486 1486 igb->capab->setup_msix(igb);
1487 1487
1488 1488 /*
1489 1489 * Initialize unicast addresses.
1490 1490 */
1491 1491 igb_init_unicst(igb);
1492 1492
1493 1493 /*
1494 1494 * Setup and initialize the mctable structures.
1495 1495 */
1496 1496 igb_setup_multicst(igb);
1497 1497
1498 1498 /*
1499 1499 * Set interrupt throttling rate
1500 1500 */
1501 1501 for (i = 0; i < igb->intr_cnt; i++)
1502 1502 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]);
1503 1503
1504 1504 /*
1505 1505 * Read identifying information and place in devinfo.
1506 1506 */
1507 1507 nvmword = 0xffff;
1508 1508 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_0, 1, &nvmword);
1509 1509 oemid[0] = (int)nvmword;
1510 1510 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_1, 1, &nvmword);
1511 1511 oemid[1] = (int)nvmword;
1512 1512 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, igb->dip,
1513 1513 "oem-identifier", oemid, 2);
1514 1514
1515 1515 pbanum[0] = '\0';
1516 1516 (void) e1000_read_pba_string(&igb->hw, pbanum, sizeof (pbanum));
1517 1517 if (*pbanum != '\0') {
1518 1518 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip,
1519 1519 "printed-board-assembly", (char *)pbanum);
1520 1520 }
1521 1521
1522 1522 nvmword = 0xffff;
1523 1523 (void) e1000_read_nvm(&igb->hw, NVM_VERSION, 1, &nvmword);
1524 1524 if ((nvmword & 0xf00) == 0) {
1525 1525 (void) snprintf(eepromver, sizeof (eepromver), "%x.%x",
1526 1526 (nvmword & 0xf000) >> 12, (nvmword & 0xff));
1527 1527 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip,
1528 1528 "nvm-version", eepromver);
1529 1529 }
1530 1530
1531 1531 /*
1532 1532 * Save the state of the phy
1533 1533 */
1534 1534 igb_get_phy_state(igb);
1535 1535
1536 1536 igb_param_sync(igb);
1537 1537
1538 1538 return (IGB_SUCCESS);
1539 1539
1540 1540 init_adapter_fail:
1541 1541 /*
1542 1542 * Reset PHY if possible
1543 1543 */
1544 1544 if (e1000_check_reset_block(hw) == E1000_SUCCESS)
1545 1545 (void) e1000_phy_hw_reset(hw);
1546 1546
1547 1547 return (IGB_FAILURE);
1548 1548 }
1549 1549
1550 1550 /*
1551 1551 * igb_stop_adapter - Stop the adapter
1552 1552 */
1553 1553 static void
1554 1554 igb_stop_adapter(igb_t *igb)
1555 1555 {
1556 1556 struct e1000_hw *hw = &igb->hw;
1557 1557
1558 1558 ASSERT(mutex_owned(&igb->gen_lock));
1559 1559
1560 1560 /* Stop the link setup timer */
1561 1561 igb_stop_link_timer(igb);
1562 1562
1563 1563 /* Tell firmware driver is no longer in control */
1564 1564 igb_release_driver_control(hw);
1565 1565
1566 1566 /*
1567 1567 * Reset the chipset
1568 1568 */
1569 1569 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1570 1570 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1571 1571 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1572 1572 }
1573 1573
1574 1574 /*
1575 1575 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient
1576 1576 */
1577 1577 }
1578 1578
1579 1579 /*
1580 1580 * igb_reset - Reset the chipset and restart the driver.
1581 1581 *
1582 1582 * It involves stopping and re-starting the chipset,
1583 1583 * and re-configuring the rx/tx rings.
1584 1584 */
1585 1585 static int
1586 1586 igb_reset(igb_t *igb)
1587 1587 {
1588 1588 int i;
1589 1589
1590 1590 mutex_enter(&igb->gen_lock);
1591 1591
1592 1592 ASSERT(igb->igb_state & IGB_STARTED);
1593 1593 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
1594 1594
1595 1595 /*
1596 1596 * Disable the adapter interrupts to stop any rx/tx activities
1597 1597 * before draining pending data and resetting hardware.
1598 1598 */
1599 1599 igb_disable_adapter_interrupts(igb);
1600 1600
1601 1601 /*
1602 1602 * Drain the pending transmit packets
1603 1603 */
1604 1604 (void) igb_tx_drain(igb);
1605 1605
1606 1606 for (i = 0; i < igb->num_rx_rings; i++)
1607 1607 mutex_enter(&igb->rx_rings[i].rx_lock);
1608 1608 for (i = 0; i < igb->num_tx_rings; i++)
1609 1609 mutex_enter(&igb->tx_rings[i].tx_lock);
1610 1610
1611 1611 /*
1612 1612 * Stop the adapter
1613 1613 */
1614 1614 igb_stop_adapter(igb);
1615 1615
1616 1616 /*
1617 1617 * Clean the pending tx data/resources
1618 1618 */
1619 1619 igb_tx_clean(igb);
1620 1620
1621 1621 /*
1622 1622 * Start the adapter
1623 1623 */
1624 1624 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1625 1625 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1626 1626 goto reset_failure;
1627 1627 }
1628 1628
1629 1629 /*
1630 1630 * Setup the rx/tx rings
1631 1631 */
1632 1632 igb->tx_ring_init = B_FALSE;
1633 1633 igb_setup_rings(igb);
1634 1634
1635 1635 atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL));
1636 1636
1637 1637 /*
1638 1638 * Enable adapter interrupts
1639 1639 * The interrupts must be enabled after the driver state is START
1640 1640 */
1641 1641 igb->capab->enable_intr(igb);
1642 1642
1643 1643 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
1644 1644 goto reset_failure;
1645 1645
1646 1646 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1647 1647 goto reset_failure;
1648 1648
1649 1649 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1650 1650 mutex_exit(&igb->tx_rings[i].tx_lock);
1651 1651 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1652 1652 mutex_exit(&igb->rx_rings[i].rx_lock);
1653 1653
1654 1654 atomic_or_32(&igb->igb_state, IGB_STARTED);
1655 1655
1656 1656 mutex_exit(&igb->gen_lock);
1657 1657
1658 1658 return (IGB_SUCCESS);
1659 1659
1660 1660 reset_failure:
1661 1661 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1662 1662 mutex_exit(&igb->tx_rings[i].tx_lock);
1663 1663 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1664 1664 mutex_exit(&igb->rx_rings[i].rx_lock);
1665 1665
1666 1666 mutex_exit(&igb->gen_lock);
1667 1667
1668 1668 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1669 1669
1670 1670 return (IGB_FAILURE);
1671 1671 }
1672 1672
1673 1673 /*
1674 1674 * igb_tx_clean - Clean the pending transmit packets and DMA resources
1675 1675 */
1676 1676 static void
1677 1677 igb_tx_clean(igb_t *igb)
1678 1678 {
1679 1679 igb_tx_ring_t *tx_ring;
1680 1680 tx_control_block_t *tcb;
1681 1681 link_list_t pending_list;
1682 1682 uint32_t desc_num;
1683 1683 int i, j;
1684 1684
1685 1685 LINK_LIST_INIT(&pending_list);
1686 1686
1687 1687 for (i = 0; i < igb->num_tx_rings; i++) {
1688 1688 tx_ring = &igb->tx_rings[i];
1689 1689
1690 1690 mutex_enter(&tx_ring->recycle_lock);
1691 1691
1692 1692 /*
1693 1693 * Clean the pending tx data - the pending packets in the
1694 1694 * work_list that have no chances to be transmitted again.
1695 1695 *
1696 1696 * We must ensure the chipset is stopped or the link is down
1697 1697 * before cleaning the transmit packets.
1698 1698 */
1699 1699 desc_num = 0;
1700 1700 for (j = 0; j < tx_ring->ring_size; j++) {
1701 1701 tcb = tx_ring->work_list[j];
1702 1702 if (tcb != NULL) {
1703 1703 desc_num += tcb->desc_num;
1704 1704
1705 1705 tx_ring->work_list[j] = NULL;
1706 1706
1707 1707 igb_free_tcb(tcb);
1708 1708
1709 1709 LIST_PUSH_TAIL(&pending_list, &tcb->link);
1710 1710 }
1711 1711 }
1712 1712
1713 1713 if (desc_num > 0) {
1714 1714 atomic_add_32(&tx_ring->tbd_free, desc_num);
1715 1715 ASSERT(tx_ring->tbd_free == tx_ring->ring_size);
1716 1716
1717 1717 /*
1718 1718 * Reset the head and tail pointers of the tbd ring;
1719 1719 * Reset the head write-back if it is enabled.
1720 1720 */
1721 1721 tx_ring->tbd_head = 0;
1722 1722 tx_ring->tbd_tail = 0;
1723 1723 if (igb->tx_head_wb_enable)
1724 1724 *tx_ring->tbd_head_wb = 0;
1725 1725
1726 1726 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0);
1727 1727 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0);
1728 1728 }
1729 1729
1730 1730 mutex_exit(&tx_ring->recycle_lock);
1731 1731
1732 1732 /*
1733 1733 * Add the tx control blocks in the pending list to
1734 1734 * the free list.
1735 1735 */
1736 1736 igb_put_free_list(tx_ring, &pending_list);
1737 1737 }
1738 1738 }
1739 1739
1740 1740 /*
1741 1741 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted
1742 1742 */
1743 1743 static boolean_t
1744 1744 igb_tx_drain(igb_t *igb)
1745 1745 {
1746 1746 igb_tx_ring_t *tx_ring;
1747 1747 boolean_t done;
1748 1748 int i, j;
1749 1749
1750 1750 /*
1751 1751 * Wait for a specific time to allow pending tx packets
1752 1752 * to be transmitted.
1753 1753 *
1754 1754 * Check the counter tbd_free to see if transmission is done.
1755 1755 * No lock protection is needed here.
1756 1756 *
1757 1757 * Return B_TRUE if all pending packets have been transmitted;
1758 1758 * Otherwise return B_FALSE;
1759 1759 */
1760 1760 for (i = 0; i < TX_DRAIN_TIME; i++) {
1761 1761
1762 1762 done = B_TRUE;
1763 1763 for (j = 0; j < igb->num_tx_rings; j++) {
1764 1764 tx_ring = &igb->tx_rings[j];
1765 1765 done = done &&
1766 1766 (tx_ring->tbd_free == tx_ring->ring_size);
1767 1767 }
1768 1768
1769 1769 if (done)
1770 1770 break;
1771 1771
1772 1772 msec_delay(1);
1773 1773 }
1774 1774
1775 1775 return (done);
1776 1776 }
1777 1777
1778 1778 /*
1779 1779 * igb_rx_drain - Wait for all rx buffers to be released by upper layer
1780 1780 */
1781 1781 static boolean_t
1782 1782 igb_rx_drain(igb_t *igb)
1783 1783 {
1784 1784 boolean_t done;
1785 1785 int i;
1786 1786
1787 1787 /*
1788 1788 * Polling the rx free list to check if those rx buffers held by
1789 1789 * the upper layer are released.
1790 1790 *
1791 1791 * Check the counter rcb_free to see if all pending buffers are
1792 1792 * released. No lock protection is needed here.
1793 1793 *
1794 1794 * Return B_TRUE if all pending buffers have been released;
1795 1795 * Otherwise return B_FALSE;
1796 1796 */
1797 1797 for (i = 0; i < RX_DRAIN_TIME; i++) {
1798 1798 done = (igb->rcb_pending == 0);
1799 1799
1800 1800 if (done)
1801 1801 break;
1802 1802
1803 1803 msec_delay(1);
1804 1804 }
1805 1805
1806 1806 return (done);
1807 1807 }
1808 1808
1809 1809 /*
1810 1810 * igb_start - Start the driver/chipset
1811 1811 */
1812 1812 int
1813 1813 igb_start(igb_t *igb, boolean_t alloc_buffer)
1814 1814 {
1815 1815 int i;
1816 1816
1817 1817 ASSERT(mutex_owned(&igb->gen_lock));
1818 1818
1819 1819 if (alloc_buffer) {
1820 1820 if (igb_alloc_rx_data(igb) != IGB_SUCCESS) {
1821 1821 igb_log(igb, IGB_LOG_ERROR,
1822 1822 "Failed to allocate software receive rings");
1823 1823 return (IGB_FAILURE);
1824 1824 }
1825 1825
1826 1826 /* Allocate buffers for all the rx/tx rings */
1827 1827 if (igb_alloc_dma(igb) != IGB_SUCCESS) {
1828 1828 igb_log(igb, IGB_LOG_ERROR,
1829 1829 "Failed to allocate DMA resource");
1830 1830 return (IGB_FAILURE);
1831 1831 }
1832 1832
1833 1833 igb->tx_ring_init = B_TRUE;
1834 1834 } else {
1835 1835 igb->tx_ring_init = B_FALSE;
1836 1836 }
1837 1837
1838 1838 for (i = 0; i < igb->num_rx_rings; i++)
1839 1839 mutex_enter(&igb->rx_rings[i].rx_lock);
1840 1840 for (i = 0; i < igb->num_tx_rings; i++)
1841 1841 mutex_enter(&igb->tx_rings[i].tx_lock);
1842 1842
1843 1843 /*
1844 1844 * Start the adapter
1845 1845 */
1846 1846 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) {
1847 1847 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1848 1848 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1849 1849 goto start_failure;
1850 1850 }
1851 1851 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
1852 1852 }
1853 1853
1854 1854 /*
1855 1855 * Setup the rx/tx rings
1856 1856 */
1857 1857 igb_setup_rings(igb);
1858 1858
1859 1859 /*
1860 1860 * Enable adapter interrupts
1861 1861 * The interrupts must be enabled after the driver state is START
1862 1862 */
1863 1863 igb->capab->enable_intr(igb);
1864 1864
1865 1865 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
1866 1866 goto start_failure;
1867 1867
1868 1868 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1869 1869 goto start_failure;
1870 1870
1871 1871 if (igb->hw.mac.type == e1000_i350)
1872 1872 (void) e1000_set_eee_i350(&igb->hw, B_FALSE, B_FALSE);
1873 1873 else if (igb->hw.mac.type == e1000_i354)
1874 1874 (void) e1000_set_eee_i354(&igb->hw, B_FALSE, B_FALSE);
1875 1875
1876 1876 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1877 1877 mutex_exit(&igb->tx_rings[i].tx_lock);
1878 1878 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1879 1879 mutex_exit(&igb->rx_rings[i].rx_lock);
1880 1880
1881 1881 return (IGB_SUCCESS);
1882 1882
1883 1883 start_failure:
1884 1884 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1885 1885 mutex_exit(&igb->tx_rings[i].tx_lock);
1886 1886 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1887 1887 mutex_exit(&igb->rx_rings[i].rx_lock);
1888 1888
1889 1889 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1890 1890
1891 1891 return (IGB_FAILURE);
1892 1892 }
1893 1893
1894 1894 /*
1895 1895 * igb_stop - Stop the driver/chipset
1896 1896 */
1897 1897 void
1898 1898 igb_stop(igb_t *igb, boolean_t free_buffer)
1899 1899 {
1900 1900 int i;
1901 1901
1902 1902 ASSERT(mutex_owned(&igb->gen_lock));
1903 1903
1904 1904 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER;
1905 1905
1906 1906 /*
1907 1907 * Disable the adapter interrupts
1908 1908 */
1909 1909 igb_disable_adapter_interrupts(igb);
1910 1910
1911 1911 /*
1912 1912 * Drain the pending tx packets
1913 1913 */
1914 1914 (void) igb_tx_drain(igb);
1915 1915
1916 1916 for (i = 0; i < igb->num_rx_rings; i++)
1917 1917 mutex_enter(&igb->rx_rings[i].rx_lock);
1918 1918 for (i = 0; i < igb->num_tx_rings; i++)
1919 1919 mutex_enter(&igb->tx_rings[i].tx_lock);
1920 1920
1921 1921 /*
1922 1922 * Stop the adapter
1923 1923 */
1924 1924 igb_stop_adapter(igb);
1925 1925
1926 1926 /*
1927 1927 * Clean the pending tx data/resources
1928 1928 */
1929 1929 igb_tx_clean(igb);
1930 1930
1931 1931 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1932 1932 mutex_exit(&igb->tx_rings[i].tx_lock);
1933 1933 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1934 1934 mutex_exit(&igb->rx_rings[i].rx_lock);
1935 1935
1936 1936 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1937 1937 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1938 1938
1939 1939 if (igb->link_state == LINK_STATE_UP) {
1940 1940 igb->link_state = LINK_STATE_UNKNOWN;
1941 1941 mac_link_update(igb->mac_hdl, igb->link_state);
1942 1942 }
1943 1943
1944 1944 if (free_buffer) {
1945 1945 /*
1946 1946 * Release the DMA/memory resources of rx/tx rings
1947 1947 */
1948 1948 igb_free_dma(igb);
1949 1949 igb_free_rx_data(igb);
1950 1950 }
1951 1951 }
1952 1952
1953 1953 /*
1954 1954 * igb_alloc_rings - Allocate memory space for rx/tx rings
1955 1955 */
1956 1956 static int
1957 1957 igb_alloc_rings(igb_t *igb)
1958 1958 {
1959 1959 /*
1960 1960 * Allocate memory space for rx rings
1961 1961 */
1962 1962 igb->rx_rings = kmem_zalloc(
1963 1963 sizeof (igb_rx_ring_t) * igb->num_rx_rings,
1964 1964 KM_NOSLEEP);
1965 1965
1966 1966 if (igb->rx_rings == NULL) {
1967 1967 return (IGB_FAILURE);
1968 1968 }
1969 1969
1970 1970 /*
1971 1971 * Allocate memory space for tx rings
1972 1972 */
1973 1973 igb->tx_rings = kmem_zalloc(
1974 1974 sizeof (igb_tx_ring_t) * igb->num_tx_rings,
1975 1975 KM_NOSLEEP);
1976 1976
1977 1977 if (igb->tx_rings == NULL) {
1978 1978 kmem_free(igb->rx_rings,
1979 1979 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1980 1980 igb->rx_rings = NULL;
1981 1981 return (IGB_FAILURE);
1982 1982 }
1983 1983
1984 1984 /*
1985 1985 * Allocate memory space for rx ring groups
1986 1986 */
1987 1987 igb->rx_groups = kmem_zalloc(
1988 1988 sizeof (igb_rx_group_t) * igb->num_rx_groups,
1989 1989 KM_NOSLEEP);
1990 1990
1991 1991 if (igb->rx_groups == NULL) {
1992 1992 kmem_free(igb->rx_rings,
1993 1993 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1994 1994 kmem_free(igb->tx_rings,
1995 1995 sizeof (igb_tx_ring_t) * igb->num_tx_rings);
1996 1996 igb->rx_rings = NULL;
1997 1997 igb->tx_rings = NULL;
1998 1998 return (IGB_FAILURE);
1999 1999 }
2000 2000
2001 2001 return (IGB_SUCCESS);
2002 2002 }
2003 2003
2004 2004 /*
2005 2005 * igb_free_rings - Free the memory space of rx/tx rings.
2006 2006 */
2007 2007 static void
2008 2008 igb_free_rings(igb_t *igb)
2009 2009 {
2010 2010 if (igb->rx_rings != NULL) {
2011 2011 kmem_free(igb->rx_rings,
2012 2012 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
2013 2013 igb->rx_rings = NULL;
2014 2014 }
2015 2015
2016 2016 if (igb->tx_rings != NULL) {
2017 2017 kmem_free(igb->tx_rings,
2018 2018 sizeof (igb_tx_ring_t) * igb->num_tx_rings);
2019 2019 igb->tx_rings = NULL;
2020 2020 }
2021 2021
2022 2022 if (igb->rx_groups != NULL) {
2023 2023 kmem_free(igb->rx_groups,
2024 2024 sizeof (igb_rx_group_t) * igb->num_rx_groups);
2025 2025 igb->rx_groups = NULL;
2026 2026 }
2027 2027 }
2028 2028
2029 2029 static int
2030 2030 igb_alloc_rx_data(igb_t *igb)
2031 2031 {
2032 2032 igb_rx_ring_t *rx_ring;
2033 2033 int i;
2034 2034
2035 2035 for (i = 0; i < igb->num_rx_rings; i++) {
2036 2036 rx_ring = &igb->rx_rings[i];
2037 2037 if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS)
2038 2038 goto alloc_rx_rings_failure;
2039 2039 }
2040 2040 return (IGB_SUCCESS);
2041 2041
2042 2042 alloc_rx_rings_failure:
2043 2043 igb_free_rx_data(igb);
2044 2044 return (IGB_FAILURE);
2045 2045 }
2046 2046
2047 2047 static void
2048 2048 igb_free_rx_data(igb_t *igb)
2049 2049 {
2050 2050 igb_rx_ring_t *rx_ring;
2051 2051 igb_rx_data_t *rx_data;
2052 2052 int i;
2053 2053
2054 2054 for (i = 0; i < igb->num_rx_rings; i++) {
2055 2055 rx_ring = &igb->rx_rings[i];
2056 2056
2057 2057 mutex_enter(&igb->rx_pending_lock);
2058 2058 rx_data = rx_ring->rx_data;
2059 2059
2060 2060 if (rx_data != NULL) {
2061 2061 rx_data->flag |= IGB_RX_STOPPED;
2062 2062
2063 2063 if (rx_data->rcb_pending == 0) {
2064 2064 igb_free_rx_ring_data(rx_data);
2065 2065 rx_ring->rx_data = NULL;
2066 2066 }
2067 2067 }
2068 2068
2069 2069 mutex_exit(&igb->rx_pending_lock);
2070 2070 }
2071 2071 }
2072 2072
2073 2073 /*
2074 2074 * igb_setup_rings - Setup rx/tx rings
2075 2075 */
2076 2076 static void
2077 2077 igb_setup_rings(igb_t *igb)
2078 2078 {
2079 2079 /*
2080 2080 * Setup the rx/tx rings, including the following:
2081 2081 *
2082 2082 * 1. Setup the descriptor ring and the control block buffers;
2083 2083 * 2. Initialize necessary registers for receive/transmit;
2084 2084 * 3. Initialize software pointers/parameters for receive/transmit;
2085 2085 */
2086 2086 igb_setup_rx(igb);
2087 2087
2088 2088 igb_setup_tx(igb);
2089 2089 }
2090 2090
2091 2091 static void
2092 2092 igb_setup_rx_ring(igb_rx_ring_t *rx_ring)
2093 2093 {
2094 2094 igb_t *igb = rx_ring->igb;
2095 2095 igb_rx_data_t *rx_data = rx_ring->rx_data;
2096 2096 struct e1000_hw *hw = &igb->hw;
2097 2097 rx_control_block_t *rcb;
2098 2098 union e1000_adv_rx_desc *rbd;
2099 2099 uint32_t size;
2100 2100 uint32_t buf_low;
2101 2101 uint32_t buf_high;
2102 2102 uint32_t rxdctl;
2103 2103 int i;
2104 2104
2105 2105 ASSERT(mutex_owned(&rx_ring->rx_lock));
2106 2106 ASSERT(mutex_owned(&igb->gen_lock));
2107 2107
2108 2108 /*
2109 2109 * Initialize descriptor ring with buffer addresses
2110 2110 */
2111 2111 for (i = 0; i < igb->rx_ring_size; i++) {
2112 2112 rcb = rx_data->work_list[i];
2113 2113 rbd = &rx_data->rbd_ring[i];
2114 2114
2115 2115 rbd->read.pkt_addr = rcb->rx_buf.dma_address;
2116 2116 rbd->read.hdr_addr = NULL;
2117 2117 }
2118 2118
2119 2119 /*
2120 2120 * Initialize the base address registers
2121 2121 */
2122 2122 buf_low = (uint32_t)rx_data->rbd_area.dma_address;
2123 2123 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32);
2124 2124 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high);
2125 2125 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low);
2126 2126
2127 2127 /*
2128 2128 * Initialize the length register
2129 2129 */
2130 2130 size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc);
2131 2131 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size);
2132 2132
2133 2133 /*
2134 2134 * Initialize buffer size & descriptor type
2135 2135 */
2136 2136 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index),
2137 2137 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) |
2138 2138 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF));
2139 2139
2140 2140 /*
2141 2141 * Setup the Receive Descriptor Control Register (RXDCTL)
2142 2142 */
2143 2143 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index));
2144 2144 rxdctl &= igb->capab->rxdctl_mask;
2145 2145 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2146 2146 rxdctl |= 16; /* pthresh */
2147 2147 rxdctl |= 8 << 8; /* hthresh */
2148 2148 rxdctl |= 1 << 16; /* wthresh */
2149 2149 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl);
2150 2150
2151 2151 rx_data->rbd_next = 0;
2152 2152 }
2153 2153
2154 2154 static void
2155 2155 igb_setup_rx(igb_t *igb)
2156 2156 {
2157 2157 igb_rx_ring_t *rx_ring;
2158 2158 igb_rx_data_t *rx_data;
2159 2159 igb_rx_group_t *rx_group;
2160 2160 struct e1000_hw *hw = &igb->hw;
2161 2161 uint32_t rctl, rxcsum;
2162 2162 uint32_t ring_per_group;
2163 2163 int i;
2164 2164
2165 2165 /*
2166 2166 * Setup the Receive Control Register (RCTL), and enable the
2167 2167 * receiver. The initial configuration is to: enable the receiver,
2168 2168 * accept broadcasts, discard bad packets, accept long packets,
2169 2169 * disable VLAN filter checking, and set receive buffer size to
2170 2170 * 2k. For 82575, also set the receive descriptor minimum
2171 2171 * threshold size to 1/2 the ring.
2172 2172 */
2173 2173 rctl = E1000_READ_REG(hw, E1000_RCTL);
2174 2174
2175 2175 /*
2176 2176 * Clear the field used for wakeup control. This driver doesn't do
2177 2177 * wakeup but leave this here for completeness.
2178 2178 */
2179 2179 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2180 2180 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2181 2181
2182 2182 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */
2183 2183 E1000_RCTL_BAM | /* Accept Broadcast Packets */
2184 2184 E1000_RCTL_LPE | /* Large Packet Enable */
2185 2185 /* Multicast filter offset */
2186 2186 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) |
2187 2187 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */
2188 2188 E1000_RCTL_SECRC); /* Strip Ethernet CRC */
2189 2189
2190 2190 for (i = 0; i < igb->num_rx_groups; i++) {
2191 2191 rx_group = &igb->rx_groups[i];
2192 2192 rx_group->index = i;
2193 2193 rx_group->igb = igb;
2194 2194 }
2195 2195
2196 2196 /*
2197 2197 * Set up all rx descriptor rings - must be called before receive unit
2198 2198 * enabled.
2199 2199 */
2200 2200 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2201 2201 for (i = 0; i < igb->num_rx_rings; i++) {
2202 2202 rx_ring = &igb->rx_rings[i];
2203 2203 igb_setup_rx_ring(rx_ring);
2204 2204
2205 2205 /*
2206 2206 * Map a ring to a group by assigning a group index
2207 2207 */
2208 2208 rx_ring->group_index = i / ring_per_group;
2209 2209 }
2210 2210
2211 2211 /*
2212 2212 * Setup the Rx Long Packet Max Length register
2213 2213 */
2214 2214 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size);
2215 2215
2216 2216 /*
2217 2217 * Hardware checksum settings
2218 2218 */
2219 2219 if (igb->rx_hcksum_enable) {
2220 2220 rxcsum =
2221 2221 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */
2222 2222 E1000_RXCSUM_IPOFL; /* IP checksum */
2223 2223
2224 2224 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2225 2225 }
2226 2226
2227 2227 /*
2228 2228 * Setup classify and RSS for multiple receive queues
2229 2229 */
2230 2230 switch (igb->vmdq_mode) {
2231 2231 case E1000_VMDQ_OFF:
2232 2232 /*
2233 2233 * One ring group, only RSS is needed when more than
2234 2234 * one ring enabled.
2235 2235 */
2236 2236 if (igb->num_rx_rings > 1)
2237 2237 igb_setup_rss(igb);
2238 2238 break;
2239 2239 case E1000_VMDQ_MAC:
2240 2240 /*
2241 2241 * Multiple groups, each group has one ring,
2242 2242 * only the MAC classification is needed.
2243 2243 */
2244 2244 igb_setup_mac_classify(igb);
2245 2245 break;
2246 2246 case E1000_VMDQ_MAC_RSS:
2247 2247 /*
2248 2248 * Multiple groups and multiple rings, both
2249 2249 * MAC classification and RSS are needed.
2250 2250 */
2251 2251 igb_setup_mac_rss_classify(igb);
2252 2252 break;
2253 2253 }
2254 2254
2255 2255 /*
2256 2256 * Enable the receive unit - must be done after all
2257 2257 * the rx setup above.
2258 2258 */
2259 2259 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2260 2260
2261 2261 /*
2262 2262 * Initialize all adapter ring head & tail pointers - must
2263 2263 * be done after receive unit is enabled
2264 2264 */
2265 2265 for (i = 0; i < igb->num_rx_rings; i++) {
2266 2266 rx_ring = &igb->rx_rings[i];
2267 2267 rx_data = rx_ring->rx_data;
2268 2268 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2269 2269 E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1);
2270 2270 }
2271 2271
2272 2272 /*
2273 2273 * 82575 with manageability enabled needs a special flush to make
2274 2274 * sure the fifos start clean.
2275 2275 */
2276 2276 if ((hw->mac.type == e1000_82575) &&
2277 2277 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) {
2278 2278 e1000_rx_fifo_flush_82575(hw);
2279 2279 }
2280 2280 }
2281 2281
2282 2282 static void
2283 2283 igb_setup_tx_ring(igb_tx_ring_t *tx_ring)
2284 2284 {
2285 2285 igb_t *igb = tx_ring->igb;
2286 2286 struct e1000_hw *hw = &igb->hw;
2287 2287 uint32_t size;
2288 2288 uint32_t buf_low;
2289 2289 uint32_t buf_high;
2290 2290 uint32_t reg_val;
2291 2291
2292 2292 ASSERT(mutex_owned(&tx_ring->tx_lock));
2293 2293 ASSERT(mutex_owned(&igb->gen_lock));
2294 2294
2295 2295
2296 2296 /*
2297 2297 * Initialize the length register
2298 2298 */
2299 2299 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc);
2300 2300 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size);
2301 2301
2302 2302 /*
2303 2303 * Initialize the base address registers
2304 2304 */
2305 2305 buf_low = (uint32_t)tx_ring->tbd_area.dma_address;
2306 2306 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32);
2307 2307 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low);
2308 2308 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high);
2309 2309
2310 2310 /*
2311 2311 * Setup head & tail pointers
2312 2312 */
2313 2313 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0);
2314 2314 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0);
2315 2315
2316 2316 /*
2317 2317 * Setup head write-back
2318 2318 */
2319 2319 if (igb->tx_head_wb_enable) {
2320 2320 /*
2321 2321 * The memory of the head write-back is allocated using
2322 2322 * the extra tbd beyond the tail of the tbd ring.
2323 2323 */
2324 2324 tx_ring->tbd_head_wb = (uint32_t *)
2325 2325 ((uintptr_t)tx_ring->tbd_area.address + size);
2326 2326 *tx_ring->tbd_head_wb = 0;
2327 2327
2328 2328 buf_low = (uint32_t)
2329 2329 (tx_ring->tbd_area.dma_address + size);
2330 2330 buf_high = (uint32_t)
2331 2331 ((tx_ring->tbd_area.dma_address + size) >> 32);
2332 2332
2333 2333 /* Set the head write-back enable bit */
2334 2334 buf_low |= E1000_TX_HEAD_WB_ENABLE;
2335 2335
2336 2336 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low);
2337 2337 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high);
2338 2338
2339 2339 /*
2340 2340 * Turn off relaxed ordering for head write back or it will
2341 2341 * cause problems with the tx recycling
2342 2342 */
2343 2343 reg_val = E1000_READ_REG(hw,
2344 2344 E1000_DCA_TXCTRL(tx_ring->index));
2345 2345 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2346 2346 E1000_WRITE_REG(hw,
2347 2347 E1000_DCA_TXCTRL(tx_ring->index), reg_val);
2348 2348 } else {
2349 2349 tx_ring->tbd_head_wb = NULL;
2350 2350 }
2351 2351
2352 2352 tx_ring->tbd_head = 0;
2353 2353 tx_ring->tbd_tail = 0;
2354 2354 tx_ring->tbd_free = tx_ring->ring_size;
2355 2355
2356 2356 if (igb->tx_ring_init == B_TRUE) {
2357 2357 tx_ring->tcb_head = 0;
2358 2358 tx_ring->tcb_tail = 0;
2359 2359 tx_ring->tcb_free = tx_ring->free_list_size;
2360 2360 }
2361 2361
2362 2362 /*
2363 2363 * Enable TXDCTL per queue
2364 2364 */
2365 2365 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index));
2366 2366 reg_val |= E1000_TXDCTL_QUEUE_ENABLE;
2367 2367 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val);
2368 2368
2369 2369 /*
2370 2370 * Initialize hardware checksum offload settings
2371 2371 */
2372 2372 bzero(&tx_ring->tx_context, sizeof (tx_context_t));
2373 2373 }
2374 2374
2375 2375 static void
2376 2376 igb_setup_tx(igb_t *igb)
2377 2377 {
2378 2378 igb_tx_ring_t *tx_ring;
2379 2379 struct e1000_hw *hw = &igb->hw;
2380 2380 uint32_t reg_val;
2381 2381 int i;
2382 2382
2383 2383 for (i = 0; i < igb->num_tx_rings; i++) {
2384 2384 tx_ring = &igb->tx_rings[i];
2385 2385 igb_setup_tx_ring(tx_ring);
2386 2386 }
2387 2387
2388 2388 /*
2389 2389 * Setup the Transmit Control Register (TCTL)
2390 2390 */
2391 2391 reg_val = E1000_READ_REG(hw, E1000_TCTL);
2392 2392 reg_val &= ~E1000_TCTL_CT;
2393 2393 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2394 2394 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2395 2395
2396 2396 /* Enable transmits */
2397 2397 reg_val |= E1000_TCTL_EN;
2398 2398
2399 2399 E1000_WRITE_REG(hw, E1000_TCTL, reg_val);
2400 2400 }
2401 2401
2402 2402 /*
2403 2403 * igb_setup_rss - Setup receive-side scaling feature
2404 2404 */
2405 2405 static void
2406 2406 igb_setup_rss(igb_t *igb)
2407 2407 {
2408 2408 struct e1000_hw *hw = &igb->hw;
2409 2409 uint32_t i, mrqc, rxcsum;
2410 2410 int shift = 0;
2411 2411 uint32_t random;
2412 2412 union e1000_reta {
2413 2413 uint32_t dword;
2414 2414 uint8_t bytes[4];
2415 2415 } reta;
2416 2416
2417 2417 /* Setup the Redirection Table */
2418 2418 if (hw->mac.type == e1000_82576) {
2419 2419 shift = 3;
2420 2420 } else if (hw->mac.type == e1000_82575) {
2421 2421 shift = 6;
2422 2422 }
2423 2423 for (i = 0; i < (32 * 4); i++) {
2424 2424 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift;
2425 2425 if ((i & 3) == 3) {
2426 2426 E1000_WRITE_REG(hw,
2427 2427 (E1000_RETA(0) + (i & ~3)), reta.dword);
2428 2428 }
2429 2429 }
2430 2430
2431 2431 /* Fill out hash function seeds */
2432 2432 for (i = 0; i < 10; i++) {
2433 2433 (void) random_get_pseudo_bytes((uint8_t *)&random,
2434 2434 sizeof (uint32_t));
2435 2435 E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
2436 2436 }
2437 2437
2438 2438 /* Setup the Multiple Receive Queue Control register */
2439 2439 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2440 2440 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2441 2441 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2442 2442 E1000_MRQC_RSS_FIELD_IPV6 |
2443 2443 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2444 2444 E1000_MRQC_RSS_FIELD_IPV4_UDP |
2445 2445 E1000_MRQC_RSS_FIELD_IPV6_UDP |
2446 2446 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2447 2447 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2448 2448
2449 2449 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2450 2450
2451 2451 /*
2452 2452 * Disable Packet Checksum to enable RSS for multiple receive queues.
2453 2453 *
2454 2454 * The Packet Checksum is not ethernet CRC. It is another kind of
2455 2455 * checksum offloading provided by the 82575 chipset besides the IP
2456 2456 * header checksum offloading and the TCP/UDP checksum offloading.
2457 2457 * The Packet Checksum is by default computed over the entire packet
2458 2458 * from the first byte of the DA through the last byte of the CRC,
2459 2459 * including the Ethernet and IP headers.
2460 2460 *
2461 2461 * It is a hardware limitation that Packet Checksum is mutually
2462 2462 * exclusive with RSS.
2463 2463 */
2464 2464 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2465 2465 rxcsum |= E1000_RXCSUM_PCSD;
2466 2466 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2467 2467 }
2468 2468
2469 2469 /*
2470 2470 * igb_setup_mac_rss_classify - Setup MAC classification and rss
2471 2471 */
2472 2472 static void
2473 2473 igb_setup_mac_rss_classify(igb_t *igb)
2474 2474 {
2475 2475 struct e1000_hw *hw = &igb->hw;
2476 2476 uint32_t i, mrqc, vmdctl, rxcsum;
2477 2477 uint32_t ring_per_group;
2478 2478 int shift_group0, shift_group1;
2479 2479 uint32_t random;
2480 2480 union e1000_reta {
2481 2481 uint32_t dword;
2482 2482 uint8_t bytes[4];
2483 2483 } reta;
2484 2484
2485 2485 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2486 2486
2487 2487 /* Setup the Redirection Table, it is shared between two groups */
2488 2488 shift_group0 = 2;
2489 2489 shift_group1 = 6;
2490 2490 for (i = 0; i < (32 * 4); i++) {
2491 2491 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) |
2492 2492 ((ring_per_group + (i % ring_per_group)) << shift_group1);
2493 2493 if ((i & 3) == 3) {
2494 2494 E1000_WRITE_REG(hw,
2495 2495 (E1000_RETA(0) + (i & ~3)), reta.dword);
2496 2496 }
2497 2497 }
2498 2498
2499 2499 /* Fill out hash function seeds */
2500 2500 for (i = 0; i < 10; i++) {
2501 2501 (void) random_get_pseudo_bytes((uint8_t *)&random,
2502 2502 sizeof (uint32_t));
2503 2503 E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
2504 2504 }
2505 2505
2506 2506 /*
2507 2507 * Setup the Multiple Receive Queue Control register,
2508 2508 * enable VMDq based on packet destination MAC address and RSS.
2509 2509 */
2510 2510 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP;
2511 2511 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2512 2512 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2513 2513 E1000_MRQC_RSS_FIELD_IPV6 |
2514 2514 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2515 2515 E1000_MRQC_RSS_FIELD_IPV4_UDP |
2516 2516 E1000_MRQC_RSS_FIELD_IPV6_UDP |
2517 2517 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2518 2518 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2519 2519
2520 2520 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2521 2521
2522 2522
2523 2523 /* Define the default group and default queues */
2524 2524 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE;
2525 2525 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl);
2526 2526
2527 2527 /*
2528 2528 * Disable Packet Checksum to enable RSS for multiple receive queues.
2529 2529 *
2530 2530 * The Packet Checksum is not ethernet CRC. It is another kind of
2531 2531 * checksum offloading provided by the 82575 chipset besides the IP
2532 2532 * header checksum offloading and the TCP/UDP checksum offloading.
2533 2533 * The Packet Checksum is by default computed over the entire packet
2534 2534 * from the first byte of the DA through the last byte of the CRC,
2535 2535 * including the Ethernet and IP headers.
2536 2536 *
2537 2537 * It is a hardware limitation that Packet Checksum is mutually
2538 2538 * exclusive with RSS.
2539 2539 */
2540 2540 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2541 2541 rxcsum |= E1000_RXCSUM_PCSD;
2542 2542 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2543 2543 }
2544 2544
2545 2545 /*
2546 2546 * igb_setup_mac_classify - Setup MAC classification feature
2547 2547 */
2548 2548 static void
2549 2549 igb_setup_mac_classify(igb_t *igb)
2550 2550 {
2551 2551 struct e1000_hw *hw = &igb->hw;
2552 2552 uint32_t mrqc, rxcsum;
2553 2553
2554 2554 /*
2555 2555 * Setup the Multiple Receive Queue Control register,
2556 2556 * enable VMDq based on packet destination MAC address.
2557 2557 */
2558 2558 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP;
2559 2559 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2560 2560
2561 2561 /*
2562 2562 * Disable Packet Checksum to enable RSS for multiple receive queues.
2563 2563 *
2564 2564 * The Packet Checksum is not ethernet CRC. It is another kind of
2565 2565 * checksum offloading provided by the 82575 chipset besides the IP
2566 2566 * header checksum offloading and the TCP/UDP checksum offloading.
2567 2567 * The Packet Checksum is by default computed over the entire packet
2568 2568 * from the first byte of the DA through the last byte of the CRC,
2569 2569 * including the Ethernet and IP headers.
2570 2570 *
2571 2571 * It is a hardware limitation that Packet Checksum is mutually
2572 2572 * exclusive with RSS.
2573 2573 */
2574 2574 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2575 2575 rxcsum |= E1000_RXCSUM_PCSD;
2576 2576 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2577 2577
2578 2578 }
2579 2579
2580 2580 /*
2581 2581 * igb_init_unicst - Initialize the unicast addresses
2582 2582 */
2583 2583 static void
2584 2584 igb_init_unicst(igb_t *igb)
2585 2585 {
2586 2586 struct e1000_hw *hw = &igb->hw;
2587 2587 int slot;
2588 2588
2589 2589 /*
2590 2590 * Here we should consider two situations:
2591 2591 *
2592 2592 * 1. Chipset is initialized the first time
2593 2593 * Initialize the multiple unicast addresses, and
2594 2594 * save the default MAC address.
2595 2595 *
2596 2596 * 2. Chipset is reset
2597 2597 * Recover the multiple unicast addresses from the
2598 2598 * software data structure to the RAR registers.
2599 2599 */
2600 2600
2601 2601 /*
2602 2602 * Clear the default MAC address in the RAR0 rgister,
2603 2603 * which is loaded from EEPROM when system boot or chipreset,
2604 2604 * this will cause the conficts with add_mac/rem_mac entry
2605 2605 * points when VMDq is enabled. For this reason, the RAR0
2606 2606 * must be cleared for both cases mentioned above.
2607 2607 */
2608 2608 e1000_rar_clear(hw, 0);
2609 2609
2610 2610 if (!igb->unicst_init) {
2611 2611
2612 2612 /* Initialize the multiple unicast addresses */
2613 2613 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES;
2614 2614 igb->unicst_avail = igb->unicst_total;
2615 2615
2616 2616 for (slot = 0; slot < igb->unicst_total; slot++)
2617 2617 igb->unicst_addr[slot].mac.set = 0;
2618 2618
2619 2619 igb->unicst_init = B_TRUE;
2620 2620 } else {
2621 2621 /* Re-configure the RAR registers */
2622 2622 for (slot = 0; slot < igb->unicst_total; slot++) {
2623 2623 (void) e1000_rar_set_vmdq(hw,
2624 2624 igb->unicst_addr[slot].mac.addr,
2625 2625 slot, igb->vmdq_mode,
2626 2626 igb->unicst_addr[slot].mac.group_index);
2627 2627 }
2628 2628 }
2629 2629 }
2630 2630
2631 2631 /*
2632 2632 * igb_unicst_find - Find the slot for the specified unicast address
2633 2633 */
2634 2634 int
2635 2635 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr)
2636 2636 {
2637 2637 int slot;
2638 2638
2639 2639 ASSERT(mutex_owned(&igb->gen_lock));
2640 2640
2641 2641 for (slot = 0; slot < igb->unicst_total; slot++) {
2642 2642 if (bcmp(igb->unicst_addr[slot].mac.addr,
2643 2643 mac_addr, ETHERADDRL) == 0)
2644 2644 return (slot);
2645 2645 }
2646 2646
2647 2647 return (-1);
2648 2648 }
2649 2649
2650 2650 /*
2651 2651 * igb_unicst_set - Set the unicast address to the specified slot
2652 2652 */
2653 2653 int
2654 2654 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr,
2655 2655 int slot)
2656 2656 {
2657 2657 struct e1000_hw *hw = &igb->hw;
2658 2658
2659 2659 ASSERT(mutex_owned(&igb->gen_lock));
2660 2660
2661 2661 /*
2662 2662 * Save the unicast address in the software data structure
2663 2663 */
2664 2664 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL);
2665 2665
2666 2666 /*
2667 2667 * Set the unicast address to the RAR register
2668 2668 */
2669 2669 (void) e1000_rar_set(hw, (uint8_t *)mac_addr, slot);
2670 2670
2671 2671 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2672 2672 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2673 2673 return (EIO);
2674 2674 }
2675 2675
2676 2676 return (0);
2677 2677 }
2678 2678
2679 2679 /*
2680 2680 * igb_multicst_add - Add a multicst address
2681 2681 */
2682 2682 int
2683 2683 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr)
2684 2684 {
2685 2685 struct ether_addr *new_table;
2686 2686 size_t new_len;
2687 2687 size_t old_len;
2688 2688
2689 2689 ASSERT(mutex_owned(&igb->gen_lock));
2690 2690
2691 2691 if ((multiaddr[0] & 01) == 0) {
2692 2692 igb_log(igb, IGB_LOG_ERROR, "Illegal multicast address");
2693 2693 return (EINVAL);
2694 2694 }
2695 2695
2696 2696 if (igb->mcast_count >= igb->mcast_max_num) {
2697 2697 igb_log(igb, IGB_LOG_ERROR,
2698 2698 "Adapter requested more than %d mcast addresses",
2699 2699 igb->mcast_max_num);
2700 2700 return (ENOENT);
2701 2701 }
2702 2702
2703 2703 if (igb->mcast_count == igb->mcast_alloc_count) {
2704 2704 old_len = igb->mcast_alloc_count *
2705 2705 sizeof (struct ether_addr);
2706 2706 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) *
2707 2707 sizeof (struct ether_addr);
2708 2708
2709 2709 new_table = kmem_alloc(new_len, KM_NOSLEEP);
2710 2710 if (new_table == NULL) {
2711 2711 igb_log(igb, IGB_LOG_ERROR,
2712 2712 "Not enough memory to alloc mcast table");
2713 2713 return (ENOMEM);
2714 2714 }
2715 2715
2716 2716 if (igb->mcast_table != NULL) {
2717 2717 bcopy(igb->mcast_table, new_table, old_len);
2718 2718 kmem_free(igb->mcast_table, old_len);
2719 2719 }
2720 2720 igb->mcast_alloc_count += MCAST_ALLOC_COUNT;
2721 2721 igb->mcast_table = new_table;
2722 2722 }
2723 2723
2724 2724 bcopy(multiaddr,
2725 2725 &igb->mcast_table[igb->mcast_count], ETHERADDRL);
2726 2726 igb->mcast_count++;
2727 2727
2728 2728 /*
2729 2729 * Update the multicast table in the hardware
2730 2730 */
2731 2731 igb_setup_multicst(igb);
2732 2732
2733 2733 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2734 2734 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2735 2735 return (EIO);
2736 2736 }
2737 2737
2738 2738 return (0);
2739 2739 }
2740 2740
2741 2741 /*
2742 2742 * igb_multicst_remove - Remove a multicst address
2743 2743 */
2744 2744 int
2745 2745 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr)
2746 2746 {
2747 2747 struct ether_addr *new_table;
2748 2748 size_t new_len;
2749 2749 size_t old_len;
2750 2750 int i;
2751 2751
2752 2752 ASSERT(mutex_owned(&igb->gen_lock));
2753 2753
2754 2754 for (i = 0; i < igb->mcast_count; i++) {
2755 2755 if (bcmp(multiaddr, &igb->mcast_table[i],
2756 2756 ETHERADDRL) == 0) {
2757 2757 for (i++; i < igb->mcast_count; i++) {
2758 2758 igb->mcast_table[i - 1] =
2759 2759 igb->mcast_table[i];
2760 2760 }
2761 2761 igb->mcast_count--;
2762 2762 break;
2763 2763 }
2764 2764 }
2765 2765
2766 2766 if ((igb->mcast_alloc_count - igb->mcast_count) >
2767 2767 MCAST_ALLOC_COUNT) {
2768 2768 old_len = igb->mcast_alloc_count *
2769 2769 sizeof (struct ether_addr);
2770 2770 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) *
2771 2771 sizeof (struct ether_addr);
2772 2772
2773 2773 new_table = kmem_alloc(new_len, KM_NOSLEEP);
2774 2774 if (new_table != NULL) {
2775 2775 bcopy(igb->mcast_table, new_table, new_len);
2776 2776 kmem_free(igb->mcast_table, old_len);
2777 2777 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT;
2778 2778 igb->mcast_table = new_table;
2779 2779 }
2780 2780 }
2781 2781
2782 2782 /*
2783 2783 * Update the multicast table in the hardware
2784 2784 */
2785 2785 igb_setup_multicst(igb);
2786 2786
2787 2787 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2788 2788 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2789 2789 return (EIO);
2790 2790 }
2791 2791
2792 2792 return (0);
2793 2793 }
2794 2794
2795 2795 static void
2796 2796 igb_release_multicast(igb_t *igb)
2797 2797 {
2798 2798 if (igb->mcast_table != NULL) {
2799 2799 kmem_free(igb->mcast_table,
2800 2800 igb->mcast_alloc_count * sizeof (struct ether_addr));
2801 2801 igb->mcast_table = NULL;
2802 2802 }
2803 2803 }
2804 2804
2805 2805 /*
2806 2806 * igb_setup_multicast - setup multicast data structures
2807 2807 *
2808 2808 * This routine initializes all of the multicast related structures
2809 2809 * and save them in the hardware registers.
2810 2810 */
2811 2811 static void
2812 2812 igb_setup_multicst(igb_t *igb)
2813 2813 {
2814 2814 uint8_t *mc_addr_list;
2815 2815 uint32_t mc_addr_count;
2816 2816 struct e1000_hw *hw = &igb->hw;
2817 2817
2818 2818 ASSERT(mutex_owned(&igb->gen_lock));
2819 2819 ASSERT(igb->mcast_count <= igb->mcast_max_num);
2820 2820
2821 2821 mc_addr_list = (uint8_t *)igb->mcast_table;
2822 2822 mc_addr_count = igb->mcast_count;
2823 2823
2824 2824 /*
2825 2825 * Update the multicase addresses to the MTA registers
2826 2826 */
2827 2827 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count);
2828 2828 }
2829 2829
2830 2830 /*
2831 2831 * igb_get_conf - Get driver configurations set in driver.conf
2832 2832 *
2833 2833 * This routine gets user-configured values out of the configuration
2834 2834 * file igb.conf.
2835 2835 *
2836 2836 * For each configurable value, there is a minimum, a maximum, and a
2837 2837 * default.
2838 2838 * If user does not configure a value, use the default.
2839 2839 * If user configures below the minimum, use the minumum.
2840 2840 * If user configures above the maximum, use the maxumum.
2841 2841 */
2842 2842 static void
2843 2843 igb_get_conf(igb_t *igb)
2844 2844 {
2845 2845 struct e1000_hw *hw = &igb->hw;
2846 2846 uint32_t default_mtu;
2847 2847 uint32_t flow_control;
2848 2848 uint32_t ring_per_group;
2849 2849 int i;
2850 2850
2851 2851 /*
2852 2852 * igb driver supports the following user configurations:
2853 2853 *
2854 2854 * Link configurations:
2855 2855 * adv_autoneg_cap
2856 2856 * adv_1000fdx_cap
2857 2857 * adv_100fdx_cap
2858 2858 * adv_100hdx_cap
2859 2859 * adv_10fdx_cap
2860 2860 * adv_10hdx_cap
2861 2861 * Note: 1000hdx is not supported.
2862 2862 *
2863 2863 * Jumbo frame configuration:
2864 2864 * default_mtu
2865 2865 *
2866 2866 * Ethernet flow control configuration:
2867 2867 * flow_control
2868 2868 *
2869 2869 * Multiple rings configurations:
2870 2870 * tx_queue_number
2871 2871 * tx_ring_size
2872 2872 * rx_queue_number
2873 2873 * rx_ring_size
2874 2874 *
2875 2875 * Call igb_get_prop() to get the value for a specific
2876 2876 * configuration parameter.
2877 2877 */
2878 2878
2879 2879 /*
2880 2880 * Link configurations
2881 2881 */
2882 2882 igb->param_adv_autoneg_cap = igb_get_prop(igb,
2883 2883 PROP_ADV_AUTONEG_CAP, 0, 1, 1);
2884 2884 igb->param_adv_1000fdx_cap = igb_get_prop(igb,
2885 2885 PROP_ADV_1000FDX_CAP, 0, 1, 1);
2886 2886 igb->param_adv_100fdx_cap = igb_get_prop(igb,
2887 2887 PROP_ADV_100FDX_CAP, 0, 1, 1);
2888 2888 igb->param_adv_100hdx_cap = igb_get_prop(igb,
2889 2889 PROP_ADV_100HDX_CAP, 0, 1, 1);
2890 2890 igb->param_adv_10fdx_cap = igb_get_prop(igb,
2891 2891 PROP_ADV_10FDX_CAP, 0, 1, 1);
2892 2892 igb->param_adv_10hdx_cap = igb_get_prop(igb,
2893 2893 PROP_ADV_10HDX_CAP, 0, 1, 1);
2894 2894
2895 2895 /*
2896 2896 * Jumbo frame configurations
2897 2897 */
2898 2898 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU,
2899 2899 MIN_MTU, MAX_MTU, DEFAULT_MTU);
2900 2900
2901 2901 igb->max_frame_size = default_mtu +
2902 2902 sizeof (struct ether_vlan_header) + ETHERFCSL;
2903 2903
2904 2904 /*
2905 2905 * Ethernet flow control configuration
2906 2906 */
2907 2907 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL,
2908 2908 e1000_fc_none, 4, e1000_fc_full);
2909 2909 if (flow_control == 4)
2910 2910 flow_control = e1000_fc_default;
2911 2911
2912 2912 hw->fc.requested_mode = flow_control;
2913 2913
2914 2914 /*
2915 2915 * Multiple rings configurations
2916 2916 */
2917 2917 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE,
2918 2918 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE);
2919 2919 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE,
2920 2920 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE);
2921 2921
2922 2922 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0);
2923 2923 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM,
2924 2924 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM);
2925 2925 /*
2926 2926 * Currently we do not support VMDq for 82576 and 82580.
2927 2927 * If it is e1000_82576, set num_rx_groups to 1.
2928 2928 */
2929 2929 if (hw->mac.type >= e1000_82576)
2930 2930 igb->num_rx_groups = 1;
2931 2931
2932 2932 if (igb->mr_enable) {
2933 2933 igb->num_tx_rings = igb->capab->def_tx_que_num;
2934 2934 igb->num_rx_rings = igb->capab->def_rx_que_num;
2935 2935 } else {
2936 2936 igb->num_tx_rings = 1;
2937 2937 igb->num_rx_rings = 1;
2938 2938
2939 2939 if (igb->num_rx_groups > 1) {
2940 2940 igb_log(igb, IGB_LOG_ERROR,
2941 2941 "Invalid rx groups number. Please enable multiple "
2942 2942 "rings first");
2943 2943 igb->num_rx_groups = 1;
2944 2944 }
2945 2945 }
2946 2946
2947 2947 /*
2948 2948 * Check the divisibility between rx rings and rx groups.
2949 2949 */
2950 2950 for (i = igb->num_rx_groups; i > 0; i--) {
2951 2951 if ((igb->num_rx_rings % i) == 0)
2952 2952 break;
2953 2953 }
2954 2954 if (i != igb->num_rx_groups) {
2955 2955 igb_log(igb, IGB_LOG_ERROR,
2956 2956 "Invalid rx groups number. Downgrade the rx group "
2957 2957 "number to %d.", i);
2958 2958 igb->num_rx_groups = i;
2959 2959 }
2960 2960
2961 2961 /*
2962 2962 * Get the ring number per group.
2963 2963 */
2964 2964 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2965 2965
2966 2966 if (igb->num_rx_groups == 1) {
2967 2967 /*
2968 2968 * One rx ring group, the rx ring number is num_rx_rings.
2969 2969 */
2970 2970 igb->vmdq_mode = E1000_VMDQ_OFF;
2971 2971 } else if (ring_per_group == 1) {
2972 2972 /*
2973 2973 * Multiple rx groups, each group has one rx ring.
2974 2974 */
2975 2975 igb->vmdq_mode = E1000_VMDQ_MAC;
2976 2976 } else {
2977 2977 /*
2978 2978 * Multiple groups and multiple rings.
2979 2979 */
2980 2980 igb->vmdq_mode = E1000_VMDQ_MAC_RSS;
2981 2981 }
2982 2982
2983 2983 /*
2984 2984 * Tunable used to force an interrupt type. The only use is
2985 2985 * for testing of the lesser interrupt types.
2986 2986 * 0 = don't force interrupt type
2987 2987 * 1 = force interrupt type MSIX
2988 2988 * 2 = force interrupt type MSI
2989 2989 * 3 = force interrupt type Legacy
2990 2990 */
2991 2991 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE,
2992 2992 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE);
2993 2993
2994 2994 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE,
2995 2995 0, 1, 1);
2996 2996 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE,
2997 2997 0, 1, 1);
2998 2998 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE,
2999 2999 0, 1, 1);
3000 3000 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE,
3001 3001 0, 1, 1);
3002 3002
3003 3003 /*
3004 3004 * igb LSO needs the tx h/w checksum support.
3005 3005 * Here LSO will be disabled if tx h/w checksum has been disabled.
3006 3006 */
3007 3007 if (igb->tx_hcksum_enable == B_FALSE)
3008 3008 igb->lso_enable = B_FALSE;
3009 3009
3010 3010 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD,
3011 3011 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD,
3012 3012 DEFAULT_TX_COPY_THRESHOLD);
3013 3013 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD,
3014 3014 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD,
3015 3015 DEFAULT_TX_RECYCLE_THRESHOLD);
3016 3016 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD,
3017 3017 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD,
3018 3018 DEFAULT_TX_OVERLOAD_THRESHOLD);
3019 3019 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD,
3020 3020 MIN_TX_RESCHED_THRESHOLD,
3021 3021 MIN(igb->tx_ring_size, MAX_TX_RESCHED_THRESHOLD),
3022 3022 igb->tx_ring_size > DEFAULT_TX_RESCHED_THRESHOLD ?
3023 3023 DEFAULT_TX_RESCHED_THRESHOLD : DEFAULT_TX_RESCHED_THRESHOLD_LOW);
3024 3024
3025 3025 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD,
3026 3026 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD,
3027 3027 DEFAULT_RX_COPY_THRESHOLD);
3028 3028 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR,
3029 3029 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR,
3030 3030 DEFAULT_RX_LIMIT_PER_INTR);
3031 3031
3032 3032 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING,
3033 3033 igb->capab->min_intr_throttle,
3034 3034 igb->capab->max_intr_throttle,
3035 3035 igb->capab->def_intr_throttle);
3036 3036
3037 3037 /*
3038 3038 * Max number of multicast addresses
3039 3039 */
3040 3040 igb->mcast_max_num =
3041 3041 igb_get_prop(igb, PROP_MCAST_MAX_NUM,
3042 3042 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM);
3043 3043 }
3044 3044
3045 3045 /*
3046 3046 * igb_get_prop - Get a property value out of the configuration file igb.conf
3047 3047 *
3048 3048 * Caller provides the name of the property, a default value, a minimum
3049 3049 * value, and a maximum value.
3050 3050 *
3051 3051 * Return configured value of the property, with default, minimum and
3052 3052 * maximum properly applied.
3053 3053 */
3054 3054 static int
3055 3055 igb_get_prop(igb_t *igb,
3056 3056 char *propname, /* name of the property */
3057 3057 int minval, /* minimum acceptable value */
3058 3058 int maxval, /* maximim acceptable value */
3059 3059 int defval) /* default value */
3060 3060 {
3061 3061 int value;
3062 3062
3063 3063 /*
3064 3064 * Call ddi_prop_get_int() to read the conf settings
3065 3065 */
3066 3066 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip,
3067 3067 DDI_PROP_DONTPASS, propname, defval);
3068 3068
3069 3069 if (value > maxval)
3070 3070 value = maxval;
3071 3071
3072 3072 if (value < minval)
3073 3073 value = minval;
3074 3074
3075 3075 return (value);
3076 3076 }
3077 3077
3078 3078 /*
3079 3079 * igb_setup_link - Using the link properties to setup the link
3080 3080 */
3081 3081 int
3082 3082 igb_setup_link(igb_t *igb, boolean_t setup_hw)
3083 3083 {
3084 3084 struct e1000_mac_info *mac;
3085 3085 struct e1000_phy_info *phy;
3086 3086 boolean_t invalid;
3087 3087
3088 3088 mac = &igb->hw.mac;
3089 3089 phy = &igb->hw.phy;
3090 3090 invalid = B_FALSE;
3091 3091
3092 3092 if (igb->param_adv_autoneg_cap == 1) {
3093 3093 mac->autoneg = B_TRUE;
3094 3094 phy->autoneg_advertised = 0;
3095 3095
3096 3096 /*
3097 3097 * 1000hdx is not supported for autonegotiation
3098 3098 */
3099 3099 if (igb->param_adv_1000fdx_cap == 1)
3100 3100 phy->autoneg_advertised |= ADVERTISE_1000_FULL;
3101 3101
3102 3102 if (igb->param_adv_100fdx_cap == 1)
3103 3103 phy->autoneg_advertised |= ADVERTISE_100_FULL;
3104 3104
3105 3105 if (igb->param_adv_100hdx_cap == 1)
3106 3106 phy->autoneg_advertised |= ADVERTISE_100_HALF;
3107 3107
3108 3108 if (igb->param_adv_10fdx_cap == 1)
3109 3109 phy->autoneg_advertised |= ADVERTISE_10_FULL;
3110 3110
3111 3111 if (igb->param_adv_10hdx_cap == 1)
3112 3112 phy->autoneg_advertised |= ADVERTISE_10_HALF;
3113 3113
3114 3114 if (phy->autoneg_advertised == 0)
3115 3115 invalid = B_TRUE;
3116 3116 } else {
3117 3117 mac->autoneg = B_FALSE;
3118 3118
3119 3119 /*
3120 3120 * 1000fdx and 1000hdx are not supported for forced link
3121 3121 */
3122 3122 if (igb->param_adv_100fdx_cap == 1)
3123 3123 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3124 3124 else if (igb->param_adv_100hdx_cap == 1)
3125 3125 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3126 3126 else if (igb->param_adv_10fdx_cap == 1)
3127 3127 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3128 3128 else if (igb->param_adv_10hdx_cap == 1)
3129 3129 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3130 3130 else
3131 3131 invalid = B_TRUE;
3132 3132 }
3133 3133
3134 3134 if (invalid) {
3135 3135 igb_log(igb, IGB_LOG_INFO, "Invalid link settings. Setup "
3136 3136 "link to autonegotiation with full link capabilities.");
3137 3137 mac->autoneg = B_TRUE;
3138 3138 phy->autoneg_advertised = ADVERTISE_1000_FULL |
3139 3139 ADVERTISE_100_FULL | ADVERTISE_100_HALF |
3140 3140 ADVERTISE_10_FULL | ADVERTISE_10_HALF;
3141 3141 }
3142 3142
3143 3143 if (setup_hw) {
3144 3144 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS)
3145 3145 return (IGB_FAILURE);
3146 3146 }
3147 3147
3148 3148 return (IGB_SUCCESS);
3149 3149 }
3150 3150
3151 3151
3152 3152 /*
3153 3153 * igb_is_link_up - Check if the link is up
3154 3154 */
3155 3155 static boolean_t
3156 3156 igb_is_link_up(igb_t *igb)
3157 3157 {
3158 3158 struct e1000_hw *hw = &igb->hw;
3159 3159 boolean_t link_up = B_FALSE;
3160 3160
3161 3161 ASSERT(mutex_owned(&igb->gen_lock));
3162 3162
3163 3163 /*
3164 3164 * get_link_status is set in the interrupt handler on link-status-change
3165 3165 * or rx sequence error interrupt. get_link_status will stay
3166 3166 * false until the e1000_check_for_link establishes link only
3167 3167 * for copper adapters.
3168 3168 */
3169 3169 switch (hw->phy.media_type) {
3170 3170 case e1000_media_type_copper:
3171 3171 if (hw->mac.get_link_status) {
3172 3172 (void) e1000_check_for_link(hw);
3173 3173 link_up = !hw->mac.get_link_status;
3174 3174 } else {
3175 3175 link_up = B_TRUE;
3176 3176 }
3177 3177 break;
3178 3178 case e1000_media_type_fiber:
3179 3179 (void) e1000_check_for_link(hw);
3180 3180 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
3181 3181 break;
3182 3182 case e1000_media_type_internal_serdes:
3183 3183 (void) e1000_check_for_link(hw);
3184 3184 link_up = hw->mac.serdes_has_link;
3185 3185 break;
3186 3186 }
3187 3187
3188 3188 return (link_up);
3189 3189 }
3190 3190
3191 3191 /*
3192 3192 * igb_link_check - Link status processing
3193 3193 */
3194 3194 static boolean_t
3195 3195 igb_link_check(igb_t *igb)
3196 3196 {
3197 3197 struct e1000_hw *hw = &igb->hw;
3198 3198 uint16_t speed = 0, duplex = 0;
3199 3199 boolean_t link_changed = B_FALSE;
3200 3200
3201 3201 ASSERT(mutex_owned(&igb->gen_lock));
3202 3202
3203 3203 if (igb_is_link_up(igb)) {
3204 3204 /*
3205 3205 * The Link is up, check whether it was marked as down earlier
3206 3206 */
3207 3207 if (igb->link_state != LINK_STATE_UP) {
3208 3208 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex);
3209 3209 igb->link_speed = speed;
3210 3210 igb->link_duplex = duplex;
3211 3211 igb->link_state = LINK_STATE_UP;
3212 3212 link_changed = B_TRUE;
3213 3213 if (!igb->link_complete)
3214 3214 igb_stop_link_timer(igb);
3215 3215 }
3216 3216 } else if (igb->link_complete) {
3217 3217 if (igb->link_state != LINK_STATE_DOWN) {
3218 3218 igb->link_speed = 0;
3219 3219 igb->link_duplex = 0;
3220 3220 igb->link_state = LINK_STATE_DOWN;
3221 3221 link_changed = B_TRUE;
3222 3222 }
3223 3223 }
3224 3224
3225 3225 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3226 3226 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3227 3227 return (B_FALSE);
3228 3228 }
3229 3229
3230 3230 return (link_changed);
3231 3231 }
3232 3232
3233 3233 /*
3234 3234 * igb_local_timer - driver watchdog function
3235 3235 *
3236 3236 * This function will handle the hardware stall check, link status
3237 3237 * check and other routines.
3238 3238 */
3239 3239 static void
3240 3240 igb_local_timer(void *arg)
3241 3241 {
3242 3242 igb_t *igb = (igb_t *)arg;
3243 3243 boolean_t link_changed = B_FALSE;
3244 3244
3245 3245 if (igb->igb_state & IGB_ERROR) {
3246 3246 igb->reset_count++;
3247 3247 if (igb_reset(igb) == IGB_SUCCESS)
3248 3248 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
3249 3249
3250 3250 igb_restart_watchdog_timer(igb);
3251 3251 return;
3252 3252 }
3253 3253
3254 3254 if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) {
3255 3255 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL);
3256 3256 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
3257 3257 igb->reset_count++;
3258 3258 if (igb_reset(igb) == IGB_SUCCESS)
3259 3259 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
3260 3260
3261 3261 igb_restart_watchdog_timer(igb);
3262 3262 return;
3263 3263 }
3264 3264
3265 3265 mutex_enter(&igb->gen_lock);
3266 3266 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED))
3267 3267 link_changed = igb_link_check(igb);
3268 3268 mutex_exit(&igb->gen_lock);
3269 3269
3270 3270 if (link_changed)
3271 3271 mac_link_update(igb->mac_hdl, igb->link_state);
3272 3272
3273 3273 igb_restart_watchdog_timer(igb);
3274 3274 }
3275 3275
3276 3276 /*
3277 3277 * igb_link_timer - link setup timer function
3278 3278 *
3279 3279 * It is called when the timer for link setup is expired, which indicates
3280 3280 * the completion of the link setup. The link state will not be updated
3281 3281 * until the link setup is completed. And the link state will not be sent
3282 3282 * to the upper layer through mac_link_update() in this function. It will
3283 3283 * be updated in the local timer routine or the interrupts service routine
3284 3284 * after the interface is started (plumbed).
3285 3285 */
3286 3286 static void
3287 3287 igb_link_timer(void *arg)
3288 3288 {
3289 3289 igb_t *igb = (igb_t *)arg;
3290 3290
3291 3291 mutex_enter(&igb->link_lock);
3292 3292 igb->link_complete = B_TRUE;
3293 3293 igb->link_tid = 0;
3294 3294 mutex_exit(&igb->link_lock);
3295 3295 }
3296 3296 /*
3297 3297 * igb_stall_check - check for transmit stall
3298 3298 *
3299 3299 * This function checks if the adapter is stalled (in transmit).
3300 3300 *
3301 3301 * It is called each time the watchdog timeout is invoked.
3302 3302 * If the transmit descriptor reclaim continuously fails,
3303 3303 * the watchdog value will increment by 1. If the watchdog
3304 3304 * value exceeds the threshold, the igb is assumed to
3305 3305 * have stalled and need to be reset.
3306 3306 */
3307 3307 static boolean_t
3308 3308 igb_stall_check(igb_t *igb)
3309 3309 {
3310 3310 igb_tx_ring_t *tx_ring;
3311 3311 struct e1000_hw *hw = &igb->hw;
3312 3312 boolean_t result;
3313 3313 int i;
3314 3314
3315 3315 if (igb->link_state != LINK_STATE_UP)
3316 3316 return (B_FALSE);
3317 3317
3318 3318 /*
3319 3319 * If any tx ring is stalled, we'll reset the chipset
3320 3320 */
3321 3321 result = B_FALSE;
3322 3322 for (i = 0; i < igb->num_tx_rings; i++) {
3323 3323 tx_ring = &igb->tx_rings[i];
3324 3324
3325 3325 if (tx_ring->recycle_fail > 0)
3326 3326 tx_ring->stall_watchdog++;
3327 3327 else
3328 3328 tx_ring->stall_watchdog = 0;
3329 3329
3330 3330 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) {
3331 3331 result = B_TRUE;
3332 3332 if (hw->mac.type == e1000_82580) {
3333 3333 hw->dev_spec._82575.global_device_reset
3334 3334 = B_TRUE;
3335 3335 }
3336 3336 break;
3337 3337 }
3338 3338 }
3339 3339
3340 3340 if (result) {
3341 3341 tx_ring->stall_watchdog = 0;
3342 3342 tx_ring->recycle_fail = 0;
3343 3343 }
3344 3344
3345 3345 return (result);
3346 3346 }
3347 3347
3348 3348
3349 3349 /*
3350 3350 * is_valid_mac_addr - Check if the mac address is valid
3351 3351 */
3352 3352 static boolean_t
3353 3353 is_valid_mac_addr(uint8_t *mac_addr)
3354 3354 {
3355 3355 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
3356 3356 const uint8_t addr_test2[6] =
3357 3357 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3358 3358
3359 3359 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
3360 3360 !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
3361 3361 return (B_FALSE);
3362 3362
3363 3363 return (B_TRUE);
3364 3364 }
3365 3365
3366 3366 static boolean_t
3367 3367 igb_find_mac_address(igb_t *igb)
3368 3368 {
3369 3369 struct e1000_hw *hw = &igb->hw;
3370 3370 #ifdef __sparc
3371 3371 uchar_t *bytes;
3372 3372 struct ether_addr sysaddr;
3373 3373 uint_t nelts;
3374 3374 int err;
3375 3375 boolean_t found = B_FALSE;
3376 3376
3377 3377 /*
3378 3378 * The "vendor's factory-set address" may already have
3379 3379 * been extracted from the chip, but if the property
3380 3380 * "local-mac-address" is set we use that instead.
3381 3381 *
3382 3382 * We check whether it looks like an array of 6
3383 3383 * bytes (which it should, if OBP set it). If we can't
3384 3384 * make sense of it this way, we'll ignore it.
3385 3385 */
3386 3386 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
3387 3387 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
3388 3388 if (err == DDI_PROP_SUCCESS) {
3389 3389 if (nelts == ETHERADDRL) {
3390 3390 while (nelts--)
3391 3391 hw->mac.addr[nelts] = bytes[nelts];
3392 3392 found = B_TRUE;
3393 3393 }
3394 3394 ddi_prop_free(bytes);
3395 3395 }
3396 3396
3397 3397 /*
3398 3398 * Look up the OBP property "local-mac-address?". If the user has set
3399 3399 * 'local-mac-address? = false', use "the system address" instead.
3400 3400 */
3401 3401 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0,
3402 3402 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
3403 3403 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
3404 3404 if (localetheraddr(NULL, &sysaddr) != 0) {
3405 3405 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
3406 3406 found = B_TRUE;
3407 3407 }
3408 3408 }
3409 3409 ddi_prop_free(bytes);
3410 3410 }
3411 3411
3412 3412 /*
3413 3413 * Finally(!), if there's a valid "mac-address" property (created
3414 3414 * if we netbooted from this interface), we must use this instead
3415 3415 * of any of the above to ensure that the NFS/install server doesn't
3416 3416 * get confused by the address changing as Solaris takes over!
3417 3417 */
3418 3418 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
3419 3419 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
3420 3420 if (err == DDI_PROP_SUCCESS) {
3421 3421 if (nelts == ETHERADDRL) {
3422 3422 while (nelts--)
3423 3423 hw->mac.addr[nelts] = bytes[nelts];
3424 3424 found = B_TRUE;
3425 3425 }
3426 3426 ddi_prop_free(bytes);
3427 3427 }
3428 3428
3429 3429 if (found) {
3430 3430 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL);
3431 3431 return (B_TRUE);
3432 3432 }
3433 3433 #endif
3434 3434
3435 3435 /*
3436 3436 * Read the device MAC address from the EEPROM
3437 3437 */
3438 3438 if (e1000_read_mac_addr(hw) != E1000_SUCCESS)
3439 3439 return (B_FALSE);
3440 3440
3441 3441 return (B_TRUE);
3442 3442 }
3443 3443
3444 3444 #pragma inline(igb_arm_watchdog_timer)
3445 3445
3446 3446 static void
3447 3447 igb_arm_watchdog_timer(igb_t *igb)
3448 3448 {
3449 3449 /*
3450 3450 * Fire a watchdog timer
3451 3451 */
3452 3452 igb->watchdog_tid =
3453 3453 timeout(igb_local_timer,
3454 3454 (void *)igb, 1 * drv_usectohz(1000000));
3455 3455
3456 3456 }
3457 3457
3458 3458 /*
3459 3459 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer
3460 3460 */
3461 3461 void
3462 3462 igb_enable_watchdog_timer(igb_t *igb)
3463 3463 {
3464 3464 mutex_enter(&igb->watchdog_lock);
3465 3465
3466 3466 if (!igb->watchdog_enable) {
3467 3467 igb->watchdog_enable = B_TRUE;
3468 3468 igb->watchdog_start = B_TRUE;
3469 3469 igb_arm_watchdog_timer(igb);
3470 3470 }
3471 3471
3472 3472 mutex_exit(&igb->watchdog_lock);
3473 3473
3474 3474 }
3475 3475
3476 3476 /*
3477 3477 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer
3478 3478 */
3479 3479 void
3480 3480 igb_disable_watchdog_timer(igb_t *igb)
3481 3481 {
3482 3482 timeout_id_t tid;
3483 3483
3484 3484 mutex_enter(&igb->watchdog_lock);
3485 3485
3486 3486 igb->watchdog_enable = B_FALSE;
3487 3487 igb->watchdog_start = B_FALSE;
3488 3488 tid = igb->watchdog_tid;
3489 3489 igb->watchdog_tid = 0;
3490 3490
3491 3491 mutex_exit(&igb->watchdog_lock);
3492 3492
3493 3493 if (tid != 0)
3494 3494 (void) untimeout(tid);
3495 3495
3496 3496 }
3497 3497
3498 3498 /*
3499 3499 * igb_start_watchdog_timer - Start the driver watchdog timer
3500 3500 */
3501 3501 static void
3502 3502 igb_start_watchdog_timer(igb_t *igb)
3503 3503 {
3504 3504 mutex_enter(&igb->watchdog_lock);
3505 3505
3506 3506 if (igb->watchdog_enable) {
3507 3507 if (!igb->watchdog_start) {
3508 3508 igb->watchdog_start = B_TRUE;
3509 3509 igb_arm_watchdog_timer(igb);
3510 3510 }
3511 3511 }
3512 3512
3513 3513 mutex_exit(&igb->watchdog_lock);
3514 3514 }
3515 3515
3516 3516 /*
3517 3517 * igb_restart_watchdog_timer - Restart the driver watchdog timer
3518 3518 */
3519 3519 static void
3520 3520 igb_restart_watchdog_timer(igb_t *igb)
3521 3521 {
3522 3522 mutex_enter(&igb->watchdog_lock);
3523 3523
3524 3524 if (igb->watchdog_start)
3525 3525 igb_arm_watchdog_timer(igb);
3526 3526
3527 3527 mutex_exit(&igb->watchdog_lock);
3528 3528 }
3529 3529
3530 3530 /*
3531 3531 * igb_stop_watchdog_timer - Stop the driver watchdog timer
3532 3532 */
3533 3533 static void
3534 3534 igb_stop_watchdog_timer(igb_t *igb)
3535 3535 {
3536 3536 timeout_id_t tid;
3537 3537
3538 3538 mutex_enter(&igb->watchdog_lock);
3539 3539
3540 3540 igb->watchdog_start = B_FALSE;
3541 3541 tid = igb->watchdog_tid;
3542 3542 igb->watchdog_tid = 0;
3543 3543
3544 3544 mutex_exit(&igb->watchdog_lock);
3545 3545
3546 3546 if (tid != 0)
3547 3547 (void) untimeout(tid);
3548 3548 }
3549 3549
3550 3550 /*
3551 3551 * igb_start_link_timer - Start the link setup timer
3552 3552 */
3553 3553 static void
3554 3554 igb_start_link_timer(struct igb *igb)
3555 3555 {
3556 3556 struct e1000_hw *hw = &igb->hw;
3557 3557 clock_t link_timeout;
3558 3558
3559 3559 if (hw->mac.autoneg)
3560 3560 link_timeout = PHY_AUTO_NEG_LIMIT *
3561 3561 drv_usectohz(100000);
3562 3562 else
3563 3563 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000);
3564 3564
3565 3565 mutex_enter(&igb->link_lock);
3566 3566 if (hw->phy.autoneg_wait_to_complete) {
3567 3567 igb->link_complete = B_TRUE;
3568 3568 } else {
3569 3569 igb->link_complete = B_FALSE;
3570 3570 igb->link_tid = timeout(igb_link_timer, (void *)igb,
3571 3571 link_timeout);
3572 3572 }
3573 3573 mutex_exit(&igb->link_lock);
3574 3574 }
3575 3575
3576 3576 /*
3577 3577 * igb_stop_link_timer - Stop the link setup timer
3578 3578 */
3579 3579 static void
3580 3580 igb_stop_link_timer(struct igb *igb)
3581 3581 {
3582 3582 timeout_id_t tid;
3583 3583
3584 3584 mutex_enter(&igb->link_lock);
3585 3585 igb->link_complete = B_TRUE;
3586 3586 tid = igb->link_tid;
3587 3587 igb->link_tid = 0;
3588 3588 mutex_exit(&igb->link_lock);
3589 3589
3590 3590 if (tid != 0)
3591 3591 (void) untimeout(tid);
3592 3592 }
3593 3593
3594 3594 /*
3595 3595 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts
3596 3596 */
3597 3597 static void
3598 3598 igb_disable_adapter_interrupts(igb_t *igb)
3599 3599 {
3600 3600 struct e1000_hw *hw = &igb->hw;
3601 3601
3602 3602 /*
3603 3603 * Set the IMC register to mask all the interrupts,
3604 3604 * including the tx interrupts.
3605 3605 */
3606 3606 E1000_WRITE_REG(hw, E1000_IMC, ~0);
3607 3607 E1000_WRITE_REG(hw, E1000_IAM, 0);
3608 3608
3609 3609 /*
3610 3610 * Additional disabling for MSI-X
3611 3611 */
3612 3612 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3613 3613 E1000_WRITE_REG(hw, E1000_EIMC, ~0);
3614 3614 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3615 3615 E1000_WRITE_REG(hw, E1000_EIAM, 0);
3616 3616 }
3617 3617
3618 3618 E1000_WRITE_FLUSH(hw);
3619 3619 }
3620 3620
3621 3621 /*
3622 3622 * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580
3623 3623 */
3624 3624 static void
3625 3625 igb_enable_adapter_interrupts_82580(igb_t *igb)
3626 3626 {
3627 3627 struct e1000_hw *hw = &igb->hw;
3628 3628
3629 3629 /* Clear any pending interrupts */
3630 3630 (void) E1000_READ_REG(hw, E1000_ICR);
3631 3631 igb->ims_mask |= E1000_IMS_DRSTA;
3632 3632
3633 3633 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3634 3634
3635 3635 /* Interrupt enabling for MSI-X */
3636 3636 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3637 3637 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3638 3638 igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA);
3639 3639 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
3640 3640 } else { /* Interrupt enabling for MSI and legacy */
3641 3641 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
3642 3642 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
3643 3643 igb->ims_mask |= E1000_IMS_DRSTA;
3644 3644 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
3645 3645 }
3646 3646
3647 3647 /* Disable auto-mask for ICR interrupt bits */
3648 3648 E1000_WRITE_REG(hw, E1000_IAM, 0);
3649 3649
3650 3650 E1000_WRITE_FLUSH(hw);
3651 3651 }
3652 3652
3653 3653 /*
3654 3654 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576
3655 3655 */
3656 3656 static void
3657 3657 igb_enable_adapter_interrupts_82576(igb_t *igb)
3658 3658 {
3659 3659 struct e1000_hw *hw = &igb->hw;
3660 3660
3661 3661 /* Clear any pending interrupts */
3662 3662 (void) E1000_READ_REG(hw, E1000_ICR);
3663 3663
3664 3664 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3665 3665
3666 3666 /* Interrupt enabling for MSI-X */
3667 3667 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3668 3668 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3669 3669 igb->ims_mask = E1000_IMS_LSC;
3670 3670 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3671 3671 } else {
3672 3672 /* Interrupt enabling for MSI and legacy */
3673 3673 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
3674 3674 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
3675 3675 E1000_WRITE_REG(hw, E1000_IMS,
3676 3676 (IMS_ENABLE_MASK | E1000_IMS_TXQE));
3677 3677 }
3678 3678
3679 3679 /* Disable auto-mask for ICR interrupt bits */
3680 3680 E1000_WRITE_REG(hw, E1000_IAM, 0);
3681 3681
3682 3682 E1000_WRITE_FLUSH(hw);
3683 3683 }
3684 3684
3685 3685 /*
3686 3686 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575
3687 3687 */
3688 3688 static void
3689 3689 igb_enable_adapter_interrupts_82575(igb_t *igb)
3690 3690 {
3691 3691 struct e1000_hw *hw = &igb->hw;
3692 3692 uint32_t reg;
3693 3693
3694 3694 /* Clear any pending interrupts */
3695 3695 (void) E1000_READ_REG(hw, E1000_ICR);
3696 3696
3697 3697 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3698 3698 /* Interrupt enabling for MSI-X */
3699 3699 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3700 3700 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3701 3701 igb->ims_mask = E1000_IMS_LSC;
3702 3702 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3703 3703
3704 3704 /* Enable MSI-X PBA support */
3705 3705 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
3706 3706 reg |= E1000_CTRL_EXT_PBA_CLR;
3707 3707
3708 3708 /* Non-selective interrupt clear-on-read */
3709 3709 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */
3710 3710
3711 3711 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
3712 3712 } else {
3713 3713 /* Interrupt enabling for MSI and legacy */
3714 3714 igb->ims_mask = IMS_ENABLE_MASK;
3715 3715 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3716 3716 }
3717 3717
3718 3718 E1000_WRITE_FLUSH(hw);
3719 3719 }
3720 3720
3721 3721 /*
3722 3722 * Loopback Support
3723 3723 */
3724 3724 static lb_property_t lb_normal =
3725 3725 { normal, "normal", IGB_LB_NONE };
3726 3726 static lb_property_t lb_external =
3727 3727 { external, "External", IGB_LB_EXTERNAL };
3728 3728 static lb_property_t lb_phy =
3729 3729 { internal, "PHY", IGB_LB_INTERNAL_PHY };
3730 3730 static lb_property_t lb_serdes =
3731 3731 { internal, "SerDes", IGB_LB_INTERNAL_SERDES };
3732 3732
3733 3733 enum ioc_reply
3734 3734 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp)
3735 3735 {
3736 3736 lb_info_sz_t *lbsp;
3737 3737 lb_property_t *lbpp;
3738 3738 struct e1000_hw *hw;
3739 3739 uint32_t *lbmp;
3740 3740 uint32_t size;
3741 3741 uint32_t value;
3742 3742
3743 3743 hw = &igb->hw;
3744 3744
3745 3745 if (mp->b_cont == NULL)
3746 3746 return (IOC_INVAL);
3747 3747
3748 3748 switch (iocp->ioc_cmd) {
3749 3749 default:
3750 3750 return (IOC_INVAL);
3751 3751
3752 3752 case LB_GET_INFO_SIZE:
3753 3753 size = sizeof (lb_info_sz_t);
3754 3754 if (iocp->ioc_count != size)
3755 3755 return (IOC_INVAL);
3756 3756
3757 3757 value = sizeof (lb_normal);
3758 3758 if (hw->phy.media_type == e1000_media_type_copper)
3759 3759 value += sizeof (lb_phy);
3760 3760 else
3761 3761 value += sizeof (lb_serdes);
3762 3762 value += sizeof (lb_external);
3763 3763
3764 3764 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
3765 3765 *lbsp = value;
3766 3766 break;
3767 3767
3768 3768 case LB_GET_INFO:
3769 3769 value = sizeof (lb_normal);
3770 3770 if (hw->phy.media_type == e1000_media_type_copper)
3771 3771 value += sizeof (lb_phy);
3772 3772 else
3773 3773 value += sizeof (lb_serdes);
3774 3774 value += sizeof (lb_external);
3775 3775
3776 3776 size = value;
3777 3777 if (iocp->ioc_count != size)
3778 3778 return (IOC_INVAL);
3779 3779
3780 3780 value = 0;
3781 3781 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
3782 3782
3783 3783 lbpp[value++] = lb_normal;
3784 3784 if (hw->phy.media_type == e1000_media_type_copper)
3785 3785 lbpp[value++] = lb_phy;
3786 3786 else
3787 3787 lbpp[value++] = lb_serdes;
3788 3788 lbpp[value++] = lb_external;
3789 3789 break;
3790 3790
3791 3791 case LB_GET_MODE:
3792 3792 size = sizeof (uint32_t);
3793 3793 if (iocp->ioc_count != size)
3794 3794 return (IOC_INVAL);
3795 3795
3796 3796 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3797 3797 *lbmp = igb->loopback_mode;
3798 3798 break;
3799 3799
3800 3800 case LB_SET_MODE:
3801 3801 size = 0;
3802 3802 if (iocp->ioc_count != sizeof (uint32_t))
3803 3803 return (IOC_INVAL);
3804 3804
3805 3805 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3806 3806 if (!igb_set_loopback_mode(igb, *lbmp))
3807 3807 return (IOC_INVAL);
3808 3808 break;
3809 3809 }
3810 3810
3811 3811 iocp->ioc_count = size;
3812 3812 iocp->ioc_error = 0;
3813 3813
3814 3814 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3815 3815 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3816 3816 return (IOC_INVAL);
3817 3817 }
3818 3818
3819 3819 return (IOC_REPLY);
3820 3820 }
3821 3821
3822 3822 /*
3823 3823 * igb_set_loopback_mode - Setup loopback based on the loopback mode
3824 3824 */
3825 3825 static boolean_t
3826 3826 igb_set_loopback_mode(igb_t *igb, uint32_t mode)
3827 3827 {
3828 3828 struct e1000_hw *hw;
3829 3829 int i;
3830 3830
3831 3831 if (mode == igb->loopback_mode)
3832 3832 return (B_TRUE);
3833 3833
3834 3834 hw = &igb->hw;
3835 3835
3836 3836 igb->loopback_mode = mode;
3837 3837
3838 3838 if (mode == IGB_LB_NONE) {
3839 3839 /* Reset the chip */
3840 3840 hw->phy.autoneg_wait_to_complete = B_TRUE;
3841 3841 (void) igb_reset(igb);
3842 3842 hw->phy.autoneg_wait_to_complete = B_FALSE;
3843 3843 return (B_TRUE);
3844 3844 }
3845 3845
3846 3846 mutex_enter(&igb->gen_lock);
3847 3847
3848 3848 switch (mode) {
3849 3849 default:
3850 3850 mutex_exit(&igb->gen_lock);
3851 3851 return (B_FALSE);
3852 3852
3853 3853 case IGB_LB_EXTERNAL:
3854 3854 igb_set_external_loopback(igb);
3855 3855 break;
3856 3856
3857 3857 case IGB_LB_INTERNAL_PHY:
3858 3858 igb_set_internal_phy_loopback(igb);
3859 3859 break;
3860 3860
3861 3861 case IGB_LB_INTERNAL_SERDES:
3862 3862 igb_set_internal_serdes_loopback(igb);
3863 3863 break;
3864 3864 }
3865 3865
3866 3866 mutex_exit(&igb->gen_lock);
3867 3867
3868 3868 /*
3869 3869 * When external loopback is set, wait up to 1000ms to get the link up.
3870 3870 * According to test, 1000ms can work and it's an experimental value.
3871 3871 */
3872 3872 if (mode == IGB_LB_EXTERNAL) {
3873 3873 for (i = 0; i <= 10; i++) {
3874 3874 mutex_enter(&igb->gen_lock);
3875 3875 (void) igb_link_check(igb);
3876 3876 mutex_exit(&igb->gen_lock);
3877 3877
3878 3878 if (igb->link_state == LINK_STATE_UP)
3879 3879 break;
3880 3880
3881 3881 msec_delay(100);
3882 3882 }
3883 3883
3884 3884 if (igb->link_state != LINK_STATE_UP) {
3885 3885 /*
3886 3886 * Does not support external loopback.
3887 3887 * Reset driver to loopback none.
3888 3888 */
3889 3889 igb->loopback_mode = IGB_LB_NONE;
3890 3890
3891 3891 /* Reset the chip */
3892 3892 hw->phy.autoneg_wait_to_complete = B_TRUE;
3893 3893 (void) igb_reset(igb);
3894 3894 hw->phy.autoneg_wait_to_complete = B_FALSE;
3895 3895
3896 3896 igb_log(igb, IGB_LOG_INFO, "Set external loopback "
3897 3897 "failed, reset to loopback none.");
3898 3898
3899 3899 return (B_FALSE);
3900 3900 }
3901 3901 }
3902 3902
3903 3903 return (B_TRUE);
3904 3904 }
3905 3905
3906 3906 /*
3907 3907 * igb_set_external_loopback - Set the external loopback mode
3908 3908 */
3909 3909 static void
3910 3910 igb_set_external_loopback(igb_t *igb)
3911 3911 {
3912 3912 struct e1000_hw *hw;
3913 3913 uint32_t ctrl_ext;
3914 3914
3915 3915 hw = &igb->hw;
3916 3916
3917 3917 /* Set link mode to PHY (00b) in the Extended Control register */
3918 3918 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3919 3919 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
3920 3920 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3921 3921
3922 3922 (void) e1000_write_phy_reg(hw, 0x0, 0x0140);
3923 3923 (void) e1000_write_phy_reg(hw, 0x9, 0x1a00);
3924 3924 (void) e1000_write_phy_reg(hw, 0x12, 0x1610);
3925 3925 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c);
3926 3926 }
3927 3927
3928 3928 /*
3929 3929 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode
3930 3930 */
3931 3931 static void
3932 3932 igb_set_internal_phy_loopback(igb_t *igb)
3933 3933 {
3934 3934 struct e1000_hw *hw;
3935 3935 uint32_t ctrl_ext;
3936 3936 uint16_t phy_ctrl;
3937 3937 uint16_t phy_pconf;
3938 3938
3939 3939 hw = &igb->hw;
3940 3940
3941 3941 /* Set link mode to PHY (00b) in the Extended Control register */
3942 3942 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3943 3943 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
3944 3944 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3945 3945
3946 3946 /*
3947 3947 * Set PHY control register (0x4140):
3948 3948 * Set full duplex mode
3949 3949 * Set loopback bit
3950 3950 * Clear auto-neg enable bit
3951 3951 * Set PHY speed
3952 3952 */
3953 3953 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK;
3954 3954 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
3955 3955
3956 3956 /* Set the link disable bit in the Port Configuration register */
3957 3957 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf);
3958 3958 phy_pconf |= (uint16_t)1 << 14;
3959 3959 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf);
3960 3960 }
3961 3961
3962 3962 /*
3963 3963 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode
3964 3964 */
3965 3965 static void
3966 3966 igb_set_internal_serdes_loopback(igb_t *igb)
3967 3967 {
3968 3968 struct e1000_hw *hw;
3969 3969 uint32_t ctrl_ext;
3970 3970 uint32_t ctrl;
3971 3971 uint32_t pcs_lctl;
3972 3972 uint32_t connsw;
3973 3973
3974 3974 hw = &igb->hw;
3975 3975
3976 3976 /* Set link mode to SerDes (11b) in the Extended Control register */
3977 3977 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3978 3978 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
3979 3979 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3980 3980
3981 3981 /* Configure the SerDes to loopback */
3982 3982 E1000_WRITE_REG(hw, E1000_SCTL, 0x410);
3983 3983
3984 3984 /* Set Device Control register */
3985 3985 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3986 3986 ctrl |= (E1000_CTRL_FD | /* Force full duplex */
3987 3987 E1000_CTRL_SLU); /* Force link up */
3988 3988 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */
3989 3989 E1000_CTRL_TFCE | /* Disable transmit flow control */
3990 3990 E1000_CTRL_LRST); /* Clear link reset */
3991 3991 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3992 3992
3993 3993 /* Set PCS Link Control register */
3994 3994 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL);
3995 3995 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK |
3996 3996 E1000_PCS_LCTL_FSD |
3997 3997 E1000_PCS_LCTL_FDV_FULL |
3998 3998 E1000_PCS_LCTL_FLV_LINK_UP);
3999 3999 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE;
4000 4000 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl);
4001 4001
4002 4002 /* Set the Copper/Fiber Switch Control - CONNSW register */
4003 4003 connsw = E1000_READ_REG(hw, E1000_CONNSW);
4004 4004 connsw &= ~E1000_CONNSW_ENRGSRC;
4005 4005 E1000_WRITE_REG(hw, E1000_CONNSW, connsw);
4006 4006 }
4007 4007
4008 4008 #pragma inline(igb_intr_rx_work)
4009 4009 /*
4010 4010 * igb_intr_rx_work - rx processing of ISR
4011 4011 */
4012 4012 static void
4013 4013 igb_intr_rx_work(igb_rx_ring_t *rx_ring)
4014 4014 {
4015 4015 mblk_t *mp;
4016 4016
4017 4017 mutex_enter(&rx_ring->rx_lock);
4018 4018 mp = igb_rx(rx_ring, IGB_NO_POLL);
4019 4019 mutex_exit(&rx_ring->rx_lock);
4020 4020
4021 4021 if (mp != NULL)
4022 4022 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp,
4023 4023 rx_ring->ring_gen_num);
4024 4024 }
4025 4025
4026 4026 #pragma inline(igb_intr_tx_work)
4027 4027 /*
4028 4028 * igb_intr_tx_work - tx processing of ISR
4029 4029 */
4030 4030 static void
4031 4031 igb_intr_tx_work(igb_tx_ring_t *tx_ring)
4032 4032 {
4033 4033 igb_t *igb = tx_ring->igb;
4034 4034
4035 4035 /* Recycle the tx descriptors */
4036 4036 tx_ring->tx_recycle(tx_ring);
4037 4037
4038 4038 /* Schedule the re-transmit */
4039 4039 if (tx_ring->reschedule &&
4040 4040 (tx_ring->tbd_free >= igb->tx_resched_thresh)) {
4041 4041 tx_ring->reschedule = B_FALSE;
4042 4042 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle);
4043 4043 IGB_DEBUG_STAT(tx_ring->stat_reschedule);
4044 4044 }
4045 4045 }
4046 4046
4047 4047 #pragma inline(igb_intr_link_work)
4048 4048 /*
4049 4049 * igb_intr_link_work - link-status-change processing of ISR
4050 4050 */
4051 4051 static void
4052 4052 igb_intr_link_work(igb_t *igb)
4053 4053 {
4054 4054 boolean_t link_changed;
4055 4055
4056 4056 igb_stop_watchdog_timer(igb);
4057 4057
4058 4058 mutex_enter(&igb->gen_lock);
4059 4059
4060 4060 /*
4061 4061 * Because we got a link-status-change interrupt, force
4062 4062 * e1000_check_for_link() to look at phy
4063 4063 */
4064 4064 igb->hw.mac.get_link_status = B_TRUE;
4065 4065
4066 4066 /* igb_link_check takes care of link status change */
4067 4067 link_changed = igb_link_check(igb);
4068 4068
4069 4069 /* Get new phy state */
4070 4070 igb_get_phy_state(igb);
4071 4071
4072 4072 mutex_exit(&igb->gen_lock);
4073 4073
4074 4074 if (link_changed)
4075 4075 mac_link_update(igb->mac_hdl, igb->link_state);
4076 4076
4077 4077 igb_start_watchdog_timer(igb);
4078 4078 }
4079 4079
4080 4080 /*
4081 4081 * igb_intr_legacy - Interrupt handler for legacy interrupts
4082 4082 */
4083 4083 static uint_t
4084 4084 igb_intr_legacy(void *arg1, void *arg2)
4085 4085 {
4086 4086 igb_t *igb = (igb_t *)arg1;
4087 4087 igb_tx_ring_t *tx_ring;
4088 4088 uint32_t icr;
4089 4089 mblk_t *mp;
4090 4090 boolean_t tx_reschedule;
4091 4091 boolean_t link_changed;
4092 4092 uint_t result;
4093 4093
4094 4094 _NOTE(ARGUNUSED(arg2));
4095 4095
4096 4096 mutex_enter(&igb->gen_lock);
4097 4097
4098 4098 if (igb->igb_state & IGB_SUSPENDED) {
4099 4099 mutex_exit(&igb->gen_lock);
4100 4100 return (DDI_INTR_UNCLAIMED);
4101 4101 }
4102 4102
4103 4103 mp = NULL;
4104 4104 tx_reschedule = B_FALSE;
4105 4105 link_changed = B_FALSE;
4106 4106 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4107 4107
4108 4108 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4109 4109 mutex_exit(&igb->gen_lock);
4110 4110 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4111 4111 atomic_or_32(&igb->igb_state, IGB_ERROR);
4112 4112 return (DDI_INTR_UNCLAIMED);
4113 4113 }
4114 4114
4115 4115 if (icr & E1000_ICR_INT_ASSERTED) {
4116 4116 /*
4117 4117 * E1000_ICR_INT_ASSERTED bit was set:
4118 4118 * Read(Clear) the ICR, claim this interrupt,
4119 4119 * look for work to do.
4120 4120 */
4121 4121 ASSERT(igb->num_rx_rings == 1);
4122 4122 ASSERT(igb->num_tx_rings == 1);
4123 4123
4124 4124 /* Make sure all interrupt causes cleared */
4125 4125 (void) E1000_READ_REG(&igb->hw, E1000_EICR);
4126 4126
4127 4127 if (icr & E1000_ICR_RXT0) {
4128 4128 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL);
4129 4129 }
4130 4130
4131 4131 if (icr & E1000_ICR_TXDW) {
4132 4132 tx_ring = &igb->tx_rings[0];
4133 4133
4134 4134 /* Recycle the tx descriptors */
4135 4135 tx_ring->tx_recycle(tx_ring);
4136 4136
4137 4137 /* Schedule the re-transmit */
4138 4138 tx_reschedule = (tx_ring->reschedule &&
4139 4139 (tx_ring->tbd_free >= igb->tx_resched_thresh));
4140 4140 }
4141 4141
4142 4142 if (icr & E1000_ICR_LSC) {
4143 4143 /*
4144 4144 * Because we got a link-status-change interrupt, force
4145 4145 * e1000_check_for_link() to look at phy
4146 4146 */
4147 4147 igb->hw.mac.get_link_status = B_TRUE;
4148 4148
4149 4149 /* igb_link_check takes care of link status change */
4150 4150 link_changed = igb_link_check(igb);
4151 4151
4152 4152 /* Get new phy state */
4153 4153 igb_get_phy_state(igb);
4154 4154 }
4155 4155
4156 4156 if (icr & E1000_ICR_DRSTA) {
4157 4157 /* 82580 Full Device Reset needed */
4158 4158 atomic_or_32(&igb->igb_state, IGB_STALL);
4159 4159 }
4160 4160
4161 4161 result = DDI_INTR_CLAIMED;
4162 4162 } else {
4163 4163 /*
4164 4164 * E1000_ICR_INT_ASSERTED bit was not set:
4165 4165 * Don't claim this interrupt.
4166 4166 */
4167 4167 result = DDI_INTR_UNCLAIMED;
4168 4168 }
4169 4169
4170 4170 mutex_exit(&igb->gen_lock);
4171 4171
4172 4172 /*
4173 4173 * Do the following work outside of the gen_lock
4174 4174 */
4175 4175 if (mp != NULL)
4176 4176 mac_rx(igb->mac_hdl, NULL, mp);
4177 4177
4178 4178 if (tx_reschedule) {
4179 4179 tx_ring->reschedule = B_FALSE;
4180 4180 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle);
4181 4181 IGB_DEBUG_STAT(tx_ring->stat_reschedule);
4182 4182 }
4183 4183
4184 4184 if (link_changed)
4185 4185 mac_link_update(igb->mac_hdl, igb->link_state);
4186 4186
4187 4187 return (result);
4188 4188 }
4189 4189
4190 4190 /*
4191 4191 * igb_intr_msi - Interrupt handler for MSI
4192 4192 */
4193 4193 static uint_t
4194 4194 igb_intr_msi(void *arg1, void *arg2)
4195 4195 {
4196 4196 igb_t *igb = (igb_t *)arg1;
4197 4197 uint32_t icr;
4198 4198
4199 4199 _NOTE(ARGUNUSED(arg2));
4200 4200
4201 4201 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4202 4202
4203 4203 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4204 4204 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4205 4205 atomic_or_32(&igb->igb_state, IGB_ERROR);
4206 4206 return (DDI_INTR_CLAIMED);
4207 4207 }
4208 4208
4209 4209 /* Make sure all interrupt causes cleared */
4210 4210 (void) E1000_READ_REG(&igb->hw, E1000_EICR);
4211 4211
4212 4212 /*
4213 4213 * For MSI interrupt, we have only one vector,
4214 4214 * so we have only one rx ring and one tx ring enabled.
4215 4215 */
4216 4216 ASSERT(igb->num_rx_rings == 1);
4217 4217 ASSERT(igb->num_tx_rings == 1);
4218 4218
4219 4219 if (icr & E1000_ICR_RXT0) {
4220 4220 igb_intr_rx_work(&igb->rx_rings[0]);
4221 4221 }
4222 4222
4223 4223 if (icr & E1000_ICR_TXDW) {
4224 4224 igb_intr_tx_work(&igb->tx_rings[0]);
4225 4225 }
4226 4226
4227 4227 if (icr & E1000_ICR_LSC) {
4228 4228 igb_intr_link_work(igb);
4229 4229 }
4230 4230
4231 4231 if (icr & E1000_ICR_DRSTA) {
4232 4232 /* 82580 Full Device Reset needed */
4233 4233 atomic_or_32(&igb->igb_state, IGB_STALL);
4234 4234 }
4235 4235
4236 4236 return (DDI_INTR_CLAIMED);
4237 4237 }
4238 4238
4239 4239 /*
4240 4240 * igb_intr_rx - Interrupt handler for rx
4241 4241 */
4242 4242 static uint_t
4243 4243 igb_intr_rx(void *arg1, void *arg2)
4244 4244 {
4245 4245 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1;
4246 4246
4247 4247 _NOTE(ARGUNUSED(arg2));
4248 4248
4249 4249 /*
4250 4250 * Only used via MSI-X vector so don't check cause bits
4251 4251 * and only clean the given ring.
4252 4252 */
4253 4253 igb_intr_rx_work(rx_ring);
4254 4254
4255 4255 return (DDI_INTR_CLAIMED);
4256 4256 }
4257 4257
4258 4258 /*
4259 4259 * igb_intr_tx - Interrupt handler for tx
4260 4260 */
4261 4261 static uint_t
4262 4262 igb_intr_tx(void *arg1, void *arg2)
4263 4263 {
4264 4264 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1;
4265 4265
4266 4266 _NOTE(ARGUNUSED(arg2));
4267 4267
4268 4268 /*
4269 4269 * Only used via MSI-X vector so don't check cause bits
4270 4270 * and only clean the given ring.
4271 4271 */
4272 4272 igb_intr_tx_work(tx_ring);
4273 4273
4274 4274 return (DDI_INTR_CLAIMED);
4275 4275 }
4276 4276
4277 4277 /*
4278 4278 * igb_intr_tx_other - Interrupt handler for both tx and other
4279 4279 *
4280 4280 */
4281 4281 static uint_t
4282 4282 igb_intr_tx_other(void *arg1, void *arg2)
4283 4283 {
4284 4284 igb_t *igb = (igb_t *)arg1;
4285 4285 uint32_t icr;
4286 4286
4287 4287 _NOTE(ARGUNUSED(arg2));
4288 4288
4289 4289 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4290 4290
4291 4291 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4292 4292 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4293 4293 atomic_or_32(&igb->igb_state, IGB_ERROR);
4294 4294 return (DDI_INTR_CLAIMED);
4295 4295 }
4296 4296
4297 4297 /*
4298 4298 * Look for tx reclaiming work first. Remember, in the
4299 4299 * case of only interrupt sharing, only one tx ring is
4300 4300 * used
4301 4301 */
4302 4302 igb_intr_tx_work(&igb->tx_rings[0]);
4303 4303
4304 4304 /*
4305 4305 * Check for "other" causes.
4306 4306 */
4307 4307 if (icr & E1000_ICR_LSC) {
4308 4308 igb_intr_link_work(igb);
4309 4309 }
4310 4310
4311 4311 /*
4312 4312 * The DOUTSYNC bit indicates a tx packet dropped because
4313 4313 * DMA engine gets "out of sync". There isn't a real fix
4314 4314 * for this. The Intel recommendation is to count the number
4315 4315 * of occurrences so user can detect when it is happening.
4316 4316 * The issue is non-fatal and there's no recovery action
4317 4317 * available.
4318 4318 */
4319 4319 if (icr & E1000_ICR_DOUTSYNC) {
4320 4320 IGB_STAT(igb->dout_sync);
4321 4321 }
4322 4322
4323 4323 if (icr & E1000_ICR_DRSTA) {
4324 4324 /* 82580 Full Device Reset needed */
4325 4325 atomic_or_32(&igb->igb_state, IGB_STALL);
4326 4326 }
4327 4327
4328 4328 return (DDI_INTR_CLAIMED);
4329 4329 }
4330 4330
4331 4331 /*
4332 4332 * igb_alloc_intrs - Allocate interrupts for the driver
4333 4333 *
4334 4334 * Normal sequence is to try MSI-X; if not sucessful, try MSI;
4335 4335 * if not successful, try Legacy.
4336 4336 * igb->intr_force can be used to force sequence to start with
4337 4337 * any of the 3 types.
4338 4338 * If MSI-X is not used, number of tx/rx rings is forced to 1.
4339 4339 */
4340 4340 static int
4341 4341 igb_alloc_intrs(igb_t *igb)
4342 4342 {
4343 4343 dev_info_t *devinfo;
4344 4344 int intr_types;
4345 4345 int rc;
4346 4346
4347 4347 devinfo = igb->dip;
4348 4348
4349 4349 /* Get supported interrupt types */
4350 4350 rc = ddi_intr_get_supported_types(devinfo, &intr_types);
4351 4351
4352 4352 if (rc != DDI_SUCCESS) {
4353 4353 igb_log(igb, IGB_LOG_ERROR,
4354 4354 "Get supported interrupt types failed: %d", rc);
4355 4355 return (IGB_FAILURE);
4356 4356 }
4357 4357 igb_log(igb, IGB_LOG_INFO, "Supported interrupt types: %x",
4358 4358 intr_types);
4359 4359
4360 4360 igb->intr_type = 0;
4361 4361
4362 4362 /* Install MSI-X interrupts */
4363 4363 if ((intr_types & DDI_INTR_TYPE_MSIX) &&
4364 4364 (igb->intr_force <= IGB_INTR_MSIX)) {
4365 4365 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX);
4366 4366
4367 4367 if (rc == IGB_SUCCESS)
4368 4368 return (IGB_SUCCESS);
4369 4369
4370 4370 igb_log(igb, IGB_LOG_INFO,
4371 4371 "Allocate MSI-X failed, trying MSI interrupts...");
4372 4372 }
4373 4373
4374 4374 /* MSI-X not used, force rings to 1 */
4375 4375 igb->num_rx_rings = 1;
4376 4376 igb->num_tx_rings = 1;
4377 4377 igb_log(igb, IGB_LOG_INFO,
4378 4378 "MSI-X not used, force rx and tx queue number to 1");
4379 4379
4380 4380 /* Install MSI interrupts */
4381 4381 if ((intr_types & DDI_INTR_TYPE_MSI) &&
4382 4382 (igb->intr_force <= IGB_INTR_MSI)) {
4383 4383 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI);
4384 4384
4385 4385 if (rc == IGB_SUCCESS)
4386 4386 return (IGB_SUCCESS);
4387 4387
4388 4388 igb_log(igb, IGB_LOG_INFO,
4389 4389 "Allocate MSI failed, trying Legacy interrupts...");
4390 4390 }
4391 4391
4392 4392 /* Install legacy interrupts */
4393 4393 if (intr_types & DDI_INTR_TYPE_FIXED) {
4394 4394 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED);
4395 4395
4396 4396 if (rc == IGB_SUCCESS)
4397 4397 return (IGB_SUCCESS);
4398 4398
4399 4399 igb_log(igb, IGB_LOG_INFO,
4400 4400 "Allocate Legacy interrupts failed");
4401 4401 }
4402 4402
4403 4403 /* If none of the 3 types succeeded, return failure */
4404 4404 return (IGB_FAILURE);
4405 4405 }
4406 4406
4407 4407 /*
4408 4408 * igb_alloc_intr_handles - Allocate interrupt handles.
4409 4409 *
4410 4410 * For legacy and MSI, only 1 handle is needed. For MSI-X,
4411 4411 * if fewer than 2 handles are available, return failure.
4412 4412 * Upon success, this sets the number of Rx rings to a number that
4413 4413 * matches the handles available for Rx interrupts.
4414 4414 */
4415 4415 static int
4416 4416 igb_alloc_intr_handles(igb_t *igb, int intr_type)
4417 4417 {
4418 4418 dev_info_t *devinfo;
4419 4419 int orig, request, count, avail, actual;
4420 4420 int diff, minimum;
4421 4421 int rc;
4422 4422
4423 4423 devinfo = igb->dip;
4424 4424
4425 4425 switch (intr_type) {
4426 4426 case DDI_INTR_TYPE_FIXED:
4427 4427 request = 1; /* Request 1 legacy interrupt handle */
4428 4428 minimum = 1;
4429 4429 igb_log(igb, IGB_LOG_INFO, "interrupt type: legacy");
4430 4430 break;
4431 4431
4432 4432 case DDI_INTR_TYPE_MSI:
4433 4433 request = 1; /* Request 1 MSI interrupt handle */
4434 4434 minimum = 1;
4435 4435 igb_log(igb, IGB_LOG_INFO, "interrupt type: MSI");
4436 4436 break;
4437 4437
4438 4438 case DDI_INTR_TYPE_MSIX:
4439 4439 /*
4440 4440 * Number of vectors for the adapter is
4441 4441 * # rx rings + # tx rings
4442 4442 * One of tx vectors is for tx & other
4443 4443 */
4444 4444 request = igb->num_rx_rings + igb->num_tx_rings;
4445 4445 orig = request;
4446 4446 minimum = 2;
4447 4447 igb_log(igb, IGB_LOG_INFO, "interrupt type: MSI-X");
4448 4448 break;
4449 4449
4450 4450 default:
4451 4451 igb_log(igb, IGB_LOG_INFO,
4452 4452 "invalid call to igb_alloc_intr_handles(): %d\n",
4453 4453 intr_type);
4454 4454 return (IGB_FAILURE);
4455 4455 }
4456 4456 igb_log(igb, IGB_LOG_INFO,
4457 4457 "interrupt handles requested: %d minimum: %d",
4458 4458 request, minimum);
4459 4459
4460 4460 /*
4461 4461 * Get number of supported interrupts
4462 4462 */
4463 4463 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
4464 4464 if ((rc != DDI_SUCCESS) || (count < minimum)) {
4465 4465 igb_log(igb, IGB_LOG_INFO,
4466 4466 "Get supported interrupt number failed. "
4467 4467 "Return: %d, count: %d", rc, count);
4468 4468 return (IGB_FAILURE);
4469 4469 }
4470 4470 igb_log(igb, IGB_LOG_INFO, "interrupts supported: %d", count);
4471 4471
4472 4472 /*
4473 4473 * Get number of available interrupts
4474 4474 */
4475 4475 rc = ddi_intr_get_navail(devinfo, intr_type, &avail);
4476 4476 if ((rc != DDI_SUCCESS) || (avail < minimum)) {
4477 4477 igb_log(igb, IGB_LOG_INFO,
4478 4478 "Get available interrupt number failed. "
4479 4479 "Return: %d, available: %d", rc, avail);
4480 4480 return (IGB_FAILURE);
4481 4481 }
4482 4482 igb_log(igb, IGB_LOG_INFO, "interrupts available: %d", avail);
4483 4483
4484 4484 if (avail < request) {
4485 4485 igb_log(igb, IGB_LOG_INFO,
4486 4486 "Request %d handles, %d available",
4487 4487 request, avail);
4488 4488 request = avail;
4489 4489 }
4490 4490
4491 4491 actual = 0;
4492 4492 igb->intr_cnt = 0;
4493 4493
4494 4494 /*
4495 4495 * Allocate an array of interrupt handles
4496 4496 */
4497 4497 igb->intr_size = request * sizeof (ddi_intr_handle_t);
4498 4498 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP);
4499 4499
4500 4500 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0,
4501 4501 request, &actual, DDI_INTR_ALLOC_NORMAL);
4502 4502 if (rc != DDI_SUCCESS) {
4503 4503 igb_log(igb, IGB_LOG_INFO, "Allocate interrupts failed. "
4504 4504 "return: %d, request: %d, actual: %d",
4505 4505 rc, request, actual);
4506 4506 goto alloc_handle_fail;
4507 4507 }
4508 4508 igb_log(igb, IGB_LOG_INFO, "interrupts actually allocated: %d", actual);
4509 4509
4510 4510 igb->intr_cnt = actual;
4511 4511
4512 4512 if (actual < minimum) {
4513 4513 igb_log(igb, IGB_LOG_INFO,
4514 4514 "Insufficient interrupt handles allocated: %d",
4515 4515 actual);
4516 4516 goto alloc_handle_fail;
4517 4517 }
4518 4518
4519 4519 /*
4520 4520 * For MSI-X, actual might force us to reduce number of tx & rx rings
4521 4521 */
4522 4522 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) {
4523 4523 diff = orig - actual;
4524 4524 if (diff < igb->num_tx_rings) {
4525 4525 igb_log(igb, IGB_LOG_INFO,
4526 4526 "MSI-X vectors force Tx queue number to %d",
4527 4527 igb->num_tx_rings - diff);
4528 4528 igb->num_tx_rings -= diff;
4529 4529 } else {
4530 4530 igb_log(igb, IGB_LOG_INFO,
4531 4531 "MSI-X vectors force Tx queue number to 1");
4532 4532 igb->num_tx_rings = 1;
4533 4533
4534 4534 igb_log(igb, IGB_LOG_INFO,
4535 4535 "MSI-X vectors force Rx queue number to %d",
4536 4536 actual - 1);
4537 4537 igb->num_rx_rings = actual - 1;
4538 4538 }
4539 4539 }
4540 4540
4541 4541 /*
4542 4542 * Get priority for first vector, assume remaining are all the same
4543 4543 */
4544 4544 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri);
4545 4545 if (rc != DDI_SUCCESS) {
4546 4546 igb_log(igb, IGB_LOG_INFO,
4547 4547 "Get interrupt priority failed: %d", rc);
4548 4548 goto alloc_handle_fail;
4549 4549 }
4550 4550
4551 4551 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap);
4552 4552 if (rc != DDI_SUCCESS) {
4553 4553 igb_log(igb, IGB_LOG_INFO,
4554 4554 "Get interrupt cap failed: %d", rc);
4555 4555 goto alloc_handle_fail;
4556 4556 }
4557 4557
4558 4558 igb->intr_type = intr_type;
4559 4559
4560 4560 return (IGB_SUCCESS);
4561 4561
4562 4562 alloc_handle_fail:
4563 4563 igb_rem_intrs(igb);
4564 4564
4565 4565 return (IGB_FAILURE);
4566 4566 }
4567 4567
4568 4568 /*
4569 4569 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type
4570 4570 *
4571 4571 * Before adding the interrupt handlers, the interrupt vectors have
4572 4572 * been allocated, and the rx/tx rings have also been allocated.
4573 4573 */
4574 4574 static int
4575 4575 igb_add_intr_handlers(igb_t *igb)
4576 4576 {
4577 4577 igb_rx_ring_t *rx_ring;
4578 4578 igb_tx_ring_t *tx_ring;
4579 4579 int vector;
4580 4580 int rc;
4581 4581 int i;
4582 4582
4583 4583 vector = 0;
4584 4584
4585 4585 switch (igb->intr_type) {
4586 4586 case DDI_INTR_TYPE_MSIX:
4587 4587 /* Add interrupt handler for tx + other */
4588 4588 tx_ring = &igb->tx_rings[0];
4589 4589 rc = ddi_intr_add_handler(igb->htable[vector],
4590 4590 (ddi_intr_handler_t *)igb_intr_tx_other,
4591 4591 (void *)igb, NULL);
4592 4592
4593 4593 if (rc != DDI_SUCCESS) {
4594 4594 igb_log(igb, IGB_LOG_INFO,
4595 4595 "Add tx/other interrupt handler failed: %d", rc);
4596 4596 return (IGB_FAILURE);
4597 4597 }
4598 4598 tx_ring->intr_vector = vector;
4599 4599 vector++;
4600 4600
4601 4601 /* Add interrupt handler for each rx ring */
4602 4602 for (i = 0; i < igb->num_rx_rings; i++) {
4603 4603 rx_ring = &igb->rx_rings[i];
4604 4604
4605 4605 rc = ddi_intr_add_handler(igb->htable[vector],
4606 4606 (ddi_intr_handler_t *)igb_intr_rx,
4607 4607 (void *)rx_ring, NULL);
4608 4608
4609 4609 if (rc != DDI_SUCCESS) {
4610 4610 igb_log(igb, IGB_LOG_INFO,
4611 4611 "Add rx interrupt handler failed. "
4612 4612 "return: %d, rx ring: %d", rc, i);
4613 4613 for (vector--; vector >= 0; vector--) {
4614 4614 (void) ddi_intr_remove_handler(
4615 4615 igb->htable[vector]);
4616 4616 }
4617 4617 return (IGB_FAILURE);
4618 4618 }
4619 4619
4620 4620 rx_ring->intr_vector = vector;
4621 4621
4622 4622 vector++;
4623 4623 }
4624 4624
4625 4625 /* Add interrupt handler for each tx ring from 2nd ring */
4626 4626 for (i = 1; i < igb->num_tx_rings; i++) {
4627 4627 tx_ring = &igb->tx_rings[i];
4628 4628
4629 4629 rc = ddi_intr_add_handler(igb->htable[vector],
4630 4630 (ddi_intr_handler_t *)igb_intr_tx,
4631 4631 (void *)tx_ring, NULL);
4632 4632
4633 4633 if (rc != DDI_SUCCESS) {
4634 4634 igb_log(igb, IGB_LOG_INFO,
4635 4635 "Add tx interrupt handler failed. "
4636 4636 "return: %d, tx ring: %d", rc, i);
4637 4637 for (vector--; vector >= 0; vector--) {
4638 4638 (void) ddi_intr_remove_handler(
4639 4639 igb->htable[vector]);
4640 4640 }
4641 4641 return (IGB_FAILURE);
4642 4642 }
4643 4643
4644 4644 tx_ring->intr_vector = vector;
4645 4645
4646 4646 vector++;
4647 4647 }
4648 4648
4649 4649 break;
4650 4650
4651 4651 case DDI_INTR_TYPE_MSI:
4652 4652 /* Add interrupt handlers for the only vector */
4653 4653 rc = ddi_intr_add_handler(igb->htable[vector],
4654 4654 (ddi_intr_handler_t *)igb_intr_msi,
4655 4655 (void *)igb, NULL);
4656 4656
4657 4657 if (rc != DDI_SUCCESS) {
4658 4658 igb_log(igb, IGB_LOG_INFO,
4659 4659 "Add MSI interrupt handler failed: %d", rc);
4660 4660 return (IGB_FAILURE);
4661 4661 }
4662 4662
4663 4663 rx_ring = &igb->rx_rings[0];
4664 4664 rx_ring->intr_vector = vector;
4665 4665
4666 4666 vector++;
4667 4667 break;
4668 4668
4669 4669 case DDI_INTR_TYPE_FIXED:
4670 4670 /* Add interrupt handlers for the only vector */
4671 4671 rc = ddi_intr_add_handler(igb->htable[vector],
4672 4672 (ddi_intr_handler_t *)igb_intr_legacy,
4673 4673 (void *)igb, NULL);
4674 4674
4675 4675 if (rc != DDI_SUCCESS) {
4676 4676 igb_log(igb, IGB_LOG_INFO,
4677 4677 "Add legacy interrupt handler failed: %d", rc);
4678 4678 return (IGB_FAILURE);
4679 4679 }
4680 4680
4681 4681 rx_ring = &igb->rx_rings[0];
4682 4682 rx_ring->intr_vector = vector;
4683 4683
4684 4684 vector++;
4685 4685 break;
4686 4686
4687 4687 default:
4688 4688 return (IGB_FAILURE);
4689 4689 }
4690 4690
4691 4691 ASSERT(vector == igb->intr_cnt);
4692 4692
4693 4693 return (IGB_SUCCESS);
4694 4694 }
4695 4695
4696 4696 /*
4697 4697 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts
4698 4698 *
4699 4699 * For each vector enabled on the adapter, Set the MSIXBM register accordingly
4700 4700 */
4701 4701 static void
4702 4702 igb_setup_msix_82575(igb_t *igb)
4703 4703 {
4704 4704 uint32_t eims = 0;
4705 4705 int i, vector;
4706 4706 struct e1000_hw *hw = &igb->hw;
4707 4707
4708 4708 /*
4709 4709 * Set vector for tx ring 0 and other causes.
4710 4710 * NOTE assumption that it is vector 0.
4711 4711 */
4712 4712 vector = 0;
4713 4713
4714 4714 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER;
4715 4715 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask);
4716 4716 vector++;
4717 4717
4718 4718 for (i = 0; i < igb->num_rx_rings; i++) {
4719 4719 /*
4720 4720 * Set vector for each rx ring
4721 4721 */
4722 4722 eims = (E1000_EICR_RX_QUEUE0 << i);
4723 4723 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
4724 4724
4725 4725 /*
4726 4726 * Accumulate bits to enable in
4727 4727 * igb_enable_adapter_interrupts_82575()
4728 4728 */
4729 4729 igb->eims_mask |= eims;
4730 4730
4731 4731 vector++;
4732 4732 }
4733 4733
4734 4734 for (i = 1; i < igb->num_tx_rings; i++) {
4735 4735 /*
4736 4736 * Set vector for each tx ring from 2nd tx ring
4737 4737 */
4738 4738 eims = (E1000_EICR_TX_QUEUE0 << i);
4739 4739 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
4740 4740
4741 4741 /*
4742 4742 * Accumulate bits to enable in
4743 4743 * igb_enable_adapter_interrupts_82575()
4744 4744 */
4745 4745 igb->eims_mask |= eims;
4746 4746
4747 4747 vector++;
4748 4748 }
4749 4749
4750 4750 ASSERT(vector == igb->intr_cnt);
4751 4751
4752 4752 /*
4753 4753 * Disable IAM for ICR interrupt bits
4754 4754 */
4755 4755 E1000_WRITE_REG(hw, E1000_IAM, 0);
4756 4756 E1000_WRITE_FLUSH(hw);
4757 4757 }
4758 4758
4759 4759 /*
4760 4760 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts
4761 4761 *
4762 4762 * 82576 uses a table based method for assigning vectors. Each queue has a
4763 4763 * single entry in the table to which we write a vector number along with a
4764 4764 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors
4765 4765 * take a different position in the 4-byte register depending on whether
4766 4766 * they are numbered above or below 8.
4767 4767 */
4768 4768 static void
4769 4769 igb_setup_msix_82576(igb_t *igb)
4770 4770 {
4771 4771 struct e1000_hw *hw = &igb->hw;
4772 4772 uint32_t ivar, index, vector;
4773 4773 int i;
4774 4774
4775 4775 /* must enable msi-x capability before IVAR settings */
4776 4776 E1000_WRITE_REG(hw, E1000_GPIE,
4777 4777 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR));
4778 4778
4779 4779 /*
4780 4780 * Set vector for tx ring 0 and other causes.
4781 4781 * NOTE assumption that it is vector 0.
4782 4782 * This is also interdependent with installation of interrupt service
4783 4783 * routines in igb_add_intr_handlers().
4784 4784 */
4785 4785
4786 4786 /* assign "other" causes to vector 0 */
4787 4787 vector = 0;
4788 4788 ivar = ((vector | E1000_IVAR_VALID) << 8);
4789 4789 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4790 4790
4791 4791 /* assign tx ring 0 to vector 0 */
4792 4792 ivar = ((vector | E1000_IVAR_VALID) << 8);
4793 4793 E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
4794 4794
4795 4795 /* prepare to enable tx & other interrupt causes */
4796 4796 igb->eims_mask = (1 << vector);
4797 4797
4798 4798 vector ++;
4799 4799 for (i = 0; i < igb->num_rx_rings; i++) {
4800 4800 /*
4801 4801 * Set vector for each rx ring
4802 4802 */
4803 4803 index = (i & 0x7);
4804 4804 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4805 4805
4806 4806 if (i < 8) {
4807 4807 /* vector goes into low byte of register */
4808 4808 ivar = ivar & 0xFFFFFF00;
4809 4809 ivar |= (vector | E1000_IVAR_VALID);
4810 4810 } else {
4811 4811 /* vector goes into third byte of register */
4812 4812 ivar = ivar & 0xFF00FFFF;
4813 4813 ivar |= ((vector | E1000_IVAR_VALID) << 16);
4814 4814 }
4815 4815 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4816 4816
4817 4817 /* Accumulate interrupt-cause bits to enable */
4818 4818 igb->eims_mask |= (1 << vector);
4819 4819
4820 4820 vector ++;
4821 4821 }
4822 4822
4823 4823 for (i = 1; i < igb->num_tx_rings; i++) {
4824 4824 /*
4825 4825 * Set vector for each tx ring from 2nd tx ring.
4826 4826 * Note assumption that tx vectors numericall follow rx vectors.
4827 4827 */
4828 4828 index = (i & 0x7);
4829 4829 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4830 4830
4831 4831 if (i < 8) {
4832 4832 /* vector goes into second byte of register */
4833 4833 ivar = ivar & 0xFFFF00FF;
4834 4834 ivar |= ((vector | E1000_IVAR_VALID) << 8);
4835 4835 } else {
4836 4836 /* vector goes into fourth byte of register */
4837 4837 ivar = ivar & 0x00FFFFFF;
4838 4838 ivar |= (vector | E1000_IVAR_VALID) << 24;
4839 4839 }
4840 4840 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4841 4841
4842 4842 /* Accumulate interrupt-cause bits to enable */
4843 4843 igb->eims_mask |= (1 << vector);
4844 4844
4845 4845 vector ++;
4846 4846 }
4847 4847
4848 4848 ASSERT(vector == igb->intr_cnt);
4849 4849 }
4850 4850
4851 4851 /*
4852 4852 * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts
4853 4853 *
4854 4854 * 82580 uses same table approach at 82576 but has fewer entries. Each
4855 4855 * queue has a single entry in the table to which we write a vector number
4856 4856 * along with a "valid" bit. Vectors take a different position in the
4857 4857 * register depending on * whether * they are numbered above or below 4.
4858 4858 */
4859 4859 static void
4860 4860 igb_setup_msix_82580(igb_t *igb)
4861 4861 {
4862 4862 struct e1000_hw *hw = &igb->hw;
4863 4863 uint32_t ivar, index, vector;
4864 4864 int i;
4865 4865
4866 4866 /* must enable msi-x capability before IVAR settings */
4867 4867 E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE |
4868 4868 E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME));
4869 4869 /*
4870 4870 * Set vector for tx ring 0 and other causes.
4871 4871 * NOTE assumption that it is vector 0.
4872 4872 * This is also interdependent with installation of interrupt service
4873 4873 * routines in igb_add_intr_handlers().
4874 4874 */
4875 4875
4876 4876 /* assign "other" causes to vector 0 */
4877 4877 vector = 0;
4878 4878 ivar = ((vector | E1000_IVAR_VALID) << 8);
4879 4879 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4880 4880
4881 4881 /* assign tx ring 0 to vector 0 */
4882 4882 ivar = ((vector | E1000_IVAR_VALID) << 8);
4883 4883 E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
4884 4884
4885 4885 /* prepare to enable tx & other interrupt causes */
4886 4886 igb->eims_mask = (1 << vector);
4887 4887
4888 4888 vector ++;
4889 4889
4890 4890 for (i = 0; i < igb->num_rx_rings; i++) {
4891 4891 /*
4892 4892 * Set vector for each rx ring
4893 4893 */
4894 4894 index = (i >> 1);
4895 4895 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4896 4896
4897 4897 if (i & 1) {
4898 4898 /* vector goes into third byte of register */
4899 4899 ivar = ivar & 0xFF00FFFF;
4900 4900 ivar |= ((vector | E1000_IVAR_VALID) << 16);
4901 4901 } else {
4902 4902 /* vector goes into low byte of register */
4903 4903 ivar = ivar & 0xFFFFFF00;
4904 4904 ivar |= (vector | E1000_IVAR_VALID);
4905 4905 }
4906 4906 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4907 4907
4908 4908 /* Accumulate interrupt-cause bits to enable */
4909 4909 igb->eims_mask |= (1 << vector);
4910 4910
4911 4911 vector ++;
4912 4912 }
4913 4913
4914 4914 for (i = 1; i < igb->num_tx_rings; i++) {
4915 4915 /*
4916 4916 * Set vector for each tx ring from 2nd tx ring.
4917 4917 * Note assumption that tx vectors numericall follow rx vectors.
4918 4918 */
4919 4919 index = (i >> 1);
4920 4920 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4921 4921
4922 4922 if (i & 1) {
4923 4923 /* vector goes into high byte of register */
4924 4924 ivar = ivar & 0x00FFFFFF;
4925 4925 ivar |= ((vector | E1000_IVAR_VALID) << 24);
4926 4926 } else {
4927 4927 /* vector goes into second byte of register */
4928 4928 ivar = ivar & 0xFFFF00FF;
4929 4929 ivar |= (vector | E1000_IVAR_VALID) << 8;
4930 4930 }
4931 4931 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4932 4932
4933 4933 /* Accumulate interrupt-cause bits to enable */
4934 4934 igb->eims_mask |= (1 << vector);
4935 4935
4936 4936 vector ++;
4937 4937 }
4938 4938 ASSERT(vector == igb->intr_cnt);
4939 4939 }
4940 4940
4941 4941 /*
4942 4942 * igb_rem_intr_handlers - remove the interrupt handlers
4943 4943 */
4944 4944 static void
4945 4945 igb_rem_intr_handlers(igb_t *igb)
4946 4946 {
4947 4947 int i;
4948 4948 int rc;
4949 4949
4950 4950 for (i = 0; i < igb->intr_cnt; i++) {
4951 4951 rc = ddi_intr_remove_handler(igb->htable[i]);
4952 4952 if (rc != DDI_SUCCESS) {
4953 4953 igb_log(igb, IGB_LOG_INFO,
4954 4954 "Remove intr handler failed: %d", rc);
4955 4955 }
4956 4956 }
4957 4957 }
4958 4958
4959 4959 /*
4960 4960 * igb_rem_intrs - remove the allocated interrupts
4961 4961 */
4962 4962 static void
4963 4963 igb_rem_intrs(igb_t *igb)
4964 4964 {
4965 4965 int i;
4966 4966 int rc;
4967 4967
4968 4968 for (i = 0; i < igb->intr_cnt; i++) {
4969 4969 rc = ddi_intr_free(igb->htable[i]);
4970 4970 if (rc != DDI_SUCCESS) {
4971 4971 igb_log(igb, IGB_LOG_INFO,
4972 4972 "Free intr failed: %d", rc);
4973 4973 }
4974 4974 }
4975 4975
4976 4976 kmem_free(igb->htable, igb->intr_size);
4977 4977 igb->htable = NULL;
4978 4978 }
4979 4979
4980 4980 /*
4981 4981 * igb_enable_intrs - enable all the ddi interrupts
4982 4982 */
4983 4983 static int
4984 4984 igb_enable_intrs(igb_t *igb)
4985 4985 {
4986 4986 int i;
4987 4987 int rc;
4988 4988
4989 4989 /* Enable interrupts */
4990 4990 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
4991 4991 /* Call ddi_intr_block_enable() for MSI */
4992 4992 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt);
4993 4993 if (rc != DDI_SUCCESS) {
4994 4994 igb_log(igb, IGB_LOG_ERROR,
4995 4995 "Enable block intr failed: %d", rc);
4996 4996 return (IGB_FAILURE);
4997 4997 }
4998 4998 } else {
4999 4999 /* Call ddi_intr_enable() for Legacy/MSI non block enable */
5000 5000 for (i = 0; i < igb->intr_cnt; i++) {
5001 5001 rc = ddi_intr_enable(igb->htable[i]);
5002 5002 if (rc != DDI_SUCCESS) {
5003 5003 igb_log(igb, IGB_LOG_ERROR,
5004 5004 "Enable intr failed: %d", rc);
5005 5005 return (IGB_FAILURE);
5006 5006 }
5007 5007 }
5008 5008 }
5009 5009
5010 5010 return (IGB_SUCCESS);
5011 5011 }
5012 5012
5013 5013 /*
5014 5014 * igb_disable_intrs - disable all the ddi interrupts
5015 5015 */
5016 5016 static int
5017 5017 igb_disable_intrs(igb_t *igb)
5018 5018 {
5019 5019 int i;
5020 5020 int rc;
5021 5021
5022 5022 /* Disable all interrupts */
5023 5023 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
5024 5024 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt);
5025 5025 if (rc != DDI_SUCCESS) {
5026 5026 igb_log(igb, IGB_LOG_ERROR,
5027 5027 "Disable block intr failed: %d", rc);
5028 5028 return (IGB_FAILURE);
5029 5029 }
5030 5030 } else {
5031 5031 for (i = 0; i < igb->intr_cnt; i++) {
5032 5032 rc = ddi_intr_disable(igb->htable[i]);
5033 5033 if (rc != DDI_SUCCESS) {
5034 5034 igb_log(igb, IGB_LOG_ERROR,
5035 5035 "Disable intr failed: %d", rc);
5036 5036 return (IGB_FAILURE);
5037 5037 }
5038 5038 }
5039 5039 }
5040 5040
5041 5041 return (IGB_SUCCESS);
5042 5042 }
5043 5043
5044 5044 /*
5045 5045 * igb_get_phy_state - Get and save the parameters read from PHY registers
5046 5046 */
5047 5047 static void
5048 5048 igb_get_phy_state(igb_t *igb)
5049 5049 {
5050 5050 struct e1000_hw *hw = &igb->hw;
5051 5051 uint16_t phy_ctrl;
5052 5052 uint16_t phy_status;
5053 5053 uint16_t phy_an_adv;
5054 5054 uint16_t phy_an_exp;
5055 5055 uint16_t phy_ext_status;
5056 5056 uint16_t phy_1000t_ctrl;
5057 5057 uint16_t phy_1000t_status;
5058 5058 uint16_t phy_lp_able;
5059 5059
5060 5060 ASSERT(mutex_owned(&igb->gen_lock));
5061 5061
5062 5062 if (hw->phy.media_type == e1000_media_type_copper) {
5063 5063 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
5064 5064 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
5065 5065 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv);
5066 5066 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp);
5067 5067 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status);
5068 5068 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl);
5069 5069 (void) e1000_read_phy_reg(hw,
5070 5070 PHY_1000T_STATUS, &phy_1000t_status);
5071 5071 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able);
5072 5072
5073 5073 igb->param_autoneg_cap =
5074 5074 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0;
5075 5075 igb->param_pause_cap =
5076 5076 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
5077 5077 igb->param_asym_pause_cap =
5078 5078 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
5079 5079 igb->param_1000fdx_cap =
5080 5080 ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
5081 5081 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0;
5082 5082 igb->param_1000hdx_cap =
5083 5083 ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) ||
5084 5084 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0;
5085 5085 igb->param_100t4_cap =
5086 5086 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0;
5087 5087 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) ||
5088 5088 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0;
5089 5089 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) ||
5090 5090 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0;
5091 5091 igb->param_10fdx_cap =
5092 5092 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0;
5093 5093 igb->param_10hdx_cap =
5094 5094 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0;
5095 5095 igb->param_rem_fault =
5096 5096 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0;
5097 5097
5098 5098 igb->param_adv_autoneg_cap = hw->mac.autoneg;
5099 5099 igb->param_adv_pause_cap =
5100 5100 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
5101 5101 igb->param_adv_asym_pause_cap =
5102 5102 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
5103 5103 igb->param_adv_1000hdx_cap =
5104 5104 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0;
5105 5105 igb->param_adv_100t4_cap =
5106 5106 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0;
5107 5107 igb->param_adv_rem_fault =
5108 5108 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0;
5109 5109 if (igb->param_adv_autoneg_cap == 1) {
5110 5110 igb->param_adv_1000fdx_cap =
5111 5111 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0;
5112 5112 igb->param_adv_100fdx_cap =
5113 5113 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0;
5114 5114 igb->param_adv_100hdx_cap =
5115 5115 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0;
5116 5116 igb->param_adv_10fdx_cap =
5117 5117 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0;
5118 5118 igb->param_adv_10hdx_cap =
5119 5119 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0;
5120 5120 }
5121 5121
5122 5122 igb->param_lp_autoneg_cap =
5123 5123 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0;
5124 5124 igb->param_lp_pause_cap =
5125 5125 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0;
5126 5126 igb->param_lp_asym_pause_cap =
5127 5127 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0;
5128 5128 igb->param_lp_1000fdx_cap =
5129 5129 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0;
5130 5130 igb->param_lp_1000hdx_cap =
5131 5131 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0;
5132 5132 igb->param_lp_100t4_cap =
5133 5133 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0;
5134 5134 igb->param_lp_100fdx_cap =
5135 5135 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0;
5136 5136 igb->param_lp_100hdx_cap =
5137 5137 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0;
5138 5138 igb->param_lp_10fdx_cap =
5139 5139 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0;
5140 5140 igb->param_lp_10hdx_cap =
5141 5141 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0;
5142 5142 igb->param_lp_rem_fault =
5143 5143 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0;
5144 5144 } else {
5145 5145 /*
5146 5146 * 1Gig Fiber adapter only offers 1Gig Full Duplex.
5147 5147 */
5148 5148 igb->param_autoneg_cap = 0;
5149 5149 igb->param_pause_cap = 1;
5150 5150 igb->param_asym_pause_cap = 1;
5151 5151 igb->param_1000fdx_cap = 1;
5152 5152 igb->param_1000hdx_cap = 0;
5153 5153 igb->param_100t4_cap = 0;
5154 5154 igb->param_100fdx_cap = 0;
5155 5155 igb->param_100hdx_cap = 0;
5156 5156 igb->param_10fdx_cap = 0;
5157 5157 igb->param_10hdx_cap = 0;
5158 5158
5159 5159 igb->param_adv_autoneg_cap = 0;
5160 5160 igb->param_adv_pause_cap = 1;
5161 5161 igb->param_adv_asym_pause_cap = 1;
5162 5162 igb->param_adv_1000fdx_cap = 1;
5163 5163 igb->param_adv_1000hdx_cap = 0;
5164 5164 igb->param_adv_100t4_cap = 0;
5165 5165 igb->param_adv_100fdx_cap = 0;
5166 5166 igb->param_adv_100hdx_cap = 0;
5167 5167 igb->param_adv_10fdx_cap = 0;
5168 5168 igb->param_adv_10hdx_cap = 0;
5169 5169
5170 5170 igb->param_lp_autoneg_cap = 0;
5171 5171 igb->param_lp_pause_cap = 0;
5172 5172 igb->param_lp_asym_pause_cap = 0;
5173 5173 igb->param_lp_1000fdx_cap = 0;
5174 5174 igb->param_lp_1000hdx_cap = 0;
5175 5175 igb->param_lp_100t4_cap = 0;
5176 5176 igb->param_lp_100fdx_cap = 0;
5177 5177 igb->param_lp_100hdx_cap = 0;
5178 5178 igb->param_lp_10fdx_cap = 0;
5179 5179 igb->param_lp_10hdx_cap = 0;
5180 5180 igb->param_lp_rem_fault = 0;
5181 5181 }
5182 5182 }
5183 5183
5184 5184 /*
5185 5185 * synchronize the adv* and en* parameters.
5186 5186 *
5187 5187 * See comments in <sys/dld.h> for details of the *_en_*
5188 5188 * parameters. The usage of ndd for setting adv parameters will
5189 5189 * synchronize all the en parameters with the e1000g parameters,
5190 5190 * implicitly disabling any settings made via dladm.
5191 5191 */
5192 5192 static void
5193 5193 igb_param_sync(igb_t *igb)
5194 5194 {
5195 5195 igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap;
5196 5196 igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap;
5197 5197 igb->param_en_100t4_cap = igb->param_adv_100t4_cap;
5198 5198 igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap;
5199 5199 igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap;
5200 5200 igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap;
5201 5201 igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap;
5202 5202 }
5203 5203
5204 5204 /*
5205 5205 * igb_get_driver_control
5206 5206 */
5207 5207 static void
5208 5208 igb_get_driver_control(struct e1000_hw *hw)
5209 5209 {
5210 5210 uint32_t ctrl_ext;
5211 5211
5212 5212 /* Notify firmware that driver is in control of device */
5213 5213 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5214 5214 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD;
5215 5215 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5216 5216 }
5217 5217
5218 5218 /*
5219 5219 * igb_release_driver_control
5220 5220 */
5221 5221 static void
5222 5222 igb_release_driver_control(struct e1000_hw *hw)
5223 5223 {
5224 5224 uint32_t ctrl_ext;
5225 5225
5226 5226 /* Notify firmware that driver is no longer in control of device */
5227 5227 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5228 5228 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD;
5229 5229 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5230 5230 }
5231 5231
5232 5232 /*
5233 5233 * igb_atomic_reserve - Atomic decrease operation
5234 5234 */
5235 5235 int
5236 5236 igb_atomic_reserve(uint32_t *count_p, uint32_t n)
5237 5237 {
5238 5238 uint32_t oldval;
5239 5239 uint32_t newval;
5240 5240
5241 5241 /* ATOMICALLY */
5242 5242 do {
5243 5243 oldval = *count_p;
5244 5244 if (oldval < n)
5245 5245 return (-1);
5246 5246 newval = oldval - n;
5247 5247 } while (atomic_cas_32(count_p, oldval, newval) != oldval);
5248 5248
5249 5249 return (newval);
5250 5250 }
5251 5251
5252 5252 /*
5253 5253 * FMA support
5254 5254 */
5255 5255
5256 5256 int
5257 5257 igb_check_acc_handle(ddi_acc_handle_t handle)
5258 5258 {
5259 5259 ddi_fm_error_t de;
5260 5260
5261 5261 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
5262 5262 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
5263 5263 return (de.fme_status);
5264 5264 }
5265 5265
5266 5266 int
5267 5267 igb_check_dma_handle(ddi_dma_handle_t handle)
5268 5268 {
5269 5269 ddi_fm_error_t de;
5270 5270
5271 5271 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
5272 5272 return (de.fme_status);
5273 5273 }
5274 5274
5275 5275 /*
5276 5276 * The IO fault service error handling callback function
5277 5277 */
5278 5278 /*ARGSUSED*/
5279 5279 static int
5280 5280 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
5281 5281 {
5282 5282 /*
5283 5283 * as the driver can always deal with an error in any dma or
5284 5284 * access handle, we can just return the fme_status value.
5285 5285 */
5286 5286 pci_ereport_post(dip, err, NULL);
5287 5287 return (err->fme_status);
5288 5288 }
5289 5289
5290 5290 static void
5291 5291 igb_fm_init(igb_t *igb)
5292 5292 {
5293 5293 ddi_iblock_cookie_t iblk;
5294 5294 int fma_dma_flag;
5295 5295
5296 5296 /* Only register with IO Fault Services if we have some capability */
5297 5297 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
5298 5298 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
5299 5299 } else {
5300 5300 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
5301 5301 }
5302 5302
5303 5303 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
5304 5304 fma_dma_flag = 1;
5305 5305 } else {
5306 5306 fma_dma_flag = 0;
5307 5307 }
5308 5308
5309 5309 (void) igb_set_fma_flags(fma_dma_flag);
5310 5310
5311 5311 if (igb->fm_capabilities) {
5312 5312
5313 5313 /* Register capabilities with IO Fault Services */
5314 5314 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk);
5315 5315
5316 5316 /*
5317 5317 * Initialize pci ereport capabilities if ereport capable
5318 5318 */
5319 5319 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
5320 5320 DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5321 5321 pci_ereport_setup(igb->dip);
5322 5322
5323 5323 /*
5324 5324 * Register error callback if error callback capable
5325 5325 */
5326 5326 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5327 5327 ddi_fm_handler_register(igb->dip,
5328 5328 igb_fm_error_cb, (void*) igb);
5329 5329 }
5330 5330 }
5331 5331
5332 5332 static void
5333 5333 igb_fm_fini(igb_t *igb)
5334 5334 {
5335 5335 /* Only unregister FMA capabilities if we registered some */
5336 5336 if (igb->fm_capabilities) {
5337 5337
5338 5338 /*
5339 5339 * Release any resources allocated by pci_ereport_setup()
5340 5340 */
5341 5341 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
5342 5342 DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5343 5343 pci_ereport_teardown(igb->dip);
5344 5344
5345 5345 /*
5346 5346 * Un-register error callback if error callback capable
5347 5347 */
5348 5348 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5349 5349 ddi_fm_handler_unregister(igb->dip);
5350 5350
5351 5351 /* Unregister from IO Fault Services */
5352 5352 ddi_fm_fini(igb->dip);
5353 5353 }
5354 5354 }
5355 5355
5356 5356 void
5357 5357 igb_fm_ereport(igb_t *igb, char *detail)
5358 5358 {
5359 5359 uint64_t ena;
5360 5360 char buf[FM_MAX_CLASS];
5361 5361
5362 5362 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
5363 5363 ena = fm_ena_generate(0, FM_ENA_FMT1);
5364 5364 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) {
5365 5365 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP,
5366 5366 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
5367 5367 }
5368 5368 }
|
↓ open down ↓ |
5174 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX