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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/common/io/audio/drv/audiots/audiots.c
+++ new/usr/src/uts/common/io/audio/drv/audiots/audiots.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26
27 27 /*
28 28 * audiots Audio Driver
29 29 *
30 30 * This Audio Driver controls the T2 audio core in the ALI M1553
31 31 * southbridge chip. This chip supports multiple play streams, but just
32 32 * a single record stream. It also supports wave table synthesis and
33 33 * hardware MIDI and joystick ports. Unfortunately the MIDI ports are
34 34 * not available because their pins have been re-assigned to expose
35 35 * interrupts. We also aren't going to do anything with the joystick
36 36 * ports. The audio core controls an AC-97 V2.1 Codec.
37 37 *
38 38 * The DMA engine uses a single buffer which is large enough to hold
39 39 * two interrupts worth of data. When it gets to the mid point an
40 40 * interrupt is generated and data is either sent (for record) or
41 41 * requested and put in that half of the buffer (for play). When the
42 42 * second half is played we do the same, but the audio core loops the
43 43 * pointer back to the beginning.
44 44 *
45 45 * The audio core has a bug in silicon that doesn't let it read the AC-97
46 46 * Codec's register. T2 has provided an algorithm that attempts to read the
47 47 * the Codec several times. This is probably heuristic and thus isn't
48 48 * absolutely guaranteed to work. However we do have to place a limit on
49 49 * the looping, otherwise when we read a valid 0x00 we would never exit
50 50 * the loop. Unfortunately there is also a problem with writing the AC-97
51 51 * Codec's registers as well. Thus we read it back to verify the write.
52 52 *
53 53 * The AC'97 common code provides shadow state for AC'97 registers for us,
54 54 * so we only need to read those registers during early startup (primarily
55 55 * to determine codec id and capabilities.)
56 56 *
57 57 * We don't save any of the audio controller registers during normal
58 58 * operation. When we need to save register state we only have to save
59 59 * the aram and eram. The rest of the controller state is never modified
60 60 * from the initial programming. Thus restoring the controller state
61 61 * can be done from audiots_chip_init() as well.
62 62 *
63 63 *
64 64 * WARNING: The SME birdsnest platform uses a PCI bridge chip between the
65 65 * CPU and the southbridge containing the audio core. There is
66 66 * a bug in silicon that causes a bogus parity error. With the mixer
67 67 * reimplementation project, Bug 4374774, the audio driver is always
68 68 * set to the best precision and number of channels. Thus when turning
69 69 * the mixer on and off the only thing that changes is the sample rate.
70 70 * This change in programming doesn't trigger the silicon error.
71 71 * Thus the supported channels must always be 2 and the precision
72 72 * must always be 16-bits. This will keep any future change in the
73 73 * mixer from exposing this bug.
74 74 *
75 75 * Due to a hardware bug, system power management is not supported by this
76 76 * driver.
77 77 *
78 78 * CAUTION: If audio controller state is changed outside of aram
79 79 * and eram then that information must be saved and restored
80 80 * during power management shutdown and bringup.
81 81 *
82 82 * NOTE: The AC-97 Codec's reset pin is set to PCI reset, so we
83 83 * can't power down the Codec all the way.
84 84 *
85 85 * NOTE: This driver depends on the drv/audio and misc/ac97
86 86 * modules being loaded first.
87 87 *
88 88 * NOTE: Don't OR the ap_stop register to stop a play or record. This
89 89 * will just stop all active channels because a read of ap_stop
90 90 * returns ap_start. Just set the ap_stop register with the
91 91 * channels you want to stop. The same goes for ap_start.
92 92 *
93 93 * NOTE: There is a hardware problem with P2 rev motherboards. After
94 94 * prolonged use, reading the AC97 register will always return
95 95 * busy. The AC97 register is now useless. Consequently, we are no
96 96 * longer able to program the Codec. This work around disables
97 97 * audio when this state is detected. It's not great, but its
98 98 * better than having audio blasting out at 100% all the time.
99 99 *
100 100 * NOTE: Power Management testing has also exposed this AC97 timeout
101 101 * problem. Management has decided this is too risky for customers
102 102 * and hence they want power management support removed from the
103 103 * audio subsystem. All PM support is now removed.
104 104 */
105 105
106 106 /*
107 107 * Synchronization notes:
108 108 *
109 109 * The audio framework guarantees that our entry points are exclusive
110 110 * with suspend and resume. This includes data flow and control entry
111 111 * points alike.
112 112 *
113 113 * The audio framework guarantees that only one control is being
114 114 * accessed on any given audio device at a time.
115 115 *
116 116 * The audio framework guarantees that entry points are themselves
117 117 * serialized for a given engine.
118 118 *
119 119 * We have no interrupt routine or other internal asynchronous routines.
120 120 *
121 121 * Our device uses completely separate registers for each engine,
122 122 * except for the start/stop registers, which are implemented in a
123 123 * manner that allows for them to be accessed concurrently safely from
124 124 * different threads.
125 125 *
126 126 * Hence, it turns out that we simply don't need any locking in this
127 127 * driver.
128 128 */
129 129
130 130 #include <sys/modctl.h>
131 131 #include <sys/kmem.h>
132 132 #include <sys/pci.h>
133 133 #include <sys/ddi.h>
134 134 #include <sys/sunddi.h>
135 135 #include <sys/debug.h>
136 136 #include <sys/note.h>
137 137 #include <sys/audio/audio_driver.h>
138 138 #include <sys/audio/ac97.h>
139 139 #include "audiots.h"
140 140
141 141 /*
142 142 * Module linkage routines for the kernel
143 143 */
144 144 static int audiots_attach(dev_info_t *, ddi_attach_cmd_t);
145 145 static int audiots_detach(dev_info_t *, ddi_detach_cmd_t);
146 146 static int audiots_quiesce(dev_info_t *);
147 147
148 148 /*
149 149 * Entry point routine prototypes
150 150 */
151 151 static int audiots_open(void *, int, unsigned *, caddr_t *);
152 152 static void audiots_close(void *);
153 153 static int audiots_start(void *);
154 154 static void audiots_stop(void *);
155 155 static int audiots_format(void *);
156 156 static int audiots_channels(void *);
157 157 static int audiots_rate(void *);
158 158 static void audiots_chinfo(void *, int, unsigned *, unsigned *);
159 159 static uint64_t audiots_count(void *);
160 160 static void audiots_sync(void *, unsigned);
161 161
162 162 static audio_engine_ops_t audiots_engine_ops = {
163 163 AUDIO_ENGINE_VERSION,
164 164 audiots_open,
165 165 audiots_close,
166 166 audiots_start,
167 167 audiots_stop,
168 168 audiots_count,
169 169 audiots_format,
170 170 audiots_channels,
171 171 audiots_rate,
172 172 audiots_sync,
173 173 NULL,
174 174 audiots_chinfo,
175 175 NULL,
176 176 };
177 177
178 178 /*
179 179 * Local Routine Prototypes
180 180 */
181 181 static void audiots_power_up(audiots_state_t *);
182 182 static void audiots_chip_init(audiots_state_t *);
183 183 static uint16_t audiots_get_ac97(void *, uint8_t);
184 184 static void audiots_set_ac97(void *, uint8_t, uint16_t);
185 185 static int audiots_init_state(audiots_state_t *, dev_info_t *);
186 186 static int audiots_map_regs(dev_info_t *, audiots_state_t *);
187 187 static uint16_t audiots_read_ac97(audiots_state_t *, int);
188 188 static void audiots_stop_everything(audiots_state_t *);
189 189 static void audiots_destroy(audiots_state_t *);
190 190 static int audiots_alloc_port(audiots_state_t *, int);
191 191
192 192 /*
193 193 * Global variables, but viewable only by this file.
194 194 */
195 195
196 196 /* anchor for soft state structures */
197 197 static void *audiots_statep;
198 198
199 199 /*
200 200 * DDI Structures
201 201 */
202 202
203 203 /* Device operations structure */
204 204 static struct dev_ops audiots_dev_ops = {
205 205 DEVO_REV, /* devo_rev */
206 206 0, /* devo_refcnt */
207 207 NULL, /* devo_getinfo */
208 208 nulldev, /* devo_identify - obsolete */
209 209 nulldev, /* devo_probe */
210 210 audiots_attach, /* devo_attach */
211 211 audiots_detach, /* devo_detach */
212 212 nodev, /* devo_reset */
213 213 NULL, /* devo_cb_ops */
214 214 NULL, /* devo_bus_ops */
215 215 NULL, /* devo_power */
216 216 audiots_quiesce, /* devo_quiesce */
217 217 };
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218 218
219 219 /* Linkage structure for loadable drivers */
220 220 static struct modldrv audiots_modldrv = {
221 221 &mod_driverops, /* drv_modops */
222 222 TS_MOD_NAME, /* drv_linkinfo */
223 223 &audiots_dev_ops /* drv_dev_ops */
224 224 };
225 225
226 226 /* Module linkage structure */
227 227 static struct modlinkage audiots_modlinkage = {
228 - MODREV_1, /* ml_rev */
229 - (void *)&audiots_modldrv, /* ml_linkage */
230 - NULL /* NULL terminates the list */
228 + MODREV_1, /* ml_rev */
229 + { (void *)&audiots_modldrv, NULL } /* ml_linkage */
231 230 };
232 231
233 232
234 233 /*
235 234 * NOTE: Grover OBP v4.0.166 and rev G of the ALI Southbridge chip force the
236 235 * audiots driver to use the upper 2 GB DMA address range. However to maintain
237 236 * backwards compatibility with older systems/OBP, we're going to try the full
238 237 * 4 GB DMA range.
239 238 *
240 239 * Eventually, this will be set back to using the proper high 2 GB DMA range.
241 240 */
242 241
243 242 /* Device attribute structure - full 4 gig address range */
244 243 static ddi_dma_attr_t audiots_attr = {
245 244 DMA_ATTR_VERSION, /* version */
246 245 0x0000000000000000LL, /* dlim_addr_lo */
247 246 0x00000000ffffffffLL, /* dlim_addr_hi */
248 247 0x0000000000003fffLL, /* DMA counter register - 16 bits */
249 248 0x0000000000000008LL, /* DMA address alignment, 64-bit */
250 249 0x0000007f, /* 1 through 64 byte burst sizes */
251 250 0x00000001, /* min effective DMA size */
252 251 0x0000000000003fffLL, /* maximum transfer size, 16k */
253 252 0x000000000000ffffLL, /* segment boundary, 64k */
254 253 0x00000001, /* s/g list length, no s/g */
255 254 0x00000001, /* granularity of device, don't care */
256 255 0 /* DMA flags */
257 256 };
258 257
259 258 static ddi_device_acc_attr_t ts_acc_attr = {
260 259 DDI_DEVICE_ATTR_V0,
261 260 DDI_NEVERSWAP_ACC,
262 261 DDI_STRICTORDER_ACC
263 262 };
264 263
265 264 static ddi_device_acc_attr_t ts_regs_attr = {
266 265 DDI_DEVICE_ATTR_V0,
267 266 DDI_STRUCTURE_LE_ACC,
268 267 DDI_STRICTORDER_ACC
269 268 };
270 269
271 270 /*
272 271 * _init()
273 272 *
274 273 * Description:
275 274 * Driver initialization, called when driver is first loaded.
276 275 * This is how access is initially given to all the static structures.
277 276 *
278 277 * Arguments:
279 278 * None
280 279 *
281 280 * Returns:
282 281 * ddi_soft_state_init() status, see ddi_soft_state_init(9f), or
283 282 * mod_install() status, see mod_install(9f)
284 283 */
285 284 int
286 285 _init(void)
287 286 {
288 287 int error;
289 288
290 289 audio_init_ops(&audiots_dev_ops, TS_NAME);
291 290
292 291 /* initialize the soft state */
293 292 if ((error = ddi_soft_state_init(&audiots_statep,
294 293 sizeof (audiots_state_t), 1)) != 0) {
295 294 audio_fini_ops(&audiots_dev_ops);
296 295 return (error);
297 296 }
298 297
299 298 if ((error = mod_install(&audiots_modlinkage)) != 0) {
300 299 audio_fini_ops(&audiots_dev_ops);
301 300 ddi_soft_state_fini(&audiots_statep);
302 301 }
303 302
304 303 return (error);
305 304 }
306 305
307 306 /*
308 307 * _fini()
309 308 *
310 309 * Description:
311 310 * Module de-initialization, called when the driver is to be unloaded.
312 311 *
313 312 * Arguments:
314 313 * None
315 314 *
316 315 * Returns:
317 316 * mod_remove() status, see mod_remove(9f)
318 317 */
319 318 int
320 319 _fini(void)
321 320 {
322 321 int error;
323 322
324 323 if ((error = mod_remove(&audiots_modlinkage)) != 0) {
325 324 return (error);
326 325 }
327 326
328 327 /* free the soft state internal structures */
329 328 ddi_soft_state_fini(&audiots_statep);
330 329
331 330 /* clean up ops */
332 331 audio_fini_ops(&audiots_dev_ops);
333 332
334 333 return (0);
335 334 }
336 335
337 336 /*
338 337 * _info()
339 338 *
340 339 * Description:
341 340 * Module information, returns infomation about the driver.
342 341 *
343 342 * Arguments:
344 343 * modinfo *modinfop Pointer to the opaque modinfo structure
345 344 *
346 345 * Returns:
347 346 * mod_info() status, see mod_info(9f)
348 347 */
349 348 int
350 349 _info(struct modinfo *modinfop)
351 350 {
352 351 int error;
353 352
354 353 error = mod_info(&audiots_modlinkage, modinfop);
355 354
356 355 return (error);
357 356 }
358 357
359 358
360 359 /*
361 360 * audiots_attach()
362 361 *
363 362 * Description:
364 363 * Attach an instance of the audiots driver. This routine does the
365 364 * device dependent attach tasks.
366 365 *
367 366 * Arguments:
368 367 * dev_info_t *dip Pointer to the device's dev_info struct
369 368 * ddi_attach_cmd_t cmd Attach command
370 369 *
371 370 * Returns:
372 371 * DDI_SUCCESS The driver was initialized properly
373 372 * DDI_FAILURE The driver couldn't be initialized properly
374 373 */
375 374 static int
376 375 audiots_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
377 376 {
378 377 audiots_state_t *state;
379 378 int instance;
380 379
381 380 instance = ddi_get_instance(dip);
382 381
383 382 switch (cmd) {
384 383 case DDI_ATTACH:
385 384 break;
386 385 case DDI_RESUME:
387 386
388 387 /* we've already allocated the state structure so get ptr */
389 388 state = ddi_get_soft_state(audiots_statep, instance);
390 389 ASSERT(dip == state->ts_dip);
391 390
392 391 /* suspend/resume resets the chip, so we have no more faults */
393 392 if (state->ts_flags & TS_AUDIO_READ_FAILED) {
394 393 ddi_dev_report_fault(state->ts_dip,
395 394 DDI_SERVICE_RESTORED,
396 395 DDI_DEVICE_FAULT,
397 396 "check port, gain, balance, and mute settings");
398 397 /* and clear the fault state flags */
399 398 state->ts_flags &=
400 399 ~(TS_AUDIO_READ_FAILED|TS_READ_FAILURE_PRINTED);
401 400 }
402 401
403 402 audiots_power_up(state);
404 403 audiots_chip_init(state);
405 404
406 405 ac97_reset(state->ts_ac97);
407 406
408 407 audio_dev_resume(state->ts_adev);
409 408
410 409 return (DDI_SUCCESS);
411 410
412 411 default:
413 412 return (DDI_FAILURE);
414 413 }
415 414
416 415 /* before we do anything make sure that we haven't had a h/w failure */
417 416 if (ddi_get_devstate(dip) == DDI_DEVSTATE_DOWN) {
418 417 cmn_err(CE_WARN, "%s%d: The audio hardware has "
419 418 "been disabled.", ddi_driver_name(dip), instance);
420 419 cmn_err(CE_CONT, "Please reboot to restore audio.");
421 420 return (DDI_FAILURE);
422 421 }
423 422
424 423 /* allocate the state structure */
425 424 if (ddi_soft_state_zalloc(audiots_statep, instance) == DDI_FAILURE) {
426 425 cmn_err(CE_WARN, "!%s%d: soft state allocate failed",
427 426 ddi_driver_name(dip), instance);
428 427 return (DDI_FAILURE);
429 428 }
430 429
431 430 /*
432 431 * WARNING: From here on all errors require that we free memory,
433 432 * including the state structure.
434 433 */
435 434
436 435 /* get the state structure - cannot fail */
437 436 state = ddi_get_soft_state(audiots_statep, instance);
438 437 ASSERT(state != NULL);
439 438
440 439 if ((state->ts_adev = audio_dev_alloc(dip, 0)) == NULL) {
441 440 cmn_err(CE_WARN, "unable to allocate audio dev");
442 441 goto error;
443 442 }
444 443
445 444 /* map in the registers, allocate DMA buffers, etc. */
446 445 if (audiots_map_regs(dip, state) == DDI_FAILURE) {
447 446 audio_dev_warn(state->ts_adev, "unable to map registers");
448 447 goto error;
449 448 }
450 449
451 450 /* initialize the audio state structures */
452 451 if (audiots_init_state(state, dip) == DDI_FAILURE) {
453 452 audio_dev_warn(state->ts_adev, "init state structure failed");
454 453 goto error;
455 454 }
456 455
457 456 /* power up */
458 457 audiots_power_up(state);
459 458
460 459 /* initialize the audio controller */
461 460 audiots_chip_init(state);
462 461
463 462 /* initialize the AC-97 Codec */
464 463 if (ac97_init(state->ts_ac97, state->ts_adev) != 0) {
465 464 goto error;
466 465 }
467 466
468 467 /* put the engine interrupts into a known state -- all off */
469 468 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten,
470 469 TS_ALL_DMA_OFF);
471 470
472 471 /* call the framework attach routine */
473 472 if (audio_dev_register(state->ts_adev) != DDI_SUCCESS) {
474 473 audio_dev_warn(state->ts_adev, "unable to register audio");
475 474 goto error;
476 475 }
477 476
478 477 /* everything worked out, so report the device */
479 478 ddi_report_dev(dip);
480 479
481 480 return (DDI_SUCCESS);
482 481
483 482 error:
484 483 audiots_destroy(state);
485 484 return (DDI_FAILURE);
486 485 }
487 486
488 487 /*
489 488 * audiots_detach()
490 489 *
491 490 * Description:
492 491 * Detach an instance of the audiots driver.
493 492 *
494 493 * Arguments:
495 494 * dev_info_t *dip Pointer to the device's dev_info struct
496 495 * ddi_detach_cmd_t cmd Detach command
497 496 *
498 497 * Returns:
499 498 * DDI_SUCCESS The driver was detached
500 499 * DDI_FAILURE The driver couldn't be detached
501 500 */
502 501 static int
503 502 audiots_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
504 503 {
505 504 audiots_state_t *state;
506 505 int instance;
507 506
508 507 instance = ddi_get_instance(dip);
509 508
510 509 /* get the state structure */
511 510 if ((state = ddi_get_soft_state(audiots_statep, instance)) == NULL) {
512 511 cmn_err(CE_WARN, "!%s%d: detach get soft state failed",
513 512 ddi_driver_name(dip), instance);
514 513 return (DDI_FAILURE);
515 514 }
516 515
517 516 switch (cmd) {
518 517 case DDI_DETACH:
519 518 break;
520 519 case DDI_SUSPEND:
521 520
522 521 audio_dev_suspend(state->ts_adev);
523 522
524 523 /* stop playing and recording */
525 524 (void) audiots_stop_everything(state);
526 525
527 526 return (DDI_SUCCESS);
528 527
529 528 default:
530 529 return (DDI_FAILURE);
531 530 }
532 531
533 532 /* attempt to unregister from the framework first */
534 533 if (audio_dev_unregister(state->ts_adev) != DDI_SUCCESS) {
535 534 return (DDI_FAILURE);
536 535 }
537 536
538 537 audiots_destroy(state);
539 538
540 539 return (DDI_SUCCESS);
541 540
542 541 }
543 542
544 543 /*
545 544 * audiots_quiesce()
546 545 *
547 546 * Description:
548 547 * Quiesce an instance of the audiots driver. Stops all DMA and
549 548 * interrupts.
550 549 *
551 550 * Arguments:
552 551 * dev_info_t *dip Pointer to the device's dev_info struct
553 552 *
554 553 * Returns:
555 554 * DDI_SUCCESS The driver was quiesced
556 555 * DDI_SUCCESS The driver was NOT quiesced
557 556 */
558 557 static int
559 558 audiots_quiesce(dev_info_t *dip)
560 559 {
561 560 audiots_state_t *state;
562 561 int instance;
563 562
564 563 instance = ddi_get_instance(dip);
565 564
566 565 /* get the state structure */
567 566 if ((state = ddi_get_soft_state(audiots_statep, instance)) == NULL) {
568 567 return (DDI_FAILURE);
569 568 }
570 569
571 570 audiots_stop_everything(state);
572 571
573 572 return (DDI_SUCCESS);
574 573 }
575 574
576 575 /*
577 576 * audiots_power_up()
578 577 *
579 578 * Description
580 579 * Ensure that the device is running in PCI power state D0.
581 580 */
582 581 static void
583 582 audiots_power_up(audiots_state_t *state)
584 583 {
585 584 ddi_acc_handle_t pcih = state->ts_pcih;
586 585 uint8_t ptr;
587 586 uint16_t pmcsr;
588 587
589 588 if ((pci_config_get16(pcih, PCI_CONF_STAT) & PCI_STAT_CAP) == 0) {
590 589 /* does not implement PCI capabilities -- no PM */
591 590 return;
592 591 }
593 592
594 593 ptr = pci_config_get8(pcih, PCI_CONF_CAP_PTR);
595 594 for (;;) {
596 595 if (ptr == PCI_CAP_NEXT_PTR_NULL) {
597 596 /* PM capability not found */
598 597 return;
599 598 }
600 599 if (pci_config_get8(pcih, ptr + PCI_CAP_ID) == PCI_CAP_ID_PM) {
601 600 /* found it */
602 601 break;
603 602 }
604 603 ptr = pci_config_get8(pcih, ptr + PCI_CAP_NEXT_PTR);
605 604 }
606 605
607 606 /* if we got here, then got valid PMCSR pointer */
608 607 ptr += PCI_PMCSR;
609 608
610 609 /* check to see if we are already in state D0 */
611 610 pmcsr = pci_config_get16(pcih, ptr);
612 611 if ((pmcsr & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
613 612
614 613 /* D3hot (or any other state) -> D0 */
615 614 pmcsr &= ~PCI_PMCSR_STATE_MASK;
616 615 pmcsr |= PCI_PMCSR_D0;
617 616 pci_config_put16(pcih, ptr, pmcsr);
618 617 }
619 618
620 619 /*
621 620 * Wait for it to power up - PCI spec says 10 ms is enough.
622 621 * We double it. Note that no locks are held when this routine
623 622 * is called, so we can sleep (we are in attach context only).
624 623 *
625 624 * We do this delay even if already powerd up, just to make
626 625 * sure we aren't seeing something that *just* transitioned
627 626 * into D0 state.
628 627 */
629 628 delay(drv_usectohz(TS_20MS));
630 629
631 630 /* clear PME# flag */
632 631 pmcsr = pci_config_get16(pcih, ptr);
633 632 pci_config_put16(pcih, ptr, pmcsr | PCI_PMCSR_PME_STAT);
634 633 }
635 634
636 635 /*
637 636 * audiots_chip_init()
638 637 *
639 638 * Description:
640 639 * Initialize the audio core.
641 640 *
642 641 * Arguments:
643 642 * audiots_state_t *state The device's state structure
644 643 */
645 644 static void
646 645 audiots_chip_init(audiots_state_t *state)
647 646 {
648 647 ddi_acc_handle_t handle = state->ts_acch;
649 648 audiots_regs_t *regs = state->ts_regs;
650 649 int str;
651 650
652 651 /* start with all interrupts & dma channels disabled */
653 652 ddi_put32(handle, ®s->aud_regs.ap_stop, TS_ALL_DMA_ENGINES);
654 653 ddi_put32(handle, ®s->aud_regs.ap_ainten, TS_ALL_DMA_OFF);
655 654
656 655 /* set global music and wave volume to 0dB */
657 656 ddi_put32(handle, ®s->aud_regs.ap_volume, 0x0);
658 657
659 658 /* enable end interrupts for all channels. */
660 659 ddi_put32(handle, ®s->aud_regs.ap_cir_gc, AP_CIR_GC_ENDLP_IE);
661 660
662 661 /* for each stream, set gain and vol settings */
663 662 for (str = 0; str < TS_MAX_HW_CHANNELS; str++) {
664 663 /*
665 664 * Set volume to all off, 1st left and then right.
666 665 * These are never changed, so we don't have to save them.
667 666 */
668 667 ddi_put16(handle,
669 668 ®s->aud_ram[str].eram.eram_gvsel_pan_vol,
670 669 (ERAM_WAVE_VOL|ERAM_PAN_LEFT|ERAM_PAN_0dB|
671 670 ERAM_VOL_MAX_ATTEN));
672 671 ddi_put16(handle,
673 672 ®s->aud_ram[str].eram.eram_gvsel_pan_vol,
674 673 (ERAM_WAVE_VOL|ERAM_PAN_RIGHT|ERAM_PAN_0dB|
675 674 ERAM_VOL_MAX_ATTEN));
676 675
677 676 /*
678 677 * The envelope engine *MUST* remain in still mode (off).
679 678 * Otherwise bad things like gain randomly disappearing might
680 679 * happen. See bug #4332773.
681 680 */
682 681
683 682 ddi_put32(handle, ®s->aud_ram[str].eram.eram_ebuf1,
684 683 ERAM_EBUF_STILL);
685 684 ddi_put32(handle, ®s->aud_ram[str].eram.eram_ebuf2,
686 685 ERAM_EBUF_STILL);
687 686
688 687 /* program the initial eram and aram rate */
689 688 ddi_put16(handle, ®s->aud_ram[str].aram.aram_delta,
690 689 1 << TS_SRC_SHIFT);
691 690 ddi_put16(handle, ®s->aud_ram[str].eram.eram_ctrl_ec,
692 691 ERAM_16_BITS | ERAM_STEREO | ERAM_LOOP_MODE |
693 692 ERAM_SIGNED_PCM);
694 693 }
695 694
696 695 /* program channel 31 for record */
697 696 OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_global_control,
698 697 (AP_CLOGAL_CTRL_E_PCMIN_CH31|AP_CLOGAL_CTRL_PCM_OUT_AC97|
699 698 AP_CLOGAL_CTRL_MMC_FROM_MIXER|AP_CLOGAL_CTRL_PCM_OUT_TO_AC97));
700 699
701 700 /* do a warm reset, which powers up the Codec */
702 701 OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl,
703 702 AP_SCTRL_WRST_CODEC);
704 703 drv_usecwait(2);
705 704 AND_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl,
706 705 ~AP_SCTRL_WRST_CODEC);
707 706
708 707 /* do a warm reset via the Codec, yes, I'm being paranoid! */
709 708 audiots_set_ac97(state, AC97_RESET_REGISTER, 0);
710 709
711 710 /* Make sure the Codec is powered up. */
712 711 int i = TS_WAIT_CNT;
713 712 while ((audiots_get_ac97(state, AC97_POWERDOWN_CTRL_STAT_REGISTER) &
714 713 PCSR_POWERD_UP) != PCSR_POWERD_UP && i--) {
715 714 drv_usecwait(1);
716 715 }
717 716
718 717 }
719 718
720 719 /*
721 720 * audiots_get_ac97()
722 721 *
723 722 * Description:
724 723 * Get the value in the specified AC-97 Codec register. There is a
725 724 * bug in silicon which forces us to do multiple reads of the Codec's
726 725 * register. This algorithm was provided by T2 and is heuristic in
727 726 * nature. Unfortunately we have no guarantees that the real answer
728 727 * isn't 0x0000, which is what we get when a read fails. So we loop
729 728 * TS_LOOP_CNT times before we give up. We just have to hope this is
730 729 * sufficient to give us the correct value.
731 730 *
732 731 * Arguments:
733 732 * audiots_state_t *state The device's state structure
734 733 * int reg AC-97 register number
735 734 *
736 735 * Returns:
737 736 * unsigned short The value in the specified register
738 737 */
739 738 static uint16_t
740 739 audiots_get_ac97(void *arg, uint8_t reg)
741 740 {
742 741 audiots_state_t *state = arg;
743 742 ddi_acc_handle_t handle = state->ts_acch;
744 743 uint16_t *data;
745 744 int count;
746 745 int delay;
747 746 uint16_t first;
748 747 uint16_t next;
749 748
750 749 if (state->ts_revid == AC_REV_ID1) {
751 750 data = &state->ts_regs->aud_regs.ap_acrd_35D_data;
752 751 } else {
753 752 data = &state->ts_regs->aud_regs.ap_acrdwr_data;
754 753 }
755 754
756 755 /* make sure the register is good */
757 756 reg &= AP_ACRD_INDEX_MASK;
758 757 for (count = TS_LOOP_CNT; count--; ) {
759 758 if ((first = audiots_read_ac97(state, reg)) != 0) {
760 759 next = first;
761 760 break;
762 761 }
763 762
764 763 delay = TS_DELAY_CNT;
765 764 while (delay--) {
766 765 (void) ddi_get16(handle, data);
767 766 }
768 767
769 768 if ((next = audiots_read_ac97(state, reg)) != 0) {
770 769 break;
771 770 }
772 771 }
773 772
774 773 /*
775 774 * Arggg, if you let the next read happen too soon then it fails.
776 775 * 12 usec fails, 13 usec succeeds. So set it to 20 for safety.
777 776 */
778 777 drv_usecwait(TS_20US);
779 778
780 779 return (next);
781 780
782 781 }
783 782
784 783 /*
785 784 * audiots_init_state()
786 785 *
787 786 * Description:
788 787 * This routine initializes the audio driver's state structure.
789 788 * This includes reading the properties.
790 789 *
791 790 * CAUTION: This routine cannot allocate resources, unless it frees
792 791 * them before returning for an error. Also, error_destroy:
793 792 * in audiots_attach() would need to be fixed as well.
794 793 *
795 794 * NOTE: birdsnest supports CD ROM input. We check for the cdrom
796 795 * property. If there we turn it on.
797 796 *
798 797 * Arguments:
799 798 * audiots_state_t *state The device's state structure
800 799 * dev_info_t *dip Pointer to the device's dev_info struct
801 800 *
802 801 * Returns:
803 802 * DDI_SUCCESS State structure initialized
804 803 * DDI_FAILURE State structure not initialized
805 804 */
806 805 static int
807 806 audiots_init_state(audiots_state_t *state, dev_info_t *dip)
808 807 {
809 808 state->ts_ac97 = ac97_alloc(dip, audiots_get_ac97,
810 809 audiots_set_ac97, state);
811 810
812 811 if (state->ts_ac97 == NULL) {
813 812 return (DDI_FAILURE);
814 813 }
815 814
816 815 /* save the device info pointer */
817 816 state->ts_dip = dip;
818 817
819 818 for (int i = 0; i < TS_NUM_PORTS; i++) {
820 819 if (audiots_alloc_port(state, i) != DDI_SUCCESS) {
821 820 return (DDI_FAILURE);
822 821 }
823 822 }
824 823
825 824 return (DDI_SUCCESS);
826 825
827 826 }
828 827
829 828 /*
830 829 * audiots_map_regs()
831 830 *
832 831 * Description:
833 832 * This routine maps the registers in.
834 833 *
835 834 * Once the config space registers are mapped in we determine if the
836 835 * audio core may be power managed. It should, but if it doesn't,
837 836 * then trying to may cause the core to hang.
838 837 *
839 838 * CAUTION: Make sure all errors call audio_dev_warn().
840 839 *
841 840 * Arguments:
842 841 * dev_info_t *dip Pointer to the device's devinfo
843 842 * audiots_state_t *state The device's state structure
844 843 * Returns:
845 844 * DDI_SUCCESS Registers successfully mapped
846 845 * DDI_FAILURE Registers not successfully mapped
847 846 */
848 847 static int
849 848 audiots_map_regs(dev_info_t *dip, audiots_state_t *state)
850 849 {
851 850 char rev[16];
852 851 char *name;
853 852
854 853 /* map in the registers, the config and memory mapped registers */
855 854 if (pci_config_setup(dip, &state->ts_pcih) != DDI_SUCCESS) {
856 855 audio_dev_warn(state->ts_adev,
857 856 "unable to map PCI configuration space");
858 857 return (DDI_FAILURE);
859 858 }
860 859
861 860 /* Read the Audio Controller's vendor, device, and revision IDs */
862 861 state->ts_devid =
863 862 (pci_config_get16(state->ts_pcih, PCI_CONF_VENID) << 16) |
864 863 pci_config_get16(state->ts_pcih, PCI_CONF_DEVID);
865 864 state->ts_revid = pci_config_get8(state->ts_pcih, PCI_CONF_REVID);
866 865
867 866 if (ddi_regs_map_setup(dip, TS_MEM_MAPPED_REGS,
868 867 (caddr_t *)&state->ts_regs, 0, 0, &ts_regs_attr, &state->ts_acch) !=
869 868 DDI_SUCCESS) {
870 869 audio_dev_warn(state->ts_adev,
871 870 "unable to map PCI device registers");
872 871 return (DDI_FAILURE);
873 872 }
874 873
875 874 switch (state->ts_devid) {
876 875 case 0x10b95451:
877 876 name = "ALI M5451";
878 877 break;
879 878 default:
880 879 name = "audiots";
881 880 break;
882 881 }
883 882 (void) snprintf(rev, sizeof (rev), "Rev %x", state->ts_revid);
884 883 audio_dev_set_description(state->ts_adev, name);
885 884 audio_dev_set_version(state->ts_adev, rev);
886 885
887 886 return (DDI_SUCCESS);
888 887 }
889 888
890 889 /*
891 890 * audiots_alloc_port()
892 891 *
893 892 * Description:
894 893 * This routine allocates the DMA handles and the memory for the
895 894 * DMA engines to use. It then binds each of the buffers to its
896 895 * respective handle, getting a DMA cookie.
897 896 *
898 897 * NOTE: All of the ddi_dma_... routines sleep if they cannot get
899 898 * memory. This means these calls should always succeed.
900 899 *
901 900 * NOTE: ddi_dma_alloc_handle() attempts to use the full 4 GB DMA address
902 901 * range. This is to work around Southbridge rev E/G OBP issues.
903 902 * (See Grover OBP note above)
904 903 *
905 904 * CAUTION: Make sure all errors call audio_dev_warn().
906 905 *
907 906 * Arguments:
908 907 * audiots_port_t *state The port structure for a device stream
909 908 * int num The port number
910 909 *
911 910 * Returns:
912 911 * DDI_SUCCESS DMA resources mapped
913 912 * DDI_FAILURE DMA resources not successfully mapped
914 913 */
915 914 int
916 915 audiots_alloc_port(audiots_state_t *state, int num)
917 916 {
918 917 audiots_port_t *port;
919 918 dev_info_t *dip = state->ts_dip;
920 919 audio_dev_t *adev = state->ts_adev;
921 920 int dir;
922 921 unsigned caps;
923 922 ddi_dma_cookie_t cookie;
924 923 unsigned count;
925 924 int rc;
926 925 ddi_acc_handle_t regsh = state->ts_acch;
927 926 uint32_t *gcptr = &state->ts_regs->aud_regs.ap_cir_gc;
928 927
929 928 port = kmem_zalloc(sizeof (*port), KM_SLEEP);
930 929 state->ts_ports[num] = port;
931 930 port->tp_num = num;
932 931 port->tp_state = state;
933 932 port->tp_rate = TS_RATE;
934 933
935 934 if (num == TS_INPUT_PORT) {
936 935 dir = DDI_DMA_READ;
937 936 caps = ENGINE_INPUT_CAP;
938 937 port->tp_dma_stream = 31;
939 938 port->tp_sync_dir = DDI_DMA_SYNC_FORKERNEL;
940 939 } else {
941 940 dir = DDI_DMA_WRITE;
942 941 caps = ENGINE_OUTPUT_CAP;
943 942 port->tp_dma_stream = 0;
944 943 port->tp_sync_dir = DDI_DMA_SYNC_FORDEV;
945 944 }
946 945
947 946 port->tp_dma_mask = (1U << port->tp_dma_stream);
948 947 port->tp_nframes = 4096;
949 948 port->tp_size = port->tp_nframes * TS_FRAMESZ;
950 949
951 950 /* allocate dma handle */
952 951 rc = ddi_dma_alloc_handle(dip, &audiots_attr, DDI_DMA_SLEEP,
953 952 NULL, &port->tp_dmah);
954 953 if (rc != DDI_SUCCESS) {
955 954 audio_dev_warn(adev, "ddi_dma_alloc_handle failed: %d", rc);
956 955 return (DDI_FAILURE);
957 956 }
958 957 /* allocate DMA buffer */
959 958 rc = ddi_dma_mem_alloc(port->tp_dmah, port->tp_size, &ts_acc_attr,
960 959 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &port->tp_kaddr,
961 960 &port->tp_size, &port->tp_acch);
962 961 if (rc == DDI_FAILURE) {
963 962 audio_dev_warn(adev, "dma_mem_alloc failed");
964 963 return (DDI_FAILURE);
965 964 }
966 965
967 966 /* bind DMA buffer */
968 967 rc = ddi_dma_addr_bind_handle(port->tp_dmah, NULL,
969 968 port->tp_kaddr, port->tp_size, dir|DDI_DMA_CONSISTENT,
970 969 DDI_DMA_SLEEP, NULL, &cookie, &count);
971 970 if (rc != DDI_DMA_MAPPED) {
972 971 audio_dev_warn(adev,
973 972 "ddi_dma_addr_bind_handle failed: %d", rc);
974 973 return (DDI_FAILURE);
975 974 }
976 975 ASSERT(count == 1);
977 976
978 977 port->tp_paddr = cookie.dmac_address;
979 978 if ((unsigned)port->tp_paddr & 0x80000000U) {
980 979 ddi_put32(regsh, gcptr,
981 980 ddi_get32(regsh, gcptr) | AP_CIR_GC_SYS_MEM_4G_ENABLE);
982 981 } else {
983 982 ddi_put32(regsh, gcptr,
984 983 ddi_get32(regsh, gcptr) & ~(AP_CIR_GC_SYS_MEM_4G_ENABLE));
985 984 }
986 985 port->tp_engine = audio_engine_alloc(&audiots_engine_ops, caps);
987 986 if (port->tp_engine == NULL) {
988 987 audio_dev_warn(adev, "audio_engine_alloc failed");
989 988 return (DDI_FAILURE);
990 989 }
991 990
992 991 audio_engine_set_private(port->tp_engine, port);
993 992 audio_dev_add_engine(adev, port->tp_engine);
994 993
995 994 return (DDI_SUCCESS);
996 995 }
997 996
998 997 /*
999 998 * audiots_read_ac97()
1000 999 *
1001 1000 * Description:
1002 1001 * This routine actually reads the AC-97 Codec's register. It may
1003 1002 * be called several times to succeed.
1004 1003 *
1005 1004 * NOTE:
1006 1005 * Revision M1535D B1-C of the ALI SouthBridge includes a workaround for
1007 1006 * the broken busy flag. Resetting the busy flag requires a software tweak
1008 1007 * to go with the worked around hardware. When we detect failure, we make
1009 1008 * 10 attempts to reset the chip before we fail. This should reset the new
1010 1009 * SB systems. On all SB systems, this will increse the read delay
1011 1010 * slightly, but shouldn't bother it otherwise.
1012 1011 *
1013 1012 * Arguments:
1014 1013 * audiots_state_t *state The device's state structure
1015 1014 * int reg AC-97 register number
1016 1015 *
1017 1016 * Returns:
1018 1017 * unsigned short The value in the specified register
1019 1018 */
1020 1019 static uint16_t
1021 1020 audiots_read_ac97(audiots_state_t *state, int reg)
1022 1021 {
1023 1022 ddi_acc_handle_t acch = state->ts_acch;
1024 1023 uint16_t *addr;
1025 1024 uint16_t *data;
1026 1025 uint32_t *stimer = &state->ts_regs->aud_regs.ap_stimer;
1027 1026 uint32_t chk1;
1028 1027 uint32_t chk2;
1029 1028 int resets = 0;
1030 1029 int i;
1031 1030
1032 1031 if (state->ts_revid == AC_REV_ID1) {
1033 1032 addr = &state->ts_regs->aud_regs.ap_acrd_35D_reg;
1034 1033 data = &state->ts_regs->aud_regs.ap_acrd_35D_data;
1035 1034 } else {
1036 1035 addr = &state->ts_regs->aud_regs.ap_acrdwr_reg;
1037 1036 data = &state->ts_regs->aud_regs.ap_acrdwr_data;
1038 1037 }
1039 1038
1040 1039 first_read:
1041 1040 /* wait for ready to send read request */
1042 1041 for (i = 0; i < TS_READ_TRIES; i++) {
1043 1042 if (!(ddi_get16(acch, addr) & AP_ACRD_R_READ_BUSY)) {
1044 1043 break;
1045 1044 }
1046 1045 /* don't beat on the bus */
1047 1046 drv_usecwait(1);
1048 1047 }
1049 1048 if (i >= TS_READ_TRIES) {
1050 1049 if (resets < TS_RESET_TRIES) {
1051 1050 /* Attempt to reset */
1052 1051 drv_usecwait(TS_20US);
1053 1052 ddi_put16(acch, addr, TS_SB_RESET);
1054 1053 resets++;
1055 1054 goto first_read;
1056 1055 } else {
1057 1056 state->ts_flags |= TS_AUDIO_READ_FAILED;
1058 1057 if (!(state->ts_flags & TS_READ_FAILURE_PRINTED)) {
1059 1058 ddi_dev_report_fault(state->ts_dip,
1060 1059 DDI_SERVICE_LOST, DDI_DEVICE_FAULT,
1061 1060 "Unable to communicate with AC97 CODEC");
1062 1061 audio_dev_warn(state->ts_adev,
1063 1062 "The audio AC97 register has timed out.");
1064 1063 audio_dev_warn(state->ts_adev,
1065 1064 "Audio is now disabled.");
1066 1065 audio_dev_warn(state->ts_adev,
1067 1066 "Please reboot to restore audio.");
1068 1067
1069 1068 /* Don't flood the console */
1070 1069 state->ts_flags |= TS_READ_FAILURE_PRINTED;
1071 1070 }
1072 1071 }
1073 1072 return (0);
1074 1073 }
1075 1074
1076 1075 /* program the register to read */
1077 1076 ddi_put16(acch, addr, (reg|AP_ACRD_W_PRIMARY_CODEC|
1078 1077 AP_ACRD_W_READ_MIXER_REG|AP_ACRD_W_AUDIO_READ_REQ&
1079 1078 (~AP_ACWR_W_SELECT_WRITE)));
1080 1079
1081 1080 /* hardware bug work around */
1082 1081 chk1 = ddi_get32(acch, stimer);
1083 1082 chk2 = ddi_get32(acch, stimer);
1084 1083 i = TS_WAIT_CNT;
1085 1084 while (chk1 == chk2 && i) {
1086 1085 chk2 = ddi_get32(acch, stimer);
1087 1086 i--;
1088 1087 }
1089 1088 OR_SET_SHORT(acch, addr, AP_ACRD_W_READ_MIXER_REG);
1090 1089 resets = 0;
1091 1090
1092 1091 second_read:
1093 1092 /* wait again for read to send read request */
1094 1093 for (i = 0; i < TS_READ_TRIES; i++) {
1095 1094 if (!(ddi_get16(acch, addr) & AP_ACRD_R_READ_BUSY)) {
1096 1095 break;
1097 1096 }
1098 1097 /* don't beat on the bus */
1099 1098 drv_usecwait(1);
1100 1099 }
1101 1100 if (i >= TS_READ_TRIES) {
1102 1101 if (resets < TS_RESET_TRIES) {
1103 1102 /* Attempt to reset */
1104 1103 drv_usecwait(TS_20US);
1105 1104 ddi_put16(acch, addr, TS_SB_RESET);
1106 1105 resets++;
1107 1106 goto second_read;
1108 1107 } else {
1109 1108 state->ts_flags |= TS_AUDIO_READ_FAILED;
1110 1109 if (!(state->ts_flags & TS_READ_FAILURE_PRINTED)) {
1111 1110 ddi_dev_report_fault(state->ts_dip,
1112 1111 DDI_SERVICE_LOST, DDI_DEVICE_FAULT,
1113 1112 "Unable to communicate with AC97 CODEC");
1114 1113 audio_dev_warn(state->ts_adev,
1115 1114 "The audio AC97 register has timed out.");
1116 1115 audio_dev_warn(state->ts_adev,
1117 1116 "Audio is now disabled.");
1118 1117 audio_dev_warn(state->ts_adev,
1119 1118 "Please reboot to restore audio.");
1120 1119
1121 1120 /* Don't flood the console */
1122 1121 state->ts_flags |= TS_READ_FAILURE_PRINTED;
1123 1122 }
1124 1123 }
1125 1124 return (0);
1126 1125 }
1127 1126
1128 1127 return (ddi_get16(acch, data));
1129 1128
1130 1129 } /* audiots_read_ac97() */
1131 1130
1132 1131 /*
1133 1132 * audiots_set_ac97()
1134 1133 *
1135 1134 * Description:
1136 1135 * Set the value in the specified AC-97 Codec register. Just like
1137 1136 * reading the AC-97 Codec, it is possible there is a problem writing
1138 1137 * it as well. So we loop.
1139 1138 *
1140 1139 * Arguments:
1141 1140 * audiots_state_t *state The device's state structure
1142 1141 * int reg AC-97 register number
1143 1142 * uint16_t value The value to write
1144 1143 */
1145 1144 static void
1146 1145 audiots_set_ac97(void *arg, uint8_t reg8, uint16_t data)
1147 1146 {
1148 1147 audiots_state_t *state = arg;
1149 1148 ddi_acc_handle_t handle = state->ts_acch;
1150 1149 uint16_t *data_addr = &state->ts_regs->aud_regs.ap_acrdwr_data;
1151 1150 uint16_t *reg_addr = &state->ts_regs->aud_regs.ap_acrdwr_reg;
1152 1151 int count;
1153 1152 int i;
1154 1153 uint16_t tmp_short;
1155 1154 uint16_t reg = reg8;
1156 1155
1157 1156 reg &= AP_ACWR_INDEX_MASK;
1158 1157
1159 1158 /* Don't touch the reserved bits on the pre 35D+ SouthBridge */
1160 1159 if (state->ts_revid == AC_REV_ID1) {
1161 1160 reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG;
1162 1161 } else {
1163 1162 reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG|
1164 1163 AP_ACWR_W_SELECT_WRITE;
1165 1164 }
1166 1165
1167 1166 for (count = TS_LOOP_CNT; count--; ) {
1168 1167 /* wait for ready to write */
1169 1168 for (i = 0; i < TS_WAIT_CNT; i++) {
1170 1169 if (!(ddi_get16(handle, reg_addr) &
1171 1170 AP_ACWR_R_WRITE_BUSY)) {
1172 1171 /* ready to write */
1173 1172 ddi_put16(handle, reg_addr, reg);
1174 1173
1175 1174 /* Write the data */
1176 1175 ddi_put16(handle, data_addr, data);
1177 1176 break;
1178 1177 }
1179 1178 }
1180 1179 if (i >= TS_WAIT_CNT) {
1181 1180 /* try again */
1182 1181 continue;
1183 1182 }
1184 1183
1185 1184 /* wait for write to complete */
1186 1185 for (i = 0; i < TS_WAIT_CNT; i++) {
1187 1186 if (!(ddi_get16(handle, reg_addr) &
1188 1187 AP_ACWR_R_WRITE_BUSY)) {
1189 1188 /* done writing */
1190 1189 break;
1191 1190 }
1192 1191 }
1193 1192
1194 1193 /* verify the value written */
1195 1194 tmp_short = audiots_get_ac97(state, reg8);
1196 1195 if (data == tmp_short) {
1197 1196 /* successfully loaded, so we can return */
1198 1197 return;
1199 1198 }
1200 1199 }
1201 1200
1202 1201 } /* audiots_set_ac97() */
1203 1202
1204 1203 /*
1205 1204 * audiots_open()
1206 1205 *
1207 1206 * Description:
1208 1207 * Opens a DMA engine for use. Will also ensure the device is powered
1209 1208 * up if not already done so.
1210 1209 *
1211 1210 * Arguments:
1212 1211 * void *arg The DMA engine to set up
1213 1212 * int flag Open flags
1214 1213 * unsigned *nframesp Receives number of frames
1215 1214 * caddr_t *bufp Receives kernel data buffer
1216 1215 *
1217 1216 * Returns:
1218 1217 * 0 on success
1219 1218 * errno on failure
1220 1219 */
1221 1220 static int
1222 1221 audiots_open(void *arg, int flag, unsigned *nframesp, caddr_t *bufp)
1223 1222 {
1224 1223 audiots_port_t *port = arg;
1225 1224
1226 1225 _NOTE(ARGUNUSED(flag));
1227 1226
1228 1227 port->tp_count = 0;
1229 1228 port->tp_cso = 0;
1230 1229 *nframesp = port->tp_nframes;
1231 1230 *bufp = port->tp_kaddr;
1232 1231
1233 1232 return (0);
1234 1233 }
1235 1234
1236 1235 /*
1237 1236 * audiots_close()
1238 1237 *
1239 1238 * Description:
1240 1239 * Closes an audio DMA engine that was previously opened. Since
1241 1240 * nobody is using it, we could take this opportunity to possibly power
1242 1241 * down the entire device, or at least the DMA engine.
1243 1242 *
1244 1243 * Arguments:
1245 1244 * void *arg The DMA engine to shut down
1246 1245 */
1247 1246 static void
1248 1247 audiots_close(void *arg)
1249 1248 {
1250 1249 _NOTE(ARGUNUSED(arg));
1251 1250 }
1252 1251
1253 1252 /*
1254 1253 * audiots_stop()
1255 1254 *
1256 1255 * Description:
1257 1256 * This is called by the framework to stop a port that is
1258 1257 * transferring data.
1259 1258 *
1260 1259 * Arguments:
1261 1260 * void *arg The DMA engine to stop
1262 1261 */
1263 1262 static void
1264 1263 audiots_stop(void *arg)
1265 1264 {
1266 1265 audiots_port_t *port = arg;
1267 1266 audiots_state_t *state = port->tp_state;
1268 1267
1269 1268 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop,
1270 1269 port->tp_dma_mask);
1271 1270 }
1272 1271
1273 1272 /*
1274 1273 * audiots_start()
1275 1274 *
1276 1275 * Description:
1277 1276 * This is called by the framework to start a port transferring data.
1278 1277 *
1279 1278 * Arguments:
1280 1279 * void *arg The DMA engine to start
1281 1280 *
1282 1281 * Returns:
1283 1282 * 0 on success (never fails, errno if it did)
1284 1283 */
1285 1284 static int
1286 1285 audiots_start(void *arg)
1287 1286 {
1288 1287 audiots_port_t *port = arg;
1289 1288 audiots_state_t *state = port->tp_state;
1290 1289 ddi_acc_handle_t handle = state->ts_acch;
1291 1290 audiots_regs_t *regs = state->ts_regs;
1292 1291 audiots_aram_t *aram;
1293 1292 audiots_eram_t *eram;
1294 1293 unsigned delta;
1295 1294 uint16_t ctrl;
1296 1295 uint16_t gvsel;
1297 1296 uint16_t eso;
1298 1297
1299 1298 aram = ®s->aud_ram[port->tp_dma_stream].aram;
1300 1299 eram = ®s->aud_ram[port->tp_dma_stream].eram;
1301 1300
1302 1301 port->tp_cso = 0;
1303 1302
1304 1303 gvsel = ERAM_WAVE_VOL | ERAM_PAN_0dB | ERAM_VOL_DEFAULT;
1305 1304 ctrl = ERAM_16_BITS | ERAM_STEREO | ERAM_LOOP_MODE | ERAM_SIGNED_PCM;
1306 1305
1307 1306 delta = (port->tp_rate << TS_SRC_SHIFT) / TS_RATE;
1308 1307
1309 1308 if (port->tp_num == TS_INPUT_PORT) {
1310 1309 delta = (TS_RATE << TS_SRC_SHIFT) / port->tp_rate;
1311 1310 }
1312 1311 eso = port->tp_nframes - 1;
1313 1312
1314 1313 /* program the sample rate */
1315 1314 ddi_put16(handle, &aram->aram_delta, (uint16_t)delta);
1316 1315
1317 1316 /* program the precision, number of channels and loop mode */
1318 1317 ddi_put16(handle, &eram->eram_ctrl_ec, ctrl);
1319 1318
1320 1319 /* program the volume settings */
1321 1320 ddi_put16(handle, &eram->eram_gvsel_pan_vol, gvsel);
1322 1321
1323 1322 /* set ALPHA and FMS to 0 */
1324 1323 ddi_put16(handle, &aram->aram_alpha_fms, 0x0);
1325 1324
1326 1325 /* set CSO to 0 */
1327 1326 ddi_put16(handle, &aram->aram_cso, 0x0);
1328 1327
1329 1328 /* set LBA */
1330 1329 ddi_put32(handle, &aram->aram_cptr_lba,
1331 1330 port->tp_paddr & ARAM_LBA_MASK);
1332 1331
1333 1332 /* set ESO */
1334 1333 ddi_put16(handle, &aram->aram_eso, eso);
1335 1334
1336 1335 /* stop the DMA engines */
1337 1336 ddi_put32(handle, ®s->aud_regs.ap_stop, port->tp_dma_mask);
1338 1337
1339 1338 /* now make sure it starts playing */
1340 1339 ddi_put32(handle, ®s->aud_regs.ap_start, port->tp_dma_mask);
1341 1340
1342 1341 return (0);
1343 1342 }
1344 1343
1345 1344 /*
1346 1345 * audiots_chinfo()
1347 1346 *
1348 1347 * Description:
1349 1348 * This is called by the framework to query the channel offsets
1350 1349 * and ordering.
1351 1350 *
1352 1351 * Arguments:
1353 1352 * void *arg The DMA engine to query
1354 1353 * int chan Channel number.
1355 1354 * unsigned *offset Starting offset of channel.
1356 1355 * unsigned *incr Increment (in samples) between frames.
1357 1356 *
1358 1357 * Returns:
1359 1358 * 0 indicating rate array is range instead of enumeration
1360 1359 */
1361 1360
1362 1361 static void
1363 1362 audiots_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr)
1364 1363 {
1365 1364 _NOTE(ARGUNUSED(arg));
1366 1365 *offset = chan;
1367 1366 *incr = 2;
1368 1367 }
1369 1368
1370 1369 /*
1371 1370 * audiots_format()
1372 1371 *
1373 1372 * Description:
1374 1373 * Called by the framework to query the format for the device.
1375 1374 *
1376 1375 * Arguments:
1377 1376 * void *arg The DMA engine to query
1378 1377 *
1379 1378 * Returns:
1380 1379 * AUDIO_FORMAT_S16_LE.
1381 1380 */
1382 1381 static int
1383 1382 audiots_format(void *arg)
1384 1383 {
1385 1384 _NOTE(ARGUNUSED(arg));
1386 1385
1387 1386 return (AUDIO_FORMAT_S16_LE);
1388 1387 }
1389 1388
1390 1389
1391 1390 /*
1392 1391 * audiots_channels()
1393 1392 *
1394 1393 * Description:
1395 1394 * Called by the framework to query the channnels for the device.
1396 1395 *
1397 1396 * Arguments:
1398 1397 * void *arg The DMA engine to query
1399 1398 *
1400 1399 * Returns:
1401 1400 * 2 (Stereo).
1402 1401 */
1403 1402 static int
1404 1403 audiots_channels(void *arg)
1405 1404 {
1406 1405 _NOTE(ARGUNUSED(arg));
1407 1406
1408 1407 return (2);
1409 1408 }
1410 1409
1411 1410 /*
1412 1411 * audiots_rate()
1413 1412 *
1414 1413 * Description:
1415 1414 * Called by the framework to query the sample rates for the device.
1416 1415 *
1417 1416 * Arguments:
1418 1417 * void *arg The DMA engine to query
1419 1418 *
1420 1419 * Returns:
1421 1420 * Sample rate in HZ (always 48000).
1422 1421 */
1423 1422 static int
1424 1423 audiots_rate(void *arg)
1425 1424 {
1426 1425 audiots_port_t *port = arg;
1427 1426
1428 1427 return (port->tp_rate);
1429 1428 }
1430 1429
1431 1430 /*
1432 1431 * audiots_count()
1433 1432 *
1434 1433 * Description:
1435 1434 * This is called by the framework to get the engine's frame counter
1436 1435 *
1437 1436 * Arguments:
1438 1437 * void *arg The DMA engine to query
1439 1438 *
1440 1439 * Returns:
1441 1440 * frame count for current engine
1442 1441 */
1443 1442 static uint64_t
1444 1443 audiots_count(void *arg)
1445 1444 {
1446 1445 audiots_port_t *port = arg;
1447 1446 audiots_state_t *state = port->tp_state;
1448 1447 uint64_t val;
1449 1448 uint16_t cso;
1450 1449 unsigned n;
1451 1450
1452 1451 cso = ddi_get16(state->ts_acch,
1453 1452 &state->ts_regs->aud_ram[port->tp_dma_stream].aram.aram_cso);
1454 1453
1455 1454 n = (cso >= port->tp_cso) ?
1456 1455 cso - port->tp_cso :
1457 1456 cso + port->tp_nframes - port->tp_cso;
1458 1457
1459 1458 port->tp_cso = cso;
1460 1459 port->tp_count += n;
1461 1460 val = port->tp_count;
1462 1461
1463 1462 return (val);
1464 1463 }
1465 1464
1466 1465 /*
1467 1466 * audiots_sync()
1468 1467 *
1469 1468 * Description:
1470 1469 * This is called by the framework to synchronize DMA caches.
1471 1470 *
1472 1471 * Arguments:
1473 1472 * void *arg The DMA engine to sync
1474 1473 */
1475 1474 static void
1476 1475 audiots_sync(void *arg, unsigned nframes)
1477 1476 {
1478 1477 audiots_port_t *port = arg;
1479 1478 _NOTE(ARGUNUSED(nframes));
1480 1479
1481 1480 (void) ddi_dma_sync(port->tp_dmah, 0, 0, port->tp_sync_dir);
1482 1481 }
1483 1482
1484 1483 /*
1485 1484 * audiots_stop_everything()
1486 1485 *
1487 1486 * Description:
1488 1487 * This routine disables the address engine interrupt for all 32 DMA
1489 1488 * engines. Just to be sure, it then explicitly issues a stop command to
1490 1489 * the address engine and envelope engines for all 32 channels.
1491 1490 *
1492 1491 * NOTE:
1493 1492 *
1494 1493 * There is a hardware bug that generates a spurious interrupt
1495 1494 * when the DMA engines are stopped. It's not consistent - it
1496 1495 * happens every 1 out of 6 stops or so. It will show up as a
1497 1496 * record interrupt. The problem is that once the driver is
1498 1497 * detached or if the system goes into low power mode, nobody
1499 1498 * will service that interrupt. The system will eventually become
1500 1499 * unusable.
1501 1500 *
1502 1501 * Arguments:
1503 1502 * audiots_state_t *state The device's state structure
1504 1503 */
1505 1504 static void
1506 1505 audiots_stop_everything(audiots_state_t *state)
1507 1506 {
1508 1507 if (state->ts_acch == NULL)
1509 1508 return;
1510 1509
1511 1510 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten,
1512 1511 TS_ALL_DMA_OFF);
1513 1512
1514 1513 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop,
1515 1514 TS_ALL_DMA_ENGINES);
1516 1515
1517 1516 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_aint,
1518 1517 TS_ALL_DMA_ENGINES);
1519 1518 }
1520 1519
1521 1520 /*
1522 1521 * audiots_free_port()
1523 1522 *
1524 1523 * Description:
1525 1524 * This routine unbinds the DMA cookies, frees the DMA buffers,
1526 1525 * deallocates the DMA handles.
1527 1526 *
1528 1527 * Arguments:
1529 1528 * audiots_port_t *port The port structure for a device stream.
1530 1529 */
1531 1530 void
1532 1531 audiots_free_port(audiots_port_t *port)
1533 1532 {
1534 1533 if (port == NULL)
1535 1534 return;
1536 1535
1537 1536 if (port->tp_engine) {
1538 1537 audio_dev_remove_engine(port->tp_state->ts_adev,
1539 1538 port->tp_engine);
1540 1539 audio_engine_free(port->tp_engine);
1541 1540 }
1542 1541 if (port->tp_paddr) {
1543 1542 (void) ddi_dma_unbind_handle(port->tp_dmah);
1544 1543 }
1545 1544 if (port->tp_acch) {
1546 1545 ddi_dma_mem_free(&port->tp_acch);
1547 1546 }
1548 1547 if (port->tp_dmah) {
1549 1548 ddi_dma_free_handle(&port->tp_dmah);
1550 1549 }
1551 1550 kmem_free(port, sizeof (*port));
1552 1551 }
1553 1552
1554 1553 /*
1555 1554 * audiots_destroy()
1556 1555 *
1557 1556 * Description:
1558 1557 * This routine releases all resources held by the device instance,
1559 1558 * as part of either detach or a failure in attach.
1560 1559 *
1561 1560 * Arguments:
1562 1561 * audiots_state_t *state The device soft state.
1563 1562 */
1564 1563 void
1565 1564 audiots_destroy(audiots_state_t *state)
1566 1565 {
1567 1566 audiots_stop_everything(state);
1568 1567
1569 1568 for (int i = 0; i < TS_NUM_PORTS; i++)
1570 1569 audiots_free_port(state->ts_ports[i]);
1571 1570
1572 1571 if (state->ts_acch)
1573 1572 ddi_regs_map_free(&state->ts_acch);
1574 1573
1575 1574 if (state->ts_pcih)
1576 1575 pci_config_teardown(&state->ts_pcih);
1577 1576
1578 1577 if (state->ts_ac97)
1579 1578 ac97_free(state->ts_ac97);
1580 1579
1581 1580 if (state->ts_adev)
1582 1581 audio_dev_free(state->ts_adev);
1583 1582
1584 1583 ddi_soft_state_free(audiots_statep, ddi_get_instance(state->ts_dip));
1585 1584 }
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