1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26
27 /*
28 * audiots Audio Driver
29 *
30 * This Audio Driver controls the T2 audio core in the ALI M1553
31 * southbridge chip. This chip supports multiple play streams, but just
32 * a single record stream. It also supports wave table synthesis and
33 * hardware MIDI and joystick ports. Unfortunately the MIDI ports are
34 * not available because their pins have been re-assigned to expose
35 * interrupts. We also aren't going to do anything with the joystick
36 * ports. The audio core controls an AC-97 V2.1 Codec.
37 *
38 * The DMA engine uses a single buffer which is large enough to hold
39 * two interrupts worth of data. When it gets to the mid point an
40 * interrupt is generated and data is either sent (for record) or
41 * requested and put in that half of the buffer (for play). When the
42 * second half is played we do the same, but the audio core loops the
43 * pointer back to the beginning.
44 *
45 * The audio core has a bug in silicon that doesn't let it read the AC-97
46 * Codec's register. T2 has provided an algorithm that attempts to read the
47 * the Codec several times. This is probably heuristic and thus isn't
48 * absolutely guaranteed to work. However we do have to place a limit on
49 * the looping, otherwise when we read a valid 0x00 we would never exit
50 * the loop. Unfortunately there is also a problem with writing the AC-97
51 * Codec's registers as well. Thus we read it back to verify the write.
52 *
53 * The AC'97 common code provides shadow state for AC'97 registers for us,
54 * so we only need to read those registers during early startup (primarily
55 * to determine codec id and capabilities.)
56 *
57 * We don't save any of the audio controller registers during normal
58 * operation. When we need to save register state we only have to save
59 * the aram and eram. The rest of the controller state is never modified
60 * from the initial programming. Thus restoring the controller state
61 * can be done from audiots_chip_init() as well.
62 *
63 *
64 * WARNING: The SME birdsnest platform uses a PCI bridge chip between the
65 * CPU and the southbridge containing the audio core. There is
66 * a bug in silicon that causes a bogus parity error. With the mixer
67 * reimplementation project, Bug 4374774, the audio driver is always
68 * set to the best precision and number of channels. Thus when turning
69 * the mixer on and off the only thing that changes is the sample rate.
70 * This change in programming doesn't trigger the silicon error.
71 * Thus the supported channels must always be 2 and the precision
72 * must always be 16-bits. This will keep any future change in the
73 * mixer from exposing this bug.
74 *
75 * Due to a hardware bug, system power management is not supported by this
76 * driver.
77 *
78 * CAUTION: If audio controller state is changed outside of aram
79 * and eram then that information must be saved and restored
80 * during power management shutdown and bringup.
81 *
82 * NOTE: The AC-97 Codec's reset pin is set to PCI reset, so we
83 * can't power down the Codec all the way.
84 *
85 * NOTE: This driver depends on the drv/audio and misc/ac97
86 * modules being loaded first.
87 *
88 * NOTE: Don't OR the ap_stop register to stop a play or record. This
89 * will just stop all active channels because a read of ap_stop
90 * returns ap_start. Just set the ap_stop register with the
91 * channels you want to stop. The same goes for ap_start.
92 *
93 * NOTE: There is a hardware problem with P2 rev motherboards. After
94 * prolonged use, reading the AC97 register will always return
95 * busy. The AC97 register is now useless. Consequently, we are no
96 * longer able to program the Codec. This work around disables
97 * audio when this state is detected. It's not great, but its
98 * better than having audio blasting out at 100% all the time.
99 *
100 * NOTE: Power Management testing has also exposed this AC97 timeout
101 * problem. Management has decided this is too risky for customers
102 * and hence they want power management support removed from the
103 * audio subsystem. All PM support is now removed.
104 */
105
106 /*
107 * Synchronization notes:
108 *
109 * The audio framework guarantees that our entry points are exclusive
110 * with suspend and resume. This includes data flow and control entry
111 * points alike.
112 *
113 * The audio framework guarantees that only one control is being
114 * accessed on any given audio device at a time.
115 *
116 * The audio framework guarantees that entry points are themselves
117 * serialized for a given engine.
118 *
119 * We have no interrupt routine or other internal asynchronous routines.
120 *
121 * Our device uses completely separate registers for each engine,
122 * except for the start/stop registers, which are implemented in a
123 * manner that allows for them to be accessed concurrently safely from
124 * different threads.
125 *
126 * Hence, it turns out that we simply don't need any locking in this
127 * driver.
128 */
129
130 #include <sys/modctl.h>
131 #include <sys/kmem.h>
132 #include <sys/pci.h>
133 #include <sys/ddi.h>
134 #include <sys/sunddi.h>
135 #include <sys/debug.h>
136 #include <sys/note.h>
137 #include <sys/audio/audio_driver.h>
138 #include <sys/audio/ac97.h>
139 #include "audiots.h"
140
141 /*
142 * Module linkage routines for the kernel
143 */
144 static int audiots_attach(dev_info_t *, ddi_attach_cmd_t);
145 static int audiots_detach(dev_info_t *, ddi_detach_cmd_t);
146 static int audiots_quiesce(dev_info_t *);
147
148 /*
149 * Entry point routine prototypes
150 */
151 static int audiots_open(void *, int, unsigned *, caddr_t *);
152 static void audiots_close(void *);
153 static int audiots_start(void *);
154 static void audiots_stop(void *);
155 static int audiots_format(void *);
156 static int audiots_channels(void *);
157 static int audiots_rate(void *);
158 static void audiots_chinfo(void *, int, unsigned *, unsigned *);
159 static uint64_t audiots_count(void *);
160 static void audiots_sync(void *, unsigned);
161
162 static audio_engine_ops_t audiots_engine_ops = {
163 AUDIO_ENGINE_VERSION,
164 audiots_open,
165 audiots_close,
166 audiots_start,
167 audiots_stop,
168 audiots_count,
169 audiots_format,
170 audiots_channels,
171 audiots_rate,
172 audiots_sync,
173 NULL,
174 audiots_chinfo,
175 NULL,
176 };
177
178 /*
179 * Local Routine Prototypes
180 */
181 static void audiots_power_up(audiots_state_t *);
182 static void audiots_chip_init(audiots_state_t *);
183 static uint16_t audiots_get_ac97(void *, uint8_t);
184 static void audiots_set_ac97(void *, uint8_t, uint16_t);
185 static int audiots_init_state(audiots_state_t *, dev_info_t *);
186 static int audiots_map_regs(dev_info_t *, audiots_state_t *);
187 static uint16_t audiots_read_ac97(audiots_state_t *, int);
188 static void audiots_stop_everything(audiots_state_t *);
189 static void audiots_destroy(audiots_state_t *);
190 static int audiots_alloc_port(audiots_state_t *, int);
191
192 /*
193 * Global variables, but viewable only by this file.
194 */
195
196 /* anchor for soft state structures */
197 static void *audiots_statep;
198
199 /*
200 * DDI Structures
201 */
202
203 /* Device operations structure */
204 static struct dev_ops audiots_dev_ops = {
205 DEVO_REV, /* devo_rev */
206 0, /* devo_refcnt */
207 NULL, /* devo_getinfo */
208 nulldev, /* devo_identify - obsolete */
209 nulldev, /* devo_probe */
210 audiots_attach, /* devo_attach */
211 audiots_detach, /* devo_detach */
212 nodev, /* devo_reset */
213 NULL, /* devo_cb_ops */
214 NULL, /* devo_bus_ops */
215 NULL, /* devo_power */
216 audiots_quiesce, /* devo_quiesce */
217 };
218
219 /* Linkage structure for loadable drivers */
220 static struct modldrv audiots_modldrv = {
221 &mod_driverops, /* drv_modops */
222 TS_MOD_NAME, /* drv_linkinfo */
223 &audiots_dev_ops /* drv_dev_ops */
224 };
225
226 /* Module linkage structure */
227 static struct modlinkage audiots_modlinkage = {
228 MODREV_1, /* ml_rev */
229 { (void *)&audiots_modldrv, NULL } /* ml_linkage */
230 };
231
232
233 /*
234 * NOTE: Grover OBP v4.0.166 and rev G of the ALI Southbridge chip force the
235 * audiots driver to use the upper 2 GB DMA address range. However to maintain
236 * backwards compatibility with older systems/OBP, we're going to try the full
237 * 4 GB DMA range.
238 *
239 * Eventually, this will be set back to using the proper high 2 GB DMA range.
240 */
241
242 /* Device attribute structure - full 4 gig address range */
243 static ddi_dma_attr_t audiots_attr = {
244 DMA_ATTR_VERSION, /* version */
245 0x0000000000000000LL, /* dlim_addr_lo */
246 0x00000000ffffffffLL, /* dlim_addr_hi */
247 0x0000000000003fffLL, /* DMA counter register - 16 bits */
248 0x0000000000000008LL, /* DMA address alignment, 64-bit */
249 0x0000007f, /* 1 through 64 byte burst sizes */
250 0x00000001, /* min effective DMA size */
251 0x0000000000003fffLL, /* maximum transfer size, 16k */
252 0x000000000000ffffLL, /* segment boundary, 64k */
253 0x00000001, /* s/g list length, no s/g */
254 0x00000001, /* granularity of device, don't care */
255 0 /* DMA flags */
256 };
257
258 static ddi_device_acc_attr_t ts_acc_attr = {
259 DDI_DEVICE_ATTR_V0,
260 DDI_NEVERSWAP_ACC,
261 DDI_STRICTORDER_ACC
262 };
263
264 static ddi_device_acc_attr_t ts_regs_attr = {
265 DDI_DEVICE_ATTR_V0,
266 DDI_STRUCTURE_LE_ACC,
267 DDI_STRICTORDER_ACC
268 };
269
270 /*
271 * _init()
272 *
273 * Description:
274 * Driver initialization, called when driver is first loaded.
275 * This is how access is initially given to all the static structures.
276 *
277 * Arguments:
278 * None
279 *
280 * Returns:
281 * ddi_soft_state_init() status, see ddi_soft_state_init(9f), or
282 * mod_install() status, see mod_install(9f)
283 */
284 int
285 _init(void)
286 {
287 int error;
288
289 audio_init_ops(&audiots_dev_ops, TS_NAME);
290
291 /* initialize the soft state */
292 if ((error = ddi_soft_state_init(&audiots_statep,
293 sizeof (audiots_state_t), 1)) != 0) {
294 audio_fini_ops(&audiots_dev_ops);
295 return (error);
296 }
297
298 if ((error = mod_install(&audiots_modlinkage)) != 0) {
299 audio_fini_ops(&audiots_dev_ops);
300 ddi_soft_state_fini(&audiots_statep);
301 }
302
303 return (error);
304 }
305
306 /*
307 * _fini()
308 *
309 * Description:
310 * Module de-initialization, called when the driver is to be unloaded.
311 *
312 * Arguments:
313 * None
314 *
315 * Returns:
316 * mod_remove() status, see mod_remove(9f)
317 */
318 int
319 _fini(void)
320 {
321 int error;
322
323 if ((error = mod_remove(&audiots_modlinkage)) != 0) {
324 return (error);
325 }
326
327 /* free the soft state internal structures */
328 ddi_soft_state_fini(&audiots_statep);
329
330 /* clean up ops */
331 audio_fini_ops(&audiots_dev_ops);
332
333 return (0);
334 }
335
336 /*
337 * _info()
338 *
339 * Description:
340 * Module information, returns infomation about the driver.
341 *
342 * Arguments:
343 * modinfo *modinfop Pointer to the opaque modinfo structure
344 *
345 * Returns:
346 * mod_info() status, see mod_info(9f)
347 */
348 int
349 _info(struct modinfo *modinfop)
350 {
351 int error;
352
353 error = mod_info(&audiots_modlinkage, modinfop);
354
355 return (error);
356 }
357
358
359 /*
360 * audiots_attach()
361 *
362 * Description:
363 * Attach an instance of the audiots driver. This routine does the
364 * device dependent attach tasks.
365 *
366 * Arguments:
367 * dev_info_t *dip Pointer to the device's dev_info struct
368 * ddi_attach_cmd_t cmd Attach command
369 *
370 * Returns:
371 * DDI_SUCCESS The driver was initialized properly
372 * DDI_FAILURE The driver couldn't be initialized properly
373 */
374 static int
375 audiots_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
376 {
377 audiots_state_t *state;
378 int instance;
379
380 instance = ddi_get_instance(dip);
381
382 switch (cmd) {
383 case DDI_ATTACH:
384 break;
385 case DDI_RESUME:
386
387 /* we've already allocated the state structure so get ptr */
388 state = ddi_get_soft_state(audiots_statep, instance);
389 ASSERT(dip == state->ts_dip);
390
391 /* suspend/resume resets the chip, so we have no more faults */
392 if (state->ts_flags & TS_AUDIO_READ_FAILED) {
393 ddi_dev_report_fault(state->ts_dip,
394 DDI_SERVICE_RESTORED,
395 DDI_DEVICE_FAULT,
396 "check port, gain, balance, and mute settings");
397 /* and clear the fault state flags */
398 state->ts_flags &=
399 ~(TS_AUDIO_READ_FAILED|TS_READ_FAILURE_PRINTED);
400 }
401
402 audiots_power_up(state);
403 audiots_chip_init(state);
404
405 ac97_reset(state->ts_ac97);
406
407 audio_dev_resume(state->ts_adev);
408
409 return (DDI_SUCCESS);
410
411 default:
412 return (DDI_FAILURE);
413 }
414
415 /* before we do anything make sure that we haven't had a h/w failure */
416 if (ddi_get_devstate(dip) == DDI_DEVSTATE_DOWN) {
417 cmn_err(CE_WARN, "%s%d: The audio hardware has "
418 "been disabled.", ddi_driver_name(dip), instance);
419 cmn_err(CE_CONT, "Please reboot to restore audio.");
420 return (DDI_FAILURE);
421 }
422
423 /* allocate the state structure */
424 if (ddi_soft_state_zalloc(audiots_statep, instance) == DDI_FAILURE) {
425 cmn_err(CE_WARN, "!%s%d: soft state allocate failed",
426 ddi_driver_name(dip), instance);
427 return (DDI_FAILURE);
428 }
429
430 /*
431 * WARNING: From here on all errors require that we free memory,
432 * including the state structure.
433 */
434
435 /* get the state structure - cannot fail */
436 state = ddi_get_soft_state(audiots_statep, instance);
437 ASSERT(state != NULL);
438
439 if ((state->ts_adev = audio_dev_alloc(dip, 0)) == NULL) {
440 cmn_err(CE_WARN, "unable to allocate audio dev");
441 goto error;
442 }
443
444 /* map in the registers, allocate DMA buffers, etc. */
445 if (audiots_map_regs(dip, state) == DDI_FAILURE) {
446 audio_dev_warn(state->ts_adev, "unable to map registers");
447 goto error;
448 }
449
450 /* initialize the audio state structures */
451 if (audiots_init_state(state, dip) == DDI_FAILURE) {
452 audio_dev_warn(state->ts_adev, "init state structure failed");
453 goto error;
454 }
455
456 /* power up */
457 audiots_power_up(state);
458
459 /* initialize the audio controller */
460 audiots_chip_init(state);
461
462 /* initialize the AC-97 Codec */
463 if (ac97_init(state->ts_ac97, state->ts_adev) != 0) {
464 goto error;
465 }
466
467 /* put the engine interrupts into a known state -- all off */
468 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten,
469 TS_ALL_DMA_OFF);
470
471 /* call the framework attach routine */
472 if (audio_dev_register(state->ts_adev) != DDI_SUCCESS) {
473 audio_dev_warn(state->ts_adev, "unable to register audio");
474 goto error;
475 }
476
477 /* everything worked out, so report the device */
478 ddi_report_dev(dip);
479
480 return (DDI_SUCCESS);
481
482 error:
483 audiots_destroy(state);
484 return (DDI_FAILURE);
485 }
486
487 /*
488 * audiots_detach()
489 *
490 * Description:
491 * Detach an instance of the audiots driver.
492 *
493 * Arguments:
494 * dev_info_t *dip Pointer to the device's dev_info struct
495 * ddi_detach_cmd_t cmd Detach command
496 *
497 * Returns:
498 * DDI_SUCCESS The driver was detached
499 * DDI_FAILURE The driver couldn't be detached
500 */
501 static int
502 audiots_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
503 {
504 audiots_state_t *state;
505 int instance;
506
507 instance = ddi_get_instance(dip);
508
509 /* get the state structure */
510 if ((state = ddi_get_soft_state(audiots_statep, instance)) == NULL) {
511 cmn_err(CE_WARN, "!%s%d: detach get soft state failed",
512 ddi_driver_name(dip), instance);
513 return (DDI_FAILURE);
514 }
515
516 switch (cmd) {
517 case DDI_DETACH:
518 break;
519 case DDI_SUSPEND:
520
521 audio_dev_suspend(state->ts_adev);
522
523 /* stop playing and recording */
524 (void) audiots_stop_everything(state);
525
526 return (DDI_SUCCESS);
527
528 default:
529 return (DDI_FAILURE);
530 }
531
532 /* attempt to unregister from the framework first */
533 if (audio_dev_unregister(state->ts_adev) != DDI_SUCCESS) {
534 return (DDI_FAILURE);
535 }
536
537 audiots_destroy(state);
538
539 return (DDI_SUCCESS);
540
541 }
542
543 /*
544 * audiots_quiesce()
545 *
546 * Description:
547 * Quiesce an instance of the audiots driver. Stops all DMA and
548 * interrupts.
549 *
550 * Arguments:
551 * dev_info_t *dip Pointer to the device's dev_info struct
552 *
553 * Returns:
554 * DDI_SUCCESS The driver was quiesced
555 * DDI_SUCCESS The driver was NOT quiesced
556 */
557 static int
558 audiots_quiesce(dev_info_t *dip)
559 {
560 audiots_state_t *state;
561 int instance;
562
563 instance = ddi_get_instance(dip);
564
565 /* get the state structure */
566 if ((state = ddi_get_soft_state(audiots_statep, instance)) == NULL) {
567 return (DDI_FAILURE);
568 }
569
570 audiots_stop_everything(state);
571
572 return (DDI_SUCCESS);
573 }
574
575 /*
576 * audiots_power_up()
577 *
578 * Description
579 * Ensure that the device is running in PCI power state D0.
580 */
581 static void
582 audiots_power_up(audiots_state_t *state)
583 {
584 ddi_acc_handle_t pcih = state->ts_pcih;
585 uint8_t ptr;
586 uint16_t pmcsr;
587
588 if ((pci_config_get16(pcih, PCI_CONF_STAT) & PCI_STAT_CAP) == 0) {
589 /* does not implement PCI capabilities -- no PM */
590 return;
591 }
592
593 ptr = pci_config_get8(pcih, PCI_CONF_CAP_PTR);
594 for (;;) {
595 if (ptr == PCI_CAP_NEXT_PTR_NULL) {
596 /* PM capability not found */
597 return;
598 }
599 if (pci_config_get8(pcih, ptr + PCI_CAP_ID) == PCI_CAP_ID_PM) {
600 /* found it */
601 break;
602 }
603 ptr = pci_config_get8(pcih, ptr + PCI_CAP_NEXT_PTR);
604 }
605
606 /* if we got here, then got valid PMCSR pointer */
607 ptr += PCI_PMCSR;
608
609 /* check to see if we are already in state D0 */
610 pmcsr = pci_config_get16(pcih, ptr);
611 if ((pmcsr & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
612
613 /* D3hot (or any other state) -> D0 */
614 pmcsr &= ~PCI_PMCSR_STATE_MASK;
615 pmcsr |= PCI_PMCSR_D0;
616 pci_config_put16(pcih, ptr, pmcsr);
617 }
618
619 /*
620 * Wait for it to power up - PCI spec says 10 ms is enough.
621 * We double it. Note that no locks are held when this routine
622 * is called, so we can sleep (we are in attach context only).
623 *
624 * We do this delay even if already powerd up, just to make
625 * sure we aren't seeing something that *just* transitioned
626 * into D0 state.
627 */
628 delay(drv_usectohz(TS_20MS));
629
630 /* clear PME# flag */
631 pmcsr = pci_config_get16(pcih, ptr);
632 pci_config_put16(pcih, ptr, pmcsr | PCI_PMCSR_PME_STAT);
633 }
634
635 /*
636 * audiots_chip_init()
637 *
638 * Description:
639 * Initialize the audio core.
640 *
641 * Arguments:
642 * audiots_state_t *state The device's state structure
643 */
644 static void
645 audiots_chip_init(audiots_state_t *state)
646 {
647 ddi_acc_handle_t handle = state->ts_acch;
648 audiots_regs_t *regs = state->ts_regs;
649 int str;
650
651 /* start with all interrupts & dma channels disabled */
652 ddi_put32(handle, ®s->aud_regs.ap_stop, TS_ALL_DMA_ENGINES);
653 ddi_put32(handle, ®s->aud_regs.ap_ainten, TS_ALL_DMA_OFF);
654
655 /* set global music and wave volume to 0dB */
656 ddi_put32(handle, ®s->aud_regs.ap_volume, 0x0);
657
658 /* enable end interrupts for all channels. */
659 ddi_put32(handle, ®s->aud_regs.ap_cir_gc, AP_CIR_GC_ENDLP_IE);
660
661 /* for each stream, set gain and vol settings */
662 for (str = 0; str < TS_MAX_HW_CHANNELS; str++) {
663 /*
664 * Set volume to all off, 1st left and then right.
665 * These are never changed, so we don't have to save them.
666 */
667 ddi_put16(handle,
668 ®s->aud_ram[str].eram.eram_gvsel_pan_vol,
669 (ERAM_WAVE_VOL|ERAM_PAN_LEFT|ERAM_PAN_0dB|
670 ERAM_VOL_MAX_ATTEN));
671 ddi_put16(handle,
672 ®s->aud_ram[str].eram.eram_gvsel_pan_vol,
673 (ERAM_WAVE_VOL|ERAM_PAN_RIGHT|ERAM_PAN_0dB|
674 ERAM_VOL_MAX_ATTEN));
675
676 /*
677 * The envelope engine *MUST* remain in still mode (off).
678 * Otherwise bad things like gain randomly disappearing might
679 * happen. See bug #4332773.
680 */
681
682 ddi_put32(handle, ®s->aud_ram[str].eram.eram_ebuf1,
683 ERAM_EBUF_STILL);
684 ddi_put32(handle, ®s->aud_ram[str].eram.eram_ebuf2,
685 ERAM_EBUF_STILL);
686
687 /* program the initial eram and aram rate */
688 ddi_put16(handle, ®s->aud_ram[str].aram.aram_delta,
689 1 << TS_SRC_SHIFT);
690 ddi_put16(handle, ®s->aud_ram[str].eram.eram_ctrl_ec,
691 ERAM_16_BITS | ERAM_STEREO | ERAM_LOOP_MODE |
692 ERAM_SIGNED_PCM);
693 }
694
695 /* program channel 31 for record */
696 OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_global_control,
697 (AP_CLOGAL_CTRL_E_PCMIN_CH31|AP_CLOGAL_CTRL_PCM_OUT_AC97|
698 AP_CLOGAL_CTRL_MMC_FROM_MIXER|AP_CLOGAL_CTRL_PCM_OUT_TO_AC97));
699
700 /* do a warm reset, which powers up the Codec */
701 OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl,
702 AP_SCTRL_WRST_CODEC);
703 drv_usecwait(2);
704 AND_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl,
705 ~AP_SCTRL_WRST_CODEC);
706
707 /* do a warm reset via the Codec, yes, I'm being paranoid! */
708 audiots_set_ac97(state, AC97_RESET_REGISTER, 0);
709
710 /* Make sure the Codec is powered up. */
711 int i = TS_WAIT_CNT;
712 while ((audiots_get_ac97(state, AC97_POWERDOWN_CTRL_STAT_REGISTER) &
713 PCSR_POWERD_UP) != PCSR_POWERD_UP && i--) {
714 drv_usecwait(1);
715 }
716
717 }
718
719 /*
720 * audiots_get_ac97()
721 *
722 * Description:
723 * Get the value in the specified AC-97 Codec register. There is a
724 * bug in silicon which forces us to do multiple reads of the Codec's
725 * register. This algorithm was provided by T2 and is heuristic in
726 * nature. Unfortunately we have no guarantees that the real answer
727 * isn't 0x0000, which is what we get when a read fails. So we loop
728 * TS_LOOP_CNT times before we give up. We just have to hope this is
729 * sufficient to give us the correct value.
730 *
731 * Arguments:
732 * audiots_state_t *state The device's state structure
733 * int reg AC-97 register number
734 *
735 * Returns:
736 * unsigned short The value in the specified register
737 */
738 static uint16_t
739 audiots_get_ac97(void *arg, uint8_t reg)
740 {
741 audiots_state_t *state = arg;
742 ddi_acc_handle_t handle = state->ts_acch;
743 uint16_t *data;
744 int count;
745 int delay;
746 uint16_t first;
747 uint16_t next;
748
749 if (state->ts_revid == AC_REV_ID1) {
750 data = &state->ts_regs->aud_regs.ap_acrd_35D_data;
751 } else {
752 data = &state->ts_regs->aud_regs.ap_acrdwr_data;
753 }
754
755 /* make sure the register is good */
756 reg &= AP_ACRD_INDEX_MASK;
757 for (count = TS_LOOP_CNT; count--; ) {
758 if ((first = audiots_read_ac97(state, reg)) != 0) {
759 next = first;
760 break;
761 }
762
763 delay = TS_DELAY_CNT;
764 while (delay--) {
765 (void) ddi_get16(handle, data);
766 }
767
768 if ((next = audiots_read_ac97(state, reg)) != 0) {
769 break;
770 }
771 }
772
773 /*
774 * Arggg, if you let the next read happen too soon then it fails.
775 * 12 usec fails, 13 usec succeeds. So set it to 20 for safety.
776 */
777 drv_usecwait(TS_20US);
778
779 return (next);
780
781 }
782
783 /*
784 * audiots_init_state()
785 *
786 * Description:
787 * This routine initializes the audio driver's state structure.
788 * This includes reading the properties.
789 *
790 * CAUTION: This routine cannot allocate resources, unless it frees
791 * them before returning for an error. Also, error_destroy:
792 * in audiots_attach() would need to be fixed as well.
793 *
794 * NOTE: birdsnest supports CD ROM input. We check for the cdrom
795 * property. If there we turn it on.
796 *
797 * Arguments:
798 * audiots_state_t *state The device's state structure
799 * dev_info_t *dip Pointer to the device's dev_info struct
800 *
801 * Returns:
802 * DDI_SUCCESS State structure initialized
803 * DDI_FAILURE State structure not initialized
804 */
805 static int
806 audiots_init_state(audiots_state_t *state, dev_info_t *dip)
807 {
808 state->ts_ac97 = ac97_alloc(dip, audiots_get_ac97,
809 audiots_set_ac97, state);
810
811 if (state->ts_ac97 == NULL) {
812 return (DDI_FAILURE);
813 }
814
815 /* save the device info pointer */
816 state->ts_dip = dip;
817
818 for (int i = 0; i < TS_NUM_PORTS; i++) {
819 if (audiots_alloc_port(state, i) != DDI_SUCCESS) {
820 return (DDI_FAILURE);
821 }
822 }
823
824 return (DDI_SUCCESS);
825
826 }
827
828 /*
829 * audiots_map_regs()
830 *
831 * Description:
832 * This routine maps the registers in.
833 *
834 * Once the config space registers are mapped in we determine if the
835 * audio core may be power managed. It should, but if it doesn't,
836 * then trying to may cause the core to hang.
837 *
838 * CAUTION: Make sure all errors call audio_dev_warn().
839 *
840 * Arguments:
841 * dev_info_t *dip Pointer to the device's devinfo
842 * audiots_state_t *state The device's state structure
843 * Returns:
844 * DDI_SUCCESS Registers successfully mapped
845 * DDI_FAILURE Registers not successfully mapped
846 */
847 static int
848 audiots_map_regs(dev_info_t *dip, audiots_state_t *state)
849 {
850 char rev[16];
851 char *name;
852
853 /* map in the registers, the config and memory mapped registers */
854 if (pci_config_setup(dip, &state->ts_pcih) != DDI_SUCCESS) {
855 audio_dev_warn(state->ts_adev,
856 "unable to map PCI configuration space");
857 return (DDI_FAILURE);
858 }
859
860 /* Read the Audio Controller's vendor, device, and revision IDs */
861 state->ts_devid =
862 (pci_config_get16(state->ts_pcih, PCI_CONF_VENID) << 16) |
863 pci_config_get16(state->ts_pcih, PCI_CONF_DEVID);
864 state->ts_revid = pci_config_get8(state->ts_pcih, PCI_CONF_REVID);
865
866 if (ddi_regs_map_setup(dip, TS_MEM_MAPPED_REGS,
867 (caddr_t *)&state->ts_regs, 0, 0, &ts_regs_attr, &state->ts_acch) !=
868 DDI_SUCCESS) {
869 audio_dev_warn(state->ts_adev,
870 "unable to map PCI device registers");
871 return (DDI_FAILURE);
872 }
873
874 switch (state->ts_devid) {
875 case 0x10b95451:
876 name = "ALI M5451";
877 break;
878 default:
879 name = "audiots";
880 break;
881 }
882 (void) snprintf(rev, sizeof (rev), "Rev %x", state->ts_revid);
883 audio_dev_set_description(state->ts_adev, name);
884 audio_dev_set_version(state->ts_adev, rev);
885
886 return (DDI_SUCCESS);
887 }
888
889 /*
890 * audiots_alloc_port()
891 *
892 * Description:
893 * This routine allocates the DMA handles and the memory for the
894 * DMA engines to use. It then binds each of the buffers to its
895 * respective handle, getting a DMA cookie.
896 *
897 * NOTE: All of the ddi_dma_... routines sleep if they cannot get
898 * memory. This means these calls should always succeed.
899 *
900 * NOTE: ddi_dma_alloc_handle() attempts to use the full 4 GB DMA address
901 * range. This is to work around Southbridge rev E/G OBP issues.
902 * (See Grover OBP note above)
903 *
904 * CAUTION: Make sure all errors call audio_dev_warn().
905 *
906 * Arguments:
907 * audiots_port_t *state The port structure for a device stream
908 * int num The port number
909 *
910 * Returns:
911 * DDI_SUCCESS DMA resources mapped
912 * DDI_FAILURE DMA resources not successfully mapped
913 */
914 int
915 audiots_alloc_port(audiots_state_t *state, int num)
916 {
917 audiots_port_t *port;
918 dev_info_t *dip = state->ts_dip;
919 audio_dev_t *adev = state->ts_adev;
920 int dir;
921 unsigned caps;
922 ddi_dma_cookie_t cookie;
923 unsigned count;
924 int rc;
925 ddi_acc_handle_t regsh = state->ts_acch;
926 uint32_t *gcptr = &state->ts_regs->aud_regs.ap_cir_gc;
927
928 port = kmem_zalloc(sizeof (*port), KM_SLEEP);
929 state->ts_ports[num] = port;
930 port->tp_num = num;
931 port->tp_state = state;
932 port->tp_rate = TS_RATE;
933
934 if (num == TS_INPUT_PORT) {
935 dir = DDI_DMA_READ;
936 caps = ENGINE_INPUT_CAP;
937 port->tp_dma_stream = 31;
938 port->tp_sync_dir = DDI_DMA_SYNC_FORKERNEL;
939 } else {
940 dir = DDI_DMA_WRITE;
941 caps = ENGINE_OUTPUT_CAP;
942 port->tp_dma_stream = 0;
943 port->tp_sync_dir = DDI_DMA_SYNC_FORDEV;
944 }
945
946 port->tp_dma_mask = (1U << port->tp_dma_stream);
947 port->tp_nframes = 4096;
948 port->tp_size = port->tp_nframes * TS_FRAMESZ;
949
950 /* allocate dma handle */
951 rc = ddi_dma_alloc_handle(dip, &audiots_attr, DDI_DMA_SLEEP,
952 NULL, &port->tp_dmah);
953 if (rc != DDI_SUCCESS) {
954 audio_dev_warn(adev, "ddi_dma_alloc_handle failed: %d", rc);
955 return (DDI_FAILURE);
956 }
957 /* allocate DMA buffer */
958 rc = ddi_dma_mem_alloc(port->tp_dmah, port->tp_size, &ts_acc_attr,
959 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &port->tp_kaddr,
960 &port->tp_size, &port->tp_acch);
961 if (rc == DDI_FAILURE) {
962 audio_dev_warn(adev, "dma_mem_alloc failed");
963 return (DDI_FAILURE);
964 }
965
966 /* bind DMA buffer */
967 rc = ddi_dma_addr_bind_handle(port->tp_dmah, NULL,
968 port->tp_kaddr, port->tp_size, dir|DDI_DMA_CONSISTENT,
969 DDI_DMA_SLEEP, NULL, &cookie, &count);
970 if (rc != DDI_DMA_MAPPED) {
971 audio_dev_warn(adev,
972 "ddi_dma_addr_bind_handle failed: %d", rc);
973 return (DDI_FAILURE);
974 }
975 ASSERT(count == 1);
976
977 port->tp_paddr = cookie.dmac_address;
978 if ((unsigned)port->tp_paddr & 0x80000000U) {
979 ddi_put32(regsh, gcptr,
980 ddi_get32(regsh, gcptr) | AP_CIR_GC_SYS_MEM_4G_ENABLE);
981 } else {
982 ddi_put32(regsh, gcptr,
983 ddi_get32(regsh, gcptr) & ~(AP_CIR_GC_SYS_MEM_4G_ENABLE));
984 }
985 port->tp_engine = audio_engine_alloc(&audiots_engine_ops, caps);
986 if (port->tp_engine == NULL) {
987 audio_dev_warn(adev, "audio_engine_alloc failed");
988 return (DDI_FAILURE);
989 }
990
991 audio_engine_set_private(port->tp_engine, port);
992 audio_dev_add_engine(adev, port->tp_engine);
993
994 return (DDI_SUCCESS);
995 }
996
997 /*
998 * audiots_read_ac97()
999 *
1000 * Description:
1001 * This routine actually reads the AC-97 Codec's register. It may
1002 * be called several times to succeed.
1003 *
1004 * NOTE:
1005 * Revision M1535D B1-C of the ALI SouthBridge includes a workaround for
1006 * the broken busy flag. Resetting the busy flag requires a software tweak
1007 * to go with the worked around hardware. When we detect failure, we make
1008 * 10 attempts to reset the chip before we fail. This should reset the new
1009 * SB systems. On all SB systems, this will increse the read delay
1010 * slightly, but shouldn't bother it otherwise.
1011 *
1012 * Arguments:
1013 * audiots_state_t *state The device's state structure
1014 * int reg AC-97 register number
1015 *
1016 * Returns:
1017 * unsigned short The value in the specified register
1018 */
1019 static uint16_t
1020 audiots_read_ac97(audiots_state_t *state, int reg)
1021 {
1022 ddi_acc_handle_t acch = state->ts_acch;
1023 uint16_t *addr;
1024 uint16_t *data;
1025 uint32_t *stimer = &state->ts_regs->aud_regs.ap_stimer;
1026 uint32_t chk1;
1027 uint32_t chk2;
1028 int resets = 0;
1029 int i;
1030
1031 if (state->ts_revid == AC_REV_ID1) {
1032 addr = &state->ts_regs->aud_regs.ap_acrd_35D_reg;
1033 data = &state->ts_regs->aud_regs.ap_acrd_35D_data;
1034 } else {
1035 addr = &state->ts_regs->aud_regs.ap_acrdwr_reg;
1036 data = &state->ts_regs->aud_regs.ap_acrdwr_data;
1037 }
1038
1039 first_read:
1040 /* wait for ready to send read request */
1041 for (i = 0; i < TS_READ_TRIES; i++) {
1042 if (!(ddi_get16(acch, addr) & AP_ACRD_R_READ_BUSY)) {
1043 break;
1044 }
1045 /* don't beat on the bus */
1046 drv_usecwait(1);
1047 }
1048 if (i >= TS_READ_TRIES) {
1049 if (resets < TS_RESET_TRIES) {
1050 /* Attempt to reset */
1051 drv_usecwait(TS_20US);
1052 ddi_put16(acch, addr, TS_SB_RESET);
1053 resets++;
1054 goto first_read;
1055 } else {
1056 state->ts_flags |= TS_AUDIO_READ_FAILED;
1057 if (!(state->ts_flags & TS_READ_FAILURE_PRINTED)) {
1058 ddi_dev_report_fault(state->ts_dip,
1059 DDI_SERVICE_LOST, DDI_DEVICE_FAULT,
1060 "Unable to communicate with AC97 CODEC");
1061 audio_dev_warn(state->ts_adev,
1062 "The audio AC97 register has timed out.");
1063 audio_dev_warn(state->ts_adev,
1064 "Audio is now disabled.");
1065 audio_dev_warn(state->ts_adev,
1066 "Please reboot to restore audio.");
1067
1068 /* Don't flood the console */
1069 state->ts_flags |= TS_READ_FAILURE_PRINTED;
1070 }
1071 }
1072 return (0);
1073 }
1074
1075 /* program the register to read */
1076 ddi_put16(acch, addr, (reg|AP_ACRD_W_PRIMARY_CODEC|
1077 AP_ACRD_W_READ_MIXER_REG|AP_ACRD_W_AUDIO_READ_REQ&
1078 (~AP_ACWR_W_SELECT_WRITE)));
1079
1080 /* hardware bug work around */
1081 chk1 = ddi_get32(acch, stimer);
1082 chk2 = ddi_get32(acch, stimer);
1083 i = TS_WAIT_CNT;
1084 while (chk1 == chk2 && i) {
1085 chk2 = ddi_get32(acch, stimer);
1086 i--;
1087 }
1088 OR_SET_SHORT(acch, addr, AP_ACRD_W_READ_MIXER_REG);
1089 resets = 0;
1090
1091 second_read:
1092 /* wait again for read to send read request */
1093 for (i = 0; i < TS_READ_TRIES; i++) {
1094 if (!(ddi_get16(acch, addr) & AP_ACRD_R_READ_BUSY)) {
1095 break;
1096 }
1097 /* don't beat on the bus */
1098 drv_usecwait(1);
1099 }
1100 if (i >= TS_READ_TRIES) {
1101 if (resets < TS_RESET_TRIES) {
1102 /* Attempt to reset */
1103 drv_usecwait(TS_20US);
1104 ddi_put16(acch, addr, TS_SB_RESET);
1105 resets++;
1106 goto second_read;
1107 } else {
1108 state->ts_flags |= TS_AUDIO_READ_FAILED;
1109 if (!(state->ts_flags & TS_READ_FAILURE_PRINTED)) {
1110 ddi_dev_report_fault(state->ts_dip,
1111 DDI_SERVICE_LOST, DDI_DEVICE_FAULT,
1112 "Unable to communicate with AC97 CODEC");
1113 audio_dev_warn(state->ts_adev,
1114 "The audio AC97 register has timed out.");
1115 audio_dev_warn(state->ts_adev,
1116 "Audio is now disabled.");
1117 audio_dev_warn(state->ts_adev,
1118 "Please reboot to restore audio.");
1119
1120 /* Don't flood the console */
1121 state->ts_flags |= TS_READ_FAILURE_PRINTED;
1122 }
1123 }
1124 return (0);
1125 }
1126
1127 return (ddi_get16(acch, data));
1128
1129 } /* audiots_read_ac97() */
1130
1131 /*
1132 * audiots_set_ac97()
1133 *
1134 * Description:
1135 * Set the value in the specified AC-97 Codec register. Just like
1136 * reading the AC-97 Codec, it is possible there is a problem writing
1137 * it as well. So we loop.
1138 *
1139 * Arguments:
1140 * audiots_state_t *state The device's state structure
1141 * int reg AC-97 register number
1142 * uint16_t value The value to write
1143 */
1144 static void
1145 audiots_set_ac97(void *arg, uint8_t reg8, uint16_t data)
1146 {
1147 audiots_state_t *state = arg;
1148 ddi_acc_handle_t handle = state->ts_acch;
1149 uint16_t *data_addr = &state->ts_regs->aud_regs.ap_acrdwr_data;
1150 uint16_t *reg_addr = &state->ts_regs->aud_regs.ap_acrdwr_reg;
1151 int count;
1152 int i;
1153 uint16_t tmp_short;
1154 uint16_t reg = reg8;
1155
1156 reg &= AP_ACWR_INDEX_MASK;
1157
1158 /* Don't touch the reserved bits on the pre 35D+ SouthBridge */
1159 if (state->ts_revid == AC_REV_ID1) {
1160 reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG;
1161 } else {
1162 reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG|
1163 AP_ACWR_W_SELECT_WRITE;
1164 }
1165
1166 for (count = TS_LOOP_CNT; count--; ) {
1167 /* wait for ready to write */
1168 for (i = 0; i < TS_WAIT_CNT; i++) {
1169 if (!(ddi_get16(handle, reg_addr) &
1170 AP_ACWR_R_WRITE_BUSY)) {
1171 /* ready to write */
1172 ddi_put16(handle, reg_addr, reg);
1173
1174 /* Write the data */
1175 ddi_put16(handle, data_addr, data);
1176 break;
1177 }
1178 }
1179 if (i >= TS_WAIT_CNT) {
1180 /* try again */
1181 continue;
1182 }
1183
1184 /* wait for write to complete */
1185 for (i = 0; i < TS_WAIT_CNT; i++) {
1186 if (!(ddi_get16(handle, reg_addr) &
1187 AP_ACWR_R_WRITE_BUSY)) {
1188 /* done writing */
1189 break;
1190 }
1191 }
1192
1193 /* verify the value written */
1194 tmp_short = audiots_get_ac97(state, reg8);
1195 if (data == tmp_short) {
1196 /* successfully loaded, so we can return */
1197 return;
1198 }
1199 }
1200
1201 } /* audiots_set_ac97() */
1202
1203 /*
1204 * audiots_open()
1205 *
1206 * Description:
1207 * Opens a DMA engine for use. Will also ensure the device is powered
1208 * up if not already done so.
1209 *
1210 * Arguments:
1211 * void *arg The DMA engine to set up
1212 * int flag Open flags
1213 * unsigned *nframesp Receives number of frames
1214 * caddr_t *bufp Receives kernel data buffer
1215 *
1216 * Returns:
1217 * 0 on success
1218 * errno on failure
1219 */
1220 static int
1221 audiots_open(void *arg, int flag, unsigned *nframesp, caddr_t *bufp)
1222 {
1223 audiots_port_t *port = arg;
1224
1225 _NOTE(ARGUNUSED(flag));
1226
1227 port->tp_count = 0;
1228 port->tp_cso = 0;
1229 *nframesp = port->tp_nframes;
1230 *bufp = port->tp_kaddr;
1231
1232 return (0);
1233 }
1234
1235 /*
1236 * audiots_close()
1237 *
1238 * Description:
1239 * Closes an audio DMA engine that was previously opened. Since
1240 * nobody is using it, we could take this opportunity to possibly power
1241 * down the entire device, or at least the DMA engine.
1242 *
1243 * Arguments:
1244 * void *arg The DMA engine to shut down
1245 */
1246 static void
1247 audiots_close(void *arg)
1248 {
1249 _NOTE(ARGUNUSED(arg));
1250 }
1251
1252 /*
1253 * audiots_stop()
1254 *
1255 * Description:
1256 * This is called by the framework to stop a port that is
1257 * transferring data.
1258 *
1259 * Arguments:
1260 * void *arg The DMA engine to stop
1261 */
1262 static void
1263 audiots_stop(void *arg)
1264 {
1265 audiots_port_t *port = arg;
1266 audiots_state_t *state = port->tp_state;
1267
1268 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop,
1269 port->tp_dma_mask);
1270 }
1271
1272 /*
1273 * audiots_start()
1274 *
1275 * Description:
1276 * This is called by the framework to start a port transferring data.
1277 *
1278 * Arguments:
1279 * void *arg The DMA engine to start
1280 *
1281 * Returns:
1282 * 0 on success (never fails, errno if it did)
1283 */
1284 static int
1285 audiots_start(void *arg)
1286 {
1287 audiots_port_t *port = arg;
1288 audiots_state_t *state = port->tp_state;
1289 ddi_acc_handle_t handle = state->ts_acch;
1290 audiots_regs_t *regs = state->ts_regs;
1291 audiots_aram_t *aram;
1292 audiots_eram_t *eram;
1293 unsigned delta;
1294 uint16_t ctrl;
1295 uint16_t gvsel;
1296 uint16_t eso;
1297
1298 aram = ®s->aud_ram[port->tp_dma_stream].aram;
1299 eram = ®s->aud_ram[port->tp_dma_stream].eram;
1300
1301 port->tp_cso = 0;
1302
1303 gvsel = ERAM_WAVE_VOL | ERAM_PAN_0dB | ERAM_VOL_DEFAULT;
1304 ctrl = ERAM_16_BITS | ERAM_STEREO | ERAM_LOOP_MODE | ERAM_SIGNED_PCM;
1305
1306 delta = (port->tp_rate << TS_SRC_SHIFT) / TS_RATE;
1307
1308 if (port->tp_num == TS_INPUT_PORT) {
1309 delta = (TS_RATE << TS_SRC_SHIFT) / port->tp_rate;
1310 }
1311 eso = port->tp_nframes - 1;
1312
1313 /* program the sample rate */
1314 ddi_put16(handle, &aram->aram_delta, (uint16_t)delta);
1315
1316 /* program the precision, number of channels and loop mode */
1317 ddi_put16(handle, &eram->eram_ctrl_ec, ctrl);
1318
1319 /* program the volume settings */
1320 ddi_put16(handle, &eram->eram_gvsel_pan_vol, gvsel);
1321
1322 /* set ALPHA and FMS to 0 */
1323 ddi_put16(handle, &aram->aram_alpha_fms, 0x0);
1324
1325 /* set CSO to 0 */
1326 ddi_put16(handle, &aram->aram_cso, 0x0);
1327
1328 /* set LBA */
1329 ddi_put32(handle, &aram->aram_cptr_lba,
1330 port->tp_paddr & ARAM_LBA_MASK);
1331
1332 /* set ESO */
1333 ddi_put16(handle, &aram->aram_eso, eso);
1334
1335 /* stop the DMA engines */
1336 ddi_put32(handle, ®s->aud_regs.ap_stop, port->tp_dma_mask);
1337
1338 /* now make sure it starts playing */
1339 ddi_put32(handle, ®s->aud_regs.ap_start, port->tp_dma_mask);
1340
1341 return (0);
1342 }
1343
1344 /*
1345 * audiots_chinfo()
1346 *
1347 * Description:
1348 * This is called by the framework to query the channel offsets
1349 * and ordering.
1350 *
1351 * Arguments:
1352 * void *arg The DMA engine to query
1353 * int chan Channel number.
1354 * unsigned *offset Starting offset of channel.
1355 * unsigned *incr Increment (in samples) between frames.
1356 *
1357 * Returns:
1358 * 0 indicating rate array is range instead of enumeration
1359 */
1360
1361 static void
1362 audiots_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr)
1363 {
1364 _NOTE(ARGUNUSED(arg));
1365 *offset = chan;
1366 *incr = 2;
1367 }
1368
1369 /*
1370 * audiots_format()
1371 *
1372 * Description:
1373 * Called by the framework to query the format for the device.
1374 *
1375 * Arguments:
1376 * void *arg The DMA engine to query
1377 *
1378 * Returns:
1379 * AUDIO_FORMAT_S16_LE.
1380 */
1381 static int
1382 audiots_format(void *arg)
1383 {
1384 _NOTE(ARGUNUSED(arg));
1385
1386 return (AUDIO_FORMAT_S16_LE);
1387 }
1388
1389
1390 /*
1391 * audiots_channels()
1392 *
1393 * Description:
1394 * Called by the framework to query the channnels for the device.
1395 *
1396 * Arguments:
1397 * void *arg The DMA engine to query
1398 *
1399 * Returns:
1400 * 2 (Stereo).
1401 */
1402 static int
1403 audiots_channels(void *arg)
1404 {
1405 _NOTE(ARGUNUSED(arg));
1406
1407 return (2);
1408 }
1409
1410 /*
1411 * audiots_rate()
1412 *
1413 * Description:
1414 * Called by the framework to query the sample rates for the device.
1415 *
1416 * Arguments:
1417 * void *arg The DMA engine to query
1418 *
1419 * Returns:
1420 * Sample rate in HZ (always 48000).
1421 */
1422 static int
1423 audiots_rate(void *arg)
1424 {
1425 audiots_port_t *port = arg;
1426
1427 return (port->tp_rate);
1428 }
1429
1430 /*
1431 * audiots_count()
1432 *
1433 * Description:
1434 * This is called by the framework to get the engine's frame counter
1435 *
1436 * Arguments:
1437 * void *arg The DMA engine to query
1438 *
1439 * Returns:
1440 * frame count for current engine
1441 */
1442 static uint64_t
1443 audiots_count(void *arg)
1444 {
1445 audiots_port_t *port = arg;
1446 audiots_state_t *state = port->tp_state;
1447 uint64_t val;
1448 uint16_t cso;
1449 unsigned n;
1450
1451 cso = ddi_get16(state->ts_acch,
1452 &state->ts_regs->aud_ram[port->tp_dma_stream].aram.aram_cso);
1453
1454 n = (cso >= port->tp_cso) ?
1455 cso - port->tp_cso :
1456 cso + port->tp_nframes - port->tp_cso;
1457
1458 port->tp_cso = cso;
1459 port->tp_count += n;
1460 val = port->tp_count;
1461
1462 return (val);
1463 }
1464
1465 /*
1466 * audiots_sync()
1467 *
1468 * Description:
1469 * This is called by the framework to synchronize DMA caches.
1470 *
1471 * Arguments:
1472 * void *arg The DMA engine to sync
1473 */
1474 static void
1475 audiots_sync(void *arg, unsigned nframes)
1476 {
1477 audiots_port_t *port = arg;
1478 _NOTE(ARGUNUSED(nframes));
1479
1480 (void) ddi_dma_sync(port->tp_dmah, 0, 0, port->tp_sync_dir);
1481 }
1482
1483 /*
1484 * audiots_stop_everything()
1485 *
1486 * Description:
1487 * This routine disables the address engine interrupt for all 32 DMA
1488 * engines. Just to be sure, it then explicitly issues a stop command to
1489 * the address engine and envelope engines for all 32 channels.
1490 *
1491 * NOTE:
1492 *
1493 * There is a hardware bug that generates a spurious interrupt
1494 * when the DMA engines are stopped. It's not consistent - it
1495 * happens every 1 out of 6 stops or so. It will show up as a
1496 * record interrupt. The problem is that once the driver is
1497 * detached or if the system goes into low power mode, nobody
1498 * will service that interrupt. The system will eventually become
1499 * unusable.
1500 *
1501 * Arguments:
1502 * audiots_state_t *state The device's state structure
1503 */
1504 static void
1505 audiots_stop_everything(audiots_state_t *state)
1506 {
1507 if (state->ts_acch == NULL)
1508 return;
1509
1510 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten,
1511 TS_ALL_DMA_OFF);
1512
1513 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop,
1514 TS_ALL_DMA_ENGINES);
1515
1516 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_aint,
1517 TS_ALL_DMA_ENGINES);
1518 }
1519
1520 /*
1521 * audiots_free_port()
1522 *
1523 * Description:
1524 * This routine unbinds the DMA cookies, frees the DMA buffers,
1525 * deallocates the DMA handles.
1526 *
1527 * Arguments:
1528 * audiots_port_t *port The port structure for a device stream.
1529 */
1530 void
1531 audiots_free_port(audiots_port_t *port)
1532 {
1533 if (port == NULL)
1534 return;
1535
1536 if (port->tp_engine) {
1537 audio_dev_remove_engine(port->tp_state->ts_adev,
1538 port->tp_engine);
1539 audio_engine_free(port->tp_engine);
1540 }
1541 if (port->tp_paddr) {
1542 (void) ddi_dma_unbind_handle(port->tp_dmah);
1543 }
1544 if (port->tp_acch) {
1545 ddi_dma_mem_free(&port->tp_acch);
1546 }
1547 if (port->tp_dmah) {
1548 ddi_dma_free_handle(&port->tp_dmah);
1549 }
1550 kmem_free(port, sizeof (*port));
1551 }
1552
1553 /*
1554 * audiots_destroy()
1555 *
1556 * Description:
1557 * This routine releases all resources held by the device instance,
1558 * as part of either detach or a failure in attach.
1559 *
1560 * Arguments:
1561 * audiots_state_t *state The device soft state.
1562 */
1563 void
1564 audiots_destroy(audiots_state_t *state)
1565 {
1566 audiots_stop_everything(state);
1567
1568 for (int i = 0; i < TS_NUM_PORTS; i++)
1569 audiots_free_port(state->ts_ports[i]);
1570
1571 if (state->ts_acch)
1572 ddi_regs_map_free(&state->ts_acch);
1573
1574 if (state->ts_pcih)
1575 pci_config_teardown(&state->ts_pcih);
1576
1577 if (state->ts_ac97)
1578 ac97_free(state->ts_ac97);
1579
1580 if (state->ts_adev)
1581 audio_dev_free(state->ts_adev);
1582
1583 ddi_soft_state_free(audiots_statep, ddi_get_instance(state->ts_dip));
1584 }