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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/common/io/audio/drv/audio810/audio810.c
+++ new/usr/src/uts/common/io/audio/drv/audio810/audio810.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26
27 27 /*
28 28 * audio810 Audio Driver
29 29 *
30 30 * The driver is primarily targeted at providing audio support for the
31 31 * Intel ICHx family of AC'97 controllers and compatible parts (such
32 32 * as those from nVidia and AMD.)
33 33 *
34 34 * These audio parts have independent channels for PCM in, PCM out,
35 35 * mic in, and sometimes modem in, and modem out. The AC'97
36 36 * controller is a PCI bus master with scatter/gather support. Each
37 37 * channel has a DMA engine. Currently, we use only the PCM in and PCM
38 38 * out channels. Each DMA engine uses one buffer descriptor list. And
39 39 * the buffer descriptor list is an array of up to 32 entries, each of
40 40 * which describes a data buffer. Each entry contains a pointer to a
41 41 * data buffer, control bits, and the length of the buffer being
42 42 * pointed to, where the length is expressed as the number of
43 43 * samples. This, combined with the 16-bit sample size, gives the
44 44 * actual physical length of the buffer.
45 45 *
46 46 * A workaround for the AD1980 and AD1985 codec:
47 47 * Most vendors connect the surr-out of the codecs to the line-out jack.
48 48 * So far we haven't found which vendors don't do that. So we assume that
49 49 * all vendors swap the surr-out and the line-out outputs. So we need swap
50 50 * the two outputs. But we still internally process the
51 51 * "ad198x-swap-output" property. If someday some vendors do not swap the
52 52 * outputs, we would set "ad198x-swap-output = 0" in the
53 53 * /kernel/drv/audio810.conf file, and unload and reload the audio810
54 54 * driver (or reboot).
55 55 *
56 56 * NOTE:
57 57 * This driver depends on the drv/audio and misc/ac97
58 58 * modules being loaded first.
59 59 *
60 60 * The audio framework guarantees that our entry points are exclusive
61 61 * with suspend and resume. This includes data flow and control entry
62 62 * points alike.
63 63 *
64 64 * The audio framework guarantees that only one control is being
65 65 * accessed on any given audio device at a time.
66 66 *
67 67 * The audio framework guarantees that entry points are themselves
68 68 * serialized for a given engine.
69 69 *
70 70 * We have no interrupt routine or other internal asynchronous routines.
71 71 *
72 72 * Our device uses completely separate registers for each engine,
73 73 * except for the start/stop registers, which are implemented in a
74 74 * manner that allows for them to be accessed concurrently safely from
75 75 * different threads.
76 76 *
77 77 * Hence, it turns out that we simply don't need any locking in this
78 78 * driver.
79 79 */
80 80 #include <sys/types.h>
81 81 #include <sys/modctl.h>
82 82 #include <sys/kmem.h>
83 83 #include <sys/conf.h>
84 84 #include <sys/ddi.h>
85 85 #include <sys/sunddi.h>
86 86 #include <sys/pci.h>
87 87 #include <sys/note.h>
88 88 #include <sys/audio/audio_driver.h>
89 89 #include <sys/audio/ac97.h>
90 90 #include "audio810.h"
91 91
92 92 /*
93 93 * Module linkage routines for the kernel
94 94 */
95 95 static int audio810_ddi_attach(dev_info_t *, ddi_attach_cmd_t);
96 96 static int audio810_ddi_detach(dev_info_t *, ddi_detach_cmd_t);
97 97 static int audio810_ddi_quiesce(dev_info_t *);
98 98
99 99 /*
100 100 * Entry point routine prototypes
101 101 */
102 102 static int audio810_open(void *, int, unsigned *, caddr_t *);
103 103 static void audio810_close(void *);
104 104 static int audio810_start(void *);
105 105 static void audio810_stop(void *);
106 106 static int audio810_format(void *);
107 107 static int audio810_channels(void *);
108 108 static int audio810_rate(void *);
109 109 static uint64_t audio810_count(void *);
110 110 static void audio810_sync(void *, unsigned);
111 111 static unsigned audio810_playahead(void *);
112 112
113 113 static audio_engine_ops_t audio810_engine_ops = {
114 114 AUDIO_ENGINE_VERSION,
115 115 audio810_open,
116 116 audio810_close,
117 117 audio810_start,
118 118 audio810_stop,
119 119 audio810_count,
120 120 audio810_format,
121 121 audio810_channels,
122 122 audio810_rate,
123 123 audio810_sync,
124 124 NULL,
125 125 NULL,
126 126 audio810_playahead
127 127 };
128 128
129 129 /*
130 130 * Local Routine Prototypes
131 131 */
132 132 static int audio810_attach(dev_info_t *);
133 133 static int audio810_resume(dev_info_t *);
134 134 static int audio810_detach(dev_info_t *);
135 135 static int audio810_suspend(dev_info_t *);
136 136
137 137 static int audio810_alloc_port(audio810_state_t *, int, uint8_t);
138 138 static int audio810_codec_sync(audio810_state_t *);
139 139 static void audio810_write_ac97(void *, uint8_t, uint16_t);
140 140 static uint16_t audio810_read_ac97(void *, uint8_t);
141 141 static int audio810_map_regs(dev_info_t *, audio810_state_t *);
142 142 static void audio810_unmap_regs(audio810_state_t *);
143 143 static void audio810_stop_dma(audio810_state_t *);
144 144 static int audio810_chip_init(audio810_state_t *);
145 145 static void audio810_set_channels(audio810_state_t *);
146 146 static void audio810_destroy(audio810_state_t *);
147 147
148 148 /*
149 149 * Global variables, but used only by this file.
150 150 */
151 151
152 152 /*
153 153 * DDI Structures
154 154 */
155 155
156 156 /* Device operations structure */
157 157 static struct dev_ops audio810_dev_ops = {
158 158 DEVO_REV, /* devo_rev */
159 159 0, /* devo_refcnt */
160 160 NULL, /* devo_getinfo */
161 161 nulldev, /* devo_identify - obsolete */
162 162 nulldev, /* devo_probe */
163 163 audio810_ddi_attach, /* devo_attach */
164 164 audio810_ddi_detach, /* devo_detach */
165 165 nodev, /* devo_reset */
166 166 NULL, /* devi_cb_ops */
167 167 NULL, /* devo_bus_ops */
168 168 NULL, /* devo_power */
169 169 audio810_ddi_quiesce, /* devo_quiesce */
170 170 };
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171 171
172 172 /* Linkage structure for loadable drivers */
173 173 static struct modldrv audio810_modldrv = {
174 174 &mod_driverops, /* drv_modops */
175 175 I810_MOD_NAME, /* drv_linkinfo */
176 176 &audio810_dev_ops, /* drv_dev_ops */
177 177 };
178 178
179 179 /* Module linkage structure */
180 180 static struct modlinkage audio810_modlinkage = {
181 - MODREV_1, /* ml_rev */
182 - (void *)&audio810_modldrv, /* ml_linkage */
183 - NULL /* NULL terminates the list */
181 + MODREV_1, /* ml_rev */
182 + { (void *)&audio810_modldrv, NULL } /* ml_linkage */
184 183 };
185 184
186 185 /*
187 186 * device access attributes for register mapping
188 187 */
189 188 static struct ddi_device_acc_attr dev_attr = {
190 189 DDI_DEVICE_ATTR_V0,
191 190 DDI_STRUCTURE_LE_ACC,
192 191 DDI_STRICTORDER_ACC
193 192 };
194 193
195 194 static struct ddi_device_acc_attr buf_attr = {
196 195 DDI_DEVICE_ATTR_V0,
197 196 DDI_STRUCTURE_LE_ACC,
198 197 DDI_STRICTORDER_ACC
199 198 };
200 199
201 200 /*
202 201 * DMA attributes of buffer descriptor list
203 202 */
204 203 static ddi_dma_attr_t bdlist_dma_attr = {
205 204 DMA_ATTR_V0, /* version */
206 205 0, /* addr_lo */
207 206 0xffffffff, /* addr_hi */
208 207 0x0000ffff, /* count_max */
209 208 8, /* align, BDL must be aligned on a 8-byte boundary */
210 209 0x3c, /* burstsize */
211 210 8, /* minxfer, set to the size of a BDlist entry */
212 211 0x0000ffff, /* maxxfer */
213 212 0x00000fff, /* seg, set to the RAM pagesize of intel platform */
214 213 1, /* sgllen, there's no scatter-gather list */
215 214 8, /* granular, set to the value of minxfer */
216 215 0 /* flags, use virtual address */
217 216 };
218 217
219 218 /*
220 219 * DMA attributes of buffers to be used to receive/send audio data
221 220 */
222 221 static ddi_dma_attr_t sample_buf_dma_attr = {
223 222 DMA_ATTR_V0,
224 223 0, /* addr_lo */
225 224 0xffffffff, /* addr_hi */
226 225 0x0001ffff, /* count_max */
227 226 4, /* align, data buffer is aligned on a 4-byte boundary */
228 227 0x3c, /* burstsize */
229 228 4, /* minxfer, set to the size of a sample data */
230 229 0x0001ffff, /* maxxfer */
231 230 0x0001ffff, /* seg */
232 231 1, /* sgllen, no scatter-gather */
233 232 4, /* granular, set to the value of minxfer */
234 233 0, /* flags, use virtual address */
235 234 };
236 235
237 236 /*
238 237 * _init()
239 238 *
240 239 * Description:
241 240 * Driver initialization, called when driver is first loaded.
242 241 * This is how access is initially given to all the static structures.
243 242 *
244 243 * Arguments:
245 244 * None
246 245 *
247 246 * Returns:
248 247 * mod_install() status, see mod_install(9f)
249 248 */
250 249 int
251 250 _init(void)
252 251 {
253 252 int error;
254 253
255 254 audio_init_ops(&audio810_dev_ops, I810_NAME);
256 255
257 256 if ((error = mod_install(&audio810_modlinkage)) != 0) {
258 257 audio_fini_ops(&audio810_dev_ops);
259 258 }
260 259
261 260 return (error);
262 261 }
263 262
264 263 /*
265 264 * _fini()
266 265 *
267 266 * Description:
268 267 * Module de-initialization, called when the driver is to be unloaded.
269 268 *
270 269 * Arguments:
271 270 * None
272 271 *
273 272 * Returns:
274 273 * mod_remove() status, see mod_remove(9f)
275 274 */
276 275 int
277 276 _fini(void)
278 277 {
279 278 int error;
280 279
281 280 if ((error = mod_remove(&audio810_modlinkage)) != 0) {
282 281 return (error);
283 282 }
284 283
285 284 /* clean up ops */
286 285 audio_fini_ops(&audio810_dev_ops);
287 286
288 287 return (0);
289 288 }
290 289
291 290 /*
292 291 * _info()
293 292 *
294 293 * Description:
295 294 * Module information, returns information about the driver.
296 295 *
297 296 * Arguments:
298 297 * modinfo *modinfop Pointer to the opaque modinfo structure
299 298 *
300 299 * Returns:
301 300 * mod_info() status, see mod_info(9f)
302 301 */
303 302 int
304 303 _info(struct modinfo *modinfop)
305 304 {
306 305 return (mod_info(&audio810_modlinkage, modinfop));
307 306 }
308 307
309 308
310 309 /* ******************* Driver Entry Points ********************************* */
311 310
312 311 /*
313 312 * audio810_ddi_attach()
314 313 *
315 314 * Description:
316 315 * Implements the DDI attach(9e) entry point.
317 316 *
318 317 * Arguments:
319 318 * dev_info_t *dip Pointer to the device's dev_info struct
320 319 * ddi_attach_cmd_t cmd Attach command
321 320 *
322 321 * Returns:
323 322 * DDI_SUCCESS The driver was initialized properly
324 323 * DDI_FAILURE The driver couldn't be initialized properly
325 324 */
326 325 static int
327 326 audio810_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
328 327 {
329 328 switch (cmd) {
330 329 case DDI_ATTACH:
331 330 return (audio810_attach(dip));
332 331
333 332 case DDI_RESUME:
334 333 return (audio810_resume(dip));
335 334 }
336 335 return (DDI_FAILURE);
337 336 }
338 337
339 338 /*
340 339 * audio810_ddi_detach()
341 340 *
342 341 * Description:
343 342 * Implements the detach(9e) entry point.
344 343 *
345 344 * Arguments:
346 345 * dev_info_t *dip Pointer to the device's dev_info struct
347 346 * ddi_detach_cmd_t cmd Detach command
348 347 *
349 348 * Returns:
350 349 * DDI_SUCCESS The driver was detached
351 350 * DDI_FAILURE The driver couldn't be detached
352 351 */
353 352 static int
354 353 audio810_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
355 354 {
356 355 switch (cmd) {
357 356 case DDI_DETACH:
358 357 return (audio810_detach(dip));
359 358
360 359 case DDI_SUSPEND:
361 360 return (audio810_suspend(dip));
362 361 }
363 362 return (DDI_FAILURE);
364 363 }
365 364
366 365 /*
367 366 * audio810_ddi_quiesce()
368 367 *
369 368 * Description:
370 369 * Implements the quiesce(9e) entry point.
371 370 *
372 371 * Arguments:
373 372 * dev_info_t *dip Pointer to the device's dev_info struct
374 373 *
375 374 * Returns:
376 375 * DDI_SUCCESS The driver was quiesced
377 376 * DDI_FAILURE The driver couldn't be quiesced
378 377 */
379 378 static int
380 379 audio810_ddi_quiesce(dev_info_t *dip)
381 380 {
382 381 audio810_state_t *statep;
383 382
384 383 if ((statep = ddi_get_driver_private(dip)) == NULL)
385 384 return (DDI_FAILURE);
386 385
387 386 audio810_stop_dma(statep);
388 387 return (DDI_SUCCESS);
389 388 }
390 389
391 390 /*
392 391 * audio810_open()
393 392 *
394 393 * Description:
395 394 * Opens a DMA engine for use.
396 395 *
397 396 * Arguments:
398 397 * void *arg The DMA engine to set up
399 398 * int flag Open flags
400 399 * unsigned *nframes Receives total number of frames
401 400 * caddr_t *bufp Receives kernel data buffer
402 401 *
403 402 * Returns:
404 403 * 0 on success
405 404 * errno on failure
406 405 */
407 406 static int
408 407 audio810_open(void *arg, int flag, unsigned *nframes, caddr_t *bufp)
409 408 {
410 409 audio810_port_t *port = arg;
411 410
412 411 _NOTE(ARGUNUSED(flag));
413 412
414 413 port->count = 0;
415 414 *nframes = port->samp_frames;
416 415 *bufp = port->samp_kaddr;
417 416
418 417 return (0);
419 418 }
420 419
421 420 /*
422 421 * audio810_close()
423 422 *
424 423 * Description:
425 424 * Closes an audio DMA engine that was previously opened. Since
426 425 * nobody is using it, we take this opportunity to possibly power
427 426 * down the entire device.
428 427 *
429 428 * Arguments:
430 429 * void *arg The DMA engine to shut down
431 430 */
432 431 static void
433 432 audio810_close(void *arg)
434 433 {
435 434 _NOTE(ARGUNUSED(arg));
436 435 }
437 436
438 437 /*
439 438 * audio810_stop()
440 439 *
441 440 * Description:
442 441 * This is called by the framework to stop a port that is
443 442 * transferring data.
444 443 *
445 444 * Arguments:
446 445 * void *arg The DMA engine to stop
447 446 */
448 447 static void
449 448 audio810_stop(void *arg)
450 449 {
451 450 audio810_port_t *port = arg;
452 451 audio810_state_t *statep = port->statep;
453 452 uint8_t cr;
454 453
455 454 cr = I810_BM_GET8(port->regoff + I810_OFFSET_CR);
456 455 cr &= ~I810_BM_CR_RUN;
457 456 I810_BM_PUT8(port->regoff + I810_OFFSET_CR, cr);
458 457 }
459 458
460 459 /*
461 460 * audio810_start()
462 461 *
463 462 * Description:
464 463 * This is called by the framework to start a port transferring data.
465 464 *
466 465 * Arguments:
467 466 * void *arg The DMA engine to start
468 467 *
469 468 * Returns:
470 469 * 0 on success (never fails, errno if it did)
471 470 */
472 471 static int
473 472 audio810_start(void *arg)
474 473 {
475 474 audio810_port_t *port = arg;
476 475 audio810_state_t *statep = port->statep;
477 476 uint8_t regoff, cr;
478 477
479 478 regoff = port->regoff;
480 479 port->offset = 0;
481 480
482 481 /* program multiple channel settings */
483 482 if (port->num == I810_PCM_OUT) {
484 483 audio810_set_channels(statep);
485 484
486 485 if (statep->quirk == QUIRK_SIS7012) {
487 486 /*
488 487 * SiS 7012 has special unmute bit.
489 488 */
490 489 I810_BM_PUT8(I810_REG_SISCTL, I810_SISCTL_UNMUTE);
491 490 }
492 491 }
493 492
494 493 /*
495 494 * Perform full reset of the engine, but leave it turned off.
496 495 */
497 496 I810_BM_PUT8(regoff + I810_OFFSET_CR, 0);
498 497 I810_BM_PUT8(regoff + I810_OFFSET_CR, I810_BM_CR_RST);
499 498
500 499 /* program the offset of the BD list */
501 500 I810_BM_PUT32(regoff + I810_OFFSET_BD_BASE, port->bdl_paddr);
502 501
503 502 /* we set the last index to the full count -- all buffers are valid */
504 503 I810_BM_PUT8(regoff + I810_OFFSET_LVI, I810_BD_NUMS - 1);
505 504
506 505 cr = I810_BM_GET8(regoff + I810_OFFSET_CR);
507 506 cr |= I810_BM_CR_RUN;
508 507 I810_BM_PUT8(regoff + I810_OFFSET_CR, cr);
509 508
510 509 (void) I810_BM_GET8(regoff + I810_OFFSET_CR);
511 510
512 511 return (0);
513 512 }
514 513
515 514 /*
516 515 * audio810_format()
517 516 *
518 517 * Description:
519 518 * This is called by the framework to query the format of the device.
520 519 *
521 520 * Arguments:
522 521 * void *arg The DMA engine to query
523 522 *
524 523 * Returns:
525 524 * Format of the device (fixed at AUDIO_FORMAT_S16_LE)
526 525 */
527 526 static int
528 527 audio810_format(void *arg)
529 528 {
530 529 _NOTE(ARGUNUSED(arg));
531 530
532 531 return (AUDIO_FORMAT_S16_LE);
533 532 }
534 533
535 534 /*
536 535 * audio810_channels()
537 536 *
538 537 * Description:
539 538 * This is called by the framework to query the num channels of
540 539 * the device.
541 540 *
542 541 * Arguments:
543 542 * void *arg The DMA engine to query
544 543 *
545 544 * Returns:
546 545 * 0 number of channels for device
547 546 */
548 547 static int
549 548 audio810_channels(void *arg)
550 549 {
551 550 audio810_port_t *port = arg;
552 551
553 552 return (port->nchan);
554 553 }
555 554
556 555 /*
557 556 * audio810_rate()
558 557 *
559 558 * Description:
560 559 * This is called by the framework to query the rate of the device.
561 560 *
562 561 * Arguments:
563 562 * void *arg The DMA engine to query
564 563 *
565 564 * Returns:
566 565 * Rate of device (fixed at 48000 Hz)
567 566 */
568 567 static int
569 568 audio810_rate(void *arg)
570 569 {
571 570 _NOTE(ARGUNUSED(arg));
572 571
573 572 return (48000);
574 573 }
575 574
576 575 /*
577 576 * audio810_count()
578 577 *
579 578 * Description:
580 579 * This is called by the framework to get the engine's frame counter
581 580 *
582 581 * Arguments:
583 582 * void *arg The DMA engine to query
584 583 *
585 584 * Returns:
586 585 * frame count for current engine
587 586 */
588 587 static uint64_t
589 588 audio810_count(void *arg)
590 589 {
591 590 audio810_port_t *port = arg;
592 591 audio810_state_t *statep = port->statep;
593 592 uint8_t regoff = port->regoff;
594 593 uint64_t val;
595 594 uint32_t offset;
596 595 uint8_t civ;
597 596
598 597 /*
599 598 * Read the position counters. We also take this opportunity
600 599 * to update the last valid index to the one just previous to
601 600 * the one we're working on (so we'll fully loop.)
602 601 */
603 602 offset = I810_BM_GET16(port->picboff);
604 603 civ = I810_BM_GET8(regoff + I810_OFFSET_CIV);
605 604 I810_BM_PUT8(port->regoff + I810_OFFSET_LVI, (civ - 1) % I810_BD_NUMS);
606 605
607 606 /* SiS counts in bytes, all others in words. */
608 607 if (statep->quirk != QUIRK_SIS7012)
609 608 offset *= 2;
610 609
611 610 /* counter is reversed */
612 611 offset = port->samp_size - offset;
613 612
614 613 if (offset < port->offset) {
615 614 val = (port->samp_size - port->offset) + offset;
616 615 } else {
617 616 val = offset - port->offset;
618 617 }
619 618 port->offset = offset;
620 619 port->count += (val / (port->nchan * 2));
621 620 val = port->count;
622 621
623 622 return (val);
624 623 }
625 624
626 625 /*
627 626 * audio810_sync()
628 627 *
629 628 * Description:
630 629 * This is called by the framework to synchronize DMA caches.
631 630 *
632 631 * Arguments:
633 632 * void *arg The DMA engine to sync
634 633 */
635 634 static void
636 635 audio810_sync(void *arg, unsigned nframes)
637 636 {
638 637 audio810_port_t *port = arg;
639 638 _NOTE(ARGUNUSED(nframes));
640 639
641 640 (void) ddi_dma_sync(port->samp_dmah, 0, 0, port->sync_dir);
642 641 }
643 642
644 643 /*
645 644 * audio810_playahead()
646 645 *
647 646 * Description:
648 647 * This is called by the framework to determine how much data it
649 648 * should queue up. We desire a deeper playahead than most to
650 649 * allow for virtualized devices which have less "regular"
651 650 * interrupt scheduling.
652 651 *
653 652 * Arguments:
654 653 * void *arg The DMA engine to query
655 654 *
656 655 * Returns:
657 656 * Play ahead in frames.
658 657 */
659 658 static unsigned
660 659 audio810_playahead(void *arg)
661 660 {
662 661 audio810_port_t *port = arg;
663 662 audio810_state_t *statep = port->statep;
664 663
665 664 /* Older ICH is likely to be emulated, deeper (40 ms) playahead */
666 665 return (statep->quirk == QUIRK_OLDICH ? 1920 : 0);
667 666 }
668 667
669 668
670 669
671 670 /* *********************** Local Routines *************************** */
672 671
673 672 /*
674 673 * audio810_attach()
675 674 *
676 675 * Description:
677 676 * Attach an instance of the audio810 driver. This routine does the
678 677 * device dependent attach tasks, and registers with the audio framework.
679 678 *
680 679 * Arguments:
681 680 * dev_info_t *dip Pointer to the device's dev_info struct
682 681 * ddi_attach_cmd_t cmd Attach command
683 682 *
684 683 * Returns:
685 684 * DDI_SUCCESS The driver was initialized properly
686 685 * DDI_FAILURE The driver couldn't be initialized properly
687 686 */
688 687 static int
689 688 audio810_attach(dev_info_t *dip)
690 689 {
691 690 uint16_t cmdreg;
692 691 audio810_state_t *statep;
693 692 audio_dev_t *adev;
694 693 ddi_acc_handle_t pcih;
695 694 uint32_t devid;
696 695 uint32_t gsr;
697 696 const char *name;
698 697 const char *vers;
699 698 uint8_t nch;
700 699 int maxch;
701 700
702 701 /* allocate the soft state structure */
703 702 statep = kmem_zalloc(sizeof (*statep), KM_SLEEP);
704 703 ddi_set_driver_private(dip, statep);
705 704
706 705 if ((adev = audio_dev_alloc(dip, 0)) == NULL) {
707 706 cmn_err(CE_WARN, "!%s%d: unable to allocate audio dev",
708 707 ddi_driver_name(dip), ddi_get_instance(dip));
709 708 goto error;
710 709 }
711 710 statep->adev = adev;
712 711 statep->dip = dip;
713 712
714 713 /* map in the registers, allocate DMA buffers, etc. */
715 714 if (audio810_map_regs(dip, statep) != DDI_SUCCESS) {
716 715 audio_dev_warn(adev, "couldn't map registers");
717 716 goto error;
718 717 }
719 718
720 719 /* set PCI command register */
721 720 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) {
722 721 audio_dev_warn(adev, "pci conf mapping failed");
723 722 goto error;
724 723 }
725 724 cmdreg = pci_config_get16(pcih, PCI_CONF_COMM);
726 725 pci_config_put16(pcih, PCI_CONF_COMM,
727 726 cmdreg | PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME);
728 727 devid = pci_config_get16(pcih, PCI_CONF_VENID);
729 728 devid <<= 16;
730 729 devid |= pci_config_get16(pcih, PCI_CONF_DEVID);
731 730 pci_config_teardown(&pcih);
732 731
733 732 name = "Unknown AC'97";
734 733 vers = "";
735 734
736 735 statep->quirk = QUIRK_NONE;
737 736 switch (devid) {
738 737 case 0x80862415:
739 738 name = "Intel AC'97";
740 739 vers = "ICH";
741 740 statep->quirk = QUIRK_OLDICH;
742 741 break;
743 742 case 0x80862425:
744 743 name = "Intel AC'97";
745 744 vers = "ICH0";
746 745 break;
747 746 case 0x80867195:
748 747 name = "Intel AC'97";
749 748 vers = "440MX";
750 749 break;
751 750 case 0x80862445:
752 751 name = "Intel AC'97";
753 752 vers = "ICH2";
754 753 break;
755 754 case 0x80862485:
756 755 name = "Intel AC'97";
757 756 vers = "ICH3";
758 757 break;
759 758 case 0x808624C5:
760 759 name = "Intel AC'97";
761 760 vers = "ICH4";
762 761 break;
763 762 case 0x808624D5:
764 763 name = "Intel AC'97";
765 764 vers = "ICH5";
766 765 break;
767 766 case 0x8086266E:
768 767 name = "Intel AC'97";
769 768 vers = "ICH6";
770 769 break;
771 770 case 0x808627DE:
772 771 name = "Intel AC'97";
773 772 vers = "ICH7";
774 773 break;
775 774 case 0x808625A6:
776 775 name = "Intel AC'97";
777 776 vers = "6300ESB";
778 777 break;
779 778 case 0x80862698:
780 779 name = "Intel AC'97";
781 780 vers = "ESB2";
782 781 break;
783 782 case 0x10397012:
784 783 name = "SiS AC'97";
785 784 vers = "7012";
786 785 statep->quirk = QUIRK_SIS7012;
787 786 break;
788 787 case 0x10de01b1: /* nForce */
789 788 name = "NVIDIA AC'97";
790 789 vers = "MCP1";
791 790 break;
792 791 case 0x10de006a: /* nForce 2 */
793 792 name = "NVIDIA AC'97";
794 793 vers = "MCP2";
795 794 break;
796 795 case 0x10de00da: /* nForce 3 */
797 796 name = "NVIDIA AC'97";
798 797 vers = "MCP3";
799 798 break;
800 799 case 0x10de00ea:
801 800 name = "NVIDIA AC'97";
802 801 vers = "CK8S";
803 802 break;
804 803 case 0x10de0059:
805 804 name = "NVIDIA AC'97";
806 805 vers = "CK804";
807 806 break;
808 807 case 0x10de008a:
809 808 name = "NVIDIA AC'97";
810 809 vers = "CK8";
811 810 break;
812 811 case 0x10de003a: /* nForce 4 */
813 812 name = "NVIDIA AC'97";
814 813 vers = "MCP4";
815 814 break;
816 815 case 0x10de026b:
817 816 name = "NVIDIA AC'97";
818 817 vers = "MCP51";
819 818 break;
820 819 case 0x1022746d:
821 820 name = "AMD AC'97";
822 821 vers = "8111";
823 822 break;
824 823 case 0x10227445:
825 824 name = "AMD AC'97";
826 825 vers = "AMD768";
827 826 break;
828 827 }
829 828 /* set device information */
830 829 audio_dev_set_description(adev, name);
831 830 audio_dev_set_version(adev, vers);
832 831
833 832 /* initialize audio controller and AC97 codec */
834 833 if (audio810_chip_init(statep) != DDI_SUCCESS) {
835 834 audio_dev_warn(adev, "failed to init chip");
836 835 goto error;
837 836 }
838 837
839 838 /* allocate ac97 handle */
840 839 statep->ac97 = ac97_alloc(dip, audio810_read_ac97, audio810_write_ac97,
841 840 statep);
842 841 if (statep->ac97 == NULL) {
843 842 audio_dev_warn(adev, "failed to allocate ac97 handle");
844 843 goto error;
845 844 }
846 845
847 846 /* initialize the AC'97 part */
848 847 if (ac97_init(statep->ac97, adev) != DDI_SUCCESS) {
849 848 audio_dev_warn(adev, "ac'97 initialization failed");
850 849 goto error;
851 850 }
852 851
853 852 /*
854 853 * Override "max-channels" property to prevent configuration
855 854 * of 4 or 6 (or possibly even 8!) channel audio. The default
856 855 * is to support as many channels as the hardware can do.
857 856 *
858 857 * (Hmmm... perhaps this should be driven in the common
859 858 * framework. The framework could even offer simplistic upmix
860 859 * and downmix for various standard configs.)
861 860 */
862 861 maxch = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
863 862 "max-channels", ac97_num_channels(statep->ac97));
864 863 if (maxch < 2) {
865 864 maxch = 2;
866 865 }
867 866
868 867 gsr = I810_BM_GET32(I810_REG_GSR);
869 868 if (gsr & I810_GSR_CAP6CH) {
870 869 nch = 6;
871 870 } else if (gsr & I810_GSR_CAP4CH) {
872 871 nch = 4;
873 872 } else {
874 873 nch = 2;
875 874 }
876 875
877 876 statep->maxch = (uint8_t)min(nch, maxch);
878 877 statep->maxch &= ~1;
879 878
880 879 /* allocate port structures */
881 880 if ((audio810_alloc_port(statep, I810_PCM_OUT, statep->maxch) !=
882 881 DDI_SUCCESS) ||
883 882 (audio810_alloc_port(statep, I810_PCM_IN, 2) != DDI_SUCCESS)) {
884 883 goto error;
885 884 }
886 885
887 886 if (audio_dev_register(adev) != DDI_SUCCESS) {
888 887 audio_dev_warn(adev, "unable to register with framework");
889 888 goto error;
890 889 }
891 890
892 891 ddi_report_dev(dip);
893 892
894 893 return (DDI_SUCCESS);
895 894
896 895 error:
897 896 audio810_destroy(statep);
898 897
899 898 return (DDI_FAILURE);
900 899 }
901 900
902 901
903 902 /*
904 903 * audio810_resume()
905 904 *
906 905 * Description:
907 906 * Resume operation of the device after sleeping or hibernating.
908 907 * Note that this should never fail, even if hardware goes wonky,
909 908 * because the current PM framework will panic if it does.
910 909 *
911 910 * Arguments:
912 911 * dev_info_t *dip Pointer to the device's dev_info struct
913 912 *
914 913 * Returns:
915 914 * DDI_SUCCESS The driver was resumed.
916 915 */
917 916 static int
918 917 audio810_resume(dev_info_t *dip)
919 918 {
920 919 audio810_state_t *statep;
921 920 audio_dev_t *adev;
922 921
923 922 /* this should always be valid */
924 923 statep = ddi_get_driver_private(dip);
925 924 adev = statep->adev;
926 925
927 926 ASSERT(statep != NULL);
928 927 ASSERT(dip == statep->dip);
929 928
930 929 /* Restore the audio810 chip's state */
931 930 if (audio810_chip_init(statep) != DDI_SUCCESS) {
932 931 /*
933 932 * Note that PM gurus say we should return success
934 933 * here. Failure of audio shouldn't be considered
935 934 * FATAL to the system.
936 935 *
937 936 * It turns out that the only way that the
938 937 * audio810_chip_init fails is that the codec won't
939 938 * re-initialize. Audio streams may or may not make
940 939 * progress; setting changes may or may not have the
941 940 * desired effect. What we'd really to do at this
942 941 * point is use FMA to offline the part. In the
943 942 * meantime, we just muddle on logging the error.
944 943 *
945 944 * Note that returning from this routine without
946 945 * allowing the audio_dev_resume() to take place can
947 946 * have bad effects, as the framework does not know
948 947 * what to do in the event of a failure of this
949 948 * nature. (It may be unsafe to call ENG_CLOSE(), for
950 949 * example.)
951 950 */
952 951 audio_dev_warn(adev, "failure to resume codec");
953 952 }
954 953
955 954 /* Reset the AC'97 codec. */
956 955 ac97_reset(statep->ac97);
957 956
958 957 /* And let the framework know we're ready for business again. */
959 958 audio_dev_resume(statep->adev);
960 959
961 960 return (DDI_SUCCESS);
962 961 }
963 962
964 963 /*
965 964 * audio810_detach()
966 965 *
967 966 * Description:
968 967 * Detach an instance of the audio810 driver.
969 968 *
970 969 * Arguments:
971 970 * dev_info_t *dip Pointer to the device's dev_info struct
972 971 *
973 972 * Returns:
974 973 * DDI_SUCCESS The driver was detached
975 974 * DDI_FAILURE The driver couldn't be detached
976 975 */
977 976 static int
978 977 audio810_detach(dev_info_t *dip)
979 978 {
980 979 audio810_state_t *statep;
981 980
982 981 statep = ddi_get_driver_private(dip);
983 982 ASSERT(statep != NULL);
984 983
985 984 /* don't detach us if we are still in use */
986 985 if (audio_dev_unregister(statep->adev) != DDI_SUCCESS) {
987 986 return (DDI_FAILURE);
988 987 }
989 988
990 989 audio810_destroy(statep);
991 990 return (DDI_SUCCESS);
992 991 }
993 992
994 993 /*
995 994 * audio810_suspend()
996 995 *
997 996 * Description:
998 997 * Suspend an instance of the audio810 driver, in preparation for
999 998 * sleep or hibernation.
1000 999 *
1001 1000 * Arguments:
1002 1001 * dev_info_t *dip Pointer to the device's dev_info struct
1003 1002 *
1004 1003 * Returns:
1005 1004 * DDI_SUCCESS The driver was suspended
1006 1005 */
1007 1006 static int
1008 1007 audio810_suspend(dev_info_t *dip)
1009 1008 {
1010 1009 audio810_state_t *statep;
1011 1010
1012 1011 statep = ddi_get_driver_private(dip);
1013 1012 ASSERT(statep != NULL);
1014 1013
1015 1014 audio_dev_suspend(statep->adev);
1016 1015
1017 1016 /* stop DMA engines - should be redundant (paranoia) */
1018 1017 audio810_stop_dma(statep);
1019 1018
1020 1019 return (DDI_SUCCESS);
1021 1020 }
1022 1021
1023 1022 /*
1024 1023 * audio810_alloc_port()
1025 1024 *
1026 1025 * Description:
1027 1026 * This routine allocates the DMA handles and the memory for the
1028 1027 * DMA engines to use. It also configures the BDL lists properly
1029 1028 * for use.
1030 1029 *
1031 1030 * Arguments:
1032 1031 * dev_info_t *dip Pointer to the device's devinfo
1033 1032 *
1034 1033 * Returns:
1035 1034 * DDI_SUCCESS Registers successfully mapped
1036 1035 * DDI_FAILURE Registers not successfully mapped
1037 1036 */
1038 1037 static int
1039 1038 audio810_alloc_port(audio810_state_t *statep, int num, uint8_t nchan)
1040 1039 {
1041 1040 ddi_dma_cookie_t cookie;
1042 1041 uint_t count;
1043 1042 int dir;
1044 1043 unsigned caps;
1045 1044 audio_dev_t *adev;
1046 1045 audio810_port_t *port;
1047 1046 int rc;
1048 1047 dev_info_t *dip;
1049 1048 i810_bd_entry_t *bdentry;
1050 1049
1051 1050 adev = statep->adev;
1052 1051 dip = statep->dip;
1053 1052
1054 1053 port = kmem_zalloc(sizeof (*port), KM_SLEEP);
1055 1054 statep->ports[num] = port;
1056 1055 port->statep = statep;
1057 1056 port->nchan = nchan;
1058 1057 port->num = num;
1059 1058
1060 1059 switch (num) {
1061 1060 case I810_PCM_IN:
1062 1061 dir = DDI_DMA_READ;
1063 1062 caps = ENGINE_INPUT_CAP;
1064 1063 port->sync_dir = DDI_DMA_SYNC_FORKERNEL;
1065 1064 port->regoff = I810_BASE_PCM_IN;
1066 1065 break;
1067 1066 case I810_PCM_OUT:
1068 1067 dir = DDI_DMA_WRITE;
1069 1068 caps = ENGINE_OUTPUT_CAP;
1070 1069 port->sync_dir = DDI_DMA_SYNC_FORDEV;
1071 1070 port->regoff = I810_BASE_PCM_OUT;
1072 1071 break;
1073 1072 default:
1074 1073 audio_dev_warn(adev, "bad port number (%d)!", num);
1075 1074 return (DDI_FAILURE);
1076 1075 }
1077 1076
1078 1077 /*
1079 1078 * SiS 7012 swaps status and picb registers.
1080 1079 */
1081 1080 if (statep->quirk == QUIRK_SIS7012) {
1082 1081 port->stsoff = port->regoff + I810_OFFSET_PICB;
1083 1082 port->picboff = port->regoff + I810_OFFSET_SR;
1084 1083 } else {
1085 1084 port->stsoff = port->regoff + I810_OFFSET_SR;
1086 1085 port->picboff = port->regoff + I810_OFFSET_PICB;
1087 1086 }
1088 1087
1089 1088 /*
1090 1089 * We use one big sample area. The sample area must be larger
1091 1090 * than about 1.5 framework fragment sizes. (Currently 480 *
1092 1091 * 1.5 = 720 frames.) This is necessary to ensure that we
1093 1092 * don't have to involve an interrupt service routine on our
1094 1093 * own, to keep the last valid index updated reasonably.
1095 1094 */
1096 1095 port->samp_frames = 4096;
1097 1096 port->samp_size = port->samp_frames * port->nchan * sizeof (int16_t);
1098 1097
1099 1098 /* allocate dma handle */
1100 1099 rc = ddi_dma_alloc_handle(dip, &sample_buf_dma_attr, DDI_DMA_SLEEP,
1101 1100 NULL, &port->samp_dmah);
1102 1101 if (rc != DDI_SUCCESS) {
1103 1102 audio_dev_warn(adev, "ddi_dma_alloc_handle failed: %d", rc);
1104 1103 return (DDI_FAILURE);
1105 1104 }
1106 1105 /* allocate DMA buffer */
1107 1106 rc = ddi_dma_mem_alloc(port->samp_dmah, port->samp_size, &buf_attr,
1108 1107 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &port->samp_kaddr,
1109 1108 &port->samp_size, &port->samp_acch);
1110 1109 if (rc == DDI_FAILURE) {
1111 1110 audio_dev_warn(adev, "dma_mem_alloc (%d) failed: %d",
1112 1111 port->samp_size, rc);
1113 1112 return (DDI_FAILURE);
1114 1113 }
1115 1114
1116 1115 /* bind DMA buffer */
1117 1116 rc = ddi_dma_addr_bind_handle(port->samp_dmah, NULL,
1118 1117 port->samp_kaddr, port->samp_size, dir|DDI_DMA_CONSISTENT,
1119 1118 DDI_DMA_SLEEP, NULL, &cookie, &count);
1120 1119 if ((rc != DDI_DMA_MAPPED) || (count != 1)) {
1121 1120 audio_dev_warn(adev,
1122 1121 "ddi_dma_addr_bind_handle failed: %d", rc);
1123 1122 return (DDI_FAILURE);
1124 1123 }
1125 1124 port->samp_paddr = cookie.dmac_address;
1126 1125
1127 1126 /*
1128 1127 * now, from here we allocate DMA memory for buffer descriptor list.
1129 1128 * we allocate adjacent DMA memory for all DMA engines.
1130 1129 */
1131 1130 rc = ddi_dma_alloc_handle(dip, &bdlist_dma_attr, DDI_DMA_SLEEP,
1132 1131 NULL, &port->bdl_dmah);
1133 1132 if (rc != DDI_SUCCESS) {
1134 1133 audio_dev_warn(adev, "ddi_dma_alloc_handle(bdlist) failed");
1135 1134 return (DDI_FAILURE);
1136 1135 }
1137 1136
1138 1137 /*
1139 1138 * we allocate all buffer descriptors lists in continuous dma memory.
1140 1139 */
1141 1140 port->bdl_size = sizeof (i810_bd_entry_t) * I810_BD_NUMS;
1142 1141 rc = ddi_dma_mem_alloc(port->bdl_dmah, port->bdl_size,
1143 1142 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
1144 1143 &port->bdl_kaddr, &port->bdl_size, &port->bdl_acch);
1145 1144 if (rc != DDI_SUCCESS) {
1146 1145 audio_dev_warn(adev, "ddi_dma_mem_alloc(bdlist) failed");
1147 1146 return (DDI_FAILURE);
1148 1147 }
1149 1148
1150 1149 rc = ddi_dma_addr_bind_handle(port->bdl_dmah, NULL, port->bdl_kaddr,
1151 1150 port->bdl_size, DDI_DMA_WRITE|DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
1152 1151 NULL, &cookie, &count);
1153 1152 if ((rc != DDI_DMA_MAPPED) || (count != 1)) {
1154 1153 audio_dev_warn(adev, "addr_bind_handle failed");
1155 1154 return (DDI_FAILURE);
1156 1155 }
1157 1156 port->bdl_paddr = cookie.dmac_address;
1158 1157
1159 1158 /*
1160 1159 * Wire up the BD list.
1161 1160 */
1162 1161 bdentry = (void *)port->bdl_kaddr;
1163 1162 for (int i = 0; i < I810_BD_NUMS; i++) {
1164 1163
1165 1164 /* set base address of buffer */
1166 1165 ddi_put32(port->bdl_acch, &bdentry->buf_base,
1167 1166 port->samp_paddr);
1168 1167 /* SiS 7012 counts in bytes, all others in words */
1169 1168 ddi_put16(port->bdl_acch, &bdentry->buf_len,
1170 1169 statep->quirk == QUIRK_SIS7012 ? port->samp_size :
1171 1170 port->samp_size / 2);
1172 1171 ddi_put16(port->bdl_acch, &bdentry->buf_cmd, BUF_CMD_BUP);
1173 1172
1174 1173 bdentry++;
1175 1174 }
1176 1175 (void) ddi_dma_sync(port->bdl_dmah, 0, 0, DDI_DMA_SYNC_FORDEV);
1177 1176
1178 1177 port->engine = audio_engine_alloc(&audio810_engine_ops, caps);
1179 1178 if (port->engine == NULL) {
1180 1179 audio_dev_warn(adev, "audio_engine_alloc failed");
1181 1180 return (DDI_FAILURE);
1182 1181 }
1183 1182
1184 1183 audio_engine_set_private(port->engine, port);
1185 1184 audio_dev_add_engine(adev, port->engine);
1186 1185
1187 1186 return (DDI_SUCCESS);
1188 1187 }
1189 1188
1190 1189 /*
1191 1190 * audio810_free_port()
1192 1191 *
1193 1192 * Description:
1194 1193 * This routine unbinds the DMA cookies, frees the DMA buffers,
1195 1194 * deallocates the DMA handles.
1196 1195 *
1197 1196 * Arguments:
1198 1197 * audio810_port_t *port The port structure for a DMA engine.
1199 1198 */
1200 1199 static void
1201 1200 audio810_free_port(audio810_port_t *port)
1202 1201 {
1203 1202 if (port == NULL)
1204 1203 return;
1205 1204
1206 1205 if (port->engine) {
1207 1206 audio_dev_remove_engine(port->statep->adev, port->engine);
1208 1207 audio_engine_free(port->engine);
1209 1208 }
1210 1209 if (port->bdl_paddr) {
1211 1210 (void) ddi_dma_unbind_handle(port->bdl_dmah);
1212 1211 }
1213 1212 if (port->bdl_acch) {
1214 1213 ddi_dma_mem_free(&port->bdl_acch);
1215 1214 }
1216 1215 if (port->bdl_dmah) {
1217 1216 ddi_dma_free_handle(&port->bdl_dmah);
1218 1217 }
1219 1218 if (port->samp_paddr) {
1220 1219 (void) ddi_dma_unbind_handle(port->samp_dmah);
1221 1220 }
1222 1221 if (port->samp_acch) {
1223 1222 ddi_dma_mem_free(&port->samp_acch);
1224 1223 }
1225 1224 if (port->samp_dmah) {
1226 1225 ddi_dma_free_handle(&port->samp_dmah);
1227 1226 }
1228 1227 kmem_free(port, sizeof (*port));
1229 1228 }
1230 1229
1231 1230 /*
1232 1231 * audio810_map_regs()
1233 1232 *
1234 1233 * Description:
1235 1234 * The registers are mapped in.
1236 1235 *
1237 1236 * Arguments:
1238 1237 * dev_info_t *dip Pointer to the device's devinfo
1239 1238 *
1240 1239 * Returns:
1241 1240 * DDI_SUCCESS Registers successfully mapped
1242 1241 * DDI_FAILURE Registers not successfully mapped
1243 1242 */
1244 1243 static int
1245 1244 audio810_map_regs(dev_info_t *dip, audio810_state_t *statep)
1246 1245 {
1247 1246 uint_t nregs = 0;
1248 1247 int *regs_list;
1249 1248 int i;
1250 1249 int pciBar1 = 0;
1251 1250 int pciBar2 = 0;
1252 1251 int pciBar3 = 0;
1253 1252 int pciBar4 = 0;
1254 1253
1255 1254 /* check the "reg" property to get the length of memory-mapped I/O */
1256 1255 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1257 1256 "reg", (int **)®s_list, &nregs) != DDI_PROP_SUCCESS) {
1258 1257 audio_dev_warn(statep->adev, "inquire regs property failed");
1259 1258 goto error;
1260 1259 }
1261 1260 /*
1262 1261 * Some hardwares, such as Intel ICH0/ICH and AMD 8111, use PCI 0x10
1263 1262 * and 0x14 BAR separately for native audio mixer BAR and native bus
1264 1263 * mastering BAR. More advanced hardwares, such as Intel ICH4 and ICH5,
1265 1264 * support PCI memory BAR, via PCI 0x18 and 0x1C BAR, that allows for
1266 1265 * higher performance access to the controller register. All features
1267 1266 * can be accessed via this BAR making the I/O BAR (PCI 0x10 and 0x14
1268 1267 * BAR) capabilities obsolete. However, these controller maintain the
1269 1268 * I/O BAR capability to allow for the reuse of legacy code maintaining
1270 1269 * backward compatibility. The I/O BAR is disabled unless system BIOS
1271 1270 * enables the simultaneous backward compatible capability on the 0x41
1272 1271 * register.
1273 1272 *
1274 1273 * When I/O BAR is enabled, the value of "reg" property should be like
1275 1274 * this,
1276 1275 * phys_hi phys_mid phys_lo size_hi size_lo
1277 1276 * --------------------------------------------------------
1278 1277 * 0000fd00 00000000 00000000 00000000 00000000
1279 1278 * 0100fd10 00000000 00000000 00000000 00000100
1280 1279 * 0100fd14 00000000 00000000 00000000 00000040
1281 1280 * 0200fd18 00000000 00000000 00000000 00000200
1282 1281 * 0200fd1c 00000000 00000000 00000000 00000100
1283 1282 *
1284 1283 * When I/O BAR is disabled, the "reg" property of the device node does
1285 1284 * not consist of the description for the I/O BAR. The following example
1286 1285 * illustrates the vaule of "reg" property,
1287 1286 *
1288 1287 * phys_hi phys_mid phys_lo size_hi size_lo
1289 1288 * --------------------------------------------------------
1290 1289 * 0000fd00 00000000 00000000 00000000 00000000
1291 1290 * 0200fd18 00000000 00000000 00000000 00000200
1292 1291 * 0200fd1c 00000000 00000000 00000000 00000100
1293 1292 *
1294 1293 * If the hardware has memory-mapped I/O access, first try to use
1295 1294 * this facility, otherwise we will try I/O access.
1296 1295 */
1297 1296 for (i = 1; i < nregs/I810_INTS_PER_REG_PROP; i++) {
1298 1297 switch (regs_list[I810_INTS_PER_REG_PROP * i] & 0x000000ff) {
1299 1298 case 0x10:
1300 1299 pciBar1 = i;
1301 1300 break;
1302 1301 case 0x14:
1303 1302 pciBar2 = i;
1304 1303 break;
1305 1304 case 0x18:
1306 1305 pciBar3 = i;
1307 1306 break;
1308 1307 case 0x1c:
1309 1308 pciBar4 = i;
1310 1309 break;
1311 1310 default: /* we don't care others */
1312 1311 break;
1313 1312 }
1314 1313 }
1315 1314
1316 1315 if ((pciBar3 != 0) && (pciBar4 != 0)) {
1317 1316 /* map audio mixer registers */
1318 1317 if ((ddi_regs_map_setup(dip, pciBar3, &statep->am_regs_base, 0,
1319 1318 0, &dev_attr, &statep->am_regs_handle)) != DDI_SUCCESS) {
1320 1319 audio_dev_warn(statep->adev,
1321 1320 "memory am mapping failed");
1322 1321 goto error;
1323 1322 }
1324 1323
1325 1324 /* map bus master register */
1326 1325 if ((ddi_regs_map_setup(dip, pciBar4, &statep->bm_regs_base, 0,
1327 1326 0, &dev_attr, &statep->bm_regs_handle)) != DDI_SUCCESS) {
1328 1327 audio_dev_warn(statep->adev,
1329 1328 "memory bm mapping failed");
1330 1329 goto error;
1331 1330 }
1332 1331
1333 1332 } else if ((pciBar1 != 0) && (pciBar2 != 0)) {
1334 1333 /* map audio mixer registers */
1335 1334 if ((ddi_regs_map_setup(dip, pciBar1, &statep->am_regs_base, 0,
1336 1335 0, &dev_attr, &statep->am_regs_handle)) != DDI_SUCCESS) {
1337 1336 audio_dev_warn(statep->adev, "I/O am mapping failed");
1338 1337 goto error;
1339 1338 }
1340 1339
1341 1340 /* map bus master register */
1342 1341 if ((ddi_regs_map_setup(dip, pciBar2, &statep->bm_regs_base, 0,
1343 1342 0, &dev_attr, &statep->bm_regs_handle)) != DDI_SUCCESS) {
1344 1343 audio_dev_warn(statep->adev, "I/O bm mapping failed");
1345 1344 goto error;
1346 1345 }
1347 1346 } else {
1348 1347 audio_dev_warn(statep->adev, "map_regs() pci BAR error");
1349 1348 goto error;
1350 1349 }
1351 1350
1352 1351 ddi_prop_free(regs_list);
1353 1352
1354 1353 return (DDI_SUCCESS);
1355 1354
1356 1355 error:
1357 1356 if (nregs > 0) {
1358 1357 ddi_prop_free(regs_list);
1359 1358 }
1360 1359 audio810_unmap_regs(statep);
1361 1360
1362 1361 return (DDI_FAILURE);
1363 1362 }
1364 1363
1365 1364 /*
1366 1365 * audio810_unmap_regs()
1367 1366 *
1368 1367 * Description:
1369 1368 * This routine unmaps control registers.
1370 1369 *
1371 1370 * Arguments:
1372 1371 * audio810_state_t *state The device's state structure
1373 1372 */
1374 1373 static void
1375 1374 audio810_unmap_regs(audio810_state_t *statep)
1376 1375 {
1377 1376 if (statep->bm_regs_handle) {
1378 1377 ddi_regs_map_free(&statep->bm_regs_handle);
1379 1378 }
1380 1379
1381 1380 if (statep->am_regs_handle) {
1382 1381 ddi_regs_map_free(&statep->am_regs_handle);
1383 1382 }
1384 1383 }
1385 1384
1386 1385 /*
1387 1386 * audio810_chip_init()
1388 1387 *
1389 1388 * Description:
1390 1389 * This routine initializes the audio controller.
1391 1390 *
1392 1391 * Arguments:
1393 1392 * audio810_state_t *state The device's state structure
1394 1393 *
1395 1394 * Returns:
1396 1395 * DDI_SUCCESS The hardware was initialized properly
1397 1396 * DDI_FAILURE The hardware couldn't be initialized properly
1398 1397 */
1399 1398 static int
1400 1399 audio810_chip_init(audio810_state_t *statep)
1401 1400 {
1402 1401 uint32_t gcr;
1403 1402 uint32_t gsr;
1404 1403 uint32_t codec_ready;
1405 1404 int loop;
1406 1405 clock_t ticks;
1407 1406
1408 1407 gcr = I810_BM_GET32(I810_REG_GCR);
1409 1408 ticks = drv_usectohz(100);
1410 1409
1411 1410 /*
1412 1411 * Clear the channels bits for now. We'll set them later in
1413 1412 * reset port.
1414 1413 */
1415 1414 if (statep->quirk == QUIRK_SIS7012) {
1416 1415 gcr &= ~(I810_GCR_ACLINK_OFF | I810_GCR_SIS_CHANNELS_MASK);
1417 1416 } else {
1418 1417 gcr &= ~(I810_GCR_ACLINK_OFF | I810_GCR_CHANNELS_MASK);
1419 1418 }
1420 1419
1421 1420 /*
1422 1421 * Datasheet(ICH5, document number of Intel: 252751-001):
1423 1422 * 3.6.5.5(page 37)
1424 1423 * if reset bit(bit1) is "0", driver must set it
1425 1424 * to "1" to de-assert the AC_RESET# signal in AC
1426 1425 * link, thus completing a cold reset. But if the
1427 1426 * bit is "1", then a warm reset is required.
1428 1427 */
1429 1428 gcr |= (gcr & I810_GCR_COLD_RST) == 0 ?
1430 1429 I810_GCR_COLD_RST:I810_GCR_WARM_RST;
1431 1430 I810_BM_PUT32(I810_REG_GCR, gcr);
1432 1431
1433 1432 /* according AC'97 spec, wait for codec reset */
1434 1433 for (loop = 6000; --loop >= 0; ) {
1435 1434 delay(ticks);
1436 1435 gcr = I810_BM_GET32(I810_REG_GCR);
1437 1436 if ((gcr & I810_GCR_WARM_RST) == 0) {
1438 1437 break;
1439 1438 }
1440 1439 }
1441 1440
1442 1441 /* codec reset failed */
1443 1442 if (loop < 0) {
1444 1443 audio_dev_warn(statep->adev, "Failed to reset codec");
1445 1444 return (DDI_FAILURE);
1446 1445 }
1447 1446
1448 1447 /*
1449 1448 * Wait for codec ready. The hardware can provide the state of
1450 1449 * codec ready bit on SDATA_IN[0], SDATA_IN[1] or SDATA_IN[2]
1451 1450 */
1452 1451 codec_ready =
1453 1452 I810_GSR_PRI_READY | I810_GSR_SEC_READY | I810_GSR_TRI_READY;
1454 1453 for (loop = 7000; --loop >= 0; ) {
1455 1454 delay(ticks);
1456 1455 gsr = I810_BM_GET32(I810_REG_GSR);
1457 1456 if ((gsr & codec_ready) != 0) {
1458 1457 break;
1459 1458 }
1460 1459 }
1461 1460 if (loop < 0) {
1462 1461 audio_dev_warn(statep->adev, "No codec ready signal received");
1463 1462 return (DDI_FAILURE);
1464 1463 }
1465 1464
1466 1465 /*
1467 1466 * put the audio controller into quiet state, everything off
1468 1467 */
1469 1468 audio810_stop_dma(statep);
1470 1469
1471 1470 return (DDI_SUCCESS);
1472 1471 }
1473 1472
1474 1473 /*
1475 1474 * audio810_set_channels()
1476 1475 *
1477 1476 * Description:
1478 1477 * This routine initializes the multichannel configuration.
1479 1478 *
1480 1479 * Arguments:
1481 1480 * audio810_state_t *state The device's state structure
1482 1481 */
1483 1482 static void
1484 1483 audio810_set_channels(audio810_state_t *statep)
1485 1484 {
1486 1485 uint32_t gcr;
1487 1486
1488 1487 /*
1489 1488 * Configure multi-channel.
1490 1489 */
1491 1490 if (statep->quirk == QUIRK_SIS7012) {
1492 1491 /*
1493 1492 * SiS 7012 needs its own special multichannel config.
1494 1493 */
1495 1494 gcr = I810_BM_GET32(I810_REG_GCR);
1496 1495 gcr &= ~I810_GCR_SIS_CHANNELS_MASK;
1497 1496 I810_BM_PUT32(I810_REG_GCR, gcr);
1498 1497 delay(drv_usectohz(50000)); /* 50 msec */
1499 1498
1500 1499 switch (statep->maxch) {
1501 1500 case 2:
1502 1501 gcr |= I810_GCR_SIS_2_CHANNELS;
1503 1502 break;
1504 1503 case 4:
1505 1504 gcr |= I810_GCR_SIS_4_CHANNELS;
1506 1505 break;
1507 1506 case 6:
1508 1507 gcr |= I810_GCR_SIS_6_CHANNELS;
1509 1508 break;
1510 1509 }
1511 1510 I810_BM_PUT32(I810_REG_GCR, gcr);
1512 1511 delay(drv_usectohz(50000)); /* 50 msec */
1513 1512 } else {
1514 1513
1515 1514 /*
1516 1515 * All other devices work the same.
1517 1516 */
1518 1517 gcr = I810_BM_GET32(I810_REG_GCR);
1519 1518 gcr &= ~I810_GCR_CHANNELS_MASK;
1520 1519
1521 1520 I810_BM_PUT32(I810_REG_GCR, gcr);
1522 1521 delay(drv_usectohz(50000)); /* 50 msec */
1523 1522
1524 1523 switch (statep->maxch) {
1525 1524 case 2:
1526 1525 gcr |= I810_GCR_2_CHANNELS;
1527 1526 break;
1528 1527 case 4:
1529 1528 gcr |= I810_GCR_4_CHANNELS;
1530 1529 break;
1531 1530 case 6:
1532 1531 gcr |= I810_GCR_6_CHANNELS;
1533 1532 break;
1534 1533 }
1535 1534 I810_BM_PUT32(I810_REG_GCR, gcr);
1536 1535 delay(drv_usectohz(50000)); /* 50 msec */
1537 1536 }
1538 1537 }
1539 1538
1540 1539 /*
1541 1540 * audio810_stop_dma()
1542 1541 *
1543 1542 * Description:
1544 1543 * This routine is used to put each DMA engine into the quiet state.
1545 1544 *
1546 1545 * Arguments:
1547 1546 * audio810_state_t *state The device's state structure
1548 1547 */
1549 1548 static void
1550 1549 audio810_stop_dma(audio810_state_t *statep)
1551 1550 {
1552 1551 if (statep->bm_regs_handle == NULL) {
1553 1552 return;
1554 1553 }
1555 1554 /* pause bus master (needed for the following reset register) */
1556 1555 I810_BM_PUT8(I810_BASE_PCM_IN + I810_OFFSET_CR, 0x0);
1557 1556 I810_BM_PUT8(I810_BASE_PCM_OUT + I810_OFFSET_CR, 0x0);
1558 1557 I810_BM_PUT8(I810_BASE_MIC + I810_OFFSET_CR, 0x0);
1559 1558
1560 1559 /* and then reset the bus master registers for a three DMA engines */
1561 1560 I810_BM_PUT8(I810_BASE_PCM_IN + I810_OFFSET_CR, I810_BM_CR_RST);
1562 1561 I810_BM_PUT8(I810_BASE_PCM_OUT + I810_OFFSET_CR, I810_BM_CR_RST);
1563 1562 I810_BM_PUT8(I810_BASE_MIC + I810_OFFSET_CR, I810_BM_CR_RST);
1564 1563 }
1565 1564
1566 1565
1567 1566 /*
1568 1567 * audio810_codec_sync()
1569 1568 *
1570 1569 * Description:
1571 1570 * Serialize access to the AC97 audio mixer registers.
1572 1571 *
1573 1572 * Arguments:
1574 1573 * audio810_state_t *state The device's state structure
1575 1574 *
1576 1575 * Returns:
1577 1576 * DDI_SUCCESS Ready for an I/O access to the codec
1578 1577 * DDI_FAILURE An I/O access is currently in progress, can't
1579 1578 * perform another I/O access.
1580 1579 */
1581 1580 static int
1582 1581 audio810_codec_sync(audio810_state_t *statep)
1583 1582 {
1584 1583 int i;
1585 1584 uint16_t casr;
1586 1585
1587 1586 for (i = 0; i < 300; i++) {
1588 1587 casr = I810_BM_GET8(I810_REG_CASR);
1589 1588 if ((casr & 1) == 0) {
1590 1589 return (DDI_SUCCESS);
1591 1590 }
1592 1591 drv_usecwait(10);
1593 1592 }
1594 1593
1595 1594 return (DDI_FAILURE);
1596 1595 }
1597 1596
1598 1597 /*
1599 1598 * audio810_write_ac97()
1600 1599 *
1601 1600 * Description:
1602 1601 * Set the specific AC97 Codec register.
1603 1602 *
1604 1603 * Arguments:
1605 1604 * void *arg The device's state structure
1606 1605 * uint8_t reg AC97 register number
1607 1606 * uint16_t data The data want to be set
1608 1607 */
1609 1608 static void
1610 1609 audio810_write_ac97(void *arg, uint8_t reg, uint16_t data)
1611 1610 {
1612 1611 audio810_state_t *statep = arg;
1613 1612
1614 1613 if (audio810_codec_sync(statep) == DDI_SUCCESS) {
1615 1614 I810_AM_PUT16(reg, data);
1616 1615 }
1617 1616
1618 1617 (void) audio810_read_ac97(statep, reg);
1619 1618 }
1620 1619
1621 1620 /*
1622 1621 * audio810_read_ac97()
1623 1622 *
1624 1623 * Description:
1625 1624 * Get the specific AC97 Codec register.
1626 1625 *
1627 1626 * Arguments:
1628 1627 * void *arg The device's state structure
1629 1628 * uint8_t reg AC97 register number
1630 1629 *
1631 1630 * Returns:
1632 1631 * The register value.
1633 1632 */
1634 1633 static uint16_t
1635 1634 audio810_read_ac97(void *arg, uint8_t reg)
1636 1635 {
1637 1636 audio810_state_t *statep = arg;
1638 1637 uint16_t val = 0xffff;
1639 1638
1640 1639 if (audio810_codec_sync(statep) == DDI_SUCCESS) {
1641 1640 val = I810_AM_GET16(reg);
1642 1641 }
1643 1642 return (val);
1644 1643 }
1645 1644
1646 1645 /*
1647 1646 * audio810_destroy()
1648 1647 *
1649 1648 * Description:
1650 1649 * This routine releases all resources held by the device instance,
1651 1650 * as part of either detach or a failure in attach.
1652 1651 *
1653 1652 * Arguments:
1654 1653 * audio810_state_t *state The device soft state.
1655 1654 */
1656 1655 void
1657 1656 audio810_destroy(audio810_state_t *statep)
1658 1657 {
1659 1658 /* stop DMA engines */
1660 1659 audio810_stop_dma(statep);
1661 1660
1662 1661 for (int i = 0; i < I810_NUM_PORTS; i++) {
1663 1662 audio810_free_port(statep->ports[i]);
1664 1663 }
1665 1664
1666 1665 audio810_unmap_regs(statep);
1667 1666
1668 1667 if (statep->ac97)
1669 1668 ac97_free(statep->ac97);
1670 1669
1671 1670 if (statep->adev)
1672 1671 audio_dev_free(statep->adev);
1673 1672
1674 1673 kmem_free(statep, sizeof (*statep));
1675 1674 }
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