10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _SYS_ECPPVAR_H
28 #define _SYS_ECPPVAR_H
29
30 #pragma ident "%Z%%M% %I% %E% SMI"
31
32 #include <sys/note.h>
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 struct ecppunit;
39
40 /*
41 * Hardware-abstraction structure
42 */
43 struct ecpp_hw {
44 int (*map_regs)(struct ecppunit *); /* map registers */
45 void (*unmap_regs)(struct ecppunit *); /* unmap registers */
46 int (*config_chip)(struct ecppunit *); /* configure SuperIO */
47 void (*config_mode)(struct ecppunit *); /* config new mode */
48 void (*mask_intr)(struct ecppunit *); /* mask interrupts */
49 void (*unmask_intr)(struct ecppunit *); /* unmask interrupts */
50 int (*dma_start)(struct ecppunit *); /* start DMA transfer */
51 int (*dma_stop)(struct ecppunit *, size_t *); /* stop DMA xfer */
79 ddi_acc_handle_t d_handle; /* handle for isa space */
80 uint8_t chn; /* 8237 dma channel */
81 int isadma_entered; /* Southbridge DMA workaround */
82 };
83
84 #if defined(__x86)
85 struct ecpp_x86 {
86 uint8_t chn;
87 };
88 #endif
89
90 /*
91 * Hardware binding structure
92 */
93 struct ecpp_hw_bind {
94 char *name; /* binding name */
95 struct ecpp_hw *hw; /* hw description */
96 char *info; /* info string */
97 };
98
99 /*
100 * ecpp soft state structure
101 */
102 struct ecppunit {
103 kmutex_t umutex; /* lock for this structure */
104 int instance; /* instance number */
105 dev_info_t *dip; /* device information */
106 ddi_iblock_cookie_t ecpp_trap_cookie; /* interrupt cookie */
107 boolean_t e_busy; /* ecpp busy flag */
108 kcondvar_t pport_cv; /* cv to signal idle state */
109 /*
110 * common SuperIO registers
111 */
112 struct info_reg *i_reg; /* info registers */
113 struct fifo_reg *f_reg; /* fifo register */
114 ddi_acc_handle_t i_handle;
115 ddi_acc_handle_t f_handle;
116 /*
117 * DMA support
118 */
119 ddi_dma_handle_t dma_handle; /* DMA handle */
120 ddi_dma_cookie_t dma_cookie; /* current cookie */
121 uint_t dma_cookie_count; /* # of cookies */
122 uint_t dma_nwin; /* # of DMA windows */
123 uint_t dma_curwin; /* current window number */
124 uint_t dma_dir; /* transfer direction */
125 /*
126 * hardware-dependent stuff
127 */
261 #define ECPP_PHASE_NIBT_REVINTR 0x23 /* nibble/byte reverse interrupt */
262
263 #define ECPP_PHASE_ECP_SETUP 0x30 /* ecp setup */
264 #define ECPP_PHASE_ECP_FWD_XFER 0x31 /* ecp forward transfer */
265 #define ECPP_PHASE_ECP_FWD_IDLE 0x32 /* ecp forward idle */
266 #define ECPP_PHASE_ECP_FWD_REV 0x33 /* ecp forward to reverse */
267 #define ECPP_PHASE_ECP_REV_XFER 0x34 /* ecp reverse transfer */
268 #define ECPP_PHASE_ECP_REV_IDLE 0x35 /* ecp reverse idle */
269 #define ECPP_PHASE_ECP_REV_FWD 0x36 /* ecp reverse to forward */
270
271 #define ECPP_PHASE_EPP_INIT_IDLE 0x40 /* epp init phase */
272 #define ECPP_PHASE_EPP_IDLE 0x41 /* epp all-round phase */
273
274 #define FAILURE_PHASE 0x80
275 #define UNDEFINED_PHASE 0x81
276
277 /* ecpp return values */
278 #define SUCCESS 1
279 #define FAILURE 2
280
281 /* ecpp e_busy states */
282 #define ECPP_IDLE 1 /* No ongoing transfers */
283 #define ECPP_BUSY 2 /* Ongoing transfers on the cable */
284 #define ECPP_DATA 3 /* Not used */
285 #define ECPP_ERR 4 /* Bad status in Centronics mode */
286 #define ECPP_FLUSH 5 /* Currently flushing the q */
287
288 #define TRUE 1
289 #define FALSE 0
290
291 /* message type */
292 #define ECPP_BACKCHANNEL 0x45
293
294 /* transfer modes */
295 #define ECPP_DMA 0x1
296 #define ECPP_PIO 0x2
297
298 /* tuneable timing defaults */
299 #define CENTRONICS_RETRY 750 /* 750 milliseconds */
300 #define WAIT_FOR_BUSY 1000 /* 1000 microseconds */
301 #define SUSPEND_TOUT 10 /* # seconds before suspend fails */
302
303 /* Centronics hanshaking defaults */
304 #define DATA_SETUP_TIME 2 /* 2 uSec Data Setup Time (2x min) */
305 #define STROBE_PULSE_WIDTH 2 /* 2 uSec Strobe Pulse (2x min) */
306
307 /* 1284 Extensibility Request values */
|
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _SYS_ECPPVAR_H
28 #define _SYS_ECPPVAR_H
29
30 #include <sys/note.h>
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 struct ecppunit;
37
38 /*
39 * Hardware-abstraction structure
40 */
41 struct ecpp_hw {
42 int (*map_regs)(struct ecppunit *); /* map registers */
43 void (*unmap_regs)(struct ecppunit *); /* unmap registers */
44 int (*config_chip)(struct ecppunit *); /* configure SuperIO */
45 void (*config_mode)(struct ecppunit *); /* config new mode */
46 void (*mask_intr)(struct ecppunit *); /* mask interrupts */
47 void (*unmask_intr)(struct ecppunit *); /* unmask interrupts */
48 int (*dma_start)(struct ecppunit *); /* start DMA transfer */
49 int (*dma_stop)(struct ecppunit *, size_t *); /* stop DMA xfer */
77 ddi_acc_handle_t d_handle; /* handle for isa space */
78 uint8_t chn; /* 8237 dma channel */
79 int isadma_entered; /* Southbridge DMA workaround */
80 };
81
82 #if defined(__x86)
83 struct ecpp_x86 {
84 uint8_t chn;
85 };
86 #endif
87
88 /*
89 * Hardware binding structure
90 */
91 struct ecpp_hw_bind {
92 char *name; /* binding name */
93 struct ecpp_hw *hw; /* hw description */
94 char *info; /* info string */
95 };
96
97 /* ecpp e_busy states */
98 typedef enum {
99 ECPP_IDLE = 1, /* No ongoing transfers */
100 ECPP_BUSY = 2, /* Ongoing transfers on the cable */
101 ECPP_DATA = 3, /* Not used */
102 ECPP_ERR = 4, /* Bad status in Centronics mode */
103 ECPP_FLUSH = 5 /* Currently flushing the q */
104 } ecpp_busy_t;
105
106 /*
107 * ecpp soft state structure
108 */
109 struct ecppunit {
110 kmutex_t umutex; /* lock for this structure */
111 int instance; /* instance number */
112 dev_info_t *dip; /* device information */
113 ddi_iblock_cookie_t ecpp_trap_cookie; /* interrupt cookie */
114 ecpp_busy_t e_busy; /* ecpp busy flag */
115 kcondvar_t pport_cv; /* cv to signal idle state */
116 /*
117 * common SuperIO registers
118 */
119 struct info_reg *i_reg; /* info registers */
120 struct fifo_reg *f_reg; /* fifo register */
121 ddi_acc_handle_t i_handle;
122 ddi_acc_handle_t f_handle;
123 /*
124 * DMA support
125 */
126 ddi_dma_handle_t dma_handle; /* DMA handle */
127 ddi_dma_cookie_t dma_cookie; /* current cookie */
128 uint_t dma_cookie_count; /* # of cookies */
129 uint_t dma_nwin; /* # of DMA windows */
130 uint_t dma_curwin; /* current window number */
131 uint_t dma_dir; /* transfer direction */
132 /*
133 * hardware-dependent stuff
134 */
268 #define ECPP_PHASE_NIBT_REVINTR 0x23 /* nibble/byte reverse interrupt */
269
270 #define ECPP_PHASE_ECP_SETUP 0x30 /* ecp setup */
271 #define ECPP_PHASE_ECP_FWD_XFER 0x31 /* ecp forward transfer */
272 #define ECPP_PHASE_ECP_FWD_IDLE 0x32 /* ecp forward idle */
273 #define ECPP_PHASE_ECP_FWD_REV 0x33 /* ecp forward to reverse */
274 #define ECPP_PHASE_ECP_REV_XFER 0x34 /* ecp reverse transfer */
275 #define ECPP_PHASE_ECP_REV_IDLE 0x35 /* ecp reverse idle */
276 #define ECPP_PHASE_ECP_REV_FWD 0x36 /* ecp reverse to forward */
277
278 #define ECPP_PHASE_EPP_INIT_IDLE 0x40 /* epp init phase */
279 #define ECPP_PHASE_EPP_IDLE 0x41 /* epp all-round phase */
280
281 #define FAILURE_PHASE 0x80
282 #define UNDEFINED_PHASE 0x81
283
284 /* ecpp return values */
285 #define SUCCESS 1
286 #define FAILURE 2
287
288 #define TRUE 1
289 #define FALSE 0
290
291 /* message type */
292 #define ECPP_BACKCHANNEL 0x45
293
294 /* transfer modes */
295 #define ECPP_DMA 0x1
296 #define ECPP_PIO 0x2
297
298 /* tuneable timing defaults */
299 #define CENTRONICS_RETRY 750 /* 750 milliseconds */
300 #define WAIT_FOR_BUSY 1000 /* 1000 microseconds */
301 #define SUSPEND_TOUT 10 /* # seconds before suspend fails */
302
303 /* Centronics hanshaking defaults */
304 #define DATA_SETUP_TIME 2 /* 2 uSec Data Setup Time (2x min) */
305 #define STROBE_PULSE_WIDTH 2 /* 2 uSec Strobe Pulse (2x min) */
306
307 /* 1284 Extensibility Request values */
|