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11210 libm should be cstyle(1ONBLD) clean
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--- old/usr/src/lib/libm/sparc/src/libm_inlines.h
+++ new/usr/src/lib/libm/sparc/src/libm_inlines.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
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27 27 /*
28 28 * Copyright 2011, Richard Lowe.
29 29 */
30 30
31 31 /* Functions in this file are duplicated in locallibm.il. Keep them in sync */
32 32
33 33 #ifndef _LIBM_INLINES_H
34 34 #define _LIBM_INLINES_H
35 35
36 36 #ifdef __GNUC__
37 -
38 37 #include <sys/types.h>
39 38 #include <sys/ieeefp.h>
40 39
41 40 #ifdef __cplusplus
42 41 extern "C" {
43 42 #endif
44 43
45 44 extern __GNU_INLINE double
46 45 __inline_sqrt(double d)
47 46 {
48 47 double ret;
49 48
50 49 __asm__ __volatile__("fsqrtd %1,%0\n\t" : "=e" (ret) : "e" (d));
51 50 return (ret);
52 51 }
53 52
54 53 extern __GNU_INLINE float
55 54 __inline_sqrtf(float f)
56 55 {
57 56 float ret;
58 57
59 58 __asm__ __volatile__("fsqrts %1,%0\n\t" : "=f" (ret) : "f" (f));
60 59 return (ret);
61 60 }
62 61
63 62 extern __GNU_INLINE enum fp_class_type
64 63 fp_classf(float f)
65 64 {
66 65 enum fp_class_type ret;
67 66 uint32_t tmp;
68 67
69 68 /* XXX: Separate input and output */
70 69 __asm__ __volatile__(
71 70 "sethi %%hi(0x80000000),%1\n\t"
72 71 "andncc %2,%1,%0\n\t"
73 72 "bne 1f\n\t"
74 73 "nop\n\t"
75 74 "mov 0,%0\n\t"
76 75 "ba 2f\n\t" /* x is 0 */
77 76 "nop\n\t"
78 77 "1:\n\t"
79 78 "sethi %%hi(0x7f800000),%1\n\t"
80 79 "andcc %0,%1,%%g0\n\t"
81 80 "bne 1f\n\t"
82 81 "nop\n\t"
83 82 "mov 1,%0\n\t"
84 83 "ba 2f\n\t" /* x is subnormal */
85 84 "nop\n\t"
86 85 "1:\n\t"
87 86 "cmp %0,%1\n\t"
88 87 "bge 1f\n\t"
89 88 "nop\n\t"
90 89 "mov 2,%0\n\t"
91 90 "ba 2f\n\t" /* x is normal */
92 91 "nop\n\t"
93 92 "1:\n\t"
94 93 "bg 1f\n\t"
95 94 "nop\n\t"
96 95 "mov 3,%0\n\t"
97 96 "ba 2f\n\t" /* x is __infinity */
98 97 "nop\n\t"
99 98 "1:\n\t"
100 99 "sethi %%hi(0x00400000),%1\n\t"
101 100 "andcc %0,%1,%%g0\n\t"
102 101 "mov 4,%0\n\t" /* x is quiet NaN */
103 102 "bne 2f\n\t"
104 103 "nop\n\t"
105 104 "mov 5,%0\n\t" /* x is signaling NaN */
106 105 "2:\n\t"
107 106 : "=r" (ret), "=&r" (tmp)
108 107 : "r" (f)
109 108 : "cc");
110 109 return (ret);
111 110 }
112 111
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113 112 #define _HI_WORD(x) ((uint32_t *)&x)[0]
114 113 #define _LO_WORD(x) ((uint32_t *)&x)[1]
115 114
116 115 extern __GNU_INLINE enum fp_class_type
117 116 fp_class(double d)
118 117 {
119 118 enum fp_class_type ret;
120 119 uint32_t tmp;
121 120
122 121 __asm__ __volatile__(
123 - "sethi %%hi(0x80000000),%1\n\t" /* %1 gets 80000000 */
124 - "andn %2,%1,%0\n\t" /* %2-%0 gets abs(x) */
125 - "orcc %0,%3,%%g0\n\t" /* set cc as x is zero/nonzero */
126 - "bne 1f\n\t" /* branch if x is nonzero */
122 + "sethi %%hi(0x80000000),%1\n\t" /* %1 gets 80000000 */
123 + "andn %2,%1,%0\n\t" /* %2-%0 gets abs(x) */
124 + "orcc %0,%3,%%g0\n\t" /* set cc as x is zero/nonzero */
125 + "bne 1f\n\t" /* branch if x is nonzero */
127 126 "nop\n\t"
128 127 "mov 0,%0\n\t"
129 - "ba 2f\n\t" /* x is 0 */
128 + "ba 2f\n\t" /* x is 0 */
130 129 "nop\n\t"
131 130 "1:\n\t"
132 - "sethi %%hi(0x7ff00000),%1\n\t" /* %1 gets 7ff00000 */
133 - "andcc %0,%1,%%g0\n\t" /* cc set by __exp field of x */
134 - "bne 1f\n\t" /* branch if normal or max __exp */
131 + "sethi %%hi(0x7ff00000),%1\n\t" /* %1 gets 7ff00000 */
132 + "andcc %0,%1,%%g0\n\t" /* cc set by __exp field of x */
133 + "bne 1f\n\t" /* branch if normal or max __exp */
135 134 "nop\n\t"
136 135 "mov 1,%0\n\t"
137 - "ba 2f\n\t" /* x is subnormal */
136 + "ba 2f\n\t" /* x is subnormal */
138 137 "nop\n\t"
139 138 "1:\n\t"
140 139 "cmp %0,%1\n\t"
141 - "bge 1f\n\t" /* branch if x is max __exp */
140 + "bge 1f\n\t" /* branch if x is max __exp */
142 141 "nop\n\t"
143 142 "mov 2,%0\n\t"
144 - "ba 2f\n\t" /* x is normal */
143 + "ba 2f\n\t" /* x is normal */
145 144 "nop\n\t"
146 145 "1:\n\t"
147 - "andn %0,%1,%0\n\t" /* o0 gets msw __significand field */
148 - "orcc %0,%3,%%g0\n\t" /* set cc by OR __significand */
149 - "bne 1f\n\t" /* Branch if __nan */
146 + "andn %0,%1,%0\n\t" /* o0 gets msw __significand field */
147 + "orcc %0,%3,%%g0\n\t" /* set cc by OR __significand */
148 + "bne 1f\n\t" /* Branch if __nan */
150 149 "nop\n\t"
151 150 "mov 3,%0\n\t"
152 - "ba 2f\n\t" /* x is __infinity */
151 + "ba 2f\n\t" /* x is __infinity */
153 152 "nop\n\t"
154 153 "1:\n\t"
155 154 "sethi %%hi(0x00080000),%1\n\t"
156 - "andcc %0,%1,%%g0\n\t" /* set cc by quiet/sig bit */
157 - "be 1f\n\t" /* Branch if signaling */
155 + "andcc %0,%1,%%g0\n\t" /* set cc by quiet/sig bit */
156 + "be 1f\n\t" /* Branch if signaling */
158 157 "nop\n\t"
159 - "mov 4,%0\n\t" /* x is quiet NaN */
158 + "mov 4,%0\n\t" /* x is quiet NaN */
160 159 "ba 2f\n\t"
161 160 "nop\n\t"
162 161 "1:\n\t"
163 - "mov 5,%0\n\t" /* x is signaling NaN */
162 + "mov 5,%0\n\t" /* x is signaling NaN */
164 163 "2:\n\t"
165 164 : "=&r" (ret), "=&r" (tmp)
166 165 : "r" (_HI_WORD(d)), "r" (_LO_WORD(d))
167 166 : "cc");
168 167
169 168 return (ret);
170 169 }
171 170
172 171 extern __GNU_INLINE int
173 172 __swapEX(int i)
174 173 {
175 174 int ret;
176 175 uint32_t fsr;
177 176 uint32_t tmp1, tmp2;
178 177
179 178 __asm__ __volatile__(
180 179 "and %4,0x1f,%2\n\t" /* tmp1 = %2 = %o1 */
181 180 "sll %2,5,%2\n\t" /* shift input to aexc bit location */
182 181 ".volatile\n\t"
183 182 "st %%fsr,%1\n\t"
184 183 "ld %1,%0\n\t" /* %0 = fsr */
185 184 "andn %0,0x3e0,%3\n\t" /* tmp2 = %3 = %o2 */
186 185 "or %2,%3,%2\n\t" /* %2 = new fsr */
187 186 "st %2,%1\n\t"
188 187 "ld %1,%%fsr\n\t"
189 188 "srl %0,5,%0\n\t"
190 189 "and %0,0x1f,%0\n\t" /* %0 = ret = %o0 */
191 190 ".nonvolatile\n\t"
192 191 : "=r" (ret), "=m" (fsr), "=r" (tmp1), "=r" (tmp2)
193 192 : "r" (i)
194 193 : "cc");
195 194
196 195 return (ret);
197 196 }
198 197
199 198 /*
200 199 * On the SPARC, __swapRP is a no-op; always return 0 for backward
201 200 * compatibility
202 201 */
203 202 /* ARGSUSED */
204 203 extern __GNU_INLINE enum fp_precision_type
205 204 __swapRP(enum fp_precision_type i)
206 205 {
207 206 return (0);
208 207 }
209 208
210 209 extern __GNU_INLINE enum fp_direction_type
211 210 __swapRD(enum fp_direction_type d)
212 211 {
213 212 enum fp_direction_type ret;
214 213 uint32_t fsr;
215 214 uint32_t tmp1, tmp2, tmp3;
216 215
217 216 __asm__ __volatile__(
218 217 "and %5,0x3,%0\n\t"
219 218 "sll %0,30,%2\n\t" /* shift input to RD bit location */
220 219 ".volatile\n\t"
221 220 "st %%fsr,%1\n\t"
222 221 "ld %1,%0\n\t" /* %0 = fsr */
223 222 "set 0xc0000000,%4\n\t" /* mask of rounding direction bits */
224 223 "andn %0,%4,%3\n\t"
225 224 "or %2,%3,%2\n\t" /* %2 = new fsr */
226 225 "st %2,%1\n\t"
227 226 "ld %1,%%fsr\n\t"
228 227 "srl %0,30,%0\n\t"
229 228 "and %0,0x3,%0\n\t"
230 229 ".nonvolatile\n\t"
231 230 : "=r" (ret), "=m" (fsr), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
232 231 : "r" (d)
233 232 : "cc");
234 233
235 234 return (ret);
236 235 }
237 236
238 237 extern __GNU_INLINE int
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239 238 __swapTE(int i)
240 239 {
241 240 int ret;
242 241 uint32_t fsr, tmp1, tmp2;
243 242
244 243 __asm__ __volatile__(
245 244 "and %4,0x1f,%0\n\t"
246 245 "sll %0,23,%2\n\t" /* shift input to TEM bit location */
247 246 ".volatile\n\t"
248 247 "st %%fsr,%1\n\t"
249 - "ld %1,%0\n\t" /* %0 = fsr */
250 - "set 0x0f800000,%3\n\t" /* mask of TEM (Trap Enable Mode bits) */
248 + "ld %1,%0\n\t" /* %0 = fsr */
249 + "set 0x0f800000,%3\n\t" /* mask of TEM (Trap Enable Mode bits) */
251 250 "andn %0,%3,%3\n\t"
252 251 "or %2,%3,%2\n\t" /* %2 = new fsr */
253 252 "st %2,%1\n\t"
254 253 "ld %1,%%fsr\n\t"
255 254 "srl %0,23,%0\n\t"
256 255 "and %0,0x1f,%0\n\t"
257 256 ".nonvolatile\n\t"
258 257 : "=r" (ret), "=m" (fsr), "=r" (tmp1), "=r" (tmp2)
259 258 : "r" (i)
260 259 : "cc");
261 260
262 261 return (ret);
263 262 }
264 263
265 264 extern __GNU_INLINE double
266 265 sqrt(double d)
267 266 {
268 267 return (__inline_sqrt(d));
269 268 }
270 269
271 270 extern __GNU_INLINE float
272 271 sqrtf(float f)
273 272 {
274 273 return (__inline_sqrtf(f));
275 274 }
276 275
277 276 extern __GNU_INLINE double
278 277 fabs(double d)
279 278 {
280 279 double ret;
281 280
282 281 __asm__ __volatile__("fabsd %1,%0\n\t" : "=e" (ret) : "e" (d));
283 282 return (ret);
284 283 }
285 284
286 285 extern __GNU_INLINE float
287 286 fabsf(float f)
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288 287 {
289 288 float ret;
290 289
291 290 __asm__ __volatile__("fabss %1,%0\n\t" : "=f" (ret) : "f" (f));
292 291 return (ret);
293 292 }
294 293
295 294 #ifdef __cplusplus
296 295 }
297 296 #endif
298 -
299 297 #endif /* __GNUC */
300 -
301 298 #endif /* _LIBM_INLINES_H */
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