1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 #ifndef _NV_SATA_H
27 #define _NV_SATA_H
28
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34
35 /*
36 * SGPIO Support
37 * Enable SGPIO support only on x86/x64, because it is implemented using
38 * functions that are only available on x86/x64.
39 */
40
41 #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports
42
43 typedef struct nv_port nv_port_t;
44
45 #ifdef SGPIO_SUPPORT
46 typedef struct nv_sgp_cmn nv_sgp_cmn_t;
47 #endif
48
49 /*
50 * sizes of strings to allocate
51 */
52 #define NV_STR_LEN 10
53 #define NV_LOGBUF_LEN 512
54 #define NV_REASON_LEN 30
55
56
57 typedef struct nv_ctl {
58 /*
59 * Each of these are specific to the chipset in use.
60 */
61 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2);
62 void (*nvc_reg_init)(struct nv_ctl *nvc,
63 ddi_acc_handle_t pci_conf_handle);
64
65 dev_info_t *nvc_dip; /* devinfo pointer of controller */
66
67 struct nv_port *nvc_port; /* array of pointers to port struct */
68
69 /*
70 * handle and base address to register space.
71 *
72 * 0: port 0 task file
73 * 1: port 0 status
74 * 2: port 1 task file
75 * 3: port 1 status
76 * 4: bus master for both ports
77 * 5: extended registers for SATA features
78 */
79 ddi_acc_handle_t nvc_bar_hdl[6];
80 uchar_t *nvc_bar_addr[6];
81
82 /*
83 * sata registers in bar 5 which are shared on all devices
84 * on the channel.
85 */
86 uint32_t *nvc_mcp5x_ctl;
87 uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */
88
89 kmutex_t nvc_mutex; /* ctrl level lock */
90
91 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */
92 int nvc_intr_type; /* What type of interrupt */
93 int nvc_intr_cnt; /* # of intrs count returned */
94 size_t nvc_intr_size; /* Size of intr array to */
95 uint_t nvc_intr_pri; /* Interrupt priority */
96 int nvc_intr_cap; /* Interrupt capabilities */
97 uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */
98
99 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
100
101 /*
102 * enable/disable interrupts, controller specific
103 */
104 void (*nvc_set_intr)(nv_port_t *nvp, int flag);
105 int nvc_state; /* state flags of ctrl see below */
106 uint8_t nvc_revid; /* PCI revid of device */
107 boolean_t dma_40bit; /* 40bit DMA support */
108
109 #ifdef SGPIO_SUPPORT
110 int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */
111 uint8_t nvc_ctlr_num; /* controller number within the part */
112 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */
113 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
114 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */
115 #endif
116 } nv_ctl_t;
117
118
119 struct nv_port {
120
121 struct nv_ctl *nvp_ctlp; /* back pointer to controller */
122
123 uint8_t nvp_port_num; /* port number, ie 0 or 1 */
124
125 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
126 uint32_t nvp_signature; /* sig acquired from task file regs */
127 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */
128 uchar_t *nvp_bm_addr; /* base addr for bus master for port */
129 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */
130
131 ddi_acc_handle_t nvp_cmd_hdl;
132 uchar_t *nvp_data; /* data register */
133 uchar_t *nvp_error; /* error register (read) */
134 uchar_t *nvp_feature; /* features (write) */
135 uchar_t *nvp_count; /* sector count */
136 uchar_t *nvp_sect; /* sector number */
137 uchar_t *nvp_lcyl; /* cylinder low byte */
138 uchar_t *nvp_hcyl; /* cylinder high byte */
139 uchar_t *nvp_drvhd; /* drive/head register */
140 uchar_t *nvp_status; /* status/command register */
141 uchar_t *nvp_cmd; /* status/command register */
142
143 ddi_acc_handle_t nvp_ctl_hdl;
144 uchar_t *nvp_altstatus; /* alternate status (read) */
145 uchar_t *nvp_devctl; /* device control (write) */
146
147 ddi_acc_handle_t nvp_bm_hdl;
148 uchar_t *nvp_bmisx;
149 uint32_t *nvp_bmidtpx;
150 uchar_t *nvp_bmicx;
151
152 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */
153 caddr_t *nvp_sg_addr; /* virtual addr of prd table */
154 uint32_t *nvp_sg_paddr; /* physical address of prd table */
155 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */
156
157 uint32_t *nvp_sstatus;
158 uint32_t *nvp_serror;
159 uint32_t *nvp_sctrl;
160 uint32_t *nvp_sactive;
161
162 kmutex_t nvp_mutex; /* main per port mutex */
163 kcondvar_t nvp_sync_cv; /* handshake btwn ISR and start thrd */
164 kcondvar_t nvp_reset_cv; /* when reset is synchronous */
165
166 /*
167 * nvp_slot is a pointer to an array of nv_slot
168 */
169 struct nv_slot *nvp_slot;
170 uint32_t nvp_sactive_cache; /* cache of SACTIVE */
171 uint8_t nvp_queue_depth;
172
173 /*
174 * NCQ flow control. During NCQ operation, no other commands
175 * allowed. The following are used to enforce this.
176 */
177 int nvp_ncq_run;
178 int nvp_non_ncq_run;
179 int nvp_seq;
180
181 timeout_id_t nvp_timeout_id;
182
183 clock_t nvp_reset_time; /* time of last reset */
184 clock_t nvp_link_event_time; /* time of last plug event */
185 int nvp_reset_retry_count;
186 clock_t nvp_wait_sig; /* wait before rechecking sig */
187
188 int nvp_state; /* state of port. flags defined below */
189
190 uint16_t *nvp_mcp5x_int_status;
191 uint16_t *nvp_mcp5x_int_ctl;
192
193 #ifdef SGPIO_SUPPORT
194 uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */
195 #endif
196 clock_t nvp_timeout_duration;
197
198
199 /*
200 * debug and statistical information
201 */
202 clock_t nvp_rem_time;
203 clock_t nvp_add_time;
204 clock_t nvp_trans_link_time;
205 int nvp_trans_link_count;
206
207 uint8_t nvp_last_cmd;
208 uint8_t nvp_previous_cmd;
209 int nvp_reset_count;
210 char nvp_first_reset_reason[NV_REASON_LEN];
211 char nvp_reset_reason[NV_REASON_LEN];
212 clock_t intr_duration; /* max length of port intr (ticks) */
213 clock_t intr_start_time;
214 int intr_loop_cnt;
215 };
216
217
218 typedef struct nv_device_table {
219 ushort_t vendor_id; /* vendor id */
220 ushort_t device_id; /* device id */
221 ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */
222 } nv_device_table_t;
223
224
225 typedef struct nv_slot {
226 caddr_t nvslot_v_addr; /* I/O buffer address */
227 size_t nvslot_byte_count; /* # bytes left to read/write */
228 sata_pkt_t *nvslot_spkt;
229 uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN];
230 clock_t nvslot_stime;
231 int (*nvslot_start)(nv_port_t *nvp, int queue);
232 void (*nvslot_intr)(nv_port_t *nvp,
233 struct nv_slot *nv_slotp);
234 uint32_t nvslot_flags;
235 } nv_slot_t;
236
237
238 #ifdef SGPIO_SUPPORT
239 struct nv_sgp_cmn {
240 uint8_t nvs_in_use; /* bit-field of active ctlrs */
241 uint8_t nvs_connected; /* port connected bit-field flag */
242 uint8_t nvs_activity; /* port usage bit-field flag */
243 int nvs_cbp; /* SGPIO Control Block Pointer */
244 int nvs_taskq_delay; /* rest time for activity LED taskq */
245 kmutex_t nvs_slock; /* lock for shared data */
246 kmutex_t nvs_tlock; /* lock for taskq */
247 kcondvar_t nvs_cv; /* condition variable for taskq wait */
248 ddi_taskq_t *nvs_taskq; /* activity LED taskq */
249 };
250
251 struct nv_sgp_cbp2cmn {
252 uint32_t c2cm_cbp; /* ctlr block ptr from pci cfg space */
253 nv_sgp_cmn_t *c2cm_cmn; /* point to common space */
254 };
255 #endif
256
257
258 /*
259 * nvslot_flags
260 */
261 #define NVSLOT_COMPLETE 0x01
262 #define NVSLOT_NCQ 0x02 /* NCQ is active */
263 #define NVSLOT_RQSENSE 0x04 /* processing request sense */
264
265 /*
266 * state values for nv_attach
267 */
268 #define ATTACH_PROGRESS_NONE (1 << 0)
269 #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1)
270 #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2)
271 #define ATTACH_PROGRESS_BARS (1 << 3)
272 #define ATTACH_PROGRESS_INTR_ADDED (1 << 4)
273 #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5)
274 #define ATTACH_PROGRESS_CTL_SETUP (1 << 6)
275 #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7)
276 #define ATTACH_PROGRESS_COUNT (1 << 8)
277 #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9)
278 #define ATTACH_PROGRESS_SATA_MODULE (1 << 10)
279
280 #ifdef DEBUG
281
282 #define NV_DEBUG 1
283
284 #endif /* DEBUG */
285
286
287 /*
288 * nv_debug_flags
289 */
290 #define NVDBG_ALWAYS 0x00001
291 #define NVDBG_INIT 0x00002
292 #define NVDBG_ENTRY 0x00004
293 #define NVDBG_DELIVER 0x00008
294 #define NVDBG_EVENT 0x00010
295 #define NVDBG_SYNC 0x00020
296 #define NVDBG_PKTCOMP 0x00040
297 #define NVDBG_TIMEOUT 0x00080
298 #define NVDBG_INFO 0x00100
299 #define NVDBG_VERBOSE 0x00200
300 #define NVDBG_INTR 0x00400
301 #define NVDBG_ERRS 0x00800
302 #define NVDBG_COOKIES 0x01000
303 #define NVDBG_HOT 0x02000
304 #define NVDBG_RESET 0x04000
305 #define NVDBG_ATAPI 0x08000
306
307 #define NVLOG(flag, nvc, nvp, fmt, args ...) \
308 if (nv_debug_flags & (flag)) { \
309 nv_log(nvc, nvp, fmt, ## args); \
310 }
311
312
313 #define NV_SUCCESS 0
314 #define NV_FAILURE -1
315
316 /*
317 * indicates whether nv_wait functions can sleep or not.
318 */
319 #define NV_SLEEP 1
320 #define NV_NOSLEEP 2
321
322
323 /*
324 * port offsets from base address ioaddr1
325 */
326 #define NV_DATA 0x00 /* data register */
327 #define NV_ERROR 0x01 /* error register (read) */
328 #define NV_FEATURE 0x01 /* features (write) */
329 #define NV_COUNT 0x02 /* sector count */
330 #define NV_SECT 0x03 /* sector number */
331 #define NV_LCYL 0x04 /* cylinder low byte */
332 #define NV_HCYL 0x05 /* cylinder high byte */
333 #define NV_DRVHD 0x06 /* drive/head register */
334 #define NV_STATUS 0x07 /* status/command register */
335 #define NV_CMD 0x07 /* status/command register */
336
337 /*
338 * port offsets from base address ioaddr2
339 */
340 #define NV_ALTSTATUS 0x02 /* alternate status (read) */
341 #define NV_DEVCTL 0x02 /* device control (write) */
342
343 /*
344 * device control register
345 */
346 #define ATDC_NIEN 0x02 /* disable interrupts */
347 #define ATDC_SRST 0x04 /* controller reset */
348 #define ATDC_D3 0x08 /* mysterious bit */
349 #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */
350
351 /*
352 * MCP5x NCQ and INTR control registers
353 */
354 #define MCP5X_CTL 0x400 /* queuing control */
355 #define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */
356 #define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */
357 #define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */
358
359 /*
360 * if either of these bits are set, when using NCQ, if no other commands are
361 * active while a new command is started, DMA engine can be programmed ahead
362 * of time to save extra interrupt. Presumably pre-programming is discarded
363 * if a subsequent command ends up finishing first.
364 */
365 #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7)
366 #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23)
367
368 /*
369 * bit definitions to indicate which NCQ command requires
370 * DMA setup.
371 */
372 #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2
373 #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18
374 #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f
375
376
377 /*
378 * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS
379 */
380 #define MCP5X_INT_SNOTIFY 0x200 /* snotification set */
381 #define MCP5X_INT_SERROR 0x100 /* serror set */
382 #define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */
383 #define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */
384 #define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */
385 #define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */
386 #define MCP5X_INT_REM 0x08 /* device removed */
387 #define MCP5X_INT_ADD 0x04 /* device added */
388 #define MCP5X_INT_PM 0x02 /* power changed */
389 #define MCP5X_INT_COMPLETE 0x01 /* device interrupt */
390
391 /*
392 * Bits above that are not used for now.
393 */
394 #define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\
395 MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\
396 MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR)
397
398 /*
399 * Bits for MCP_SATA_AE_CTL
400 */
401 #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */
402 #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */
403
404 #define NV_DELAY_NSEC(wait_ns) \
405 { \
406 hrtime_t start, end; \
407 start = end = gethrtime(); \
408 while ((end - start) < wait_ns) \
409 end = gethrtime(); \
410 }
411
412 /*
413 * signature in task file registers after device reset
414 */
415 #define NV_DISK_SIG 0x00000101
416 #define NV_ATAPI_SIG 0xeb140101
417 #define NV_PM_SIG 0x96690101
418 #define NV_NO_SIG 0x00000000
419
420 /*
421 * These bar5 offsets are common to mcp51/mcp55/ck804 and thus
422 * prefixed with NV.
423 */
424 #define NV_SSTATUS 0x00
425 #define NV_SERROR 0x04
426 #define NV_SCTRL 0x08
427 #define NV_SACTIVE 0x0c
428 #define NV_SNOTIFICATION 0x10
429
430 #define CH0_SREG_OFFSET 0x0
431 #define CH1_SREG_OFFSET 0x40
432
433
434 /*
435 * The following config space offsets are needed to enable
436 * bar 5 register access in ck804/mcp51/mcp55
437 */
438 #define NV_SATA_CFG_20 0x50
439 #define NV_BAR5_SPACE_EN 0x04
440 #define NV_40BIT_PRD 0x20
441
442 #define NV_SATA_CFG_23 0x60
443
444 /*
445 * ck804 interrupt status register
446 */
447
448 /*
449 * offsets to bar 5 registers
450 */
451 #define CK804_SATA_INT_STATUS 0x440
452 #define CK804_SATA_INT_EN 0x441
453
454
455 /*
456 * bit fields for int status and int enable
457 * registers
458 */
459 #define CK804_INT_PDEV_INT 0x01 /* completion interrupt */
460 #define CK804_INT_PDEV_PM 0x02 /* power change */
461 #define CK804_INT_PDEV_ADD 0x04 /* hot plug */
462 #define CK804_INT_PDEV_REM 0x08 /* hot remove */
463 #define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM
464
465 #define CK804_INT_SDEV_INT 0x10 /* completion interrupt */
466 #define CK804_INT_SDEV_PM 0x20 /* power change */
467 #define CK804_INT_SDEV_ADD 0x40 /* hot plug */
468 #define CK804_INT_SDEV_REM 0x80 /* hot remove */
469 #define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM
470
471 #define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\
472 CK804_INT_PDEV_PM
473 #define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\
474 CK804_INT_SDEV_PM
475
476 /*
477 * config space offset 42
478 */
479 #define NV_SATA_CFG_42 0xac
480
481 /*
482 * bit in CFG_42 which delays hotplug interrupt until
483 * PHY ready
484 */
485 #define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12)
486
487
488 /*
489 * bar 5 offsets for SATA registers in ck804
490 */
491 #define CK804_CH1_SSTATUS 0x00
492 #define CK804_CH1_SERROR 0x04
493 #define CK804_CH1_SCTRL 0x08
494 #define CK804_CH1_SACTIVE 0x0c
495 #define CK804_CH1_SNOTIFICATION 0x10
496
497 #define CK804_CH2_SSTATUS 0x40
498 #define CK804_CH2_SERROR 0x44
499 #define CK804_CH2_SCTRL 0x48
500 #define CK804_CH2_SACTIVE 0x4c
501 #define CK804_CH2_SNOTIFICATION 0x50
502
503
504 /*
505 * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55
506 */
507 #define NV_ADMACTL_X 0x4C0
508 #define NV_ADMACTL_Y 0x5C0
509
510 /*
511 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y
512 */
513 #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */
514 #define NV_CH_RST 0x04 /* reset channel */
515
516
517 /*
518 * bar 5 offset for ADMASTAT regs for ck804
519 */
520 #define CK804_ADMASTAT_X 0x4C4
521 #define CK804_ADMASTAT_Y 0x5C4
522
523 /*
524 * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y
525 */
526 #define CK804_HPIRQ 0x4
527 #define MCP05_HUIRQ 0x2
528
529
530 /*
531 * bar 4 offset to bus master command registers
532 */
533 #define BMICX_REG 0
534
535 /*
536 * bit definitions for BMICX_REG
537 */
538 #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */
539 /* 1=Start (Enable) */
540 /* 0=Start (Disable) */
541
542 /*
543 * NOTE: "read" and "write" are the actions of the DMA engine
544 * on the PCI bus, not the SATA bus. Therefore for a ATA READ
545 * command, program the DMA engine to "write to memory" mode
546 * (and vice versa).
547 */
548 #define BMICX_RWCON 0x08 /* Read/Write Control */
549 #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */
550 #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */
551
552 /*
553 * BMICX bits to preserve during updates
554 */
555 #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON))
556
557 /*
558 * bar 4 offset to bus master status register
559 */
560 #define BMISX_REG 2
561
562 /*
563 * bit fields for bus master status register
564 */
565 #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */
566 #define BMISX_IDERR 0x02 /* IDE DMA Error */
567 #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */
568
569 /*
570 * bus master status register bits to preserve
571 */
572 #define BMISX_MASK 0xf8
573
574 /*
575 * bar4 offset to bus master PRD descriptor table
576 */
577 #define BMIDTPX_REG 4
578
579
580 /*
581 * structure for a single entry in the PRD table
582 * (physical region descriptor table)
583 */
584 typedef struct prde {
585 uint32_t p_address; /* physical address */
586 uint32_t p_count; /* byte count, EOT in high order bit */
587 } prde_t;
588
589
590 #define PRDE_EOT ((uint_t)0x80000000)
591
592 #define NV_DMA_NSEGS 257 /* at least 1MB (4KB/pg * 256) + 1 if misaligned */
593
594 /*
595 * ck804 and mcp55 both have 2 ports per controller
596 */
597 #define NV_NUM_PORTS 2
598
599 /*
600 * Number of slots to allocate in data nv_sata structures to handle
601 * multiple commands at once. This does not reflect the capability of
602 * the drive or the hardware, and in many cases will not match.
603 * 1 or 32 slots are allocated, so in cases where the driver has NCQ
604 * enabled but the drive doesn't support it, or supports fewer than
605 * 32 slots, here may be an over allocation of memory.
606 */
607 #ifdef NCQ
608 #define NV_QUEUE_SLOTS 32
609 #else
610 #define NV_QUEUE_SLOTS 1
611 #endif
612
613 #define NV_BM_64K_BOUNDARY 0x10000ull
614
615 #define NV_MAX_INTR_PER_DEV 20 /* Empirical value */
616
617 /*
618 * 1 second (in microseconds)
619 */
620 #define NV_ONE_SEC 1000000
621
622 /*
623 * 1 millisecond (in microseconds)
624 */
625 #define NV_ONE_MSEC 1000
626
627 /*
628 * initial wait before checking for signature, in microseconds
629 */
630 #define NV_WAIT_SIG 2500
631
632
633 /*
634 * Length of port reset (microseconds) - SControl bit 0 set to 1
635 */
636 #define NV_RESET_LENGTH 1000
637
638 /*
639 * the maximum number of comresets to issue while
640 * performing link reset in nv_reset()
641 */
642 #define NV_COMRESET_ATTEMPTS 3
643
644 /*
645 * amount of time to wait for a signature in reset, in ms, before
646 * issuing another reset
647 */
648 #define NV_RETRY_RESET_SIG 5000
649
650 /*
651 * the maximum number of resets to issue to gather signature
652 * before giving up
653 */
654 #define NV_MAX_RESET_RETRY 8
655
656 /*
657 * amount of time (us) to wait after receiving a link event
658 * before acting on it. This is because of flakey hardware
659 * sometimes issues the wrong, multiple, or out of order link
660 * events.
661 */
662 #define NV_LINK_EVENT_SETTLE 500000
663
664 /*
665 * The amount of time (ms) a link can be missing
666 * before declaring it removed.
667 */
668 #define NV_LINK_EVENT_DOWN 200
669
670 /*
671 * nvp_state flags
672 */
673 #define NV_DEACTIVATED 0x001
674 #define NV_ABORTING 0x002
675 #define NV_FAILED 0x004
676 #define NV_RESET 0x008
677 #define NV_RESTORE 0x010
678 #define NV_LINK_EVENT 0x020
679 #define NV_ATTACH 0x040
680 #define NV_HOTPLUG 0x080
681
682
683 /*
684 * flags for nv_report_link_event()
685 */
686 #define NV_ADD_DEV 0
687 #define NV_REM_DEV 1
688
689 /*
690 * nvc_state flags
691 */
692 #define NV_CTRL_SUSPEND 0x1
693
694
695 /*
696 * flags for ck804_set_intr/mcp5x_set_intr
697 */
698 #define NV_INTR_DISABLE 0x1
699 #define NV_INTR_ENABLE 0x2
700 #define NV_INTR_CLEAR_ALL 0x4
701 #define NV_INTR_DISABLE_NON_BLOCKING 0x8
702
703
704 #define NV_BYTES_PER_SEC 512
705
706 #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */
707 #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */
708 #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */
709 #define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */
710
711 /*
712 * definition labels for the BAR registers
713 */
714 #define NV_BAR_0 0 /* chan 0 task file regs */
715 #define NV_BAR_1 1 /* chan 0 status reg */
716 #define NV_BAR_2 2 /* chan 1 task file regs */
717 #define NV_BAR_3 3 /* chan 1 status reg */
718 #define NV_BAR_4 4 /* bus master regs */
719 #define NV_BAR_5 5 /* extra regs mostly SATA related */
720
721 /*
722 * transform seconds to microseconds
723 */
724 #define NV_SEC2USEC(x) x * MICROSEC
725
726
727 /*
728 * ck804 maps in task file regs into bar 5. These are
729 * only used to identify ck804, therefore only this reg is
730 * listed here.
731 */
732 #define NV_BAR5_TRAN_LEN_CH_X 0x518
733
734 /*
735 * if after this many iterations through the interrupt
736 * processing loop, declare the interrupt wedged and
737 * disable.
738 */
739 #define NV_MAX_INTR_LOOP 10
740
741 /*
742 * flag values for nv_copy_regs_out
743 */
744 #define NV_COPY_COMPLETE 0x01 /* normal command completion */
745 #define NV_COPY_ERROR 0x02 /* error, did not complete ok */
746 #define NV_COPY_SSREGS 0x04 /* SS port registers */
747
748 #ifdef SGPIO_SUPPORT
749 #define NV_MAX_CBPS 16 /* Maximum # of Control Block */
750 /* Pointers. Corresponds to */
751 /* each MCP55 and IO55 */
752 #define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */
753 #define SGPIO_TQ_NAME_LEN 32
754
755 /*
756 * The drive number format is ccp (binary).
757 * cc is the controller number (0-based number)
758 * p is the port number (0 or 1)
759 */
760 #define SGP_DRV_TO_PORT(d) ((d) & 1)
761 #define SGP_DRV_TO_CTLR(d) ((d) >> 1)
762 #define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1))
763 #endif
764
765 #ifdef __cplusplus
766 }
767 #endif
768
769 #endif /* _NV_SATA_H */