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8956 Implement KPTI
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
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--- old/usr/src/uts/i86pc/os/intr.c
+++ new/usr/src/uts/i86pc/os/intr.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
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14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
24 - * Copyright (c) 2012, Joyent, Inc. All rights reserverd.
24 + * Copyright (c) 2018 Joyent, Inc. All rights reserverd.
25 25 */
26 26
27 27 /*
28 28 * To understand the present state of interrupt handling on i86pc, we must
29 29 * first consider the history of interrupt controllers and our way of handling
30 30 * interrupts.
31 31 *
32 32 * History of Interrupt Controllers on i86pc
33 33 * -----------------------------------------
34 34 *
35 35 * Intel 8259 and 8259A
36 36 *
37 37 * The first interrupt controller that attained widespread use on i86pc was
38 38 * the Intel 8259(A) Programmable Interrupt Controller that first saw use with
39 39 * the 8086. It took up to 8 interrupt sources and combined them into one
40 40 * output wire. Up to 8 8259s could be slaved together providing up to 64 IRQs.
41 41 * With the switch to the 8259A, level mode interrupts became possible. For a
42 42 * long time on i86pc the 8259A was the only way to handle interrupts and it
43 43 * had its own set of quirks. The 8259A and its corresponding interval timer
44 44 * the 8254 are programmed using outb and inb instructions.
45 45 *
46 46 * Intel Advanced Programmable Interrupt Controller (APIC)
47 47 *
48 48 * Starting around the time of the introduction of the P6 family
49 49 * microarchitecture (i686) Intel introduced a new interrupt controller.
50 50 * Instead of having the series of slaved 8259A devices, Intel opted to outfit
51 51 * each processor with a Local APIC (lapic) and to outfit the system with at
52 52 * least one, but potentially more, I/O APICs (ioapic). The lapics and ioapics
53 53 * initially communicated over a dedicated bus, but this has since been
54 54 * replaced. Each physical core and even hyperthread currently contains its
55 55 * own local apic, which is not shared. There are a few exceptions for
56 56 * hyperthreads, but that does not usually concern us.
57 57 *
58 58 * Instead of talking directly to 8259 for status, sending End Of Interrupt
59 59 * (EOI), etc. a microprocessor now communicates directly to the lapic. This
60 60 * also allows for each microprocessor to be able to have independent controls.
61 61 * The programming method is different from the 8259. Consumers map the lapic
62 62 * registers into uncacheable memory to read and manipulate the state.
63 63 *
64 64 * The number of addressable interrupt vectors was increased to 256. However
65 65 * vectors 0-31 are reserved for the processor exception handling, leaving the
66 66 * remaining vectors for general use. In addition to hardware generated
67 67 * interrupts, the lapic provides a way for generating inter-processor
68 68 * interrupts (IPI) which are the basis for CPU cross calls and CPU pokes.
69 69 *
70 70 * AMD ended up implementing the Intel APIC architecture in lieu of their work
71 71 * with Cyrix.
72 72 *
73 73 * Intel x2apic
74 74 *
75 75 * The x2apic is an extension to the lapic which started showing up around the
76 76 * same time as the Sandy Bridge chipsets. It provides a new programming mode
77 77 * as well as new features. The goal of the x2apic is to solve a few problems
78 78 * with the previous generation of lapic and the x2apic is backwards compatible
79 79 * with the previous programming and model. The only downsides to using the
80 80 * backwards compatibility is that you are not able to take advantage of the new
81 81 * x2apic features.
82 82 *
83 83 * o The APIC ID is increased from an 8-bit value to a 32-bit value. This
84 84 * increases the maximum number of addressable physical processors beyond
85 85 * 256. This new ID is assembled in a similar manner as the information that
86 86 * is obtainable by the extended cpuid topology leaves.
87 87 *
88 88 * o A new means of generating IPIs was introduced.
89 89 *
90 90 * o Instead of memory mapping the registers, the x2apic only allows for
91 91 * programming it through a series of wrmsrs. This has important semantic
92 92 * side effects. Recall that the registers were previously all mapped to
93 93 * uncachable memory which meant that all operations to the local apic were
94 94 * serializing instructions. With the switch to using wrmsrs this has been
95 95 * relaxed and these operations can no longer be assumed to be serializing
96 96 * instructions.
97 97 *
98 98 * Note for the rest of this we are only going to concern ourselves with the
99 99 * apic and x2apic which practically all of i86pc has been using now for
100 100 * quite some time.
101 101 *
102 102 * Interrupt Priority Levels
103 103 * -------------------------
104 104 *
105 105 * On i86pc systems there are a total of fifteen interrupt priority levels
106 106 * (ipls) which range from 1-15. Level 0 is for normal processing and
107 107 * non-interrupt processing. To manipulate these values the family of spl
108 108 * functions (which date back to UNIX on the PDP-11) are used. Specifically,
109 109 * splr() to raise the priority level and splx() to lower it. One should not
110 110 * generally call setspl() directly.
111 111 *
112 112 * Both i86pc and the supported SPARC platforms honor the same conventions for
113 113 * the meaning behind these IPLs. The most important IPL is the platform's
114 114 * LOCK_LEVEL (0xa on i86pc). If a thread is above LOCK_LEVEL it _must_ not
115 115 * sleep on any synchronization object. The only allowed synchronization
116 116 * primitive is a mutex that has been specifically initialized to be a spin
117 117 * lock (see mutex_init(9F)). Another important level is DISP_LEVEL (0xb on
118 118 * i86pc). You must be at DISP_LEVEL if you want to control the dispatcher.
119 119 * The XC_HI_PIL is the highest level (0xf) and is used during cross-calls.
120 120 *
121 121 * Each interrupt that is registered in the system fires at a specific IPL.
122 122 * Generally most interrupts fire below LOCK_LEVEL.
123 123 *
124 124 * PSM Drivers
125 125 * -----------
126 126 *
127 127 * We currently have three sets of PSM (platform specific module) drivers
128 128 * available. uppc, pcplusmp, and apix. uppc (uni-processor PC) is the original
129 129 * driver that interacts with the 8259A and 8254. In general, it is not used
130 130 * anymore given the prevalence of the apic.
131 131 *
132 132 * The system prefers to use the apix driver over the pcplusmp driver. The apix
133 133 * driver requires HW support for an x2apic. If there is no x2apic HW, apix
134 134 * will not be used. In general we prefer using the apix driver over the
135 135 * pcplusmp driver because it gives us much more flexibility with respect to
136 136 * interrupts. In the apix driver each local apic has its own independent set
137 137 * of interrupts, whereas the pcplusmp driver only has a single global set of
138 138 * interrupts. This is why pcplusmp only supports a finite number of interrupts
139 139 * per IPL -- generally 16, often less. The apix driver supports using either
140 140 * the x2apic or the local apic programing modes. The programming mode does not
141 141 * change the number of interrupts available, just the number of processors
142 142 * that we can address. For the apix driver, the x2apic mode is enabled if the
143 143 * system supports interrupt re-mapping, otherwise the module manages the
144 144 * x2apic in local mode.
145 145 *
146 146 * When there is no x2apic present, we default back to the pcplusmp PSM driver.
147 147 * In general, this is not problematic unless you have more than 256
148 148 * processors in the machine or you do not have enough interrupts available.
149 149 *
150 150 * Controlling Interrupt Generation on i86pc
151 151 * -----------------------------------------
152 152 *
153 153 * There are two different ways to manipulate which interrupts will be
154 154 * generated on i86pc. Each offers different degrees of control.
155 155 *
156 156 * The first is through the flags register (eflags and rflags on i386 and amd64
157 157 * respectively). The IF bit determines whether or not interrupts are enabled
158 158 * or disabled. This is manipulated in one of several ways. The most common way
159 159 * is through the cli and sti instructions. These clear the IF flag and set it,
160 160 * respectively, for the current processor. The other common way is through the
161 161 * use of the intr_clear and intr_restore functions.
162 162 *
163 163 * Assuming interrupts are not blocked by the IF flag, then the second form is
164 164 * through the Processor-Priority Register (PPR). The PPR is used to determine
165 165 * whether or not a pending interrupt should be delivered. If the ipl of the
166 166 * new interrupt is higher than the current value in the PPR, then the lapic
167 167 * will either deliver it immediately (if interrupts are not in progress) or it
168 168 * will deliver it once the current interrupt processing has issued an EOI. The
169 169 * highest unmasked interrupt will be the one delivered.
170 170 *
171 171 * The PPR register is based upon the max of the following two registers in the
172 172 * lapic, the TPR register (also known as CR8 on amd64) that can be used to
173 173 * mask interrupt levels, and the current vector. Because the pcplusmp module
174 174 * always sets TPR appropriately early in the do_interrupt path, we can usually
175 175 * just think that the PPR is the TPR. The pcplusmp module also issues an EOI
176 176 * once it has set the TPR, so higher priority interrupts can come in while
177 177 * we're servicing a lower priority interrupt.
178 178 *
179 179 * Handling Interrupts
180 180 * -------------------
181 181 *
182 182 * Interrupts can be broken down into three categories based on priority and
183 183 * source:
184 184 *
185 185 * o High level interrupts
186 186 * o Low level hardware interrupts
187 187 * o Low level software interrupts
188 188 *
189 189 * High Level Interrupts
190 190 *
191 191 * High level interrupts encompasses both hardware-sourced and software-sourced
192 192 * interrupts. Examples of high level hardware interrupts include the serial
193 193 * console. High level software-sourced interrupts are still delivered through
194 194 * the local apic through IPIs. This is primarily cross calls.
195 195 *
196 196 * When a high level interrupt comes in, we will raise the SPL and then pin the
197 197 * current lwp to the processor. We will use its lwp, but our own interrupt
198 198 * stack and process the high level interrupt in-situ. These handlers are
199 199 * designed to be very short in nature and cannot go to sleep, only block on a
200 200 * spin lock. If the interrupt has a lot of work to do, it must generate a
201 201 * low-priority software interrupt that will be processed later.
202 202 *
203 203 * Low level hardware interrupts
204 204 *
205 205 * Low level hardware interrupts start off like their high-level cousins. The
206 206 * current CPU contains a number of kernel threads (kthread_t) that can be used
207 207 * to process low level interrupts. These are shared between both low level
208 208 * hardware and software interrupts. Note that while we run with our
209 209 * kthread_t, we borrow the pinned threads lwp_t until such a time as we hit a
210 210 * synchronization object. If we hit one and need to sleep, then the scheduler
211 211 * will instead create the rest of what we need.
212 212 *
213 213 * Low level software interrupts
214 214 *
215 215 * Low level software interrupts are handled in a similar way as hardware
216 216 * interrupts, but the notification vector is different. Each CPU has a bitmask
217 217 * of pending software interrupts. We can notify a CPU to process software
218 218 * interrupts through a specific trap vector as well as through several
219 219 * checks that are performed throughout the code. These checks will look at
220 220 * processing software interrupts as we lower our spl.
221 221 *
222 222 * We attempt to process the highest pending software interrupt that we can
223 223 * which is greater than our current IPL. If none currently exist, then we move
224 224 * on. We process a software interrupt in a similar fashion to a hardware
225 225 * interrupt.
226 226 *
227 227 * Traditional Interrupt Flow
228 228 * --------------------------
229 229 *
230 230 * The following diagram tracks the flow of the traditional uppc and pcplusmp
231 231 * interrupt handlers. The apix driver has its own version of do_interrupt().
232 232 * We come into the interrupt handler with all interrupts masked by the IF
233 233 * flag. This is because we set up the handler using an interrupt-gate, which
234 234 * is defined architecturally to have cleared the IF flag for us.
235 235 *
236 236 * +--------------+ +----------------+ +-----------+
237 237 * | _interrupt() |--->| do_interrupt() |--->| *setlvl() |
238 238 * +--------------+ +----------------+ +-----------+
239 239 * | | |
240 240 * | | |
241 241 * low-level| | | softint
242 242 * HW int | | +---------------------------------------+
243 243 * +--------------+ | | |
244 244 * | intr_thread_ |<-----+ | hi-level int |
245 245 * | prolog() | | +----------+ |
246 246 * +--------------+ +--->| hilevel_ | Not on intr stack |
247 247 * | | intr_ |-----------------+ |
248 248 * | | prolog() | | |
249 249 * +------------+ +----------+ | |
250 250 * | switch_sp_ | | On intr v |
251 251 * | and_call() | | Stack +------------+ |
252 252 * +------------+ | | switch_sp_ | |
253 253 * | v | and_call() | |
254 254 * v +-----------+ +------------+ |
255 255 * +-----------+ | dispatch_ | | |
256 256 * | dispatch_ | +-------------------| hilevel() |<------------+ |
257 257 * | hardint() | | +-----------+ |
258 258 * +-----------+ | |
259 259 * | v |
260 260 * | +-----+ +----------------------+ +-----+ hi-level |
261 261 * +---->| sti |->| av_dispatch_autovect |->| cli |---------+ |
262 262 * +-----+ +----------------------+ +-----+ | |
263 263 * | | | |
264 264 * v | | |
265 265 * +----------+ | | |
266 266 * | for each | | | |
267 267 * | handler | | | |
268 268 * | *intr() | | v |
269 269 * +--------------+ +----------+ | +----------------+ |
270 270 * | intr_thread_ | low-level | | hilevel_intr_ | |
271 271 * | epilog() |<-------------------------------+ | epilog() | |
272 272 * +--------------+ +----------------+ |
273 273 * | | | |
274 274 * | +----------------------v v---------------------+ |
275 275 * | +------------+ |
276 276 * | +---------------------->| *setlvlx() | |
277 277 * | | +------------+ |
278 278 * | | | |
279 279 * | | v |
280 280 * | | +--------+ +------------------+ +-------------+ |
281 281 * | | | return |<----| softint pending? |----->| dosoftint() |<-----+
282 282 * | | +--------+ no +------------------+ yes +-------------+
283 283 * | | ^ | |
284 284 * | | | softint pil too low | |
285 285 * | | +--------------------------------------+ |
286 286 * | | v
287 287 * | | +-----------+ +------------+ +-----------+
288 288 * | | | dispatch_ |<-----| switch_sp_ |<---------| *setspl() |
289 289 * | | | softint() | | and_call() | +-----------+
290 290 * | | +-----------+ +------------+
291 291 * | | |
292 292 * | | v
293 293 * | | +-----+ +----------------------+ +-----+ +------------+
294 294 * | | | sti |->| av_dispatch_autovect |->| cli |->| dosoftint_ |
295 295 * | | +-----+ +----------------------+ +-----+ | epilog() |
296 296 * | | +------------+
297 297 * | | | |
298 298 * | +----------------------------------------------------+ |
299 299 * v |
300 300 * +-----------+ |
301 301 * | interrupt | |
302 302 * | thread |<---------------------------------------------------+
303 303 * | blocked |
304 304 * +-----------+
305 305 * |
306 306 * v
307 307 * +----------------+ +------------+ +-----------+ +-------+ +---------+
308 308 * | set_base_spl() |->| *setlvlx() |->| splhigh() |->| sti() |->| swtch() |
309 309 * +----------------+ +------------+ +-----------+ +-------+ +---------+
310 310 *
311 311 * Calls made on Interrupt Stacks and Epilogue routines
312 312 *
313 313 * We use the switch_sp_and_call() assembly routine to switch our sp to the
314 314 * interrupt stacks and then call the appropriate dispatch function. In the
315 315 * case of interrupts which may block, softints and hardints, we always ensure
316 316 * that we are still on the interrupt thread when we call the epilog routine.
317 317 * This is not just important, it's necessary. If the interrupt thread blocked,
318 318 * we won't return from our switch_sp_and_call() function and instead we'll go
319 319 * through and set ourselves up to swtch() directly.
320 320 *
321 321 * New Interrupt Flow
322 322 * ------------------
323 323 *
324 324 * The apix module has its own interrupt path. This is done for various
325 325 * reasons. The first is that rather than having global interrupt vectors, we
326 326 * now have per-cpu vectors.
327 327 *
328 328 * The other substantial change is that the apix design does not use the TPR to
329 329 * mask interrupts below the current level. In fact, except for one special
330 330 * case, it does not use the TPR at all. Instead, it only uses the IF flag
331 331 * (cli/sti) to either block all interrupts or allow any interrupts to come in.
332 332 * The design is such that when interrupts are allowed to come in, if we are
333 333 * currently servicing a higher priority interupt, the new interrupt is treated
334 334 * as pending and serviced later. Specifically, in the pcplusmp module's
335 335 * apic_intr_enter() the code masks interrupts at or below the current
336 336 * IPL using the TPR before sending EOI, whereas the apix module's
337 337 * apix_intr_enter() simply sends EOI.
338 338 *
339 339 * The one special case where the apix code uses the TPR is when it calls
340 340 * through the apic_reg_ops function pointer apic_write_task_reg in
341 341 * apix_init_intr() to initially mask all levels and then finally to enable all
342 342 * levels.
343 343 *
344 344 * Recall that we come into the interrupt handler with all interrupts masked
345 345 * by the IF flag. This is because we set up the handler using an
346 346 * interrupt-gate which is defined architecturally to have cleared the IF flag
347 347 * for us.
348 348 *
349 349 * +--------------+ +---------------------+
350 350 * | _interrupt() |--->| apix_do_interrupt() |
351 351 * +--------------+ +---------------------+
352 352 * |
353 353 * hard int? +----+--------+ softint?
354 354 * | | (but no low-level looping)
355 355 * +-----------+ |
356 356 * | *setlvl() | |
357 357 * +---------+ +-----------+ +----------------------------------+
358 358 * |apix_add_| check IPL | |
359 359 * |pending_ |<-------------+------+----------------------+ |
360 360 * |hardint()| low-level int| hi-level int| |
361 361 * +---------+ v v |
362 362 * | check IPL +-----------------+ +---------------+ |
363 363 * +--+-----+ | apix_intr_ | | apix_hilevel_ | |
364 364 * | | | thread_prolog() | | intr_prolog() | |
365 365 * | return +-----------------+ +---------------+ |
366 366 * | | | On intr |
367 367 * | +------------+ | stack? +------------+ |
368 368 * | | switch_sp_ | +---------| switch_sp_ | |
369 369 * | | and_call() | | | and_call() | |
370 370 * | +------------+ | +------------+ |
371 371 * | | | | |
372 372 * | +----------------+ +----------------+ |
373 373 * | | apix_dispatch_ | | apix_dispatch_ | |
374 374 * | | lowlevel() | | hilevel() | |
375 375 * | +----------------+ +----------------+ |
376 376 * | | | |
377 377 * | v v |
378 378 * | +-------------------------+ |
379 379 * | |apix_dispatch_by_vector()|----+ |
380 380 * | +-------------------------+ | |
381 381 * | !XC_HI_PIL| | | | |
382 382 * | +---+ +-------+ +---+ | |
383 383 * | |sti| |*intr()| |cli| | |
384 384 * | +---+ +-------+ +---+ | hi-level? |
385 385 * | +---------------------------+----+ |
386 386 * | v low-level? v |
387 387 * | +----------------+ +----------------+ |
388 388 * | | apix_intr_ | | apix_hilevel_ | |
389 389 * | | thread_epilog()| | intr_epilog() | |
390 390 * | +----------------+ +----------------+ |
391 391 * | | | |
392 392 * | v-----------------+--------------------------------+ |
393 393 * | +------------+ |
394 394 * | | *setlvlx() | +----------------------------------------------------+
395 395 * | +------------+ |
396 396 * | | | +--------------------------------+ low
397 397 * v v v------+ v | level
398 398 * +------------------+ +------------------+ +-----------+ | pending?
399 399 * | apix_do_pending_ |----->| apix_do_pending_ |----->| apix_do_ |--+
400 400 * | hilevel() | | hardint() | | softint() | |
401 401 * +------------------+ +------------------+ +-----------+ return
402 402 * | | |
403 403 * | while pending | while pending | while pending
404 404 * | hi-level | low-level | softint
405 405 * | | |
406 406 * +---------------+ +-----------------+ +-----------------+
407 407 * | apix_hilevel_ | | apix_intr_ | | apix_do_ |
408 408 * | intr_prolog() | | thread_prolog() | | softint_prolog()|
409 409 * +---------------+ +-----------------+ +-----------------+
410 410 * | On intr | |
411 411 * | stack? +------------+ +------------+ +------------+
412 412 * +--------| switch_sp_ | | switch_sp_ | | switch_sp_ |
413 413 * | | and_call() | | and_call() | | and_call() |
414 414 * | +------------+ +------------+ +------------+
415 415 * | | | |
416 416 * +------------------+ +------------------+ +------------------------+
417 417 * | apix_dispatch_ | | apix_dispatch_ | | apix_dispatch_softint()|
418 418 * | pending_hilevel()| | pending_hardint()| +------------------------+
419 419 * +------------------+ +------------------+ | | | |
420 420 * | | | | | | | |
421 421 * | +----------------+ | +----------------+ | | | |
422 422 * | | apix_hilevel_ | | | apix_intr_ | | | | |
423 423 * | | intr_epilog() | | | thread_epilog()| | | | |
424 424 * | +----------------+ | +----------------+ | | | |
425 425 * | | | | | | | |
426 426 * | +------------+ | +----------+ +------+ | | |
427 427 * | | *setlvlx() | | |*setlvlx()| | | | |
428 428 * | +------------+ | +----------+ | +----------+ | +---------+
429 429 * | | +---+ |av_ | +---+ |apix_do_ |
430 430 * +---------------------------------+ |sti| |dispatch_ | |cli| |softint_ |
431 431 * | apix_dispatch_pending_autovect()| +---+ |softvect()| +---+ |epilog() |
432 432 * +---------------------------------+ +----------+ +---------+
433 433 * |!XC_HI_PIL | | | |
434 434 * +---+ +-------+ +---+ +----------+ +-------+
435 435 * |sti| |*intr()| |cli| |apix_post_| |*intr()|
436 436 * +---+ +-------+ +---+ |hardint() | +-------+
437 437 * +----------+
438 438 */
439 439
440 440 #include <sys/cpuvar.h>
441 441 #include <sys/cpu_event.h>
442 442 #include <sys/regset.h>
443 443 #include <sys/psw.h>
444 444 #include <sys/types.h>
445 445 #include <sys/thread.h>
446 446 #include <sys/systm.h>
447 447 #include <sys/segments.h>
448 448 #include <sys/pcb.h>
449 449 #include <sys/trap.h>
450 450 #include <sys/ftrace.h>
451 451 #include <sys/traptrace.h>
452 452 #include <sys/clock.h>
453 453 #include <sys/panic.h>
454 454 #include <sys/disp.h>
455 455 #include <vm/seg_kp.h>
456 456 #include <sys/stack.h>
457 457 #include <sys/sysmacros.h>
458 458 #include <sys/cmn_err.h>
459 459 #include <sys/kstat.h>
460 460 #include <sys/smp_impldefs.h>
461 461 #include <sys/pool_pset.h>
462 462 #include <sys/zone.h>
463 463 #include <sys/bitmap.h>
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464 464 #include <sys/archsystm.h>
465 465 #include <sys/machsystm.h>
466 466 #include <sys/ontrap.h>
467 467 #include <sys/x86_archext.h>
468 468 #include <sys/promif.h>
469 469 #include <vm/hat_i86.h>
470 470 #if defined(__xpv)
471 471 #include <sys/hypervisor.h>
472 472 #endif
473 473
474 +#if defined(__amd64) && !defined(__xpv)
475 +/* If this fails, then the padding numbers in machcpuvar.h are wrong. */
476 +CTASSERT((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_pad))
477 + < MMU_PAGESIZE);
478 +CTASSERT((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_kpti))
479 + >= MMU_PAGESIZE);
480 +CTASSERT((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_kpti_dbg))
481 + < 2 * MMU_PAGESIZE);
482 +CTASSERT((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_pad2))
483 + < 2 * MMU_PAGESIZE);
484 +CTASSERT(((sizeof (struct kpti_frame)) & 0xF) == 0);
485 +CTASSERT(((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_kpti_dbg))
486 + & 0xF) == 0);
487 +CTASSERT((offsetof(struct kpti_frame, kf_tr_rsp) & 0xF) == 0);
488 +#endif
474 489
475 490 #if defined(__xpv) && defined(DEBUG)
476 491
477 492 /*
478 493 * This panic message is intended as an aid to interrupt debugging.
479 494 *
480 495 * The associated assertion tests the condition of enabling
481 496 * events when events are already enabled. The implication
482 497 * being that whatever code the programmer thought was
483 498 * protected by having events disabled until the second
484 499 * enable happened really wasn't protected at all ..
485 500 */
486 501
487 502 int stistipanic = 1; /* controls the debug panic check */
488 503 const char *stistimsg = "stisti";
489 504 ulong_t laststi[NCPU];
490 505
491 506 /*
492 507 * This variable tracks the last place events were disabled on each cpu
493 508 * it assists in debugging when asserts that interrupts are enabled trip.
494 509 */
495 510 ulong_t lastcli[NCPU];
496 511
497 512 #endif
498 513
499 514 void do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);
500 515
501 516 void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *) = do_interrupt;
502 517 uintptr_t (*get_intr_handler)(int, short) = NULL;
503 518
504 519 /*
505 520 * Set cpu's base SPL level to the highest active interrupt level
506 521 */
507 522 void
508 523 set_base_spl(void)
509 524 {
510 525 struct cpu *cpu = CPU;
511 526 uint16_t active = (uint16_t)cpu->cpu_intr_actv;
512 527
513 528 cpu->cpu_base_spl = active == 0 ? 0 : bsrw_insn(active);
514 529 }
515 530
516 531 /*
517 532 * Do all the work necessary to set up the cpu and thread structures
518 533 * to dispatch a high-level interrupt.
519 534 *
520 535 * Returns 0 if we're -not- already on the high-level interrupt stack,
521 536 * (and *must* switch to it), non-zero if we are already on that stack.
522 537 *
523 538 * Called with interrupts masked.
524 539 * The 'pil' is already set to the appropriate level for rp->r_trapno.
525 540 */
526 541 static int
527 542 hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp)
528 543 {
529 544 struct machcpu *mcpu = &cpu->cpu_m;
530 545 uint_t mask;
531 546 hrtime_t intrtime;
532 547 hrtime_t now = tsc_read();
533 548
534 549 ASSERT(pil > LOCK_LEVEL);
535 550
536 551 if (pil == CBE_HIGH_PIL) {
537 552 cpu->cpu_profile_pil = oldpil;
538 553 if (USERMODE(rp->r_cs)) {
539 554 cpu->cpu_profile_pc = 0;
540 555 cpu->cpu_profile_upc = rp->r_pc;
541 556 cpu->cpu_cpcprofile_pc = 0;
542 557 cpu->cpu_cpcprofile_upc = rp->r_pc;
543 558 } else {
544 559 cpu->cpu_profile_pc = rp->r_pc;
545 560 cpu->cpu_profile_upc = 0;
546 561 cpu->cpu_cpcprofile_pc = rp->r_pc;
547 562 cpu->cpu_cpcprofile_upc = 0;
548 563 }
549 564 }
550 565
551 566 mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK;
552 567 if (mask != 0) {
553 568 int nestpil;
554 569
555 570 /*
556 571 * We have interrupted another high-level interrupt.
557 572 * Load starting timestamp, compute interval, update
558 573 * cumulative counter.
559 574 */
560 575 nestpil = bsrw_insn((uint16_t)mask);
561 576 ASSERT(nestpil < pil);
562 577 intrtime = now -
563 578 mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)];
564 579 mcpu->intrstat[nestpil][0] += intrtime;
565 580 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
566 581 /*
567 582 * Another high-level interrupt is active below this one, so
568 583 * there is no need to check for an interrupt thread. That
569 584 * will be done by the lowest priority high-level interrupt
570 585 * active.
571 586 */
572 587 } else {
573 588 kthread_t *t = cpu->cpu_thread;
574 589
575 590 /*
576 591 * See if we are interrupting a low-level interrupt thread.
577 592 * If so, account for its time slice only if its time stamp
578 593 * is non-zero.
579 594 */
580 595 if ((t->t_flag & T_INTR_THREAD) != 0 && t->t_intr_start != 0) {
581 596 intrtime = now - t->t_intr_start;
582 597 mcpu->intrstat[t->t_pil][0] += intrtime;
583 598 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
584 599 t->t_intr_start = 0;
585 600 }
586 601 }
587 602
588 603 /*
589 604 * Store starting timestamp in CPU structure for this PIL.
590 605 */
591 606 mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
592 607
593 608 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
594 609
595 610 if (pil == 15) {
596 611 /*
597 612 * To support reentrant level 15 interrupts, we maintain a
598 613 * recursion count in the top half of cpu_intr_actv. Only
599 614 * when this count hits zero do we clear the PIL 15 bit from
600 615 * the lower half of cpu_intr_actv.
601 616 */
602 617 uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1;
603 618 (*refcntp)++;
604 619 }
605 620
606 621 mask = cpu->cpu_intr_actv;
607 622
608 623 cpu->cpu_intr_actv |= (1 << pil);
609 624
610 625 return (mask & CPU_INTR_ACTV_HIGH_LEVEL_MASK);
611 626 }
612 627
613 628 /*
614 629 * Does most of the work of returning from a high level interrupt.
615 630 *
616 631 * Returns 0 if there are no more high level interrupts (in which
617 632 * case we must switch back to the interrupted thread stack) or
618 633 * non-zero if there are more (in which case we should stay on it).
619 634 *
620 635 * Called with interrupts masked
621 636 */
622 637 static int
623 638 hilevel_intr_epilog(struct cpu *cpu, uint_t pil, uint_t oldpil, uint_t vecnum)
624 639 {
625 640 struct machcpu *mcpu = &cpu->cpu_m;
626 641 uint_t mask;
627 642 hrtime_t intrtime;
628 643 hrtime_t now = tsc_read();
629 644
630 645 ASSERT(mcpu->mcpu_pri == pil);
631 646
632 647 cpu->cpu_stats.sys.intr[pil - 1]++;
633 648
634 649 ASSERT(cpu->cpu_intr_actv & (1 << pil));
635 650
636 651 if (pil == 15) {
637 652 /*
638 653 * To support reentrant level 15 interrupts, we maintain a
639 654 * recursion count in the top half of cpu_intr_actv. Only
640 655 * when this count hits zero do we clear the PIL 15 bit from
641 656 * the lower half of cpu_intr_actv.
642 657 */
643 658 uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1;
644 659
645 660 ASSERT(*refcntp > 0);
646 661
647 662 if (--(*refcntp) == 0)
648 663 cpu->cpu_intr_actv &= ~(1 << pil);
649 664 } else {
650 665 cpu->cpu_intr_actv &= ~(1 << pil);
651 666 }
652 667
653 668 ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0);
654 669
655 670 intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)];
656 671 mcpu->intrstat[pil][0] += intrtime;
657 672 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
658 673
659 674 /*
660 675 * Check for lower-pil nested high-level interrupt beneath
661 676 * current one. If so, place a starting timestamp in its
662 677 * pil_high_start entry.
663 678 */
664 679 mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK;
665 680 if (mask != 0) {
666 681 int nestpil;
667 682
668 683 /*
669 684 * find PIL of nested interrupt
670 685 */
671 686 nestpil = bsrw_insn((uint16_t)mask);
672 687 ASSERT(nestpil < pil);
673 688 mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now;
674 689 /*
675 690 * (Another high-level interrupt is active below this one,
676 691 * so there is no need to check for an interrupt
677 692 * thread. That will be done by the lowest priority
678 693 * high-level interrupt active.)
679 694 */
680 695 } else {
681 696 /*
682 697 * Check to see if there is a low-level interrupt active.
683 698 * If so, place a starting timestamp in the thread
684 699 * structure.
685 700 */
686 701 kthread_t *t = cpu->cpu_thread;
687 702
688 703 if (t->t_flag & T_INTR_THREAD)
689 704 t->t_intr_start = now;
690 705 }
691 706
692 707 mcpu->mcpu_pri = oldpil;
693 708 (void) (*setlvlx)(oldpil, vecnum);
694 709
695 710 return (cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK);
696 711 }
697 712
698 713 /*
699 714 * Set up the cpu, thread and interrupt thread structures for
700 715 * executing an interrupt thread. The new stack pointer of the
701 716 * interrupt thread (which *must* be switched to) is returned.
702 717 */
703 718 static caddr_t
704 719 intr_thread_prolog(struct cpu *cpu, caddr_t stackptr, uint_t pil)
705 720 {
706 721 struct machcpu *mcpu = &cpu->cpu_m;
707 722 kthread_t *t, *volatile it;
708 723 hrtime_t now = tsc_read();
709 724
710 725 ASSERT(pil > 0);
711 726 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
712 727 cpu->cpu_intr_actv |= (1 << pil);
713 728
714 729 /*
715 730 * Get set to run an interrupt thread.
716 731 * There should always be an interrupt thread, since we
717 732 * allocate one for each level on each CPU.
718 733 *
719 734 * t_intr_start could be zero due to cpu_intr_swtch_enter.
720 735 */
721 736 t = cpu->cpu_thread;
722 737 if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) {
723 738 hrtime_t intrtime = now - t->t_intr_start;
724 739 mcpu->intrstat[t->t_pil][0] += intrtime;
725 740 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
726 741 t->t_intr_start = 0;
727 742 }
728 743
729 744 ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr);
730 745
731 746 t->t_sp = (uintptr_t)stackptr; /* mark stack in curthread for resume */
732 747
733 748 /*
734 749 * unlink the interrupt thread off the cpu
735 750 *
736 751 * Note that the code in kcpc_overflow_intr -relies- on the
737 752 * ordering of events here - in particular that t->t_lwp of
738 753 * the interrupt thread is set to the pinned thread *before*
739 754 * curthread is changed.
740 755 */
741 756 it = cpu->cpu_intr_thread;
742 757 cpu->cpu_intr_thread = it->t_link;
743 758 it->t_intr = t;
744 759 it->t_lwp = t->t_lwp;
745 760
746 761 /*
747 762 * (threads on the interrupt thread free list could have state
748 763 * preset to TS_ONPROC, but it helps in debugging if
749 764 * they're TS_FREE.)
750 765 */
751 766 it->t_state = TS_ONPROC;
752 767
753 768 cpu->cpu_thread = it; /* new curthread on this cpu */
754 769 it->t_pil = (uchar_t)pil;
755 770 it->t_pri = intr_pri + (pri_t)pil;
756 771 it->t_intr_start = now;
757 772
758 773 return (it->t_stk);
759 774 }
760 775
761 776
762 777 #ifdef DEBUG
763 778 int intr_thread_cnt;
764 779 #endif
765 780
766 781 /*
767 782 * Called with interrupts disabled
768 783 */
769 784 static void
770 785 intr_thread_epilog(struct cpu *cpu, uint_t vec, uint_t oldpil)
771 786 {
772 787 struct machcpu *mcpu = &cpu->cpu_m;
773 788 kthread_t *t;
774 789 kthread_t *it = cpu->cpu_thread; /* curthread */
775 790 uint_t pil, basespl;
776 791 hrtime_t intrtime;
777 792 hrtime_t now = tsc_read();
778 793
779 794 pil = it->t_pil;
780 795 cpu->cpu_stats.sys.intr[pil - 1]++;
781 796
782 797 ASSERT(it->t_intr_start != 0);
783 798 intrtime = now - it->t_intr_start;
784 799 mcpu->intrstat[pil][0] += intrtime;
785 800 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
786 801
787 802 ASSERT(cpu->cpu_intr_actv & (1 << pil));
788 803 cpu->cpu_intr_actv &= ~(1 << pil);
789 804
790 805 /*
791 806 * If there is still an interrupted thread underneath this one
792 807 * then the interrupt was never blocked and the return is
793 808 * fairly simple. Otherwise it isn't.
794 809 */
795 810 if ((t = it->t_intr) == NULL) {
796 811 /*
797 812 * The interrupted thread is no longer pinned underneath
798 813 * the interrupt thread. This means the interrupt must
799 814 * have blocked, and the interrupted thread has been
800 815 * unpinned, and has probably been running around the
801 816 * system for a while.
802 817 *
803 818 * Since there is no longer a thread under this one, put
804 819 * this interrupt thread back on the CPU's free list and
805 820 * resume the idle thread which will dispatch the next
806 821 * thread to run.
807 822 */
808 823 #ifdef DEBUG
809 824 intr_thread_cnt++;
810 825 #endif
811 826 cpu->cpu_stats.sys.intrblk++;
812 827 /*
813 828 * Set CPU's base SPL based on active interrupts bitmask
814 829 */
815 830 set_base_spl();
816 831 basespl = cpu->cpu_base_spl;
817 832 mcpu->mcpu_pri = basespl;
818 833 (*setlvlx)(basespl, vec);
819 834 (void) splhigh();
820 835 sti();
821 836 it->t_state = TS_FREE;
822 837 /*
823 838 * Return interrupt thread to pool
824 839 */
825 840 it->t_link = cpu->cpu_intr_thread;
826 841 cpu->cpu_intr_thread = it;
827 842 swtch();
828 843 panic("intr_thread_epilog: swtch returned");
829 844 /*NOTREACHED*/
830 845 }
831 846
832 847 /*
833 848 * Return interrupt thread to the pool
834 849 */
835 850 it->t_link = cpu->cpu_intr_thread;
836 851 cpu->cpu_intr_thread = it;
837 852 it->t_state = TS_FREE;
838 853
839 854 basespl = cpu->cpu_base_spl;
840 855 pil = MAX(oldpil, basespl);
841 856 mcpu->mcpu_pri = pil;
842 857 (*setlvlx)(pil, vec);
843 858 t->t_intr_start = now;
844 859 cpu->cpu_thread = t;
845 860 }
846 861
847 862 /*
848 863 * intr_get_time() is a resource for interrupt handlers to determine how
849 864 * much time has been spent handling the current interrupt. Such a function
850 865 * is needed because higher level interrupts can arrive during the
851 866 * processing of an interrupt. intr_get_time() only returns time spent in the
852 867 * current interrupt handler.
853 868 *
854 869 * The caller must be calling from an interrupt handler running at a pil
855 870 * below or at lock level. Timings are not provided for high-level
856 871 * interrupts.
857 872 *
858 873 * The first time intr_get_time() is called while handling an interrupt,
859 874 * it returns the time since the interrupt handler was invoked. Subsequent
860 875 * calls will return the time since the prior call to intr_get_time(). Time
861 876 * is returned as ticks. Use scalehrtimef() to convert ticks to nsec.
862 877 *
863 878 * Theory Of Intrstat[][]:
864 879 *
865 880 * uint64_t intrstat[pil][0..1] is an array indexed by pil level, with two
866 881 * uint64_ts per pil.
867 882 *
868 883 * intrstat[pil][0] is a cumulative count of the number of ticks spent
869 884 * handling all interrupts at the specified pil on this CPU. It is
870 885 * exported via kstats to the user.
871 886 *
872 887 * intrstat[pil][1] is always a count of ticks less than or equal to the
873 888 * value in [0]. The difference between [1] and [0] is the value returned
874 889 * by a call to intr_get_time(). At the start of interrupt processing,
875 890 * [0] and [1] will be equal (or nearly so). As the interrupt consumes
876 891 * time, [0] will increase, but [1] will remain the same. A call to
877 892 * intr_get_time() will return the difference, then update [1] to be the
878 893 * same as [0]. Future calls will return the time since the last call.
879 894 * Finally, when the interrupt completes, [1] is updated to the same as [0].
880 895 *
881 896 * Implementation:
882 897 *
883 898 * intr_get_time() works much like a higher level interrupt arriving. It
884 899 * "checkpoints" the timing information by incrementing intrstat[pil][0]
885 900 * to include elapsed running time, and by setting t_intr_start to rdtsc.
886 901 * It then sets the return value to intrstat[pil][0] - intrstat[pil][1],
887 902 * and updates intrstat[pil][1] to be the same as the new value of
888 903 * intrstat[pil][0].
889 904 *
890 905 * In the normal handling of interrupts, after an interrupt handler returns
891 906 * and the code in intr_thread() updates intrstat[pil][0], it then sets
892 907 * intrstat[pil][1] to the new value of intrstat[pil][0]. When [0] == [1],
893 908 * the timings are reset, i.e. intr_get_time() will return [0] - [1] which
894 909 * is 0.
895 910 *
896 911 * Whenever interrupts arrive on a CPU which is handling a lower pil
897 912 * interrupt, they update the lower pil's [0] to show time spent in the
898 913 * handler that they've interrupted. This results in a growing discrepancy
899 914 * between [0] and [1], which is returned the next time intr_get_time() is
900 915 * called. Time spent in the higher-pil interrupt will not be returned in
901 916 * the next intr_get_time() call from the original interrupt, because
902 917 * the higher-pil interrupt's time is accumulated in intrstat[higherpil][].
903 918 */
904 919 uint64_t
905 920 intr_get_time(void)
906 921 {
907 922 struct cpu *cpu;
908 923 struct machcpu *mcpu;
909 924 kthread_t *t;
910 925 uint64_t time, delta, ret;
911 926 uint_t pil;
912 927
913 928 cli();
914 929 cpu = CPU;
915 930 mcpu = &cpu->cpu_m;
916 931 t = cpu->cpu_thread;
917 932 pil = t->t_pil;
918 933 ASSERT((cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK) == 0);
919 934 ASSERT(t->t_flag & T_INTR_THREAD);
920 935 ASSERT(pil != 0);
921 936 ASSERT(t->t_intr_start != 0);
922 937
923 938 time = tsc_read();
924 939 delta = time - t->t_intr_start;
925 940 t->t_intr_start = time;
926 941
927 942 time = mcpu->intrstat[pil][0] + delta;
928 943 ret = time - mcpu->intrstat[pil][1];
929 944 mcpu->intrstat[pil][0] = time;
930 945 mcpu->intrstat[pil][1] = time;
931 946 cpu->cpu_intracct[cpu->cpu_mstate] += delta;
932 947
933 948 sti();
934 949 return (ret);
935 950 }
936 951
937 952 static caddr_t
938 953 dosoftint_prolog(
939 954 struct cpu *cpu,
940 955 caddr_t stackptr,
941 956 uint32_t st_pending,
942 957 uint_t oldpil)
943 958 {
944 959 kthread_t *t, *volatile it;
945 960 struct machcpu *mcpu = &cpu->cpu_m;
946 961 uint_t pil;
947 962 hrtime_t now;
948 963
949 964 top:
950 965 ASSERT(st_pending == mcpu->mcpu_softinfo.st_pending);
951 966
952 967 pil = bsrw_insn((uint16_t)st_pending);
953 968 if (pil <= oldpil || pil <= cpu->cpu_base_spl)
954 969 return (0);
955 970
956 971 /*
957 972 * XX64 Sigh.
958 973 *
959 974 * This is a transliteration of the i386 assembler code for
960 975 * soft interrupts. One question is "why does this need
961 976 * to be atomic?" One possible race is -other- processors
962 977 * posting soft interrupts to us in set_pending() i.e. the
963 978 * CPU might get preempted just after the address computation,
964 979 * but just before the atomic transaction, so another CPU would
965 980 * actually set the original CPU's st_pending bit. However,
966 981 * it looks like it would be simpler to disable preemption there.
967 982 * Are there other races for which preemption control doesn't work?
968 983 *
969 984 * The i386 assembler version -also- checks to see if the bit
970 985 * being cleared was actually set; if it wasn't, it rechecks
971 986 * for more. This seems a bit strange, as the only code that
972 987 * ever clears the bit is -this- code running with interrupts
973 988 * disabled on -this- CPU. This code would probably be cheaper:
974 989 *
975 990 * atomic_and_32((uint32_t *)&mcpu->mcpu_softinfo.st_pending,
976 991 * ~(1 << pil));
977 992 *
978 993 * and t->t_preempt--/++ around set_pending() even cheaper,
979 994 * but at this point, correctness is critical, so we slavishly
980 995 * emulate the i386 port.
981 996 */
982 997 if (atomic_btr32((uint32_t *)
983 998 &mcpu->mcpu_softinfo.st_pending, pil) == 0) {
984 999 st_pending = mcpu->mcpu_softinfo.st_pending;
985 1000 goto top;
986 1001 }
987 1002
988 1003 mcpu->mcpu_pri = pil;
989 1004 (*setspl)(pil);
990 1005
991 1006 now = tsc_read();
992 1007
993 1008 /*
994 1009 * Get set to run interrupt thread.
995 1010 * There should always be an interrupt thread since we
996 1011 * allocate one for each level on the CPU.
997 1012 */
998 1013 it = cpu->cpu_intr_thread;
999 1014 cpu->cpu_intr_thread = it->t_link;
1000 1015
1001 1016 /* t_intr_start could be zero due to cpu_intr_swtch_enter. */
1002 1017 t = cpu->cpu_thread;
1003 1018 if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) {
1004 1019 hrtime_t intrtime = now - t->t_intr_start;
1005 1020 mcpu->intrstat[pil][0] += intrtime;
1006 1021 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
1007 1022 t->t_intr_start = 0;
1008 1023 }
1009 1024
1010 1025 /*
1011 1026 * Note that the code in kcpc_overflow_intr -relies- on the
1012 1027 * ordering of events here - in particular that t->t_lwp of
1013 1028 * the interrupt thread is set to the pinned thread *before*
1014 1029 * curthread is changed.
1015 1030 */
1016 1031 it->t_lwp = t->t_lwp;
1017 1032 it->t_state = TS_ONPROC;
1018 1033
1019 1034 /*
1020 1035 * Push interrupted thread onto list from new thread.
1021 1036 * Set the new thread as the current one.
1022 1037 * Set interrupted thread's T_SP because if it is the idle thread,
1023 1038 * resume() may use that stack between threads.
1024 1039 */
1025 1040
1026 1041 ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr);
1027 1042 t->t_sp = (uintptr_t)stackptr;
1028 1043
1029 1044 it->t_intr = t;
1030 1045 cpu->cpu_thread = it;
1031 1046
1032 1047 /*
1033 1048 * Set bit for this pil in CPU's interrupt active bitmask.
1034 1049 */
1035 1050 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
1036 1051 cpu->cpu_intr_actv |= (1 << pil);
1037 1052
1038 1053 /*
1039 1054 * Initialize thread priority level from intr_pri
1040 1055 */
1041 1056 it->t_pil = (uchar_t)pil;
1042 1057 it->t_pri = (pri_t)pil + intr_pri;
1043 1058 it->t_intr_start = now;
1044 1059
1045 1060 return (it->t_stk);
1046 1061 }
1047 1062
1048 1063 static void
1049 1064 dosoftint_epilog(struct cpu *cpu, uint_t oldpil)
1050 1065 {
1051 1066 struct machcpu *mcpu = &cpu->cpu_m;
1052 1067 kthread_t *t, *it;
1053 1068 uint_t pil, basespl;
1054 1069 hrtime_t intrtime;
1055 1070 hrtime_t now = tsc_read();
1056 1071
1057 1072 it = cpu->cpu_thread;
1058 1073 pil = it->t_pil;
1059 1074
1060 1075 cpu->cpu_stats.sys.intr[pil - 1]++;
1061 1076
1062 1077 ASSERT(cpu->cpu_intr_actv & (1 << pil));
1063 1078 cpu->cpu_intr_actv &= ~(1 << pil);
1064 1079 intrtime = now - it->t_intr_start;
1065 1080 mcpu->intrstat[pil][0] += intrtime;
1066 1081 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
1067 1082
1068 1083 /*
1069 1084 * If there is still an interrupted thread underneath this one
1070 1085 * then the interrupt was never blocked and the return is
1071 1086 * fairly simple. Otherwise it isn't.
1072 1087 */
1073 1088 if ((t = it->t_intr) == NULL) {
1074 1089 /*
1075 1090 * Put thread back on the interrupt thread list.
1076 1091 * This was an interrupt thread, so set CPU's base SPL.
1077 1092 */
1078 1093 set_base_spl();
1079 1094 it->t_state = TS_FREE;
1080 1095 it->t_link = cpu->cpu_intr_thread;
1081 1096 cpu->cpu_intr_thread = it;
1082 1097 (void) splhigh();
1083 1098 sti();
1084 1099 swtch();
1085 1100 /*NOTREACHED*/
1086 1101 panic("dosoftint_epilog: swtch returned");
1087 1102 }
1088 1103 it->t_link = cpu->cpu_intr_thread;
1089 1104 cpu->cpu_intr_thread = it;
1090 1105 it->t_state = TS_FREE;
1091 1106 cpu->cpu_thread = t;
1092 1107 if (t->t_flag & T_INTR_THREAD)
1093 1108 t->t_intr_start = now;
1094 1109 basespl = cpu->cpu_base_spl;
1095 1110 pil = MAX(oldpil, basespl);
1096 1111 mcpu->mcpu_pri = pil;
1097 1112 (*setspl)(pil);
1098 1113 }
1099 1114
1100 1115
1101 1116 /*
1102 1117 * Make the interrupted thread 'to' be runnable.
1103 1118 *
1104 1119 * Since t->t_sp has already been saved, t->t_pc is all
1105 1120 * that needs to be set in this function.
1106 1121 *
1107 1122 * Returns the interrupt level of the interrupt thread.
1108 1123 */
1109 1124 int
1110 1125 intr_passivate(
1111 1126 kthread_t *it, /* interrupt thread */
1112 1127 kthread_t *t) /* interrupted thread */
1113 1128 {
1114 1129 extern void _sys_rtt();
1115 1130
1116 1131 ASSERT(it->t_flag & T_INTR_THREAD);
1117 1132 ASSERT(SA(t->t_sp) == t->t_sp);
1118 1133
1119 1134 t->t_pc = (uintptr_t)_sys_rtt;
1120 1135 return (it->t_pil);
1121 1136 }
1122 1137
1123 1138 /*
1124 1139 * Create interrupt kstats for this CPU.
1125 1140 */
1126 1141 void
1127 1142 cpu_create_intrstat(cpu_t *cp)
1128 1143 {
1129 1144 int i;
1130 1145 kstat_t *intr_ksp;
1131 1146 kstat_named_t *knp;
1132 1147 char name[KSTAT_STRLEN];
1133 1148 zoneid_t zoneid;
1134 1149
1135 1150 ASSERT(MUTEX_HELD(&cpu_lock));
1136 1151
1137 1152 if (pool_pset_enabled())
1138 1153 zoneid = GLOBAL_ZONEID;
1139 1154 else
1140 1155 zoneid = ALL_ZONES;
1141 1156
1142 1157 intr_ksp = kstat_create_zone("cpu", cp->cpu_id, "intrstat", "misc",
1143 1158 KSTAT_TYPE_NAMED, PIL_MAX * 2, NULL, zoneid);
1144 1159
1145 1160 /*
1146 1161 * Initialize each PIL's named kstat
1147 1162 */
1148 1163 if (intr_ksp != NULL) {
1149 1164 intr_ksp->ks_update = cpu_kstat_intrstat_update;
1150 1165 knp = (kstat_named_t *)intr_ksp->ks_data;
1151 1166 intr_ksp->ks_private = cp;
1152 1167 for (i = 0; i < PIL_MAX; i++) {
1153 1168 (void) snprintf(name, KSTAT_STRLEN, "level-%d-time",
1154 1169 i + 1);
1155 1170 kstat_named_init(&knp[i * 2], name, KSTAT_DATA_UINT64);
1156 1171 (void) snprintf(name, KSTAT_STRLEN, "level-%d-count",
1157 1172 i + 1);
1158 1173 kstat_named_init(&knp[(i * 2) + 1], name,
1159 1174 KSTAT_DATA_UINT64);
1160 1175 }
1161 1176 kstat_install(intr_ksp);
1162 1177 }
1163 1178 }
1164 1179
1165 1180 /*
1166 1181 * Delete interrupt kstats for this CPU.
1167 1182 */
1168 1183 void
1169 1184 cpu_delete_intrstat(cpu_t *cp)
1170 1185 {
1171 1186 kstat_delete_byname_zone("cpu", cp->cpu_id, "intrstat", ALL_ZONES);
1172 1187 }
1173 1188
1174 1189 /*
1175 1190 * Convert interrupt statistics from CPU ticks to nanoseconds and
1176 1191 * update kstat.
1177 1192 */
1178 1193 int
1179 1194 cpu_kstat_intrstat_update(kstat_t *ksp, int rw)
1180 1195 {
1181 1196 kstat_named_t *knp = ksp->ks_data;
1182 1197 cpu_t *cpup = (cpu_t *)ksp->ks_private;
1183 1198 int i;
1184 1199 hrtime_t hrt;
1185 1200
1186 1201 if (rw == KSTAT_WRITE)
1187 1202 return (EACCES);
1188 1203
1189 1204 for (i = 0; i < PIL_MAX; i++) {
1190 1205 hrt = (hrtime_t)cpup->cpu_m.intrstat[i + 1][0];
1191 1206 scalehrtimef(&hrt);
1192 1207 knp[i * 2].value.ui64 = (uint64_t)hrt;
1193 1208 knp[(i * 2) + 1].value.ui64 = cpup->cpu_stats.sys.intr[i];
1194 1209 }
1195 1210
1196 1211 return (0);
1197 1212 }
1198 1213
1199 1214 /*
1200 1215 * An interrupt thread is ending a time slice, so compute the interval it
1201 1216 * ran for and update the statistic for its PIL.
1202 1217 */
1203 1218 void
1204 1219 cpu_intr_swtch_enter(kthread_id_t t)
1205 1220 {
1206 1221 uint64_t interval;
1207 1222 uint64_t start;
1208 1223 cpu_t *cpu;
1209 1224
1210 1225 ASSERT((t->t_flag & T_INTR_THREAD) != 0);
1211 1226 ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
1212 1227
1213 1228 /*
1214 1229 * We could be here with a zero timestamp. This could happen if:
1215 1230 * an interrupt thread which no longer has a pinned thread underneath
1216 1231 * it (i.e. it blocked at some point in its past) has finished running
1217 1232 * its handler. intr_thread() updated the interrupt statistic for its
1218 1233 * PIL and zeroed its timestamp. Since there was no pinned thread to
1219 1234 * return to, swtch() gets called and we end up here.
1220 1235 *
1221 1236 * Note that we use atomic ops below (atomic_cas_64 and
1222 1237 * atomic_add_64), which we don't use in the functions above,
1223 1238 * because we're not called with interrupts blocked, but the
1224 1239 * epilog/prolog functions are.
1225 1240 */
1226 1241 if (t->t_intr_start) {
1227 1242 do {
1228 1243 start = t->t_intr_start;
1229 1244 interval = tsc_read() - start;
1230 1245 } while (atomic_cas_64(&t->t_intr_start, start, 0) != start);
1231 1246 cpu = CPU;
1232 1247 cpu->cpu_m.intrstat[t->t_pil][0] += interval;
1233 1248
1234 1249 atomic_add_64((uint64_t *)&cpu->cpu_intracct[cpu->cpu_mstate],
1235 1250 interval);
1236 1251 } else
1237 1252 ASSERT(t->t_intr == NULL);
1238 1253 }
1239 1254
1240 1255 /*
1241 1256 * An interrupt thread is returning from swtch(). Place a starting timestamp
1242 1257 * in its thread structure.
1243 1258 */
1244 1259 void
1245 1260 cpu_intr_swtch_exit(kthread_id_t t)
1246 1261 {
1247 1262 uint64_t ts;
1248 1263
1249 1264 ASSERT((t->t_flag & T_INTR_THREAD) != 0);
1250 1265 ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
1251 1266
1252 1267 do {
1253 1268 ts = t->t_intr_start;
1254 1269 } while (atomic_cas_64(&t->t_intr_start, ts, tsc_read()) != ts);
1255 1270 }
1256 1271
1257 1272 /*
1258 1273 * Dispatch a hilevel interrupt (one above LOCK_LEVEL)
1259 1274 */
1260 1275 /*ARGSUSED*/
1261 1276 static void
1262 1277 dispatch_hilevel(uint_t vector, uint_t arg2)
1263 1278 {
1264 1279 sti();
1265 1280 av_dispatch_autovect(vector);
1266 1281 cli();
1267 1282 }
1268 1283
1269 1284 /*
1270 1285 * Dispatch a soft interrupt
1271 1286 */
1272 1287 /*ARGSUSED*/
1273 1288 static void
1274 1289 dispatch_softint(uint_t oldpil, uint_t arg2)
1275 1290 {
1276 1291 struct cpu *cpu = CPU;
1277 1292
1278 1293 sti();
1279 1294 av_dispatch_softvect((int)cpu->cpu_thread->t_pil);
1280 1295 cli();
1281 1296
1282 1297 /*
1283 1298 * Must run softint_epilog() on the interrupt thread stack, since
1284 1299 * there may not be a return from it if the interrupt thread blocked.
1285 1300 */
1286 1301 dosoftint_epilog(cpu, oldpil);
1287 1302 }
1288 1303
1289 1304 /*
1290 1305 * Dispatch a normal interrupt
1291 1306 */
1292 1307 static void
1293 1308 dispatch_hardint(uint_t vector, uint_t oldipl)
1294 1309 {
1295 1310 struct cpu *cpu = CPU;
1296 1311
1297 1312 sti();
1298 1313 av_dispatch_autovect(vector);
1299 1314 cli();
1300 1315
1301 1316 /*
1302 1317 * Must run intr_thread_epilog() on the interrupt thread stack, since
1303 1318 * there may not be a return from it if the interrupt thread blocked.
1304 1319 */
1305 1320 intr_thread_epilog(cpu, vector, oldipl);
1306 1321 }
1307 1322
1308 1323 /*
1309 1324 * Deliver any softints the current interrupt priority allows.
1310 1325 * Called with interrupts disabled.
1311 1326 */
1312 1327 void
1313 1328 dosoftint(struct regs *regs)
1314 1329 {
1315 1330 struct cpu *cpu = CPU;
1316 1331 int oldipl;
1317 1332 caddr_t newsp;
1318 1333
1319 1334 while (cpu->cpu_softinfo.st_pending) {
1320 1335 oldipl = cpu->cpu_pri;
1321 1336 newsp = dosoftint_prolog(cpu, (caddr_t)regs,
1322 1337 cpu->cpu_softinfo.st_pending, oldipl);
1323 1338 /*
1324 1339 * If returned stack pointer is NULL, priority is too high
1325 1340 * to run any of the pending softints now.
1326 1341 * Break out and they will be run later.
1327 1342 */
1328 1343 if (newsp == NULL)
1329 1344 break;
1330 1345 switch_sp_and_call(newsp, dispatch_softint, oldipl, 0);
1331 1346 }
1332 1347 }
1333 1348
1334 1349 /*
1335 1350 * Interrupt service routine, called with interrupts disabled.
1336 1351 */
1337 1352 /*ARGSUSED*/
1338 1353 void
1339 1354 do_interrupt(struct regs *rp, trap_trace_rec_t *ttp)
1340 1355 {
1341 1356 struct cpu *cpu = CPU;
1342 1357 int newipl, oldipl = cpu->cpu_pri;
1343 1358 uint_t vector;
1344 1359 caddr_t newsp;
1345 1360
1346 1361 #ifdef TRAPTRACE
1347 1362 ttp->ttr_marker = TT_INTERRUPT;
1348 1363 ttp->ttr_ipl = 0xff;
1349 1364 ttp->ttr_pri = oldipl;
1350 1365 ttp->ttr_spl = cpu->cpu_base_spl;
1351 1366 ttp->ttr_vector = 0xff;
1352 1367 #endif /* TRAPTRACE */
1353 1368
1354 1369 cpu_idle_exit(CPU_IDLE_CB_FLAG_INTR);
1355 1370
1356 1371 ++*(uint16_t *)&cpu->cpu_m.mcpu_istamp;
1357 1372
1358 1373 /*
1359 1374 * If it's a softint go do it now.
1360 1375 */
1361 1376 if (rp->r_trapno == T_SOFTINT) {
1362 1377 dosoftint(rp);
1363 1378 ASSERT(!interrupts_enabled());
1364 1379 return;
1365 1380 }
1366 1381
1367 1382 /*
1368 1383 * Raise the interrupt priority.
1369 1384 */
1370 1385 newipl = (*setlvl)(oldipl, (int *)&rp->r_trapno);
1371 1386 #ifdef TRAPTRACE
1372 1387 ttp->ttr_ipl = newipl;
1373 1388 #endif /* TRAPTRACE */
1374 1389
1375 1390 /*
1376 1391 * Bail if it is a spurious interrupt
1377 1392 */
1378 1393 if (newipl == -1)
1379 1394 return;
1380 1395 cpu->cpu_pri = newipl;
1381 1396 vector = rp->r_trapno;
1382 1397 #ifdef TRAPTRACE
1383 1398 ttp->ttr_vector = vector;
1384 1399 #endif /* TRAPTRACE */
1385 1400 if (newipl > LOCK_LEVEL) {
1386 1401 /*
1387 1402 * High priority interrupts run on this cpu's interrupt stack.
1388 1403 */
1389 1404 if (hilevel_intr_prolog(cpu, newipl, oldipl, rp) == 0) {
1390 1405 newsp = cpu->cpu_intr_stack;
1391 1406 switch_sp_and_call(newsp, dispatch_hilevel, vector, 0);
1392 1407 } else { /* already on the interrupt stack */
1393 1408 dispatch_hilevel(vector, 0);
1394 1409 }
1395 1410 (void) hilevel_intr_epilog(cpu, newipl, oldipl, vector);
1396 1411 } else {
1397 1412 /*
1398 1413 * Run this interrupt in a separate thread.
1399 1414 */
1400 1415 newsp = intr_thread_prolog(cpu, (caddr_t)rp, newipl);
1401 1416 switch_sp_and_call(newsp, dispatch_hardint, vector, oldipl);
1402 1417 }
1403 1418
1404 1419 #if !defined(__xpv)
1405 1420 /*
1406 1421 * Deliver any pending soft interrupts.
1407 1422 */
1408 1423 if (cpu->cpu_softinfo.st_pending)
1409 1424 dosoftint(rp);
1410 1425 #endif /* !__xpv */
1411 1426 }
1412 1427
1413 1428
1414 1429 /*
1415 1430 * Common tasks always done by _sys_rtt, called with interrupts disabled.
1416 1431 * Returns 1 if returning to userland, 0 if returning to system mode.
1417 1432 */
1418 1433 int
1419 1434 sys_rtt_common(struct regs *rp)
1420 1435 {
1421 1436 kthread_t *tp;
1422 1437 extern void mutex_exit_critical_start();
1423 1438 extern long mutex_exit_critical_size;
1424 1439 extern void mutex_owner_running_critical_start();
1425 1440 extern long mutex_owner_running_critical_size;
1426 1441
1427 1442 loop:
1428 1443
1429 1444 /*
1430 1445 * Check if returning to user
1431 1446 */
1432 1447 tp = CPU->cpu_thread;
1433 1448 if (USERMODE(rp->r_cs)) {
1434 1449 /*
1435 1450 * Check if AST pending.
1436 1451 */
1437 1452 if (tp->t_astflag) {
1438 1453 /*
1439 1454 * Let trap() handle the AST
1440 1455 */
1441 1456 sti();
1442 1457 rp->r_trapno = T_AST;
1443 1458 trap(rp, (caddr_t)0, CPU->cpu_id);
1444 1459 cli();
1445 1460 goto loop;
1446 1461 }
1447 1462
1448 1463 #if defined(__amd64)
1449 1464 /*
1450 1465 * We are done if segment registers do not need updating.
1451 1466 */
1452 1467 if (tp->t_lwp->lwp_pcb.pcb_rupdate == 0)
1453 1468 return (1);
1454 1469
1455 1470 if (update_sregs(rp, tp->t_lwp)) {
1456 1471 /*
1457 1472 * 1 or more of the selectors is bad.
1458 1473 * Deliver a SIGSEGV.
1459 1474 */
1460 1475 proc_t *p = ttoproc(tp);
1461 1476
1462 1477 sti();
1463 1478 mutex_enter(&p->p_lock);
1464 1479 tp->t_lwp->lwp_cursig = SIGSEGV;
1465 1480 mutex_exit(&p->p_lock);
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1466 1481 psig();
1467 1482 tp->t_sig_check = 1;
1468 1483 cli();
1469 1484 }
1470 1485 tp->t_lwp->lwp_pcb.pcb_rupdate = 0;
1471 1486
1472 1487 #endif /* __amd64 */
1473 1488 return (1);
1474 1489 }
1475 1490
1491 +#if !defined(__xpv)
1476 1492 /*
1493 + * Assert that we're not trying to return into the syscall return
1494 + * trampolines. Things will go baaaaad if we try to do that.
1495 + *
1496 + * Note that none of these run with interrupts on, so this should
1497 + * never happen (even in the sysexit case the STI doesn't take effect
1498 + * until after sysexit finishes).
1499 + */
1500 + extern void tr_sysc_ret_start();
1501 + extern void tr_sysc_ret_end();
1502 + ASSERT(!(rp->r_pc >= (uintptr_t)tr_sysc_ret_start &&
1503 + rp->r_pc <= (uintptr_t)tr_sysc_ret_end));
1504 +#endif
1505 +
1506 + /*
1477 1507 * Here if we are returning to supervisor mode.
1478 1508 * Check for a kernel preemption request.
1479 1509 */
1480 1510 if (CPU->cpu_kprunrun && (rp->r_ps & PS_IE)) {
1481 1511
1482 1512 /*
1483 1513 * Do nothing if already in kpreempt
1484 1514 */
1485 1515 if (!tp->t_preempt_lk) {
1486 1516 tp->t_preempt_lk = 1;
1487 1517 sti();
1488 1518 kpreempt(1); /* asynchronous kpreempt call */
1489 1519 cli();
1490 1520 tp->t_preempt_lk = 0;
1491 1521 }
1492 1522 }
1493 1523
1494 1524 /*
1495 1525 * If we interrupted the mutex_exit() critical region we must
1496 1526 * reset the PC back to the beginning to prevent missed wakeups
1497 1527 * See the comments in mutex_exit() for details.
1498 1528 */
1499 1529 if ((uintptr_t)rp->r_pc - (uintptr_t)mutex_exit_critical_start <
1500 1530 mutex_exit_critical_size) {
1501 1531 rp->r_pc = (greg_t)mutex_exit_critical_start;
1502 1532 }
1503 1533
1504 1534 /*
1505 1535 * If we interrupted the mutex_owner_running() critical region we
1506 1536 * must reset the PC back to the beginning to prevent dereferencing
1507 1537 * of a freed thread pointer. See the comments in mutex_owner_running
1508 1538 * for details.
1509 1539 */
1510 1540 if ((uintptr_t)rp->r_pc -
1511 1541 (uintptr_t)mutex_owner_running_critical_start <
1512 1542 mutex_owner_running_critical_size) {
1513 1543 rp->r_pc = (greg_t)mutex_owner_running_critical_start;
1514 1544 }
1515 1545
1516 1546 return (0);
1517 1547 }
1518 1548
1519 1549 void
1520 1550 send_dirint(int cpuid, int int_level)
1521 1551 {
1522 1552 (*send_dirintf)(cpuid, int_level);
1523 1553 }
1524 1554
1525 1555 #define IS_FAKE_SOFTINT(flag, newpri) \
1526 1556 (((flag) & PS_IE) && \
1527 1557 (((*get_pending_spl)() > (newpri)) || \
1528 1558 bsrw_insn((uint16_t)cpu->cpu_softinfo.st_pending) > (newpri)))
1529 1559
1530 1560 /*
1531 1561 * do_splx routine, takes new ipl to set
1532 1562 * returns the old ipl.
1533 1563 * We are careful not to set priority lower than CPU->cpu_base_pri,
1534 1564 * even though it seems we're raising the priority, it could be set
1535 1565 * higher at any time by an interrupt routine, so we must block interrupts
1536 1566 * and look at CPU->cpu_base_pri
1537 1567 */
1538 1568 int
1539 1569 do_splx(int newpri)
1540 1570 {
1541 1571 ulong_t flag;
1542 1572 cpu_t *cpu;
1543 1573 int curpri, basepri;
1544 1574
1545 1575 flag = intr_clear();
1546 1576 cpu = CPU; /* ints are disabled, now safe to cache cpu ptr */
1547 1577 curpri = cpu->cpu_m.mcpu_pri;
1548 1578 basepri = cpu->cpu_base_spl;
1549 1579 if (newpri < basepri)
1550 1580 newpri = basepri;
1551 1581 cpu->cpu_m.mcpu_pri = newpri;
1552 1582 (*setspl)(newpri);
1553 1583 /*
1554 1584 * If we are going to reenable interrupts see if new priority level
1555 1585 * allows pending softint delivery.
1556 1586 */
1557 1587 if (IS_FAKE_SOFTINT(flag, newpri))
1558 1588 fakesoftint();
1559 1589 ASSERT(!interrupts_enabled());
1560 1590 intr_restore(flag);
1561 1591 return (curpri);
1562 1592 }
1563 1593
1564 1594 /*
1565 1595 * Common spl raise routine, takes new ipl to set
1566 1596 * returns the old ipl, will not lower ipl.
1567 1597 */
1568 1598 int
1569 1599 splr(int newpri)
1570 1600 {
1571 1601 ulong_t flag;
1572 1602 cpu_t *cpu;
1573 1603 int curpri, basepri;
1574 1604
1575 1605 flag = intr_clear();
1576 1606 cpu = CPU; /* ints are disabled, now safe to cache cpu ptr */
1577 1607 curpri = cpu->cpu_m.mcpu_pri;
1578 1608 /*
1579 1609 * Only do something if new priority is larger
1580 1610 */
1581 1611 if (newpri > curpri) {
1582 1612 basepri = cpu->cpu_base_spl;
1583 1613 if (newpri < basepri)
1584 1614 newpri = basepri;
1585 1615 cpu->cpu_m.mcpu_pri = newpri;
1586 1616 (*setspl)(newpri);
1587 1617 /*
1588 1618 * See if new priority level allows pending softint delivery
1589 1619 */
1590 1620 if (IS_FAKE_SOFTINT(flag, newpri))
1591 1621 fakesoftint();
1592 1622 }
1593 1623 intr_restore(flag);
1594 1624 return (curpri);
1595 1625 }
1596 1626
1597 1627 int
1598 1628 getpil(void)
1599 1629 {
1600 1630 return (CPU->cpu_m.mcpu_pri);
1601 1631 }
1602 1632
1603 1633 int
1604 1634 spl_xcall(void)
1605 1635 {
1606 1636 return (splr(ipltospl(XCALL_PIL)));
1607 1637 }
1608 1638
1609 1639 int
1610 1640 interrupts_enabled(void)
1611 1641 {
1612 1642 ulong_t flag;
1613 1643
1614 1644 flag = getflags();
1615 1645 return ((flag & PS_IE) == PS_IE);
1616 1646 }
1617 1647
1618 1648 #ifdef DEBUG
1619 1649 void
1620 1650 assert_ints_enabled(void)
1621 1651 {
1622 1652 ASSERT(!interrupts_unleashed || interrupts_enabled());
1623 1653 }
1624 1654 #endif /* DEBUG */
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