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9215 update CPUID defines
@@ -89,11 +89,11 @@
* cpuid instruction feature flags in %ecx (standard function 1)
*/
#define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
#define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
- /* 0x00000004 - reserved */
+#define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
#define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
#define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
#define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
#define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
#define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
@@ -102,19 +102,20 @@
#define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
/* 0x00000800 - reserved */
#define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
#define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
#define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
- /* 0x00008000 - reserved */
+#define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
/* 0x00010000 - reserved */
- /* 0x00020000 - reserved */
+#define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
#define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
#define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
#define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
#define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
#define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
#define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
+#define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
#define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
#define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
#define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
#define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
#define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
@@ -168,13 +169,21 @@
#define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
#define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
#define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
#define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
#define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
-#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
+#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
#define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
#define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
+ /* 0x00004000 - reserved */
+#define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
+#define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
+ /* 0x00020000 - reserved */
+ /* 0x00040000 - reserved */
+#define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
+ /* 0x00100000 - reserved */
+#define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
#define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
/*
* AMD uses %ebx for some of their features (extended function 0x80000008).
*/