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9210 remove KMDB branch debugging support
9211 ::crregs could do with cr2/cr3 support
9209 ::ttrace should be able to filter by thread
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
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--- old/usr/src/uts/intel/sys/controlregs.h
+++ new/usr/src/uts/intel/sys/controlregs.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
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14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright 2015, Joyent, Inc.
24 + *
25 + * Copyright 2018 Joyent, Inc.
24 26 */
25 27
26 28 #ifndef _SYS_CONTROLREGS_H
27 29 #define _SYS_CONTROLREGS_H
28 30
29 31 #ifndef _ASM
30 32 #include <sys/types.h>
31 33 #endif
32 34
33 35 #ifdef __cplusplus
34 36 extern "C" {
35 37 #endif
36 38
37 39 /*
38 40 * This file describes the x86 architecture control registers which
39 41 * are part of the privileged architecture.
40 42 *
41 43 * Many of these definitions are shared between IA-32-style and
42 44 * AMD64-style processors.
43 45 */
44 46
45 47 /* CR0 Register */
46 48
47 49 #define CR0_PG 0x80000000 /* paging enabled */
48 50 #define CR0_CD 0x40000000 /* cache disable */
49 51 #define CR0_NW 0x20000000 /* not writethrough */
50 52 #define CR0_AM 0x00040000 /* alignment mask */
51 53 #define CR0_WP 0x00010000 /* write protect */
52 54 #define CR0_NE 0x00000020 /* numeric error */
53 55 #define CR0_ET 0x00000010 /* extension type */
54 56 #define CR0_TS 0x00000008 /* task switch */
55 57 #define CR0_EM 0x00000004 /* emulation */
56 58 #define CR0_MP 0x00000002 /* monitor coprocessor */
57 59 #define CR0_PE 0x00000001 /* protection enabled */
58 60
59 61 /* XX64 eliminate these compatibility defines */
60 62
61 63 #define CR0_CE CR0_CD
62 64 #define CR0_WT CR0_NW
63 65
64 66 #define FMT_CR0 \
65 67 "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
66 68
67 69 /*
68 70 * Set the FPU-related control bits to explain to the processor that
69 71 * we're managing FPU state:
70 72 * - set monitor coprocessor (allow TS bit to control FPU)
71 73 * - set numeric exception (disable IGNNE# mechanism)
72 74 * - set task switch (#nm on first fp instruction)
73 75 * - clear emulate math bit (cause we're not emulating!)
74 76 */
75 77 #define CR0_ENABLE_FPU_FLAGS(cr) \
76 78 (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM)
77 79
78 80 /*
79 81 * Set the FPU-related control bits to explain to the processor that
80 82 * we're -not- managing FPU state:
81 83 * - set emulate (all fp instructions cause #nm)
82 84 * - clear monitor coprocessor (so fwait/wait doesn't #nm)
83 85 */
84 86 #define CR0_DISABLE_FPU_FLAGS(cr) \
85 87 (((cr) | CR0_EM) & (uint32_t)~CR0_MP)
86 88
87 89 /* CR3 Register */
88 90
89 91 #define CR3_PCD 0x00000010 /* cache disable */
90 92 #define CR3_PWT 0x00000008 /* write through */
91 93
92 94 #define FMT_CR3 "\20\5pcd\4pwt"
93 95
94 96 /* CR4 Register */
95 97
96 98 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */
97 99 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */
98 100 #define CR4_TSD 0x0004 /* time stamp disable */
99 101 #define CR4_DE 0x0008 /* debugging extensions */
100 102 #define CR4_PSE 0x0010 /* page size extensions */
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101 103 #define CR4_PAE 0x0020 /* physical address extension */
102 104 #define CR4_MCE 0x0040 /* machine check enable */
103 105 #define CR4_PGE 0x0080 /* page global enable */
104 106 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */
105 107 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */
106 108 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */
107 109 /* 0x0800 reserved */
108 110 /* 0x1000 reserved */
109 111 #define CR4_VMXE 0x2000
110 112 #define CR4_SMXE 0x4000
113 +#define CR4_PCIDE 0x20000 /* PCID enable */
111 114 #define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */
112 115 #define CR4_SMEP 0x100000 /* NX for user pages in kernel */
113 116 #define CR4_SMAP 0x200000 /* kernel can't access user pages */
114 117
115 118 #define FMT_CR4 \
116 - "\20\26smap\25smep\23osxsav" \
119 + "\20\26smap\25smep\23osxsav\22pcide" \
117 120 "\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge" \
118 121 "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
119 122
120 123 /*
121 124 * Enable the SSE-related control bits to explain to the processor that
122 125 * we're managing XMM state and exceptions
123 126 */
124 127 #define CR4_ENABLE_SSE_FLAGS(cr) \
125 128 ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT)
126 129
127 130 /*
128 131 * Disable the SSE-related control bits to explain to the processor
129 132 * that we're NOT managing XMM state
130 133 */
131 134 #define CR4_DISABLE_SSE_FLAGS(cr) \
132 135 ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
133 136
134 137 /* Intel's SYSENTER configuration registers */
135 138
136 139 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */
137 140 #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */
138 141 #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */
139 142
140 143 /* Intel's microcode registers */
141 144 #define MSR_INTC_UCODE_WRITE 0x79 /* microcode write */
142 145 #define MSR_INTC_UCODE_REV 0x8b /* microcode revision */
143 146 #define INTC_UCODE_REV_SHIFT 32 /* Bits 63:32 */
144 147
145 148 /* Intel's platform identification */
146 149 #define MSR_INTC_PLATFORM_ID 0x17
147 150 #define INTC_PLATFORM_ID_SHIFT 50 /* Bit 52:50 */
148 151 #define INTC_PLATFORM_ID_MASK 0x7
149 152
150 153 /* AMD's EFER register */
151 154
152 155 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */
153 156
154 157 #define AMD_EFER_FFXSR 0x4000 /* fast fxsave/fxrstor */
155 158 #define AMD_EFER_SVME 0x1000 /* svm enable */
156 159 #define AMD_EFER_NXE 0x0800 /* no-execute enable */
157 160 #define AMD_EFER_LMA 0x0400 /* long mode active (read-only) */
158 161 #define AMD_EFER_LME 0x0100 /* long mode enable */
159 162 #define AMD_EFER_SCE 0x0001 /* system call extensions */
160 163
161 164 #define FMT_AMD_EFER \
162 165 "\20\17ffxsr\15svme\14nxe\13lma\11lme\1sce"
163 166
164 167 /* AMD's SYSCFG register */
165 168
166 169 #define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */
167 170
168 171 #define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */
169 172 #define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */
170 173 #define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */
171 174 #define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */
172 175
173 176 #define FMT_AMD_SYSCFG \
174 177 "\20\26tom2\25mvdm\24mfdm\23mfde"
175 178
176 179 /* AMD's syscall/sysret MSRs */
177 180
178 181 #define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */
179 182 #define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */
180 183 #define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */
181 184 #define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */
182 185
183 186 /* AMD's FS.base and GS.base MSRs */
184 187
185 188 #define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */
186 189 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */
187 190 #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */
188 191 #define MSR_AMD_TSCAUX 0xc0000103 /* %ecx value on rdtscp insn */
189 192
190 193 /* AMD's configuration MSRs, weakly documented in the revision guide */
191 194
192 195 #define MSR_AMD_DC_CFG 0xc0011022
193 196
194 197 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3)
195 198 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10)
196 199
197 200 /* AMD's HWCR MSR */
198 201
199 202 #define MSR_AMD_HWCR 0xc0010015
200 203
201 204 #define AMD_HWCR_TLBCACHEDIS (UINT64_C(1) << 3)
202 205 #define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */
203 206 #define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */
204 207
205 208 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
206 209
207 210 #define MSR_AMD_NB_CFG 0xc001001f
208 211
209 212 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20)
210 213 #define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32)
211 214
212 215 #define MSR_AMD_BU_CFG 0xc0011023
213 216
214 217 #define AMD_BU_CFG_E298 (UINT64_C(1) << 1)
215 218
216 219 #define MSR_AMD_DE_CFG 0xc0011029
217 220
218 221 #define AMD_DE_CFG_E721 (UINT64_C(1))
219 222
220 223 /* AMD's osvw MSRs */
221 224 #define MSR_AMD_OSVW_ID_LEN 0xc0010140
222 225 #define MSR_AMD_OSVW_STATUS 0xc0010141
223 226
224 227
225 228 #define OSVW_ID_LEN_MASK 0xffffULL
226 229 #define OSVW_ID_CNT_PER_MSR 64
227 230
228 231 /*
229 232 * Enable PCI Extended Configuration Space (ECS) on Greyhound
230 233 */
231 234 #define AMD_GH_NB_CFG_EN_ECS (UINT64_C(1) << 46)
232 235
233 236 /* AMD microcode patch loader */
234 237 #define MSR_AMD_PATCHLEVEL 0x8b
235 238 #define MSR_AMD_PATCHLOADER 0xc0010020
236 239
237 240 #ifdef __cplusplus
238 241 }
239 242 #endif
240 243
241 244 #endif /* !_SYS_CONTROLREGS_H */
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