--- old/usr/src/uts/common/io/nxge/nxge_hcall.s	Thu Nov 14 19:00:11 2019
+++ new/usr/src/uts/common/io/nxge/nxge_hcall.s	Thu Nov 14 19:00:11 2019
@@ -87,181 +87,6 @@
 #define	N2NIU_CFGH_TX_LP_GET	0x145
 #define	N2NIU_CFGH_VR_ASSIGN	0x146
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
-	uint64_t raddr, uint64_t size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
-	uint64_t *raddr, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
-	uint64_t raddr, uint64_t size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx,
-	uint64_t *raddr, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
-{ return (0); }
-
-/*
- * KT: Interfaces functions which require the configuration handle
- */
-/*ARGSUSED*/
-uint64_t
-hv_niu_cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
-	uint64_t raddr, uint64_t size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
-	uint64_t *raddr, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
-	uint64_t raddr, uint64_t size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
-	uint64_t *raddr, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vr_unassign(uint32_t cookie)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
-    uint64_t raddr, uint64_t size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
-    uint64_t *raddr, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
-    uint64_t raddr, uint64_t size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
-    uint64_t *raddr, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param,
-	uint64_t *value)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param,
-	uint64_t value)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param,
-	uint64_t *value)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param,
-	uint64_t value)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx,
-	uint64_t *group, uint64_t *logdev)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx,
-		uint64_t *group, uint64_t *logdev)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	/*
 	 * hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
 	 *	uint64_t raddr, uint64_t size)
@@ -627,6 +452,4 @@
 	stw	%o1, [%g1]
 	SET_SIZE(hv_niu_cfgh_vr_assign)
 
-#endif	/* lint || __lint */
-
 #endif /*defined(sun4v)*/
--- old/usr/src/uts/common/io/tpm/tpm_hcall.s	Thu Nov 14 19:00:11 2019
+++ new/usr/src/uts/common/io/tpm/tpm_hcall.s	Thu Nov 14 19:00:11 2019
@@ -33,26 +33,6 @@
 #if defined(sun4v)
 #include <sys/hypervisor_api.h>
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-hcall_tpm_get(uint64_t locality, uint64_t offset, uint64_t size,
-    uint64_t *value)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint64_t
-hcall_tpm_put(uint64_t locality, uint64_t offset, uint64_t size,
-    uint64_t value)
-{
-	return (0);
-}
-
-#else  /* lint || __lint */
-
 /*
  * hcall_tpm_get(uint64_t locality, uint64_t offset, uint64_t size,
  *     uint64_t *value)
@@ -78,6 +58,4 @@
 	nop
 	SET_SIZE(hcall_tpm_put)
 
-#endif /* lint || __lint */
-
 #endif /* defined(sun4v) */
--- old/usr/src/uts/i86pc/Makefile.files	Thu Nov 14 19:00:11 2019
+++ new/usr/src/uts/i86pc/Makefile.files	Thu Nov 14 19:00:11 2019
@@ -152,21 +152,13 @@
 #	locore.o is special. It must be the first file relocated so that it
 #	it is relocated just where its name implies.
 #
-SPECIAL_OBJS_32 +=		\
+SPECIAL_OBJS +=			\
 	locore.o		\
 	fast_trap_asm.o		\
 	interrupt.o		\
-	syscall_asm.o
-
-SPECIAL_OBJS_64 +=		\
-	locore.o		\
-	fast_trap_asm.o		\
-	interrupt.o		\
-	syscall_asm_amd64.o	\
+	syscall_asm.o		\
 	kpti_trampolines.o
 
-SPECIAL_OBJS += $(SPECIAL_OBJS_$(CLASS))
-
 #
 # Objects that get compiled into the identity mapped PT_LOAD section of unix
 # to handle the earliest part of booting.
@@ -271,7 +263,6 @@
 	sseblk.o		\
 	swtch.o			\
 	syscall_asm.o		\
-	syscall_asm_amd64.o	\
 	kpti_trampolines.o	\
 	cpr_wakecode.o
 
--- old/usr/src/uts/i86pc/Makefile.i86pc	Thu Nov 14 19:00:12 2019
+++ new/usr/src/uts/i86pc/Makefile.i86pc	Thu Nov 14 19:00:12 2019
@@ -25,6 +25,7 @@
 # Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
 # Copyright (c) 2013 Andrew Stormont.  All rights reserved.
 # Copyright 2019 OmniOS Community Edition (OmniOSce) Association.
+# Copyright 2019 Joyent, Inc.
 #
 #
 #	This makefile contains the common definitions for the i86pc unix
@@ -98,15 +99,6 @@
 ALL_BUILDS		= $(ALL_BUILDS64)
 
 #
-#	x86 or amd64 inline templates
-#
-INLINES_32		= $(UTSBASE)/intel/ia32/ml/ia32.il \
-			  $(UTSBASE)/$(PLATFORM)/ml/ia32.il
-INLINES_64		= $(UTSBASE)/intel/amd64/ml/amd64.il \
-			  $(UTSBASE)/$(PLATFORM)/ml/amd64.il
-INLINES			+= $(INLINES_$(CLASS))
-
-#
 #	kernel-specific optimizations; override default in Makefile.master
 #
 
@@ -120,7 +112,7 @@
 
 CFLAGS			= $(CFLAGS_XARCH)
 CFLAGS			+= $(COPTIMIZE)
-CFLAGS			+= $(INLINES) -D_ASM_INLINES
+CFLAGS			+= -D_ASM_INLINES
 CFLAGS			+= $(CCMODE)
 CFLAGS			+= $(SPACEFLAG)
 CFLAGS			+= $(CCUNBOUND)
@@ -146,9 +138,7 @@
 MODSTUBS	 = $(UTSBASE)/intel/ia32/ml/modstubs.s
 GENASSYM_SRC	 = $(UTSBASE)/$(PLATFORM)/ml/genassym.c
 OFFSETS_SRC	 = $(UTSBASE)/$(PLATFORM)/ml/offsets.in
-PLATFORM_OFFSETS_32	= $(UTSBASE)/$(PLATFORM)/ml/mach_offsets.in
-PLATFORM_OFFSETS_64	= $(UTSBASE)/intel/amd64/ml/mach_offsets.in
-PLATFORM_OFFSETS_SRC	= $(PLATFORM_OFFSETS_$(CLASS))
+PLATFORM_OFFSETS_SRC	= $(UTSBASE)/intel/amd64/ml/mach_offsets.in
 KDI_OFFSETS_SRC	 = $(UTSBASE)/intel/kdi/kdi_offsets.in
 
 #
@@ -186,7 +176,6 @@
 
 $(IF_DEBUG_OBJ)trap.o		:= DEBUG_DEFS += -DTRAPDEBUG -DTRAPTRACE
 $(IF_DEBUG_OBJ)syscall_asm.o	:= DEBUG_DEFS += -DSYSCALLTRACE -DTRAPTRACE
-$(IF_DEBUG_OBJ)syscall_asm_amd64.o := DEBUG_DEFS += -DSYSCALLTRACE -DTRAPTRACE
 $(IF_DEBUG_OBJ)fast_trap_asm.o	:= DEBUG_DEFS += -DTRAPTRACE
 $(IF_DEBUG_OBJ)interrupt.o	:= DEBUG_DEFS += -DTRAPTRACE
 $(IF_DEBUG_OBJ)intr.o		:= DEBUG_DEFS += -DTRAPTRACE
--- old/usr/src/uts/i86pc/boot/boot_gdt.s	Thu Nov 14 19:00:12 2019
+++ new/usr/src/uts/i86pc/boot/boot_gdt.s	Thu Nov 14 19:00:12 2019
@@ -25,24 +25,6 @@
  */
 
 
-#if defined(__lint)
-#pragma pack(1)
-struct {
-	uint16_t limit_low;
-	uint16_t base_low;
-	uint8_t base_middle;
-	uint8_t attr;
-	uint8_t attr_and_limit;
-	uint8_t base_high;
-} global_descriptor_table[8];
-struct {
-	uint16_t limit;	/* sizeof (global_descriptor_table) - 1 */
-	void     *base;	/* &global_descriptor_table */
-} gdt_info;
-#pragma pack()
-
-#else	/* __lint */
-
 	.align 16
 	.data
 	/*
@@ -143,4 +125,3 @@
 	.4byte 0
 	.skip 0x6c0, 0
 
-#endif	/* __lint */
--- old/usr/src/uts/i86pc/dboot/dboot_asm.s	Thu Nov 14 19:00:12 2019
+++ new/usr/src/uts/i86pc/dboot/dboot_asm.s	Thu Nov 14 19:00:12 2019
@@ -27,27 +27,6 @@
 #include <sys/asm_linkage.h>
 #include <sys/asm_misc.h>
 
-#if defined(__lint)
-
-#include "dboot_asm.h"
-
-/* ARGSUSED */
-uint32_t
-get_cpuid_edx(uint32_t *eax)
-{ return (0); }
-
-/* ARGSUSED */
-void
-outb(int port, uint8_t value)
-{}
-
-/* ARGSUSED */
-uint8_t
-inb(int port)
-{ return (0); }
-
-#else /* __lint */
-
 #if defined(__amd64)
 
 	/*
@@ -140,4 +119,3 @@
 
 #endif	/* __i386 */
 
-#endif /* __lint */
--- old/usr/src/uts/i86pc/dboot/dboot_grub.s	Thu Nov 14 19:00:12 2019
+++ new/usr/src/uts/i86pc/dboot/dboot_grub.s	Thu Nov 14 19:00:12 2019
@@ -24,12 +24,6 @@
  * Use is subject to license terms.
  */
 
-#if defined(__lint)
-
-int silence_lint_warnings = 0;
-
-#else /* __lint */
-
 #include <sys/multiboot.h>
 #include <sys/multiboot2.h>
 #include <sys/asm_linkage.h>
@@ -372,4 +366,3 @@
 	.skip 4096
 	.long	0
 
-#endif /* __lint */
--- old/usr/src/uts/i86pc/dboot/dboot_xen.s	Thu Nov 14 19:00:13 2019
+++ new/usr/src/uts/i86pc/dboot/dboot_xen.s	Thu Nov 14 19:00:13 2019
@@ -24,16 +24,10 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/asm_linkage.h>
 #include <sys/asm_misc.h>
 #include "dboot_xboot.h"
 
-#if defined(__lint)
-
-#else /* __lint */
-
 #if defined(__amd64)
 
 	ENTRY_NP(_start)
@@ -125,4 +119,3 @@
 
 #endif	/* __i386 */
 
-#endif /* __lint */
--- old/usr/src/uts/i86pc/ml/amd64.il	Thu Nov 14 19:00:13 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,179 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-
-/
-/ Inline functions specific to the i86pc kernel running on bare metal.
-/
-
-/
-/ return value of cr3 register
-/
-	.inline	getcr3,0
-	movq	%cr3, %rax
-	.end
-
-/
-/ reload cr3 register with its current value
-/
-	.inline	reload_cr3,0
-	movq	%cr3, %rdi
-	movq	%rdi, %cr3
-	.end
-
-/
-/ set cr3 register with new value
-/
-	.inline	setcr3,0
-	movq	%rdi, %cr3
-	.end
-
-/
-/ return value of cr8 register
-/
-	.inline	getcr8,0
-	movq	%cr8, %rax
-	.end
-
-/
-/ set cr8 register
-/
-	.inline	setcr8,0
-	movq	%rdi, %cr8
-	.end
-
-/
-/ enable interrupts
-/
-	.inline	sti,0
-	sti
-	.end
-
-/
-/ disable interrupts
-/
-	.inline cli,0
-	cli
-	.end
-
-/
-/ disable interrupts and return value describing if interrupts were enabled
-/
-	.inline	clear_int_flag,0
-	pushfq
-	cli
-	popq	%rax
-	.end
-
-	.inline	intr_clear,0
-	pushfq
-	cli
-	popq	%rax
-	.end
-
-/
-/ return the value of the flags register
-/
-	.inline	getflags,0
-	pushfq
-	popq	%rax
-	.end
-
-/
-/ restore interrupt enable flag to value returned from 'clear_int_flag' above
-/
-	.inline restore_int_flag,4
-	testq	$0x200, %rdi
-	jz	1f
-	sti
-1:
-	.end
-
-	.inline intr_restore,4
-	testq	$0x200, %rdi
-	jz	1f
-	sti
-1:
-	.end
-
-/
-/ in and out
-/
-	.inline	inb,4
-	movq	%rdi, %rdx
-	xorq    %rax, %rax
-	inb	(%dx)
-	.end
-
-	.inline	inw,4
-	movq	%rdi, %rdx
-	xorq    %rax, %rax
-	inw	(%dx)
-	.end
-
-	.inline	inl,4
-	movq	%rdi, %rdx
-	xorq    %rax, %rax
-	inl	(%dx)
-	.end
-
-	.inline	outb,8
-	movq	%rdi, %rdx
-	movq	%rsi, %rax
-	outb	(%dx)
-	.end
-
-	.inline	outw,8
-	movq	%rdi, %rdx
-	movq	%rsi, %rax
-	outw	(%dx)
-	.end
-
-	.inline	outl,8
-	movq	%rdi, %rdx
-	movq	%rsi, %rax
-	outl	(%dx)
-	.end
-
-/*
- * Call the halt instruction. This will put the CPU to sleep until
- * it is again awoken via an interrupt.
- * This function should be called with interrupts already disabled
- * for the CPU.
- * Note that "sti" will only enable interrupts at the end of the
- * subsequent instruction...in this case: "hlt".
- */
-	.inline i86_halt,0
-	sti
-	hlt
-	.end
-/
-/ execute the bsrw instruction
-/
-	.inline bsrw_insn,4
-	xorl	%eax, %eax
-	bsrw	%di, %ax
-	.end
--- old/usr/src/uts/i86pc/ml/bios_call_src.s	Thu Nov 14 19:00:13 2019
+++ new/usr/src/uts/i86pc/ml/bios_call_src.s	Thu Nov 14 19:00:13 2019
@@ -24,14 +24,10 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
+/*
+ * Copyright 2019 Joyent, Inc.
+ */
 
-#if defined(__lint)
-
-int silence_lint = 0;
-
-#else
-
 #include <sys/segments.h>
 #include <sys/controlregs.h>
 
@@ -44,46 +40,12 @@
  */
 #define DATASZ	.byte 0x66;
 
-#if defined(__amd64)
-#define	MOVCR(x, y)	movq  x,%rax; movq  %rax, y
-#define LOAD_XAX(sym)	leaq	sym, %rax
-#elif defined(__i386)
-#define	MOVCR(x, y)	movl  x,%eax; movl  %eax, y
-#define LOAD_XAX(sym)	leal	sym, %eax
-#endif
-
 	.globl	_start
 _start:
 
-#if defined(__i386)
-
 	/*
 	 * Save caller registers
 	 */
-	movl	%ebp, save_ebp
-	movl	%esp, save_esp
-	movl	%ebx, save_ebx
-	movl	%esi, save_esi
-	movl	%edi, save_edi
-
-	/* get registers argument into esi */
-	movl	8(%esp), %esi
-
-	/* put interrupt number in %bl */
-	movl	4(%esp), %ebx
-
-	/* Switch to a low memory stack */
-	movl	$_start, %esp
-
-	/* allocate space for args on stack */
-	subl	$18, %esp
-	movl	%esp, %edi
-
-#elif defined(__amd64)
-
-	/*
-	 * Save caller registers
-	 */
 	movq	%rbp, save_rbp
 	movq	%rsp, save_rsp
 	movq	%rbx, save_rbx
@@ -103,8 +65,6 @@
 	subq	$18, %rsp
 	movq	%rsp, %rdi
 
-#endif
-
 	/* copy args from high memory to stack in low memory */
 	cld
 	movl	$18, %ecx
@@ -123,11 +83,13 @@
 	movw	%es, save_es
 	movw	%fs, save_fs
 	movw	%gs, save_gs
-	MOVCR(	%cr4, save_cr4)
-	MOVCR(	%cr3, save_cr3)
-	MOVCR(	%cr0, save_cr0)
+	movq	%cr4, %rax
+	movq	%rax, save_cr4
+	movq	%cr3, %rax
+	movq	%rax, save_cr3
+	movq	%cr0, %rax
+	movq	%rax, save_cr0
 
-#if defined(__amd64)
 	/*
 	 * save/clear the extension parts of the fs/gs base registers and cr8
 	 */
@@ -157,18 +119,17 @@
 
 	movq	%cr8, %rax
 	movq	%rax, save_cr8
-#endif
 
 	/*
 	 * set offsets in 16 bit ljmp instructions below
 	 */
-	LOAD_XAX(enter_real)
+	leaq	enter_real, %rax
 	movw	%ax, enter_real_ljmp
 
-	LOAD_XAX(enter_protected)
+	leaq	enter_protected, %rax
 	movw	%ax, enter_protected_ljmp
 
-	LOAD_XAX(gdt_info)
+	leaq	gdt_info, %rax
 	movw	%ax, gdt_info_load
 
 	/*
@@ -181,7 +142,6 @@
 	/*
 	 * zero out all the registers to make sure they're 16 bit clean
 	 */
-#if defined(__amd64)
 	xorq	%r8, %r8
 	xorq	%r9, %r9
 	xorq	%r10, %r10
@@ -190,7 +150,6 @@
 	xorq	%r13, %r13
 	xorq	%r14, %r14
 	xorq	%r15, %r15
-#endif
 	xorl	%eax, %eax
 	xorl	%ebx, %ebx
 	xorl	%ecx, %ecx
@@ -205,9 +164,8 @@
 	lgdt	gdt_info
 	lidt	idt_info
 
-#if defined(__amd64)
 	/*
-	 * Shut down 64 bit mode. First get into compatiblity mode.
+	 * Shut down 64 bit mode. First get into compatibility mode.
 	 */
 	movq	%rsp, %rax
 	pushq	$B32DATA_SEL
@@ -238,7 +196,6 @@
 	rdmsr
 	btcl	$8, %eax		/* bit 8 Long Mode Enable bit */
 	wrmsr
-#endif
 
 	/*
 	 * ok.. now enter 16 bit mode, so we can shut down protected mode
@@ -351,7 +308,6 @@
 	movl	save_cr3, %eax
 	movl	%eax, %cr3
 
-#if defined(__amd64)
 	/*
 	 * re-enable long mode
 	 */
@@ -359,7 +315,6 @@
 	rdmsr
 	btsl	$8, %eax
 	wrmsr
-#endif
 
 	movl	save_cr0, %eax
 	movl	%eax, %cr0
@@ -367,7 +322,6 @@
 enter_paging:
 
 
-#if defined(__amd64)
 	/*
 	 * transition back to 64 bit mode
 	 */
@@ -376,7 +330,6 @@
 	lret
 longmode:
 	.code64
-#endif
 	/*
 	 * restore caller frame pointer and segment registers
 	 */
@@ -388,15 +341,9 @@
 	 * in its corresponding GDT selector. The busy bit is the 2nd bit in
 	 * the 5th byte of the selector.
 	 */
-#if defined(__i386)
-	movzwl	save_tr, %eax
-	addl	save_gdt+2, %eax
-	btcl	$1, 5(%eax)
-#elif defined(__amd64)
 	movzwq	save_tr, %rax
 	addq	save_gdt+2, %rax
 	btcl	$1, 5(%rax)
-#endif
 	ltr	save_tr
 	movw	save_ds, %ds
 	movw	save_ss, %ss
@@ -404,18 +351,11 @@
 	movw	save_fs, %fs
 	movw	save_gs, %gs
 
-#if defined(__i386)
-	pushl	save_cs
-	pushl	$.newcs
-	lret
-#elif defined(__amd64)
 	pushq	save_cs
 	pushq	$.newcs
 	lretq
-#endif
 .newcs:
 
-#if defined(__amd64)
 	/*
 	 * restore the hidden kernel segment base register values
 	 */
@@ -439,29 +379,10 @@
 	je	1f
 	movq	%rax, %cr8
 1:
-#endif
 
 	/*
 	 * copy results to caller's location, then restore remaining registers
 	 */
-#if defined(__i386)
-	movl    save_esp, %edi
-	movl	8(%edi), %edi
-	movl	%esp, %esi
-	movl	$18, %ecx
-	rep
-	movsb
-	movw	18(%esp), %ax
-	andl	$0xffff, %eax
-	movl    save_ebx, %ebx
-	movl    save_esi, %esi
-	movl    save_edi, %edi
-	movl    save_esp, %esp
-	movl    save_ebp, %ebp
-	movl    save_esp, %esp
-	ret
-
-#elif defined(__amd64)
 	movq    save_rsi, %rdi
 	movq	%rsp, %rsi
 	movq	$18, %rcx
@@ -478,9 +399,7 @@
 	movq    save_rsp, %rsp
 	ret
 
-#endif
 
-
 /*
  * Caller's registers to restore
  */
@@ -497,7 +416,6 @@
 	.long	0
 
 	.align 8
-#if defined(__amd64)
 save_rsi:
 	.quad	0
 save_rbx:
@@ -522,7 +440,6 @@
 	.quad	0
 save_cr8:
 	.quad	0
-#endif	/* __amd64 */
 
 save_idt:
 	.quad	0
@@ -562,4 +479,3 @@
  * We need to trampoline thru a gdt we have in low memory.
  */
 #include "../boot/boot_gdt.s"
-#endif /* __lint */
--- old/usr/src/uts/i86pc/ml/comm_page.s	Thu Nov 14 19:00:13 2019
+++ new/usr/src/uts/i86pc/ml/comm_page.s	Thu Nov 14 19:00:13 2019
@@ -20,7 +20,7 @@
 #include <sys/comm_page.h>
 #include <sys/tsc.h>
 
-#if defined(_GENCTF) || defined(__lint)
+#if defined(_GENCTF)
 
 hrtime_t tsc_last;
 hrtime_t tsc_resume_cap;
@@ -37,7 +37,7 @@
 
 comm_page_t comm_page;
 
-#else /* defined(_GENCTF) || defined(__lint) */
+#else /* defined(_GENCTF) */
 
 #include "assym.h"
 
@@ -85,4 +85,4 @@
 	/* pad out the rest of the page from the struct end */
 	.fill	_CONST(COMM_PAGE_SIZE - COMM_PAGE_S_SIZE), 1, 0
 
-#endif /* defined(_GENCTF) || defined(__lint) */
+#endif /* defined(_GENCTF) */
--- old/usr/src/uts/i86pc/ml/cpr_wakecode.s	Thu Nov 14 19:00:14 2019
+++ new/usr/src/uts/i86pc/ml/cpr_wakecode.s	Thu Nov 14 19:00:14 2019
@@ -30,10 +30,8 @@
 #include <sys/x86_archext.h>
 #include <sys/cpr_wakecode.h>
 
-#if !defined(__lint)
 #include <sys/segments.h>
 #include "assym.h"
-#endif
 
 #ifdef  DEBUG
 #define LED     1
@@ -76,17 +74,6 @@
  *
  */
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-int
-wc_save_context(wc_cpu_t *pcpu)
-{ return 0; }
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(wc_save_context)
 
 	movq	(%rsp), %rdx		/ return address
@@ -174,60 +161,7 @@
 
 	SET_SIZE(wc_save_context)
 
-#elif defined(__i386)
 
-	ENTRY_NP(wc_save_context)
-
-	movl	4(%esp), %eax		/ wc_cpu_t *
-	movl	%eax, WC_VIRTADDR(%eax)
-
-	movl	(%esp), %edx		/ return address
-	movl	%edx, WC_RETADDR(%eax)
-
-	str	WC_TR(%eax)		/ stash everything else we need
-	sgdt	WC_GDT(%eax)
-	sldt	WC_LDT(%eax)
-	sidt	WC_IDT(%eax)
-
-	movl	%cr0, %edx
-	movl	%edx, WC_CR0(%eax)
-	movl	%cr3, %edx
-	movl	%edx, WC_CR3(%eax)
-	movl	%cr4, %edx
-	movl	%edx, WC_CR4(%eax)
-
-	movl	%ebx, WC_EBX(%eax)
-	movl	%edi, WC_EDI(%eax)
-	movl	%esi, WC_ESI(%eax)
-	movl	%ebp, WC_EBP(%eax)
-	movl	%esp, WC_ESP(%eax)
-
-	movw	%ss, WC_SS(%eax)
-	movw	%cs, WC_CS(%eax)
-	movw	%ds, WC_DS(%eax)
-	movw	%es, WC_ES(%eax)
-	movw	%fs, WC_FS(%eax)
-	movw	%gs, WC_GS(%eax)
-
-	pushfl
-	popl	WC_EFLAGS(%eax)
-
-	pushl	%gs:CPU_ID		/ save current cpu id
-	popl	WC_CPU_ID(%eax)
-
-	wbinvd				/ flush the cache
-	mfence
-
-	movl	$1, %eax		/ at suspend return 1
-	ret
-
-	SET_SIZE(wc_save_context)
-
-#endif	/* __amd64 */
-
-#endif /* lint */
-
-
 /*
  *	Our assumptions:
  *		- We are running in real mode.
@@ -244,20 +178,6 @@
  *		- We return to original caller (a la setjmp)
  */
 
-#if defined(lint) || defined(__lint)
-
-void
-wc_rm_start(void)
-{}
-
-void
-wc_rm_end(void)
-{}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(wc_rm_start)
 
 	/*
@@ -871,299 +791,4 @@
 	.globl wc_rm_end
 wc_rm_end:
 	nop
-
-#elif defined(__i386)
-
-	ENTRY_NP(wc_rm_start)
-
-/entry:	jmp		entry			/ stop here for HDT
-
-	cli
-	movw		%cs, %ax
-	movw		%ax, %ds		/ establish ds ...
-	movw		%ax, %ss		/ ... and ss:esp
-	D16 movl	$WC_STKSTART, %esp
-
-#if     LED
-	D16 movl        $WC_LED, %edx
-	D16 movb        $0xd1, %al
-	outb    (%dx)
-#endif
-
-#if     SERIAL
-	D16 movl        $WC_COM, %edx
-	D16 movb        $0x61, %al
-	outb    (%dx)
-#endif
-
-
-	D16 call	vgainit
-	D16 call	kbdinit
-	D16 call	cominit
-
-#if     LED
-	D16 movl        $WC_LED, %edx
-	D16 movb        $0xd2, %al
-	outb    (%dx)
-#endif
-
-#if     SERIAL
-	D16 movl        $WC_COM, %edx
-	D16 movb        $0x62, %al
-	outb    (%dx)
-#endif
-
-	D16 A16 movl	$WC_CPU, %ebx		/ base add of wc_cpu_t
-
-#if     LED
-	D16 movb        $0xd3, %al
-	outb    $WC_LED
-#endif
-
-#if     SERIAL
-	D16 movl        $WC_COM, %edx
-	D16 movb        $0x63, %al
-	outb    (%dx)
-#endif
-
-	D16 A16 movl	%cs:WC_DS(%ebx), %edx	/ %ds post prot/paging transit
-
-#if     LED
-	D16 movb        $0xd4, %al
-	outb    $WC_LED
-#endif
-
-	D16 A16 lgdt	%cs:WC_GDT(%ebx)	/ restore gdt and idtr
-	D16 A16 lidt	%cs:WC_IDT(%ebx)
-
-#if     LED
-	D16 movb        $0xd5, %al
-	outb    $WC_LED
-#endif
-
-	D16 A16 movl	%cs:WC_CR4(%ebx), %eax	/ restore cr4
-	D16 andl	$_BITNOT(CR4_PGE), %eax / don't set Global Enable yet
-	movl		%eax, %cr4
-
-#if     LED
-	D16 movb        $0xd6, %al
-	outb    $WC_LED
-#endif
-
-	D16 A16 movl	%cs:WC_CR3(%ebx), %eax	/ set PDPT
-	movl		%eax, %cr3
-
-#if     LED
-	D16 movb        $0xd7, %al
-	outb    $WC_LED
-#endif
-
-	D16 A16 movl	%cs:WC_CR0(%ebx), %eax	/ enable prot/paging, etc.
-	movl		%eax, %cr0
-
-#if     LED
-	D16 movb        $0xd8, %al
-	outb    $WC_LED
-#endif
-
-	D16 A16 movl	%cs:WC_VIRTADDR(%ebx), %ebx	/ virtaddr of wc_cpu_t
-
-#if     LED
-	D16 movb        $0xd9, %al
-	outb    $WC_LED
-#endif
-
-#if     LED
-	D16 movb        $0xda, %al
-	outb    $WC_LED
-#endif
-
-	jmp		flush			/ flush prefetch queue
-flush:
-	D16 pushl	$KCS_SEL
-	D16 pushl	$kernel_wc_code
-	D16 lret				/ re-appear at kernel_wc_code
-
-
-/*
- * Support routine to re-initialize VGA subsystem
- */
-vgainit:
-	D16 ret
-
-/*
- * Support routine to re-initialize keyboard (which is USB - help!)
- */
-kbdinit:
-	D16 ret
-
-/*
- * Support routine to re-initialize COM ports to something sane for debug output
- */
-cominit:
-#if     DEBUG
-/*
- * on debug kernels we need to initialize COM1 & COM2 here, so that
- * we can get debug output before the asy driver has resumed
- */
-
-/ select COM1
-	D16 movl	$_CONST(COM1+LCR), %edx
-	D16 movb	$DLAB, %al		/ divisor latch
-	outb	(%dx)
-
-	D16 movl	$_CONST(COM1+DLL), %edx	/ divisor latch lsb
-	D16 movb	$B9600L, %al		/ divisor latch
-	outb	(%dx)
-
-	D16 movl	$_CONST(COM1+DLH), %edx	/ divisor latch hsb
-	D16 movb	$B9600H, %al		/ divisor latch
-	outb	(%dx)
-
-	D16 movl	$_CONST(COM1+LCR), %edx	/ select COM1
-	D16 movb	$_CONST(STOP1|BITS8), %al	/ 1 stop bit, 8bit word len
-	outb	(%dx)
-
-	D16 movl	$_CONST(COM1+MCR), %edx	/ select COM1
-	D16 movb	$_CONST(RTS|DTR), %al		/ 1 stop bit, 8bit word len
-	outb	(%dx)
-
-/ select COM2
-	D16 movl	$_CONST(COM2+LCR), %edx
-	D16 movb	$DLAB, %al		/ divisor latch
-	outb	(%dx)
-
-	D16 movl	$_CONST(COM2+DLL), %edx	/ divisor latch lsb
-	D16 movb	$B9600L, %al		/ divisor latch
-	outb	(%dx)
-
-	D16 movl	$_CONST(COM2+DLH), %edx	/ divisor latch hsb
-	D16 movb	$B9600H, %al		/ divisor latch
-	outb	(%dx)
-
-	D16 movl	$_CONST(COM2+LCR), %edx	/ select COM1
-	D16 movb	$_CONST(STOP1|BITS8), %al	/ 1 stop bit, 8bit word len
-	outb	(%dx)
-
-	D16 movl	$_CONST(COM2+MCR), %edx	/ select COM1
-	D16 movb	$_CONST(RTS|DTR), %al		/ 1 stop bit, 8bit word len
-	outb	(%dx)
-#endif	/*	DEBUG	*/
-
-	D16 ret
-
-	.globl wc_rm_end
-wc_rm_end:
-	nop
-
-	.globl	kernel_wc_code
-kernel_wc_code:
-	/ At this point we are with kernel's cs and proper eip.
-	/ We will be executing not from the copy in real mode platter,
-	/ but from the original code where boot loaded us.
-	/ By this time GDT and IDT are loaded as is cr0, cr3 and cr4.
-	/ %ebx is wc_cpu
-	/ %dx is our ds
-
-#if     LED
-	D16 movb        $0xdb, %al
-	outb	$WC_LED
-#endif
-
-/ got here OK
-
-	movw	%dx, %ds		/ $KDS_SEL
-
-#if     LED
-	movb	$0xdc, %al
-	outb	$WC_LED
-#endif
-
-	/*
-	 * Before proceeding, enable usage of the page table NX bit if
-	 * that's how the page tables are set up.
-	 */
-	bt      $X86FSET_NX, x86_featureset
-	jnc     1f
-	movl    $MSR_AMD_EFER, %ecx
-	rdmsr
-	orl     $AMD_EFER_NXE, %eax
-	wrmsr
-1:
-
-	movl	WC_CR4(%ebx), %eax	/ restore full cr4 (with Global Enable)
-	movl	%eax, %cr4
-
-
-	lldt	WC_LDT(%ebx)		/ $LDT_SEL
-
-	movzwl	WC_TR(%ebx), %eax	/ clear TSS busy bit
-	addl	WC_GDT+2(%ebx), %eax
-	andl	$_BITNOT(0x200), 4(%eax)
-	ltr	WC_TR(%ebx)		/ $UTSS_SEL
-
-	movw	WC_SS(%ebx), %ss	/ restore segment registers
-	movw	WC_ES(%ebx), %es
-	movw	WC_FS(%ebx), %fs
-	movw	WC_GS(%ebx), %gs
-
-	/*
-	 * set the stack pointer to point into the identity mapped page
-	 * temporarily, so we can make function calls
-	 */
-	.globl  rm_platter_va
-	movl    rm_platter_va, %eax
-	movl	$WC_STKSTART, %esp
-	addl	%eax, %esp
-	movl	%esp, %ebp
-
-	/*
-	 * if we are not running on the boot CPU restore stack contents by
-	 * calling i_cpr_restore_stack(curthread, save_stack);
-	 */
-	call	i_cpr_bootcpuid
-	cmpl	%eax, WC_CPU_ID(%ebx)
-	je	2f
-
-	pushl	WC_SAVED_STACK(%ebx)
-	pushl	%gs:CPU_THREAD
-	call	i_cpr_restore_stack
-	addl	$0x10, %esp
-2:
-
-	movl	WC_ESP(%ebx), %esp
-	movl	%esp, %ebp
-
-	movl	WC_RETADDR(%ebx), %eax	/ return to caller of wc_save_context
-	movl	%eax, (%esp)
-
-	/*
-	 * APIC initialization, skip iff function pointer is NULL
-	 */
-	cmpl	$0, ap_mlsetup
-	je	3f
-	call	*ap_mlsetup
-3:
-
-	call	*cpr_start_cpu_func
-
-	pushl	WC_EFLAGS(%ebx)		/ restore flags
-	popfl
-
-	movl	WC_EDI(%ebx), %edi	/ restore general registers
-	movl	WC_ESI(%ebx), %esi
-	movl	WC_EBP(%ebx), %ebp
-	movl	WC_EBX(%ebx), %ebx
-
-/exit:	jmp	exit			/ stop here for HDT
-
-	xorl	%eax, %eax		/ at wakeup return 0
-	ret
-
-	SET_SIZE(wc_rm_start)
-
-
-#endif	/* defined(__amd64) */
-
-#endif /* lint */
 
--- old/usr/src/uts/i86pc/ml/fast_trap_asm.s	Thu Nov 14 19:00:14 2019
+++ new/usr/src/uts/i86pc/ml/fast_trap_asm.s	Thu Nov 14 19:00:14 2019
@@ -29,15 +29,6 @@
 #include <sys/regset.h>
 #include <sys/psw.h>
 
-#if defined(__lint)
-
-#include <sys/types.h>
-#include <sys/thread.h>
-#include <sys/systm.h>
-#include <sys/lgrp.h>
-
-#else   /* __lint */
-
 #include <sys/pcb.h>
 #include <sys/trap.h>
 #include <sys/ftrace.h>
@@ -48,42 +39,7 @@
 
 #include "assym.h"
 
-#endif	/* __lint */
 
-
-#if defined(__lint)
-
-hrtime_t
-get_hrtime(void)
-{ return (0); }
-
-hrtime_t
-get_hrestime(void)
-{
-	hrtime_t ts;
-
-	gethrestime((timespec_t *)&ts);
-	return (ts);
-}
-
-hrtime_t
-gethrvtime(void)
-{
-	klwp_t *lwp = ttolwp(curthread);
-	struct mstate *ms = &lwp->lwp_mstate;
-
-	return (gethrtime() - ms->ms_state_start + ms->ms_acct[LMS_USER]);
-}
-
-uint64_t
-getlgrp(void)
-{
-	return (((uint64_t)(curthread->t_lpl->lpl_lgrpid) << 32) |
-			curthread->t_cpu->cpu_id);
-}
-
-#else	/* __lint */
-
 /*
  * XX64: We are assuming that libc continues to expect the 64-bit value being
  * returned in %edx:%eax.  We further assume that it is safe to leave
@@ -95,8 +51,6 @@
  * assumptions are not true.
  */
 
-#if defined(__amd64)
-
 	.globl	gethrtimef
 	ENTRY_NP(get_hrtime)
 	FAST_INTR_PUSH
@@ -108,20 +62,6 @@
 	FAST_INTR_RETURN
 	SET_SIZE(get_hrtime)
 
-#elif defined(__i386)
-
-	.globl	gethrtimef
-	ENTRY_NP(get_hrtime)
-	FAST_INTR_PUSH
-	call	*gethrtimef
-	FAST_INTR_POP
-	FAST_INTR_RETURN
-	SET_SIZE(get_hrtime)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	.globl	gethrestimef
 	ENTRY_NP(get_hrestime)
 	FAST_INTR_PUSH
@@ -136,25 +76,6 @@
 	FAST_INTR_RETURN
 	SET_SIZE(get_hrestime)
 
-#elif defined(__i386)
-
-	.globl	gethrestimef
-	ENTRY_NP(get_hrestime)
-	FAST_INTR_PUSH
-	subl	$TIMESPEC_SIZE, %esp
-	pushl	%esp
-	call	*gethrestimef
-	movl	_CONST(4 + 0)(%esp), %eax
-	movl	_CONST(4 + CLONGSIZE)(%esp), %edx
-	addl	$_CONST(4 + TIMESPEC_SIZE), %esp
-	FAST_INTR_POP
-	FAST_INTR_RETURN
-	SET_SIZE(get_hrestime)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY_NP(gethrvtime)
 	FAST_INTR_PUSH
 	call	gethrtime_unscaled		/* get time since boot */
@@ -173,34 +94,6 @@
 	FAST_INTR_RETURN
 	SET_SIZE(gethrvtime)
 
-#elif defined(__i386)
-
-	ENTRY_NP(gethrvtime)
-	FAST_INTR_PUSH
-	call	gethrtime_unscaled		/* get time since boot */
-	movl	%gs:CPU_LWP, %ecx		/* current lwp */
-	subl	LWP_MS_STATE_START(%ecx), %eax	/* - ms->ms_state_start */
-	sbbl	LWP_MS_STATE_START+4(%ecx), %edx
-	addl	LWP_ACCT_USER(%ecx), %eax	/* add ms->ms_acct[LMS_USER] */
-	adcl	LWP_ACCT_USER+4(%ecx), %edx
-	subl	$0x8, %esp
-	leal	(%esp), %ecx
-	movl	%eax, (%ecx)
-	movl	%edx, 4(%ecx)
-	pushl	%ecx
-	call	scalehrtime
-	popl	%ecx
-	movl	(%ecx), %eax
-	movl	4(%ecx), %edx
-	addl	$0x8, %esp
-	FAST_INTR_POP
-	FAST_INTR_RETURN
-	SET_SIZE(gethrvtime)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY_NP(getlgrp)
 	FAST_INTR_PUSH
 	movq	%gs:CPU_THREAD, %rcx
@@ -211,18 +104,3 @@
 	FAST_INTR_RETURN
 	SET_SIZE(getlgrp)
 
-#elif defined(__i386)
-
-	ENTRY_NP(getlgrp)
-	FAST_INTR_PUSH
-	movl	%gs:CPU_THREAD, %ecx
-	movl	T_LPL(%ecx), %ecx
-	movl	LPL_LGRPID(%ecx), %edx
-	movl	%gs:CPU_ID, %eax
-	FAST_INTR_POP
-	FAST_INTR_RETURN
-	SET_SIZE(getlgrp)
-
-#endif	/* __i386 */
-
-#endif	/* __lint */
--- old/usr/src/uts/i86pc/ml/fb_swtch_src.s	Thu Nov 14 19:00:14 2019
+++ new/usr/src/uts/i86pc/ml/fb_swtch_src.s	Thu Nov 14 19:00:14 2019
@@ -26,12 +26,6 @@
  */
 
 
-#if defined(__lint)
-
-int fb_swtch_silence_lint = 0;
-
-#else
-
 #include <sys/asm_linkage.h>
 #include <sys/segments.h>
 #include <sys/controlregs.h>
@@ -96,7 +90,6 @@
 	/* Disable interrupts */
 	cli
 
-#if defined(__amd64)
 	/* Switch to a low memory stack */
 	movq	$_start, %rsp
 	addq	$FASTBOOT_STACK_OFFSET, %rsp
@@ -112,23 +105,6 @@
 	rep
 	  smovb
 
-#elif defined(__i386)
-	movl	0x4(%esp), %esi	/* address of fastboot info struct */
-
-	/* Switch to a low memory stack */
-	movl	$_start, %esp
-	addl	$FASTBOOT_STACK_OFFSET, %esp
-
-	/* Copy struct to stack */
-	movl	%esp, %edi	/* destination on the new stack */
-	movl	$FI_VALID, %ecx	/* size to copy */
-	rep
-	  smovb
-
-#endif
-
-#if defined(__amd64)
-
 	xorl	%eax, %eax
 	xorl	%edx, %edx
 
@@ -141,11 +117,9 @@
 	movl	$MSR_AMD_KGSBASE, %ecx
 	wrmsr
 
-#endif
 	/*
 	 * zero out all the registers to make sure they're 16 bit clean
 	 */
-#if defined(__amd64)
 	xorq	%r8, %r8
 	xorq	%r9, %r9
 	xorq	%r10, %r10
@@ -154,7 +128,6 @@
 	xorq	%r13, %r13
 	xorq	%r14, %r14
 	xorq	%r15, %r15
-#endif
 	xorl	%eax, %eax
 	xorl	%ebx, %ebx
 	xorl	%ecx, %ecx
@@ -161,18 +134,15 @@
 	xorl	%edx, %edx
 	xorl	%ebp, %ebp
 
-#if defined(__amd64)
 	/*
 	 * Load our own GDT
 	 */
 	lgdt	gdt_info
-#endif
 	/*
 	 * Load our own IDT
 	 */
 	lidt	idt_info
 
-#if defined(__amd64)
 	/*
 	 * Invalidate all TLB entries.
 	 * Load temporary pagetables to copy kernel and boot-archive
@@ -229,13 +199,10 @@
 	 * - turning off PCID in cr4
 	 * - disabling LME (long mode enable) in EFER (extended feature reg)
 	 */
-#endif
 	DISABLE_PAGING		/* clobbers %eax */
 
-#if defined(__amd64)
 	ljmp	$B32CODE_SEL, $1f
 1:
-#endif
 
 	/*
 	 * Clear PGE, PAE and PSE flags as dboot expects them to be
@@ -245,68 +212,11 @@
 	andl	$_BITNOT(CR4_PGE | CR4_PAE | CR4_PSE), %eax
 	movl	%eax, %cr4
 
-#if defined(__amd64)
 	movl	$MSR_AMD_EFER, %ecx	/* Extended Feature Enable */
 	rdmsr
 	btcl	$8, %eax		/* bit 8 Long Mode Enable bit */
 	wrmsr
 
-#elif defined(__i386)
-	/*
-	 * If fi_has_pae is set, re-enable paging with PAE.
-	 */
-	leal	FI_FILES(%esp), %ebx	/* offset to the files */
-	movl	FI_HAS_PAE(%esp), %edi	/* need to enable paging or not */
-	cmpl	$0, %edi
-	je	paging_on		/* no need to enable paging */
-
-	movl	FI_LAST_TABLE_PA(%esp), %esi	/* page table PA */
-
-	/*
-	 * Turn on PAE
-	 */
-	movl	%cr4, %eax
-	orl	$CR4_PAE, %eax
-	movl	%eax, %cr4
-
-	/*
-	 * Load top pagetable base address into cr3
-	 */
-	movl	FI_PAGETABLE_PA(%esp), %eax
-	movl	%eax, %cr3
-
-	movl	%cr0, %eax
-	orl	$_CONST(CR0_PG | CR0_WP | CR0_AM), %eax
-	andl	$_BITNOT(CR0_NW | CR0_CD), %eax
-	movl	%eax, %cr0
-	jmp	paging_on
-paging_on:
-
-	/* copy unix to final destination */
-	leal	_MUL(FASTBOOT_UNIX, FI_FILES_INCR)(%ebx), %edx
-	call	map_copy
-
-	/* copy boot archive to final destination */
-	leal	_MUL(FASTBOOT_BOOTARCHIVE, FI_FILES_INCR)(%ebx), %edx
-	call	map_copy
-
-	/* Disable paging one more time */
-	DISABLE_PAGING
-
-	/* Copy sections if there are any */ 
-	leal	_MUL(FASTBOOT_UNIX, FI_FILES_INCR)(%ebx), %edx
-	movl	FB_SECTCNT(%edx), %eax
-	cmpl	$0, %eax
-	je	1f
-	call	copy_sections
-1:
-
-	/* Whatever flags we turn on we need to turn off */
-	movl	%cr4, %eax
-	andl	$_BITNOT(CR4_PAE), %eax
-	movl	%eax, %cr4
-#endif	/* __i386 */
-
 dboot_jump:
 	/* Jump to dboot */
 	movl	$DBOOT_ENTRY_ADDRESS, %edi
@@ -314,8 +224,6 @@
 	movl	$MB_BOOTLOADER_MAGIC, %eax
 	jmp	*%edi
 
-#if defined(__amd64)
-
 	.code64
 	ENTRY_NP(copy_sections)
 	/*
@@ -361,89 +269,6 @@
 	ret
 	SET_SIZE(map_copy)	
 
-#elif defined(__i386)
-
-	ENTRY_NP(copy_sections)
-	/*
-	 * On entry
-	 *	%edx points to the fboot_file_t
-	 *	%eax contains the number of sections
-	 */
-	pushl	%ebp
-	pushl	%ebx
-	pushl	%esi
-	pushl	%edi
-
-	movl	%eax, %ebp
-
-	COPY_SECT(%edx, %ebx, %ebp)
-
-	popl	%edi
-	popl	%esi
-	popl	%ebx
-	popl	%ebp
-	ret
-	SET_SIZE(copy_sections)	
-
-	ENTRY_NP(map_copy)
-	/*
-	 * On entry
-	 *	%edx points to the fboot_file_t
-	 *	%edi has FB_HAS_PAE(%esp)
-	 *	%esi has FI_LAST_TABLE_PA(%esp)
-	 */
-	pushl	%eax
-	pushl	%ebx
-	pushl	%ecx
-	pushl	%edx
-	pushl	%ebp
-	pushl	%esi
-	pushl	%edi
-	movl	%esi, %ebp	/* Save page table PA in %ebp */
-
-	movl	FB_PTE_LIST_PA(%edx), %eax	/* PA list of the source */
-	movl	FB_DEST_PA(%edx), %ebx		/* PA of the destination */
-
-loop:
-	movl	(%eax), %esi			/* Are we done? */
-	cmpl	$FASTBOOT_TERMINATE, %esi
-	je	done
-
-	cmpl	$1, (%esp)			/* Is paging on? */
-	jne	no_paging			/* Nope */
-
-	movl	%ebp, %edi			/* Page table PA */
-	movl	%esi, (%edi)			/* Program low 32-bit */
-	movl	4(%eax), %esi			/* high bits of the table */
-	movl	%esi, 4(%edi)			/* Program high 32-bit */
-	movl	%cr3, %esi			/* Reload cr3 */
-	movl	%esi, %cr3
-	movl	FB_VA(%edx), %esi		/* Load from VA */
-	jmp	do_copy
-no_paging:
-	andl	$_BITNOT(MMU_PAGEOFFSET), %esi	/* clear lower 12-bit */
-do_copy:
-	movl	%ebx, %edi
-	movl	$PAGESIZE, %ecx
-	shrl	$2, %ecx	/* 4-byte at a time */
-	rep
-	  smovl
-	addl	$8, %eax /* We built the PTEs as 8-byte entries */
-	addl	$PAGESIZE, %ebx
-	jmp	loop
-done:
-	popl	%edi
-	popl	%esi
-	popl	%ebp
-	popl	%edx
-	popl	%ecx
-	popl	%ebx
-	popl	%eax
-	ret
-	SET_SIZE(map_copy)	
-#endif	/* __i386 */
-
-
 idt_info:
 	.value	0x3ff
 	.quad	0
@@ -452,4 +277,3 @@
  * We need to trampoline thru a gdt we have in low memory.
  */
 #include "../boot/boot_gdt.s"
-#endif /* __lint */
--- old/usr/src/uts/i86pc/ml/ia32.il	Thu Nov 14 19:00:15 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,178 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-/
-/ Inline functions specific to the i86pc kernel running on bare metal.
-/
-
-/
-/ return value of cr3 register
-/
-	.inline	getcr3,0
-	movl	%cr3, %eax
-	.end
-
-/
-/ reload cr3 register with its current value
-/
-	.inline	reload_cr3,0
-	movl	%cr3, %eax
-	movl	%eax, %cr3
-	.end
-
-/*
- * Put a new value into cr3 (page table base register
- *	void setcr3(void *value)
- */
-	.inline	setcr3,4
-	movl	(%esp), %eax
-	movl	%eax, %cr3
-	.end
-
-/
-/ enable interrupts
-/
-	.inline	sti,0
-	sti
-	.end
-
-/
-/ disable interrupts
-/
-	.inline cli,0
-	cli
-	.end
-
-/
-/ disable interrupts and return value describing if interrupts were enabled
-/
-	.inline	clear_int_flag,0
-	pushfl
-	cli
-	popl	%eax
-	.end
-
-	.inline	intr_clear,0
-	pushfl
-	cli
-	popl	%eax
-	.end
-
-/
-/ return the flags register
-/
-	.inline getflags,0
-	pushfl
-	popl	%eax
-	.end
-
-/
-/ restore interrupt enable flag to value returned from 'clear_int_flag' above
-/
-	.inline restore_int_flag,4
-	testl	$0x200, (%esp)
-	jz	1f
-	sti
-1:
-	.end
-
-	.inline intr_restore,4
-	testl	$0x200, (%esp)
-	jz	1f
-	sti
-1:
-	.end
-
-/
-/ in and out
-/
-	.inline	inb,4
-	movl	(%esp), %edx
-	xorl    %eax, %eax
-	inb	(%dx)
-	.end
-
-	.inline	inw,4
-	movl	(%esp), %edx
-	xorl    %eax, %eax
-	inw	(%dx)
-	.end
-
-	.inline	inl,4
-	movl	(%esp), %edx
-	xorl    %eax, %eax
-	inl	(%dx)
-	.end
-
-	.inline	outb,8
-	movl	(%esp), %edx
-	movl    4(%esp), %eax
-	outb	(%dx)
-	.end
-
-	.inline	outw,8
-	movl	(%esp), %edx
-	movl    4(%esp), %eax
-	outw	(%dx)
-	.end
-
-	.inline	outl,8
-	movl	(%esp), %edx
-	movl    4(%esp), %eax
-	outl	(%dx)
-	.end
-
-/*
- * Invalidate TLB translation to 1 page.
- *	void mmu_tlbflush_entry(void *addr)
- */
-	.inline	mmu_tlbflush_entry,4
-	movl	(%esp), %eax
-	invlpg	(%eax)
-	.end
-
-/*
- * Call the halt instruction. This will put the CPU to sleep until
- * it is again awoken via an interrupt.
- * This function should be called with interrupts already disabled
- * for the CPU.
- * Note that "sti" will only enable interrupts at the end of the
- * subsequent instruction...in this case: "hlt".
- */
-	.inline i86_halt,0
-	sti
-	hlt
-	.end
-
-/*
- * execute the bsrw instruction
- *	int bsrw_insn(uint16_t)
- */
-	.inline	bsrw_insn,4
-	xorl	%eax, %eax
-	movw	(%esp), %cx
-	bsrw	%cx, %ax
-	.end
--- old/usr/src/uts/i86pc/ml/interrupt.s	Thu Nov 14 19:00:15 2019
+++ new/usr/src/uts/i86pc/ml/interrupt.s	Thu Nov 14 19:00:15 2019
@@ -36,14 +36,6 @@
 #include <sys/psw.h>
 #include <sys/x86_archext.h>
 
-#if defined(__lint)
-
-#include <sys/types.h>
-#include <sys/thread.h>
-#include <sys/systm.h>
-
-#else   /* __lint */
-
 #include <sys/segments.h>
 #include <sys/pcb.h>
 #include <sys/trap.h>
@@ -53,18 +45,6 @@
 #include <sys/panic.h>
 #include "assym.h"
 
-#endif	/* lint */
-
-#if defined(__lint)
-
-void
-_interrupt(void)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	/*
 	 * Common register usage:
 	 *
@@ -109,38 +89,6 @@
 	SET_SIZE(cmnint)
 	SET_SIZE(_interrupt)
 
-#elif defined(__i386)
-
-	ENTRY_NP2(cmnint, _interrupt)
-
-	INTR_PUSH
-	INTGATE_INIT_KERNEL_FLAGS
-
-	/*
-	 * At the end of TRACE_PTR %esi points to the current TRAPTRACE entry
-	 */
-	TRACE_PTR(%esi, %eax, %eax, %edx, $TT_INTERRUPT)
-						/* Uses labels 8 and 9 */
-	TRACE_REGS(%esi, %esp, %eax, %ebx)	/* Uses label 9 */
-	TRACE_STAMP(%esi)		/* Clobbers %eax, %edx, uses 9 */
-
-	movl	%esp, %ebp
-
-	TRACE_STACK(%esi)
-
-	pushl	%esi			/* pass traptrace record pointer */
-	pushl	%ebp			/* pass struct regs pointer */
-	call	*do_interrupt_common	/* interrupt service routine */
-	addl	$8, %esp		/* pop args off of stack */
-
-	jmp	_sys_rtt_ints_disabled
-	/*NOTREACHED*/
-
-	SET_SIZE(cmnint)
-	SET_SIZE(_interrupt)
-
-#endif	/* __i386 */
-
 /*
  * Declare a uintptr_t which has the size of _interrupt to enable stack
  * traceback code to know when a regs structure is on the stack.
@@ -151,33 +99,20 @@
 	.NWORD	. - _interrupt
 	.type	_interrupt_size, @object
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-void
-fakesoftint(void)
-{}
-
-#else	/* __lint */
-
-	/
-	/ If we're here, we're being called from splx() to fake a soft
-	/ interrupt (note that interrupts are still disabled from splx()).
-	/ We execute this code when a soft interrupt is posted at
-	/ level higher than the CPU's current spl; when spl is lowered in
-	/ splx(), it will see the softint and jump here.  We'll do exactly
-	/ what a trap would do:  push our flags, %cs, %eip, error code
-	/ and trap number (T_SOFTINT).  The cmnint() code will see T_SOFTINT
-	/ and branch to the dosoftint() code.
-	/
-#if defined(__amd64)
-
 	/*
-	 * In 64-bit mode, iretq -always- pops all five regs
-	 * Imitate the 16-byte auto-align of the stack, and the
-	 * zero-ed out %ss value.
+	 * If we're here, we're being called from splx() to fake a soft
+	 * interrupt (note that interrupts are still disabled from
+	 * splx()).  We execute this code when a soft interrupt is
+	 * posted at level higher than the CPU's current spl; when spl
+	 * is lowered in splx(), it will see the softint and jump here.
+	 * We'll do exactly what a trap would do:  push our flags, %cs,
+	 * %rip, error code and trap number (T_SOFTINT).  The cmnint()
+	 * code will see T_SOFTINT and branch to the dosoftint() code.
+	 *
+	 * iretq -always- pops all five regs. Imitate the 16-byte
+	 * auto-align of the stack, and the zero-ed out %ss value.
 	 */
+
 	ENTRY_NP(fakesoftint)
 	movq	%rsp, %r11
 	andq	$-16, %rsp
@@ -200,24 +135,3 @@
 	SET_SIZE(fakesoftint_return)
 	SET_SIZE(fakesoftint)
 
-#elif defined(__i386)
-
-	ENTRY_NP(fakesoftint)
-	pushfl
-#if defined(__xpv)
-	popl	%eax
-	EVENT_MASK_TO_IE(%edx, %eax)
-	pushl	%eax
-#endif
-	pushl	%cs
-	pushl	$fakesoftint_return
-	pushl	$0
-	pushl	$T_SOFTINT
-	jmp	cmnint
-	ALTENTRY(fakesoftint_return)
-	ret
-	SET_SIZE(fakesoftint_return)
-	SET_SIZE(fakesoftint)
-
-#endif	/* __i386 */
-#endif	/* __lint */
--- old/usr/src/uts/i86pc/ml/kpti_trampolines.s	Thu Nov 14 19:00:15 2019
+++ new/usr/src/uts/i86pc/ml/kpti_trampolines.s	Thu Nov 14 19:00:15 2019
@@ -110,14 +110,6 @@
 #include <sys/machbrand.h>
 #include <sys/param.h>
 
-#if defined(__lint)
-
-#include <sys/types.h>
-#include <sys/thread.h>
-#include <sys/systm.h>
-
-#else	/* __lint */
-
 #include <sys/segments.h>
 #include <sys/pcb.h>
 #include <sys/trap.h>
@@ -818,4 +810,3 @@
 kpti_tramp_end:
 	nop
 
-#endif	/* __lint */
--- old/usr/src/uts/i86pc/ml/locore.s	Thu Nov 14 19:00:15 2019
+++ new/usr/src/uts/i86pc/ml/locore.s	Thu Nov 14 19:00:15 2019
@@ -43,19 +43,6 @@
 #include <sys/x86_archext.h>
 #include <sys/machparam.h>
 
-#if defined(__lint)
-
-#include <sys/types.h>
-#include <sys/thread.h>
-#include <sys/systm.h>
-#include <sys/lgrp.h>
-#include <sys/regset.h>
-#include <sys/link.h>
-#include <sys/bootconf.h>
-#include <sys/bootsvcs.h>
-
-#else	/* __lint */
-
 #include <sys/segments.h>
 #include <sys/pcb.h>
 #include <sys/trap.h>
@@ -133,20 +120,7 @@
 	.comm	t0stack, DEFAULTSTKSZ, 32
 	.comm	t0, 4094, 32
 
-#endif	/* __lint */
 
-
-#if defined(__amd64)
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-_locore_start(struct boot_syscalls *sysp, ulong_t rsi, struct bootops *bop)
-{}
-
-#else	/* __lint */
-
 	/*
 	 * kobj_init() vectors us back to here with (note) a slightly different
 	 * set of arguments than _start is given (see lint prototypes above).
@@ -229,11 +203,6 @@
 	call	panic
 	SET_SIZE(_locore_start)
 
-#endif	/* __amd64 */
-#endif	/* __lint */
-
-#if !defined(__lint)
-
 __return_from_main:
 	.string	"main() returned"
 __unsupported_cpu:
@@ -244,862 +213,14 @@
 	.string	"locore.s:%d lwp_rtt(lwp %p) but pcb_rupdate != 1"
 #endif
 
-#endif	/* !__lint */
-
-#if !defined(__amd64)
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-_locore_start(struct boot_syscalls *sysp, struct bootops *bop)
-{}
-
-#else	/* __lint */
-
-	/*
-	 * kobj_init() vectors us back to here with (note) a slightly different
-	 * set of arguments than _start is given (see lint prototypes above).
-	 *
-	 * XXX	Make this less vile, please.
-	 */
-	ENTRY_NP(_locore_start)
-
-	/*
-	 *	%ecx = boot services (should die someday)
-	 *	%ebx = bootops
-	 */
-	mov	$edata, %ebp		/ edata needs to be defined for ksyms
-	movl	$0, (%ebp)		/ limit stack back trace
-
-	/*
-	 * Initialize our stack pointer to the thread 0 stack (t0stack)
-	 * and leave room for a phony "struct regs".
-	 */
-	movl	$t0stack + DEFAULTSTKSZ - REGSIZE, %esp
-
-	/*
-	 * Save call back for special x86 boot services vector
-	 */
-	mov	%ecx, sysp		/ save call back for boot services
-
-	mov	%ebx, bootops		/ save bootops
-	movl	$bootops, bootopsp
-
-
-	/*
-	 * Save all registers and flags
-	 */
-	pushal
-	pushfl
-
-#if !defined(__xpv)
-	/*
-	 * Override bios settings and enable write protect and
-	 * alignment check faults.
-	 */
-	movl	%cr0, %eax
-
-	/*
-	 * enable WP for detecting faults, and enable alignment checking.
-	 */
-	orl	$_CONST(CR0_WP|CR0_AM), %eax
-	andl	$_BITNOT(CR0_WT|CR0_CE), %eax
-	movl	%eax, %cr0		/ set the cr0 register correctly and
-					/ override the BIOS setup
-
-	/*
-	 * If bit 21 of eflags can be flipped, then cpuid is present
-	 * and enabled.
-	 */
-	pushfl
-	popl	%ecx
-	movl	%ecx, %eax
-	xorl	$PS_ID, %eax		/ try complemented bit
-	pushl	%eax
-	popfl
-	pushfl
-	popl    %eax
-	cmpl	%eax, %ecx
-	jne	have_cpuid
-
-	/*
-	 * cpuid may be disabled on Cyrix, try to detect Cyrix by the 5/2 test
-	 * div does not modify the cc flags on Cyrix, even though this may
-	 * also be true for other vendors, this is generally true only for
-	 * newer models from those vendors that support and do not disable
-	 * cpuid (usually because cpuid cannot be disabled)
-	 */
-
-	/*
-	 * clear cc flags
-	 */
-	xorb	%ah, %ah
-	sahf
-
-	/*
-	 * perform 5/2 test
-	 */
-	movw	$5, %ax
-	movb	$2, %bl
-	divb	%bl
-
-	lahf
-	cmpb	$2, %ah
-	jne	cpu_486
-
-	/*
-	 * div did not modify the cc flags, chances are the vendor is Cyrix
-	 * assume the vendor is Cyrix and use the CCR's to enable cpuid
-	 */
-	.set	CYRIX_CRI, 0x22		/ CR Index Register
-	.set	CYRIX_CRD, 0x23		/ CR Data Register
-
-	.set	CYRIX_CCR3, 0xc3	/ Config Control Reg 3
-	.set	CYRIX_CCR4, 0xe8	/ Config Control Reg 4
-	.set	CYRIX_DIR0, 0xfe	/ Device Identification Reg 0
-	.set	CYRIX_DIR1, 0xff	/ Device Identification Reg 1
-
-	/*
-	 * even if the cpu vendor is Cyrix and the motherboard/chipset
-	 * vendor decided to ignore lines A1-A4 for I/O addresses, I/O port
-	 * 0x21 corresponds with 0x23 and since 0x22 is still untouched,
-	 * the reads and writes of 0x21 are guaranteed to be off-chip of
-	 * the cpu
-	 */
-
-	/*
-	 * enable read of ISR at I/O port 0x20
-	 */
-	movb	$0xb, %al
-	outb	$MCMD_PORT
-
-	/*
-	 * read IMR and store in %bl
-	 */
-	inb	$MIMR_PORT
-	movb	%al, %bl
-
-	/*
-	 * mask out all interrupts so that ISR will not change
-	 */
-	movb	$0xff, %al
-	outb	$MIMR_PORT
-
-	/*
-	 * reads of I/O port 0x22 on Cyrix are always directed off-chip
-	 * make use of I/O pull-up to test for an unknown device on 0x22
-	 */
-	inb	$CYRIX_CRI
-	cmpb	$0xff, %al
-	je	port_22_free
-
-	/*
-	 * motherboard/chipset vendor may be ignoring line A1 of I/O address
-	 */
-	movb	%al, %cl
-
-	/*
-	 * if the ISR and the value read from 0x22 do not match then we have
-	 * detected some unknown device, probably a chipset, at 0x22
-	 */
-	inb	$MCMD_PORT
-	cmpb	%al, %cl
-	jne	restore_IMR
-
-port_22_free:
-	/*
-	 * now test to see if some unknown device is using I/O port 0x23
-	 *
-	 * read the external I/O port at 0x23
-	 */
-	inb	$CYRIX_CRD
-
-	/*
-	 * Test for pull-up at 0x23 or if I/O address line A1 is being ignored.
-	 * IMR is 0xff so both tests are performed simultaneously.
-	 */
-	cmpb	$0xff, %al
-	jne	restore_IMR
-
-	/*
-	 * We are a Cyrix part. In case we are some model of Cx486 or a Cx586,
-	 * record the type and fix it later if not.
-	 */
-	movl	$X86_VENDOR_Cyrix, x86_vendor
-	movl	$X86_TYPE_CYRIX_486, x86_type
-
-	/*
-	 * Try to read CCR3. All Cyrix cpu's which support cpuid have CCR3.
-	 *
-	 * load CCR3 index into CCR index register
-	 */
-
-	movb	$CYRIX_CCR3, %al
-	outb	$CYRIX_CRI
-
-	/*
-	 * If we are not a Cyrix cpu, then we have performed an external I/O
-	 * cycle. If the CCR index was not valid for this Cyrix model, we may
-	 * have performed an external I/O cycle as well. In these cases and
-	 * if the motherboard/chipset vendor ignores I/O address line A1,
-	 * then the PIC will have IRQ3 set at the lowest priority as a side
-	 * effect of the above outb. We are reasonalbly confident that there
-	 * is not an unknown device on I/O port 0x22, so there should have been
-	 * no unpredictable side-effect of the above outb.
-	 */
-
-	/*
-	 * read CCR3
-	 */
-	inb	$CYRIX_CRD
-
-	/*
-	 * If we are not a Cyrix cpu the inb above produced an external I/O
-	 * cycle. If we are a Cyrix model that does not support CCR3 wex
-	 * produced an external I/O cycle. In all known Cyrix models 6x86 and
-	 * above, bit 3 of CCR3 is reserved and cannot be set to 1. In all
-	 * Cyrix models prior to the 6x86 that supported CCR3, bits 4-7 are
-	 * reserved as well. It is highly unlikely that CCR3 contains the value
-	 * 0xff. We test to see if I/O port 0x23 is pull-up or the IMR and
-	 * deduce we are not a Cyrix with support for cpuid if so.
-	 */
-	cmpb	$0xff, %al
-	je	restore_PIC
-
-	/*
-	 * There exist 486 ISA Cyrix chips that support CCR3 but do not support
-	 * DIR0 and DIR1. If we try to read DIR0, we may generate external I/O
-	 * cycles, the exact behavior is model specific and undocumented.
-	 * Unfortunately these external I/O cycles may confuse some PIC's beyond
-	 * recovery. Fortunatetly we can use the following undocumented trick:
-	 * if bit 4 of CCR3 can be toggled, then DIR0 and DIR1 are supported.
-	 * Pleasantly MAPEN contains bit 4 of CCR3, so this trick is guaranteed
-	 * to work on all Cyrix cpu's which support cpuid.
-	 */
-	movb	%al, %dl
-	xorb	$0x10, %dl
-	movb	%al, %cl
-
-	/*
-	 * write back CRR3 with toggled bit 4 to CCR3
-	 */
-	movb	$CYRIX_CCR3, %al
-	outb	$CYRIX_CRI
-
-	movb	%dl, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * read CCR3
-	 */
-	movb	$CYRIX_CCR3, %al
-	outb	$CYRIX_CRI
-	inb	$CYRIX_CRD
-	movb	%al, %dl
-
-	/*
-	 * restore CCR3
-	 */
-	movb	$CYRIX_CCR3, %al
-	outb	$CYRIX_CRI
-
-	movb	%cl, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * if bit 4 was not toggled DIR0 and DIR1 are not supported in which
-	 * case we do not have cpuid anyway
-	 */
-	andb	$0x10, %al
-	andb	$0x10, %dl
-	cmpb	%al, %dl
-	je	restore_PIC
-
-	/*
-	 * read DIR0
-	 */
-	movb	$CYRIX_DIR0, %al
-	outb	$CYRIX_CRI
-	inb	$CYRIX_CRD
-
-	/*
-	 * test for pull-up
-	 */
-	cmpb	$0xff, %al
-	je	restore_PIC
-
-	/*
-	 * Values of 0x20-0x27 in DIR0 are currently reserved by Cyrix for
-	 * future use. If Cyrix ever produces a cpu that supports cpuid with
-	 * these ids, the following test will have to change. For now we remain
-	 * pessimistic since the formats of the CRR's may be different then.
-	 *
-	 * test for at least a 6x86, to see if we support both MAPEN and CPUID
-	 */
-	cmpb	$0x30, %al
-	jb	restore_IMR
-
-	/*
-	 * enable MAPEN
-	 */
-	movb	$CYRIX_CCR3, %al
-	outb	$CYRIX_CRI
-
-	andb	$0xf, %cl
-	movb	%cl, %al
-	orb	$0x10, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * select CCR4
-	 */
-	movb	$CYRIX_CCR4, %al
-	outb	$CYRIX_CRI
-
-	/*
-	 * read CCR4
-	 */
-	inb	$CYRIX_CRD
-
-	/*
-	 * enable cpuid
-	 */
-	orb	$0x80, %al
-	movb	%al, %dl
-
-	/*
-	 * select CCR4
-	 */
-	movb	$CYRIX_CCR4, %al
-	outb	$CYRIX_CRI
-
-	/*
-	 * write CCR4
-	 */
-	movb	%dl, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * select CCR3
-	 */
-	movb	$CYRIX_CCR3, %al
-	outb	$CYRIX_CRI
-
-	/*
-	 * disable MAPEN and write CCR3
-	 */
-	movb	%cl, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * restore IMR
-	 */
-	movb	%bl, %al
-	outb	$MIMR_PORT
-
-	/*
-	 * test to see if cpuid available
-	 */
-	pushfl
-	popl	%ecx
-	movl	%ecx, %eax
-	xorl	$PS_ID, %eax		/ try complemented bit
-	pushl	%eax
-	popfl
-	pushfl
-	popl    %eax
-	cmpl	%eax, %ecx
-	jne	have_cpuid
-	jmp	cpu_486
-
-restore_PIC:
-	/*
-	 * In case the motherboard/chipset vendor is ignoring line A1 of the
-	 * I/O address, we set the PIC priorities to sane values.
-	 */
-	movb	$0xc7, %al	/ irq 7 lowest priority
-	outb	$MCMD_PORT
-
-restore_IMR:
-	movb	%bl, %al
-	outb	$MIMR_PORT
-	jmp	cpu_486
-
-have_cpuid:
-	/*
-	 * cpuid instruction present
-	 */
-	bts	$X86FSET_CPUID, x86_featureset	/ Just to set; Ignore the CF
-	movl	$0, %eax
-	cpuid
-
-	movl	%ebx, cpu_vendor
-	movl	%edx, cpu_vendor+4
-	movl	%ecx, cpu_vendor+8
-
-	/*
-	 * early cyrix cpus are somewhat strange and need to be
-	 * probed in curious ways to determine their identity
-	 */
-
-	leal	cpu_vendor, %esi
-	leal	CyrixInstead, %edi
-	movl	$12, %ecx
-	repz
-	  cmpsb
-	je	vendor_is_cyrix
-
-	/ let mlsetup()/cpuid_pass1() handle everything else in C
-
-	jmp	cpu_done
-
-is486:
-	/*
-	 * test to see if a useful cpuid
-	 */
-	testl	%eax, %eax
-	jz	isa486
-
-	movl	$1, %eax
-	cpuid
-
-	movl	%eax, %ebx
-	andl	$0xF00, %ebx
-	cmpl	$0x400, %ebx
-	je	isa486
-
-	rep;	ret	/* use 2 byte return instruction */
-			/* AMD Software Optimization Guide - Section 6.2 */
-isa486:
-	/*
-	 * lose the return address
-	 */
-	popl	%eax
-	jmp	cpu_486
-
-vendor_is_cyrix:
-	call	is486
-
-	/*
-	 * Processor signature and feature flags for Cyrix are insane.
-	 * BIOS can play with semi-documented registers, so cpuid must be used
-	 * cautiously. Since we are Cyrix that has cpuid, we have DIR0 and DIR1
-	 * Keep the family in %ebx and feature flags in %edx until not needed
-	 */
-
-	/*
-	 * read DIR0
-	 */
-	movb	$CYRIX_DIR0, %al
-	outb	$CYRIX_CRI
-	inb	$CYRIX_CRD
-
-	/*
-	 * First we handle the cases where we are a 6x86 or 6x86L.
-	 * The 6x86 is basically a 486, the only reliable bit in the
-	 * feature flags is for FPU. The 6x86L is better, unfortunately
-	 * there is no really good way to distinguish between these two
-	 * cpu's. We are pessimistic and when in doubt assume 6x86.
-	 */
-
-	cmpb	$0x40, %al
-	jae	maybeGX
-
-	/*
-	 * We are an M1, either a 6x86 or 6x86L.
-	 */
-	cmpb	$0x30, %al
-	je	maybe6x86L
-	cmpb	$0x31, %al
-	je	maybe6x86L
-	cmpb	$0x34, %al
-	je	maybe6x86L
-	cmpb	$0x35, %al
-	je	maybe6x86L
-
-	/*
-	 * although it is possible that we are a 6x86L, the cpu and
-	 * documentation are so buggy, we just do not care.
-	 */
-	jmp	likely6x86
-
-maybe6x86L:
-	/*
-	 *  read DIR1
-	 */
-	movb	$CYRIX_DIR1, %al
-	outb	$CYRIX_CRI
-	inb	$CYRIX_CRD
-	cmpb	$0x22, %al
-	jb	likely6x86
-
-	/*
-	 * We are a 6x86L, or at least a 6x86 with honest cpuid feature flags
-	 */
-	movl	$X86_TYPE_CYRIX_6x86L, x86_type
-	jmp	coma_bug
-
-likely6x86:
-	/*
-	 * We are likely a 6x86, or a 6x86L without a way of knowing
-	 *
-	 * The 6x86 has NO Pentium or Pentium Pro compatible features even
-	 * though it claims to be a Pentium Pro compatible!
-	 *
-	 * The 6x86 core used in the 6x86 may have most of the Pentium system
-	 * registers and largely conform to the Pentium System Programming
-	 * Reference. Documentation on these parts is long gone. Treat it as
-	 * a crippled Pentium and hope for the best.
-	 */
-
-	movl	$X86_TYPE_CYRIX_6x86, x86_type
-	jmp	coma_bug
-
-maybeGX:
-	/*
-	 * Now we check whether we are a MediaGX or GXm. We have particular
-	 * reason for concern here. Even though most of the GXm's
-	 * report having TSC in the cpuid feature flags, the TSC may be
-	 * horribly broken. What is worse, is that MediaGX's are basically
-	 * 486's while the good GXm's are more like Pentium Pro's!
-	 */
-
-	cmpb	$0x50, %al
-	jae	maybeM2
-
-	/*
-	 * We are either a MediaGX (sometimes called a Gx86) or GXm
-	 */
-
-	cmpb	$41, %al
-	je	maybeMediaGX
-
-	cmpb	$44, %al
-	jb	maybeGXm
-
-	cmpb	$47, %al
-	jbe	maybeMediaGX
-
-	/*
-	 * We do not honestly know what we are, so assume a MediaGX
-	 */
-	jmp	media_gx
-
-maybeGXm:
-	/*
-	 * It is still possible we are either a MediaGX or GXm, trust cpuid
-	 * family should be 5 on a GXm
-	 */
-	cmpl	$0x500, %ebx
-	je	GXm
-
-	/*
-	 * BIOS/Cyrix might set family to 6 on a GXm
-	 */
-	cmpl	$0x600, %ebx
-	jne	media_gx
-
-GXm:
-	movl	$X86_TYPE_CYRIX_GXm, x86_type
-	jmp	cpu_done
-
-maybeMediaGX:
-	/*
-	 * read DIR1
-	 */
-	movb	$CYRIX_DIR1, %al
-	outb	$CYRIX_CRI
-	inb	$CYRIX_CRD
-
-	cmpb	$0x30, %al
-	jae	maybeGXm
-
-	/*
-	 * we are a MediaGX for which we do not trust cpuid
-	 */
-media_gx:
-	movl	$X86_TYPE_CYRIX_MediaGX, x86_type
-	jmp	cpu_486
-
-maybeM2:
-	/*
-	 * Now we check whether we are a 6x86MX or MII. These cpu's are
-	 * virtually identical, but we care because for the 6x86MX, we
-	 * must work around the coma bug. Also for 6x86MX prior to revision
-	 * 1.4, the TSC may have serious bugs.
-	 */
-
-	cmpb	$0x60, %al
-	jae	maybeM3
-
-	/*
-	 * family should be 6, but BIOS/Cyrix might set it to 5
-	 */
-	cmpl	$0x600, %ebx
-	ja	cpu_486
-
-	/*
-	 *  read DIR1
-	 */
-	movb	$CYRIX_DIR1, %al
-	outb	$CYRIX_CRI
-	inb	$CYRIX_CRD
-
-	cmpb	$0x8, %al
-	jb	cyrix6x86MX
-	cmpb	$0x80, %al
-	jb	MII
-
-cyrix6x86MX:
-	/*
-	 * It is altogether unclear how the revision stamped on the cpu
-	 * maps to the values in DIR0 and DIR1. Just assume TSC is broken.
-	 */
-	movl	$X86_TYPE_CYRIX_6x86MX, x86_type
-	jmp	coma_bug
-
-MII:
-	movl	$X86_TYPE_CYRIX_MII, x86_type
-likeMII:
-	jmp	cpu_done
-
-maybeM3:
-	/*
-	 * We are some chip that we cannot identify yet, an MIII perhaps.
-	 * We will be optimistic and hope that the chip is much like an MII,
-	 * and that cpuid is sane. Cyrix seemed to have gotten it right in
-	 * time for the MII, we can only hope it stayed that way.
-	 * Maybe the BIOS or Cyrix is trying to hint at something
-	 */
-	cmpl	$0x500, %ebx
-	je	GXm
-
-	cmpb	$0x80, %al
-	jae	likelyM3
-
-	/*
-	 * Just test for the features Cyrix is known for
-	 */
-
-	jmp	MII
-
-likelyM3:
-	/*
-	 * DIR0 with values from 0x80 to 0x8f indicates a VIA Cyrix III, aka
-	 * the Cyrix MIII. There may be parts later that use the same ranges
-	 * for DIR0 with special values in DIR1, maybe the VIA CIII, but for
-	 * now we will call anything with a DIR0 of 0x80 or higher an MIII.
-	 * The MIII is supposed to support large pages, but we will believe
-	 * it when we see it. For now we just enable and test for MII features.
-	 */
-	movl	$X86_TYPE_VIA_CYRIX_III, x86_type
-	jmp	likeMII
-
-coma_bug:
-
 /*
- * With NO_LOCK set to 0 in CCR1, the usual state that BIOS enforces, some
- * bus cycles are issued with LOCK# asserted. With NO_LOCK set to 1, all bus
- * cycles except page table accesses and interrupt ACK cycles do not assert
- * LOCK#. xchgl is an instruction that asserts LOCK# if NO_LOCK is set to 0.
- * Due to a bug in the cpu core involving over-optimization of branch
- * prediction, register renaming, and execution of instructions down both the
- * X and Y pipes for the xchgl instruction, short loops can be written that
- * never de-assert LOCK# from one invocation of the loop to the next, ad
- * infinitum. The undesirable effect of this situation is that interrupts are
- * not serviced. The ideal workaround to this bug would be to set NO_LOCK to
- * 1. Unfortunately bus cycles that would otherwise have asserted LOCK# no
- * longer do, unless they are page table accesses or interrupt ACK cycles.
- * With LOCK# not asserted, these bus cycles are now cached. This can cause
- * undesirable behaviour if the ARR's are not configured correctly. Solaris
- * does not configure the ARR's, nor does it provide any useful mechanism for
- * doing so, thus the ideal workaround is not viable. Fortunately, the only
- * known exploits for this bug involve the xchgl instruction specifically.
- * There is a group of undocumented registers on Cyrix 6x86, 6x86L, and
- * 6x86MX cpu's which can be used to specify one instruction as a serializing
- * instruction. With the xchgl instruction serialized, LOCK# is still
- * asserted, but it is the sole instruction for which LOCK# is asserted.
- * There is now some added penalty for the xchgl instruction, but the usual
- * bus locking is preserved. This ingenious workaround was discovered by
- * disassembling a binary provided by Cyrix as a workaround for this bug on
- * Windows, but its not documented anywhere by Cyrix, nor is the bug actually
- * mentioned in any public errata! The only concern for this workaround is
- * that there may be similar undiscovered bugs with other instructions that
- * assert LOCK# that may be leveraged to similar ends. The fact that Cyrix
- * fixed this bug sometime late in 1997 and no other exploits other than
- * xchgl have been discovered is good indication that this workaround is
- * reasonable.
- */
-
-	.set	CYRIX_DBR0, 0x30	/ Debug Register 0
-	.set	CYRIX_DBR1, 0x31	/ Debug Register 1
-	.set	CYRIX_DBR2, 0x32	/ Debug Register 2
-	.set	CYRIX_DBR3, 0x33	/ Debug Register 3
-	.set	CYRIX_DOR, 0x3c		/ Debug Opcode Register
-
-	/*
-	 * What is known about DBR1, DBR2, DBR3, and DOR is that for normal
-	 * cpu execution DBR1, DBR2, and DBR3 are set to 0. To obtain opcode
-	 * serialization, DBR1, DBR2, and DBR3 are loaded with 0xb8, 0x7f,
-	 * and 0xff. Then, DOR is loaded with the one byte opcode.
-	 */
-
-	/*
-	 * select CCR3
-	 */
-	movb	$CYRIX_CCR3, %al
-	outb	$CYRIX_CRI
-
-	/*
-	 * read CCR3 and mask out MAPEN
-	 */
-	inb	$CYRIX_CRD
-	andb	$0xf, %al
-
-	/*
-	 * save masked CCR3 in %ah
-	 */
-	movb	%al, %ah
-
-	/*
-	 * select CCR3
-	 */
-	movb	$CYRIX_CCR3, %al
-	outb	$CYRIX_CRI
-
-	/*
-	 * enable MAPEN
-	 */
-	movb	%ah, %al
-	orb	$0x10, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * read DBR0
-	 */
-	movb	$CYRIX_DBR0, %al
-	outb	$CYRIX_CRI
-	inb	$CYRIX_CRD
-
-	/*
-	 * disable MATCH and save in %bh
-	 */
-	orb	$0x80, %al
-	movb	%al, %bh
-
-	/*
-	 * write DBR0
-	 */
-	movb	$CYRIX_DBR0, %al
-	outb	$CYRIX_CRI
-	movb	%bh, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * write DBR1
-	 */
-	movb	$CYRIX_DBR1, %al
-	outb	$CYRIX_CRI
-	movb	$0xf8, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * write DBR2
-	 */
-	movb	$CYRIX_DBR2, %al
-	outb	$CYRIX_CRI
-	movb	$0x7f, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * write DBR3
-	 */
-	movb	$CYRIX_DBR3, %al
-	outb	$CYRIX_CRI
-	xorb	%al, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * write DOR
-	 */
-	movb	$CYRIX_DOR, %al
-	outb	$CYRIX_CRI
-	movb	$0x87, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * enable MATCH
-	 */
-	movb	$CYRIX_DBR0, %al
-	outb	$CYRIX_CRI
-	movb	%bh, %al
-	andb	$0x7f, %al
-	outb	$CYRIX_CRD
-
-	/*
-	 * disable MAPEN
-	 */
-	movb	$0xc3, %al
-	outb	$CYRIX_CRI
-	movb	%ah, %al
-	outb	$CYRIX_CRD
-
-	jmp	cpu_done
-
-cpu_done:
-
-	popfl					/* Restore original FLAGS */
-	popal					/* Restore all registers */
-
-#endif	/* !__xpv */
-
-	/*
-	 *  mlsetup(%esp) gets called.
-	 */
-	pushl	%esp
-	call	mlsetup
-	addl	$4, %esp
-
-	/*
-	 * We change our appearance to look like the real thread 0.
-	 * (NOTE: making ourselves to be a real thread may be a noop)
-	 * main() gets called.  (NOTE: main() never returns).
-	 */
-	call	main
-	/* NOTREACHED */
-	pushl	$__return_from_main
-	call	panic
-
-	/* NOTREACHED */
-cpu_486:
-	pushl	$__unsupported_cpu
-	call	panic
-	SET_SIZE(_locore_start)
-
-#endif	/* __lint */
-#endif	/* !__amd64 */
-
-
-/*
  *  For stack layout, see privregs.h
  *  When cmntrap gets called, the error code and trap number have been pushed.
  *  When cmntrap_pushed gets called, the entire struct regs has been pushed.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-cmntrap()
-{}
-
-#else	/* __lint */
-
 	.globl	trap		/* C handler called below */
 
-#if defined(__amd64)
-
 	ENTRY_NP2(cmntrap, _cmntrap)
 
 	INTR_PUSH
@@ -1206,111 +327,6 @@
 	SET_SIZE(cmntrap)
 	SET_SIZE(_cmntrap)
 
-#elif defined(__i386)
-
-
-	ENTRY_NP2(cmntrap, _cmntrap)
-
-	INTR_PUSH
-
-	ALTENTRY(cmntrap_pushed)
-
-	movl	%esp, %ebp
-
-	/*
-	 * - if this is a #pf i.e. T_PGFLT, %esi is live
-	 *   and contains the faulting address i.e. a copy of %cr2
-	 *
-	 * - if this is a #db i.e. T_SGLSTP, %esi is live
-	 *   and contains the value of %db6
-	 */
-
-	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_TRAP) /* Uses labels 8 and 9 */
-	TRACE_REGS(%edi, %esp, %ebx, %ecx)	/* Uses label 9 */
-	TRACE_STAMP(%edi)		/* Clobbers %eax, %edx, uses 9 */
-
-	/*
-	 * We must first check if DTrace has set its NOFAULT bit.  This
-	 * regrettably must happen before the trap stack is recorded, because
-	 * this requires a call to getpcstack() and may induce recursion if an
-	 * fbt::getpcstack: enabling is inducing the bad load.
-	 */
-	movl	%gs:CPU_ID, %eax
-	shll	$CPU_CORE_SHIFT, %eax
-	addl	$cpu_core, %eax
-	movw	CPUC_DTRACE_FLAGS(%eax), %cx
-	testw	$CPU_DTRACE_NOFAULT, %cx
-	jnz	.dtrace_induced
-
-	TRACE_STACK(%edi)
-
-	pushl	%gs:CPU_ID
-	pushl	%esi		/* fault address for PGFLTs */
-	pushl	%ebp		/* &regs */
-
-	/*
-	 * We know that this isn't a DTrace non-faulting load; we can now safely
-	 * reenable interrupts.  (In the case of pagefaults, we enter through an
-	 * interrupt gate.)
-	 */
-	ENABLE_INTR_FLAGS
-
-	call	trap		/* trap(rp, addr, cpuid) handles all traps */
-	addl	$12, %esp	/* get argument off stack */
-	jmp	_sys_rtt
-
-.dtrace_induced:
-	cmpw	$KCS_SEL, REGOFF_CS(%ebp)	/* test CS for user-mode trap */
-	jne	3f				/* if from user, panic */
-
-	cmpl	$T_PGFLT, REGOFF_TRAPNO(%ebp)
-	je	1f
-
-	cmpl	$T_GPFLT, REGOFF_TRAPNO(%ebp)
-	je	0f
-
-	cmpl	$T_ZERODIV, REGOFF_TRAPNO(%ebp)
-	jne	4f				/* if not PF/GP/UD/DE, panic */
-
-	orw	$CPU_DTRACE_DIVZERO, %cx
-	movw	%cx, CPUC_DTRACE_FLAGS(%eax)
-	jmp	2f
-
-0:
-	/*
-	 * If we've taken a GPF, we don't (unfortunately) have the address that
-	 * induced the fault.  So instead of setting the fault to BADADDR,
-	 * we'll set the fault to ILLOP.
-	 */
-	orw	$CPU_DTRACE_ILLOP, %cx
-	movw	%cx, CPUC_DTRACE_FLAGS(%eax)
-	jmp	2f
-1:
-	orw	$CPU_DTRACE_BADADDR, %cx
-	movw	%cx, CPUC_DTRACE_FLAGS(%eax)	/* set fault to bad addr */
-	movl	%esi, CPUC_DTRACE_ILLVAL(%eax)
-					    /* fault addr is illegal value */
-2:
-	pushl	REGOFF_EIP(%ebp)
-	call	dtrace_instr_size
-	addl	$4, %esp
-	movl	REGOFF_EIP(%ebp), %ecx
-	addl	%eax, %ecx
-	movl	%ecx, REGOFF_EIP(%ebp)
-	INTR_POP_KERNEL
-	IRET
-	/*NOTREACHED*/
-3:
-	pushl	$dtrace_badflags
-	call	panic
-4:
-	pushl	$dtrace_badtrap
-	call	panic
-	SET_SIZE(cmntrap)
-	SET_SIZE(_cmntrap)
-
-#endif	/* __i386 */
-
 /*
  * Declare a uintptr_t which has the size of _cmntrap to enable stack
  * traceback code to know when a regs structure is on the stack.
@@ -1327,27 +343,8 @@
 dtrace_badtrap:
 	.string "bad DTrace trap"
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-cmninttrap()
-{}
-
-#if !defined(__xpv)
-void
-bop_trap_handler(void)
-{}
-#endif
-
-#else	/* __lint */
-
 	.globl	trap		/* C handler called below */
 
-#if defined(__amd64)
-
 	ENTRY_NP(cmninttrap)
 
 	INTR_PUSH
@@ -1380,58 +377,8 @@
 	SET_SIZE(bop_trap_handler)
 #endif
 
-#elif defined(__i386)
-
-	ENTRY_NP(cmninttrap)
-
-	INTR_PUSH
-	INTGATE_INIT_KERNEL_FLAGS
-
-	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_TRAP) /* Uses labels 8 and 9 */
-	TRACE_REGS(%edi, %esp, %ebx, %ecx)	/* Uses label 9 */
-	TRACE_STAMP(%edi)		/* Clobbers %eax, %edx, uses 9 */
-
-	movl	%esp, %ebp
-
-	TRACE_STACK(%edi)
-
-	pushl	%gs:CPU_ID
-	pushl	$0
-	pushl	%ebp
-	call	trap		/* trap(rp, addr, cpuid) handles all traps */
-	addl	$12, %esp
-	jmp	_sys_rtt
-	SET_SIZE(cmninttrap)
-
-#if !defined(__xpv)
-	/*
-	 * Handle traps early in boot. Just revectors into C quickly as
-	 * these are always fatal errors.
-	 */
-	ENTRY(bop_trap_handler)
-	movl	%esp, %eax
-	pushl	%eax
-	call	bop_trap
-	SET_SIZE(bop_trap_handler)
-#endif
-
-#endif	/* __i386 */
-
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-dtrace_trap()
-{}
-
-#else	/* __lint */
-
 	.globl	dtrace_user_probe
 
-#if defined(__amd64)
-
 	ENTRY_NP(dtrace_trap)
 
 	INTR_PUSH
@@ -1458,60 +405,10 @@
 
 	SET_SIZE(dtrace_trap)
 
-#elif defined(__i386)
-
-	ENTRY_NP(dtrace_trap)
-
-	INTR_PUSH
-
-	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_TRAP) /* Uses labels 8 and 9 */
-	TRACE_REGS(%edi, %esp, %ebx, %ecx)	/* Uses label 9 */
-	TRACE_STAMP(%edi)		/* Clobbers %eax, %edx, uses 9 */
-
-	movl	%esp, %ebp
-
-	pushl	%gs:CPU_ID
-#if defined(__xpv)
-	movl	%gs:CPU_VCPU_INFO, %eax
-	movl	VCPU_INFO_ARCH_CR2(%eax), %eax
-#else
-	movl	%cr2, %eax
-#endif
-	pushl	%eax
-	pushl	%ebp
-
-	ENABLE_INTR_FLAGS
-
-	call	dtrace_user_probe /* dtrace_user_probe(rp, addr, cpuid) */
-	addl	$12, %esp		/* get argument off stack */
-
-	jmp	_sys_rtt
-	SET_SIZE(dtrace_trap)
-
-#endif	/* __i386 */
-
-#endif	/* __lint */
-
 /*
  * Return from _sys_trap routine.
  */
 
-#if defined(__lint)
-
-void
-lwp_rtt_initial(void)
-{}
-
-void
-lwp_rtt(void)
-{}
-
-void
-_sys_rtt(void)
-{}
-
-#else	/* __lint */
-
 	ENTRY_NP(lwp_rtt_initial)
 	movq	%gs:CPU_THREAD, %r15
 	movq	T_STACK(%r15), %rsp	/* switch to the thread stack */
@@ -1636,32 +533,6 @@
 	SET_SIZE(sys_rtt_syscall)
 	SET_SIZE(sys_rtt_syscall32)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*
- * So why do we have to deal with all this crud in the world of ia32?
- *
- * Basically there are four classes of ia32 implementations, those that do not
- * have a TSC, those that have a marginal TSC that is broken to the extent
- * that it is useless, those that have a marginal TSC that is not quite so
- * horribly broken and can be used with some care, and those that have a
- * reliable TSC. This crud has to be here in order to sift through all the
- * variants.
- */
-
-/*ARGSUSED*/
-uint64_t
-freq_tsc(uint32_t *pit_counter)
-{
-	return (0);
-}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	/*
 	 * XX64 quick and dirty port from the i386 version. Since we
 	 * believe the amd64 tsc is more reliable, could this code be
@@ -1867,410 +738,3 @@
 	ret
 	SET_SIZE(freq_tsc)
 
-#elif defined(__i386)
-
-	ENTRY_NP(freq_tsc)
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	%edi
-	pushl	%esi
-	pushl	%ebx
-
-/ We have a TSC, but we have no way in general to know how reliable it is.
-/ Usually a marginal TSC behaves appropriately unless not enough time
-/ elapses between reads. A reliable TSC can be read as often and as rapidly
-/ as desired. The simplistic approach of reading the TSC counter and
-/ correlating to the PIT counter cannot be naively followed. Instead estimates
-/ have to be taken to successively refine a guess at the speed of the cpu
-/ and then the TSC and PIT counter are correlated. In practice very rarely
-/ is more than one quick loop required for an estimate. Measures have to be
-/ taken to prevent the PIT counter from wrapping beyond its resolution and for
-/ measuring the clock rate of very fast processors.
-/
-/ The following constant can be tuned. It should be such that the loop does
-/ not take too many nor too few PIT counts to execute. If this value is too
-/ large, then on slow machines the loop will take a long time, or the PIT
-/ counter may even wrap. If this value is too small, then on fast machines
-/ the PIT counter may count so few ticks that the resolution of the PIT
-/ itself causes a bad guess. Because this code is used in machines with
-/ marginal TSC's and/or IO, if this value is too small on those, it may
-/ cause the calculated cpu frequency to vary slightly from boot to boot.
-/
-/ In all cases even if this constant is set inappropriately, the algorithm
-/ will still work and the caller should be able to handle variances in the
-/ calculation of cpu frequency, but the calculation will be inefficient and
-/ take a disproportionate amount of time relative to a well selected value.
-/ As the slowest supported cpu becomes faster, this constant should be
-/ carefully increased.
-
-	movl	$0x8000, %ecx
-
-	/ to make sure the instruction cache has been warmed
-	clc
-
-	jmp	freq_tsc_loop
-
-/ The following block of code up to and including the latching of the PIT
-/ counter after freq_tsc_perf_loop is very critical and very carefully
-/ written, it should only be modified with great care. freq_tsc_loop to
-/ freq_tsc_perf_loop fits exactly in 16 bytes as do the instructions in
-/ freq_tsc_perf_loop up to the unlatching of the PIT counter.
-
-	.align	32
-freq_tsc_loop:
-	/ save the loop count in %ebx
-	movl	%ecx, %ebx
-
-	/ initialize the PIT counter and start a count down
-	movb	$PIT_LOADMODE, %al
-	outb	$PITCTL_PORT
-	movb	$0xff, %al
-	outb	$PITCTR0_PORT
-	outb	$PITCTR0_PORT
-
-	/ read the TSC and store the TS in %edi:%esi
-	rdtsc
-	movl	%eax, %esi
-
-freq_tsc_perf_loop:
-	movl	%edx, %edi
-	movl	%eax, %esi
-	movl	%edx, %edi
-	loop	freq_tsc_perf_loop
-
-	/ read the TSC and store the LSW in %ecx
-	rdtsc
-	movl	%eax, %ecx
-
-	/ latch the PIT counter and status
-	movb	$_CONST(PIT_READBACK|PIT_READBACKC0), %al
-	outb	$PITCTL_PORT
-
-	/ remember if the icache has been warmed
-	setc	%ah
-
-	/ read the PIT status
-	inb	$PITCTR0_PORT
-	shll	$8, %eax
-
-	/ read PIT count
-	inb	$PITCTR0_PORT
-	shll	$8, %eax
-	inb	$PITCTR0_PORT
-	bswap	%eax
-
-	/ check to see if the PIT count was loaded into the CE
-	btw	$_CONST(PITSTAT_NULLCNT+8), %ax
-	jc	freq_tsc_increase_count
-
-	/ check to see if PIT counter wrapped
-	btw	$_CONST(PITSTAT_OUTPUT+8), %ax
-	jnc	freq_tsc_pit_did_not_wrap
-
-	/ halve count
-	shrl	$1, %ebx
-	movl	%ebx, %ecx
-
-	/ the instruction cache has been warmed
-	stc
-
-	jmp	freq_tsc_loop
-
-freq_tsc_increase_count:
-	shll	$1, %ebx
-	jc	freq_tsc_too_fast
-
-	movl	%ebx, %ecx
-
-	/ the instruction cache has been warmed
-	stc
-
-	jmp	freq_tsc_loop
-
-freq_tsc_pit_did_not_wrap:
-	roll	$16, %eax
-
-	cmpw	$0x2000, %ax
-	notw	%ax
-	jb	freq_tsc_sufficient_duration
-
-freq_tsc_calculate:
-	/ in mode 0, the PIT loads the count into the CE on the first CLK pulse,
-	/ then on the second CLK pulse the CE is decremented, therefore mode 0
-	/ is really a (count + 1) counter, ugh
-	xorl	%esi, %esi
-	movw	%ax, %si
-	incl	%esi
-
-	movl	$0xf000, %eax
-	mull	%ebx
-
-	/ tuck away (target_pit_count * loop_count)
-	movl	%edx, %ecx
-	movl	%eax, %ebx
-
-	movl	%esi, %eax
-	movl	$0xffffffff, %edx
-	mull	%edx
-
-	addl	%esi, %eax
-	adcl	$0, %edx
-
-	cmpl	%ecx, %edx
-	ja	freq_tsc_div_safe
-	jb	freq_tsc_too_fast
-
-	cmpl	%ebx, %eax
-	jbe	freq_tsc_too_fast
-
-freq_tsc_div_safe:
-	movl	%ecx, %edx
-	movl	%ebx, %eax
-
-	movl	%esi, %ecx
-	divl	%ecx
-
-	movl	%eax, %ecx
-
-	/ the instruction cache has been warmed
-	stc
-
-	jmp	freq_tsc_loop
-
-freq_tsc_sufficient_duration:
-	/ test to see if the icache has been warmed
-	btl	$16, %eax
-	jnc	freq_tsc_calculate
-
-	/ recall mode 0 is a (count + 1) counter
-	andl	$0xffff, %eax
-	incl	%eax
-
-	/ save the number of PIT counts
-	movl	8(%ebp), %ebx
-	movl	%eax, (%ebx)
-
-	/ calculate the number of TS's that elapsed
-	movl	%ecx, %eax
-	subl	%esi, %eax
-	sbbl	%edi, %edx
-
-	jmp	freq_tsc_end
-
-freq_tsc_too_fast:
-	/ return 0 as a 64 bit quantity
-	xorl	%eax, %eax
-	xorl	%edx, %edx
-
-freq_tsc_end:
-	popl	%ebx
-	popl	%esi
-	popl	%edi
-	popl	%ebp
-	ret
-	SET_SIZE(freq_tsc)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if !defined(__amd64)
-#if defined(__lint)
-
-/*
- * We do not have a TSC so we use a block of instructions with well known
- * timings.
- */
-
-/*ARGSUSED*/
-uint64_t
-freq_notsc(uint32_t *pit_counter)
-{
-	return (0);
-}
-
-#else	/* __lint */
-	ENTRY_NP(freq_notsc)
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	%edi
-	pushl	%esi
-	pushl	%ebx
-
-	/ initial count for the idivl loop
-	movl	$0x1000, %ecx
-
-	/ load the divisor
-	movl	$1, %ebx
-
-	jmp	freq_notsc_loop
-
-.align	16
-freq_notsc_loop:
-	/ set high 32 bits of dividend to zero
-	xorl	%edx, %edx
-
-	/ save the loop count in %edi
-	movl	%ecx, %edi
-
-	/ initialize the PIT counter and start a count down
-	movb	$PIT_LOADMODE, %al
-	outb	$PITCTL_PORT
-	movb	$0xff, %al
-	outb	$PITCTR0_PORT
-	outb	$PITCTR0_PORT
-
-	/ set low 32 bits of dividend to zero
-	xorl	%eax, %eax
-
-/ It is vital that the arguments to idivl be set appropriately because on some
-/ cpu's this instruction takes more or less clock ticks depending on its
-/ arguments.
-freq_notsc_perf_loop:
-	idivl	%ebx
-	idivl	%ebx
-	idivl	%ebx
-	idivl	%ebx
-	idivl	%ebx
-	loop	freq_notsc_perf_loop
-
-	/ latch the PIT counter and status
-	movb	$_CONST(PIT_READBACK|PIT_READBACKC0), %al
-	outb	$PITCTL_PORT
-
-	/ read the PIT status
-	inb	$PITCTR0_PORT
-	shll	$8, %eax
-
-	/ read PIT count
-	inb	$PITCTR0_PORT
-	shll	$8, %eax
-	inb	$PITCTR0_PORT
-	bswap	%eax
-
-	/ check to see if the PIT count was loaded into the CE
-	btw	$_CONST(PITSTAT_NULLCNT+8), %ax
-	jc	freq_notsc_increase_count
-
-	/ check to see if PIT counter wrapped
-	btw	$_CONST(PITSTAT_OUTPUT+8), %ax
-	jnc	freq_notsc_pit_did_not_wrap
-
-	/ halve count
-	shrl	$1, %edi
-	movl	%edi, %ecx
-
-	jmp	freq_notsc_loop
-
-freq_notsc_increase_count:
-	shll	$1, %edi
-	jc	freq_notsc_too_fast
-
-	movl	%edi, %ecx
-
-	jmp	freq_notsc_loop
-
-freq_notsc_pit_did_not_wrap:
-	shrl	$16, %eax
-
-	cmpw	$0x2000, %ax
-	notw	%ax
-	jb	freq_notsc_sufficient_duration
-
-freq_notsc_calculate:
-	/ in mode 0, the PIT loads the count into the CE on the first CLK pulse,
-	/ then on the second CLK pulse the CE is decremented, therefore mode 0
-	/ is really a (count + 1) counter, ugh
-	xorl	%esi, %esi
-	movw	%ax, %si
-	incl	%esi
-
-	movl	%edi, %eax
-	movl	$0xf000, %ecx
-	mull	%ecx
-
-	/ tuck away (target_pit_count * loop_count)
-	movl	%edx, %edi
-	movl	%eax, %ecx
-
-	movl	%esi, %eax
-	movl	$0xffffffff, %edx
-	mull	%edx
-
-	addl	%esi, %eax
-	adcl	$0, %edx
-
-	cmpl	%edi, %edx
-	ja	freq_notsc_div_safe
-	jb	freq_notsc_too_fast
-
-	cmpl	%ecx, %eax
-	jbe	freq_notsc_too_fast
-
-freq_notsc_div_safe:
-	movl	%edi, %edx
-	movl	%ecx, %eax
-
-	movl	%esi, %ecx
-	divl	%ecx
-
-	movl	%eax, %ecx
-
-	jmp	freq_notsc_loop
-
-freq_notsc_sufficient_duration:
-	/ recall mode 0 is a (count + 1) counter
-	incl	%eax
-
-	/ save the number of PIT counts
-	movl	8(%ebp), %ebx
-	movl	%eax, (%ebx)
-
-	/ calculate the number of cpu clock ticks that elapsed
-	cmpl	$X86_VENDOR_Cyrix, x86_vendor
-	jz	freq_notsc_notcyrix
-
-	/ freq_notsc_perf_loop takes 86 clock cycles on Cyrix 6x86 cores
-	movl	$86, %eax
-	jmp	freq_notsc_calculate_tsc
-
-freq_notsc_notcyrix:
-	/ freq_notsc_perf_loop takes 237 clock cycles on Intel Pentiums
-	movl	$237, %eax
-
-freq_notsc_calculate_tsc:
-	mull	%edi
-
-	jmp	freq_notsc_end
-
-freq_notsc_too_fast:
-	/ return 0 as a 64 bit quantity
-	xorl	%eax, %eax
-	xorl	%edx, %edx
-
-freq_notsc_end:
-	popl	%ebx
-	popl	%esi
-	popl	%edi
-	popl	%ebp
-
-	ret
-	SET_SIZE(freq_notsc)
-
-#endif	/* __lint */
-#endif	/* !__amd64 */
-
-#if !defined(__lint)
-	.data
-#if !defined(__amd64)
-	.align	4
-cpu_vendor:
-	.long	0, 0, 0		/* Vendor ID string returned */
-
-	.globl	CyrixInstead
-
-	.globl	x86_featureset
-	.globl	x86_type
-	.globl	x86_vendor
-#endif
-
-#endif	/* __lint */
--- old/usr/src/uts/i86pc/ml/mach_offsets.in	Thu Nov 14 19:00:16 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,150 +0,0 @@
-\
-\ Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
-\ Use is subject to license terms.
-\
-\ CDDL HEADER START
-\
-\ The contents of this file are subject to the terms of the
-\ Common Development and Distribution License (the "License").
-\ You may not use this file except in compliance with the License.
-\
-\ You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
-\ or http://www.opensolaris.org/os/licensing.
-\ See the License for the specific language governing permissions
-\ and limitations under the License.
-\
-\ When distributing Covered Code, include this CDDL HEADER in each
-\ file and include the License file at usr/src/OPENSOLARIS.LICENSE.
-\ If applicable, add the following below this CDDL HEADER, with the
-\ fields enclosed by brackets "[]" replaced with your own identifying
-\ information: Portions Copyright [yyyy] [name of copyright owner]
-\
-\ CDDL HEADER END
-\
-\ Copyright 2011 Joyent, Inc. All rights reserved.
-\
-
-\
-\ offsets.in: input file to produce assym.h using the ctfstabs program
-\
-
-#ifndef	_GENASSYM
-#define	_GENASSYM
-#endif
-
-#define	SIZES	1
-
-#if defined(__xpv)
-\
-\ XXPV	This seems to need to be first to avoid a namespace collision
-\	with another header file in the list below.
-\
-#include <sys/hypervisor.h>
-#endif
-
-#include <sys/types.h>
-#include <sys/bootsvcs.h>
-#include <sys/systm.h>
-#include <sys/sysinfo.h>
-#include <sys/user.h>
-#include <sys/thread.h>
-#include <sys/proc.h>
-#include <sys/cpuvar.h>
-#include <sys/tss.h>
-#include <sys/privregs.h>
-#include <sys/segments.h>
-#include <sys/devops.h>
-#include <sys/ddi_impldefs.h>
-#include <vm/as.h>
-#include <sys/avintr.h>
-#include <sys/pic.h>
-#include <sys/rm_platter.h>
-#include <sys/stream.h>
-#include <sys/strsubr.h>
-#include <sys/sunddi.h>
-#include <sys/traptrace.h>
-#include <sys/ontrap.h>
-#include <sys/lgrp.h>
-#include <sys/dtrace.h>
-
-regs	REGSIZE
-	r_savfp	REGOFF_SAVFP
-	r_savpc	REGOFF_SAVPC
-	r_gs	REGOFF_GS
-	r_fs	REGOFF_FS
-	r_es	REGOFF_ES
-	r_ds	REGOFF_DS
-	r_edi	REGOFF_EDI
-	r_esi	REGOFF_ESI
-	r_ebp	REGOFF_EBP
-	r_esp	REGOFF_ESP
-	r_ebx	REGOFF_EBX
-	r_edx	REGOFF_EDX
-	r_ecx	REGOFF_ECX
-	r_eax	REGOFF_EAX
-	r_trapno	REGOFF_TRAPNO
-	r_err	REGOFF_ERR
-	r_eip	REGOFF_EIP
-	r_cs	REGOFF_CS
-	r_efl	REGOFF_EFL
-	r_uesp	REGOFF_UESP
-	r_ss	REGOFF_SS
-
-\#define	REGOFF_PC	REGOFF_EIP
-
-tss_t
-	tss_esp0		TSS_ESP0
-	tss_ss0		TSS_SS0
-	tss_ldt		TSS_LDT
-	tss_cr3		TSS_CR3
-	tss_cs		TSS_CS
-	tss_ss		TSS_SS
-	tss_ds		TSS_DS
-	tss_es		TSS_ES
-	tss_fs		TSS_FS
-	tss_gs		TSS_GS
-	tss_ebp		TSS_EBP
-	tss_eip		TSS_EIP
-	tss_eflags	TSS_EFL
-	tss_esp		TSS_ESP
-	tss_eax		TSS_EAX
-	tss_ebx		TSS_EBX
-	tss_ecx		TSS_ECX
-	tss_edx		TSS_EDX
-	tss_esi		TSS_ESI
-	tss_edi		TSS_EDI
-
-\#define	LABEL_EBP	_CONST(_MUL(2, LABEL_VAL_INCR) + LABEL_VAL)
-\#define	LABEL_EBX	_CONST(_MUL(3, LABEL_VAL_INCR) + LABEL_VAL)
-\#define	LABEL_ESI	_CONST(_MUL(4, LABEL_VAL_INCR) + LABEL_VAL)
-\#define	LABEL_EDI	_CONST(_MUL(5, LABEL_VAL_INCR) + LABEL_VAL)
-\#define	T_EBP		_CONST(T_LABEL + LABEL_EBP)
-\#define	T_EBX		_CONST(T_LABEL + LABEL_EBX)
-\#define	T_ESI		_CONST(T_LABEL + LABEL_ESI)
-\#define	T_EDI		_CONST(T_LABEL + LABEL_EDI)
-
-_klwp
-	lwp_pcb.pcb_fsdesc			LWP_PCB_FSDESC
-	lwp_pcb.pcb_gsdesc			LWP_PCB_GSDESC
-	lwp_pcb.pcb_drstat			LWP_PCB_DRSTAT
-	lwp_pcb.pcb_flags			PCB_FLAGS
-	lwp_pcb.pcb_fpu				LWP_PCB_FPU
-	lwp_pcb.pcb_fpu.fpu_regs		LWP_FPU_REGS
-	lwp_pcb.pcb_fpu.fpu_flags		LWP_FPU_FLAGS
-	lwp_pcb.pcb_fpu.fpu_regs.kfpu_u.kfpu_fx	LWP_FPU_CHIP_STATE
-
-pcb	PCBSIZE
-	pcb_drstat
-	pcb_fsdesc
-	pcb_gsdesc
-	pcb_fpu.fpu_regs	PCB_FPU_REGS
-	pcb_fpu.fpu_flags	PCB_FPU_FLAGS
-
-#if defined(__xpv)
-
-vcpu_info
-	evtchn_upcall_pending	VCPU_INFO_EVTCHN_UPCALL_PENDING
-	evtchn_upcall_mask	VCPU_INFO_EVTCHN_UPCALL_MASK
-	arch.cr2		VCPU_INFO_ARCH_CR2
-
-#endif	/* __xpv */
--- old/usr/src/uts/i86pc/ml/mpcore.s	Thu Nov 14 19:00:16 2019
+++ new/usr/src/uts/i86pc/ml/mpcore.s	Thu Nov 14 19:00:16 2019
@@ -34,10 +34,8 @@
 #include <sys/privregs.h>
 #include <sys/x86_archext.h>
 
-#if !defined(__lint)
 #include <sys/segments.h>
 #include "assym.h"
-#endif
 
 /*
  *	Our assumptions:
@@ -60,24 +58,6 @@
  *
  */
 
-#if defined(__lint)
-
-void
-real_mode_start_cpu(void)
-{}
-
-void
-real_mode_stop_cpu_stage1(void)
-{}
-
-void
-real_mode_stop_cpu_stage2(void)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(real_mode_start_cpu)
 
 	/*
@@ -118,30 +98,9 @@
 	/*
 	 * 16-bit protected mode is now active, so prepare to turn on long
 	 * mode.
-	 *
-	 * Note that we currently assume that if we're attempting to run a
-	 * kernel compiled with (__amd64) #defined, the target CPU has long
-	 * mode support.
 	 */
 
-#if 0
 	/*
-	 * If there's a chance this might not be true, the following test should
-	 * be done, with the no_long_mode branch then doing something
-	 * appropriate:
-	 */
-
-	movl		$0x80000000, %eax	/* get largest extended CPUID */
-	cpuid
-	cmpl		$0x80000000, %eax	/* check if > 0x80000000 */
-	jbe		no_long_mode		/* nope, no long mode */
-	movl		$0x80000001, %eax
-	cpuid					/* get extended feature flags */
-	btl		$29, %edx		/* check for long mode */
-	jnc		no_long_mode		/* long mode not supported */
-#endif
-
-	/*
 	 * Add any initial cr4 bits
 	 */
 	movl		%cr4, %eax
@@ -335,200 +294,6 @@
 
 	SET_SIZE(real_mode_start_cpu)
 
-#elif defined(__i386)
-
-	ENTRY_NP(real_mode_start_cpu)
-
-#if !defined(__GNUC_AS__)
-
-	cli
-	D16 movw	%cs, %eax
-	movw		%eax, %ds	/* load cs into ds */
-	movw		%eax, %ss	/* and into ss */
-
-	/*
-	 * Helps in debugging by giving us the fault address.
-	 *
-	 * Remember to patch a hlt (0xf4) at cmntrap to get a good stack.
-	 */
-	D16 movl	$0xffc, %esp
-
-	D16 A16 lgdt	%cs:GDTROFF
-	D16 A16 lidt	%cs:IDTROFF
-	D16 A16 movl	%cs:CR4OFF, %eax	/* set up CR4, if desired */
-	D16 andl	%eax, %eax
-	D16 A16 je	no_cr4
-
-	D16 movl	%eax, %ecx
-	D16 movl	%cr4, %eax
-	D16 orl		%ecx, %eax
-	D16 movl	%eax, %cr4
-no_cr4:
-	D16 A16 movl	%cs:CR3OFF, %eax
-	A16 movl	%eax, %cr3
-	movl		%cr0, %eax
-
-	/*
-	 * Enable protected-mode, paging, write protect, and alignment mask
-	 */
-	D16 orl		$[CR0_PG|CR0_PE|CR0_WP|CR0_AM], %eax
-	movl		%eax, %cr0
-	jmp		pestart
-
-pestart:
-	D16 pushl	$KCS_SEL
-	D16 pushl	$kernel_cs_code
-	D16 lret
-	.globl real_mode_start_cpu_end
-real_mode_start_cpu_end:
-	nop
-
-	.globl	kernel_cs_code
-kernel_cs_code:
-	/*
-	 * At this point we are with kernel's cs and proper eip.
-	 *
-	 * We will be executing not from the copy in real mode platter,
-	 * but from the original code where boot loaded us.
-	 *
-	 * By this time GDT and IDT are loaded as is cr3.
-	 */
-	movw	$KFS_SEL,%eax
-	movw	%eax,%fs
-	movw	$KGS_SEL,%eax
-	movw	%eax,%gs
-	movw	$KDS_SEL,%eax
-	movw	%eax,%ds
-	movw	%eax,%es
-	movl	%gs:CPU_TSS,%esi
-	movw	%eax,%ss
-	movl	TSS_ESP0(%esi),%esp
-	movw	$KTSS_SEL,%ax
-	ltr	%ax
-	xorw	%ax, %ax		/* clear LDTR */
-	lldt	%ax
-	movl	%cr0,%edx
-	andl    $-1![CR0_TS|CR0_EM],%edx  /* clear emulate math chip bit */
-	orl     $[CR0_MP|CR0_NE],%edx
-	movl    %edx,%cr0		  /* set machine status word */
-
-	/*
-	 * Before going any further, enable usage of page table NX bit if
-	 * that's how our page tables are set up.
-	 */
-	bt	$X86FSET_NX, x86_featureset
-	jnc	1f
-	movl	%cr4, %ecx
-	andl	$CR4_PAE, %ecx
-	jz	1f
-	movl	$MSR_AMD_EFER, %ecx
-	rdmsr
-	orl	$AMD_EFER_NXE, %eax
-	wrmsr
-1:
-	movl	%gs:CPU_THREAD, %eax	/* get thread ptr */
-	call	*T_PC(%eax)		/* call mp_startup */
-	/* not reached */
-	int	$20			/* whoops, returned somehow! */
-
-#else
-
-	cli
-	mov		%cs, %ax
-	mov		%eax, %ds	/* load cs into ds */
-	mov		%eax, %ss	/* and into ss */
-
-	/*
-	 * Helps in debugging by giving us the fault address.
-	 *
-	 * Remember to patch a hlt (0xf4) at cmntrap to get a good stack.
-	 */
-	D16 mov		$0xffc, %esp
-
-	D16 A16 lgdtl	%cs:GDTROFF
-	D16 A16 lidtl	%cs:IDTROFF
-	D16 A16 mov	%cs:CR4OFF, %eax	/* set up CR4, if desired */
-	D16 and		%eax, %eax
-	D16 A16 je	no_cr4
-
-	D16 mov		%eax, %ecx
-	D16 mov		%cr4, %eax
-	D16 or		%ecx, %eax
-	D16 mov		%eax, %cr4
-no_cr4:
-	D16 A16 mov	%cs:CR3OFF, %eax
-	A16 mov		%eax, %cr3
-	mov		%cr0, %eax
-
-	/*
-	 * Enable protected-mode, paging, write protect, and alignment mask
-	 */
-	D16 or		$(CR0_PG|CR0_PE|CR0_WP|CR0_AM), %eax
-	mov		%eax, %cr0
-	jmp		pestart
-
-pestart:
-	D16 pushl	$KCS_SEL
-	D16 pushl	$kernel_cs_code
-	D16 lret
-	.globl real_mode_start_cpu_end
-real_mode_start_cpu_end:
-	nop
-	.globl	kernel_cs_code
-kernel_cs_code:
-	/*
-	 * At this point we are with kernel's cs and proper eip.
-	 *
-	 * We will be executing not from the copy in real mode platter,
-	 * but from the original code where boot loaded us.
-	 *
-	 * By this time GDT and IDT are loaded as is cr3.
-	 */
-	mov	$KFS_SEL, %ax
-	mov	%eax, %fs
-	mov	$KGS_SEL, %ax
-	mov	%eax, %gs
-	mov	$KDS_SEL, %ax
-	mov	%eax, %ds
-	mov	%eax, %es
-	mov	%gs:CPU_TSS, %esi
-	mov	%eax, %ss
-	mov	TSS_ESP0(%esi), %esp
-	mov	$(KTSS_SEL), %ax
-	ltr	%ax
-	xorw	%ax, %ax		/* clear LDTR */
-	lldt	%ax
-	mov	%cr0, %edx
-	and	$~(CR0_TS|CR0_EM), %edx	/* clear emulate math chip bit */
-	or	$(CR0_MP|CR0_NE), %edx
-	mov	%edx, %cr0		/* set machine status word */
-
-	/*
-	 * Before going any farther, enable usage of page table NX bit if
-	 * that's how our page tables are set up.  (PCIDE is enabled later on).
-	 */
-	bt	$X86FSET_NX, x86_featureset
-	jnc	1f
-	movl	%cr4, %ecx
-	andl	$CR4_PAE, %ecx
-	jz	1f
-	movl	$MSR_AMD_EFER, %ecx
-	rdmsr
-	orl	$AMD_EFER_NXE, %eax
-	wrmsr
-1:
-	mov	%gs:CPU_THREAD, %eax	/* get thread ptr */
-	call	*T_PC(%eax)		/* call mp_startup */
-	/* not reached */
-	int	$20			/* whoops, returned somehow! */
-#endif
-
-	SET_SIZE(real_mode_start_cpu)
-
-#endif	/* __amd64 */
-
-#if defined(__amd64)
-
 	ENTRY_NP(real_mode_stop_cpu_stage1)
 
 #if !defined(__GNUC_AS__)
@@ -580,52 +345,6 @@
 
 	SET_SIZE(real_mode_stop_cpu_stage1)
 
-#elif defined(__i386)
-
-	ENTRY_NP(real_mode_stop_cpu_stage1)
-
-#if !defined(__GNUC_AS__)
-
-	cli
-	D16 movw	%cs, %eax
-	movw		%eax, %ds	/* load cs into ds */
-	movw		%eax, %ss	/* and into ss */
-
-	/*
-	 * Jump to the stage 2 code in the rm_platter_va->rm_cpu_halt_code
-	 */
-	movw		$CPUHALTCODEOFF, %ax
-	.byte		0xff, 0xe0	/* jmp *%ax */
-
-#else	/* __GNUC_AS__ */
-
-	cli
-	mov		%cs, %ax
-	mov		%eax, %ds	/* load cs into ds */
-	mov		%eax, %ss	/* and into ss */
-
-	/*
-	 * Jump to the stage 2 code in the rm_platter_va->rm_cpu_halt_code
-	 */
-	movw		$CPUHALTCODEOFF, %ax
-	/*
-	 * The following indirect call is executed as part of starting up a CPU.
-	 * As such nothing else should be running on it or executing in the
-	 * system such that it is a viable Spectre v2 branch target injection
-	 * location. At least, in theory.
-	 */
-	jmp		*%ax
-
-#endif	/* !__GNUC_AS__ */
-
-	.globl real_mode_stop_cpu_stage1_end
-real_mode_stop_cpu_stage1_end:
-	nop
-
-	SET_SIZE(real_mode_stop_cpu_stage1)
-
-#endif	/* __amd64 */
-
 	ENTRY_NP(real_mode_stop_cpu_stage2)
 
 	movw		$0xdead, %ax
@@ -645,4 +364,3 @@
 
 	SET_SIZE(real_mode_stop_cpu_stage2)
 
-#endif	/* __lint */
--- old/usr/src/uts/i86pc/ml/notes.s	Thu Nov 14 19:00:16 2019
+++ new/usr/src/uts/i86pc/ml/notes.s	Thu Nov 14 19:00:16 2019
@@ -21,21 +21,18 @@
  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
-	
-#include <sys/elf_notes.h>
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
+/*
+ * Copyright 2019 Joyent, Inc.
+ */
 
-#if defined(lint)
-#include <sys/types.h>
-#else
+#include <sys/elf_notes.h>
 
 #include "assym.h"
 
-/
-/ Tell the booter that we'd like to load unix on a large page
-/ if the chip supports it.
-/
+/*
+ * Tell the booter that we'd like to load unix on a large page.
+ */
 	.section        .note
 	.align          4
 	.4byte           .name1_end - .name1_begin 
@@ -49,4 +46,3 @@
 	.4byte		FOUR_MEG
 .desc1_end:
 	.align		4
-#endif
--- old/usr/src/uts/i86pc/ml/offsets.in	Thu Nov 14 19:00:17 2019
+++ new/usr/src/uts/i86pc/ml/offsets.in	Thu Nov 14 19:00:17 2019
@@ -1,7 +1,7 @@
 \
 \ Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
 \ Copyright 2012 Garrett D'Amore <garrett@damore.org>.  All rights reserved.
-\ Copyright 2018 Joyent, Inc.
+\ Copyright 2019 Joyent, Inc.
 \
 \ CDDL HEADER START
 \
@@ -124,9 +124,7 @@
 	_tu._ts._t_post_sys	T_POST_SYS
 	_tu._t_post_sys_ast	T_POST_SYS_AST
 	t_copyops
-#ifdef	__amd64
 	t_useracc
-#endif
 
 ctxop
 	save_op			CTXOP_SAVE
--- old/usr/src/uts/i86pc/ml/syscall_asm.s	Thu Nov 14 19:00:17 2019
+++ new/usr/src/uts/i86pc/ml/syscall_asm.s	Thu Nov 14 19:00:17 2019
@@ -20,32 +20,17 @@
  */
 /*
  * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2019 Joyent, Inc.
  * Copyright (c) 2016 by Delphix. All rights reserved.
  */
 
-/*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc.	*/
-/*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T	*/
-/*	  All Rights Reserved					*/
-
-/*	Copyright (c) 1987, 1988 Microsoft Corporation		*/
-/*	  All Rights Reserved					*/
-
 #include <sys/asm_linkage.h>
 #include <sys/asm_misc.h>
 #include <sys/regset.h>
+#include <sys/privregs.h>
 #include <sys/psw.h>
-#include <sys/x86_archext.h>
 #include <sys/machbrand.h>
-#include <sys/privregs.h>
 
-#if defined(__lint)
-
-#include <sys/types.h>
-#include <sys/thread.h>
-#include <sys/systm.h>
-
-#else	/* __lint */
-
 #include <sys/segments.h>
 #include <sys/pcb.h>
 #include <sys/trap.h>
@@ -52,438 +37,927 @@
 #include <sys/ftrace.h>
 #include <sys/traptrace.h>
 #include <sys/clock.h>
+#include <sys/model.h>
 #include <sys/panic.h>
-#include "assym.h"
 
-#endif	/* __lint */
+#if defined(__xpv)
+#include <sys/hypervisor.h>
+#endif
 
+#include "assym.h"
+
 /*
- * We implement two flavours of system call entry points
+ * We implement five flavours of system call entry points
  *
- * -	{int,lcall}/iret	(i386)
- * -	sysenter/sysexit	(Pentium II and beyond)
+ * -	syscall/sysretq		(amd64 generic)
+ * -	syscall/sysretl		(i386 plus SYSC bit)
+ * -	sysenter/sysexit	(i386 plus SEP bit)
+ * -	int/iret		(i386 generic)
+ * -	lcall/iret		(i386 generic)
  *
- * The basic pattern used in the handlers is to check to see if we can
- * do fast (simple) version of the system call; if we can't we use various
- * C routines that handle corner cases and debugging.
+ * The current libc included in Solaris uses int/iret as the base unoptimized
+ * kernel entry method. Older libc implementations and legacy binaries may use
+ * the lcall call gate, so it must continue to be supported.
  *
- * To reduce the amount of assembler replication, yet keep the system call
- * implementations vaguely comprehensible, the common code in the body
- * of the handlers is broken up into a set of preprocessor definitions
- * below.
+ * System calls that use an lcall call gate are processed in trap() via a
+ * segment-not-present trap, i.e. lcalls are extremely slow(!).
+ *
+ * The basic pattern used in the 32-bit SYSC handler at this point in time is
+ * to have the bare minimum of assembler, and get to the C handlers as
+ * quickly as possible.
+ *
+ * The 64-bit handler is much closer to the sparcv9 handler; that's
+ * because of passing arguments in registers.  The 32-bit world still
+ * passes arguments on the stack -- that makes that handler substantially
+ * more complex.
+ *
+ * The two handlers share a few code fragments which are broken
+ * out into preprocessor macros below.
+ *
+ * XX64	come back and speed all this up later.  The 32-bit stuff looks
+ * especially easy to speed up the argument copying part ..
+ *
+ *
+ * Notes about segment register usage (c.f. the 32-bit kernel)
+ *
+ * In the 32-bit kernel, segment registers are dutifully saved and
+ * restored on all mode transitions because the kernel uses them directly.
+ * When the processor is running in 64-bit mode, segment registers are
+ * largely ignored.
+ *
+ * %cs and %ss
+ *	controlled by the hardware mechanisms that make mode transitions
+ *
+ * The remaining segment registers have to either be pointing at a valid
+ * descriptor i.e. with the 'present' bit set, or they can NULL descriptors
+ *
+ * %ds and %es
+ *	always ignored
+ *
+ * %fs and %gs
+ *	fsbase and gsbase are used to control the place they really point at.
+ *	The kernel only depends on %gs, and controls its own gsbase via swapgs
+ *
+ * Note that loading segment registers is still costly because the GDT
+ * lookup still happens (this is because the hardware can't know that we're
+ * not setting up these segment registers for a 32-bit program).  Thus we
+ * avoid doing this in the syscall path, and defer them to lwp context switch
+ * handlers, so the register values remain virtualized to the lwp.
  */
 
-/*
- * When we have SYSCALLTRACE defined, we sneak an extra
- * predicate into a couple of tests.
- */
 #if defined(SYSCALLTRACE)
-#define	ORL_SYSCALLTRACE(r32)	\
-	orl	syscalltrace, r32
+#define	ORL_SYSCALLTRACE(r32)		\
+	orl	syscalltrace(%rip), r32
 #else
 #define	ORL_SYSCALLTRACE(r32)
 #endif
 
 /*
- * This check is false whenever we want to go fast i.e.
+ * In the 32-bit kernel, we do absolutely nothing before getting into the
+ * brand callback checks.  In 64-bit land, we do swapgs and then come here.
+ * We assume that the %rsp- and %r15-stashing fields in the CPU structure
+ * are still unused.
  *
- *	if (code >= NSYSCALL ||
- *	    t->t_pre_sys || (t->t_proc_flag & TP_WATCHPT) != 0)
- *		do full version
- * #ifdef SYSCALLTRACE
- *	if (syscalltrace)
- *		do full version
- * #endif
- *
- * Preconditions:
- * -	t	curthread
- * -	code	contains the syscall number
- * Postconditions:
- * -	%ecx and %edi are smashed
- * -	condition code flag ZF is cleared if pre-sys is too complex
- */
-#define	CHECK_PRESYS_NE(t, code)		\
-	movzbl	T_PRE_SYS(t), %edi;		\
-	movzwl	T_PROC_FLAG(t), %ecx;		\
-	andl	$TP_WATCHPT, %ecx;		\
-	orl	%ecx, %edi;			\
-	cmpl	$NSYSCALL, code;		\
-	setae	%cl;				\
-	movzbl	%cl, %ecx;			\
-	orl	%ecx, %edi;			\
-	ORL_SYSCALLTRACE(%edi)
-
-/*
  * Check if a brand_mach_ops callback is defined for the specified callback_id
- * type.  If so invoke it with the user's %gs value loaded and the following
+ * type.  If so invoke it with the kernel's %gs value loaded and the following
  * data on the stack:
- *	   --------------------------------------
- *         | user's %ss                         |
- *    |    | user's %esp                        |
- *    |    | EFLAGS register                    |
- *    |    | user's %cs                         |
- *    |    | user's %eip (user return address)  |
- *    |    | 'scratch space'			|
- *    |    | user's %ebx			|
- *    |    | user's %gs selector		|
- *    v    | lwp pointer			|
- *         | callback wrapper return addr 	|
+ *
+ * stack:  --------------------------------------
+ *      32 | callback pointer			|
+ *    | 24 | user (or interrupt) stack pointer	|
+ *    | 16 | lwp pointer			|
+ *    v  8 | userland return address		|
+ *       0 | callback wrapper return addr	|
  *         --------------------------------------
  *
- * If the brand code returns, we assume that we are meant to execute the
- * normal system call path.
+ * Since we're pushing the userland return address onto the kernel stack
+ * we need to get that address without accessing the user's stack (since we
+ * can't trust that data).  There are different ways to get the userland
+ * return address depending on how the syscall trap was made:
  *
- * The interface to the brand callbacks on the 32-bit kernel assumes %ebx
+ * a) For sys_syscall and sys_syscall32 the return address is in %rcx.
+ * b) For sys_sysenter the return address is in %rdx.
+ * c) For sys_int80 and sys_syscall_int (int91), upon entry into the macro,
+ *    the stack pointer points at the state saved when we took the interrupt:
+ *	 ------------------------
+ *    |  | user's %ss		|
+ *    |  | user's %esp		|
+ *    |  | EFLAGS register	|
+ *    v  | user's %cs		|
+ *       | user's %eip		|
+ *	 ------------------------
+ *
+ * The 2nd parameter to the BRAND_CALLBACK macro is either the
+ * BRAND_URET_FROM_REG or BRAND_URET_FROM_INTR_STACK macro.  These macros are
+ * used to generate the proper code to get the userland return address for
+ * each syscall entry point.
+ *
+ * The interface to the brand callbacks on the 64-bit kernel assumes %r15
  * is available as a scratch register within the callback.  If the callback
- * returns within the kernel then this macro will restore %ebx.  If the
+ * returns within the kernel then this macro will restore %r15.  If the
  * callback is going to return directly to userland then it should restore
- * %ebx before returning to userland.
+ * %r15 before returning to userland.
  */
-#define	BRAND_CALLBACK(callback_id)					    \
-	subl	$4, %esp		/* save some scratch space	*/ ;\
-	pushl	%ebx			/* save %ebx to use for scratch	*/ ;\
-	pushl	%gs			/* save the user %gs		*/ ;\
-	movl	$KGS_SEL, %ebx						   ;\
-	movw	%bx, %gs		/* switch to the kernel's %gs	*/ ;\
-	movl	%gs:CPU_THREAD, %ebx	/* load the thread pointer	*/ ;\
-	movl	T_LWP(%ebx), %ebx	/* load the lwp pointer		*/ ;\
-	pushl	%ebx			/* push the lwp pointer		*/ ;\
-	movl	LWP_PROCP(%ebx), %ebx	/* load the proc pointer	*/ ;\
-	movl	P_BRAND(%ebx), %ebx	/* load the brand pointer	*/ ;\
-	movl	B_MACHOPS(%ebx), %ebx	/* load the machops pointer	*/ ;\
-	movl	_CONST(_MUL(callback_id, CPTRSIZE))(%ebx), %ebx		   ;\
-	cmpl	$0, %ebx						   ;\
+#define BRAND_URET_FROM_REG(rip_reg)					\
+	pushq	rip_reg			/* push the return address	*/
+
+/*
+ * The interrupt stack pointer we saved on entry to the BRAND_CALLBACK macro
+ * is currently pointing at the user return address (%eip).
+ */
+#define BRAND_URET_FROM_INTR_STACK()					\
+	movq	%gs:CPU_RTMP_RSP, %r15	/* grab the intr. stack pointer	*/ ;\
+	pushq	(%r15)			/* push the return address	*/
+
+#define	BRAND_CALLBACK(callback_id, push_userland_ret)			    \
+	movq	%rsp, %gs:CPU_RTMP_RSP	/* save the stack pointer	*/ ;\
+	movq	%r15, %gs:CPU_RTMP_R15	/* save %r15			*/ ;\
+	movq	%gs:CPU_THREAD, %r15	/* load the thread pointer	*/ ;\
+	movq	T_STACK(%r15), %rsp	/* switch to the kernel stack	*/ ;\
+	subq	$16, %rsp		/* save space for 2 pointers	*/ ;\
+	pushq	%r14			/* save %r14			*/ ;\
+	movq	%gs:CPU_RTMP_RSP, %r14					   ;\
+	movq	%r14, 8(%rsp)		/* stash the user stack pointer	*/ ;\
+	popq	%r14			/* restore %r14			*/ ;\
+	movq	T_LWP(%r15), %r15	/* load the lwp pointer		*/ ;\
+	pushq	%r15			/* push the lwp pointer		*/ ;\
+	movq	LWP_PROCP(%r15), %r15	/* load the proc pointer	*/ ;\
+	movq	P_BRAND(%r15), %r15	/* load the brand pointer	*/ ;\
+	movq	B_MACHOPS(%r15), %r15	/* load the machops pointer	*/ ;\
+	movq	_CONST(_MUL(callback_id, CPTRSIZE))(%r15), %r15		   ;\
+	cmpq	$0, %r15						   ;\
 	je	1f							   ;\
-	movl	%ebx, 12(%esp)		/* save callback to scratch	*/ ;\
-	movl	4(%esp), %ebx		/* grab the user %gs		*/ ;\
-	movw	%bx, %gs		/* restore the user %gs		*/ ;\
-	call	*12(%esp)		/* call callback in scratch	*/ ;\
-1:	movl	4(%esp), %ebx		/* restore user %gs (re-do if	*/ ;\
-	movw	%bx, %gs		/* branch due to no callback)	*/ ;\
-	movl	8(%esp), %ebx		/* restore user's %ebx		*/ ;\
-	addl	$16, %esp		/* restore stack ptr		*/
+	movq	%r15, 16(%rsp)		/* save the callback pointer	*/ ;\
+	push_userland_ret		/* push the return address	*/ ;\
+	movq	24(%rsp), %r15		/* load callback pointer	*/ ;\
+	INDIRECT_CALL_REG(r15)		/* call callback		*/ ;\
+1:	movq	%gs:CPU_RTMP_R15, %r15	/* restore %r15			*/ ;\
+	movq	%gs:CPU_RTMP_RSP, %rsp	/* restore the stack pointer	*/
 
 #define	MSTATE_TRANSITION(from, to)		\
-	pushl	$to;				\
-	pushl	$from;				\
-	call	syscall_mstate;			\
-	addl	$0x8, %esp
+	movl	$from, %edi;			\
+	movl	$to, %esi;			\
+	call	syscall_mstate
 
 /*
- * aka CPU_STATS_ADDQ(CPU, sys.syscall, 1)
- * This must be called with interrupts or preemption disabled.
+ * Check to see if a simple (direct) return is possible i.e.
+ *
+ *	if (t->t_post_sys_ast | syscalltrace |
+ *	    lwp->lwp_pcb.pcb_rupdate == 1)
+ *		do full version	;
+ *
+ * Preconditions:
+ * -	t is curthread
+ * Postconditions:
+ * -	condition code NE is set if post-sys is too complex
+ * -	rtmp is zeroed if it isn't (we rely on this!)
+ * -	ltmp is smashed
  */
-#define	CPU_STATS_SYS_SYSCALL_INC			\
-	addl	$1, %gs:CPU_STATS_SYS_SYSCALL;		\
-	adcl	$0, %gs:CPU_STATS_SYS_SYSCALL+4;
+#define	CHECK_POSTSYS_NE(t, ltmp, rtmp)			\
+	movq	T_LWP(t), ltmp;				\
+	movzbl	PCB_RUPDATE(ltmp), rtmp;		\
+	ORL_SYSCALLTRACE(rtmp);				\
+	orl	T_POST_SYS_AST(t), rtmp;		\
+	cmpl	$0, rtmp
 
-#if !defined(__lint)
+/*
+ * Fix up the lwp, thread, and eflags for a successful return
+ *
+ * Preconditions:
+ * -	zwreg contains zero
+ */
+#define	SIMPLE_SYSCALL_POSTSYS(t, lwp, zwreg)		\
+	movb	$LWP_USER, LWP_STATE(lwp);		\
+	movw	zwreg, T_SYSNUM(t);			\
+	andb	$_CONST(0xffff - PS_C), REGOFF_RFL(%rsp)
 
 /*
  * ASSERT(lwptoregs(lwp) == rp);
  *
- * this may seem obvious, but very odd things happen if this
+ * This may seem obvious, but very odd things happen if this
  * assertion is false
  *
  * Preconditions:
+ *	(%rsp is ready for normal call sequence)
+ * Postconditions (if assertion is true):
+ *	%r11 is smashed
+ *
+ * ASSERT(rp->r_cs == descnum)
+ *
+ * The code selector is written into the regs structure when the
+ * lwp stack is created.  We use this ASSERT to validate that
+ * the regs structure really matches how we came in.
+ *
+ * Preconditions:
+ *	(%rsp is ready for normal call sequence)
+ * Postconditions (if assertion is true):
  *	-none-
+ *
+ * ASSERT(lwp->lwp_pcb.pcb_rupdate == 0);
+ *
+ * If this is false, it meant that we returned to userland without
+ * updating the segment registers as we were supposed to.
+ *
+ * Note that we must ensure no interrupts or other traps intervene
+ * between entering privileged mode and performing the assertion,
+ * otherwise we may perform a context switch on the thread, which
+ * will end up setting pcb_rupdate to 1 again.
+ *
+ * ASSERT(%cr0 & CR0_TS == 0);
+ * Preconditions:
+ *	(%rsp is ready for normal call sequence)
  * Postconditions (if assertion is true):
- *	%esi and %edi are smashed
+ *      (specified register is clobbered)
+ *
+ * Check to make sure that we are returning to user land and that CR0.TS
+ * is not set. This is required as part of the eager FPU (see
+ * uts/intel/ia32/os/fpu.c for more information).
  */
+
 #if defined(DEBUG)
 
 __lwptoregs_msg:
 	.string	"syscall_asm.s:%d lwptoregs(%p) [%p] != rp [%p]"
 
-#define	ASSERT_LWPTOREGS(t, rp)				\
-	movl	T_LWP(t), %esi;				\
-	movl	LWP_REGS(%esi), %edi;			\
-	cmpl	rp, %edi;				\
+__codesel_msg:
+	.string	"syscall_asm.s:%d rp->r_cs [%ld] != %ld"
+
+__no_rupdate_msg:
+	.string	"syscall_asm.s:%d lwp %p, pcb_rupdate != 0"
+
+__bad_ts_msg:
+	.string "syscall_asm.s:%d CR0.TS set on user return"
+
+#define	ASSERT_LWPTOREGS(lwp, rp)			\
+	movq	LWP_REGS(lwp), %r11;			\
+	cmpq	rp, %r11;				\
 	je	7f;					\
-	pushl	rp;					\
-	pushl	%edi;					\
-	pushl	%esi;					\
-	pushl	$__LINE__;				\
-	pushl	$__lwptoregs_msg;			\
+	leaq	__lwptoregs_msg(%rip), %rdi;		\
+	movl	$__LINE__, %esi;			\
+	movq	lwp, %rdx;				\
+	movq	%r11, %rcx;				\
+	movq	rp, %r8;				\
+	xorl	%eax, %eax;				\
 	call	panic;					\
 7:
+
+#define	ASSERT_NO_RUPDATE_PENDING(lwp)			\
+	testb	$0x1, PCB_RUPDATE(lwp);			\
+	je	8f;					\
+	movq	lwp, %rdx;				\
+	leaq	__no_rupdate_msg(%rip), %rdi;		\
+	movl	$__LINE__, %esi;			\
+	xorl	%eax, %eax;				\
+	call	panic;					\
+8:
+
+#define	ASSERT_CR0TS_ZERO(reg)				\
+	movq	%cr0, reg;				\
+	testq	$CR0_TS, reg;				\
+	jz	9f;					\
+	leaq	__bad_ts_msg(%rip), %rdi;		\
+	movl	$__LINE__, %esi;			\
+	xorl	%eax, %eax;				\
+	call	panic;					\
+9:
+
 #else
-#define	ASSERT_LWPTOREGS(t, rp)
+#define	ASSERT_LWPTOREGS(lwp, rp)
+#define	ASSERT_NO_RUPDATE_PENDING(lwp)
+#define	ASSERT_CR0TS_ZERO(reg)
 #endif
 
-#endif	/* __lint */
-
 /*
- * This is an assembler version of this fragment:
- *
- * lwp->lwp_state = LWP_SYS;
- * lwp->lwp_ru.sysc++;
- * lwp->lwp_eosys = NORMALRETURN;
- * lwp->lwp_ap = argp;
- *
- * Preconditions:
- *	-none-
- * Postconditions:
- *	-none-
+ * Do the traptrace thing and restore any registers we used
+ * in situ.  Assumes that %rsp is pointing at the base of
+ * the struct regs, obviously ..
  */
-#define	SET_LWP(lwp, argp)				\
-	movb	$LWP_SYS, LWP_STATE(lwp);		\
-	addl	$1, LWP_RU_SYSC(lwp);			\
-	adcl	$0, LWP_RU_SYSC+4(lwp);			\
-	movb	$NORMALRETURN, LWP_EOSYS(lwp);		\
-	movl	argp, LWP_AP(lwp)
+#ifdef TRAPTRACE
+#define	SYSCALL_TRAPTRACE(ttype)				\
+	TRACE_PTR(%rdi, %rbx, %ebx, %rcx, ttype);		\
+	TRACE_REGS(%rdi, %rsp, %rbx, %rcx);			\
+	TRACE_STAMP(%rdi);	/* rdtsc clobbers %eax, %edx */	\
+	movq	REGOFF_RAX(%rsp), %rax;				\
+	movq	REGOFF_RBX(%rsp), %rbx;				\
+	movq	REGOFF_RCX(%rsp), %rcx;				\
+	movq	REGOFF_RDX(%rsp), %rdx;				\
+	movl	%eax, TTR_SYSNUM(%rdi);				\
+	movq	REGOFF_RDI(%rsp), %rdi
 
-/*
- * Set up the thread, lwp, find the handler, and copy
- * in the arguments from userland to the kernel stack.
- *
- * Preconditions:
- * -	%eax contains the syscall number
- * Postconditions:
- * -	%eax contains a pointer to the sysent structure
- * -	%ecx is zeroed
- * -	%esi, %edi are smashed
- * -	%esp is SYS_DROPped ready for the syscall
- */
-#define	SIMPLE_SYSCALL_PRESYS(t, faultlabel)		\
-	movl	T_LWP(t), %esi;				\
-	movw	%ax, T_SYSNUM(t);			\
-	subl	$SYS_DROP, %esp;			\
-	shll	$SYSENT_SIZE_SHIFT, %eax;			\
-	SET_LWP(%esi, %esp);				\
-	leal	sysent(%eax), %eax;			\
-	movzbl	SY_NARG(%eax), %ecx;			\
-	testl	%ecx, %ecx;				\
-	jz	4f;					\
-	movl	%esp, %edi;				\
-	movl	SYS_DROP + REGOFF_UESP(%esp), %esi;	\
-	movl	$faultlabel, T_LOFAULT(t);		\
-	addl	$4, %esi;				\
-	rep;						\
-	  smovl;					\
-	movl	%ecx, T_LOFAULT(t);			\
-4:
+#define	SYSCALL_TRAPTRACE32(ttype)				\
+	SYSCALL_TRAPTRACE(ttype);				\
+	/* paranoia: clean the top 32-bits of the registers */	\
+	orl	%eax, %eax;					\
+	orl	%ebx, %ebx;					\
+	orl	%ecx, %ecx;					\
+	orl	%edx, %edx;					\
+	orl	%edi, %edi
+#else	/* TRAPTRACE */
+#define	SYSCALL_TRAPTRACE(ttype)
+#define	SYSCALL_TRAPTRACE32(ttype)
+#endif	/* TRAPTRACE */
 
 /*
- * Check to see if a simple return is possible i.e.
+ * The 64-bit libc syscall wrapper does this:
  *
- *	if ((t->t_post_sys_ast | syscalltrace) != 0)
- *		do full version;
+ * fn(<args>)
+ * {
+ *	movq	%rcx, %r10	-- because syscall smashes %rcx
+ *	movl	$CODE, %eax
+ *	syscall
+ *	<error processing>
+ * }
  *
- * Preconditions:
- * -	t is curthread
- * Postconditions:
- * -	condition code NE is set if post-sys is too complex
- * -	rtmp is zeroed if it isn't (we rely on this!)
- */
-#define	CHECK_POSTSYS_NE(t, rtmp)			\
-	xorl	rtmp, rtmp;				\
-	ORL_SYSCALLTRACE(rtmp);				\
-	orl	T_POST_SYS_AST(t), rtmp;		\
-	cmpl	$0, rtmp
-
-/*
- * Fix up the lwp, thread, and eflags for a successful return
+ * Thus when we come into the kernel:
  *
- * Preconditions:
- * -	zwreg contains zero
- * Postconditions:
- * -	%esp has been unSYS_DROPped
- * -	%esi is smashed (points to lwp)
- */
-#define	SIMPLE_SYSCALL_POSTSYS(t, zwreg)		\
-	movl	T_LWP(t), %esi;				\
-	addl	$SYS_DROP, %esp;			\
-	movw	zwreg, T_SYSNUM(t);			\
-	movb	$LWP_USER, LWP_STATE(%esi);		\
-	andb	$_CONST(0xffff - PS_C), REGOFF_EFL(%esp)
-
-/*
- * System call handler.  This is the destination of both the call
- * gate (lcall 0x27) _and_ the interrupt gate (int 0x91). For our purposes,
- * there are two significant differences between an interrupt gate and a call
- * gate:
+ *	%rdi, %rsi, %rdx, %r10, %r8, %r9 contain first six args
+ *	%rax is the syscall number
+ *	%r12-%r15 contain caller state
  *
- * 1) An interrupt gate runs the handler with interrupts disabled, whereas a
- * call gate runs the handler with whatever EFLAGS settings were in effect at
- * the time of the call.
+ * The syscall instruction arranges that:
  *
- * 2) An interrupt gate pushes the contents of the EFLAGS register at the time
- * of the interrupt onto the stack, whereas a call gate does not.
+ *	%rcx contains the return %rip
+ *	%r11d contains bottom 32-bits of %rflags
+ *	%rflags is masked (as determined by the SFMASK msr)
+ *	%cs is set to UCS_SEL (as determined by the STAR msr)
+ *	%ss is set to UDS_SEL (as determined by the STAR msr)
+ *	%rip is set to sys_syscall (as determined by the LSTAR msr)
  *
- * Because we use the following code sequence to handle system calls made from
- * _both_ a call gate _and_ an interrupt gate, these two differences must be
- * respected. In regards to number 1) above, the handler must ensure that a sane
- * EFLAGS snapshot is stored on the stack so that when the kernel returns back
- * to the user via iret (which returns to user with the EFLAGS value saved on
- * the stack), interrupts are re-enabled.
+ * Or in other words, we have no registers available at all.
+ * Only swapgs can save us!
  *
- * In regards to number 2) above, the handler must always put a current snapshot
- * of EFLAGS onto the stack in the appropriate place. If we came in via an
- * interrupt gate, we will be clobbering the EFLAGS value that was pushed by
- * the interrupt gate. This is OK, as the only bit that was changed by the
- * hardware was the IE (interrupt enable) bit, which for an interrupt gate is
- * now off. If we were to do nothing, the stack would contain an EFLAGS with
- * IE off, resulting in us eventually returning back to the user with interrupts
- * disabled. The solution is to turn on the IE bit in the EFLAGS value saved on
- * the stack.
+ * Under the hypervisor, the swapgs has happened already.  However, the
+ * state of the world is very different from that we're familiar with.
  *
- * Another subtlety which deserves mention is the difference between the two
- * descriptors. The call gate descriptor is set to instruct the hardware to copy
- * one parameter from the user stack to the kernel stack, whereas the interrupt
- * gate descriptor doesn't use the parameter passing mechanism at all. The
- * kernel doesn't actually use the parameter that is copied by the hardware; the
- * only reason it does this is so that there is a space on the stack large
- * enough to hold an EFLAGS register value, which happens to be in the correct
- * place for use by iret when we go back to userland. How convenient.
+ * In particular, we have a stack structure like that for interrupt
+ * gates, except that the %cs and %ss registers are modified for reasons
+ * that are not entirely clear.  Critically, the %rcx/%r11 values do
+ * *not* reflect the usage of those registers under a 'real' syscall[1];
+ * the stack, therefore, looks like this:
  *
- * Stack frame description in syscall() and callees.
+ *	0x0(rsp)	potentially junk %rcx
+ *	0x8(rsp)	potentially junk %r11
+ *	0x10(rsp)	user %rip
+ *	0x18(rsp)	modified %cs
+ *	0x20(rsp)	user %rflags
+ *	0x28(rsp)	user %rsp
+ *	0x30(rsp)	modified %ss
  *
- * |------------|
- * | regs	| +(8*4)+4	registers
- * |------------|
- * | 8 args	| <- %esp	MAXSYSARGS (currently 8) arguments
- * |------------|
  *
+ * and before continuing on, we must load the %rip into %rcx and the
+ * %rflags into %r11.
+ *
+ * [1] They used to, and we relied on it, but this was broken in 3.1.1.
+ * Sigh.
  */
-#define	SYS_DROP	_CONST(_MUL(MAXSYSARGS, 4))
+#if defined(__xpv)
+#define	XPV_SYSCALL_PROD						\
+	movq	0x10(%rsp), %rcx;					\
+	movq	0x20(%rsp), %r11;					\
+	movq	0x28(%rsp), %rsp
+#else
+#define	XPV_SYSCALL_PROD /* nothing */
+#endif
 
-#if defined(__lint)
+	ENTRY_NP2(brand_sys_syscall,_allsyscalls)
+	SWAPGS				/* kernel gsbase */
+	XPV_SYSCALL_PROD
+	BRAND_CALLBACK(BRAND_CB_SYSCALL, BRAND_URET_FROM_REG(%rcx))
+	jmp	noprod_sys_syscall
 
-/*ARGSUSED*/
-void
-sys_call()
-{}
+	ALTENTRY(sys_syscall)
+	SWAPGS				/* kernel gsbase */
+	XPV_SYSCALL_PROD
 
-void
-_allsyscalls()
-{}
+noprod_sys_syscall:
+	movq	%r15, %gs:CPU_RTMP_R15
+	movq	%rsp, %gs:CPU_RTMP_RSP
 
-size_t _allsyscalls_size;
+	movq	%gs:CPU_THREAD, %r15
+	movq	T_STACK(%r15), %rsp	/* switch from user to kernel stack */
 
-#else	/* __lint */
+	ASSERT_UPCALL_MASK_IS_SET
 
-	ENTRY_NP2(brand_sys_call, _allsyscalls)
-	BRAND_CALLBACK(BRAND_CB_SYSCALL)
+	movl	$UCS_SEL, REGOFF_CS(%rsp)
+	movq	%rcx, REGOFF_RIP(%rsp)		/* syscall: %rip -> %rcx */
+	movq	%r11, REGOFF_RFL(%rsp)		/* syscall: %rfl -> %r11d */
+	movl	$UDS_SEL, REGOFF_SS(%rsp)
 
-	ALTENTRY(sys_call)
-	/ on entry	eax = system call number
+	movl	%eax, %eax			/* wrapper: sysc# -> %eax */
+	movq	%rdi, REGOFF_RDI(%rsp)
+	movq	%rsi, REGOFF_RSI(%rsp)
+	movq	%rdx, REGOFF_RDX(%rsp)
+	movq	%r10, REGOFF_RCX(%rsp)		/* wrapper: %rcx -> %r10 */
+	movq	%r10, %rcx			/* arg[3] for direct calls */
 
-	/ set up the stack to look as in reg.h
-	subl    $8, %esp        / pad the stack with ERRCODE and TRAPNO
+	movq	%r8, REGOFF_R8(%rsp)
+	movq	%r9, REGOFF_R9(%rsp)
+	movq	%rax, REGOFF_RAX(%rsp)
+	movq	%rbx, REGOFF_RBX(%rsp)
 
-	SYSCALL_PUSH
+	movq	%rbp, REGOFF_RBP(%rsp)
+	movq	%r10, REGOFF_R10(%rsp)
+	movq	%gs:CPU_RTMP_RSP, %r11
+	movq	%r11, REGOFF_RSP(%rsp)
+	movq	%r12, REGOFF_R12(%rsp)
 
-#ifdef TRAPTRACE
-	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_SYSCALL) / Uses labels "8" and "9"
-	TRACE_REGS(%edi, %esp, %ebx, %ecx)	/ Uses label "9"
-	pushl	%eax
-	TRACE_STAMP(%edi)		/ Clobbers %eax, %edx, uses "9"
-	popl	%eax
-	movl	%eax, TTR_SYSNUM(%edi)
+	movq	%r13, REGOFF_R13(%rsp)
+	movq	%r14, REGOFF_R14(%rsp)
+	movq	%gs:CPU_RTMP_R15, %r10
+	movq	%r10, REGOFF_R15(%rsp)
+	movq	$0, REGOFF_SAVFP(%rsp)
+	movq	$0, REGOFF_SAVPC(%rsp)
+
+	/*
+	 * Copy these registers here in case we end up stopped with
+	 * someone (like, say, /proc) messing with our register state.
+	 * We don't -restore- them unless we have to in update_sregs.
+	 *
+	 * Since userland -can't- change fsbase or gsbase directly,
+	 * and capturing them involves two serializing instructions,
+	 * we don't bother to capture them here.
+	 */
+	xorl	%ebx, %ebx
+	movw	%ds, %bx
+	movq	%rbx, REGOFF_DS(%rsp)
+	movw	%es, %bx
+	movq	%rbx, REGOFF_ES(%rsp)
+	movw	%fs, %bx
+	movq	%rbx, REGOFF_FS(%rsp)
+	movw	%gs, %bx
+	movq	%rbx, REGOFF_GS(%rsp)
+
+	/*
+	 * If we're trying to use TRAPTRACE though, I take that back: we're
+	 * probably debugging some problem in the SWAPGS logic and want to know
+	 * what the incoming gsbase was.
+	 *
+	 * Since we already did SWAPGS, record the KGSBASE.
+	 */
+#if defined(DEBUG) && defined(TRAPTRACE) && !defined(__xpv)
+	movl	$MSR_AMD_KGSBASE, %ecx
+	rdmsr
+	movl	%eax, REGOFF_GSBASE(%rsp)
+	movl	%edx, REGOFF_GSBASE+4(%rsp)
 #endif
 
-_watch_do_syscall:
-	movl	%esp, %ebp
+	/*
+	 * Machine state saved in the regs structure on the stack
+	 * First six args in %rdi, %rsi, %rdx, %rcx, %r8, %r9
+	 * %eax is the syscall number
+	 * %rsp is the thread's stack, %r15 is curthread
+	 * REG_RSP(%rsp) is the user's stack
+	 */
 
-	/ Interrupts may be enabled here, so we must make sure this thread
-	/ doesn't migrate off the CPU while it updates the CPU stats.
-	/
-	/ XXX This is only true if we got here via call gate thru the LDT for
-	/ old style syscalls. Perhaps this preempt++-- will go away soon?
-	movl	%gs:CPU_THREAD, %ebx
-	addb	$1, T_PREEMPT(%ebx)
-	CPU_STATS_SYS_SYSCALL_INC
-	subb	$1, T_PREEMPT(%ebx)
+	SYSCALL_TRAPTRACE($TT_SYSC64)
 
+	movq	%rsp, %rbp
+
+	movq	T_LWP(%r15), %r14
+	ASSERT_NO_RUPDATE_PENDING(%r14)
 	ENABLE_INTR_FLAGS
 
-	pushl	%eax				/ preserve across mstate call
 	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
-	popl	%eax
+	movl	REGOFF_RAX(%rsp), %eax	/* (%rax damaged by mstate call) */
 
-	movl	%gs:CPU_THREAD, %ebx
+	ASSERT_LWPTOREGS(%r14, %rsp)
 
-	ASSERT_LWPTOREGS(%ebx, %esp)
+	movb	$LWP_SYS, LWP_STATE(%r14)
+	incq	LWP_RU_SYSC(%r14)
+	movb	$NORMALRETURN, LWP_EOSYS(%r14)
 
-	CHECK_PRESYS_NE(%ebx, %eax)
-	jne	_full_syscall_presys
-	SIMPLE_SYSCALL_PRESYS(%ebx, _syscall_fault)
+	incq	%gs:CPU_STATS_SYS_SYSCALL
 
-_syslcall_call:
-	call	*SY_CALLC(%eax)
+	movw	%ax, T_SYSNUM(%r15)
+	movzbl	T_PRE_SYS(%r15), %ebx
+	ORL_SYSCALLTRACE(%ebx)
+	testl	%ebx, %ebx
+	jne	_syscall_pre
 
-_syslcall_done:
-	CHECK_POSTSYS_NE(%ebx, %ecx)
-	jne	_full_syscall_postsys
-	SIMPLE_SYSCALL_POSTSYS(%ebx, %cx)
-	movl	%eax, REGOFF_EAX(%esp)
-	movl	%edx, REGOFF_EDX(%esp)
+_syscall_invoke:
+	movq	REGOFF_RDI(%rbp), %rdi
+	movq	REGOFF_RSI(%rbp), %rsi
+	movq	REGOFF_RDX(%rbp), %rdx
+	movq	REGOFF_RCX(%rbp), %rcx
+	movq	REGOFF_R8(%rbp), %r8
+	movq	REGOFF_R9(%rbp), %r9
 
+	cmpl	$NSYSCALL, %eax
+	jae	_syscall_ill
+	shll	$SYSENT_SIZE_SHIFT, %eax
+	leaq	sysent(%rax), %rbx
+
+	movq	SY_CALLC(%rbx), %rax
+	INDIRECT_CALL_REG(rax)
+
+	movq	%rax, %r12
+	movq	%rdx, %r13
+
+	/*
+	 * If the handler returns two ints, then we need to split the
+	 * 64-bit return value into two 32-bit values.
+	 */
+	testw	$SE_32RVAL2, SY_FLAGS(%rbx)
+	je	5f
+	movq	%r12, %r13
+	shrq	$32, %r13	/* upper 32-bits into %edx */
+	movl	%r12d, %r12d	/* lower 32-bits into %eax */
+5:
+	/*
+	 * Optimistically assume that there's no post-syscall
+	 * work to do.  (This is to avoid having to call syscall_mstate()
+	 * with interrupts disabled)
+	 */
 	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
 
-	/
-	/ get back via iret
-	/
-	CLI(%edx)
-	jmp	sys_rtt_syscall
+	/*
+	 * We must protect ourselves from being descheduled here;
+	 * If we were, and we ended up on another cpu, or another
+	 * lwp got in ahead of us, it could change the segment
+	 * registers without us noticing before we return to userland.
+	 */
+	CLI(%r14)
+	CHECK_POSTSYS_NE(%r15, %r14, %ebx)
+	jne	_syscall_post
 
-_full_syscall_presys:
-	movl	T_LWP(%ebx), %esi
-	subl	$SYS_DROP, %esp
-	movb	$LWP_SYS, LWP_STATE(%esi)
-	pushl	%esp
-	pushl	%ebx
-	call	syscall_entry
-	addl	$8, %esp
-	jmp	_syslcall_call
+	/*
+	 * We need to protect ourselves against non-canonical return values
+	 * because Intel doesn't check for them on sysret (AMD does).  Canonical
+	 * addresses on current amd64 processors only use 48-bits for VAs; an
+	 * address is canonical if all upper bits (47-63) are identical. If we
+	 * find a non-canonical %rip, we opt to go through the full
+	 * _syscall_post path which takes us into an iretq which is not
+	 * susceptible to the same problems sysret is.
+	 *
+	 * We're checking for a canonical address by first doing an arithmetic
+	 * shift. This will fill in the remaining bits with the value of bit 63.
+	 * If the address were canonical, the register would now have either all
+	 * zeroes or all ones in it. Therefore we add one (inducing overflow)
+	 * and compare against 1. A canonical address will either be zero or one
+	 * at this point, hence the use of ja.
+	 *
+	 * At this point, r12 and r13 have the return value so we can't use
+	 * those registers.
+	 */
+	movq	REGOFF_RIP(%rsp), %rcx
+	sarq	$47, %rcx
+	incq	%rcx
+	cmpq	$1, %rcx
+	ja	_syscall_post
 
-_full_syscall_postsys:
-	addl	$SYS_DROP, %esp
-	pushl	%edx
-	pushl	%eax
-	pushl	%ebx
-	call	syscall_exit
-	addl	$12, %esp
+
+	SIMPLE_SYSCALL_POSTSYS(%r15, %r14, %bx)
+
+	movq	%r12, REGOFF_RAX(%rsp)
+	movq	%r13, REGOFF_RDX(%rsp)
+
+	/*
+	 * Clobber %r11 as we check CR0.TS.
+	 */
+	ASSERT_CR0TS_ZERO(%r11)
+
+	/*
+	 * Unlike other cases, because we need to restore the user stack pointer
+	 * before exiting the kernel we must clear the microarch state before
+	 * getting here. This should be safe because it means that the only
+	 * values on the bus after this are based on the user's registers and
+	 * potentially the addresses where we stored them. Given the constraints
+	 * of sysret, that's how it has to be.
+	 */
+	call	x86_md_clear
+
+	/*
+	 * To get back to userland, we need the return %rip in %rcx and
+	 * the return %rfl in %r11d.  The sysretq instruction also arranges
+	 * to fix up %cs and %ss; everything else is our responsibility.
+	 */
+	movq	REGOFF_RDI(%rsp), %rdi
+	movq	REGOFF_RSI(%rsp), %rsi
+	movq	REGOFF_RDX(%rsp), %rdx
+	/* %rcx used to restore %rip value */
+
+	movq	REGOFF_R8(%rsp), %r8
+	movq	REGOFF_R9(%rsp), %r9
+	movq	REGOFF_RAX(%rsp), %rax
+	movq	REGOFF_RBX(%rsp), %rbx
+
+	movq	REGOFF_RBP(%rsp), %rbp
+	movq	REGOFF_R10(%rsp), %r10
+	/* %r11 used to restore %rfl value */
+	movq	REGOFF_R12(%rsp), %r12
+
+	movq	REGOFF_R13(%rsp), %r13
+	movq	REGOFF_R14(%rsp), %r14
+	movq	REGOFF_R15(%rsp), %r15
+
+	movq	REGOFF_RIP(%rsp), %rcx
+	movl	REGOFF_RFL(%rsp), %r11d
+
+#if defined(__xpv)
+	addq	$REGOFF_RIP, %rsp
+#else
+	movq	REGOFF_RSP(%rsp), %rsp
+#endif
+
+        /*
+         * There can be no instructions between the ALTENTRY below and
+	 * SYSRET or we could end up breaking brand support. See label usage
+         * in sn1_brand_syscall_callback for an example.
+         */
+	ASSERT_UPCALL_MASK_IS_SET
+#if defined(__xpv)
+	SYSRETQ
+        ALTENTRY(nopop_sys_syscall_swapgs_sysretq)
+
+	/*
+	 * We can only get here after executing a brand syscall
+	 * interposition callback handler and simply need to
+	 * "sysretq" back to userland. On the hypervisor this
+	 * involves the iret hypercall which requires us to construct
+	 * just enough of the stack needed for the hypercall.
+	 * (rip, cs, rflags, rsp, ss).
+	 */
+	movq    %rsp, %gs:CPU_RTMP_RSP		/* save user's rsp */
+	movq	%gs:CPU_THREAD, %r11
+	movq	T_STACK(%r11), %rsp
+
+	movq	%rcx, REGOFF_RIP(%rsp)
+	movl	$UCS_SEL, REGOFF_CS(%rsp)
+	movq	%gs:CPU_RTMP_RSP, %r11
+	movq	%r11, REGOFF_RSP(%rsp)
+	pushfq
+	popq	%r11				/* hypercall enables ints */
+	movq	%r11, REGOFF_RFL(%rsp)
+	movl	$UDS_SEL, REGOFF_SS(%rsp)
+	addq	$REGOFF_RIP, %rsp
+	/*
+	 * XXPV: see comment in SYSRETQ definition for future optimization
+	 *       we could take.
+	 */
+	ASSERT_UPCALL_MASK_IS_SET
+	SYSRETQ
+#else
+        ALTENTRY(nopop_sys_syscall_swapgs_sysretq)
+	jmp	tr_sysretq
+#endif
+        /*NOTREACHED*/
+        SET_SIZE(nopop_sys_syscall_swapgs_sysretq)
+
+_syscall_pre:
+	call	pre_syscall
+	movl	%eax, %r12d
+	testl	%eax, %eax
+	jne	_syscall_post_call
+	/*
+	 * Didn't abort, so reload the syscall args and invoke the handler.
+	 */
+	movzwl	T_SYSNUM(%r15), %eax
+	jmp	_syscall_invoke
+
+_syscall_ill:
+	call	nosys
+	movq	%rax, %r12
+	movq	%rdx, %r13
+	jmp	_syscall_post_call
+
+_syscall_post:
+	STI
+	/*
+	 * Sigh, our optimism wasn't justified, put it back to LMS_SYSTEM
+	 * so that we can account for the extra work it takes us to finish.
+	 */
+	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
+_syscall_post_call:
+	movq	%r12, %rdi
+	movq	%r13, %rsi
+	call	post_syscall
 	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
 	jmp	_sys_rtt
+	SET_SIZE(sys_syscall)
+	SET_SIZE(brand_sys_syscall)
 
-_syscall_fault:
-	push	$0xe			/ EFAULT
-	call	set_errno
-	addl	$4, %esp
-	xorl	%eax, %eax		/ fake syscall_err()
-	xorl	%edx, %edx
-	jmp	_syslcall_done
-	SET_SIZE(sys_call)
-	SET_SIZE(brand_sys_call)
+	ENTRY_NP(brand_sys_syscall32)
+	SWAPGS				/* kernel gsbase */
+	XPV_TRAP_POP
+	BRAND_CALLBACK(BRAND_CB_SYSCALL32, BRAND_URET_FROM_REG(%rcx))
+	jmp	nopop_sys_syscall32
 
-#endif	/* __lint */
+	ALTENTRY(sys_syscall32)
+	SWAPGS				/* kernel gsbase */
+	XPV_TRAP_POP
 
+nopop_sys_syscall32:
+	movl	%esp, %r10d
+	movq	%gs:CPU_THREAD, %r15
+	movq	T_STACK(%r15), %rsp
+	movl	%eax, %eax
+
+	movl	$U32CS_SEL, REGOFF_CS(%rsp)
+	movl	%ecx, REGOFF_RIP(%rsp)		/* syscall: %rip -> %rcx */
+	movq	%r11, REGOFF_RFL(%rsp)		/* syscall: %rfl -> %r11d */
+	movq	%r10, REGOFF_RSP(%rsp)
+	movl	$UDS_SEL, REGOFF_SS(%rsp)
+
+_syscall32_save:
+	movl	%edi, REGOFF_RDI(%rsp)
+	movl	%esi, REGOFF_RSI(%rsp)
+	movl	%ebp, REGOFF_RBP(%rsp)
+	movl	%ebx, REGOFF_RBX(%rsp)
+	movl	%edx, REGOFF_RDX(%rsp)
+	movl	%ecx, REGOFF_RCX(%rsp)
+	movl	%eax, REGOFF_RAX(%rsp)		/* wrapper: sysc# -> %eax */
+	movq	$0, REGOFF_SAVFP(%rsp)
+	movq	$0, REGOFF_SAVPC(%rsp)
+
+	/*
+	 * Copy these registers here in case we end up stopped with
+	 * someone (like, say, /proc) messing with our register state.
+	 * We don't -restore- them unless we have to in update_sregs.
+	 *
+	 * Since userland -can't- change fsbase or gsbase directly,
+	 * we don't bother to capture them here.
+	 */
+	xorl	%ebx, %ebx
+	movw	%ds, %bx
+	movq	%rbx, REGOFF_DS(%rsp)
+	movw	%es, %bx
+	movq	%rbx, REGOFF_ES(%rsp)
+	movw	%fs, %bx
+	movq	%rbx, REGOFF_FS(%rsp)
+	movw	%gs, %bx
+	movq	%rbx, REGOFF_GS(%rsp)
+
+	/*
+	 * If we're trying to use TRAPTRACE though, I take that back: we're
+	 * probably debugging some problem in the SWAPGS logic and want to know
+	 * what the incoming gsbase was.
+	 *
+	 * Since we already did SWAPGS, record the KGSBASE.
+	 */
+#if defined(DEBUG) && defined(TRAPTRACE) && !defined(__xpv)
+	movl	$MSR_AMD_KGSBASE, %ecx
+	rdmsr
+	movl	%eax, REGOFF_GSBASE(%rsp)
+	movl	%edx, REGOFF_GSBASE+4(%rsp)
+#endif
+
+	/*
+	 * Application state saved in the regs structure on the stack
+	 * %eax is the syscall number
+	 * %rsp is the thread's stack, %r15 is curthread
+	 * REG_RSP(%rsp) is the user's stack
+	 */
+
+	SYSCALL_TRAPTRACE32($TT_SYSC)
+
+	movq	%rsp, %rbp
+
+	movq	T_LWP(%r15), %r14
+	ASSERT_NO_RUPDATE_PENDING(%r14)
+
+	ENABLE_INTR_FLAGS
+
+	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
+	movl	REGOFF_RAX(%rsp), %eax	/* (%rax damaged by mstate call) */
+
+	ASSERT_LWPTOREGS(%r14, %rsp)
+
+	incq	 %gs:CPU_STATS_SYS_SYSCALL
+
+	/*
+	 * Make some space for MAXSYSARGS (currently 8) 32-bit args placed
+	 * into 64-bit (long) arg slots, maintaining 16 byte alignment.  Or
+	 * more succinctly:
+	 *
+	 *	SA(MAXSYSARGS * sizeof (long)) == 64
+	 */
+#define	SYS_DROP	64			/* drop for args */
+	subq	$SYS_DROP, %rsp
+	movb	$LWP_SYS, LWP_STATE(%r14)
+	movq	%r15, %rdi
+	movq	%rsp, %rsi
+	call	syscall_entry
+
+	/*
+	 * Fetch the arguments copied onto the kernel stack and put
+	 * them in the right registers to invoke a C-style syscall handler.
+	 * %rax contains the handler address.
+	 *
+	 * Ideas for making all this go faster of course include simply
+	 * forcibly fetching 6 arguments from the user stack under lofault
+	 * protection, reverting to copyin_args only when watchpoints
+	 * are in effect.
+	 *
+	 * (If we do this, make sure that exec and libthread leave
+	 * enough space at the top of the stack to ensure that we'll
+	 * never do a fetch from an invalid page.)
+	 *
+	 * Lots of ideas here, but they won't really help with bringup B-)
+	 * Correctness can't wait, performance can wait a little longer ..
+	 */
+
+	movq	%rax, %rbx
+	movl	0(%rsp), %edi
+	movl	8(%rsp), %esi
+	movl	0x10(%rsp), %edx
+	movl	0x18(%rsp), %ecx
+	movl	0x20(%rsp), %r8d
+	movl	0x28(%rsp), %r9d
+
+	movq	SY_CALLC(%rbx), %rax
+	INDIRECT_CALL_REG(rax)
+
+	movq	%rbp, %rsp	/* pop the args */
+
+	/*
+	 * amd64 syscall handlers -always- return a 64-bit value in %rax.
+	 * On the 32-bit kernel, they always return that value in %eax:%edx
+	 * as required by the 32-bit ABI.
+	 *
+	 * Simulate the same behaviour by unconditionally splitting the
+	 * return value in the same way.
+	 */
+	movq	%rax, %r13
+	shrq	$32, %r13	/* upper 32-bits into %edx */
+	movl	%eax, %r12d	/* lower 32-bits into %eax */
+
+	/*
+	 * Optimistically assume that there's no post-syscall
+	 * work to do.  (This is to avoid having to call syscall_mstate()
+	 * with interrupts disabled)
+	 */
+	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
+
+	/*
+	 * We must protect ourselves from being descheduled here;
+	 * If we were, and we ended up on another cpu, or another
+	 * lwp got in ahead of us, it could change the segment
+	 * registers without us noticing before we return to userland.
+	 */
+	CLI(%r14)
+	CHECK_POSTSYS_NE(%r15, %r14, %ebx)
+	jne	_full_syscall_postsys32
+	SIMPLE_SYSCALL_POSTSYS(%r15, %r14, %bx)
+
+	/*
+	 * Clobber %r11 as we check CR0.TS.
+	 */
+	ASSERT_CR0TS_ZERO(%r11)
+
+	/*
+	 * Unlike other cases, because we need to restore the user stack pointer
+	 * before exiting the kernel we must clear the microarch state before
+	 * getting here. This should be safe because it means that the only
+	 * values on the bus after this are based on the user's registers and
+	 * potentially the addresses where we stored them. Given the constraints
+	 * of sysret, that's how it has to be.
+	 */
+	call	x86_md_clear
+
+	/*
+	 * To get back to userland, we need to put the return %rip in %rcx and
+	 * the return %rfl in %r11d.  The sysret instruction also arranges
+	 * to fix up %cs and %ss; everything else is our responsibility.
+	 */
+
+	movl	%r12d, %eax			/* %eax: rval1 */
+	movl	REGOFF_RBX(%rsp), %ebx
+	/* %ecx used for return pointer */
+	movl	%r13d, %edx			/* %edx: rval2 */
+	movl	REGOFF_RBP(%rsp), %ebp
+	movl	REGOFF_RSI(%rsp), %esi
+	movl	REGOFF_RDI(%rsp), %edi
+
+	movl	REGOFF_RFL(%rsp), %r11d		/* %r11 -> eflags */
+	movl	REGOFF_RIP(%rsp), %ecx		/* %ecx -> %eip */
+	movl	REGOFF_RSP(%rsp), %esp
+
+	ASSERT_UPCALL_MASK_IS_SET
+        ALTENTRY(nopop_sys_syscall32_swapgs_sysretl)
+	jmp	tr_sysretl
+        SET_SIZE(nopop_sys_syscall32_swapgs_sysretl)
+	/*NOTREACHED*/
+
+_full_syscall_postsys32:
+	STI
+	/*
+	 * Sigh, our optimism wasn't justified, put it back to LMS_SYSTEM
+	 * so that we can account for the extra work it takes us to finish.
+	 */
+	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
+	movq	%r15, %rdi
+	movq	%r12, %rsi			/* rval1 - %eax */
+	movq	%r13, %rdx			/* rval2 - %edx */
+	call	syscall_exit
+	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
+	jmp	_sys_rtt
+	SET_SIZE(sys_syscall32)
+	SET_SIZE(brand_sys_syscall32)
+
 /*
  * System call handler via the sysenter instruction
+ * Used only for 32-bit system calls on the 64-bit kernel.
  *
- * Here's how syscall entry usually works (see sys_call for details).
- *
- * There, the caller (lcall or int) in userland has arranged that:
- *
- * -	%eax contains the syscall number
- * -	the user stack contains the args to the syscall
- *
- * Normally the lcall instruction into the call gate causes the processor
- * to push %ss, %esp, <top-of-stack>, %cs, %eip onto the kernel stack.
- * The sys_call handler then leaves space for r_trapno and r_err, and
- * pusha's {%eax, %ecx, %edx, %ebx, %esp, %ebp, %esi, %edi}, followed
- * by %ds, %es, %fs and %gs to capture a 'struct regs' on the stack.
- * Then the kernel sets %ds, %es and %gs to kernel selectors, and finally
- * extracts %efl and puts it into r_efl (which happens to live at the offset
- * that <top-of-stack> was copied into). Note that the value in r_efl has
- * the IF (interrupt enable) flag turned on. (The int instruction into the
- * interrupt gate does essentially the same thing, only instead of
- * <top-of-stack> we get eflags - see comment above.)
- *
- * In the sysenter case, things are a lot more primitive.
- *
  * The caller in userland has arranged that:
  *
  * -	%eax contains the syscall number
@@ -491,149 +965,336 @@
  * -	%edx contains the return %eip
  * -	the user stack contains the args to the syscall
  *
- * e.g.
- *	<args on the stack>
- *	mov	$SYS_callnum, %eax
- *	mov	$1f, %edx	/ return %eip
- *	mov	%esp, %ecx	/ return %esp
- *	sysenter
- * 1:
- *
  * Hardware and (privileged) initialization code have arranged that by
  * the time the sysenter instructions completes:
  *
- * - %eip is pointing to sys_sysenter (below).
+ * - %rip is pointing to sys_sysenter (below).
  * - %cs and %ss are set to kernel text and stack (data) selectors.
- * - %esp is pointing at the lwp's stack
- * - Interrupts have been disabled.
+ * - %rsp is pointing at the lwp's stack
+ * - interrupts have been disabled.
  *
- * The task for the sysenter handler is:
+ * Note that we are unable to return both "rvals" to userland with
+ * this call, as %edx is used by the sysexit instruction.
  *
- * -	recreate the same regs structure on the stack and the same
- *	kernel state as if we'd come in on an lcall
- * -	do the normal work of a syscall
- * -	execute the system call epilogue, use sysexit to return to userland.
- *
- * Note that we are unable to return both "rvals" to userland with this
- * call, as %edx is used by the sysexit instruction.
- *
  * One final complication in this routine is its interaction with
- * single-stepping in a debugger.  For most of the system call mechanisms,
- * the CPU automatically clears the single-step flag before we enter the
- * kernel.  The sysenter mechanism does not clear the flag, so a user
- * single-stepping through a libc routine may suddenly find themself
- * single-stepping through the kernel.  To detect this, kmdb compares the
- * trap %pc to the [brand_]sys_enter addresses on each single-step trap.
- * If it finds that we have single-stepped to a sysenter entry point, it
- * explicitly clears the flag and executes the sys_sysenter routine.
+ * single-stepping in a debugger.  For most of the system call mechanisms, the
+ * CPU automatically clears the single-step flag before we enter the kernel.
+ * The sysenter mechanism does not clear the flag, so a user single-stepping
+ * through a libc routine may suddenly find themself single-stepping through the
+ * kernel.  To detect this, kmdb and trap() both compare the trap %pc to the
+ * [brand_]sys_enter addresses on each single-step trap.  If it finds that we
+ * have single-stepped to a sysenter entry point, it explicitly clears the flag
+ * and executes the sys_sysenter routine.
  *
- * One final complication in this final complication is the fact that we
- * have two different entry points for sysenter: brand_sys_sysenter and
- * sys_sysenter.  If we enter at brand_sys_sysenter and start single-stepping
- * through the kernel with kmdb, we will eventually hit the instruction at
- * sys_sysenter.  kmdb cannot distinguish between that valid single-step
- * and the undesirable one mentioned above.  To avoid this situation, we
- * simply add a jump over the instruction at sys_sysenter to make it
- * impossible to single-step to it.
+ * One final complication in this final complication is the fact that we have
+ * two different entry points for sysenter: brand_sys_sysenter and sys_sysenter.
+ * If we enter at brand_sys_sysenter and start single-stepping through the
+ * kernel with kmdb, we will eventually hit the instruction at sys_sysenter.
+ * kmdb cannot distinguish between that valid single-step and the undesirable
+ * one mentioned above.  To avoid this situation, we simply add a jump over the
+ * instruction at sys_sysenter to make it impossible to single-step to it.
  */
-#if defined(__lint)
 
-void
-sys_sysenter()
-{}
-
-#else	/* __lint */
-
 	ENTRY_NP(brand_sys_sysenter)
-	pushl	%edx
-	BRAND_CALLBACK(BRAND_CB_SYSENTER)
-	popl	%edx
+	SWAPGS				/* kernel gsbase */
+	ALTENTRY(_brand_sys_sysenter_post_swapgs)
+
+	BRAND_CALLBACK(BRAND_CB_SYSENTER, BRAND_URET_FROM_REG(%rdx))
 	/*
 	 * Jump over sys_sysenter to allow single-stepping as described
 	 * above.
 	 */
-	ja	1f
+	jmp	_sys_sysenter_post_swapgs
 
 	ALTENTRY(sys_sysenter)
-	nop
-1:
-	/
-	/ do what the call gate would've done to the stack ..
-	/
-	pushl	$UDS_SEL	/ (really %ss, but it's the same ..)
-	pushl	%ecx		/ userland makes this a copy of %esp
-	pushfl
-	orl	$PS_IE, (%esp)	/ turn interrupts on when we return to user
-	pushl	$UCS_SEL
-	pushl	%edx		/ userland makes this a copy of %eip
-	/
-	/ done.  finish building the stack frame
-	/
-	subl	$8, %esp	/ leave space for ERR and TRAPNO
+	SWAPGS				/* kernel gsbase */
+	ALTENTRY(_sys_sysenter_post_swapgs)
 
-	SYSENTER_PUSH
+	movq	%gs:CPU_THREAD, %r15
 
-#ifdef TRAPTRACE
-	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_SYSENTER)	/ uses labels 8 and 9
-	TRACE_REGS(%edi, %esp, %ebx, %ecx)		/ uses label 9
-	pushl	%eax
-	TRACE_STAMP(%edi)		/ clobbers %eax, %edx, uses label 9
-	popl	%eax
-	movl	%eax, TTR_SYSNUM(%edi)
+	movl	$U32CS_SEL, REGOFF_CS(%rsp)
+	movl	%ecx, REGOFF_RSP(%rsp)		/* wrapper: %esp -> %ecx */
+	movl	%edx, REGOFF_RIP(%rsp)		/* wrapper: %eip -> %edx */
+	/*
+	 * NOTE: none of the instructions that run before we get here should
+	 * clobber bits in (R)FLAGS! This includes the kpti trampoline.
+	 */
+	pushfq
+	popq	%r10
+	movl	$UDS_SEL, REGOFF_SS(%rsp)
+
+	/*
+	 * Set the interrupt flag before storing the flags to the
+	 * flags image on the stack so we can return to user with
+	 * interrupts enabled if we return via sys_rtt_syscall32
+	 */
+	orq	$PS_IE, %r10
+	movq	%r10, REGOFF_RFL(%rsp)
+
+	movl	%edi, REGOFF_RDI(%rsp)
+	movl	%esi, REGOFF_RSI(%rsp)
+	movl	%ebp, REGOFF_RBP(%rsp)
+	movl	%ebx, REGOFF_RBX(%rsp)
+	movl	%edx, REGOFF_RDX(%rsp)
+	movl	%ecx, REGOFF_RCX(%rsp)
+	movl	%eax, REGOFF_RAX(%rsp)		/* wrapper: sysc# -> %eax */
+	movq	$0, REGOFF_SAVFP(%rsp)
+	movq	$0, REGOFF_SAVPC(%rsp)
+
+	/*
+	 * Copy these registers here in case we end up stopped with
+	 * someone (like, say, /proc) messing with our register state.
+	 * We don't -restore- them unless we have to in update_sregs.
+	 *
+	 * Since userland -can't- change fsbase or gsbase directly,
+	 * we don't bother to capture them here.
+	 */
+	xorl	%ebx, %ebx
+	movw	%ds, %bx
+	movq	%rbx, REGOFF_DS(%rsp)
+	movw	%es, %bx
+	movq	%rbx, REGOFF_ES(%rsp)
+	movw	%fs, %bx
+	movq	%rbx, REGOFF_FS(%rsp)
+	movw	%gs, %bx
+	movq	%rbx, REGOFF_GS(%rsp)
+
+	/*
+	 * If we're trying to use TRAPTRACE though, I take that back: we're
+	 * probably debugging some problem in the SWAPGS logic and want to know
+	 * what the incoming gsbase was.
+	 *
+	 * Since we already did SWAPGS, record the KGSBASE.
+	 */
+#if defined(DEBUG) && defined(TRAPTRACE) && !defined(__xpv)
+	movl	$MSR_AMD_KGSBASE, %ecx
+	rdmsr
+	movl	%eax, REGOFF_GSBASE(%rsp)
+	movl	%edx, REGOFF_GSBASE+4(%rsp)
 #endif
-	movl	%esp, %ebp
 
-	CPU_STATS_SYS_SYSCALL_INC
+	/*
+	 * Application state saved in the regs structure on the stack
+	 * %eax is the syscall number
+	 * %rsp is the thread's stack, %r15 is curthread
+	 * REG_RSP(%rsp) is the user's stack
+	 */
 
+	SYSCALL_TRAPTRACE($TT_SYSENTER)
+
+	movq	%rsp, %rbp
+
+	movq	T_LWP(%r15), %r14
+	ASSERT_NO_RUPDATE_PENDING(%r14)
+
 	ENABLE_INTR_FLAGS
 
-	pushl	%eax				/ preserve across mstate call
+	/*
+	 * Catch 64-bit process trying to issue sysenter instruction
+	 * on Nocona based systems.
+	 */
+	movq	LWP_PROCP(%r14), %rax
+	cmpq	$DATAMODEL_ILP32, P_MODEL(%rax)
+	je	7f
+
+	/*
+	 * For a non-32-bit process, simulate a #ud, since that's what
+	 * native hardware does.  The traptrace entry (above) will
+	 * let you know what really happened.
+	 */
+	movq	$T_ILLINST, REGOFF_TRAPNO(%rsp)
+	movq	REGOFF_CS(%rsp), %rdi
+	movq	%rdi, REGOFF_ERR(%rsp)
+	movq	%rsp, %rdi
+	movq	REGOFF_RIP(%rsp), %rsi
+	movl	%gs:CPU_ID, %edx
+	call	trap
+	jmp	_sys_rtt
+7:
+
 	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
-	popl	%eax
+	movl	REGOFF_RAX(%rsp), %eax	/* (%rax damaged by mstate calls) */
 
-	movl	%gs:CPU_THREAD, %ebx
+	ASSERT_LWPTOREGS(%r14, %rsp)
 
-	ASSERT_LWPTOREGS(%ebx, %esp)
+	incq	%gs:CPU_STATS_SYS_SYSCALL
 
-	CHECK_PRESYS_NE(%ebx, %eax)
-	jne	_full_syscall_presys
-	SIMPLE_SYSCALL_PRESYS(%ebx, _syscall_fault)
+	/*
+	 * Make some space for MAXSYSARGS (currently 8) 32-bit args
+	 * placed into 64-bit (long) arg slots, plus one 64-bit
+	 * (long) arg count, maintaining 16 byte alignment.
+	 */
+	subq	$SYS_DROP, %rsp
+	movb	$LWP_SYS, LWP_STATE(%r14)
+	movq	%r15, %rdi
+	movq	%rsp, %rsi
+	call	syscall_entry
 
-_sysenter_call:
-	call	*SY_CALLC(%eax)
+	/*
+	 * Fetch the arguments copied onto the kernel stack and put
+	 * them in the right registers to invoke a C-style syscall handler.
+	 * %rax contains the handler address.
+	 */
+	movq	%rax, %rbx
+	movl	0(%rsp), %edi
+	movl	8(%rsp), %esi
+	movl	0x10(%rsp), %edx
+	movl	0x18(%rsp), %ecx
+	movl	0x20(%rsp), %r8d
+	movl	0x28(%rsp), %r9d
 
-_sysenter_done:
-	CHECK_POSTSYS_NE(%ebx, %ecx)
-	jne	_full_syscall_postsys
-	SIMPLE_SYSCALL_POSTSYS(%ebx, %cx)
-	/
-	/ sysexit uses %edx to restore %eip, so we can't use it
-	/ to return a value, sigh.
-	/
-	movl	%eax, REGOFF_EAX(%esp)
-	/ movl	%edx, REGOFF_EDX(%esp)
+	movq	SY_CALLC(%rbx), %rax
+	INDIRECT_CALL_REG(rax)
 
-	/ Interrupts will be turned on by the 'sti' executed just before
-	/ sysexit. The following ensures that restoring the user's EFLAGS
-	/ doesn't enable interrupts too soon.
-	andl	$_BITNOT(PS_IE), REGOFF_EFL(%esp)
+	movq	%rbp, %rsp	/* pop the args */
 
+	/*
+	 * amd64 syscall handlers -always- return a 64-bit value in %rax.
+	 * On the 32-bit kernel, the always return that value in %eax:%edx
+	 * as required by the 32-bit ABI.
+	 *
+	 * Simulate the same behaviour by unconditionally splitting the
+	 * return value in the same way.
+	 */
+	movq	%rax, %r13
+	shrq	$32, %r13	/* upper 32-bits into %edx */
+	movl	%eax, %r12d	/* lower 32-bits into %eax */
+
+	/*
+	 * Optimistically assume that there's no post-syscall
+	 * work to do.  (This is to avoid having to call syscall_mstate()
+	 * with interrupts disabled)
+	 */
 	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
 
+	/*
+	 * We must protect ourselves from being descheduled here;
+	 * If we were, and we ended up on another cpu, or another
+	 * lwp got int ahead of us, it could change the segment
+	 * registers without us noticing before we return to userland.
+	 *
+	 * This cli is undone in the tr_sysexit trampoline code.
+	 */
 	cli
+	CHECK_POSTSYS_NE(%r15, %r14, %ebx)
+	jne	_full_syscall_postsys32
+	SIMPLE_SYSCALL_POSTSYS(%r15, %r14, %bx)
 
-	SYSCALL_POP
+	/*
+	 * To get back to userland, load up the 32-bit registers and
+	 * sysexit back where we came from.
+	 */
 
-	popl	%edx			/ sysexit: %edx -> %eip
-	addl	$4, %esp		/ get CS off the stack
-	popfl				/ EFL
-	popl	%ecx			/ sysexit: %ecx -> %esp
-	sti
-	sysexit
+	/*
+	 * Interrupts will be turned on by the 'sti' executed just before
+	 * sysexit.  The following ensures that restoring the user's rflags
+	 * doesn't enable interrupts too soon.
+	 */
+	andq	$_BITNOT(PS_IE), REGOFF_RFL(%rsp)
+
+	/*
+	 * Clobber %r11 as we check CR0.TS.
+	 */
+	ASSERT_CR0TS_ZERO(%r11)
+
+	/*
+	 * (There's no point in loading up %edx because the sysexit
+	 * mechanism smashes it.)
+	 */
+	movl	%r12d, %eax
+	movl	REGOFF_RBX(%rsp), %ebx
+	movl	REGOFF_RBP(%rsp), %ebp
+	movl	REGOFF_RSI(%rsp), %esi
+	movl	REGOFF_RDI(%rsp), %edi
+
+	movl	REGOFF_RIP(%rsp), %edx	/* sysexit: %edx -> %eip */
+	pushq	REGOFF_RFL(%rsp)
+	popfq
+	movl	REGOFF_RSP(%rsp), %ecx	/* sysexit: %ecx -> %esp */
+        ALTENTRY(sys_sysenter_swapgs_sysexit)
+	call	x86_md_clear
+	jmp	tr_sysexit
+	SET_SIZE(sys_sysenter_swapgs_sysexit)
 	SET_SIZE(sys_sysenter)
+	SET_SIZE(_sys_sysenter_post_swapgs)
 	SET_SIZE(brand_sys_sysenter)
 
 /*
+ * This is the destination of the "int $T_SYSCALLINT" interrupt gate, used by
+ * the generic i386 libc to do system calls. We do a small amount of setup
+ * before jumping into the existing sys_syscall32 path.
+ */
+
+	ENTRY_NP(brand_sys_syscall_int)
+	SWAPGS				/* kernel gsbase */
+	XPV_TRAP_POP
+	call	smap_enable
+	BRAND_CALLBACK(BRAND_CB_INT91, BRAND_URET_FROM_INTR_STACK())
+	jmp	nopop_syscall_int
+
+	ALTENTRY(sys_syscall_int)
+	SWAPGS				/* kernel gsbase */
+	XPV_TRAP_POP
+	call	smap_enable
+
+nopop_syscall_int:
+	movq	%gs:CPU_THREAD, %r15
+	movq	T_STACK(%r15), %rsp
+	movl	%eax, %eax
+	/*
+	 * Set t_post_sys on this thread to force ourselves out via the slow
+	 * path. It might be possible at some later date to optimize this out
+	 * and use a faster return mechanism.
+	 */
+	movb	$1, T_POST_SYS(%r15)
+	CLEAN_CS
+	jmp	_syscall32_save
+	/*
+	 * There should be no instructions between this label and SWAPGS/IRET
+	 * or we could end up breaking branded zone support. See the usage of
+	 * this label in lx_brand_int80_callback and sn1_brand_int91_callback
+	 * for examples.
+	 *
+	 * We want to swapgs to maintain the invariant that all entries into
+	 * tr_iret_user are done on the user gsbase.
+	 */
+	ALTENTRY(sys_sysint_swapgs_iret)
+	call	x86_md_clear
+	SWAPGS
+	jmp	tr_iret_user
+	/*NOTREACHED*/
+	SET_SIZE(sys_sysint_swapgs_iret)
+	SET_SIZE(sys_syscall_int)
+	SET_SIZE(brand_sys_syscall_int)
+
+/*
+ * Legacy 32-bit applications and old libc implementations do lcalls;
+ * we should never get here because the LDT entry containing the syscall
+ * segment descriptor has the "segment present" bit cleared, which means
+ * we end up processing those system calls in trap() via a not-present trap.
+ *
+ * We do it this way because a call gate unhelpfully does -nothing- to the
+ * interrupt flag bit, so an interrupt can run us just after the lcall
+ * completes, but just before the swapgs takes effect.   Thus the INTR_PUSH and
+ * INTR_POP paths would have to be slightly more complex to dance around
+ * this problem, and end up depending explicitly on the first
+ * instruction of this handler being either swapgs or cli.
+ */
+
+	ENTRY_NP(sys_lcall32)
+	SWAPGS				/* kernel gsbase */
+	pushq	$0
+	pushq	%rbp
+	movq	%rsp, %rbp
+	leaq	__lcall_panic_str(%rip), %rdi
+	xorl	%eax, %eax
+	call	panic
+	SET_SIZE(sys_lcall32)
+
+__lcall_panic_str:
+	.string	"sys_lcall32: shouldn't be here!"
+
+/*
  * Declare a uintptr_t which covers the entire pc range of syscall
  * handlers for the stack walkers that need this.
  */
@@ -644,26 +1305,10 @@
 	.NWORD	. - _allsyscalls
 	SET_SIZE(_allsyscalls_size)
 
-#endif	/* __lint */
-
 /*
  * These are the thread context handlers for lwps using sysenter/sysexit.
  */
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-sep_save(void *ksp)
-{}
-
-/*ARGSUSED*/
-void
-sep_restore(void *ksp)
-{}
-
-#else	/* __lint */
-
 	/*
 	 * setting this value to zero as we switch away causes the
 	 * stack-pointer-on-sysenter to be NULL, ensuring that we
@@ -682,33 +1327,11 @@
 	 * Update the kernel stack pointer as we resume onto this cpu.
 	 */
 	ENTRY_NP(sep_restore)
-	movl	4(%esp), %eax			/* per-lwp kernel sp */
-	xorl	%edx, %edx
+	movq	%rdi, %rdx
+	shrq	$32, %rdx
+	movl	%edi, %eax
 	movl	$MSR_INTC_SEP_ESP, %ecx
 	wrmsr
 	ret
 	SET_SIZE(sep_restore)
 
-#endif	/* __lint */
-
-/*
- * Call syscall().  Called from trap() on watchpoint at lcall 0,7
- */
-
-#if defined(__lint)
-
-void
-watch_syscall(void)
-{}
-
-#else	/* __lint */
-
-	ENTRY_NP(watch_syscall)
-	CLI(%eax)
-	movl	%gs:CPU_THREAD, %ebx
-	movl	T_STACK(%ebx), %esp		/ switch to the thread stack
-	movl	REGOFF_EAX(%esp), %eax		/ recover original syscall#
-	jmp	_watch_do_syscall
-	SET_SIZE(watch_syscall)
-
-#endif	/* __lint */
--- old/usr/src/uts/i86pc/ml/syscall_asm_amd64.s	Thu Nov 14 19:00:18 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,1424 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-/*
- * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2019 Joyent, Inc.
- * Copyright (c) 2016 by Delphix. All rights reserved.
- */
-
-#include <sys/asm_linkage.h>
-#include <sys/asm_misc.h>
-#include <sys/regset.h>
-#include <sys/privregs.h>
-#include <sys/psw.h>
-#include <sys/machbrand.h>
-
-#if defined(__lint)
-
-#include <sys/types.h>
-#include <sys/thread.h>
-#include <sys/systm.h>
-
-#else	/* __lint */
-
-#include <sys/segments.h>
-#include <sys/pcb.h>
-#include <sys/trap.h>
-#include <sys/ftrace.h>
-#include <sys/traptrace.h>
-#include <sys/clock.h>
-#include <sys/model.h>
-#include <sys/panic.h>
-
-#if defined(__xpv)
-#include <sys/hypervisor.h>
-#endif
-
-#include "assym.h"
-
-#endif	/* __lint */
-
-/*
- * We implement five flavours of system call entry points
- *
- * -	syscall/sysretq		(amd64 generic)
- * -	syscall/sysretl		(i386 plus SYSC bit)
- * -	sysenter/sysexit	(i386 plus SEP bit)
- * -	int/iret		(i386 generic)
- * -	lcall/iret		(i386 generic)
- *
- * The current libc included in Solaris uses int/iret as the base unoptimized
- * kernel entry method. Older libc implementations and legacy binaries may use
- * the lcall call gate, so it must continue to be supported.
- *
- * System calls that use an lcall call gate are processed in trap() via a
- * segment-not-present trap, i.e. lcalls are extremely slow(!).
- *
- * The basic pattern used in the 32-bit SYSC handler at this point in time is
- * to have the bare minimum of assembler, and get to the C handlers as
- * quickly as possible.
- *
- * The 64-bit handler is much closer to the sparcv9 handler; that's
- * because of passing arguments in registers.  The 32-bit world still
- * passes arguments on the stack -- that makes that handler substantially
- * more complex.
- *
- * The two handlers share a few code fragments which are broken
- * out into preprocessor macros below.
- *
- * XX64	come back and speed all this up later.  The 32-bit stuff looks
- * especially easy to speed up the argument copying part ..
- *
- *
- * Notes about segment register usage (c.f. the 32-bit kernel)
- *
- * In the 32-bit kernel, segment registers are dutifully saved and
- * restored on all mode transitions because the kernel uses them directly.
- * When the processor is running in 64-bit mode, segment registers are
- * largely ignored.
- *
- * %cs and %ss
- *	controlled by the hardware mechanisms that make mode transitions
- *
- * The remaining segment registers have to either be pointing at a valid
- * descriptor i.e. with the 'present' bit set, or they can NULL descriptors
- *
- * %ds and %es
- *	always ignored
- *
- * %fs and %gs
- *	fsbase and gsbase are used to control the place they really point at.
- *	The kernel only depends on %gs, and controls its own gsbase via swapgs
- *
- * Note that loading segment registers is still costly because the GDT
- * lookup still happens (this is because the hardware can't know that we're
- * not setting up these segment registers for a 32-bit program).  Thus we
- * avoid doing this in the syscall path, and defer them to lwp context switch
- * handlers, so the register values remain virtualized to the lwp.
- */
-
-#if defined(SYSCALLTRACE)
-#define	ORL_SYSCALLTRACE(r32)		\
-	orl	syscalltrace(%rip), r32
-#else
-#define	ORL_SYSCALLTRACE(r32)
-#endif
-
-/*
- * In the 32-bit kernel, we do absolutely nothing before getting into the
- * brand callback checks.  In 64-bit land, we do swapgs and then come here.
- * We assume that the %rsp- and %r15-stashing fields in the CPU structure
- * are still unused.
- *
- * Check if a brand_mach_ops callback is defined for the specified callback_id
- * type.  If so invoke it with the kernel's %gs value loaded and the following
- * data on the stack:
- *
- * stack:  --------------------------------------
- *      32 | callback pointer			|
- *    | 24 | user (or interrupt) stack pointer	|
- *    | 16 | lwp pointer			|
- *    v  8 | userland return address		|
- *       0 | callback wrapper return addr	|
- *         --------------------------------------
- *
- * Since we're pushing the userland return address onto the kernel stack
- * we need to get that address without accessing the user's stack (since we
- * can't trust that data).  There are different ways to get the userland
- * return address depending on how the syscall trap was made:
- *
- * a) For sys_syscall and sys_syscall32 the return address is in %rcx.
- * b) For sys_sysenter the return address is in %rdx.
- * c) For sys_int80 and sys_syscall_int (int91), upon entry into the macro,
- *    the stack pointer points at the state saved when we took the interrupt:
- *	 ------------------------
- *    |  | user's %ss		|
- *    |  | user's %esp		|
- *    |  | EFLAGS register	|
- *    v  | user's %cs		|
- *       | user's %eip		|
- *	 ------------------------
- *
- * The 2nd parameter to the BRAND_CALLBACK macro is either the
- * BRAND_URET_FROM_REG or BRAND_URET_FROM_INTR_STACK macro.  These macros are
- * used to generate the proper code to get the userland return address for
- * each syscall entry point.
- *
- * The interface to the brand callbacks on the 64-bit kernel assumes %r15
- * is available as a scratch register within the callback.  If the callback
- * returns within the kernel then this macro will restore %r15.  If the
- * callback is going to return directly to userland then it should restore
- * %r15 before returning to userland.
- */
-#define BRAND_URET_FROM_REG(rip_reg)					\
-	pushq	rip_reg			/* push the return address	*/
-
-/*
- * The interrupt stack pointer we saved on entry to the BRAND_CALLBACK macro
- * is currently pointing at the user return address (%eip).
- */
-#define BRAND_URET_FROM_INTR_STACK()					\
-	movq	%gs:CPU_RTMP_RSP, %r15	/* grab the intr. stack pointer	*/ ;\
-	pushq	(%r15)			/* push the return address	*/
-
-#define	BRAND_CALLBACK(callback_id, push_userland_ret)			    \
-	movq	%rsp, %gs:CPU_RTMP_RSP	/* save the stack pointer	*/ ;\
-	movq	%r15, %gs:CPU_RTMP_R15	/* save %r15			*/ ;\
-	movq	%gs:CPU_THREAD, %r15	/* load the thread pointer	*/ ;\
-	movq	T_STACK(%r15), %rsp	/* switch to the kernel stack	*/ ;\
-	subq	$16, %rsp		/* save space for 2 pointers	*/ ;\
-	pushq	%r14			/* save %r14			*/ ;\
-	movq	%gs:CPU_RTMP_RSP, %r14					   ;\
-	movq	%r14, 8(%rsp)		/* stash the user stack pointer	*/ ;\
-	popq	%r14			/* restore %r14			*/ ;\
-	movq	T_LWP(%r15), %r15	/* load the lwp pointer		*/ ;\
-	pushq	%r15			/* push the lwp pointer		*/ ;\
-	movq	LWP_PROCP(%r15), %r15	/* load the proc pointer	*/ ;\
-	movq	P_BRAND(%r15), %r15	/* load the brand pointer	*/ ;\
-	movq	B_MACHOPS(%r15), %r15	/* load the machops pointer	*/ ;\
-	movq	_CONST(_MUL(callback_id, CPTRSIZE))(%r15), %r15		   ;\
-	cmpq	$0, %r15						   ;\
-	je	1f							   ;\
-	movq	%r15, 16(%rsp)		/* save the callback pointer	*/ ;\
-	push_userland_ret		/* push the return address	*/ ;\
-	movq	24(%rsp), %r15		/* load callback pointer	*/ ;\
-	INDIRECT_CALL_REG(r15)		/* call callback		*/ ;\
-1:	movq	%gs:CPU_RTMP_R15, %r15	/* restore %r15			*/ ;\
-	movq	%gs:CPU_RTMP_RSP, %rsp	/* restore the stack pointer	*/
-
-#define	MSTATE_TRANSITION(from, to)		\
-	movl	$from, %edi;			\
-	movl	$to, %esi;			\
-	call	syscall_mstate
-
-/*
- * Check to see if a simple (direct) return is possible i.e.
- *
- *	if (t->t_post_sys_ast | syscalltrace |
- *	    lwp->lwp_pcb.pcb_rupdate == 1)
- *		do full version	;
- *
- * Preconditions:
- * -	t is curthread
- * Postconditions:
- * -	condition code NE is set if post-sys is too complex
- * -	rtmp is zeroed if it isn't (we rely on this!)
- * -	ltmp is smashed
- */
-#define	CHECK_POSTSYS_NE(t, ltmp, rtmp)			\
-	movq	T_LWP(t), ltmp;				\
-	movzbl	PCB_RUPDATE(ltmp), rtmp;		\
-	ORL_SYSCALLTRACE(rtmp);				\
-	orl	T_POST_SYS_AST(t), rtmp;		\
-	cmpl	$0, rtmp
-
-/*
- * Fix up the lwp, thread, and eflags for a successful return
- *
- * Preconditions:
- * -	zwreg contains zero
- */
-#define	SIMPLE_SYSCALL_POSTSYS(t, lwp, zwreg)		\
-	movb	$LWP_USER, LWP_STATE(lwp);		\
-	movw	zwreg, T_SYSNUM(t);			\
-	andb	$_CONST(0xffff - PS_C), REGOFF_RFL(%rsp)
-
-/*
- * ASSERT(lwptoregs(lwp) == rp);
- *
- * This may seem obvious, but very odd things happen if this
- * assertion is false
- *
- * Preconditions:
- *	(%rsp is ready for normal call sequence)
- * Postconditions (if assertion is true):
- *	%r11 is smashed
- *
- * ASSERT(rp->r_cs == descnum)
- *
- * The code selector is written into the regs structure when the
- * lwp stack is created.  We use this ASSERT to validate that
- * the regs structure really matches how we came in.
- *
- * Preconditions:
- *	(%rsp is ready for normal call sequence)
- * Postconditions (if assertion is true):
- *	-none-
- *
- * ASSERT(lwp->lwp_pcb.pcb_rupdate == 0);
- *
- * If this is false, it meant that we returned to userland without
- * updating the segment registers as we were supposed to.
- *
- * Note that we must ensure no interrupts or other traps intervene
- * between entering privileged mode and performing the assertion,
- * otherwise we may perform a context switch on the thread, which
- * will end up setting pcb_rupdate to 1 again.
- *
- * ASSERT(%cr0 & CR0_TS == 0);
- * Preconditions:
- *	(%rsp is ready for normal call sequence)
- * Postconditions (if assertion is true):
- *      (specified register is clobbered)
- *
- * Check to make sure that we are returning to user land and that CR0.TS
- * is not set. This is required as part of the eager FPU (see
- * uts/intel/ia32/os/fpu.c for more information).
- */
-
-#if defined(DEBUG)
-
-#if !defined(__lint)
-
-__lwptoregs_msg:
-	.string	"syscall_asm_amd64.s:%d lwptoregs(%p) [%p] != rp [%p]"
-
-__codesel_msg:
-	.string	"syscall_asm_amd64.s:%d rp->r_cs [%ld] != %ld"
-
-__no_rupdate_msg:
-	.string	"syscall_asm_amd64.s:%d lwp %p, pcb_rupdate != 0"
-
-__bad_ts_msg:
-	.string "sysscall_asm_amd64.s:%d CR0.TS set on user return"
-
-#endif	/* !__lint */
-
-#define	ASSERT_LWPTOREGS(lwp, rp)			\
-	movq	LWP_REGS(lwp), %r11;			\
-	cmpq	rp, %r11;				\
-	je	7f;					\
-	leaq	__lwptoregs_msg(%rip), %rdi;		\
-	movl	$__LINE__, %esi;			\
-	movq	lwp, %rdx;				\
-	movq	%r11, %rcx;				\
-	movq	rp, %r8;				\
-	xorl	%eax, %eax;				\
-	call	panic;					\
-7:
-
-#define	ASSERT_NO_RUPDATE_PENDING(lwp)			\
-	testb	$0x1, PCB_RUPDATE(lwp);			\
-	je	8f;					\
-	movq	lwp, %rdx;				\
-	leaq	__no_rupdate_msg(%rip), %rdi;		\
-	movl	$__LINE__, %esi;			\
-	xorl	%eax, %eax;				\
-	call	panic;					\
-8:
-
-#define	ASSERT_CR0TS_ZERO(reg)				\
-	movq	%cr0, reg;				\
-	testq	$CR0_TS, reg;				\
-	jz	9f;					\
-	leaq	__bad_ts_msg(%rip), %rdi;		\
-	movl	$__LINE__, %esi;			\
-	xorl	%eax, %eax;				\
-	call	panic;					\
-9:
-
-#else
-#define	ASSERT_LWPTOREGS(lwp, rp)
-#define	ASSERT_NO_RUPDATE_PENDING(lwp)
-#define	ASSERT_CR0TS_ZERO(reg)
-#endif
-
-/*
- * Do the traptrace thing and restore any registers we used
- * in situ.  Assumes that %rsp is pointing at the base of
- * the struct regs, obviously ..
- */
-#ifdef TRAPTRACE
-#define	SYSCALL_TRAPTRACE(ttype)				\
-	TRACE_PTR(%rdi, %rbx, %ebx, %rcx, ttype);		\
-	TRACE_REGS(%rdi, %rsp, %rbx, %rcx);			\
-	TRACE_STAMP(%rdi);	/* rdtsc clobbers %eax, %edx */	\
-	movq	REGOFF_RAX(%rsp), %rax;				\
-	movq	REGOFF_RBX(%rsp), %rbx;				\
-	movq	REGOFF_RCX(%rsp), %rcx;				\
-	movq	REGOFF_RDX(%rsp), %rdx;				\
-	movl	%eax, TTR_SYSNUM(%rdi);				\
-	movq	REGOFF_RDI(%rsp), %rdi
-
-#define	SYSCALL_TRAPTRACE32(ttype)				\
-	SYSCALL_TRAPTRACE(ttype);				\
-	/* paranoia: clean the top 32-bits of the registers */	\
-	orl	%eax, %eax;					\
-	orl	%ebx, %ebx;					\
-	orl	%ecx, %ecx;					\
-	orl	%edx, %edx;					\
-	orl	%edi, %edi
-#else	/* TRAPTRACE */
-#define	SYSCALL_TRAPTRACE(ttype)
-#define	SYSCALL_TRAPTRACE32(ttype)
-#endif	/* TRAPTRACE */
-
-/*
- * The 64-bit libc syscall wrapper does this:
- *
- * fn(<args>)
- * {
- *	movq	%rcx, %r10	-- because syscall smashes %rcx
- *	movl	$CODE, %eax
- *	syscall
- *	<error processing>
- * }
- *
- * Thus when we come into the kernel:
- *
- *	%rdi, %rsi, %rdx, %r10, %r8, %r9 contain first six args
- *	%rax is the syscall number
- *	%r12-%r15 contain caller state
- *
- * The syscall instruction arranges that:
- *
- *	%rcx contains the return %rip
- *	%r11d contains bottom 32-bits of %rflags
- *	%rflags is masked (as determined by the SFMASK msr)
- *	%cs is set to UCS_SEL (as determined by the STAR msr)
- *	%ss is set to UDS_SEL (as determined by the STAR msr)
- *	%rip is set to sys_syscall (as determined by the LSTAR msr)
- *
- * Or in other words, we have no registers available at all.
- * Only swapgs can save us!
- *
- * Under the hypervisor, the swapgs has happened already.  However, the
- * state of the world is very different from that we're familiar with.
- *
- * In particular, we have a stack structure like that for interrupt
- * gates, except that the %cs and %ss registers are modified for reasons
- * that are not entirely clear.  Critically, the %rcx/%r11 values do
- * *not* reflect the usage of those registers under a 'real' syscall[1];
- * the stack, therefore, looks like this:
- *
- *	0x0(rsp)	potentially junk %rcx
- *	0x8(rsp)	potentially junk %r11
- *	0x10(rsp)	user %rip
- *	0x18(rsp)	modified %cs
- *	0x20(rsp)	user %rflags
- *	0x28(rsp)	user %rsp
- *	0x30(rsp)	modified %ss
- *
- *
- * and before continuing on, we must load the %rip into %rcx and the
- * %rflags into %r11.
- *
- * [1] They used to, and we relied on it, but this was broken in 3.1.1.
- * Sigh.
- */
-#if defined(__xpv)
-#define	XPV_SYSCALL_PROD						\
-	movq	0x10(%rsp), %rcx;					\
-	movq	0x20(%rsp), %r11;					\
-	movq	0x28(%rsp), %rsp
-#else
-#define	XPV_SYSCALL_PROD /* nothing */
-#endif
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-sys_syscall()
-{}
-
-void
-_allsyscalls()
-{}
-
-size_t _allsyscalls_size;
-
-#else	/* __lint */
-
-	ENTRY_NP2(brand_sys_syscall,_allsyscalls)
-	SWAPGS				/* kernel gsbase */
-	XPV_SYSCALL_PROD
-	BRAND_CALLBACK(BRAND_CB_SYSCALL, BRAND_URET_FROM_REG(%rcx))
-	jmp	noprod_sys_syscall
-
-	ALTENTRY(sys_syscall)
-	SWAPGS				/* kernel gsbase */
-	XPV_SYSCALL_PROD
-
-noprod_sys_syscall:
-	movq	%r15, %gs:CPU_RTMP_R15
-	movq	%rsp, %gs:CPU_RTMP_RSP
-
-	movq	%gs:CPU_THREAD, %r15
-	movq	T_STACK(%r15), %rsp	/* switch from user to kernel stack */
-
-	ASSERT_UPCALL_MASK_IS_SET
-
-	movl	$UCS_SEL, REGOFF_CS(%rsp)
-	movq	%rcx, REGOFF_RIP(%rsp)		/* syscall: %rip -> %rcx */
-	movq	%r11, REGOFF_RFL(%rsp)		/* syscall: %rfl -> %r11d */
-	movl	$UDS_SEL, REGOFF_SS(%rsp)
-
-	movl	%eax, %eax			/* wrapper: sysc# -> %eax */
-	movq	%rdi, REGOFF_RDI(%rsp)
-	movq	%rsi, REGOFF_RSI(%rsp)
-	movq	%rdx, REGOFF_RDX(%rsp)
-	movq	%r10, REGOFF_RCX(%rsp)		/* wrapper: %rcx -> %r10 */
-	movq	%r10, %rcx			/* arg[3] for direct calls */
-
-	movq	%r8, REGOFF_R8(%rsp)
-	movq	%r9, REGOFF_R9(%rsp)
-	movq	%rax, REGOFF_RAX(%rsp)
-	movq	%rbx, REGOFF_RBX(%rsp)
-
-	movq	%rbp, REGOFF_RBP(%rsp)
-	movq	%r10, REGOFF_R10(%rsp)
-	movq	%gs:CPU_RTMP_RSP, %r11
-	movq	%r11, REGOFF_RSP(%rsp)
-	movq	%r12, REGOFF_R12(%rsp)
-
-	movq	%r13, REGOFF_R13(%rsp)
-	movq	%r14, REGOFF_R14(%rsp)
-	movq	%gs:CPU_RTMP_R15, %r10
-	movq	%r10, REGOFF_R15(%rsp)
-	movq	$0, REGOFF_SAVFP(%rsp)
-	movq	$0, REGOFF_SAVPC(%rsp)
-
-	/*
-	 * Copy these registers here in case we end up stopped with
-	 * someone (like, say, /proc) messing with our register state.
-	 * We don't -restore- them unless we have to in update_sregs.
-	 *
-	 * Since userland -can't- change fsbase or gsbase directly,
-	 * and capturing them involves two serializing instructions,
-	 * we don't bother to capture them here.
-	 */
-	xorl	%ebx, %ebx
-	movw	%ds, %bx
-	movq	%rbx, REGOFF_DS(%rsp)
-	movw	%es, %bx
-	movq	%rbx, REGOFF_ES(%rsp)
-	movw	%fs, %bx
-	movq	%rbx, REGOFF_FS(%rsp)
-	movw	%gs, %bx
-	movq	%rbx, REGOFF_GS(%rsp)
-
-	/*
-	 * If we're trying to use TRAPTRACE though, I take that back: we're
-	 * probably debugging some problem in the SWAPGS logic and want to know
-	 * what the incoming gsbase was.
-	 *
-	 * Since we already did SWAPGS, record the KGSBASE.
-	 */
-#if defined(DEBUG) && defined(TRAPTRACE) && !defined(__xpv)
-	movl	$MSR_AMD_KGSBASE, %ecx
-	rdmsr
-	movl	%eax, REGOFF_GSBASE(%rsp)
-	movl	%edx, REGOFF_GSBASE+4(%rsp)
-#endif
-
-	/*
-	 * Machine state saved in the regs structure on the stack
-	 * First six args in %rdi, %rsi, %rdx, %rcx, %r8, %r9
-	 * %eax is the syscall number
-	 * %rsp is the thread's stack, %r15 is curthread
-	 * REG_RSP(%rsp) is the user's stack
-	 */
-
-	SYSCALL_TRAPTRACE($TT_SYSC64)
-
-	movq	%rsp, %rbp
-
-	movq	T_LWP(%r15), %r14
-	ASSERT_NO_RUPDATE_PENDING(%r14)
-	ENABLE_INTR_FLAGS
-
-	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
-	movl	REGOFF_RAX(%rsp), %eax	/* (%rax damaged by mstate call) */
-
-	ASSERT_LWPTOREGS(%r14, %rsp)
-
-	movb	$LWP_SYS, LWP_STATE(%r14)
-	incq	LWP_RU_SYSC(%r14)
-	movb	$NORMALRETURN, LWP_EOSYS(%r14)
-
-	incq	%gs:CPU_STATS_SYS_SYSCALL
-
-	movw	%ax, T_SYSNUM(%r15)
-	movzbl	T_PRE_SYS(%r15), %ebx
-	ORL_SYSCALLTRACE(%ebx)
-	testl	%ebx, %ebx
-	jne	_syscall_pre
-
-_syscall_invoke:
-	movq	REGOFF_RDI(%rbp), %rdi
-	movq	REGOFF_RSI(%rbp), %rsi
-	movq	REGOFF_RDX(%rbp), %rdx
-	movq	REGOFF_RCX(%rbp), %rcx
-	movq	REGOFF_R8(%rbp), %r8
-	movq	REGOFF_R9(%rbp), %r9
-
-	cmpl	$NSYSCALL, %eax
-	jae	_syscall_ill
-	shll	$SYSENT_SIZE_SHIFT, %eax
-	leaq	sysent(%rax), %rbx
-
-	movq	SY_CALLC(%rbx), %rax
-	INDIRECT_CALL_REG(rax)
-
-	movq	%rax, %r12
-	movq	%rdx, %r13
-
-	/*
-	 * If the handler returns two ints, then we need to split the
-	 * 64-bit return value into two 32-bit values.
-	 */
-	testw	$SE_32RVAL2, SY_FLAGS(%rbx)
-	je	5f
-	movq	%r12, %r13
-	shrq	$32, %r13	/* upper 32-bits into %edx */
-	movl	%r12d, %r12d	/* lower 32-bits into %eax */
-5:
-	/*
-	 * Optimistically assume that there's no post-syscall
-	 * work to do.  (This is to avoid having to call syscall_mstate()
-	 * with interrupts disabled)
-	 */
-	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
-
-	/*
-	 * We must protect ourselves from being descheduled here;
-	 * If we were, and we ended up on another cpu, or another
-	 * lwp got in ahead of us, it could change the segment
-	 * registers without us noticing before we return to userland.
-	 */
-	CLI(%r14)
-	CHECK_POSTSYS_NE(%r15, %r14, %ebx)
-	jne	_syscall_post
-
-	/*
-	 * We need to protect ourselves against non-canonical return values
-	 * because Intel doesn't check for them on sysret (AMD does).  Canonical
-	 * addresses on current amd64 processors only use 48-bits for VAs; an
-	 * address is canonical if all upper bits (47-63) are identical. If we
-	 * find a non-canonical %rip, we opt to go through the full
-	 * _syscall_post path which takes us into an iretq which is not
-	 * susceptible to the same problems sysret is.
-	 *
-	 * We're checking for a canonical address by first doing an arithmetic
-	 * shift. This will fill in the remaining bits with the value of bit 63.
-	 * If the address were canonical, the register would now have either all
-	 * zeroes or all ones in it. Therefore we add one (inducing overflow)
-	 * and compare against 1. A canonical address will either be zero or one
-	 * at this point, hence the use of ja.
-	 *
-	 * At this point, r12 and r13 have the return value so we can't use
-	 * those registers.
-	 */
-	movq	REGOFF_RIP(%rsp), %rcx
-	sarq	$47, %rcx
-	incq	%rcx
-	cmpq	$1, %rcx
-	ja	_syscall_post
-
-
-	SIMPLE_SYSCALL_POSTSYS(%r15, %r14, %bx)
-
-	movq	%r12, REGOFF_RAX(%rsp)
-	movq	%r13, REGOFF_RDX(%rsp)
-
-	/*
-	 * Clobber %r11 as we check CR0.TS.
-	 */
-	ASSERT_CR0TS_ZERO(%r11)
-
-	/*
-	 * Unlike other cases, because we need to restore the user stack pointer
-	 * before exiting the kernel we must clear the microarch state before
-	 * getting here. This should be safe because it means that the only
-	 * values on the bus after this are based on the user's registers and
-	 * potentially the addresses where we stored them. Given the constraints
-	 * of sysret, that's how it has to be.
-	 */
-	call	x86_md_clear
-
-	/*
-	 * To get back to userland, we need the return %rip in %rcx and
-	 * the return %rfl in %r11d.  The sysretq instruction also arranges
-	 * to fix up %cs and %ss; everything else is our responsibility.
-	 */
-	movq	REGOFF_RDI(%rsp), %rdi
-	movq	REGOFF_RSI(%rsp), %rsi
-	movq	REGOFF_RDX(%rsp), %rdx
-	/* %rcx used to restore %rip value */
-
-	movq	REGOFF_R8(%rsp), %r8
-	movq	REGOFF_R9(%rsp), %r9
-	movq	REGOFF_RAX(%rsp), %rax
-	movq	REGOFF_RBX(%rsp), %rbx
-
-	movq	REGOFF_RBP(%rsp), %rbp
-	movq	REGOFF_R10(%rsp), %r10
-	/* %r11 used to restore %rfl value */
-	movq	REGOFF_R12(%rsp), %r12
-
-	movq	REGOFF_R13(%rsp), %r13
-	movq	REGOFF_R14(%rsp), %r14
-	movq	REGOFF_R15(%rsp), %r15
-
-	movq	REGOFF_RIP(%rsp), %rcx
-	movl	REGOFF_RFL(%rsp), %r11d
-
-#if defined(__xpv)
-	addq	$REGOFF_RIP, %rsp
-#else
-	movq	REGOFF_RSP(%rsp), %rsp
-#endif
-
-        /*
-         * There can be no instructions between the ALTENTRY below and
-	 * SYSRET or we could end up breaking brand support. See label usage
-         * in sn1_brand_syscall_callback for an example.
-         */
-	ASSERT_UPCALL_MASK_IS_SET
-#if defined(__xpv)
-	SYSRETQ
-        ALTENTRY(nopop_sys_syscall_swapgs_sysretq)
-
-	/*
-	 * We can only get here after executing a brand syscall
-	 * interposition callback handler and simply need to
-	 * "sysretq" back to userland. On the hypervisor this
-	 * involves the iret hypercall which requires us to construct
-	 * just enough of the stack needed for the hypercall.
-	 * (rip, cs, rflags, rsp, ss).
-	 */
-	movq    %rsp, %gs:CPU_RTMP_RSP		/* save user's rsp */
-	movq	%gs:CPU_THREAD, %r11
-	movq	T_STACK(%r11), %rsp
-
-	movq	%rcx, REGOFF_RIP(%rsp)
-	movl	$UCS_SEL, REGOFF_CS(%rsp)
-	movq	%gs:CPU_RTMP_RSP, %r11
-	movq	%r11, REGOFF_RSP(%rsp)
-	pushfq
-	popq	%r11				/* hypercall enables ints */
-	movq	%r11, REGOFF_RFL(%rsp)
-	movl	$UDS_SEL, REGOFF_SS(%rsp)
-	addq	$REGOFF_RIP, %rsp
-	/*
-	 * XXPV: see comment in SYSRETQ definition for future optimization
-	 *       we could take.
-	 */
-	ASSERT_UPCALL_MASK_IS_SET
-	SYSRETQ
-#else
-        ALTENTRY(nopop_sys_syscall_swapgs_sysretq)
-	jmp	tr_sysretq
-#endif
-        /*NOTREACHED*/
-        SET_SIZE(nopop_sys_syscall_swapgs_sysretq)
-
-_syscall_pre:
-	call	pre_syscall
-	movl	%eax, %r12d
-	testl	%eax, %eax
-	jne	_syscall_post_call
-	/*
-	 * Didn't abort, so reload the syscall args and invoke the handler.
-	 */
-	movzwl	T_SYSNUM(%r15), %eax
-	jmp	_syscall_invoke
-
-_syscall_ill:
-	call	nosys
-	movq	%rax, %r12
-	movq	%rdx, %r13
-	jmp	_syscall_post_call
-
-_syscall_post:
-	STI
-	/*
-	 * Sigh, our optimism wasn't justified, put it back to LMS_SYSTEM
-	 * so that we can account for the extra work it takes us to finish.
-	 */
-	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
-_syscall_post_call:
-	movq	%r12, %rdi
-	movq	%r13, %rsi
-	call	post_syscall
-	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
-	jmp	_sys_rtt
-	SET_SIZE(sys_syscall)
-	SET_SIZE(brand_sys_syscall)
-
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-sys_syscall32()
-{}
-
-#else	/* __lint */
-
-	ENTRY_NP(brand_sys_syscall32)
-	SWAPGS				/* kernel gsbase */
-	XPV_TRAP_POP
-	BRAND_CALLBACK(BRAND_CB_SYSCALL32, BRAND_URET_FROM_REG(%rcx))
-	jmp	nopop_sys_syscall32
-
-	ALTENTRY(sys_syscall32)
-	SWAPGS				/* kernel gsbase */
-	XPV_TRAP_POP
-
-nopop_sys_syscall32:
-	movl	%esp, %r10d
-	movq	%gs:CPU_THREAD, %r15
-	movq	T_STACK(%r15), %rsp
-	movl	%eax, %eax
-
-	movl	$U32CS_SEL, REGOFF_CS(%rsp)
-	movl	%ecx, REGOFF_RIP(%rsp)		/* syscall: %rip -> %rcx */
-	movq	%r11, REGOFF_RFL(%rsp)		/* syscall: %rfl -> %r11d */
-	movq	%r10, REGOFF_RSP(%rsp)
-	movl	$UDS_SEL, REGOFF_SS(%rsp)
-
-_syscall32_save:
-	movl	%edi, REGOFF_RDI(%rsp)
-	movl	%esi, REGOFF_RSI(%rsp)
-	movl	%ebp, REGOFF_RBP(%rsp)
-	movl	%ebx, REGOFF_RBX(%rsp)
-	movl	%edx, REGOFF_RDX(%rsp)
-	movl	%ecx, REGOFF_RCX(%rsp)
-	movl	%eax, REGOFF_RAX(%rsp)		/* wrapper: sysc# -> %eax */
-	movq	$0, REGOFF_SAVFP(%rsp)
-	movq	$0, REGOFF_SAVPC(%rsp)
-
-	/*
-	 * Copy these registers here in case we end up stopped with
-	 * someone (like, say, /proc) messing with our register state.
-	 * We don't -restore- them unless we have to in update_sregs.
-	 *
-	 * Since userland -can't- change fsbase or gsbase directly,
-	 * we don't bother to capture them here.
-	 */
-	xorl	%ebx, %ebx
-	movw	%ds, %bx
-	movq	%rbx, REGOFF_DS(%rsp)
-	movw	%es, %bx
-	movq	%rbx, REGOFF_ES(%rsp)
-	movw	%fs, %bx
-	movq	%rbx, REGOFF_FS(%rsp)
-	movw	%gs, %bx
-	movq	%rbx, REGOFF_GS(%rsp)
-
-	/*
-	 * If we're trying to use TRAPTRACE though, I take that back: we're
-	 * probably debugging some problem in the SWAPGS logic and want to know
-	 * what the incoming gsbase was.
-	 *
-	 * Since we already did SWAPGS, record the KGSBASE.
-	 */
-#if defined(DEBUG) && defined(TRAPTRACE) && !defined(__xpv)
-	movl	$MSR_AMD_KGSBASE, %ecx
-	rdmsr
-	movl	%eax, REGOFF_GSBASE(%rsp)
-	movl	%edx, REGOFF_GSBASE+4(%rsp)
-#endif
-
-	/*
-	 * Application state saved in the regs structure on the stack
-	 * %eax is the syscall number
-	 * %rsp is the thread's stack, %r15 is curthread
-	 * REG_RSP(%rsp) is the user's stack
-	 */
-
-	SYSCALL_TRAPTRACE32($TT_SYSC)
-
-	movq	%rsp, %rbp
-
-	movq	T_LWP(%r15), %r14
-	ASSERT_NO_RUPDATE_PENDING(%r14)
-
-	ENABLE_INTR_FLAGS
-
-	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
-	movl	REGOFF_RAX(%rsp), %eax	/* (%rax damaged by mstate call) */
-
-	ASSERT_LWPTOREGS(%r14, %rsp)
-
-	incq	 %gs:CPU_STATS_SYS_SYSCALL
-
-	/*
-	 * Make some space for MAXSYSARGS (currently 8) 32-bit args placed
-	 * into 64-bit (long) arg slots, maintaining 16 byte alignment.  Or
-	 * more succinctly:
-	 *
-	 *	SA(MAXSYSARGS * sizeof (long)) == 64
-	 */
-#define	SYS_DROP	64			/* drop for args */
-	subq	$SYS_DROP, %rsp
-	movb	$LWP_SYS, LWP_STATE(%r14)
-	movq	%r15, %rdi
-	movq	%rsp, %rsi
-	call	syscall_entry
-
-	/*
-	 * Fetch the arguments copied onto the kernel stack and put
-	 * them in the right registers to invoke a C-style syscall handler.
-	 * %rax contains the handler address.
-	 *
-	 * Ideas for making all this go faster of course include simply
-	 * forcibly fetching 6 arguments from the user stack under lofault
-	 * protection, reverting to copyin_args only when watchpoints
-	 * are in effect.
-	 *
-	 * (If we do this, make sure that exec and libthread leave
-	 * enough space at the top of the stack to ensure that we'll
-	 * never do a fetch from an invalid page.)
-	 *
-	 * Lots of ideas here, but they won't really help with bringup B-)
-	 * Correctness can't wait, performance can wait a little longer ..
-	 */
-
-	movq	%rax, %rbx
-	movl	0(%rsp), %edi
-	movl	8(%rsp), %esi
-	movl	0x10(%rsp), %edx
-	movl	0x18(%rsp), %ecx
-	movl	0x20(%rsp), %r8d
-	movl	0x28(%rsp), %r9d
-
-	movq	SY_CALLC(%rbx), %rax
-	INDIRECT_CALL_REG(rax)
-
-	movq	%rbp, %rsp	/* pop the args */
-
-	/*
-	 * amd64 syscall handlers -always- return a 64-bit value in %rax.
-	 * On the 32-bit kernel, they always return that value in %eax:%edx
-	 * as required by the 32-bit ABI.
-	 *
-	 * Simulate the same behaviour by unconditionally splitting the
-	 * return value in the same way.
-	 */
-	movq	%rax, %r13
-	shrq	$32, %r13	/* upper 32-bits into %edx */
-	movl	%eax, %r12d	/* lower 32-bits into %eax */
-
-	/*
-	 * Optimistically assume that there's no post-syscall
-	 * work to do.  (This is to avoid having to call syscall_mstate()
-	 * with interrupts disabled)
-	 */
-	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
-
-	/*
-	 * We must protect ourselves from being descheduled here;
-	 * If we were, and we ended up on another cpu, or another
-	 * lwp got in ahead of us, it could change the segment
-	 * registers without us noticing before we return to userland.
-	 */
-	CLI(%r14)
-	CHECK_POSTSYS_NE(%r15, %r14, %ebx)
-	jne	_full_syscall_postsys32
-	SIMPLE_SYSCALL_POSTSYS(%r15, %r14, %bx)
-
-	/*
-	 * Clobber %r11 as we check CR0.TS.
-	 */
-	ASSERT_CR0TS_ZERO(%r11)
-
-	/*
-	 * Unlike other cases, because we need to restore the user stack pointer
-	 * before exiting the kernel we must clear the microarch state before
-	 * getting here. This should be safe because it means that the only
-	 * values on the bus after this are based on the user's registers and
-	 * potentially the addresses where we stored them. Given the constraints
-	 * of sysret, that's how it has to be.
-	 */
-	call	x86_md_clear
-
-	/*
-	 * To get back to userland, we need to put the return %rip in %rcx and
-	 * the return %rfl in %r11d.  The sysret instruction also arranges
-	 * to fix up %cs and %ss; everything else is our responsibility.
-	 */
-
-	movl	%r12d, %eax			/* %eax: rval1 */
-	movl	REGOFF_RBX(%rsp), %ebx
-	/* %ecx used for return pointer */
-	movl	%r13d, %edx			/* %edx: rval2 */
-	movl	REGOFF_RBP(%rsp), %ebp
-	movl	REGOFF_RSI(%rsp), %esi
-	movl	REGOFF_RDI(%rsp), %edi
-
-	movl	REGOFF_RFL(%rsp), %r11d		/* %r11 -> eflags */
-	movl	REGOFF_RIP(%rsp), %ecx		/* %ecx -> %eip */
-	movl	REGOFF_RSP(%rsp), %esp
-
-	ASSERT_UPCALL_MASK_IS_SET
-        ALTENTRY(nopop_sys_syscall32_swapgs_sysretl)
-	jmp	tr_sysretl
-        SET_SIZE(nopop_sys_syscall32_swapgs_sysretl)
-	/*NOTREACHED*/
-
-_full_syscall_postsys32:
-	STI
-	/*
-	 * Sigh, our optimism wasn't justified, put it back to LMS_SYSTEM
-	 * so that we can account for the extra work it takes us to finish.
-	 */
-	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
-	movq	%r15, %rdi
-	movq	%r12, %rsi			/* rval1 - %eax */
-	movq	%r13, %rdx			/* rval2 - %edx */
-	call	syscall_exit
-	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
-	jmp	_sys_rtt
-	SET_SIZE(sys_syscall32)
-	SET_SIZE(brand_sys_syscall32)
-
-#endif	/* __lint */
-
-/*
- * System call handler via the sysenter instruction
- * Used only for 32-bit system calls on the 64-bit kernel.
- *
- * The caller in userland has arranged that:
- *
- * -	%eax contains the syscall number
- * -	%ecx contains the user %esp
- * -	%edx contains the return %eip
- * -	the user stack contains the args to the syscall
- *
- * Hardware and (privileged) initialization code have arranged that by
- * the time the sysenter instructions completes:
- *
- * - %rip is pointing to sys_sysenter (below).
- * - %cs and %ss are set to kernel text and stack (data) selectors.
- * - %rsp is pointing at the lwp's stack
- * - interrupts have been disabled.
- *
- * Note that we are unable to return both "rvals" to userland with
- * this call, as %edx is used by the sysexit instruction.
- *
- * One final complication in this routine is its interaction with
- * single-stepping in a debugger.  For most of the system call mechanisms, the
- * CPU automatically clears the single-step flag before we enter the kernel.
- * The sysenter mechanism does not clear the flag, so a user single-stepping
- * through a libc routine may suddenly find themself single-stepping through the
- * kernel.  To detect this, kmdb and trap() both compare the trap %pc to the
- * [brand_]sys_enter addresses on each single-step trap.  If it finds that we
- * have single-stepped to a sysenter entry point, it explicitly clears the flag
- * and executes the sys_sysenter routine.
- *
- * One final complication in this final complication is the fact that we have
- * two different entry points for sysenter: brand_sys_sysenter and sys_sysenter.
- * If we enter at brand_sys_sysenter and start single-stepping through the
- * kernel with kmdb, we will eventually hit the instruction at sys_sysenter.
- * kmdb cannot distinguish between that valid single-step and the undesirable
- * one mentioned above.  To avoid this situation, we simply add a jump over the
- * instruction at sys_sysenter to make it impossible to single-step to it.
- */
-#if defined(__lint)
-
-void
-sys_sysenter()
-{}
-
-#else	/* __lint */
-
-	ENTRY_NP(brand_sys_sysenter)
-	SWAPGS				/* kernel gsbase */
-	ALTENTRY(_brand_sys_sysenter_post_swapgs)
-
-	BRAND_CALLBACK(BRAND_CB_SYSENTER, BRAND_URET_FROM_REG(%rdx))
-	/*
-	 * Jump over sys_sysenter to allow single-stepping as described
-	 * above.
-	 */
-	jmp	_sys_sysenter_post_swapgs
-
-	ALTENTRY(sys_sysenter)
-	SWAPGS				/* kernel gsbase */
-	ALTENTRY(_sys_sysenter_post_swapgs)
-
-	movq	%gs:CPU_THREAD, %r15
-
-	movl	$U32CS_SEL, REGOFF_CS(%rsp)
-	movl	%ecx, REGOFF_RSP(%rsp)		/* wrapper: %esp -> %ecx */
-	movl	%edx, REGOFF_RIP(%rsp)		/* wrapper: %eip -> %edx */
-	/*
-	 * NOTE: none of the instructions that run before we get here should
-	 * clobber bits in (R)FLAGS! This includes the kpti trampoline.
-	 */
-	pushfq
-	popq	%r10
-	movl	$UDS_SEL, REGOFF_SS(%rsp)
-
-	/*
-	 * Set the interrupt flag before storing the flags to the
-	 * flags image on the stack so we can return to user with
-	 * interrupts enabled if we return via sys_rtt_syscall32
-	 */
-	orq	$PS_IE, %r10
-	movq	%r10, REGOFF_RFL(%rsp)
-
-	movl	%edi, REGOFF_RDI(%rsp)
-	movl	%esi, REGOFF_RSI(%rsp)
-	movl	%ebp, REGOFF_RBP(%rsp)
-	movl	%ebx, REGOFF_RBX(%rsp)
-	movl	%edx, REGOFF_RDX(%rsp)
-	movl	%ecx, REGOFF_RCX(%rsp)
-	movl	%eax, REGOFF_RAX(%rsp)		/* wrapper: sysc# -> %eax */
-	movq	$0, REGOFF_SAVFP(%rsp)
-	movq	$0, REGOFF_SAVPC(%rsp)
-
-	/*
-	 * Copy these registers here in case we end up stopped with
-	 * someone (like, say, /proc) messing with our register state.
-	 * We don't -restore- them unless we have to in update_sregs.
-	 *
-	 * Since userland -can't- change fsbase or gsbase directly,
-	 * we don't bother to capture them here.
-	 */
-	xorl	%ebx, %ebx
-	movw	%ds, %bx
-	movq	%rbx, REGOFF_DS(%rsp)
-	movw	%es, %bx
-	movq	%rbx, REGOFF_ES(%rsp)
-	movw	%fs, %bx
-	movq	%rbx, REGOFF_FS(%rsp)
-	movw	%gs, %bx
-	movq	%rbx, REGOFF_GS(%rsp)
-
-	/*
-	 * If we're trying to use TRAPTRACE though, I take that back: we're
-	 * probably debugging some problem in the SWAPGS logic and want to know
-	 * what the incoming gsbase was.
-	 *
-	 * Since we already did SWAPGS, record the KGSBASE.
-	 */
-#if defined(DEBUG) && defined(TRAPTRACE) && !defined(__xpv)
-	movl	$MSR_AMD_KGSBASE, %ecx
-	rdmsr
-	movl	%eax, REGOFF_GSBASE(%rsp)
-	movl	%edx, REGOFF_GSBASE+4(%rsp)
-#endif
-
-	/*
-	 * Application state saved in the regs structure on the stack
-	 * %eax is the syscall number
-	 * %rsp is the thread's stack, %r15 is curthread
-	 * REG_RSP(%rsp) is the user's stack
-	 */
-
-	SYSCALL_TRAPTRACE($TT_SYSENTER)
-
-	movq	%rsp, %rbp
-
-	movq	T_LWP(%r15), %r14
-	ASSERT_NO_RUPDATE_PENDING(%r14)
-
-	ENABLE_INTR_FLAGS
-
-	/*
-	 * Catch 64-bit process trying to issue sysenter instruction
-	 * on Nocona based systems.
-	 */
-	movq	LWP_PROCP(%r14), %rax
-	cmpq	$DATAMODEL_ILP32, P_MODEL(%rax)
-	je	7f
-
-	/*
-	 * For a non-32-bit process, simulate a #ud, since that's what
-	 * native hardware does.  The traptrace entry (above) will
-	 * let you know what really happened.
-	 */
-	movq	$T_ILLINST, REGOFF_TRAPNO(%rsp)
-	movq	REGOFF_CS(%rsp), %rdi
-	movq	%rdi, REGOFF_ERR(%rsp)
-	movq	%rsp, %rdi
-	movq	REGOFF_RIP(%rsp), %rsi
-	movl	%gs:CPU_ID, %edx
-	call	trap
-	jmp	_sys_rtt
-7:
-
-	MSTATE_TRANSITION(LMS_USER, LMS_SYSTEM)
-	movl	REGOFF_RAX(%rsp), %eax	/* (%rax damaged by mstate calls) */
-
-	ASSERT_LWPTOREGS(%r14, %rsp)
-
-	incq	%gs:CPU_STATS_SYS_SYSCALL
-
-	/*
-	 * Make some space for MAXSYSARGS (currently 8) 32-bit args
-	 * placed into 64-bit (long) arg slots, plus one 64-bit
-	 * (long) arg count, maintaining 16 byte alignment.
-	 */
-	subq	$SYS_DROP, %rsp
-	movb	$LWP_SYS, LWP_STATE(%r14)
-	movq	%r15, %rdi
-	movq	%rsp, %rsi
-	call	syscall_entry
-
-	/*
-	 * Fetch the arguments copied onto the kernel stack and put
-	 * them in the right registers to invoke a C-style syscall handler.
-	 * %rax contains the handler address.
-	 */
-	movq	%rax, %rbx
-	movl	0(%rsp), %edi
-	movl	8(%rsp), %esi
-	movl	0x10(%rsp), %edx
-	movl	0x18(%rsp), %ecx
-	movl	0x20(%rsp), %r8d
-	movl	0x28(%rsp), %r9d
-
-	movq	SY_CALLC(%rbx), %rax
-	INDIRECT_CALL_REG(rax)
-
-	movq	%rbp, %rsp	/* pop the args */
-
-	/*
-	 * amd64 syscall handlers -always- return a 64-bit value in %rax.
-	 * On the 32-bit kernel, the always return that value in %eax:%edx
-	 * as required by the 32-bit ABI.
-	 *
-	 * Simulate the same behaviour by unconditionally splitting the
-	 * return value in the same way.
-	 */
-	movq	%rax, %r13
-	shrq	$32, %r13	/* upper 32-bits into %edx */
-	movl	%eax, %r12d	/* lower 32-bits into %eax */
-
-	/*
-	 * Optimistically assume that there's no post-syscall
-	 * work to do.  (This is to avoid having to call syscall_mstate()
-	 * with interrupts disabled)
-	 */
-	MSTATE_TRANSITION(LMS_SYSTEM, LMS_USER)
-
-	/*
-	 * We must protect ourselves from being descheduled here;
-	 * If we were, and we ended up on another cpu, or another
-	 * lwp got int ahead of us, it could change the segment
-	 * registers without us noticing before we return to userland.
-	 *
-	 * This cli is undone in the tr_sysexit trampoline code.
-	 */
-	cli
-	CHECK_POSTSYS_NE(%r15, %r14, %ebx)
-	jne	_full_syscall_postsys32
-	SIMPLE_SYSCALL_POSTSYS(%r15, %r14, %bx)
-
-	/*
-	 * To get back to userland, load up the 32-bit registers and
-	 * sysexit back where we came from.
-	 */
-
-	/*
-	 * Interrupts will be turned on by the 'sti' executed just before
-	 * sysexit.  The following ensures that restoring the user's rflags
-	 * doesn't enable interrupts too soon.
-	 */
-	andq	$_BITNOT(PS_IE), REGOFF_RFL(%rsp)
-
-	/*
-	 * Clobber %r11 as we check CR0.TS.
-	 */
-	ASSERT_CR0TS_ZERO(%r11)
-
-	/*
-	 * (There's no point in loading up %edx because the sysexit
-	 * mechanism smashes it.)
-	 */
-	movl	%r12d, %eax
-	movl	REGOFF_RBX(%rsp), %ebx
-	movl	REGOFF_RBP(%rsp), %ebp
-	movl	REGOFF_RSI(%rsp), %esi
-	movl	REGOFF_RDI(%rsp), %edi
-
-	movl	REGOFF_RIP(%rsp), %edx	/* sysexit: %edx -> %eip */
-	pushq	REGOFF_RFL(%rsp)
-	popfq
-	movl	REGOFF_RSP(%rsp), %ecx	/* sysexit: %ecx -> %esp */
-        ALTENTRY(sys_sysenter_swapgs_sysexit)
-	call	x86_md_clear
-	jmp	tr_sysexit
-	SET_SIZE(sys_sysenter_swapgs_sysexit)
-	SET_SIZE(sys_sysenter)
-	SET_SIZE(_sys_sysenter_post_swapgs)
-	SET_SIZE(brand_sys_sysenter)
-
-#endif	/* __lint */
-
-/*
- * This is the destination of the "int $T_SYSCALLINT" interrupt gate, used by
- * the generic i386 libc to do system calls. We do a small amount of setup
- * before jumping into the existing sys_syscall32 path.
- */
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-sys_syscall_int()
-{}
-
-#else	/* __lint */
-
-	ENTRY_NP(brand_sys_syscall_int)
-	SWAPGS				/* kernel gsbase */
-	XPV_TRAP_POP
-	call	smap_enable
-	BRAND_CALLBACK(BRAND_CB_INT91, BRAND_URET_FROM_INTR_STACK())
-	jmp	nopop_syscall_int
-
-	ALTENTRY(sys_syscall_int)
-	SWAPGS				/* kernel gsbase */
-	XPV_TRAP_POP
-	call	smap_enable
-
-nopop_syscall_int:
-	movq	%gs:CPU_THREAD, %r15
-	movq	T_STACK(%r15), %rsp
-	movl	%eax, %eax
-	/*
-	 * Set t_post_sys on this thread to force ourselves out via the slow
-	 * path. It might be possible at some later date to optimize this out
-	 * and use a faster return mechanism.
-	 */
-	movb	$1, T_POST_SYS(%r15)
-	CLEAN_CS
-	jmp	_syscall32_save
-	/*
-	 * There should be no instructions between this label and SWAPGS/IRET
-	 * or we could end up breaking branded zone support. See the usage of
-	 * this label in lx_brand_int80_callback and sn1_brand_int91_callback
-	 * for examples.
-	 *
-	 * We want to swapgs to maintain the invariant that all entries into
-	 * tr_iret_user are done on the user gsbase.
-	 */
-	ALTENTRY(sys_sysint_swapgs_iret)
-	call	x86_md_clear
-	SWAPGS
-	jmp	tr_iret_user
-	/*NOTREACHED*/
-	SET_SIZE(sys_sysint_swapgs_iret)
-	SET_SIZE(sys_syscall_int)
-	SET_SIZE(brand_sys_syscall_int)
-
-#endif	/* __lint */
-
-/*
- * Legacy 32-bit applications and old libc implementations do lcalls;
- * we should never get here because the LDT entry containing the syscall
- * segment descriptor has the "segment present" bit cleared, which means
- * we end up processing those system calls in trap() via a not-present trap.
- *
- * We do it this way because a call gate unhelpfully does -nothing- to the
- * interrupt flag bit, so an interrupt can run us just after the lcall
- * completes, but just before the swapgs takes effect.   Thus the INTR_PUSH and
- * INTR_POP paths would have to be slightly more complex to dance around
- * this problem, and end up depending explicitly on the first
- * instruction of this handler being either swapgs or cli.
- */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-sys_lcall32()
-{}
-
-#else	/* __lint */
-
-	ENTRY_NP(sys_lcall32)
-	SWAPGS				/* kernel gsbase */
-	pushq	$0
-	pushq	%rbp
-	movq	%rsp, %rbp
-	leaq	__lcall_panic_str(%rip), %rdi
-	xorl	%eax, %eax
-	call	panic
-	SET_SIZE(sys_lcall32)
-
-__lcall_panic_str:
-	.string	"sys_lcall32: shouldn't be here!"
-
-/*
- * Declare a uintptr_t which covers the entire pc range of syscall
- * handlers for the stack walkers that need this.
- */
-	.align	CPTRSIZE
-	.globl	_allsyscalls_size
-	.type	_allsyscalls_size, @object
-_allsyscalls_size:
-	.NWORD	. - _allsyscalls
-	SET_SIZE(_allsyscalls_size)
-
-#endif	/* __lint */
-
-/*
- * These are the thread context handlers for lwps using sysenter/sysexit.
- */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-sep_save(void *ksp)
-{}
-
-/*ARGSUSED*/
-void
-sep_restore(void *ksp)
-{}
-
-#else	/* __lint */
-
-	/*
-	 * setting this value to zero as we switch away causes the
-	 * stack-pointer-on-sysenter to be NULL, ensuring that we
-	 * don't silently corrupt another (preempted) thread stack
-	 * when running an lwp that (somehow) didn't get sep_restore'd
-	 */
-	ENTRY_NP(sep_save)
-	xorl	%edx, %edx
-	xorl	%eax, %eax
-	movl	$MSR_INTC_SEP_ESP, %ecx
-	wrmsr
-	ret
-	SET_SIZE(sep_save)
-
-	/*
-	 * Update the kernel stack pointer as we resume onto this cpu.
-	 */
-	ENTRY_NP(sep_restore)
-	movq	%rdi, %rdx
-	shrq	$32, %rdx
-	movl	%edi, %eax
-	movl	$MSR_INTC_SEP_ESP, %ecx
-	wrmsr
-	ret
-	SET_SIZE(sep_restore)
-
-#endif	/* __lint */
--- old/usr/src/uts/i86xpv/Makefile.files	Thu Nov 14 19:00:18 2019
+++ new/usr/src/uts/i86xpv/Makefile.files	Thu Nov 14 19:00:18 2019
@@ -154,21 +154,13 @@
 #	locore.o is special. It must be the first file relocated so that it
 #	it is relocated just where its name implies.
 #
-SPECIAL_OBJS_32 +=		\
+SPECIAL_OBJS +=			\
 	locore.o		\
 	fast_trap_asm.o		\
 	interrupt.o		\
-	syscall_asm.o
-
-SPECIAL_OBJS_64 +=		\
-	locore.o		\
-	fast_trap_asm.o		\
-	interrupt.o		\
-	syscall_asm_amd64.o	\
+	syscall_asm.o		\
 	kpti_trampolines.o
 
-SPECIAL_OBJS += $(SPECIAL_OBJS_$(CLASS))
-
 #
 # object files used to boot into full kernel
 #
@@ -254,7 +246,6 @@
 	panic_asm.o		\
 	sseblk.o		\
 	swtch.o			\
-	syscall_asm.o		\
-	syscall_asm_amd64.o
+	syscall_asm.o
 
 $(KDI_ASSYM_DEPS:%=$(OBJS_DIR)/%):	$(DSF_DIR)/$(OBJS_DIR)/kdi_assym.h
--- old/usr/src/uts/i86xpv/Makefile.i86xpv	Thu Nov 14 19:00:18 2019
+++ new/usr/src/uts/i86xpv/Makefile.i86xpv	Thu Nov 14 19:00:18 2019
@@ -25,6 +25,7 @@
 # Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 # Use is subject to license terms.
 # Copyright (c) 2013 Andrew Stormont.  All rights reserved.
+# Copyright 2019 Joyent, Inc.
 #
 
 #
@@ -97,15 +98,6 @@
 ALL_BUILDS		= $(ALL_BUILDS64)
 
 #
-#	x86 or amd64 inline templates
-#
-INLINES_32		= $(UTSBASE)/intel/ia32/ml/ia32.il \
-			  $(UTSBASE)/$(PLATFORM)/ml/ia32.il
-INLINES_64		= $(UTSBASE)/intel/amd64/ml/amd64.il \
-			  $(UTSBASE)/$(PLATFORM)/ml/amd64.il
-INLINES			+= $(INLINES_$(CLASS))
-
-#
 #	kernel-specific optimizations; override default in Makefile.master
 #
 
@@ -119,7 +111,7 @@
 
 CFLAGS			= $(CFLAGS_XARCH)
 CFLAGS			+= $(COPTIMIZE)
-CFLAGS			+= $(INLINES) -D_ASM_INLINES
+CFLAGS			+= -D_ASM_INLINES
 CFLAGS			+= $(CCMODE)
 CFLAGS			+= $(SPACEFLAG)
 CFLAGS			+= $(CCUNBOUND)
@@ -145,10 +137,7 @@
 GENASSYM_SRC	= $(UTSBASE)/i86pc/ml/genassym.c
 OFFSETS_SRC	= $(UTSBASE)/i86pc/ml/offsets.in
 
-#PLATFORM_OFFSETS_32	= $(UTSBASE)/$(PLATFORM)/ml/mach_offsets.in
-PLATFORM_OFFSETS_32	= $(UTSBASE)/i86pc/ml/mach_offsets.in
-PLATFORM_OFFSETS_64	= $(UTSBASE)/intel/amd64/ml/mach_offsets.in
-PLATFORM_OFFSETS_SRC	= $(PLATFORM_OFFSETS_$(CLASS))
+PLATFORM_OFFSETS_SRC	= $(UTSBASE)/intel/amd64/ml/mach_offsets.in
 KDI_OFFSETS_SRC		= $(UTSBASE)/intel/kdi/kdi_offsets.in
 
 #
@@ -186,7 +175,6 @@
 
 $(IF_DEBUG_OBJ)trap.o		:= DEBUG_DEFS += -DTRAPDEBUG -DTRAPTRACE
 $(IF_DEBUG_OBJ)syscall_asm.o	:= DEBUG_DEFS += -DSYSCALLTRACE -DTRAPTRACE
-$(IF_DEBUG_OBJ)syscall_asm_amd64.o := DEBUG_DEFS += -DSYSCALLTRACE -DTRAPTRACE
 $(IF_DEBUG_OBJ)fast_trap_asm.o	:= DEBUG_DEFS += -DTRAPTRACE
 $(IF_DEBUG_OBJ)interrupt.o	:= DEBUG_DEFS += -DTRAPTRACE
 $(IF_DEBUG_OBJ)intr.o		:= DEBUG_DEFS += -DTRAPTRACE
--- old/usr/src/uts/i86xpv/ml/amd64.il	Thu Nov 14 19:00:19 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,88 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-/
-/ Inline functions for the x64 kernel running on the hypervisor
-/
-
-	.inline	__hypercall0, 0
-	movq	%rdi, %rax
-	syscall
-	.end
-
-	.inline	__hypercall1, 0
-	movq	%rdi, %rax
-	movq	%rsi, %rdi		/ arg 1 
-	syscall
-	.end
-
-	.inline	__hypercall2, 0
-	movq	%rdi, %rax
-	movq	%rsi, %rdi		/ arg 1
-	movq	%rdx, %rsi		/ arg 2
-	syscall
-	.end
-
-	.inline	__hypercall3, 0
-	movq	%rdi, %rax
-	movq	%rsi, %rdi		/ arg 1
-	movq	%rdx, %rsi		/ arg 2
-	movq	%rcx, %rdx		/ arg 3
-	syscall
-	.end
-
-/*  XXPV studio bug  r10 is changed to eax by compiler */
-	.inline	__hypercall4_broken, 0
-	movq	%rdi, %rax
-	movq	%rsi, %rdi		/ arg 1
-	movq	%rdx, %rsi		/ arg 2
-	movq	%rcx, %rdx		/ arg 3
-	movq	%r8, %r10		/ r10 = 4th arg
-	syscall
-	.end
-
-	.inline	__hypercall5_broken, 0
-	movq	%rdi, %rax
-	movq	%rsi, %rdi		/ arg 1
-	movq	%rdx, %rsi		/ arg 2
-	movq	%rcx, %rdx		/ arg 3
-	movq	%r8, %r10		/ r10 = 4th arg
-	movq	%r9, %r8		/ arg 5
-	syscall
-	.end
-
-/*
- * Read the -real- TSC.
- * This is difficult to virtualize on the hypervisor given there is
- * no way to prevent preemption; thus this inline function
- * should only be used in the middle of the paravirtualized
- * implementation of tsc_read.
- */
-	.inline	__rdtsc_insn, 0
-	rdtsc
-	shlq	$32, %rdx
-	orq	%rdx, %rax
-	.end
--- old/usr/src/uts/i86xpv/ml/hyperevent.s	Thu Nov 14 19:00:19 2019
+++ new/usr/src/uts/i86xpv/ml/hyperevent.s	Thu Nov 14 19:00:19 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/asm_linkage.h>
 #include <sys/hypervisor.h>
 #include <sys/privregs.h>
@@ -36,22 +34,8 @@
 #include <sys/x86_archext.h>
 #include <sys/asm_misc.h>
 
-#if !defined(__lint)
 #include "assym.h"
-#endif
 
-#if defined(__lint)
-
-void
-xen_failsafe_callback(void)
-{}
-
-void
-xen_callback(void)
-{}
-
-#else	/* __lint */
-
 	/*
 	 * The stack frame for events is exactly that of an x86 hardware
 	 * interrupt.
@@ -246,4 +230,3 @@
 	SET_SIZE(xen_callback)
 
 #endif	/* __i386 */
-#endif	/* __lint */
--- old/usr/src/uts/i86xpv/ml/ia32.il	Thu Nov 14 19:00:19 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,101 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-/
-/ Inline functions for the x86 kernel running on the hypervisor
-/
-
-	.inline	__hypercall0, 4
-	movl	(%esp), %eax
-	int	$0x82
-	.end
-
-	.inline	__hypercall1, 8
-	pushl	%ebx
-	movl	4(%esp), %eax
-	movl	8(%esp), %ebx
-	int	$0x82
-	popl	%ebx
-	.end
-
-	.inline	__hypercall2, 12
-	pushl	%ebx
-	movl	4(%esp), %eax
-	movl	8(%esp), %ebx
-	movl	12(%esp), %ecx
-	int	$0x82
-	popl	%ebx
-	.end
-
-	.inline	__hypercall3, 16
-	pushl	%ebx
-	movl	4(%esp), %eax
-	movl	8(%esp), %ebx
-	movl	12(%esp), %ecx
-	movl	16(%esp), %edx
-	int	$0x82
-	popl	%ebx
-	.end
-
-	.inline	__hypercall4, 20
-	pushl	%ebx
-	pushl	%esi
-	movl	8(%esp), %eax
-	movl	12(%esp), %ebx
-	movl	16(%esp), %ecx
-	movl	20(%esp), %edx
-	movl	24(%esp), %esi
-	int	$0x82
-	popl	%esi
-	popl	%ebx
-	.end
-
-	.inline	__hypercall5, 24
-	pushl	%ebx
-	pushl	%esi
-	pushl	%edi
-	movl	12(%esp), %eax
-	movl	16(%esp), %ebx
-	movl	20(%esp), %ecx
-	movl	24(%esp), %edx
-	movl	28(%esp), %esi
-	movl	32(%esp), %edi
-	int	$0x82
-	popl	%edi
-	popl	%esi
-	popl	%ebx
-	.end
-
-/*
- * Read the -real- TSC.
- * This is difficult to virtualize on the hypervisor given there is
- * no way to prevent preemption; thus this inline function
- * should only be used in the middle of the paravirtualized
- * implementation of tsc_read.
- */
-	.inline	__rdtsc_insn, 0
-	rdtsc
-	.end
--- old/usr/src/uts/i86xpv/ml/panic_asm.s	Thu Nov 14 19:00:19 2019
+++ new/usr/src/uts/i86xpv/ml/panic_asm.s	Thu Nov 14 19:00:19 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/asm_linkage.h>
 #include <sys/hypervisor.h>
 #include <sys/privregs.h>
@@ -37,31 +35,8 @@
 #include <sys/asm_misc.h>
 #include <sys/panic.h>
 
-#if !defined(__lint)
 #include "assym.h"
-#endif
 
-#if defined(__lint)
-
-void
-xpv_panic_callback(void)
-{}
-
-/* ARGSUSED */
-void
-xpv_panic_setcr3(ulong_t cr3)
-{}
-
-void
-xpv_panic_reload_cr3(void)
-{}
-
-void
-xpv_resetgs(void)
-{}
-
-#else	/* __lint */
-
 #if defined(__amd64)
 	ENTRY_NP(xpv_panic_getcr3)
 	movq	%cr3, %rax
@@ -392,4 +367,3 @@
 	jmp	xpv_panic_prep
 	SET_SIZE(xpv_xmtrap)
 
-#endif	/* __lint */
--- old/usr/src/uts/i86xpv/ml/xenguest.s	Thu Nov 14 19:00:20 2019
+++ new/usr/src/uts/i86xpv/ml/xenguest.s	Thu Nov 14 19:00:20 2019
@@ -24,18 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(__lint)
-
-/*
- * Stop lint complaining about an empty compilation unit!
- * Sigh.  There should be a better way to handle this.
- */
-int __lint_xen_guest;
-
-#else	/* __lint */
-
 #include <xen/public/elfnote.h>
 
 /*
@@ -64,4 +52,3 @@
 	NOTE("Xen", XEN_ELFNOTE_PAE_MODE, .string, "yes,bimodal")
 #endif
 
-#endif /* __lint */
--- old/usr/src/uts/intel/Makefile.files	Thu Nov 14 19:00:20 2019
+++ new/usr/src/uts/intel/Makefile.files	Thu Nov 14 19:00:20 2019
@@ -63,14 +63,6 @@
 	retpoline.o
 
 #
-# 64-bit multiply/divide compiler helper routines
-# used only for ia32
-#
-
-SPECIAL_OBJS_32 +=	\
-	muldiv.o
-
-#
 #	Generic-unix Module
 #
 GENUNIX_OBJS +=		\
--- old/usr/src/uts/intel/Makefile.intel	Thu Nov 14 19:00:21 2019
+++ new/usr/src/uts/intel/Makefile.intel	Thu Nov 14 19:00:21 2019
@@ -108,13 +108,6 @@
 ALL_BUILDS		= $(ALL_BUILDS64)
 
 #
-#	x86 or amd64 inline templates
-#
-INLINES_32		= $(UTSBASE)/intel/ia32/ml/ia32.il
-INLINES_64		= $(UTSBASE)/intel/amd64/ml/amd64.il
-INLINES			+= $(INLINES_$(CLASS))
-
-#
 #	kernel-specific optimizations; override default in Makefile.master
 #
 
@@ -128,7 +121,7 @@
 
 CFLAGS			= $(CFLAGS_XARCH)
 CFLAGS			+= $(COPTIMIZE)
-CFLAGS			+= $(INLINES) -D_ASM_INLINES
+CFLAGS			+= -D_ASM_INLINES
 CFLAGS			+= $(CCMODE)
 CFLAGS			+= $(SPACEFLAG)
 CFLAGS			+= $(CCUNBOUND)
--- old/usr/src/uts/intel/Makefile.rules	Thu Nov 14 19:00:21 2019
+++ new/usr/src/uts/intel/Makefile.rules	Thu Nov 14 19:00:21 2019
@@ -41,9 +41,7 @@
 #
 # Need a way to distinguish between the ia32 and amd64 subdirs.
 #
-SUBARCH_DIR_32 = ia32
-SUBARCH_DIR_64 = amd64
-SUBARCH_DIR	= $(SUBARCH_DIR_$(CLASS))
+SUBARCH_DIR = amd64
 
 #
 #	Section 1a: C object build rules
@@ -56,9 +54,6 @@
 	$(COMPILE.c) -o $@ $<
 	$(CTFCONVERT_O)
 
-$(OBJS_DIR)/%.o:		$(SRC)/common/util/i386/%.s
-	$(COMPILE.s) -o $@ $<
-
 $(OBJS_DIR)/%.o:		$(UTSBASE)/intel/brand/sn1/%.s
 	$(COMPILE.s) -o $@ $<
 
@@ -304,189 +299,3 @@
 $(OBJS_DIR)/%.o:	$(SRC)/common/util/$(SUBARCH_DIR)/%.c
 	$(COMPILE.c) $(KRTLD_INC_PATH) $(KRTLD_CPPFLAGS) -o $@ $<
 	$(CTFCONVERT_O)
-
-
-#
-#	Section 1b: Lint `object' build rules.
-#
-$(LINTS_DIR)/%.ln:		$(SRC)/common/fs/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/util/i386/%.s
-	@($(LHEAD) $(LINT.s) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/brand/sn1/%.s
-	@($(LHEAD) $(LINT.s) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/brand/solaris10/%.s
-	@($(LHEAD) $(LINT.s) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/dtrace/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/dtrace/%.s
-	@($(LHEAD) $(LINT.s) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/zfs/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/fs/proc/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/ia32/ml/%.s
-	@($(LHEAD) $(LINT.s) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/ia32/os/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/ia32/promif/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/ia32/syscall/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/acpica/%.s
-	@($(LHEAD) $(LINT.s) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/acpica/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/events/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/hardware/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/dispatcher/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/executer/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/parser/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/namespace/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/resources/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/tables/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/utilities/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/acpica/disassembler/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/amd8111s/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/amr/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/scsi/adapters/arcmsr/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/hotplug/pcicfg/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/hotplug/pci/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/intel_nb5000/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/intel_nhm/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/ipmi/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(SRC)/common/mc/mc-amd/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/mc-amd/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/pci/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/pciex/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/dktp/controller/ata/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/dktp/dcdev/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/dktp/disk/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/dktp/drvobj/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/dktp/hba/ghd/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/dnet/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/scsi/targets/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/vgatext/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/vmxnet3s/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/io/scsi/adapters/pvscsi/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/os/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/pcbe/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/promif/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/syscall/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/common/os/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/kdi/%.c
-	@($(LHEAD) $(LINT.c) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/kdi/%.s
-	@($(LHEAD) $(LINT.s) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/intel/nskern/%.s
-	@($(LHEAD) $(LINT.s) $< $(LTAIL))
-
-#
-# krtld lints
-#
-$(LINTS_DIR)/%.ln:		$(UTSBASE)/common/krtld/%.c
-	@($(LHEAD) $(LINT.c) $(KRTLD_INC_PATH) $(KRTLD_CPPFLAGS) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:	$(UTSBASE)/intel/$(SUBARCH_DIR)/krtld/%.c
-	@($(LHEAD) $(LINT.c) $(KRTLD_INC_PATH) $(KRTLD_CPPFLAGS) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:	$(UTSBASE)/intel/$(SUBARCH_DIR)/krtld/%.s
-	@($(LHEAD) $(LINT.s) $(KRTLD_INC_PATH) $(KRTLD_CPPFLAGS) $< $(LTAIL))
-
-$(LINTS_DIR)/%.ln:	$(SRC)/common/util/$(SUBARCH_DIR)/%.c
-	@($(LHEAD) $(LINT.c) $(KRTLD_INC_PATH) $(KRTLD_CPPFLAGS) $< $(LTAIL))
-
-$(OBJS_DIR)/kobj.ln		:= CPPFLAGS += -D_DBOOT
--- old/usr/src/uts/intel/amd64/krtld/kobj_crt.s	Thu Nov 14 19:00:21 2019
+++ new/usr/src/uts/intel/amd64/krtld/kobj_crt.s	Thu Nov 14 19:00:21 2019
@@ -37,16 +37,7 @@
  *	There is NO RETURN from exitto().
  */
 
-#if defined(lint)
 
-/* ARGSUSED */
-void
-exitto(caddr_t entrypoint)
-{}
-
-#else	/* lint */
-
-
 	ENTRY(exitto)
 
 	/preserve destination in temporary register %r11
@@ -66,6 +57,4 @@
 	INDIRECT_CALL_REG(r11)
 
 	SET_SIZE(exitto)
-
-#endif
 
--- old/usr/src/uts/intel/amd64/ml/amd64.il	Thu Nov 14 19:00:22 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,218 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-/*
- * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-/*
- * Copyright 2019 Joyent, Inc.
- */
-
-/
-/ In-line functions for amd64 kernels.
-/
-
-/
-/ return current thread pointer
-/
-/ NOTE: the "0x18" should be replaced by the computed value of the
-/	offset of "cpu_thread" from the beginning of the struct cpu.
-/	Including "assym.h" does not work, however, since that stuff
-/	is PSM-specific and is only visible to the 'unix' build anyway.
-/	Same with current cpu pointer, where "0xc" should be replaced
-/	by the computed value of the offset of "cpu_self".
-/	Ugh -- what a disaster.
-/
-	.inline	threadp,0
-	movq	%gs:0x18, %rax
-	.end
-
-/
-/ return current cpu pointer
-/
-	.inline	curcpup,0
-	movq	%gs:0x10, %rax
-	.end
-
-/
-/ return caller
-/
-	.inline caller,0
-	movq	8(%rbp), %rax
-	.end
-
-/
-/ convert ipl to spl.  This is the identity function for i86
-/
-	.inline	ipltospl,0
-	movq	%rdi, %rax
-	.end
-
-/
-/ Networking byte order functions (too bad, Intel has the wrong byte order)
-/
-
-	.inline	htonll,4
-	movq	%rdi, %rax
-	bswapq	%rax
-	.end
-
-	.inline	ntohll,4
-	movq	%rdi, %rax
-	bswapq	%rax
-	.end
-
-	.inline	htonl,4
-	movl	%edi, %eax
-	bswap	%eax
-	.end
-
-	.inline	ntohl,4
-	movl	%edi, %eax
-	bswap	%eax
-	.end
-
-	.inline	htons,4
-	movl	%edi, %eax
-	bswap	%eax
-	shrl	$16, %eax
-	.end
-
-	.inline	ntohs,4
-	movl	%edi, %eax
-	bswap	%eax
-	shrl	$16, %eax
-	.end
-
-/*
- * multiply two long numbers and yield a u_lonlong_t result
- * Provided to manipulate hrtime_t values.
- */
-	/* XX64 These don't work correctly with SOS9 build 13.0 yet
-	.inline mul32, 8
-	xorl	%edx, %edx
-	movl	%edi, %eax
-	mull	%esi
-	shlq	$32, %rdx
-	orq	%rdx, %rax
-	ret
-	.end
-	*/
-/*
- * Unlock hres_lock and increment the count value. (See clock.h)
- */
-	.inline unlock_hres_lock, 0
-	lock
-	incl	hres_lock
-	.end
-
-	.inline	atomic_orb,8
-	movl	%esi, %eax
-	lock
-	orb	%al,(%rdi)
-	.end
-
-	.inline	atomic_andb,8
-	movl	%esi, %eax
-	lock
-	andb	%al,(%rdi)
-	.end
-
-/*
- * atomic inc/dec operations.
- *	void atomic_inc16(uint16_t *addr) { ++*addr; }
- *	void atomic_dec16(uint16_t *addr) { --*addr; }
- */
-	.inline	atomic_inc16,4
-	lock
-	incw	(%rdi)
-	.end
-
-	.inline	atomic_dec16,4
-	lock
-	decw	(%rdi)
-	.end
-
-/*
- * atomic bit clear
- */
-	.inline atomic_btr32,8
-	lock
-	btrl %esi, (%rdi)
-	setc %al
-	.end
-
-/*
- * Call the pause instruction.  To the Pentium 4 Xeon processor, it acts as
- * a hint that the code sequence is a busy spin-wait loop.  Without a pause
- * instruction in these loops, the P4 Xeon processor may suffer a severe
- * penalty when exiting the loop because the processor detects a possible
- * memory violation.  Inserting the pause instruction significantly reduces
- * the likelihood of a memory order violation, improving performance.
- * The pause instruction is a NOP on all other IA-32 processors.
- */
-	.inline ht_pause, 0
-	pause
-	.end
-
-/*
- * inlines for update_sregs().
- */
-        .inline __set_ds, 0
-        movw    %di, %ds
-        .end
-
-        .inline __set_es, 0
-        movw    %di, %es
-        .end
-
-        .inline __set_fs, 0
-        movw    %di, %fs
-        .end
-
-        .inline __set_gs, 0
-        movw    %di, %gs
-        .end
-
-/*
- * prefetch 64 bytes
- */
-
-	.inline	prefetch_read_many,8
-	prefetcht0	(%rdi)
-	prefetcht0	32(%rdi)
-	.end
-
-	.inline	prefetch_read_once,8
-	prefetchnta	(%rdi)
-	prefetchnta	32(%rdi)
-	.end
-
-	.inline	prefetch_write_many,8
-	prefetcht0	(%rdi)
-	prefetcht0	32(%rdi)
-	.end
-
-	.inline	prefetch_write_once,8
-	prefetcht0	(%rdi)
-	prefetcht0	32(%rdi)
-	.end
--- old/usr/src/uts/intel/brand/common/brand_solaris.s	Thu Nov 14 19:00:22 2019
+++ new/usr/src/uts/intel/brand/common/brand_solaris.s	Thu Nov 14 19:00:22 2019
@@ -32,12 +32,6 @@
  * use brand-specific #defines to replace the XXX_brand_... definitions.
  */
 
-#ifdef lint
-
-#include <sys/systm.h>
-
-#else /* !lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
 #include <sys/segments.h>
@@ -44,38 +38,8 @@
 #include "assym.h"
 #include "brand_asm.h"
 
-#endif	/* !lint */
-
-#ifdef  lint
-
-void
-XXX_brand_sysenter_callback(void)
-{
-}
-
-void
-XXX_brand_syscall_callback(void)
-{
-}
-
-#if defined(__amd64)
-void
-XXX_brand_syscall32_callback(void)
-{
-}
-#endif  /* amd64 */
-
-void
-XXX_brand_int91_callback(void)
-{
-}
-
-#else   /* !lint */
-
 #ifdef _ASM	/* The remainder of this file is only for assembly files */
 
-#if defined(__amd64)
-
 /*
  * syscall handler for 32-bit user processes:
  * See "64-BIT INTERPOSITION STACK" in brand_asm.h.
@@ -155,44 +119,4 @@
 	retq
 SET_SIZE(XXX_brand_int91_callback)
 
-#else	/* !__amd64 */
-
-/*
- * To 'return' to our user-space handler, we need to replace the iret target
- * address.  The original return address is passed back in %eax.
- * See "32-BIT INTERPOSITION STACK" and "32-BIT INT STACK" in brand_asm.h.
- */
-ENTRY(XXX_brand_syscall_callback)
-	CALLBACK_PROLOGUE(XXX_emulation_table, SPD_HANDLER, SYSCALL_REG,
-	    SCR_REG, SCR_REGB);
-	CALC_TABLE_ADDR(SCR_REG, SPD_HANDLER); /* new ret addr is in scratch */
-	mov	SCR_REG, SYSCALL_REG;	/* place new ret addr in syscallreg */
-	GET_V(SP_REG, 0, V_U_EBX, SCR_REG); /* restore scratch register */
-	add	$V_END, SP_REG;		/* restore intr stack pointer */
-	/*CSTYLED*/
-	xchg	(SP_REG), SYSCALL_REG	/* swap new and orig. return addrs */
-	jmp	nopop_sys_rtt_syscall
-9:
-	ret
-SET_SIZE(XXX_brand_syscall_callback)
-
-/*
- * To 'return' to our user-space handler, we just need to place its address
- * into %edx.  The original return address is passed back in SYSCALL_REG.
- * See "32-BIT INTERPOSITION STACK" in brand_asm.h.
- */
-ENTRY(XXX_brand_sysenter_callback)
-	CALLBACK_PROLOGUE(XXX_emulation_table, SPD_HANDLER, SYSCALL_REG,
-	    SCR_REG, SCR_REGB);
-	mov	%edx, SCR_REG;	/* save orig return addr in scr reg */
-	CALC_TABLE_ADDR(%edx, SPD_HANDLER); /* new return addr is in %edx */
-	mov	SCR_REG, SYSCALL_REG;	/* save orig return addr in %eax */
-	GET_V(SP_REG, 0, V_U_EBX, SCR_REG) /* restore scratch register */
-	sysexit
-9:
-	ret
-SET_SIZE(XXX_brand_sysenter_callback)
-
-#endif	/* !__amd64 */
 #endif	/* _ASM */
-#endif  /* !lint */
--- old/usr/src/uts/intel/dtrace/dtrace_asm.s	Thu Nov 14 19:00:22 2019
+++ new/usr/src/uts/intel/dtrace/dtrace_asm.s	Thu Nov 14 19:00:22 2019
@@ -23,55 +23,20 @@
  * Use is subject to license terms.
  */
 /*
- * Copyright 2015 Joyent, Inc.
+ * Copyright 2019 Joyent, Inc.
  */
 
 #include <sys/asm_linkage.h>
 #include <sys/regset.h>
 
-#if defined(lint)
-#include <sys/dtrace_impl.h>
-#else
 #include "assym.h"
-#endif
 
-#if defined(lint) || defined(__lint)
-
-greg_t
-dtrace_getfp(void)
-{ return (0); }
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(dtrace_getfp)
 	movq	%rbp, %rax
 	ret
 	SET_SIZE(dtrace_getfp)
 
-#elif defined(__i386)
 
-	ENTRY_NP(dtrace_getfp)
-	movl	%ebp, %eax
-	ret
-	SET_SIZE(dtrace_getfp)
-
-#endif	/* __i386 */
-#endif	/* lint */
-
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-dtrace_getvmreg(uint32_t reg, volatile uint16_t *flags)
-{ return (0); }
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(dtrace_getvmreg)
 
 	movq	%rdi, %rdx
@@ -80,51 +45,7 @@
 
 	SET_SIZE(dtrace_getvmreg)
 
-#elif defined(__i386)
 
-	ENTRY_NP(dtrace_getvmreg)
-	pushl	%ebp			/ Setup stack frame
-	movl	%esp, %ebp
-
-	movl	12(%ebp), %eax		/ Load flag pointer
-	movw	(%eax), %cx		/ Load flags
-	orw	$CPU_DTRACE_ILLOP, %cx	/ Set ILLOP
-	movw	%cx, (%eax)		/ Store flags
-
-	leave
-	ret
-	SET_SIZE(dtrace_getvmreg)
-
-#endif	/* __i386 */
-#endif	/* lint */
-
-
-#if defined(lint) || defined(__lint)
-
-uint32_t
-dtrace_cas32(uint32_t *target, uint32_t cmp, uint32_t new)
-{
-	uint32_t old;
-
-	if ((old = *target) == cmp)
-		*target = new;
-	return (old);
-}
-
-void *
-dtrace_casptr(void *target, void *cmp, void *new)
-{
-	void *old;
-
-	if ((old = *(void **)target) == cmp)
-		*(void **)target = new;
-	return (old);
-}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY(dtrace_cas32)
 	movl	%esi, %eax
 	lock
@@ -139,60 +60,11 @@
 	ret
 	SET_SIZE(dtrace_casptr)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_cas32)
-	ALTENTRY(dtrace_casptr)
-	movl	4(%esp), %edx
-	movl	8(%esp), %eax
-	movl	12(%esp), %ecx
-	lock
-	cmpxchgl %ecx, (%edx)
-	ret
-	SET_SIZE(dtrace_casptr)
-	SET_SIZE(dtrace_cas32)
-
-#endif	/* __i386 */
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uintptr_t
-dtrace_caller(int aframes)
-{
-	return (0);
-}
-
-#else	/* lint */
-
-#if defined(__amd64)
 	ENTRY(dtrace_caller)
 	movq	$-1, %rax
 	ret
 	SET_SIZE(dtrace_caller)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_caller)
-	movl	$-1, %eax
-	ret
-	SET_SIZE(dtrace_caller)
-
-#endif	/* __i386 */
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-dtrace_copy(uintptr_t src, uintptr_t dest, size_t size)
-{}
-
-#else
-
-#if defined(__amd64)
-
 	ENTRY(dtrace_copy)
 	pushq	%rbp
 	call	smap_disable
@@ -207,42 +79,6 @@
 	ret
 	SET_SIZE(dtrace_copy)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_copy)
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	%esi
-	pushl	%edi
-
-	movl	8(%ebp), %esi		/ Load source address
-	movl	12(%ebp), %edi		/ Load destination address
-	movl	16(%ebp), %ecx		/ Load count
-	repz				/ Repeat for count...
-	smovb				/   move from %ds:si to %es:di
-
-	popl	%edi
-	popl	%esi
-	movl	%ebp, %esp
-	popl	%ebp
-	ret
-	SET_SIZE(dtrace_copy)
-
-#endif	/* __i386 */
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-dtrace_copystr(uintptr_t uaddr, uintptr_t kaddr, size_t size,
-    volatile uint16_t *flags)
-{}
-
-#else
-
-#if defined(__amd64)
-
 	ENTRY(dtrace_copystr)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -269,56 +105,6 @@
 
 	SET_SIZE(dtrace_copystr)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_copystr)
-
-	pushl	%ebp			/ Setup stack frame
-	movl	%esp, %ebp
-	pushl	%ebx			/ Save registers
-	
-	movl	8(%ebp), %ebx		/ Load source address
-	movl	12(%ebp), %edx		/ Load destination address
-	movl	16(%ebp), %ecx		/ Load count
-
-0:
-	movb	(%ebx), %al		/ Load from source
-	movb	%al, (%edx)		/ Store to destination
-	incl	%ebx			/ Increment source pointer
-	incl	%edx			/ Increment destination pointer
-	decl	%ecx			/ Decrement remaining count
-	cmpb	$0, %al
-	je	2f
-	testl	$0xfff, %ecx		/ Check if count is 4k-aligned
-	jnz	1f
-	movl	20(%ebp), %eax		/ load flags pointer
-	testl	$CPU_DTRACE_BADADDR, (%eax) / load and test dtrace flags
-	jnz	2f
-1:
-	cmpl	$0, %ecx
-	jne	0b
-
-2:
-	popl	%ebx
-	movl	%ebp, %esp
-	popl	%ebp
-	ret
-
-	SET_SIZE(dtrace_copystr)
-
-#endif	/* __i386 */
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uintptr_t
-dtrace_fulword(void *addr)
-{ return (0); }
-
-#else
-#if defined(__amd64)
-
 	ENTRY(dtrace_fulword)
 	call	smap_disable
 	movq	(%rdi), %rax
@@ -326,28 +112,6 @@
 	ret
 	SET_SIZE(dtrace_fulword)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_fulword)
-	movl	4(%esp), %ecx
-	xorl	%eax, %eax
-	movl	(%ecx), %eax
-	ret
-	SET_SIZE(dtrace_fulword)
-
-#endif	/* __i386 */
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint8_t
-dtrace_fuword8_nocheck(void *addr)
-{ return (0); }
-
-#else
-#if defined(__amd64)
-
 	ENTRY(dtrace_fuword8_nocheck)
 	call	smap_disable
 	xorq	%rax, %rax
@@ -356,28 +120,6 @@
 	ret
 	SET_SIZE(dtrace_fuword8_nocheck)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_fuword8_nocheck)
-	movl	4(%esp), %ecx
-	xorl	%eax, %eax
-	movzbl	(%ecx), %eax
-	ret
-	SET_SIZE(dtrace_fuword8_nocheck)
-
-#endif	/* __i386 */
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint16_t
-dtrace_fuword16_nocheck(void *addr)
-{ return (0); }
-
-#else
-#if defined(__amd64)
-
 	ENTRY(dtrace_fuword16_nocheck)
 	call	smap_disable
 	xorq	%rax, %rax
@@ -386,28 +128,6 @@
 	ret
 	SET_SIZE(dtrace_fuword16_nocheck)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_fuword16_nocheck)
-	movl	4(%esp), %ecx
-	xorl	%eax, %eax
-	movzwl	(%ecx), %eax
-	ret
-	SET_SIZE(dtrace_fuword16_nocheck)
-
-#endif	/* __i386 */
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint32_t
-dtrace_fuword32_nocheck(void *addr)
-{ return (0); }
-
-#else
-#if defined(__amd64)
-
 	ENTRY(dtrace_fuword32_nocheck)
 	call	smap_disable
 	xorq	%rax, %rax
@@ -416,28 +136,6 @@
 	ret
 	SET_SIZE(dtrace_fuword32_nocheck)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_fuword32_nocheck)
-	movl	4(%esp), %ecx
-	xorl	%eax, %eax
-	movl	(%ecx), %eax
-	ret
-	SET_SIZE(dtrace_fuword32_nocheck)
-
-#endif	/* __i386 */
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint64_t
-dtrace_fuword64_nocheck(void *addr)
-{ return (0); }
-
-#else
-#if defined(__amd64)
-
 	ENTRY(dtrace_fuword64_nocheck)
 	call	smap_disable
 	movq	(%rdi), %rax
@@ -445,31 +143,6 @@
 	ret
 	SET_SIZE(dtrace_fuword64_nocheck)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_fuword64_nocheck)
-	movl	4(%esp), %ecx
-	xorl	%eax, %eax
-	xorl	%edx, %edx
-	movl	(%ecx), %eax
-	movl	4(%ecx), %edx
-	ret
-	SET_SIZE(dtrace_fuword64_nocheck)
-
-#endif	/* __i386 */
-#endif
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-dtrace_probe_error(dtrace_state_t *state, dtrace_epid_t epid, int which,
-    int fault, int fltoffs, uintptr_t illval)
-{}
-
-#else	/* lint */
-#if defined(__amd64)
-
 	ENTRY(dtrace_probe_error)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -487,23 +160,3 @@
 	ret
 	SET_SIZE(dtrace_probe_error)
 	
-#elif defined(__i386)
-
-	ENTRY(dtrace_probe_error)
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	0x1c(%ebp)
-	pushl	0x18(%ebp)
-	pushl	0x14(%ebp)
-	pushl	0x10(%ebp)
-	pushl	0xc(%ebp)
-	pushl	0x8(%ebp)
-	pushl	dtrace_probeid_error
-	call	dtrace_probe
-	movl	%ebp, %esp
-	popl	%ebp
-	ret
-	SET_SIZE(dtrace_probe_error)
-
-#endif	/* __i386 */
-#endif
--- old/usr/src/uts/intel/ia32/ml/copy.s	Thu Nov 14 19:00:23 2019
+++ new/usr/src/uts/intel/ia32/ml/copy.s	Thu Nov 14 19:00:23 2019
@@ -42,12 +42,7 @@
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
 
-#if defined(__lint)
-#include <sys/types.h>
-#include <sys/systm.h>
-#else	/* __lint */
 #include "assym.h"
-#endif	/* __lint */
 
 #define	KCOPY_MIN_SIZE	128	/* Must be >= 16 bytes */
 #define	XCOPY_MIN_SIZE	128	/* Must be >= 16 bytes */
@@ -143,13 +138,8 @@
  * I'm sorry about these macros, but copy.s is unsurprisingly sensitive to
  * additional call instructions.
  */
-#if defined(__amd64)
 #define	SMAP_DISABLE_COUNT	16
 #define	SMAP_ENABLE_COUNT	26
-#elif defined(__i386)
-#define	SMAP_DISABLE_COUNT	0
-#define	SMAP_ENABLE_COUNT	0
-#endif
 
 #define	SMAP_DISABLE_INSTR(ITER)		\
 	.globl	_smap_disable_patch_/**/ITER;	\
@@ -161,20 +151,9 @@
 	_smap_enable_patch_/**/ITER/**/:;	\
 	nop; nop; nop;
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-kcopy(const void *from, void *to, size_t count)
-{ return (0); }
-
-#else	/* __lint */
-
 	.globl	kernelbase
 	.globl	postbootkernelbase
 
-#if defined(__amd64)
-
 	ENTRY(kcopy)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -211,86 +190,10 @@
 	ret
 	SET_SIZE(kcopy)
 
-#elif defined(__i386)
-
-#define	ARG_FROM	8
-#define	ARG_TO		12
-#define	ARG_COUNT	16
-
-	ENTRY(kcopy)
-#ifdef DEBUG
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	postbootkernelbase, %eax
-	cmpl	%eax, ARG_FROM(%ebp)
-	jb	0f
-	cmpl	%eax, ARG_TO(%ebp)
-	jnb	1f
-0:	pushl	$.kcopy_panic_msg
-	call	panic
-1:	popl	%ebp
-#endif
-	lea	_kcopy_copyerr, %eax	/* lofault value */
-	movl	%gs:CPU_THREAD, %edx
-
-do_copy_fault:
-	pushl	%ebp
-	movl	%esp, %ebp		/* setup stack frame */
-	pushl	%esi
-	pushl	%edi			/* save registers */
-
-	movl	T_LOFAULT(%edx), %edi
-	pushl	%edi			/* save the current lofault */
-	movl	%eax, T_LOFAULT(%edx)	/* new lofault */
-
-	movl	ARG_COUNT(%ebp), %ecx
-	movl	ARG_FROM(%ebp), %esi
-	movl	ARG_TO(%ebp), %edi
-	shrl	$2, %ecx		/* word count */
-	rep
-	  smovl
-	movl	ARG_COUNT(%ebp), %ecx
-	andl	$3, %ecx		/* bytes left over */
-	rep
-	  smovb
-	xorl	%eax, %eax
-
-	/*
-	 * A fault during do_copy_fault is indicated through an errno value
-	 * in %eax and we iret from the trap handler to here.
-	 */
-_kcopy_copyerr:
-	popl	%ecx
-	popl	%edi
-	movl	%ecx, T_LOFAULT(%edx)	/* restore the original lofault */
-	popl	%esi
-	popl	%ebp
-	ret
-	SET_SIZE(kcopy)
-
 #undef	ARG_FROM
 #undef	ARG_TO
 #undef	ARG_COUNT
 
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*
- * Copy a block of storage.  Similar to kcopy but uses non-temporal
- * instructions.
- */
-
-/* ARGSUSED */
-int
-kcopy_nta(const void *from, void *to, size_t count, int copy_cached)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 #define	COPY_LOOP_INIT(src, dst, cnt)	\
 	addq	cnt, src;			\
 	addq	cnt, dst;			\
@@ -367,88 +270,6 @@
 	SET_SIZE(do_copy_fault_nta)
 	SET_SIZE(kcopy_nta)
 
-#elif defined(__i386)
-
-#define	ARG_FROM	8
-#define	ARG_TO		12
-#define	ARG_COUNT	16
-
-#define	COPY_LOOP_INIT(src, dst, cnt)	\
-	addl	cnt, src;			\
-	addl	cnt, dst;			\
-	shrl	$3, cnt;			\
-	neg	cnt
-
-#define	COPY_LOOP_BODY(src, dst, cnt)	\
-	prefetchnta	0x100(src, cnt, 8);	\
-	movl	(src, cnt, 8), %esi;		\
-	movnti	%esi, (dst, cnt, 8);		\
-	movl	0x4(src, cnt, 8), %esi;		\
-	movnti	%esi, 0x4(dst, cnt, 8);		\
-	movl	0x8(src, cnt, 8), %esi;		\
-	movnti	%esi, 0x8(dst, cnt, 8);		\
-	movl	0xc(src, cnt, 8), %esi;		\
-	movnti	%esi, 0xc(dst, cnt, 8);		\
-	addl	$2, cnt
-
-	/*
-	 * kcopy_nta is not implemented for 32-bit as no performance
-	 * improvement was shown.  We simply jump directly to kcopy
-	 * and discard the 4 arguments.
-	 */
-	ENTRY(kcopy_nta)
-	jmp	kcopy
-
-	lea	_kcopy_nta_copyerr, %eax	/* lofault value */
-	ALTENTRY(do_copy_fault_nta)
-	pushl	%ebp
-	movl	%esp, %ebp		/* setup stack frame */
-	pushl	%esi
-	pushl	%edi
-
-	movl	%gs:CPU_THREAD, %edx
-	movl	T_LOFAULT(%edx), %edi
-	pushl	%edi			/* save the current lofault */
-	movl	%eax, T_LOFAULT(%edx)	/* new lofault */
-
-	/* COPY_LOOP_BODY needs to use %esi */
-	movl	ARG_COUNT(%ebp), %ecx
-	movl	ARG_FROM(%ebp), %edi
-	movl	ARG_TO(%ebp), %eax
-	COPY_LOOP_INIT(%edi, %eax, %ecx)
-1:	COPY_LOOP_BODY(%edi, %eax, %ecx)
-	jnz	1b
-	mfence
-
-	xorl	%eax, %eax
-_kcopy_nta_copyerr:
-	popl	%ecx
-	popl	%edi
-	movl	%ecx, T_LOFAULT(%edx)	/* restore the original lofault */
-	popl	%esi
-	leave
-	ret
-	SET_SIZE(do_copy_fault_nta)
-	SET_SIZE(kcopy_nta)
-
-#undef	ARG_FROM
-#undef	ARG_TO
-#undef	ARG_COUNT
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-bcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(bcopy)
 #ifdef DEBUG
 	orq	%rdx, %rdx		/* %rdx = count */
@@ -977,55 +798,7 @@
 	SET_SIZE(bcopy_altentry)
 	SET_SIZE(bcopy)
 
-#elif defined(__i386)
 
-#define	ARG_FROM	4
-#define	ARG_TO		8
-#define	ARG_COUNT	12
-
-	ENTRY(bcopy)
-#ifdef DEBUG
-	movl	ARG_COUNT(%esp), %eax
-	orl	%eax, %eax
-	jz	1f
-	movl	postbootkernelbase, %eax
-	cmpl	%eax, ARG_FROM(%esp)
-	jb	0f
-	cmpl	%eax, ARG_TO(%esp)
-	jnb	1f
-0:	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	$.bcopy_panic_msg
-	call	panic
-1:
-#endif
-do_copy:
-	movl	%esi, %eax		/* save registers */
-	movl	%edi, %edx
-	movl	ARG_COUNT(%esp), %ecx
-	movl	ARG_FROM(%esp), %esi
-	movl	ARG_TO(%esp), %edi
-
-	shrl	$2, %ecx		/* word count */
-	rep
-	  smovl
-	movl	ARG_COUNT(%esp), %ecx
-	andl	$3, %ecx		/* bytes left over */
-	rep
-	  smovb
-	movl	%eax, %esi		/* restore registers */
-	movl	%edx, %edi
-	ret
-	SET_SIZE(bcopy)
-
-#undef	ARG_COUNT
-#undef	ARG_FROM
-#undef	ARG_TO
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
 /*
  * Zero a block of storage, returning an error code if we
  * take a kernel pagefault which cannot be resolved.
@@ -1032,17 +805,6 @@
  * Returns errno value on pagefault error, 0 if all ok
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-kzero(void *addr, size_t count)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(kzero)
 #ifdef DEBUG
         cmpq	postbootkernelbase(%rip), %rdi	/* %rdi = addr */
@@ -1073,78 +835,10 @@
 	ret
 	SET_SIZE(kzero)
 
-#elif defined(__i386)
-
-#define	ARG_ADDR	8
-#define	ARG_COUNT	12
-
-	ENTRY(kzero)
-#ifdef DEBUG
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	postbootkernelbase, %eax
-        cmpl	%eax, ARG_ADDR(%ebp)
-        jnb	0f
-        pushl   $.kzero_panic_msg
-        call    panic
-0:	popl	%ebp
-#endif
-	lea	_kzeroerr, %eax		/* kzeroerr is lofault value */
-
-	pushl	%ebp			/* save stack base */
-	movl	%esp, %ebp		/* set new stack base */
-	pushl	%edi			/* save %edi */
-
-	mov	%gs:CPU_THREAD, %edx
-	movl	T_LOFAULT(%edx), %edi
-	pushl	%edi			/* save the current lofault */
-	movl	%eax, T_LOFAULT(%edx)	/* new lofault */
-
-	movl	ARG_COUNT(%ebp), %ecx	/* get size in bytes */
-	movl	ARG_ADDR(%ebp), %edi	/* %edi <- address of bytes to clear */
-	shrl	$2, %ecx		/* Count of double words to zero */
-	xorl	%eax, %eax		/* sstol val */
-	rep
-	  sstol			/* %ecx contains words to clear (%eax=0) */
-
-	movl	ARG_COUNT(%ebp), %ecx	/* get size in bytes */
-	andl	$3, %ecx		/* do mod 4 */
-	rep
-	  sstob			/* %ecx contains residual bytes to clear */
-
-	/*
-	 * A fault during kzero is indicated through an errno value
-	 * in %eax when we iret to here.
-	 */
-_kzeroerr:
-	popl	%edi
-	movl	%edi, T_LOFAULT(%edx)	/* restore the original lofault */
-	popl	%edi
-	popl	%ebp
-	ret
-	SET_SIZE(kzero)
-
-#undef	ARG_ADDR
-#undef	ARG_COUNT
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Zero a block of storage.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-bzero(void *addr, size_t count)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(bzero)
 #ifdef DEBUG
 	cmpq	postbootkernelbase(%rip), %rdi	/* %rdi = addr */
@@ -1459,44 +1153,6 @@
 	SET_SIZE(bzero_altentry)
 	SET_SIZE(bzero)
 
-#elif defined(__i386)
-
-#define	ARG_ADDR	4
-#define	ARG_COUNT	8
-
-	ENTRY(bzero)
-#ifdef DEBUG
-	movl	postbootkernelbase, %eax
-	cmpl	%eax, ARG_ADDR(%esp)
-	jnb	0f
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	$.bzero_panic_msg
-	call	panic
-0:
-#endif
-do_zero:
-	movl	%edi, %edx
-	movl	ARG_COUNT(%esp), %ecx
-	movl	ARG_ADDR(%esp), %edi
-	shrl	$2, %ecx
-	xorl	%eax, %eax
-	rep
-	  sstol
-	movl	ARG_COUNT(%esp), %ecx
-	andl	$3, %ecx
-	rep
-	  sstob
-	movl	%edx, %edi
-	ret
-	SET_SIZE(bzero)
-
-#undef	ARG_ADDR
-#undef	ARG_COUNT
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Transfer data to and from user space -
  * Note that these routines can cause faults
@@ -1519,17 +1175,6 @@
  * Copy user data to kernel space.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-copyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY(copyin)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -1585,62 +1230,6 @@
 	ret
 	SET_SIZE(copyin)
 
-#elif defined(__i386)
-
-#define	ARG_UADDR	4
-#define	ARG_KADDR	8
-
-	ENTRY(copyin)
-	movl	kernelbase, %ecx
-#ifdef DEBUG
-	cmpl	%ecx, ARG_KADDR(%esp)
-	jnb	1f
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	$.copyin_panic_msg
-	call	panic
-1:
-#endif
-	lea	_copyin_err, %eax
-
-	movl	%gs:CPU_THREAD, %edx
-	cmpl	%ecx, ARG_UADDR(%esp)	/* test uaddr < kernelbase */
-	jb	do_copy_fault
-	jmp	3f
-
-_copyin_err:
-	popl	%ecx
-	popl	%edi
-	movl	%ecx, T_LOFAULT(%edx)	/* restore original lofault */
-	popl	%esi
-	popl	%ebp
-3:
-	movl	T_COPYOPS(%edx), %eax
-	cmpl	$0, %eax
-	jz	2f
-	jmp	*CP_COPYIN(%eax)
-
-2:	movl	$-1, %eax
-	ret
-	SET_SIZE(copyin)
-
-#undef	ARG_UADDR
-#undef	ARG_KADDR
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-xcopyin_nta(const void *uaddr, void *kaddr, size_t count, int copy_cached)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(xcopyin_nta)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -1730,95 +1319,10 @@
 	ret
 	SET_SIZE(xcopyin_nta)
 
-#elif defined(__i386)
-
-#define	ARG_UADDR	4
-#define	ARG_KADDR	8
-#define	ARG_COUNT	12
-#define	ARG_CACHED	16
-
-	.globl	use_sse_copy
-
-	ENTRY(xcopyin_nta)
-	movl	kernelbase, %ecx
-	lea	_xcopyin_err, %eax
-	movl	%gs:CPU_THREAD, %edx
-	cmpl	%ecx, ARG_UADDR(%esp)	/* test uaddr < kernelbase */
-	jae	4f
-
-	cmpl	$0, use_sse_copy	/* no sse support */
-	jz	do_copy_fault
-
-	cmpl	$0, ARG_CACHED(%esp)	/* copy_cached hint set? */
-	jnz	do_copy_fault
-
-	/*
-	 * Make sure cnt is >= XCOPY_MIN_SIZE bytes
-	 */
-	cmpl	$XCOPY_MIN_SIZE, ARG_COUNT(%esp)
-	jb	do_copy_fault
-
-	/*
-	 * Make sure src and dst are NTA_ALIGN_SIZE aligned,
-	 * count is COUNT_ALIGN_SIZE aligned.
-	 */
-	movl	ARG_UADDR(%esp), %ecx
-	orl	ARG_KADDR(%esp), %ecx
-	andl	$NTA_ALIGN_MASK, %ecx
-	orl	ARG_COUNT(%esp), %ecx
-	andl	$COUNT_ALIGN_MASK, %ecx
-	jnz	do_copy_fault
-
-	jmp	do_copy_fault_nta	/* use regular access */
-
-4:
-	movl	$EFAULT, %eax
-	jmp	3f
-
-	/*
-	 * A fault during do_copy_fault or do_copy_fault_nta is
-	 * indicated through an errno value in %eax and we iret from the
-	 * trap handler to here.
-	 */
-_xcopyin_err:
-	popl	%ecx
-	popl	%edi
-	movl	%ecx, T_LOFAULT(%edx)	/* restore original lofault */
-	popl	%esi
-	popl	%ebp
-3:
-	cmpl	$0, T_COPYOPS(%edx)
-	jz	2f
-	movl	T_COPYOPS(%edx), %eax
-	jmp	*CP_XCOPYIN(%eax)
-
-2:	rep;	ret	/* use 2 byte return instruction when branch target */
-			/* AMD Software Optimization Guide - Section 6.2 */
-	SET_SIZE(xcopyin_nta)
-
-#undef	ARG_UADDR
-#undef	ARG_KADDR
-#undef	ARG_COUNT
-#undef	ARG_CACHED
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Copy kernel data to user space.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-copyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(copyout)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -1875,61 +1379,6 @@
 	ret
 	SET_SIZE(copyout)
 
-#elif defined(__i386)
-
-#define	ARG_KADDR	4
-#define	ARG_UADDR	8
-
-	ENTRY(copyout)
-	movl	kernelbase, %ecx
-#ifdef DEBUG
-	cmpl	%ecx, ARG_KADDR(%esp)
-	jnb	1f
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	$.copyout_panic_msg
-	call	panic
-1:
-#endif
-	lea	_copyout_err, %eax
-	movl	%gs:CPU_THREAD, %edx
-	cmpl	%ecx, ARG_UADDR(%esp)	/* test uaddr < kernelbase */
-	jb	do_copy_fault
-	jmp	3f
-
-_copyout_err:
-	popl	%ecx
-	popl	%edi
-	movl	%ecx, T_LOFAULT(%edx)	/* restore original lofault */
-	popl	%esi
-	popl	%ebp
-3:
-	movl	T_COPYOPS(%edx), %eax
-	cmpl	$0, %eax
-	jz	2f
-	jmp	*CP_COPYOUT(%eax)
-
-2:	movl	$-1, %eax
-	ret
-	SET_SIZE(copyout)
-
-#undef	ARG_UADDR
-#undef	ARG_KADDR
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-xcopyout_nta(const void *kaddr, void *uaddr, size_t count, int copy_cached)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(xcopyout_nta)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -2020,94 +1469,11 @@
 	ret
 	SET_SIZE(xcopyout_nta)
 
-#elif defined(__i386)
-
-#define	ARG_KADDR	4
-#define	ARG_UADDR	8
-#define	ARG_COUNT	12
-#define	ARG_CACHED	16
-
-	ENTRY(xcopyout_nta)
-	movl	kernelbase, %ecx
-	lea	_xcopyout_err, %eax
-	movl	%gs:CPU_THREAD, %edx
-	cmpl	%ecx, ARG_UADDR(%esp)	/* test uaddr < kernelbase */
-	jae	4f
-
-	cmpl	$0, use_sse_copy	/* no sse support */
-	jz	do_copy_fault
-
-	cmpl	$0, ARG_CACHED(%esp)	/* copy_cached hint set? */
-	jnz	do_copy_fault
-
-	/*
-	 * Make sure cnt is >= XCOPY_MIN_SIZE bytes
-	 */
-	cmpl	$XCOPY_MIN_SIZE, %edx
-	jb	do_copy_fault
-
-	/*
-	 * Make sure src and dst are NTA_ALIGN_SIZE aligned,
-	 * count is COUNT_ALIGN_SIZE aligned.
-	 */
-	movl	ARG_UADDR(%esp), %ecx
-	orl	ARG_KADDR(%esp), %ecx
-	andl	$NTA_ALIGN_MASK, %ecx
-	orl	ARG_COUNT(%esp), %ecx
-	andl	$COUNT_ALIGN_MASK, %ecx
-	jnz	do_copy_fault
-	jmp	do_copy_fault_nta
-
-4:
-	movl	$EFAULT, %eax
-	jmp	3f
-
-	/*
-	 * A fault during do_copy_fault or do_copy_fault_nta is
-	 * indicated through an errno value in %eax and we iret from the
-	 * trap handler to here.
-	 */
-_xcopyout_err:
-	/ restore the original lofault
-	popl	%ecx
-	popl	%edi
-	movl	%ecx, T_LOFAULT(%edx)	/ original lofault
-	popl	%esi
-	popl	%ebp
-3:
-	cmpl	$0, T_COPYOPS(%edx)
-	jz	2f
-	movl	T_COPYOPS(%edx), %eax
-	jmp	*CP_XCOPYOUT(%eax)
-
-2:	rep;	ret	/* use 2 byte return instruction when branch target */
-			/* AMD Software Optimization Guide - Section 6.2 */
-	SET_SIZE(xcopyout_nta)
-
-#undef	ARG_UADDR
-#undef	ARG_KADDR
-#undef	ARG_COUNT
-#undef	ARG_CACHED
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Copy a null terminated string from one point to another in
  * the kernel address space.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-copystr(const char *from, char *to, size_t maxlength, size_t *lencopied)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(copystr)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -2172,109 +1538,11 @@
 	ret
 	SET_SIZE(copystr)
 
-#elif defined(__i386)
-
-#define	ARG_FROM	8
-#define	ARG_TO		12
-#define	ARG_MAXLEN	16
-#define	ARG_LENCOPIED	20
-
-	ENTRY(copystr)
-#ifdef DEBUG
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	kernelbase, %eax
-	cmpl	%eax, ARG_FROM(%esp)
-	jb	0f
-	cmpl	%eax, ARG_TO(%esp)
-	jnb	1f
-0:	pushl	$.copystr_panic_msg
-	call	panic
-1:	popl	%ebp
-#endif
-	/* get the current lofault address */
-	movl	%gs:CPU_THREAD, %eax
-	movl	T_LOFAULT(%eax), %eax
-do_copystr:
-	pushl	%ebp			/* setup stack frame */
-	movl	%esp, %ebp
-	pushl	%ebx			/* save registers */
-	pushl	%edi
-
-	movl	%gs:CPU_THREAD, %ebx
-	movl	T_LOFAULT(%ebx), %edi
-	pushl	%edi			/* save the current lofault */
-	movl	%eax, T_LOFAULT(%ebx)	/* new lofault */
-
-	movl	ARG_MAXLEN(%ebp), %ecx
-	cmpl	$0, %ecx
-	je	copystr_enametoolong	/* maxlength == 0 */
-
-	movl	ARG_FROM(%ebp), %ebx	/* source address */
-	movl	ARG_TO(%ebp), %edx	/* destination address */
-
-copystr_loop:
-	decl	%ecx
-	movb	(%ebx), %al
-	incl	%ebx
-	movb	%al, (%edx)
-	incl	%edx
-	cmpb	$0, %al
-	je	copystr_null		/* null char */
-	cmpl	$0, %ecx
-	jne	copystr_loop
-
-copystr_enametoolong:
-	movl	$ENAMETOOLONG, %eax
-	jmp	copystr_out
-
-copystr_null:
-	xorl	%eax, %eax		/* no error */
-
-copystr_out:
-	cmpl	$0, ARG_LENCOPIED(%ebp)	/* want length? */
-	je	copystr_done		/* no */
-	movl	ARG_MAXLEN(%ebp), %edx
-	subl	%ecx, %edx		/* compute length and store it */
-	movl	ARG_LENCOPIED(%ebp), %ecx
-	movl	%edx, (%ecx)
-
-copystr_done:
-	popl	%edi
-	movl	%gs:CPU_THREAD, %ebx
-	movl	%edi, T_LOFAULT(%ebx)	/* restore the original lofault */
-
-	popl	%edi
-	popl	%ebx
-	popl	%ebp
-	ret
-	SET_SIZE(copystr)
-
-#undef	ARG_FROM
-#undef	ARG_TO
-#undef	ARG_MAXLEN
-#undef	ARG_LENCOPIED
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Copy a null terminated string from the user address space into
  * the kernel address space.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-copyinstr(const char *uaddr, char *kaddr, size_t maxlength,
-    size_t *lencopied)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(copyinstr)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -2336,69 +1604,11 @@
 	ret
 	SET_SIZE(copyinstr)
 
-#elif defined(__i386)
-
-#define	ARG_UADDR	4
-#define	ARG_KADDR	8
-
-	ENTRY(copyinstr)
-	movl	kernelbase, %ecx
-#ifdef DEBUG
-	cmpl	%ecx, ARG_KADDR(%esp)
-	jnb	1f
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	$.copyinstr_panic_msg
-	call	panic
-1:
-#endif
-	lea	_copyinstr_error, %eax
-	cmpl	%ecx, ARG_UADDR(%esp)	/* test uaddr < kernelbase */
-	jb	do_copystr
-	movl	%gs:CPU_THREAD, %edx
-	jmp	3f
-
-_copyinstr_error:
-	popl	%edi
-	movl	%gs:CPU_THREAD, %edx
-	movl	%edi, T_LOFAULT(%edx)	/* original lofault */
-
-	popl	%edi
-	popl	%ebx
-	popl	%ebp
-3:
-	movl	T_COPYOPS(%edx), %eax
-	cmpl	$0, %eax
-	jz	2f
-	jmp	*CP_COPYINSTR(%eax)
-
-2:	movl	$EFAULT, %eax		/* return EFAULT */
-	ret
-	SET_SIZE(copyinstr)
-
-#undef	ARG_UADDR
-#undef	ARG_KADDR
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Copy a null terminated string from the kernel
  * address space to the user address space.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-copyoutstr(const char *kaddr, char *uaddr, size_t maxlength,
-    size_t *lencopied)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(copyoutstr)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -2459,87 +1669,11 @@
 	ret
 	SET_SIZE(copyoutstr)
 
-#elif defined(__i386)
-
-#define	ARG_KADDR	4
-#define	ARG_UADDR	8
-
-	ENTRY(copyoutstr)
-	movl	kernelbase, %ecx
-#ifdef DEBUG
-	cmpl	%ecx, ARG_KADDR(%esp)
-	jnb	1f
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	$.copyoutstr_panic_msg
-	call	panic
-1:
-#endif
-	lea	_copyoutstr_error, %eax
-	cmpl	%ecx, ARG_UADDR(%esp)	/* test uaddr < kernelbase */
-	jb	do_copystr
-	movl	%gs:CPU_THREAD, %edx
-	jmp	3f
-
-_copyoutstr_error:
-	popl	%edi
-	movl	%gs:CPU_THREAD, %edx
-	movl	%edi, T_LOFAULT(%edx)	/* restore the original lofault */
-
-	popl	%edi
-	popl	%ebx
-	popl	%ebp
-3:
-	movl	T_COPYOPS(%edx), %eax
-	cmpl	$0, %eax
-	jz	2f
-	jmp	*CP_COPYOUTSTR(%eax)
-
-2:	movl	$EFAULT, %eax		/* return EFAULT */
-	ret
-	SET_SIZE(copyoutstr)
-
-#undef	ARG_KADDR
-#undef	ARG_UADDR
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Since all of the fuword() variants are so similar, we have a macro to spit
  * them out.  This allows us to create DTrace-unobservable functions easily.
  */
 
-#if defined(__lint)
-
-#if defined(__amd64)
-
-/* ARGSUSED */
-int
-fuword64(const void *addr, uint64_t *dst)
-{ return (0); }
-
-#endif
-
-/* ARGSUSED */
-int
-fuword32(const void *addr, uint32_t *dst)
-{ return (0); }
-
-/* ARGSUSED */
-int
-fuword16(const void *addr, uint16_t *dst)
-{ return (0); }
-
-/* ARGSUSED */
-int
-fuword8(const void *addr, uint8_t *dst)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 /*
  * Note that we don't save and reload the arguments here
  * because their values are not altered in the copy path.
@@ -2580,79 +1714,12 @@
 	FUWORD(fuword16, movw, %ax, CP_FUWORD16,10,14,15)
 	FUWORD(fuword8, movb, %al, CP_FUWORD8,11,16,17)
 
-#elif defined(__i386)
-
-#define	FUWORD(NAME, INSTR, REG, COPYOP)	\
-	ENTRY(NAME)				\
-	movl	%gs:CPU_THREAD, %ecx;		\
-	movl	kernelbase, %eax;		\
-	cmpl	%eax, 4(%esp);			\
-	jae	1f;				\
-	lea	_flt_/**/NAME, %edx;		\
-	movl	%edx, T_LOFAULT(%ecx);		\
-	movl	4(%esp), %eax;			\
-	movl	8(%esp), %edx;			\
-	INSTR	(%eax), REG;			\
-	movl	$0, T_LOFAULT(%ecx);		\
-	INSTR	REG, (%edx);			\
-	xorl	%eax, %eax;			\
-	ret;					\
-_flt_/**/NAME:					\
-	movl	$0, T_LOFAULT(%ecx);		\
-1:						\
-	movl	T_COPYOPS(%ecx), %eax;		\
-	cmpl	$0, %eax;			\
-	jz	2f;				\
-	jmp	*COPYOP(%eax);			\
-2:						\
-	movl	$-1, %eax;			\
-	ret;					\
-	SET_SIZE(NAME)
-
-	FUWORD(fuword32, movl, %eax, CP_FUWORD32)
-	FUWORD(fuword16, movw, %ax, CP_FUWORD16)
-	FUWORD(fuword8, movb, %al, CP_FUWORD8)
-
-#endif	/* __i386 */
-
 #undef	FUWORD
 
-#endif	/* __lint */
-
 /*
  * Set user word.
  */
 
-#if defined(__lint)
-
-#if defined(__amd64)
-
-/* ARGSUSED */
-int
-suword64(void *addr, uint64_t value)
-{ return (0); }
-
-#endif
-
-/* ARGSUSED */
-int
-suword32(void *addr, uint32_t value)
-{ return (0); }
-
-/* ARGSUSED */
-int
-suword16(void *addr, uint16_t value)
-{ return (0); }
-
-/* ARGSUSED */
-int
-suword8(void *addr, uint8_t value)
-{ return (0); }
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 /*
  * Note that we don't save and reload the arguments here
  * because their values are not altered in the copy path.
@@ -2690,75 +1757,8 @@
 	SUWORD(suword16, movw, %si, CP_SUWORD16,14,22,23)
 	SUWORD(suword8, movb, %sil, CP_SUWORD8,15,24,25)
 
-#elif defined(__i386)
-
-#define	SUWORD(NAME, INSTR, REG, COPYOP)	\
-	ENTRY(NAME)				\
-	movl	%gs:CPU_THREAD, %ecx;		\
-	movl	kernelbase, %eax;		\
-	cmpl	%eax, 4(%esp);			\
-	jae	1f;				\
-	lea	_flt_/**/NAME, %edx;		\
-	movl	%edx, T_LOFAULT(%ecx);		\
-	movl	4(%esp), %eax;			\
-	movl	8(%esp), %edx;			\
-	INSTR	REG, (%eax);			\
-	movl	$0, T_LOFAULT(%ecx);		\
-	xorl	%eax, %eax;			\
-	ret;					\
-_flt_/**/NAME:					\
-	movl	$0, T_LOFAULT(%ecx);		\
-1:						\
-	movl	T_COPYOPS(%ecx), %eax;		\
-	cmpl	$0, %eax;			\
-	jz	3f;				\
-	movl	COPYOP(%eax), %ecx;		\
-	jmp	*%ecx;				\
-3:						\
-	movl	$-1, %eax;			\
-	ret;					\
-	SET_SIZE(NAME)
-
-	SUWORD(suword32, movl, %edx, CP_SUWORD32)
-	SUWORD(suword16, movw, %dx, CP_SUWORD16)
-	SUWORD(suword8, movb, %dl, CP_SUWORD8)
-
-#endif	/* __i386 */
-
 #undef	SUWORD
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-#if defined(__amd64)
-
-/*ARGSUSED*/
-void
-fuword64_noerr(const void *addr, uint64_t *dst)
-{}
-
-#endif
-
-/*ARGSUSED*/
-void
-fuword32_noerr(const void *addr, uint32_t *dst)
-{}
-
-/*ARGSUSED*/
-void
-fuword8_noerr(const void *addr, uint8_t *dst)
-{}
-
-/*ARGSUSED*/
-void
-fuword16_noerr(const void *addr, uint16_t *dst)
-{}
-
-#else   /* __lint */
-
-#if defined(__amd64)
-
 #define	FUWORD_NOERR(NAME, INSTR, REG)		\
 	ENTRY(NAME)				\
 	cmpq	kernelbase(%rip), %rdi;		\
@@ -2773,60 +1773,8 @@
 	FUWORD_NOERR(fuword16_noerr, movw, %ax)
 	FUWORD_NOERR(fuword8_noerr, movb, %al)
 
-#elif defined(__i386)
-
-#define	FUWORD_NOERR(NAME, INSTR, REG)		\
-	ENTRY(NAME)				\
-	movl	4(%esp), %eax;			\
-	cmpl	kernelbase, %eax;		\
-	jb	1f;				\
-	movl	kernelbase, %eax;		\
-1:	movl	8(%esp), %edx;			\
-	INSTR	(%eax), REG;			\
-	INSTR	REG, (%edx);			\
-	ret;					\
-	SET_SIZE(NAME)
-
-	FUWORD_NOERR(fuword32_noerr, movl, %ecx)
-	FUWORD_NOERR(fuword16_noerr, movw, %cx)
-	FUWORD_NOERR(fuword8_noerr, movb, %cl)
-
-#endif	/* __i386 */
-
 #undef	FUWORD_NOERR
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-#if defined(__amd64)
-
-/*ARGSUSED*/
-void
-suword64_noerr(void *addr, uint64_t value)
-{}
-
-#endif
-
-/*ARGSUSED*/
-void
-suword32_noerr(void *addr, uint32_t value)
-{}
-
-/*ARGSUSED*/
-void
-suword16_noerr(void *addr, uint16_t value)
-{}
-
-/*ARGSUSED*/
-void
-suword8_noerr(void *addr, uint8_t value)
-{}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 #define	SUWORD_NOERR(NAME, INSTR, REG)		\
 	ENTRY(NAME)				\
 	cmpq	kernelbase(%rip), %rdi;		\
@@ -2840,72 +1788,14 @@
 	SUWORD_NOERR(suword16_noerr, movw, %si)
 	SUWORD_NOERR(suword8_noerr, movb, %sil)
 
-#elif defined(__i386)
-
-#define	SUWORD_NOERR(NAME, INSTR, REG)		\
-	ENTRY(NAME)				\
-	movl	4(%esp), %eax;			\
-	cmpl	kernelbase, %eax;		\
-	jb	1f;				\
-	movl	kernelbase, %eax;		\
-1:						\
-	movl	8(%esp), %edx;			\
-	INSTR	REG, (%eax);			\
-	ret;					\
-	SET_SIZE(NAME)
-
-	SUWORD_NOERR(suword32_noerr, movl, %edx)
-	SUWORD_NOERR(suword16_noerr, movw, %dx)
-	SUWORD_NOERR(suword8_noerr, movb, %dl)
-
-#endif	/* __i386 */
-
 #undef	SUWORD_NOERR
 
-#endif	/* lint */
 
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-int
-subyte(void *addr, uchar_t value)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-subyte_noerr(void *addr, uchar_t value)
-{}
-
-/*ARGSUSED*/
-int
-fulword(const void *addr, ulong_t *valuep)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-fulword_noerr(const void *addr, ulong_t *valuep)
-{}
-
-/*ARGSUSED*/
-int
-sulword(void *addr, ulong_t valuep)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-sulword_noerr(void *addr, ulong_t valuep)
-{}
-
-#else
-
 	.weak	subyte
 	subyte=suword8
 	.weak	subyte_noerr
 	subyte_noerr=suword8_noerr
 
-#if defined(__amd64)
-
 	.weak	fulword
 	fulword=fuword64
 	.weak	fulword_noerr
@@ -2915,69 +1805,6 @@
 	.weak	sulword_noerr
 	sulword_noerr=suword64_noerr
 
-#elif defined(__i386)
-
-	.weak	fulword
-	fulword=fuword32
-	.weak	fulword_noerr
-	fulword_noerr=fuword32_noerr
-	.weak	sulword
-	sulword=suword32
-	.weak	sulword_noerr
-	sulword_noerr=suword32_noerr
-
-#endif /* __i386 */
-
-#endif /* __lint */
-
-#if defined(__lint)
-
-/*
- * Copy a block of storage - must not overlap (from + len <= to).
- * No fault handler installed (to be called under on_fault())
- */
-
-/* ARGSUSED */
-void
-copyout_noerr(const void *kfrom, void *uto, size_t count)
-{}
-
-/* ARGSUSED */
-void
-copyin_noerr(const void *ufrom, void *kto, size_t count)
-{}
-
-/*
- * Zero a block of storage in user space
- */
-
-/* ARGSUSED */
-void
-uzero(void *addr, size_t count)
-{}
-
-/*
- * copy a block of storage in user space
- */
-
-/* ARGSUSED */
-void
-ucopy(const void *ufrom, void *uto, size_t ulength)
-{}
-
-/*
- * copy a string in user space
- */
-
-/* ARGSUSED */
-void
-ucopystr(const char *ufrom, char *uto, size_t umaxlength, size_t *lencopied)
-{}
-
-#else /* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(copyin_noerr)
 	movq	kernelbase(%rip), %rax
 #ifdef DEBUG
@@ -3045,77 +1872,7 @@
 	jmp	do_copystr
 	SET_SIZE(ucopystr)
 
-#elif defined(__i386)
-
-	ENTRY(copyin_noerr)
-	movl	kernelbase, %eax
 #ifdef DEBUG
-	cmpl	%eax, 8(%esp)
-	jae	1f
-	pushl	$.cpyin_ne_pmsg
-	call	panic
-1:
-#endif
-	cmpl	%eax, 4(%esp)
-	jb	do_copy
-	movl	%eax, 4(%esp)	/* force fault at kernelbase */
-	jmp	do_copy
-	SET_SIZE(copyin_noerr)
-
-	ENTRY(copyout_noerr)
-	movl	kernelbase, %eax
-#ifdef DEBUG
-	cmpl	%eax, 4(%esp)
-	jae	1f
-	pushl	$.cpyout_ne_pmsg
-	call	panic
-1:
-#endif
-	cmpl	%eax, 8(%esp)
-	jb	do_copy
-	movl	%eax, 8(%esp)	/* force fault at kernelbase */
-	jmp	do_copy
-	SET_SIZE(copyout_noerr)
-
-	ENTRY(uzero)
-	movl	kernelbase, %eax
-	cmpl	%eax, 4(%esp)
-	jb	do_zero
-	movl	%eax, 4(%esp)	/* force fault at kernelbase */
-	jmp	do_zero
-	SET_SIZE(uzero)
-
-	ENTRY(ucopy)
-	movl	kernelbase, %eax
-	cmpl	%eax, 4(%esp)
-	jb	1f
-	movl	%eax, 4(%esp)	/* force fault at kernelbase */
-1:
-	cmpl	%eax, 8(%esp)
-	jb	do_copy
-	movl	%eax, 8(%esp)	/* force fault at kernelbase */
-	jmp	do_copy
-	SET_SIZE(ucopy)
-
-	ENTRY(ucopystr)
-	movl	kernelbase, %eax
-	cmpl	%eax, 4(%esp)
-	jb	1f
-	movl	%eax, 4(%esp)	/* force fault at kernelbase */
-1:
-	cmpl	%eax, 8(%esp)
-	jb	2f
-	movl	%eax, 8(%esp)	/* force fault at kernelbase */
-2:
-	/* do_copystr expects the lofault address in %eax */
-	movl	%gs:CPU_THREAD, %eax
-	movl	T_LOFAULT(%eax), %eax
-	jmp	do_copystr
-	SET_SIZE(ucopystr)
-
-#endif	/* __i386 */
-
-#ifdef DEBUG
 	.data
 .kcopy_panic_msg:
 	.string "kcopy: arguments below kernelbase"
@@ -3145,8 +1902,6 @@
 	.string "copyout_noerr: argument not in kernel address space"
 #endif
 
-#endif	/* __lint */
-
 /*
  * These functions are used for SMAP, supervisor mode access protection. They
  * are hotpatched to become real instructions when the system starts up which is
@@ -3157,19 +1912,6 @@
  * out of paranoia, the kernel will likely call it at several points.
  */
 
-#if defined(__lint)
-
-void
-smap_enable(void)
-{}
-
-void
-smap_disable(void)
-{}
-
-#else
-
-#if defined (__amd64) || defined(__i386)
 	ENTRY(smap_disable)
 	nop
 	nop
@@ -3184,12 +1926,6 @@
 	ret
 	SET_SIZE(smap_enable)
 
-#endif /* __amd64 || __i386 */
-
-#endif /* __lint */
-
-#ifndef __lint
-
 .data
 .align	4
 .globl	_smap_enable_patch_count
@@ -3203,5 +1939,3 @@
 .size	_smap_disable_patch_count, 4
 _smap_disable_patch_count:
 	.long SMAP_DISABLE_COUNT
-
-#endif /* __lint */
--- old/usr/src/uts/intel/ia32/ml/ddi_i86_asm.s	Thu Nov 14 19:00:23 2019
+++ new/usr/src/uts/intel/ia32/ml/ddi_i86_asm.s	Thu Nov 14 19:00:23 2019
@@ -28,250 +28,10 @@
  * Copyright 2019 Joyent, Inc.
  */
 
-#if defined(lint) || defined(__lint)
-#include <sys/types.h>
-#include <sys/sunddi.h>
-#else
 #include <sys/asm_linkage.h>
 #include <sys/asm_misc.h>
 #include "assym.h"
-#endif
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint8_t
-ddi_get8(ddi_acc_handle_t handle, uint8_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint8_t
-ddi_mem_get8(ddi_acc_handle_t handle, uint8_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint8_t
-ddi_io_get8(ddi_acc_handle_t handle, uint8_t *dev_addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-ddi_get16(ddi_acc_handle_t handle, uint16_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-ddi_mem_get16(ddi_acc_handle_t handle, uint16_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-ddi_io_get16(ddi_acc_handle_t handle, uint16_t *dev_addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-ddi_get32(ddi_acc_handle_t handle, uint32_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-ddi_mem_get32(ddi_acc_handle_t handle, uint32_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-ddi_io_get32(ddi_acc_handle_t handle, uint32_t *dev_addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint64_t
-ddi_get64(ddi_acc_handle_t handle, uint64_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint64_t
-ddi_mem_get64(ddi_acc_handle_t handle, uint64_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-void
-ddi_put8(ddi_acc_handle_t handle, uint8_t *addr, uint8_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_put8(ddi_acc_handle_t handle, uint8_t *dev_addr, uint8_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_io_put8(ddi_acc_handle_t handle, uint8_t *dev_addr, uint8_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_put16(ddi_acc_handle_t handle, uint16_t *addr, uint16_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_put16(ddi_acc_handle_t handle, uint16_t *dev_addr, uint16_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_io_put16(ddi_acc_handle_t handle, uint16_t *dev_addr, uint16_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_put32(ddi_acc_handle_t handle, uint32_t *addr, uint32_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_put32(ddi_acc_handle_t handle, uint32_t *dev_addr, uint32_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_io_put32(ddi_acc_handle_t handle, uint32_t *dev_addr, uint32_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_put64(ddi_acc_handle_t handle, uint64_t *addr, uint64_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_put64(ddi_acc_handle_t handle, uint64_t *dev_addr, uint64_t value)
-{}
-
-/*ARGSUSED*/
-void
-ddi_rep_get8(ddi_acc_handle_t handle, uint8_t *host_addr, uint8_t *dev_addr,
-    size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_rep_get16(ddi_acc_handle_t handle, uint16_t *host_addr, uint16_t *dev_addr,
-    size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_rep_get32(ddi_acc_handle_t handle, uint32_t *host_addr, uint32_t *dev_addr,
-    size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_rep_get64(ddi_acc_handle_t handle, uint64_t *host_addr, uint64_t *dev_addr,
-    size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_rep_put8(ddi_acc_handle_t handle, uint8_t *host_addr, uint8_t *dev_addr,
-    size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_rep_put16(ddi_acc_handle_t handle, uint16_t *host_addr, uint16_t *dev_addr,
-    size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_rep_put32(ddi_acc_handle_t handle, uint32_t *host_addr, uint32_t *dev_addr,
-    size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_rep_put64(ddi_acc_handle_t handle, uint64_t *host_addr, uint64_t *dev_addr,
-    size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_get8(ddi_acc_handle_t handle, uint8_t *host_addr,
-    uint8_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_get16(ddi_acc_handle_t handle, uint16_t *host_addr,
-    uint16_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_get32(ddi_acc_handle_t handle, uint32_t *host_addr,
-    uint32_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_get64(ddi_acc_handle_t handle, uint64_t *host_addr,
-    uint64_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_put8(ddi_acc_handle_t handle, uint8_t *host_addr,
-    uint8_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_put16(ddi_acc_handle_t handle, uint16_t *host_addr,
-    uint16_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_put32(ddi_acc_handle_t handle, uint32_t *host_addr,
-    uint32_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_put64(ddi_acc_handle_t handle, uint64_t *host_addr,
-    uint64_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-#else	/* lint */
-
-
-#if defined(__amd64)
-
 	ENTRY(ddi_get8)
 	ALTENTRY(ddi_getb)
 	ALTENTRY(ddi_mem_getb)
@@ -300,41 +60,7 @@
 	SET_SIZE(ddi_io_getb)
 	SET_SIZE(ddi_io_get8)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_get8)
-	ALTENTRY(ddi_getb)
-	ALTENTRY(ddi_mem_getb)
-	ALTENTRY(ddi_mem_get8)
-	ALTENTRY(ddi_io_getb)
-	ALTENTRY(ddi_io_get8)
-	movl	4(%esp), %eax
-	movl	ACC_ATTR(%eax), %ecx
-	cmpl	$_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %ecx
-	jne	1f
-	movl	8(%esp), %edx
-	xorl	%eax, %eax
-	inb	(%dx)
-	ret
-1:
-	cmpl	$_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %ecx
-	jne	2f
-	movl	8(%esp), %eax
-	movzbl	(%eax), %eax
-	ret
-2:
-	jmp	*ACC_GETB(%eax)
-	SET_SIZE(ddi_get8)
-	SET_SIZE(ddi_getb)
-	SET_SIZE(ddi_mem_getb)
-	SET_SIZE(ddi_mem_get8)
-	SET_SIZE(ddi_io_getb)
-	SET_SIZE(ddi_io_get8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_get16)
 	ALTENTRY(ddi_getw)
 	ALTENTRY(ddi_mem_getw)
@@ -363,41 +89,7 @@
 	SET_SIZE(ddi_io_getw)
 	SET_SIZE(ddi_io_get16)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_get16)
-	ALTENTRY(ddi_getw)
-	ALTENTRY(ddi_mem_getw)
-	ALTENTRY(ddi_mem_get16)
-	ALTENTRY(ddi_io_getw)
-	ALTENTRY(ddi_io_get16)
-	movl	4(%esp), %eax
-	movl	ACC_ATTR(%eax), %ecx
-	cmpl	$_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %ecx
-	jne	3f
-	movl	8(%esp), %edx
-	xorl	%eax, %eax
-	inw	(%dx)
-	ret
-3:
-	cmpl	$_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %ecx
-	jne	4f
-	movl	8(%esp), %eax
-	movzwl	(%eax), %eax
-	ret
-4:
-	jmp	*ACC_GETW(%eax)
-	SET_SIZE(ddi_get16)
-	SET_SIZE(ddi_getw)
-	SET_SIZE(ddi_mem_getw)
-	SET_SIZE(ddi_mem_get16)
-	SET_SIZE(ddi_io_getw)
-	SET_SIZE(ddi_io_get16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_get32)
 	ALTENTRY(ddi_getl)
 	ALTENTRY(ddi_mem_getl)
@@ -425,40 +117,7 @@
 	SET_SIZE(ddi_io_getl)
 	SET_SIZE(ddi_io_get32)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_get32)
-	ALTENTRY(ddi_getl)
-	ALTENTRY(ddi_mem_getl)
-	ALTENTRY(ddi_mem_get32)
-	ALTENTRY(ddi_io_getl)
-	ALTENTRY(ddi_io_get32)
-	movl	4(%esp), %eax
-	movl	ACC_ATTR(%eax), %ecx
-	cmpl	$_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %ecx
-	jne	5f
-	movl	8(%esp), %edx
-	inl	(%dx)
-	ret
-5:
-	cmpl	$_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %ecx
-	jne	6f
-	movl	8(%esp), %eax
-	movl	(%eax), %eax
-	ret
-6:
-	jmp	*ACC_GETL(%eax)
-	SET_SIZE(ddi_get32)
-	SET_SIZE(ddi_getl)
-	SET_SIZE(ddi_mem_getl)
-	SET_SIZE(ddi_mem_get32)
-	SET_SIZE(ddi_io_getl)
-	SET_SIZE(ddi_io_get32)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_get64)
 	ALTENTRY(ddi_getll)
 	ALTENTRY(ddi_mem_getll)
@@ -470,23 +129,7 @@
 	SET_SIZE(ddi_mem_getll)
 	SET_SIZE(ddi_mem_get64)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_get64)
-	ALTENTRY(ddi_getll)
-	ALTENTRY(ddi_mem_getll)
-	ALTENTRY(ddi_mem_get64)
-	movl	4(%esp), %eax
-	jmp	*ACC_GETLL(%eax)
-	SET_SIZE(ddi_get64)
-	SET_SIZE(ddi_getll)
-	SET_SIZE(ddi_mem_getll)
-	SET_SIZE(ddi_mem_get64)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_put8)
 	ALTENTRY(ddi_putb)
 	ALTENTRY(ddi_mem_putb)
@@ -515,42 +158,7 @@
 	SET_SIZE(ddi_io_putb)
 	SET_SIZE(ddi_io_put8)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_put8)
-	ALTENTRY(ddi_putb)
-	ALTENTRY(ddi_mem_putb)
-	ALTENTRY(ddi_mem_put8)
-	ALTENTRY(ddi_io_putb)
-	ALTENTRY(ddi_io_put8)
-	movl	4(%esp), %eax
-	movl	ACC_ATTR(%eax), %ecx
-	cmpl	$_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %ecx
-	jne	7f
-	movl	12(%esp), %eax
-	movl	8(%esp), %edx
-	outb	(%dx)
-	ret
-7:
-	cmpl	$_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %ecx
-	jne	8f
-	movl	8(%esp), %eax
-	movl	12(%esp), %ecx
-	movb	%cl, (%eax)
-	ret
-8:
-	jmp	*ACC_PUTB(%eax)
-	SET_SIZE(ddi_put8)
-	SET_SIZE(ddi_putb)
-	SET_SIZE(ddi_mem_putb)
-	SET_SIZE(ddi_mem_put8)
-	SET_SIZE(ddi_io_putb)
-	SET_SIZE(ddi_io_put8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_put16)
 	ALTENTRY(ddi_putw)
 	ALTENTRY(ddi_mem_putw)
@@ -579,42 +187,7 @@
 	SET_SIZE(ddi_io_putw)
 	SET_SIZE(ddi_io_put16)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_put16)
-	ALTENTRY(ddi_putw)
-	ALTENTRY(ddi_mem_putw)
-	ALTENTRY(ddi_mem_put16)
-	ALTENTRY(ddi_io_putw)
-	ALTENTRY(ddi_io_put16)
-	movl	4(%esp), %eax
-	movl	ACC_ATTR(%eax), %ecx
-	cmpl	$_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %ecx
-	jne	8f
-	movl	12(%esp), %eax
-	movl	8(%esp), %edx
-	outw	(%dx)
-	ret
-8:
-	cmpl	$_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %ecx
-	jne	9f
-	movl	8(%esp), %eax
-	movl	12(%esp), %ecx
-	movw	%cx, (%eax)
-	ret
-9:
-	jmp	*ACC_PUTW(%eax)
-	SET_SIZE(ddi_put16)
-	SET_SIZE(ddi_putw)
-	SET_SIZE(ddi_mem_putw)
-	SET_SIZE(ddi_mem_put16)
-	SET_SIZE(ddi_io_putw)
-	SET_SIZE(ddi_io_put16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_put32)
 	ALTENTRY(ddi_putl)
 	ALTENTRY(ddi_mem_putl)
@@ -643,42 +216,7 @@
 	SET_SIZE(ddi_io_putl)
 	SET_SIZE(ddi_io_put32)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_put32)
-	ALTENTRY(ddi_putl)
-	ALTENTRY(ddi_mem_putl)
-	ALTENTRY(ddi_mem_put32)
-	ALTENTRY(ddi_io_putl)
-	ALTENTRY(ddi_io_put32)
-	movl	4(%esp), %eax
-	movl	ACC_ATTR(%eax), %ecx
-	cmpl	$_CONST(DDI_ACCATTR_IO_SPACE|DDI_ACCATTR_DIRECT), %ecx
-	jne	8f
-	movl	12(%esp), %eax
-	movl	8(%esp), %edx
-	outl	(%dx)
-	ret
-8:
-	cmpl	$_CONST(DDI_ACCATTR_CPU_VADDR|DDI_ACCATTR_DIRECT), %ecx
-	jne	9f
-	movl	8(%esp), %eax
-	movl	12(%esp), %ecx
-	movl	%ecx, (%eax)
-	ret
-9:
-	jmp	*ACC_PUTL(%eax)
-	SET_SIZE(ddi_put32)
-	SET_SIZE(ddi_putl)
-	SET_SIZE(ddi_mem_putl)
-	SET_SIZE(ddi_mem_put32)
-	SET_SIZE(ddi_io_putl)
-	SET_SIZE(ddi_io_put32)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_put64)
 	ALTENTRY(ddi_putll)
 	ALTENTRY(ddi_mem_putll)
@@ -690,23 +228,7 @@
 	SET_SIZE(ddi_mem_putll)
 	SET_SIZE(ddi_mem_put64)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_put64)
-	ALTENTRY(ddi_putll)
-	ALTENTRY(ddi_mem_putll)
-	ALTENTRY(ddi_mem_put64)
-	movl	4(%esp), %eax
-	jmp	*ACC_PUTLL(%eax)
-	SET_SIZE(ddi_put64)
-	SET_SIZE(ddi_putll)
-	SET_SIZE(ddi_mem_putll)
-	SET_SIZE(ddi_mem_put64)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_rep_get8)
 	ALTENTRY(ddi_rep_getb)
 	ALTENTRY(ddi_mem_rep_getb)
@@ -718,23 +240,7 @@
 	SET_SIZE(ddi_mem_rep_getb)
 	SET_SIZE(ddi_mem_rep_get8)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_rep_get8)
-	ALTENTRY(ddi_rep_getb)
-	ALTENTRY(ddi_mem_rep_getb)
-	ALTENTRY(ddi_mem_rep_get8)
-	movl	4(%esp), %eax
-	jmp	*ACC_REP_GETB(%eax)
-	SET_SIZE(ddi_rep_get8)
-	SET_SIZE(ddi_rep_getb)
-	SET_SIZE(ddi_mem_rep_getb)
-	SET_SIZE(ddi_mem_rep_get8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_rep_get16)
 	ALTENTRY(ddi_rep_getw)
 	ALTENTRY(ddi_mem_rep_getw)
@@ -746,23 +252,7 @@
 	SET_SIZE(ddi_mem_rep_getw)
 	SET_SIZE(ddi_mem_rep_get16)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_rep_get16)
-	ALTENTRY(ddi_rep_getw)
-	ALTENTRY(ddi_mem_rep_getw)
-	ALTENTRY(ddi_mem_rep_get16)
-	movl	4(%esp), %eax
-	jmp	*ACC_REP_GETW(%eax)
-	SET_SIZE(ddi_rep_get16)
-	SET_SIZE(ddi_rep_getw)
-	SET_SIZE(ddi_mem_rep_getw)
-	SET_SIZE(ddi_mem_rep_get16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_rep_get32)
 	ALTENTRY(ddi_rep_getl)
 	ALTENTRY(ddi_mem_rep_getl)
@@ -774,23 +264,7 @@
 	SET_SIZE(ddi_mem_rep_getl)
 	SET_SIZE(ddi_mem_rep_get32)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_rep_get32)
-	ALTENTRY(ddi_rep_getl)
-	ALTENTRY(ddi_mem_rep_getl)
-	ALTENTRY(ddi_mem_rep_get32)
-	movl	4(%esp), %eax
-	jmp	*ACC_REP_GETL(%eax)
-	SET_SIZE(ddi_rep_get32)
-	SET_SIZE(ddi_rep_getl)
-	SET_SIZE(ddi_mem_rep_getl)
-	SET_SIZE(ddi_mem_rep_get32)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_rep_get64)
 	ALTENTRY(ddi_rep_getll)
 	ALTENTRY(ddi_mem_rep_getll)
@@ -802,23 +276,7 @@
 	SET_SIZE(ddi_mem_rep_getll)
 	SET_SIZE(ddi_mem_rep_get64)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_rep_get64)
-	ALTENTRY(ddi_rep_getll)
-	ALTENTRY(ddi_mem_rep_getll)
-	ALTENTRY(ddi_mem_rep_get64)
-	movl	4(%esp), %eax
-	jmp	*ACC_REP_GETLL(%eax)
-	SET_SIZE(ddi_rep_get64)
-	SET_SIZE(ddi_rep_getll)
-	SET_SIZE(ddi_mem_rep_getll)
-	SET_SIZE(ddi_mem_rep_get64)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_rep_put8)
 	ALTENTRY(ddi_rep_putb)
 	ALTENTRY(ddi_mem_rep_putb)
@@ -830,23 +288,7 @@
 	SET_SIZE(ddi_mem_rep_putb)
 	SET_SIZE(ddi_mem_rep_put8)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_rep_put8)
-	ALTENTRY(ddi_rep_putb)
-	ALTENTRY(ddi_mem_rep_putb)
-	ALTENTRY(ddi_mem_rep_put8)
-	movl	4(%esp), %eax
-	jmp	*ACC_REP_PUTB(%eax)
-	SET_SIZE(ddi_rep_put8)
-	SET_SIZE(ddi_rep_putb)
-	SET_SIZE(ddi_mem_rep_putb)
-	SET_SIZE(ddi_mem_rep_put8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_rep_put16)
 	ALTENTRY(ddi_rep_putw)
 	ALTENTRY(ddi_mem_rep_putw)
@@ -858,23 +300,7 @@
 	SET_SIZE(ddi_mem_rep_putw)
 	SET_SIZE(ddi_mem_rep_put16)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_rep_put16)
-	ALTENTRY(ddi_rep_putw)
-	ALTENTRY(ddi_mem_rep_putw)
-	ALTENTRY(ddi_mem_rep_put16)
-	movl	4(%esp), %eax
-	jmp	*ACC_REP_PUTW(%eax)
-	SET_SIZE(ddi_rep_put16)
-	SET_SIZE(ddi_rep_putw)
-	SET_SIZE(ddi_mem_rep_putw)
-	SET_SIZE(ddi_mem_rep_put16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_rep_put32)
 	ALTENTRY(ddi_rep_putl)
 	ALTENTRY(ddi_mem_rep_putl)
@@ -886,23 +312,7 @@
 	SET_SIZE(ddi_mem_rep_putl)
 	SET_SIZE(ddi_mem_rep_put32)
 
-#elif defined(__i386)
 
-	ENTRY(ddi_rep_put32)
-	ALTENTRY(ddi_rep_putl)
-	ALTENTRY(ddi_mem_rep_putl)
-	ALTENTRY(ddi_mem_rep_put32)
-	movl	4(%esp), %eax
-	jmp	*ACC_REP_PUTL(%eax)
-	SET_SIZE(ddi_rep_put32)
-	SET_SIZE(ddi_rep_putl)
-	SET_SIZE(ddi_mem_rep_putl)
-	SET_SIZE(ddi_mem_rep_put32)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(ddi_rep_put64)
 	ALTENTRY(ddi_rep_putll)
 	ALTENTRY(ddi_mem_rep_putll)
@@ -914,154 +324,29 @@
 	SET_SIZE(ddi_mem_rep_putll)
 	SET_SIZE(ddi_mem_rep_put64)
 
-#elif defined(__i386)
-
-	ENTRY(ddi_rep_put64)
-	ALTENTRY(ddi_rep_putll)
-	ALTENTRY(ddi_mem_rep_putll)
-	ALTENTRY(ddi_mem_rep_put64)
-	movl	4(%esp), %eax
-	jmp	*ACC_REP_PUTLL(%eax)
-	SET_SIZE(ddi_rep_put64)
-	SET_SIZE(ddi_rep_putll)
-	SET_SIZE(ddi_mem_rep_putll)
-	SET_SIZE(ddi_mem_rep_put64)
-
-#endif	/* __i386 */
-
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint8_t
-i_ddi_vaddr_get8(ddi_acc_impl_t *hdlp, uint8_t *addr)
-{
-	return (*addr);
-}
-
-/*ARGSUSED*/
-uint16_t
-i_ddi_vaddr_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
-{
-	return (*addr);
-}
-
-/*ARGSUSED*/
-uint32_t
-i_ddi_vaddr_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
-{
-	return (*addr);
-}
-
-/*ARGSUSED*/
-uint64_t
-i_ddi_vaddr_get64(ddi_acc_impl_t *hdlp, uint64_t *addr)
-{
-	return (*addr);
-}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_vaddr_get8)
 	movzbq	(%rsi), %rax
 	ret
 	SET_SIZE(i_ddi_vaddr_get8)
 
-#elif defined(__i386)
-
-	ENTRY(i_ddi_vaddr_get8)
-	movl	8(%esp), %eax
-	movzbl	(%eax), %eax
-	ret
-	SET_SIZE(i_ddi_vaddr_get8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_vaddr_get16)
 	movzwq	(%rsi), %rax
 	ret
 	SET_SIZE(i_ddi_vaddr_get16)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_vaddr_get16)
-	movl	8(%esp), %eax
-	movzwl	(%eax), %eax
-	ret
-	SET_SIZE(i_ddi_vaddr_get16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_vaddr_get32)
 	movl	(%rsi), %eax
 	ret
 	SET_SIZE(i_ddi_vaddr_get32)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_vaddr_get32)
-	movl	8(%esp), %eax
-	movl	(%eax), %eax
-	ret
-	SET_SIZE(i_ddi_vaddr_get32)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_vaddr_get64)
 	movq	(%rsi), %rax
 	ret
 	SET_SIZE(i_ddi_vaddr_get64)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_vaddr_get64)
-	movl	8(%esp), %ecx
-	movl	(%ecx), %eax
-	movl	4(%ecx), %edx
-	ret
-	SET_SIZE(i_ddi_vaddr_get64)
-
-#endif	/* __i386 */
-
-#endif /* lint */
-
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint8_t
-i_ddi_io_get8(ddi_acc_impl_t *hdlp, uint8_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-i_ddi_io_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-i_ddi_io_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
-{
-	return (0);
-}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_get8)
 	movq	%rsi, %rdx
 	inb	(%dx)
@@ -1069,19 +354,7 @@
 	ret
 	SET_SIZE(i_ddi_io_get8)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_io_get8)
-	movl	8(%esp), %edx
-	inb	(%dx)
-	movzbl	%al, %eax
-	ret
-	SET_SIZE(i_ddi_io_get8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_get16)
 	movq	%rsi, %rdx
 	inw	(%dx)
@@ -1089,19 +362,7 @@
 	ret
 	SET_SIZE(i_ddi_io_get16)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_io_get16)
-	movl	8(%esp), %edx
-	inw	(%dx)
-	movzwl	%ax, %eax
-	ret
-	SET_SIZE(i_ddi_io_get16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_get32)
 	movq	%rsi, %rdx
 	inl	(%dx)
@@ -1108,147 +369,29 @@
 	ret
 	SET_SIZE(i_ddi_io_get32)
 
-#elif defined(__i386)
-
-	ENTRY(i_ddi_io_get32)
-	movl	8(%esp), %edx
-	inl	(%dx)
-	ret
-	SET_SIZE(i_ddi_io_get32)
-
-#endif	/* __i386 */
-
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-i_ddi_vaddr_put8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value)
-{
-	*addr = value;
-}
-
-/*ARGSUSED*/
-void
-i_ddi_vaddr_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value)
-{
-	*addr = value;
-}
-
-/*ARGSUSED*/
-void
-i_ddi_vaddr_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value)
-{
-	*(uint32_t *)addr = value;
-}
-
-/*ARGSUSED*/
-void
-i_ddi_vaddr_put64(ddi_acc_impl_t *hdlp, uint64_t *addr, uint64_t value)
-{
-	*addr = value;
-}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_vaddr_put8)
 	movb	%dl, (%rsi)
 	ret
 	SET_SIZE(i_ddi_vaddr_put8)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_vaddr_put8)
-	movl	8(%esp), %eax
-	movb	12(%esp), %cl
-	movb	%cl, (%eax)
-	ret
-	SET_SIZE(i_ddi_vaddr_put8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_vaddr_put16)
 	movw	%dx, (%rsi)
 	ret
 	SET_SIZE(i_ddi_vaddr_put16)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_vaddr_put16)
-	movl	8(%esp), %eax
-	movl	12(%esp), %ecx
-	movw	%cx, (%eax)
-	ret
-	SET_SIZE(i_ddi_vaddr_put16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_vaddr_put32)
 	movl	%edx, (%rsi)
 	ret
 	SET_SIZE(i_ddi_vaddr_put32)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_vaddr_put32)
-	movl	8(%esp), %eax
-	movl	12(%esp), %ecx
-	movl	%ecx, (%eax)
-	ret
-	SET_SIZE(i_ddi_vaddr_put32)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_vaddr_put64)
 	movq	%rdx, (%rsi)
 	ret
 	SET_SIZE(i_ddi_vaddr_put64)
 
-#elif defined(__i386)
-
-	ENTRY(i_ddi_vaddr_put64)
-	movl	8(%esp), %ecx
-	movl	12(%esp), %edx
-	movl	16(%esp), %eax
-	movl	%edx, (%ecx)
-	movl	%eax, 4(%ecx)
-	ret
-	SET_SIZE(i_ddi_vaddr_put64)
-
-#endif	/* __i386 */
-
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-i_ddi_io_put8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value)
-{}
-
-/*ARGSUSED*/
-void
-i_ddi_io_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value)
-{}
-
-/*ARGSUSED*/
-void
-i_ddi_io_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value)
-{}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_put8)
 	movq	%rdx, %rax
 	movq	%rsi, %rdx
@@ -1256,19 +399,7 @@
 	ret
 	SET_SIZE(i_ddi_io_put8)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_io_put8)
-	movl	12(%esp), %eax
-	movl	8(%esp), %edx
-	outb	(%dx)
-	ret
-	SET_SIZE(i_ddi_io_put8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_put16)
 	movq	%rdx, %rax
 	movq	%rsi, %rdx
@@ -1276,19 +407,7 @@
 	ret
 	SET_SIZE(i_ddi_io_put16)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_io_put16)
-	movl	12(%esp), %eax
-	movl	8(%esp), %edx
-	outw	(%dx)
-	ret
-	SET_SIZE(i_ddi_io_put16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_put32)
 	movq	%rdx, %rax
 	movq	%rsi, %rdx
@@ -1296,43 +415,6 @@
 	ret
 	SET_SIZE(i_ddi_io_put32)
 
-#elif defined(__i386)
-
-	ENTRY(i_ddi_io_put32)
-	movl	12(%esp), %eax
-	movl	8(%esp), %edx
-	outl	(%dx)
-	ret
-	SET_SIZE(i_ddi_io_put32)
-
-#endif	/* __i386 */
-
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-i_ddi_io_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
-	uint8_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-i_ddi_io_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
-	uint16_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-i_ddi_io_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
-	uint32_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	/*
 	 * Incoming arguments
 	 *
@@ -1370,43 +452,7 @@
 
 	SET_SIZE(i_ddi_io_rep_get8)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_io_rep_get8)
-	pushl	%edi
-
-	movl	12(%esp),%edi			/ get host_addr
-	movl	16(%esp),%edx			/ get port
-	movl	20(%esp),%ecx			/ get repcount
-	cmpl	$DDI_DEV_AUTOINCR, 24(%esp)
-	je	gb_ioadv
-
-	rep
-	insb
-	popl	%edi
-	ret
-
-gb_ioadv:
-	andl	%ecx, %ecx
-	jz	gb_ioadv_done
-gb_ioadv2:
-	inb	(%dx)
-	movb	%al,(%edi)
-	incl	%edi
-	incl	%edx
-	decl	%ecx
-	jg	gb_ioadv2
-
-gb_ioadv_done:
-	popl	%edi
-	ret
-
-	SET_SIZE(i_ddi_io_rep_get8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_rep_get16)
 
 	cmpq	$DDI_DEV_AUTOINCR, %r8
@@ -1433,42 +479,7 @@
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(i_ddi_io_rep_get16)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_io_rep_get16)
-	pushl	%edi
-
-	movl	12(%esp),%edi			/ get host_addr
-	movl	16(%esp),%edx			/ get port
-	movl	20(%esp),%ecx			/ get repcount
-	cmpl	$DDI_DEV_AUTOINCR, 24(%esp)
-	je	gw_ioadv
-
-	rep
-	insw
-	popl	%edi
-	ret
-
-gw_ioadv:
-	andl	%ecx, %ecx
-	jz	gw_ioadv_done
-gw_ioadv2:
-	inw	(%dx)
-	movw	%ax,(%edi)
-	addl	$2, %edi
-	addl	$2, %edx
-	decl	%ecx
-	jg	gw_ioadv2
-
-gw_ioadv_done:
-	popl	%edi
-	ret
-	SET_SIZE(i_ddi_io_rep_get16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_rep_get32)
 
 	cmpq	$DDI_DEV_AUTOINCR, %r8
@@ -1496,68 +507,6 @@
 
 	SET_SIZE(i_ddi_io_rep_get32)
 
-
-#elif defined(__i386)
-
-	ENTRY(i_ddi_io_rep_get32)
-	pushl	%edi
-
-	movl	12(%esp),%edi			/ get host_addr
-	movl	16(%esp),%edx			/ get port
-	movl	20(%esp),%ecx			/ get repcount
-	cmpl	$DDI_DEV_AUTOINCR, 24(%esp)
-	je	gl_ioadv
-
-	rep
-	insl
-	popl	%edi
-	ret
-
-gl_ioadv:
-	andl	%ecx, %ecx
-	jz	gl_ioadv_done
-gl_ioadv2:
-	inl	(%dx)
-	movl	%eax,(%edi)
-	addl	$4, %edi
-	addl	$4, %edx
-	decl	%ecx
-	jg	gl_ioadv2
-
-gl_ioadv_done:
-	popl	%edi
-	ret
-
-	SET_SIZE(i_ddi_io_rep_get32)
-
-#endif	/* __i386 */
-
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-i_ddi_io_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
-	uint8_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-i_ddi_io_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
-	uint16_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-/*ARGSUSED*/
-void
-i_ddi_io_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
-	uint32_t *dev_addr, size_t repcount, uint_t flags)
-{}
-
-#else	/* lint */
-
-#if defined(__amd64)
-
 	/*
 	 * Incoming arguments
 	 *
@@ -1595,42 +544,6 @@
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(i_ddi_io_rep_put8)
 
-#elif defined(__i386)
-
-	ENTRY(i_ddi_io_rep_put8)
-	pushl	%esi
-
-	movl	12(%esp),%esi			/ get host_addr
-	movl	16(%esp),%edx			/ get port
-	movl	20(%esp),%ecx			/ get repcount
-	cmpl	$DDI_DEV_AUTOINCR, 24(%esp)
-	je	pb_ioadv
-
-	rep
-	outsb
-	popl	%esi
-	ret
-
-pb_ioadv:
-	andl	%ecx, %ecx
-	jz	pb_ioadv_done
-pb_ioadv2:
-	movb	(%esi), %al
-	outb	(%dx)
-	incl	%esi
-	incl	%edx
-	decl	%ecx
-	jg	pb_ioadv2
-
-pb_ioadv_done:
-	popl	%esi
-	ret
-	SET_SIZE(i_ddi_io_rep_put8)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_rep_put16)
 
 	cmpq	$DDI_DEV_AUTOINCR, %r8
@@ -1657,42 +570,7 @@
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(i_ddi_io_rep_put16)
 
-#elif defined(__i386)
 
-	ENTRY(i_ddi_io_rep_put16)
-	pushl	%esi
-
-	movl	12(%esp),%esi			/ get host_addr
-	movl	16(%esp),%edx			/ get port
-	movl	20(%esp),%ecx			/ get repcount
-	cmpl	$DDI_DEV_AUTOINCR, 24(%esp)
-	je	pw_ioadv
-
-	rep
-	outsw
-	popl	%esi
-	ret
-
-pw_ioadv:
-	andl	%ecx, %ecx
-	jz	pw_ioadv_done
-pw_ioadv2:
-	movw	(%esi), %ax
-	outw	(%dx)
-	addl	$2, %esi
-	addl	$2, %edx
-	decl	%ecx
-	jg	pw_ioadv2
-
-pw_ioadv_done:
-	popl	%esi
-	ret
-	SET_SIZE(i_ddi_io_rep_put16)
-
-#endif	/* __i386 */
-
-#if defined(__amd64)
-
 	ENTRY(i_ddi_io_rep_put32)
 
 	cmpq	$DDI_DEV_AUTOINCR, %r8
@@ -1719,38 +597,3 @@
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(i_ddi_io_rep_put32)
 
-#elif defined(__i386)
-
-	ENTRY(i_ddi_io_rep_put32)
-	pushl	%esi
-
-	movl	12(%esp),%esi			/ get host_addr
-	movl	16(%esp),%edx			/ get port
-	movl	20(%esp),%ecx			/ get repcount
-	cmpl	$DDI_DEV_AUTOINCR, 24(%esp)
-	je	pl_ioadv
-
-	rep
-	outsl
-	popl	%esi
-	ret
-
-pl_ioadv:
-	andl	%ecx, %ecx
-	jz	pl_ioadv_done
-pl_ioadv2:
-	movl	(%esi), %eax
-	outl	(%dx)
-	addl	$4, %esi
-	addl	$4, %edx
-	decl	%ecx
-	jg	pl_ioadv2
-
-pl_ioadv_done:
-	popl	%esi
-	ret
-	SET_SIZE(i_ddi_io_rep_put32)
-
-#endif	/* __i386 */
-
-#endif /* lint */
--- old/usr/src/uts/intel/ia32/ml/desctbls_asm.s	Thu Nov 14 19:00:24 2019
+++ new/usr/src/uts/intel/ia32/ml/desctbls_asm.s	Thu Nov 14 19:00:24 2019
@@ -23,6 +23,10 @@
  * Use is subject to license terms.
  */
 
+/*
+ * Copyright 2019 Joyent, Inc.
+ */
+
 #include <sys/asm_linkage.h>
 #include <sys/asm_misc.h>
 #include <sys/regset.h>
@@ -32,34 +36,8 @@
 #include <sys/segments.h>
 #include <sys/trap.h>
 
-#if defined(__lint)
-#include <sys/types.h>
-#include <sys/systm.h>
-#include <sys/thread.h>
-#include <sys/archsystm.h>
-#include <sys/byteorder.h>
-#include <sys/dtrace.h>
-#include <sys/x86_archext.h>
-#else   /* __lint */
 #include "assym.h"
-#endif  /* __lint */
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-rd_idtr(desctbr_t *idtr)
-{}
-
-/*ARGSUSED*/
-void
-wr_idtr(desctbr_t *idtr)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(rd_idtr)
 	sidt	(%rdi)
 	ret
@@ -70,45 +48,6 @@
 	ret
 	SET_SIZE(wr_idtr)
 
-#elif defined(__i386)
-
-	ENTRY_NP(rd_idtr)
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	8(%ebp), %edx
-	sidt	(%edx)
-	leave
-	ret
-	SET_SIZE(rd_idtr)
-
-	ENTRY_NP(wr_idtr)
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	8(%ebp), %edx
-	lidt	(%edx)
-	leave
-	ret
-	SET_SIZE(wr_idtr)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-rd_gdtr(desctbr_t *gdtr)
-{}
-
-/*ARGSUSED*/
-void
-wr_gdtr(desctbr_t *gdtr)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(rd_gdtr)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -128,47 +67,6 @@
 	ret
 	SET_SIZE(wr_gdtr)
 
-#elif defined(__i386)
-
-	ENTRY_NP(rd_gdtr)
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	8(%ebp), %edx
-	sgdt	(%edx)
-	leave
-	ret
-	SET_SIZE(rd_gdtr)
-
-	ENTRY_NP(wr_gdtr)
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	8(%ebp), %edx
-	lgdt	(%edx)
-	jmp	1f
-	nop
-1:
-	leave
-	ret
-	SET_SIZE(wr_gdtr)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__amd64)
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-load_segment_registers(selector_t cs, selector_t fs, selector_t gs,
-    selector_t ss)
-{}
-
-selector_t
-get_cs_register()
-{ return (0); }
-
-#else	/* __lint */
-
 	/*
 	 * loads zero selector for ds and es.
 	 */
@@ -200,70 +98,6 @@
 	ret
 	SET_SIZE(get_cs_register)
 
-#endif	/* __lint */
-#elif defined(__i386)
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-load_segment_registers(
-    selector_t cs, selector_t ds, selector_t es,
-    selector_t fs, selector_t gs, selector_t ss)
-{}
-
-selector_t
-get_cs_register()
-{ return ((selector_t) 0); }
-
-#else	/* __lint */
-
-	ENTRY_NP(load_segment_registers)
-	pushl	%ebp
-	movl	%esp, %ebp
-
-	pushl	0x8(%ebp)
-	pushl	$.newcs
-	lret
-.newcs:
-	movw	0xc(%ebp), %ax
-	movw	%ax, %ds
-	movw	0x10(%ebp), %ax
-	movw	%ax, %es
-	movw	0x14(%ebp), %ax
-	movw	%ax, %fs
-	movw	0x18(%ebp), %ax
-	movw	%ax, %gs
-	movw	0x1c(%ebp), %ax
-	movw	%ax, %ss
-	leave
-	ret
-	SET_SIZE(load_segment_registers)
-
-	ENTRY_NP(get_cs_register)
-	movl	$0, %eax
-	movw	%cs, %ax
-	ret
-	SET_SIZE(get_cs_register)
-
-#endif	/* __lint */
-#endif	/* __i386 */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-wr_ldtr(selector_t ldtsel)
-{}
-
-selector_t
-rd_ldtr(void)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(wr_ldtr)
 	movq	%rdi, %rax
 	lldt	%ax
@@ -276,34 +110,6 @@
 	ret
 	SET_SIZE(rd_ldtr)
 
-#elif defined(__i386)
-
-	ENTRY_NP(wr_ldtr)
-	movw	4(%esp), %ax
-	lldt	%ax
-	ret
-	SET_SIZE(wr_ldtr)
-
-	ENTRY_NP(rd_ldtr)
-	xorl	%eax, %eax
-	sldt	%ax
-	ret
-	SET_SIZE(rd_ldtr)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-wr_tsr(selector_t tsssel)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(wr_tsr)
 	movq	%rdi, %rax
 	ltr	%ax
@@ -310,13 +116,3 @@
 	ret
 	SET_SIZE(wr_tsr)
 
-#elif defined(__i386)
-
-	ENTRY_NP(wr_tsr)
-	movw	4(%esp), %ax
-	ltr	%ax
-	ret
-	SET_SIZE(wr_tsr)
-
-#endif	/* __i386 */
-#endif	/* __lint */
--- old/usr/src/uts/intel/ia32/ml/exception.s	Thu Nov 14 19:00:24 2019
+++ new/usr/src/uts/intel/ia32/ml/exception.s	Thu Nov 14 19:00:24 2019
@@ -51,8 +51,6 @@
 #include <sys/traptrace.h>
 #include <sys/machparam.h>
 
-#if !defined(__lint)
-
 #include "assym.h"
 
 /*
@@ -67,7 +65,7 @@
  * it get saved as is running native.
  */
 
-#if defined(__xpv) && defined(__amd64)
+#if defined(__xpv)
 
 #define	NPTRAP_NOERR(trapno)	\
 	pushq	$0;		\
@@ -85,7 +83,7 @@
 	XPV_TRAP_POP;		\
 	pushq	$trapno
 
-#else /* __xpv && __amd64 */
+#else /* __xpv */
 
 #define	TRAP_NOERR(trapno)	\
 	push	$0;		\
@@ -100,11 +98,11 @@
 #define	TRAP_ERR(trapno)	\
 	push	$trapno
 
-#endif	/* __xpv && __amd64 */
+#endif	/* __xpv */
 
 	/*
 	 * These are the stacks used on cpu0 for taking double faults,
-	 * NMIs and MCEs (the latter two only on amd64 where we have IST).
+	 * NMIs and MCEs.
 	 *
 	 * We define them here instead of in a C file so that we can page-align
 	 * them (gcc won't do that in a .c file).
@@ -134,7 +132,6 @@
 	ENTRY_NP(dbgtrap)
 	TRAP_NOERR(T_SGLSTP)	/* $1 */
 
-#if defined(__amd64)
 #if !defined(__xpv)		/* no sysenter support yet */
 	/*
 	 * If we get here as a result of single-stepping a sysenter
@@ -193,29 +190,9 @@
 	movq	%rax, %db6
 #endif
 
-#elif defined(__i386)
-
-	INTR_PUSH
-#if defined(__xpv)
-	pushl	$6
-	call	kdi_dreg_get
-	addl	$4, %esp
-	movl	%eax, %esi		/* %dr6 -> %esi */
-	pushl	$0
-	pushl	$6
-	call	kdi_dreg_set		/* 0 -> %dr6 */
-	addl	$8, %esp
-#else
-	movl	%db6, %esi
-	xorl	%eax, %eax
-	movl	%eax, %db6
-#endif
-#endif	/* __i386 */
-
 	jmp	cmntrap_pushed
 	SET_SIZE(dbgtrap)
 
-#if defined(__amd64)
 #if !defined(__xpv)
 
 /*
@@ -277,11 +254,8 @@
 #define	SET_CPU_GSBASE	/* noop on the hypervisor */
 
 #endif	/* __xpv */
-#endif	/* __amd64 */
 
 
-#if defined(__amd64)
-
 	/*
 	 * #NMI
 	 *
@@ -314,43 +288,10 @@
 	/*NOTREACHED*/
 	SET_SIZE(nmiint)
 
-#elif defined(__i386)
-
 	/*
-	 * #NMI
-	 */
-	ENTRY_NP(nmiint)
-	TRAP_NOERR(T_NMIFLT)	/* $2 */
-
-	/*
-	 * Save all registers and setup segment registers
-	 * with kernel selectors.
-	 */
-	INTR_PUSH
-	INTGATE_INIT_KERNEL_FLAGS
-
-	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_TRAP)
-	TRACE_REGS(%edi, %esp, %ebx, %ecx)
-	TRACE_STAMP(%edi)
-
-	movl	%esp, %ebp
-
-	pushl	%ebp
-	call	av_dispatch_nmivect
-	addl	$4, %esp
-
-	INTR_POP_USER
-	IRET
-	SET_SIZE(nmiint)
-
-#endif	/* __i386 */
-
-	/*
 	 * #BP
 	 */
 	ENTRY_NP(brktrap)
-
-#if defined(__amd64)
 	XPV_TRAP_POP
 	cmpw	$KCS_SEL, 8(%rsp)
 	jne	bp_user
@@ -368,7 +309,6 @@
 	jmp	ud_kernel
 
 bp_user:
-#endif /* __amd64 */
 
 	NPTRAP_NOERR(T_BPTFLT)	/* $3 */
 	jmp	dtrace_trap
@@ -391,8 +331,6 @@
 	jmp	cmntrap
 	SET_SIZE(boundstrap)
 
-#if defined(__amd64)
-
 	ENTRY_NP(invoptrap)
 
 	XPV_TRAP_POP
@@ -454,12 +392,12 @@
 
 ud_leave:
 	/*
-	 * We must emulate a "leave", which is the same as a "movq %rbp, %rsp"
-	 * followed by a "popq %rbp".  This is quite a bit simpler on amd64
-	 * than it is on i386 -- we can exploit the fact that the %rsp is
-	 * explicitly saved to effect the pop without having to reshuffle
-	 * the other data pushed for the trap.
+	 * We must emulate a "leave", which is the same as a "movq %rbp,
+	 * %rsp" followed by a "popq %rbp".  We can exploit the fact
+	 * that the %rsp is explicitly saved to effect the pop without
+	 * having to reshuffle the other data pushed for the trap.
 	 */
+
 	INTR_POP
 	pushq	%rax			/* push temp */
 	movq	8(%rsp), %rax		/* load calling RIP */
@@ -515,127 +453,7 @@
 	jmp	cmntrap
 	SET_SIZE(invoptrap)
 
-#elif defined(__i386)
-
 	/*
-	 * #UD
-	 */
-	ENTRY_NP(invoptrap)
-	/*
-	 * If we are taking an invalid opcode trap while in the kernel, this
-	 * is likely an FBT probe point.
-	 */
-	pushl   %gs
-	cmpw	$KGS_SEL, (%esp)
-	jne	8f
-
-	addl	$4, %esp
-#if defined(__xpv)
-	movb	$0, 6(%esp)		/* clear saved upcall_mask from %cs */
-#endif	/* __xpv */
-	pusha
-	pushl	%eax			/* push %eax -- may be return value */
-	pushl	%esp			/* push stack pointer */
-	addl	$48, (%esp)		/* adjust to incoming args */
-	pushl	40(%esp)		/* push calling EIP */
-	call	dtrace_invop
-	ALTENTRY(dtrace_invop_callsite)
-	addl	$12, %esp
-	cmpl	$DTRACE_INVOP_PUSHL_EBP, %eax
-	je	1f
-	cmpl	$DTRACE_INVOP_POPL_EBP, %eax
-	je	2f
-	cmpl	$DTRACE_INVOP_LEAVE, %eax
-	je	3f
-	cmpl	$DTRACE_INVOP_NOP, %eax
-	je	4f
-	jmp	7f
-1:
-	/*
-	 * We must emulate a "pushl %ebp".  To do this, we pull the stack
-	 * down 4 bytes, and then store the base pointer.
-	 */
-	popa
-	subl	$4, %esp		/* make room for %ebp */
-	pushl	%eax			/* push temp */
-	movl	8(%esp), %eax		/* load calling EIP */
-	incl	%eax			/* increment over LOCK prefix */
-	movl	%eax, 4(%esp)		/* store calling EIP */
-	movl	12(%esp), %eax		/* load calling CS */
-	movl	%eax, 8(%esp)		/* store calling CS */
-	movl	16(%esp), %eax		/* load calling EFLAGS */
-	movl	%eax, 12(%esp)		/* store calling EFLAGS */
-	movl	%ebp, 16(%esp)		/* push %ebp */
-	popl	%eax			/* pop off temp */
-	jmp	_emul_done
-2:
-	/*
-	 * We must emulate a "popl %ebp".  To do this, we do the opposite of
-	 * the above:  we remove the %ebp from the stack, and squeeze up the
-	 * saved state from the trap.
-	 */
-	popa
-	pushl	%eax			/* push temp */
-	movl	16(%esp), %ebp		/* pop %ebp */
-	movl	12(%esp), %eax		/* load calling EFLAGS */
-	movl	%eax, 16(%esp)		/* store calling EFLAGS */
-	movl	8(%esp), %eax		/* load calling CS */
-	movl	%eax, 12(%esp)		/* store calling CS */
-	movl	4(%esp), %eax		/* load calling EIP */
-	incl	%eax			/* increment over LOCK prefix */
-	movl	%eax, 8(%esp)		/* store calling EIP */
-	popl	%eax			/* pop off temp */
-	addl	$4, %esp		/* adjust stack pointer */
-	jmp	_emul_done
-3:
-	/*
-	 * We must emulate a "leave", which is the same as a "movl %ebp, %esp"
-	 * followed by a "popl %ebp".  This looks similar to the above, but
-	 * requires two temporaries:  one for the new base pointer, and one
-	 * for the staging register.
-	 */
-	popa
-	pushl	%eax			/* push temp */
-	pushl	%ebx			/* push temp */
-	movl	%ebp, %ebx		/* set temp to old %ebp */
-	movl	(%ebx), %ebp		/* pop %ebp */
-	movl	16(%esp), %eax		/* load calling EFLAGS */
-	movl	%eax, (%ebx)		/* store calling EFLAGS */
-	movl	12(%esp), %eax		/* load calling CS */
-	movl	%eax, -4(%ebx)		/* store calling CS */
-	movl	8(%esp), %eax		/* load calling EIP */
-	incl	%eax			/* increment over LOCK prefix */
-	movl	%eax, -8(%ebx)		/* store calling EIP */
-	movl	%ebx, -4(%esp)		/* temporarily store new %esp */
-	popl	%ebx			/* pop off temp */
-	popl	%eax			/* pop off temp */
-	movl	-12(%esp), %esp		/* set stack pointer */
-	subl	$8, %esp		/* adjust for three pushes, one pop */
-	jmp	_emul_done
-4:
-	/*
-	 * We must emulate a "nop".  This is obviously not hard:  we need only
-	 * advance the %eip by one.
-	 */
-	popa
-	incl	(%esp)
-_emul_done:
-	IRET				/* return from interrupt */
-7:
-	popa
-	pushl	$0
-	pushl	$T_ILLINST	/* $6 */
-	jmp	cmntrap
-8:
-	addl	$4, %esp
-	pushl	$0
-	pushl	$T_ILLINST	/* $6 */
-	jmp	cmntrap
-	SET_SIZE(invoptrap)
-
-#endif	/* __i386 */
-
-	/*
 	 * #NM
 	 */
 
@@ -646,7 +464,6 @@
 	SET_SIZE(ndptrap)
 
 #if !defined(__xpv)
-#if defined(__amd64)
 
 	/*
 	 * #DF
@@ -699,129 +516,6 @@
 
 	SET_SIZE(syserrtrap)
 
-#elif defined(__i386)
-
-	/*
-	 * #DF
-	 */
-	ENTRY_NP(syserrtrap)
-	cli				/* disable interrupts */
-
-	/*
-	 * We share this handler with kmdb (if kmdb is loaded).  As such, we
-	 * may have reached this point after encountering a #df in kmdb.  If
-	 * that happens, we'll still be on kmdb's IDT.  We need to switch back
-	 * to this CPU's IDT before proceeding.  Furthermore, if we did arrive
-	 * here from kmdb, kmdb is probably in a very sickly state, and
-	 * shouldn't be entered from the panic flow.  We'll suppress that
-	 * entry by setting nopanicdebug.
-	 */
-
-	subl	$DESCTBR_SIZE, %esp
-	movl	%gs:CPU_IDT, %eax
-	sidt	(%esp)
-	cmpl	DTR_BASE(%esp), %eax
-	je	1f
-
-	movl	%eax, DTR_BASE(%esp)
-	movw	$_MUL(NIDT, GATE_DESC_SIZE), DTR_LIMIT(%esp)
-	lidt	(%esp)
-
-	movl	$1, nopanicdebug
-
-1:	addl	$DESCTBR_SIZE, %esp
-
-	/*
-	 * Check the CPL in the TSS to see what mode
-	 * (user or kernel) we took the fault in.  At this
-	 * point we are running in the context of the double
-	 * fault task (dftss) but the CPU's task points to
-	 * the previous task (ktss) where the process context
-	 * has been saved as the result of the task switch.
-	 */
-	movl	%gs:CPU_TSS, %eax	/* get the TSS */
-	movl	TSS_SS(%eax), %ebx	/* save the fault SS */
-	movl	TSS_ESP(%eax), %edx	/* save the fault ESP */
-	testw	$CPL_MASK, TSS_CS(%eax)	/* user mode ? */
-	jz	make_frame
-	movw	TSS_SS0(%eax), %ss	/* get on the kernel stack */
-	movl	TSS_ESP0(%eax), %esp
-
-	/*
-	 * Clear the NT flag to avoid a task switch when the process
-	 * finally pops the EFL off the stack via an iret.  Clear
-	 * the TF flag since that is what the processor does for
-	 * a normal exception. Clear the IE flag so that interrupts
-	 * remain disabled.
-	 */
-	movl	TSS_EFL(%eax), %ecx
-	andl	$_BITNOT(PS_NT|PS_T|PS_IE), %ecx
-	pushl	%ecx
-	popfl				/* restore the EFL */
-	movw	TSS_LDT(%eax), %cx	/* restore the LDT */
-	lldt	%cx
-
-	/*
-	 * Restore process segment selectors.
-	 */
-	movw	TSS_DS(%eax), %ds
-	movw	TSS_ES(%eax), %es
-	movw	TSS_FS(%eax), %fs
-	movw	TSS_GS(%eax), %gs
-
-	/*
-	 * Restore task segment selectors.
-	 */
-	movl	$KDS_SEL, TSS_DS(%eax)
-	movl	$KDS_SEL, TSS_ES(%eax)
-	movl	$KDS_SEL, TSS_SS(%eax)
-	movl	$KFS_SEL, TSS_FS(%eax)
-	movl	$KGS_SEL, TSS_GS(%eax)
-
-	/*
-	 * Clear the TS bit, the busy bits in both task
-	 * descriptors, and switch tasks.
-	 */
-	clts
-	leal	gdt0, %ecx
-	movl	DFTSS_SEL+4(%ecx), %esi
-	andl	$_BITNOT(0x200), %esi
-	movl	%esi, DFTSS_SEL+4(%ecx)
-	movl	KTSS_SEL+4(%ecx), %esi
-	andl	$_BITNOT(0x200), %esi
-	movl	%esi, KTSS_SEL+4(%ecx)
-	movw	$KTSS_SEL, %cx
-	ltr	%cx
-
-	/*
-	 * Restore part of the process registers.
-	 */
-	movl	TSS_EBP(%eax), %ebp
-	movl	TSS_ECX(%eax), %ecx
-	movl	TSS_ESI(%eax), %esi
-	movl	TSS_EDI(%eax), %edi
-
-make_frame:
-	/*
-	 * Make a trap frame.  Leave the error code (0) on
-	 * the stack since the first word on a trap stack is
-	 * unused anyway.
-	 */
-	pushl	%ebx			/ fault SS
-	pushl	%edx			/ fault ESP
-	pushl	TSS_EFL(%eax)		/ fault EFL
-	pushl	TSS_CS(%eax)		/ fault CS
-	pushl	TSS_EIP(%eax)		/ fault EIP
-	pushl	$0			/ error code
-	pushl	$T_DBLFLT		/ trap number 8
-	movl	TSS_EBX(%eax), %ebx	/ restore EBX
-	movl	TSS_EDX(%eax), %edx	/ restore EDX
-	movl	TSS_EAX(%eax), %eax	/ restore EAX
-	sti				/ enable interrupts
-	jmp	cmntrap
-	SET_SIZE(syserrtrap)
-
-#endif	/* __i386 */
 #endif	/* !__xpv */
 
 	/*
@@ -837,9 +531,7 @@
 	 */
 	ENTRY_NP(segnptrap)
 	TRAP_ERR(T_SEGFLT)	/* $11 already have error code on stack */
-#if defined(__amd64)
 	SET_CPU_GSBASE
-#endif
 	jmp	cmntrap
 	SET_SIZE(segnptrap)
 
@@ -848,9 +540,7 @@
 	 */
 	ENTRY_NP(stktrap)
 	TRAP_ERR(T_STKFLT)	/* $12 already have error code on stack */
-#if defined(__amd64)
 	SET_CPU_GSBASE
-#endif
 	jmp	cmntrap
 	SET_SIZE(stktrap)
 
@@ -859,9 +549,7 @@
 	 */
 	ENTRY_NP(gptrap)
 	TRAP_ERR(T_GPFLT)	/* $13 already have error code on stack */
-#if defined(__amd64)
 	SET_CPU_GSBASE
-#endif
 	jmp	cmntrap
 	SET_SIZE(gptrap)
 
@@ -873,65 +561,17 @@
 	INTR_PUSH
 #if defined(__xpv)
 
-#if defined(__amd64)
 	movq	%gs:CPU_VCPU_INFO, %r15
 	movq	VCPU_INFO_ARCH_CR2(%r15), %r15	/* vcpu[].arch.cr2 */
-#elif defined(__i386)
-	movl	%gs:CPU_VCPU_INFO, %esi
-	movl	VCPU_INFO_ARCH_CR2(%esi), %esi	/* vcpu[].arch.cr2 */
-#endif	/* __i386 */
 
 #else	/* __xpv */
 
-#if defined(__amd64)
 	movq	%cr2, %r15
-#elif defined(__i386)
-	movl	%cr2, %esi
-#endif	/* __i386 */
 
 #endif	/* __xpv */
 	jmp	cmntrap_pushed
 	SET_SIZE(pftrap)
 
-#if !defined(__amd64)
-
-	.globl	idt0_default_r
-
-	/*
-	 * #PF pentium bug workaround
-	 */
-	ENTRY_NP(pentium_pftrap)
-	pushl	%eax
-	movl	%cr2, %eax
-	andl	$MMU_STD_PAGEMASK, %eax
-
-	cmpl	%eax, %cs:idt0_default_r+2	/* fixme */
-
-	je	check_for_user_address
-user_mode:
-	popl	%eax
-	pushl	$T_PGFLT	/* $14 */
-	jmp	cmntrap
-check_for_user_address:
-	/*
-	 * Before we assume that we have an unmapped trap on our hands,
-	 * check to see if this is a fault from user mode.  If it is,
-	 * we'll kick back into the page fault handler.
-	 */
-	movl	4(%esp), %eax	/* error code */
-	andl	$PF_ERR_USER, %eax
-	jnz	user_mode
-
-	/*
-	 * We now know that this is the invalid opcode trap.
-	 */
-	popl	%eax
-	addl	$4, %esp	/* pop error code */
-	jmp	invoptrap
-	SET_SIZE(pentium_pftrap)
-
-#endif	/* !__amd64 */
-
 	ENTRY_NP(resvtrap)
 	TRAP_NOERR(T_RESVTRAP)	/* (reserved)  */
 	jmp	cmntrap
@@ -958,8 +598,6 @@
 	 */
 	.globl	cmi_mca_trap	/* see uts/i86pc/os/cmi.c */
 
-#if defined(__amd64)
-
 	ENTRY_NP(mcetrap)
 	TRAP_NOERR(T_MCE)	/* $18 */
 
@@ -980,30 +618,6 @@
 	jmp	_sys_rtt
 	SET_SIZE(mcetrap)
 
-#else
-
-	ENTRY_NP(mcetrap)
-	TRAP_NOERR(T_MCE)	/* $18 */
-
-	INTR_PUSH
-	INTGATE_INIT_KERNEL_FLAGS
-
-	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_TRAP)
-	TRACE_REGS(%edi, %esp, %ebx, %ecx)
-	TRACE_STAMP(%edi)
-
-	movl	%esp, %ebp
-
-	movl	%esp, %ecx
-	pushl	%ecx		/* arg0 = struct regs *rp */
-	call	cmi_mca_trap	/* cmi_mca_trap(rp) */
-	addl	$4, %esp	/* pop arg0 */
-
-	jmp	_sys_rtt
-	SET_SIZE(mcetrap)
-
-#endif
-
 	/*
 	 * #XF
 	 */
@@ -1019,8 +633,6 @@
 
 	.globl	fasttable
 
-#if defined(__amd64)
-
 	ENTRY_NP(fasttrap)
 	cmpl	$T_LASTFAST, %eax
 	ja	1f
@@ -1051,36 +663,11 @@
 	jmp	gptrap
 	SET_SIZE(fasttrap)
 
-#elif defined(__i386)
-
-	ENTRY_NP(fasttrap)
-	cmpl	$T_LASTFAST, %eax
-	ja	1f
-	jmp	*%cs:fasttable(, %eax, CLONGSIZE)
-1:
-	/*
-	 * Fast syscall number was illegal.  Make it look
-	 * as if the INT failed.  Modify %eip to point before the
-	 * INT, push the expected error code and fake a GP fault.
-	 *
-	 * XXX Why make the error code be offset into idt + 1?
-	 * Instead we should push a real (soft?) error code
-	 * on the stack and #gp handler could know about fasttraps?
-	 */
-	subl	$2, (%esp)	/* XXX int insn 2-bytes */
-	pushl	$_CONST(_MUL(T_FASTTRAP, GATE_DESC_SIZE) + 2)
-	jmp	gptrap
-	SET_SIZE(fasttrap)
-
-#endif	/* __i386 */
-
 	ENTRY_NP(dtrace_ret)
 	TRAP_NOERR(T_DTRACE_RET)
 	jmp	dtrace_trap
 	SET_SIZE(dtrace_ret)
 
-#if defined(__amd64)
-
 	/*
 	 * RFLAGS 24 bytes up the stack from %rsp.
 	 * XXX a constant would be nicer.
@@ -1093,15 +680,6 @@
 	/*NOTREACHED*/
 	SET_SIZE(fast_null)
 
-#elif defined(__i386)
-
-	ENTRY_NP(fast_null)
-	orw	$PS_C, 8(%esp)	/* set carry bit in user flags */
-	IRET
-	SET_SIZE(fast_null)
-
-#endif	/* __i386 */
-
 	/*
 	 * Interrupts start at 32
 	 */
@@ -1337,4 +915,3 @@
 	MKIVCT(254)
 	MKIVCT(255)
 
-#endif	/* __lint */
--- old/usr/src/uts/intel/ia32/ml/float.s	Thu Nov 14 19:00:25 2019
+++ new/usr/src/uts/intel/ia32/ml/float.s	Thu Nov 14 19:00:25 2019
@@ -42,21 +42,8 @@
 #include <sys/privregs.h>
 #include <sys/x86_archext.h>
 
-#if defined(__lint)
-#include <sys/types.h>
-#include <sys/fp.h>
-#else
 #include "assym.h"
-#endif
 
-#if defined(__lint)
- 
-uint_t
-fpu_initial_probe(void)
-{ return (0); }
-
-#else	/* __lint */
-
 	/*
 	 * Returns zero if x87 "chip" is present(!)
 	 */
@@ -68,48 +55,16 @@
 	ret
 	SET_SIZE(fpu_initial_probe)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-fxsave_insn(struct fxsave_state *fx)
-{}
-
-#else	/* __lint */
-
 	ENTRY_NP(fxsave_insn)
 	fxsaveq (%rdi)
 	ret
 	SET_SIZE(fxsave_insn)
 
-#endif	/* __lint */
-
 /*
  * One of these routines is called from any lwp with floating
  * point context as part of the prolog of a context switch.
  */
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-xsave_ctxt(void *arg)
-{}
-
-/*ARGSUSED*/
-void
-xsaveopt_ctxt(void *arg)
-{}
-
-/*ARGSUSED*/
-void
-fpxsave_ctxt(void *arg)
-{}
-
-#else	/* __lint */
-
 /*
  * These three functions define the Intel "xsave" handling for CPUs with
  * different features. Newer AMD CPUs can also use these functions. See the
@@ -224,33 +179,7 @@
 	.4byte	0x0
 	.4byte	0x0
 
-#endif	/* __lint */
 
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-fpsave(struct fnsave_state *f)
-{}
-
-/*ARGSUSED*/
-void
-fpxsave(struct fxsave_state *f)
-{}
-
-/*ARGSUSED*/
-void
-xsave(struct xsave_state *f, uint64_t m)
-{}
-
-/*ARGSUSED*/
-void
-xsaveopt(struct xsave_state *f, uint64_t m)
-{}
-
-#else	/* __lint */
-
 	ENTRY_NP(fpxsave)
 	CLTS
 	fxsaveq (%rdi)
@@ -283,27 +212,11 @@
 	ret
 	SET_SIZE(xsaveopt)
 
-#endif	/* __lint */
-
 /*
  * These functions are used when restoring the FPU as part of the epilogue of a
  * context switch.
  */
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-fpxrestore_ctxt(void *arg)
-{}
-
-/*ARGSUSED*/
-void
-xrestore_ctxt(void *arg)
-{}
-
-#else	/* __lint */
-
 	ENTRY(fpxrestore_ctxt)
 	cmpl	$_CONST(FPU_EN|FPU_VALID), FPU_CTX_FPU_FLAGS(%rdi)
 	jne	1f
@@ -328,23 +241,7 @@
 	ret
 	SET_SIZE(xrestore_ctxt)
 
-#endif	/* __lint */
 
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-fpxrestore(struct fxsave_state *f)
-{}
-
-/*ARGSUSED*/
-void
-xrestore(struct xsave_state *f, uint64_t m)
-{}
-
-#else	/* __lint */
-
 	ENTRY_NP(fpxrestore)
 	CLTS
 	fxrstorq	(%rdi)
@@ -360,39 +257,19 @@
 	ret
 	SET_SIZE(xrestore)
 
-#endif	/* __lint */
-
 /*
  * Disable the floating point unit.
  */
 
-#if defined(__lint)
-
-void
-fpdisable(void)
-{}
-
-#else	/* __lint */
-
 	ENTRY_NP(fpdisable)
 	STTS(%rdi)			/* set TS bit in %cr0 (disable FPU) */ 
 	ret
 	SET_SIZE(fpdisable)
 
-#endif	/* __lint */
-
 /*
  * Initialize the fpu hardware.
  */
 
-#if defined(__lint)
-
-void
-fpinit(void)
-{}
-
-#else	/* __lint */
-
 	ENTRY_NP(fpinit)
 	CLTS
 	cmpl	$FP_XSAVE, fp_save_mech
@@ -414,25 +291,11 @@
 	ret
 	SET_SIZE(fpinit)
 
-#endif	/* __lint */
-
 /*
  * Clears FPU exception state.
  * Returns the FP status word.
  */
 
-#if defined(__lint)
-
-uint32_t
-fperr_reset(void)
-{ return (0); }
-
-uint32_t
-fpxerr_reset(void)
-{ return (0); }
-
-#else	/* __lint */
-
 	ENTRY_NP(fperr_reset)
 	CLTS
 	xorl	%eax, %eax
@@ -454,18 +317,6 @@
 	ret
 	SET_SIZE(fpxerr_reset)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-uint32_t
-fpgetcwsw(void)
-{
-	return (0);
-}
-
-#else   /* __lint */
-
 	ENTRY_NP(fpgetcwsw)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -478,22 +329,10 @@
 	ret
 	SET_SIZE(fpgetcwsw)
 
-#endif  /* __lint */
-
 /*
  * Returns the MXCSR register.
  */
 
-#if defined(__lint)
-
-uint32_t
-fpgetmxcsr(void)
-{
-	return (0);
-}
-
-#else   /* __lint */
-
 	ENTRY_NP(fpgetmxcsr)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -505,4 +344,3 @@
 	ret
 	SET_SIZE(fpgetmxcsr)
 
-#endif  /* __lint */
--- old/usr/src/uts/intel/ia32/ml/hypersubr.s	Thu Nov 14 19:00:25 2019
+++ new/usr/src/uts/intel/ia32/ml/hypersubr.s	Thu Nov 14 19:00:25 2019
@@ -37,16 +37,12 @@
 /*
  * Hypervisor "system calls"
  *
- * i386
- *	%eax == call number
- *	args in registers (%ebx, %ecx, %edx, %esi, %edi)
- *
  * amd64
  *	%rax == call number
  *	args in registers (%rdi, %rsi, %rdx, %r10, %r8, %r9)
  *
- * Note that for amd64 we use %r10 instead of %rcx for passing 4th argument
- * as in C calling convention since the "syscall" instruction clobbers %rcx.
+ * Note that we use %r10 instead of %rcx for passing 4th argument as in
+ * C calling convention since the "syscall" instruction clobbers %rcx.
  *
  * (These calls can be done more efficiently as gcc-style inlines, but
  * for simplicity and help with initial debugging, we use these primitives
@@ -53,72 +49,6 @@
  * to build the hypervisor calls up from C wrappers.)
  */
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-long
-__hypercall0(int callnum)
-{ return (0); }
-
-/*ARGSUSED*/
-long
-__hypercall1(int callnum, ulong_t a1)
-{ return (0); }
-
-/*ARGSUSED*/
-long
-__hypercall2(int callnum, ulong_t a1, ulong_t a2)
-{ return (0); }
-
-/*ARGSUSED*/
-long
-__hypercall3(int callnum, ulong_t a1, ulong_t a2, ulong_t a3)
-{ return (0); }
-
-/*ARGSUSED*/
-long
-__hypercall4(int callnum, ulong_t a1, ulong_t a2, ulong_t a3, ulong_t a4)
-{ return (0); }
-
-/*ARGSUSED*/
-long
-__hypercall5(int callnum,
-    ulong_t a1, ulong_t a2, ulong_t a3, ulong_t a4, ulong_t a5)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-__hypercall0_int(int callnum)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-__hypercall1_int(int callnum, ulong_t a1)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-__hypercall2_int(int callnum, ulong_t a1, ulong_t a2)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-__hypercall3_int(int callnum, ulong_t a1, ulong_t a2, ulong_t a3)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-__hypercall4_int(int callnum, ulong_t a1, ulong_t a2, ulong_t a3, ulong_t a4)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-__hypercall5_int(int callnum,
-    ulong_t a1, ulong_t a2, ulong_t a3, ulong_t a4, ulong_t a5)
-{ return (0); }
-
-#else	/* __lint */
-
 /*
  * XXPV grr - assembler can't deal with an instruction in a quoted string
  */
@@ -164,30 +94,17 @@
 hypercall_page:
 	.skip	HYPERCALL_PAGESIZE
 	.size	hypercall_page, HYPERCALL_PAGESIZE
-#if defined(__amd64)
 #define	TRAP_INSTR			\
 	shll	$5, %eax;		\
 	addq	$hypercall_page, %rax;	\
 	INDIRECT_JMP_REG(rax);
-#else
-#define	TRAP_INSTR			\
-	shll	$5, %eax;		\
-	addl	$hypercall_page, %eax;	\
-	call	*%eax
-#endif
 
 #else /* !_xpv */
 
-#if defined(__amd64)
 #define	TRAP_INSTR	syscall
-#elif defined(__i386)
-#define	TRAP_INSTR	int $0x82
-#endif
 #endif /* !__xpv */
 
 
-#if defined(__amd64)
-
 	ENTRY_NP(__hypercall0)
 	ALTENTRY(__hypercall0_int)
 	movl	%edi, %eax
@@ -245,81 +162,3 @@
 	ret
 	SET_SIZE(__hypercall5)
 
-#elif defined(__i386)
-
-	ENTRY_NP(__hypercall0)
-	ALTENTRY(__hypercall0_int)
-	movl	4(%esp), %eax
-	TRAP_INSTR
-	ret
-	SET_SIZE(__hypercall0)
-
-	ENTRY_NP(__hypercall1)
-	ALTENTRY(__hypercall1_int)
-	pushl	%ebx
-	movl	8(%esp), %eax
-	movl	12(%esp), %ebx
-	TRAP_INSTR
-	popl	%ebx
-	ret
-	SET_SIZE(__hypercall1)
-
-	ENTRY_NP(__hypercall2)
-	ALTENTRY(__hypercall2_int)
-	pushl	%ebx
-	movl	8(%esp), %eax
-	movl	12(%esp), %ebx
-	movl	16(%esp), %ecx
-	TRAP_INSTR
-	popl	%ebx
-	ret
-	SET_SIZE(__hypercall2)
-
-	ENTRY_NP(__hypercall3)
-	ALTENTRY(__hypercall3_int)
-	pushl	%ebx
-	movl	8(%esp), %eax
-	movl	12(%esp), %ebx
-	movl	16(%esp), %ecx
-	movl	20(%esp), %edx
-	TRAP_INSTR
-	popl	%ebx
-	ret
-	SET_SIZE(__hypercall3)
-
-	ENTRY_NP(__hypercall4)
-	ALTENTRY(__hypercall4_int)
-	pushl	%ebx
-	pushl	%esi
-	movl	12(%esp), %eax
-	movl	16(%esp), %ebx
-	movl	20(%esp), %ecx
-	movl	24(%esp), %edx
-	movl	28(%esp), %esi
-	TRAP_INSTR
-	popl	%esi
-	popl	%ebx
-	ret
-	SET_SIZE(__hypercall4)
-
-	ENTRY_NP(__hypercall5)
-	ALTENTRY(__hypercall5_int)
-	pushl	%ebx
-	pushl	%esi
-	pushl	%edi
-	movl	16(%esp), %eax
-	movl	20(%esp), %ebx
-	movl	24(%esp), %ecx
-	movl	28(%esp), %edx
-	movl	32(%esp), %esi
-	movl	36(%esp), %edi
-	TRAP_INSTR
-	popl	%edi
-	popl	%esi
-	popl	%ebx
-	ret
-	SET_SIZE(__hypercall5)
-
-#endif	/* __i386 */
-
-#endif	/* lint */
--- old/usr/src/uts/intel/ia32/ml/i86_subr.s	Thu Nov 14 19:00:25 2019
+++ new/usr/src/uts/intel/ia32/ml/i86_subr.s	Thu Nov 14 19:00:25 2019
@@ -57,17 +57,7 @@
 #include <sys/psw.h>
 #include <sys/x86_archext.h>
 
-#if defined(__lint)
-#include <sys/types.h>
-#include <sys/systm.h>
-#include <sys/thread.h>
-#include <sys/archsystm.h>
-#include <sys/byteorder.h>
-#include <sys/dtrace.h>
-#include <sys/ftrace.h>
-#else	/* __lint */
 #include "assym.h"
-#endif	/* __lint */
 #include <sys/dditypes.h>
 
 /*
@@ -80,21 +70,6 @@
  * uts/intel/ia32/ml/copy.s.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-on_fault(label_t *ljb)
-{ return (0); }
-
-void
-no_fault(void)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(on_fault)
 	movq	%gs:CPU_THREAD, %rsi
 	leaq	catch_fault(%rip), %rdx
@@ -122,52 +97,11 @@
 	ret
 	SET_SIZE(no_fault)
 
-#elif defined(__i386)
-
-	ENTRY(on_fault)
-	movl	%gs:CPU_THREAD, %edx
-	movl	4(%esp), %eax			/* jumpbuf address */
-	leal	catch_fault, %ecx
-	movl	%eax, T_ONFAULT(%edx)		/* jumpbuf in t_onfault */
-	movl	%ecx, T_LOFAULT(%edx)		/* catch_fault in t_lofault */
-	jmp	setjmp				/* let setjmp do the rest */
-
-catch_fault:
-	movl	%gs:CPU_THREAD, %edx
-	xorl	%eax, %eax
-	movl	T_ONFAULT(%edx), %ecx		/* address of save area */
-	movl	%eax, T_ONFAULT(%edx)		/* turn off onfault */
-	movl	%eax, T_LOFAULT(%edx)		/* turn off lofault */
-	pushl	%ecx
-	call	longjmp				/* let longjmp do the rest */
-	SET_SIZE(on_fault)
-
-	ENTRY(no_fault)
-	movl	%gs:CPU_THREAD, %edx
-	xorl	%eax, %eax
-	movl	%eax, T_ONFAULT(%edx)		/* turn off onfault */
-	movl	%eax, T_LOFAULT(%edx)		/* turn off lofault */
-	ret
-	SET_SIZE(no_fault)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Default trampoline code for on_trap() (see <sys/ontrap.h>).  We just
  * do a longjmp(&curthread->t_ontrap->ot_jmpbuf) if this is ever called.
  */
 
-#if defined(lint)
-
-void
-on_trap_trampoline(void)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(on_trap_trampoline)
 	movq	%gs:CPU_THREAD, %rsi
 	movq	T_ONTRAP(%rsi), %rdi
@@ -175,35 +109,12 @@
 	jmp	longjmp
 	SET_SIZE(on_trap_trampoline)
 
-#elif defined(__i386)
-
-	ENTRY(on_trap_trampoline)
-	movl	%gs:CPU_THREAD, %eax
-	movl	T_ONTRAP(%eax), %eax
-	addl	$OT_JMPBUF, %eax
-	pushl	%eax
-	call	longjmp
-	SET_SIZE(on_trap_trampoline)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Push a new element on to the t_ontrap stack.  Refer to <sys/ontrap.h> for
  * more information about the on_trap() mechanism.  If the on_trap_data is the
  * same as the topmost stack element, we just modify that element.
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-int
-on_trap(on_trap_data_t *otp, uint_t prot)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(on_trap)
 	movw	%si, OT_PROT(%rdi)		/* ot_prot = prot */
 	movw	$0, OT_TRAP(%rdi)		/* ot_trap = 0 */
@@ -224,59 +135,15 @@
 	jmp	setjmp
 	SET_SIZE(on_trap)
 
-#elif defined(__i386)
-
-	ENTRY(on_trap)
-	movl	4(%esp), %eax			/* %eax = otp */
-	movl	8(%esp), %edx			/* %edx = prot */
-
-	movw	%dx, OT_PROT(%eax)		/* ot_prot = prot */
-	movw	$0, OT_TRAP(%eax)		/* ot_trap = 0 */
-	leal	on_trap_trampoline, %edx	/* %edx = &on_trap_trampoline */
-	movl	%edx, OT_TRAMPOLINE(%eax)	/* ot_trampoline = %edx */
-	movl	$0, OT_HANDLE(%eax)		/* ot_handle = NULL */
-	movl	$0, OT_PAD1(%eax)		/* ot_pad1 = NULL */
-	movl	%gs:CPU_THREAD, %edx		/* %edx = curthread */
-	movl	T_ONTRAP(%edx), %ecx		/* %ecx = curthread->t_ontrap */
-	cmpl	%eax, %ecx			/* if (otp == %ecx) */
-	je	0f				/*    don't modify t_ontrap */
-
-	movl	%ecx, OT_PREV(%eax)		/* ot_prev = t_ontrap */
-	movl	%eax, T_ONTRAP(%edx)		/* curthread->t_ontrap = otp */
-
-0:	addl	$OT_JMPBUF, %eax		/* %eax = &ot_jmpbuf */
-	movl	%eax, 4(%esp)			/* put %eax back on the stack */
-	jmp	setjmp				/* let setjmp do the rest */
-	SET_SIZE(on_trap)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Setjmp and longjmp implement non-local gotos using state vectors
  * type label_t.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-setjmp(label_t *lp)
-{ return (0); }
-
-/* ARGSUSED */
-void
-longjmp(label_t *lp)
-{}
-
-#else	/* __lint */
-
 #if LABEL_PC != 0
 #error LABEL_PC MUST be defined as 0 for setjmp/longjmp to work as coded
 #endif	/* LABEL_PC != 0 */
 
-#if defined(__amd64)
-
 	ENTRY(setjmp)
 	movq	%rsp, LABEL_SP(%rdi)
 	movq	%rbp, LABEL_RBP(%rdi)
@@ -306,37 +173,6 @@
 	ret
 	SET_SIZE(longjmp)
 
-#elif defined(__i386)
-
-	ENTRY(setjmp)
-	movl	4(%esp), %edx		/* address of save area */
-	movl	%ebp, LABEL_EBP(%edx)
-	movl	%ebx, LABEL_EBX(%edx)
-	movl	%esi, LABEL_ESI(%edx)
-	movl	%edi, LABEL_EDI(%edx)
-	movl	%esp, 4(%edx)
-	movl	(%esp), %ecx		/* %eip (return address) */
-	movl	%ecx, (%edx)		/* LABEL_PC is 0 */
-	subl	%eax, %eax		/* return 0 */
-	ret
-	SET_SIZE(setjmp)
-
-	ENTRY(longjmp)
-	movl	4(%esp), %edx		/* address of save area */
-	movl	LABEL_EBP(%edx), %ebp
-	movl	LABEL_EBX(%edx), %ebx
-	movl	LABEL_ESI(%edx), %esi
-	movl	LABEL_EDI(%edx), %edi
-	movl	4(%edx), %esp
-	movl	(%edx), %ecx		/* %eip (return addr); LABEL_PC is 0 */
-	movl	$1, %eax
-	addl	$4, %esp		/* pop ret adr */
-	jmp	*%ecx			/* indirect */
-	SET_SIZE(longjmp)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * if a() calls b() calls caller(),
  * caller() returns return address in a().
@@ -344,171 +180,44 @@
  *  sequence.)
  */
 
-#if defined(__lint)
-
-caddr_t
-caller(void)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(caller)
 	movq	8(%rbp), %rax		/* b()'s return pc, in a() */
 	ret
 	SET_SIZE(caller)
 
-#elif defined(__i386)
-
-	ENTRY(caller)
-	movl	4(%ebp), %eax		/* b()'s return pc, in a() */
-	ret
-	SET_SIZE(caller)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * if a() calls callee(), callee() returns the
  * return address in a();
  */
 
-#if defined(__lint)
-
-caddr_t
-callee(void)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(callee)
 	movq	(%rsp), %rax		/* callee()'s return pc, in a() */
 	ret
 	SET_SIZE(callee)
 
-#elif defined(__i386)
-
-	ENTRY(callee)
-	movl	(%esp), %eax		/* callee()'s return pc, in a() */
-	ret
-	SET_SIZE(callee)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * return the current frame pointer
  */
 
-#if defined(__lint)
-
-greg_t
-getfp(void)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(getfp)
 	movq	%rbp, %rax
 	ret
 	SET_SIZE(getfp)
 
-#elif defined(__i386)
-
-	ENTRY(getfp)
-	movl	%ebp, %eax
-	ret
-	SET_SIZE(getfp)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Invalidate a single page table entry in the TLB
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-mmu_invlpg(caddr_t m)
-{}
-
-#else	/* __lint */
-
 	ENTRY(mmu_invlpg)
 	invlpg	(%rdi)
 	ret
 	SET_SIZE(mmu_invlpg)
 
-#endif	/* __lint */
 
-
 /*
  * Get/Set the value of various control registers
  */
 
-#if defined(__lint)
-
-ulong_t
-getcr0(void)
-{ return (0); }
-
-/* ARGSUSED */
-void
-setcr0(ulong_t value)
-{}
-
-ulong_t
-getcr2(void)
-{ return (0); }
-
-ulong_t
-getcr3(void)
-{ return (0); }
-
-#if !defined(__xpv)
-/* ARGSUSED */
-void
-setcr3(ulong_t val)
-{}
-
-void
-reload_cr3(void)
-{}
-#endif
-
-ulong_t
-getcr4(void)
-{ return (0); }
-
-/* ARGSUSED */
-void
-setcr4(ulong_t val)
-{}
-
-#if defined(__amd64)
-
-ulong_t
-getcr8(void)
-{ return (0); }
-
-/* ARGSUSED */
-void
-setcr8(ulong_t val)
-{}
-
-#endif	/* __amd64 */
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(getcr0)
 	movq	%cr0, %rax
 	ret
@@ -569,93 +278,6 @@
 	ret
 	SET_SIZE(setcr8)
 
-#elif defined(__i386)
-
-        ENTRY(getcr0)
-        movl    %cr0, %eax
-        ret
-	SET_SIZE(getcr0)
-
-        ENTRY(setcr0)
-        movl    4(%esp), %eax
-        movl    %eax, %cr0
-        ret
-	SET_SIZE(setcr0)
-
-	/*
-	 * "lock mov %cr0" is used on processors which indicate it is
-	 * supported via CPUID. Normally the 32 bit TPR is accessed via
-	 * the local APIC.
-	 */
-	ENTRY(getcr8)
-	lock
-	movl	%cr0, %eax
-	ret
-	SET_SIZE(getcr8)
-
-	ENTRY(setcr8)
-        movl    4(%esp), %eax
-	lock
-        movl    %eax, %cr0
-	ret
-	SET_SIZE(setcr8)
-
-        ENTRY(getcr2)
-#if defined(__xpv)
-	movl	%gs:CPU_VCPU_INFO, %eax
-	movl	VCPU_INFO_ARCH_CR2(%eax), %eax
-#else
-        movl    %cr2, %eax
-#endif
-        ret
-	SET_SIZE(getcr2)
-
-	ENTRY(getcr3)
-	movl    %cr3, %eax
-	ret
-	SET_SIZE(getcr3)
-
-#if !defined(__xpv)
-
-        ENTRY(setcr3)
-        movl    4(%esp), %eax
-        movl    %eax, %cr3
-        ret
-	SET_SIZE(setcr3)
-
-	ENTRY(reload_cr3)
-	movl    %cr3, %eax
-	movl    %eax, %cr3
-	ret
-	SET_SIZE(reload_cr3)
-
-#endif	/* __xpv */
-
-	ENTRY(getcr4)
-	movl    %cr4, %eax
-	ret
-	SET_SIZE(getcr4)
-
-        ENTRY(setcr4)
-        movl    4(%esp), %eax
-        movl    %eax, %cr4
-        ret
-	SET_SIZE(setcr4)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-uint32_t
-__cpuid_insn(struct cpuid_regs *regs)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(__cpuid_insn)
 	movq	%rbx, %r8
 	movq	%rcx, %r9
@@ -675,44 +297,6 @@
 	ret
 	SET_SIZE(__cpuid_insn)
 
-#elif defined(__i386)
-
-        ENTRY(__cpuid_insn)
-	pushl	%ebp
-	movl	0x8(%esp), %ebp		/* %ebp = regs */
-	pushl	%ebx
-	pushl	%ecx
-	pushl	%edx
-	movl	(%ebp), %eax		/* %eax = regs->cp_eax */
-	movl	0x4(%ebp), %ebx		/* %ebx = regs->cp_ebx */
-	movl	0x8(%ebp), %ecx		/* %ecx = regs->cp_ecx */
-	movl	0xc(%ebp), %edx		/* %edx = regs->cp_edx */
-	cpuid
-	movl	%eax, (%ebp)		/* regs->cp_eax = %eax */
-	movl	%ebx, 0x4(%ebp)		/* regs->cp_ebx = %ebx */
-	movl	%ecx, 0x8(%ebp)		/* regs->cp_ecx = %ecx */
-	movl	%edx, 0xc(%ebp)		/* regs->cp_edx = %edx */
-	popl	%edx
-	popl	%ecx
-	popl	%ebx
-	popl	%ebp
-	ret
-	SET_SIZE(__cpuid_insn)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-i86_monitor(volatile uint32_t *addr, uint32_t extensions, uint32_t hints)
-{}
-
-#else   /* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(i86_monitor)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -725,34 +309,6 @@
 	ret
 	SET_SIZE(i86_monitor)
 
-#elif defined(__i386)
-
-ENTRY_NP(i86_monitor)
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	0x8(%ebp),%eax		/* addr */
-	movl	0xc(%ebp),%ecx		/* extensions */
-	movl	0x10(%ebp),%edx		/* hints */
-	clflush	(%eax)
-	.byte	0x0f, 0x01, 0xc8	/* monitor */
-	leave
-	ret
-	SET_SIZE(i86_monitor)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-i86_mwait(uint32_t data, uint32_t extensions)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(i86_mwait)
 	pushq	%rbp
 	call	x86_md_clear
@@ -764,21 +320,6 @@
 	ret
 	SET_SIZE(i86_mwait)
 
-#elif defined(__i386)
-
-	ENTRY_NP(i86_mwait)
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	0x8(%ebp),%eax		/* data */
-	movl	0xc(%ebp),%ecx		/* extensions */
-	.byte	0x0f, 0x01, 0xc9	/* mwait */
-	leave
-	ret
-	SET_SIZE(i86_mwait)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 #if defined(__xpv)
 	/*
 	 * Defined in C
@@ -785,18 +326,6 @@
 	 */
 #else
 
-#if defined(__lint)
-
-hrtime_t
-tsc_read(void)
-{
-	return (0);
-}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(tsc_read)
 	movq	%rbx, %r11
 	movl	$0, %eax
@@ -841,64 +370,9 @@
 _tsc_lfence_end:
 	SET_SIZE(tsc_read)
 
-#else /* __i386 */
 
-	ENTRY_NP(tsc_read)
-	pushl	%ebx
-	movl	$0, %eax
-	cpuid
-	rdtsc
-	popl	%ebx
-	ret
-	.globl _tsc_mfence_start
-_tsc_mfence_start:
-	mfence
-	rdtsc
-	ret
-	.globl _tsc_mfence_end
-_tsc_mfence_end:
-	.globl	_tscp_start
-_tscp_start:
-	.byte	0x0f, 0x01, 0xf9	/* rdtscp instruction */
-	ret
-	.globl _tscp_end
-_tscp_end:
-	.globl _no_rdtsc_start
-_no_rdtsc_start:
-	xorl	%edx, %edx
-	xorl	%eax, %eax
-	ret
-	.globl _no_rdtsc_end
-_no_rdtsc_end:
-	.globl _tsc_lfence_start
-_tsc_lfence_start:
-	lfence
-	rdtsc
-	ret
-	.globl _tsc_lfence_end
-_tsc_lfence_end:
-	SET_SIZE(tsc_read)
-
-#endif	/* __i386 */
-
-#endif	/* __lint */
-
-
 #endif	/* __xpv */
 
-#ifdef __lint
-/*
- * Do not use this function for obtaining clock tick.  This
- * is called by callers who do not need to have a guarenteed
- * correct tick value.  The proper routine to use is tsc_read().
- */
-u_longlong_t
-randtick(void)
-{
-	return (0);
-}
-#else
-#if defined(__amd64)
 	ENTRY_NP(randtick)
 	rdtsc
 	shlq    $32, %rdx
@@ -905,28 +379,10 @@
 	orq     %rdx, %rax
 	ret
 	SET_SIZE(randtick)
-#else
-	ENTRY_NP(randtick)
-	rdtsc
-	ret
-	SET_SIZE(randtick)
-#endif /* __i386 */
-#endif /* __lint */
 /*
  * Insert entryp after predp in a doubly linked list.
  */
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-_insque(caddr_t entryp, caddr_t predp)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(_insque)
 	movq	(%rsi), %rax		/* predp->forw			*/
 	movq	%rsi, CPTRSIZE(%rdi)	/* entryp->back = predp		*/
@@ -936,37 +392,10 @@
 	ret
 	SET_SIZE(_insque)
 
-#elif defined(__i386)
-
-	ENTRY(_insque)
-	movl	8(%esp), %edx
-	movl	4(%esp), %ecx
-	movl	(%edx), %eax		/* predp->forw			*/
-	movl	%edx, CPTRSIZE(%ecx)	/* entryp->back = predp		*/
-	movl	%eax, (%ecx)		/* entryp->forw = predp->forw	*/
-	movl	%ecx, (%edx)		/* predp->forw = entryp		*/
-	movl	%ecx, CPTRSIZE(%eax)	/* predp->forw->back = entryp	*/
-	ret
-	SET_SIZE(_insque)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Remove entryp from a doubly linked list
  */
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-_remque(caddr_t entryp)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(_remque)
 	movq	(%rdi), %rax		/* entry->forw */
 	movq	CPTRSIZE(%rdi), %rdx	/* entry->back */
@@ -975,36 +404,11 @@
 	ret
 	SET_SIZE(_remque)
 
-#elif defined(__i386)
-
-	ENTRY(_remque)
-	movl	4(%esp), %ecx
-	movl	(%ecx), %eax		/* entry->forw */
-	movl	CPTRSIZE(%ecx), %edx	/* entry->back */
-	movl	%eax, (%edx)		/* entry->back->forw = entry->forw */
-	movl	%edx, CPTRSIZE(%eax)	/* entry->forw->back = entry->back */
-	ret
-	SET_SIZE(_remque)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Returns the number of
  * non-NULL bytes in string argument.
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-size_t
-strlen(const char *str)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 /*
  * This is close to a simple transliteration of a C version of this
  * routine.  We should either just -make- this be a C version, or
@@ -1050,58 +454,12 @@
 	ret
 	SET_SIZE(strlen)
 
-#elif defined(__i386)
-
-	ENTRY(strlen)
 #ifdef DEBUG
-	movl	postbootkernelbase, %eax
-	cmpl	%eax, 4(%esp)
-	jae	str_valid
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	$.str_panic_msg
-	call	panic
-#endif /* DEBUG */
-
-str_valid:
-	movl	4(%esp), %eax		/* %eax = string address */
-	testl	$3, %eax		/* if %eax not word aligned */
-	jnz	.not_word_aligned	/* goto .not_word_aligned */
-	.align	4
-.word_aligned:
-	movl	(%eax), %edx		/* move 1 word from (%eax) to %edx */
-	movl	$0x7f7f7f7f, %ecx
-	andl	%edx, %ecx		/* %ecx = %edx & 0x7f7f7f7f */
-	addl	$4, %eax		/* next word */
-	addl	$0x7f7f7f7f, %ecx	/* %ecx += 0x7f7f7f7f */
-	orl	%edx, %ecx		/* %ecx |= %edx */
-	andl	$0x80808080, %ecx	/* %ecx &= 0x80808080 */
-	cmpl	$0x80808080, %ecx	/* if no null byte in this word */
-	je	.word_aligned		/* goto .word_aligned */
-	subl	$4, %eax		/* post-incremented */
-.not_word_aligned:
-	cmpb	$0, (%eax)		/* if a byte in (%eax) is null */
-	je	.null_found		/* goto .null_found */
-	incl	%eax			/* next byte */
-	testl	$3, %eax		/* if %eax not word aligned */
-	jnz	.not_word_aligned	/* goto .not_word_aligned */
-	jmp	.word_aligned		/* goto .word_aligned */
-	.align	4
-.null_found:
-	subl	4(%esp), %eax		/* %eax -= string address */
-	ret
-	SET_SIZE(strlen)
-
-#endif	/* __i386 */
-
-#ifdef DEBUG
 	.text
 .str_panic_msg:
 	.string "strlen: argument below kernelbase"
 #endif /* DEBUG */
 
-#endif	/* __lint */
-
 	/*
 	 * Berkeley 4.3 introduced symbolically named interrupt levels
 	 * as a way deal with priority in a machine independent fashion.
@@ -1140,25 +498,6 @@
 	 *	spl0()		Used to lower priority to 0.
 	 */
 
-#if defined(__lint)
-
-int spl0(void)		{ return (0); }
-int spl6(void)		{ return (0); }
-int spl7(void)		{ return (0); }
-int spl8(void)		{ return (0); }
-int splhigh(void)	{ return (0); }
-int splhi(void)		{ return (0); }
-int splzs(void)		{ return (0); }
-
-/* ARGSUSED */
-void
-splx(int level)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 #define	SETPRI(level) \
 	movl	$/**/level, %edi;	/* new priority */		\
 	jmp	do_splx			/* redirect to do_splx */
@@ -1167,22 +506,6 @@
 	movl	$/**/level, %edi;	/* new priority */		\
 	jmp	splr			/* redirect to splr */
 
-#elif defined(__i386)
-
-#define	SETPRI(level) \
-	pushl	$/**/level;	/* new priority */			\
-	call	do_splx;	/* invoke common splx code */		\
-	addl	$4, %esp;	/* unstack arg */			\
-	ret
-
-#define	RAISE(level) \
-	pushl	$/**/level;	/* new priority */			\
-	call	splr;		/* invoke common splr code */		\
-	addl	$4, %esp;	/* unstack args */			\
-	ret
-
-#endif	/* __i386 */
-
 	/* locks out all interrupts, including memory errors */
 	ENTRY(spl8)
 	SETPRI(15)
@@ -1221,70 +544,14 @@
 	jmp	do_splx		/* redirect to common splx code */
 	SET_SIZE(splx)
 
-#endif	/* __lint */
-
-#if defined(__i386)
-
-/*
- * Read and write the %gs register
- */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-uint16_t
-getgs(void)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-setgs(uint16_t sel)
-{}
-
-#else	/* __lint */
-
-	ENTRY(getgs)
-	clr	%eax
-	movw	%gs, %ax
-	ret
-	SET_SIZE(getgs)
-
-	ENTRY(setgs)
-	movw	4(%esp), %gs
-	ret
-	SET_SIZE(setgs)
-
-#endif	/* __lint */
-#endif	/* __i386 */
-
-#if defined(__lint)
-
-void
-pc_reset(void)
-{}
-
-void
-efi_reset(void)
-{}
-
-#else	/* __lint */
-
 	ENTRY(wait_500ms)
-#if defined(__amd64)
 	pushq	%rbx
-#elif defined(__i386)
-	push	%ebx
-#endif
 	movl	$50000, %ebx
 1:
 	call	tenmicrosec
 	decl	%ebx
 	jnz	1b
-#if defined(__amd64)
 	popq	%rbx
-#elif defined(__i386)
-	pop	%ebx
-#endif
 	ret
 	SET_SIZE(wait_500ms)
 
@@ -1297,11 +564,7 @@
 
 	ENTRY(pc_reset)
 
-#if defined(__i386)
-	testl	$RESET_METHOD_KBC, pc_reset_methods
-#elif defined(__amd64)
 	testl	$RESET_METHOD_KBC, pc_reset_methods(%rip)
-#endif
 	jz	1f
 
 	/
@@ -1321,11 +584,7 @@
 	call	wait_500ms
 
 1:
-#if defined(__i386)
-	testl	$RESET_METHOD_PORT92, pc_reset_methods
-#elif defined(__amd64)
 	testl	$RESET_METHOD_PORT92, pc_reset_methods(%rip)
-#endif
 	jz	3f
 
 	/
@@ -1347,11 +606,7 @@
 	call	wait_500ms
 
 3:
-#if defined(__i386)
-	testl	$RESET_METHOD_PCI, pc_reset_methods
-#elif defined(__amd64)
 	testl	$RESET_METHOD_PCI, pc_reset_methods(%rip)
-#endif
 	jz	4f
 
 	/ Try the PCI (soft) reset vector (should work on all modern systems,
@@ -1360,7 +615,7 @@
 	/ When resetting via this method, 2 writes are required.  The first
 	/ targets bit 1 (0=hard reset without power cycle, 1=hard reset with
 	/ power cycle).
-	/ The reset occurs on the second write, during bit 2's transition from
+	/ The reset occurs on the second write, during bit 2 's transition from
 	/ 0->1.
 	movw	$0xcf9, %dx
 	movb	$0x2, %al	/ Reset mode = hard, no power cycle
@@ -1377,15 +632,9 @@
 	/ Also, use triple fault for EFI firmware
 	/
 	ENTRY(efi_reset)
-#if defined(__amd64)
 	pushq	$0x0
 	pushq	$0x0		/ IDT base of 0, limit of 0 + 2 unused bytes
 	lidt	(%rsp)
-#elif defined(__i386)
-	pushl	$0x0
-	pushl	$0x0		/ IDT base of 0, limit of 0 + 2 unused bytes
-	lidt	(%esp)
-#endif
 	int	$0x0		/ Trigger interrupt, generate triple-fault
 
 	cli
@@ -1394,23 +643,10 @@
 	SET_SIZE(efi_reset)
 	SET_SIZE(pc_reset)
 
-#endif	/* __lint */
-
 /*
  * C callable in and out routines
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-outl(int port_address, uint32_t val)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(outl)
 	movw	%di, %dx
 	movl	%esi, %eax
@@ -1418,32 +654,6 @@
 	ret
 	SET_SIZE(outl)
 
-#elif defined(__i386)
-
-	.set	PORT, 4
-	.set	VAL, 8
-
-	ENTRY(outl)
-	movw	PORT(%esp), %dx
-	movl	VAL(%esp), %eax
-	outl	(%dx)
-	ret
-	SET_SIZE(outl)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-outw(int port_address, uint16_t val)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(outw)
 	movw	%di, %dx
 	movw	%si, %ax
@@ -1451,29 +661,6 @@
 	ret
 	SET_SIZE(outw)
 
-#elif defined(__i386)
-
-	ENTRY(outw)
-	movw	PORT(%esp), %dx
-	movw	VAL(%esp), %ax
-	D16 outl (%dx)
-	ret
-	SET_SIZE(outw)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-outb(int port_address, uint8_t val)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(outb)
 	movw	%di, %dx
 	movb	%sil, %al
@@ -1481,29 +668,6 @@
 	ret
 	SET_SIZE(outb)
 
-#elif defined(__i386)
-
-	ENTRY(outb)
-	movw	PORT(%esp), %dx
-	movb	VAL(%esp), %al
-	outb	(%dx)
-	ret
-	SET_SIZE(outb)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-uint32_t
-inl(int port_address)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(inl)
 	xorl	%eax, %eax
 	movw	%di, %dx
@@ -1511,28 +675,6 @@
 	ret
 	SET_SIZE(inl)
 
-#elif defined(__i386)
-
-	ENTRY(inl)
-	movw	PORT(%esp), %dx
-	inl	(%dx)
-	ret
-	SET_SIZE(inl)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-uint16_t
-inw(int port_address)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(inw)
 	xorl	%eax, %eax
 	movw	%di, %dx
@@ -1540,30 +682,7 @@
 	ret
 	SET_SIZE(inw)
 
-#elif defined(__i386)
 
-	ENTRY(inw)
-	subl	%eax, %eax
-	movw	PORT(%esp), %dx
-	D16 inl	(%dx)
-	ret
-	SET_SIZE(inw)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(__lint)
-
-/* ARGSUSED */
-uint8_t
-inb(int port_address)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(inb)
 	xorl	%eax, %eax
 	movw	%di, %dx
@@ -1571,30 +690,7 @@
 	ret
 	SET_SIZE(inb)
 
-#elif defined(__i386)
 
-	ENTRY(inb)
-	subl    %eax, %eax
-	movw	PORT(%esp), %dx
-	inb	(%dx)
-	ret
-	SET_SIZE(inb)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-repoutsw(int port, uint16_t *addr, int cnt)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(repoutsw)
 	movl	%edx, %ecx
 	movw	%di, %dx
@@ -1603,49 +699,7 @@
 	ret
 	SET_SIZE(repoutsw)
 
-#elif defined(__i386)
 
-	/*
-	 * The arguments and saved registers are on the stack in the
-	 *  following order:
-	 *      |  cnt  |  +16
-	 *      | *addr |  +12
-	 *      | port  |  +8
-	 *      |  eip  |  +4
-	 *      |  esi  |  <-- %esp
-	 * If additional values are pushed onto the stack, make sure
-	 * to adjust the following constants accordingly.
-	 */
-	.set	PORT, 8
-	.set	ADDR, 12
-	.set	COUNT, 16
-
-	ENTRY(repoutsw)
-	pushl	%esi
-	movl	PORT(%esp), %edx
-	movl	ADDR(%esp), %esi
-	movl	COUNT(%esp), %ecx
-	rep
-	  D16 outsl
-	popl	%esi
-	ret
-	SET_SIZE(repoutsw)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-repinsw(int port_addr, uint16_t *addr, int cnt)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(repinsw)
 	movl	%edx, %ecx
 	movw	%di, %dx
@@ -1654,34 +708,7 @@
 	ret
 	SET_SIZE(repinsw)
 
-#elif defined(__i386)
 
-	ENTRY(repinsw)
-	pushl	%edi
-	movl	PORT(%esp), %edx
-	movl	ADDR(%esp), %edi
-	movl	COUNT(%esp), %ecx
-	rep
-	  D16 insl
-	popl	%edi
-	ret
-	SET_SIZE(repinsw)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-repinsb(int port, uint8_t *addr, int count)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(repinsb)
 	movl	%edx, %ecx
 	movw	%di, %dx
@@ -1691,53 +718,12 @@
 	ret
 	SET_SIZE(repinsb)
 
-#elif defined(__i386)
 
-	/*
-	 * The arguments and saved registers are on the stack in the
-	 *  following order:
-	 *      |  cnt  |  +16
-	 *      | *addr |  +12
-	 *      | port  |  +8
-	 *      |  eip  |  +4
-	 *      |  esi  |  <-- %esp
-	 * If additional values are pushed onto the stack, make sure
-	 * to adjust the following constants accordingly.
-	 */
-	.set	IO_PORT, 8
-	.set	IO_ADDR, 12
-	.set	IO_COUNT, 16
-
-	ENTRY(repinsb)
-	pushl	%edi
-	movl	IO_ADDR(%esp), %edi
-	movl	IO_COUNT(%esp), %ecx
-	movl	IO_PORT(%esp), %edx
-	rep
-	  insb
-	popl	%edi
-	ret
-	SET_SIZE(repinsb)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
 /*
  * Input a stream of 32-bit words.
  * NOTE: count is a DWORD count.
  */
-#if defined(__lint)
 
-/* ARGSUSED */
-void
-repinsd(int port, uint32_t *addr, int count)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(repinsd)
 	movl	%edx, %ecx
 	movw	%di, %dx
@@ -1747,37 +733,11 @@
 	ret
 	SET_SIZE(repinsd)
 
-#elif defined(__i386)
-
-	ENTRY(repinsd)
-	pushl	%edi
-	movl	IO_ADDR(%esp), %edi
-	movl	IO_COUNT(%esp), %ecx
-	movl	IO_PORT(%esp), %edx
-	rep
-	  insl
-	popl	%edi
-	ret
-	SET_SIZE(repinsd)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Output a stream of bytes
  * NOTE: count is a byte count
  */
-#if defined(__lint)
 
-/* ARGSUSED */
-void
-repoutsb(int port, uint8_t *addr, int count)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(repoutsb)
 	movl	%edx, %ecx
 	movw	%di, %dx
@@ -1786,37 +746,11 @@
 	ret
 	SET_SIZE(repoutsb)
 
-#elif defined(__i386)
-
-	ENTRY(repoutsb)
-	pushl	%esi
-	movl	IO_ADDR(%esp), %esi
-	movl	IO_COUNT(%esp), %ecx
-	movl	IO_PORT(%esp), %edx
-	rep
-	  outsb
-	popl	%esi
-	ret
-	SET_SIZE(repoutsb)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Output a stream of 32-bit words
  * NOTE: count is a DWORD count
  */
-#if defined(__lint)
 
-/* ARGSUSED */
-void
-repoutsd(int port, uint32_t *addr, int count)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(repoutsd)
 	movl	%edx, %ecx
 	movw	%di, %dx
@@ -1825,22 +759,6 @@
 	ret
 	SET_SIZE(repoutsd)
 
-#elif defined(__i386)
-
-	ENTRY(repoutsd)
-	pushl	%esi
-	movl	IO_ADDR(%esp), %esi
-	movl	IO_COUNT(%esp), %ecx
-	movl	IO_PORT(%esp), %edx
-	rep
-	  outsl
-	popl	%esi
-	ret
-	SET_SIZE(repoutsd)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * void int3(void)
  * void int18(void)
@@ -1848,26 +766,6 @@
  * void int_cmci(void)
  */
 
-#if defined(__lint)
-
-void
-int3(void)
-{}
-
-void
-int18(void)
-{}
-
-void
-int20(void)
-{}
-
-void
-int_cmci(void)
-{}
-
-#else	/* __lint */
-
 	ENTRY(int3)
 	int	$T_BPTFLT
 	ret
@@ -1894,19 +792,6 @@
 	ret
 	SET_SIZE(int_cmci)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/* ARGSUSED */
-int
-scanc(size_t size, uchar_t *cp, uchar_t *table, uchar_t mask)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(scanc)
 					/* rdi == size */
 					/* rsi == cp */
@@ -1927,55 +812,11 @@
 	ret
 	SET_SIZE(scanc)
 
-#elif defined(__i386)
-
-	ENTRY(scanc)
-	pushl	%edi
-	pushl	%esi
-	movb	24(%esp), %cl		/* mask = %cl */
-	movl	16(%esp), %esi		/* cp = %esi */
-	movl	20(%esp), %edx		/* table = %edx */
-	movl	%esi, %edi
-	addl	12(%esp), %edi		/* end = &cp[size]; */
-.scanloop:
-	cmpl	%edi, %esi		/* while (cp < end */
-	jnb	.scandone
-	movzbl	(%esi),  %eax		/* %al = *cp */
-	incl	%esi			/* cp++ */
-	movb	(%edx,  %eax), %al	/* %al = table[*cp] */
-	testb	%al, %cl
-	jz	.scanloop		/*   && (table[*cp] & mask) == 0) */
-	dec	%esi			/* post-incremented */
-.scandone:
-	movl	%edi, %eax
-	subl	%esi, %eax		/* return (end - cp) */
-	popl	%esi
-	popl	%edi
-	ret
-	SET_SIZE(scanc)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * Replacement functions for ones that are normally inlined.
  * In addition to the copy in i86.il, they are defined here just in case.
  */
 
-#if defined(__lint)
-
-ulong_t
-intr_clear(void)
-{ return (0); }
-
-ulong_t
-clear_int_flag(void)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(intr_clear)
 	ENTRY(clear_int_flag)
 	pushfq
@@ -2002,62 +843,11 @@
 	SET_SIZE(clear_int_flag)
 	SET_SIZE(intr_clear)
 
-#elif defined(__i386)
-
-	ENTRY(intr_clear)
-	ENTRY(clear_int_flag)
-	pushfl
-	popl	%eax
-#if defined(__xpv)
-	leal	xpv_panicking, %edx
-	movl	(%edx), %edx
-	cmpl	$0, %edx
-	jne	2f
-	CLIRET(%edx, %cl)	/* returns event mask in %cl */
-	/*
-	 * Synthesize the PS_IE bit from the event mask bit
-	 */
-	andl    $_BITNOT(PS_IE), %eax
-	testb	$1, %cl
-	jnz	1f
-	orl	$PS_IE, %eax
-1:
-	ret
-2:
-#endif
-	CLI(%edx)
-	ret
-	SET_SIZE(clear_int_flag)
-	SET_SIZE(intr_clear)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-struct cpu *
-curcpup(void)
-{ return 0; }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(curcpup)
 	movq	%gs:CPU_SELF, %rax
 	ret
 	SET_SIZE(curcpup)
 
-#elif defined(__i386)
-
-	ENTRY(curcpup)
-	movl	%gs:CPU_SELF, %eax
-	ret
-	SET_SIZE(curcpup)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /* htonll(), ntohll(), htonl(), ntohl(), htons(), ntohs()
  * These functions reverse the byte order of the input parameter and returns
  * the result.  This is to convert the byte order from host byte order
@@ -2064,36 +854,6 @@
  * (little endian) to network byte order (big endian), or vice versa.
  */
 
-#if defined(__lint)
-
-uint64_t
-htonll(uint64_t i)
-{ return (i); }
-
-uint64_t
-ntohll(uint64_t i)
-{ return (i); }
-
-uint32_t
-htonl(uint32_t i)
-{ return (i); }
-
-uint32_t
-ntohl(uint32_t i)
-{ return (i); }
-
-uint16_t
-htons(uint16_t i)
-{ return (i); }
-
-uint16_t
-ntohs(uint16_t i)
-{ return (i); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(htonll)
 	ALTENTRY(ntohll)
 	movq	%rdi, %rax
@@ -2121,55 +881,7 @@
 	SET_SIZE(ntohs)
 	SET_SIZE(htons)
 
-#elif defined(__i386)
 
-	ENTRY(htonll)
-	ALTENTRY(ntohll)
-	movl	4(%esp), %edx
-	movl	8(%esp), %eax
-	bswap	%edx
-	bswap	%eax
-	ret
-	SET_SIZE(ntohll)
-	SET_SIZE(htonll)
-
-	ENTRY(htonl)
-	ALTENTRY(ntohl)
-	movl	4(%esp), %eax
-	bswap	%eax
-	ret
-	SET_SIZE(ntohl)
-	SET_SIZE(htonl)
-
-	ENTRY(htons)
-	ALTENTRY(ntohs)
-	movl	4(%esp), %eax
-	bswap	%eax
-	shrl	$16, %eax
-	ret
-	SET_SIZE(ntohs)
-	SET_SIZE(htons)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-intr_restore(ulong_t i)
-{ return; }
-
-/* ARGSUSED */
-void
-restore_int_flag(ulong_t i)
-{ return; }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(intr_restore)
 	ENTRY(restore_int_flag)
 	testq	$PS_IE, %rdi
@@ -2193,46 +905,6 @@
 	SET_SIZE(restore_int_flag)
 	SET_SIZE(intr_restore)
 
-#elif defined(__i386)
-
-	ENTRY(intr_restore)
-	ENTRY(restore_int_flag)
-	testl	$PS_IE, 4(%esp)
-	jz	1f
-#if defined(__xpv)
-	leal	xpv_panicking, %edx
-	movl	(%edx), %edx
-	cmpl	$0, %edx
-	jne	1f
-	/*
-	 * Since we're -really- running unprivileged, our attempt
-	 * to change the state of the IF bit will be ignored.
-	 * The virtual IF bit is tweaked by CLI and STI.
-	 */
-	IE_TO_EVENT_MASK(%edx, 4(%esp))
-#else
-	sti
-#endif
-1:
-	ret
-	SET_SIZE(restore_int_flag)
-	SET_SIZE(intr_restore)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-void
-sti(void)
-{}
-
-void
-cli(void)
-{}
-
-#else	/* __lint */
-
 	ENTRY(sti)
 	STI
 	ret
@@ -2239,26 +911,10 @@
 	SET_SIZE(sti)
 
 	ENTRY(cli)
-#if defined(__amd64)
 	CLI(%rax)
-#elif defined(__i386)
-	CLI(%eax)
-#endif	/* __i386 */
 	ret
 	SET_SIZE(cli)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-dtrace_icookie_t
-dtrace_interrupt_disable(void)
-{ return (0); }
-
-#else   /* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(dtrace_interrupt_disable)
 	pushfq
 	popq	%rax
@@ -2282,45 +938,6 @@
 	ret
 	SET_SIZE(dtrace_interrupt_disable)
 
-#elif defined(__i386)
-
-	ENTRY(dtrace_interrupt_disable)
-	pushfl
-	popl	%eax
-#if defined(__xpv)
-	leal	xpv_panicking, %edx
-	movl	(%edx), %edx
-	cmpl	$0, %edx
-	jne	.dtrace_interrupt_disable_done
-	CLIRET(%edx, %cl)	/* returns event mask in %cl */
-	/*
-	 * Synthesize the PS_IE bit from the event mask bit
-	 */
-	andl    $_BITNOT(PS_IE), %eax
-	testb	$1, %cl
-	jnz	.dtrace_interrupt_disable_done
-	orl	$PS_IE, %eax
-#else
-	CLI(%edx)
-#endif
-.dtrace_interrupt_disable_done:
-	ret
-	SET_SIZE(dtrace_interrupt_disable)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-dtrace_interrupt_enable(dtrace_icookie_t cookie)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(dtrace_interrupt_enable)
 	pushq	%rdi
 	popfq
@@ -2340,44 +957,7 @@
 	ret
 	SET_SIZE(dtrace_interrupt_enable)
 
-#elif defined(__i386)
 
-	ENTRY(dtrace_interrupt_enable)
-	movl	4(%esp), %eax
-	pushl	%eax
-	popfl
-#if defined(__xpv)
-	leal	xpv_panicking, %edx
-	movl	(%edx), %edx
-	cmpl	$0, %edx
-	jne	.dtrace_interrupt_enable_done
-	/*
-	 * Since we're -really- running unprivileged, our attempt
-	 * to change the state of the IF bit will be ignored. The
-	 * virtual IF bit is tweaked by CLI and STI.
-	 */
-	IE_TO_EVENT_MASK(%edx, %eax)
-#endif
-.dtrace_interrupt_enable_done:
-	ret
-	SET_SIZE(dtrace_interrupt_enable)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(lint)
-
-void
-dtrace_membar_producer(void)
-{}
-
-void
-dtrace_membar_consumer(void)
-{}
-
-#else	/* __lint */
-
 	ENTRY(dtrace_membar_producer)
 	rep;	ret	/* use 2 byte return instruction when branch target */
 			/* AMD Software Optimization Guide - Section 6.2 */
@@ -2388,70 +968,15 @@
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(dtrace_membar_consumer)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-kthread_id_t
-threadp(void)
-{ return ((kthread_id_t)0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(threadp)
 	movq	%gs:CPU_THREAD, %rax
 	ret
 	SET_SIZE(threadp)
 
-#elif defined(__i386)
-
-	ENTRY(threadp)
-	movl	%gs:CPU_THREAD, %eax
-	ret
-	SET_SIZE(threadp)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  *   Checksum routine for Internet Protocol Headers
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-unsigned int
-ip_ocsum(
-	ushort_t *address,	/* ptr to 1st message buffer */
-	int halfword_count,	/* length of data */
-	unsigned int sum)	/* partial checksum */
-{
-	int		i;
-	unsigned int	psum = 0;	/* partial sum */
-
-	for (i = 0; i < halfword_count; i++, address++) {
-		psum += *address;
-	}
-
-	while ((psum >> 16) != 0) {
-		psum = (psum & 0xffff) + (psum >> 16);
-	}
-
-	psum += sum;
-
-	while ((psum >> 16) != 0) {
-		psum = (psum & 0xffff) + (psum >> 16);
-	}
-
-	return (psum);
-}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(ip_ocsum)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -2570,140 +1095,11 @@
 	.quad	.only48, .only52, .only56, .only60
 	SET_SIZE(ip_ocsum)
 
-#elif defined(__i386)
-
-	ENTRY(ip_ocsum)
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	%ebx
-	pushl	%esi
-	pushl	%edi
-	movl	12(%ebp), %ecx	/* count of half words */
-	movl	16(%ebp), %edx	/* partial checksum */
-	movl	8(%ebp), %esi
-	xorl	%eax, %eax
-	testl	%ecx, %ecx
-	jz	.ip_ocsum_done
-
-	testl	$3, %esi
-	jnz	.ip_csum_notaligned
-.ip_csum_aligned:
-.next_iter:
-	subl	$32, %ecx
-	jl	.less_than_32
-
-	addl	0(%esi), %edx
-.only60:
-	adcl	4(%esi), %eax
-.only56:
-	adcl	8(%esi), %edx
-.only52:
-	adcl	12(%esi), %eax
-.only48:
-	adcl	16(%esi), %edx
-.only44:
-	adcl	20(%esi), %eax
-.only40:
-	adcl	24(%esi), %edx
-.only36:
-	adcl	28(%esi), %eax
-.only32:
-	adcl	32(%esi), %edx
-.only28:
-	adcl	36(%esi), %eax
-.only24:
-	adcl	40(%esi), %edx
-.only20:
-	adcl	44(%esi), %eax
-.only16:
-	adcl	48(%esi), %edx
-.only12:
-	adcl	52(%esi), %eax
-.only8:
-	adcl	56(%esi), %edx
-.only4:
-	adcl	60(%esi), %eax	/* We could be adding -1 and -1 with a carry */
-.only0:
-	adcl	$0, %eax	/* we could be adding -1 in eax with a carry */
-	adcl	$0, %eax
-
-	addl	$64, %esi
-	andl	%ecx, %ecx
-	jnz	.next_iter
-
-.ip_ocsum_done:
-	addl	%eax, %edx
-	adcl	$0, %edx
-	movl	%edx, %eax	/* form a 16 bit checksum by */
-	shrl	$16, %eax	/* adding two halves of 32 bit checksum */
-	addw	%dx, %ax
-	adcw	$0, %ax
-	andl	$0xffff, %eax
-	popl	%edi		/* restore registers */
-	popl	%esi
-	popl	%ebx
-	leave
-	ret
-
-.ip_csum_notaligned:
-	xorl	%edi, %edi
-	movw	(%esi), %di
-	addl	%edi, %edx
-	adcl	$0, %edx
-	addl	$2, %esi
-	decl	%ecx
-	jmp	.ip_csum_aligned
-
-.less_than_32:
-	addl	$32, %ecx
-	testl	$1, %ecx
-	jz	.size_aligned
-	andl	$0xfe, %ecx
-	movzwl	(%esi, %ecx, 2), %edi
-	addl	%edi, %edx
-	adcl	$0, %edx
-.size_aligned:
-	movl	%ecx, %edi
-	shrl	$1, %ecx
-	shl	$1, %edi
-	subl	$64, %edi
-	addl	%edi, %esi
-	movl	$.ip_ocsum_jmptbl, %edi
-	lea	(%edi, %ecx, 4), %edi
-	xorl	%ecx, %ecx
-	clc
-	jmp	*(%edi)
-	SET_SIZE(ip_ocsum)
-
-	.data
-	.align	4
-
-.ip_ocsum_jmptbl:
-	.long	.only0, .only4, .only8, .only12, .only16, .only20
-	.long	.only24, .only28, .only32, .only36, .only40, .only44
-	.long	.only48, .only52, .only56, .only60
-
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * multiply two long numbers and yield a u_longlong_t result, callable from C.
  * Provided to manipulate hrtime_t values.
  */
-#if defined(__lint)
 
-/* result = a * b; */
-
-/* ARGSUSED */
-unsigned long long
-mul32(uint_t a, uint_t b)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(mul32)
 	xorl	%edx, %edx	/* XX64 joe, paranoia? */
 	movl	%edi, %eax
@@ -2713,47 +1109,6 @@
 	ret
 	SET_SIZE(mul32)
 
-#elif defined(__i386)
-
-	ENTRY(mul32)
-	movl	8(%esp), %eax
-	movl	4(%esp), %ecx
-	mull	%ecx
-	ret
-	SET_SIZE(mul32)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(notused)
-#if defined(__lint)
-/* ARGSUSED */
-void
-load_pte64(uint64_t *pte, uint64_t pte_value)
-{}
-#else	/* __lint */
-	.globl load_pte64
-load_pte64:
-	movl	4(%esp), %eax
-	movl	8(%esp), %ecx
-	movl	12(%esp), %edx
-	movl	%edx, 4(%eax)
-	movl	%ecx, (%eax)
-	ret
-#endif	/* __lint */
-#endif	/* notused */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-scan_memory(caddr_t addr, size_t size)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(scan_memory)
 	shrq	$3, %rsi	/* convert %rsi from byte to quadword count */
 	jz	.scanm_done
@@ -2765,38 +1120,7 @@
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(scan_memory)
 
-#elif defined(__i386)
 
-	ENTRY(scan_memory)
-	pushl	%ecx
-	pushl	%esi
-	movl	16(%esp), %ecx	/* move 2nd arg into rep control register */
-	shrl	$2, %ecx	/* convert from byte count to word count */
-	jz	.scanm_done
-	movl	12(%esp), %esi	/* move 1st arg into lodsw control register */
-	.byte	0xf3		/* rep prefix.  lame assembler.  sigh. */
-	lodsl
-.scanm_done:
-	popl	%esi
-	popl	%ecx
-	ret
-	SET_SIZE(scan_memory)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(__lint)
-
-/*ARGSUSED */
-int
-lowbit(ulong_t i)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(lowbit)
 	movl	$-1, %eax
 	bsfq	%rdi, %rdi
@@ -2805,37 +1129,6 @@
 	ret
 	SET_SIZE(lowbit)
 
-#elif defined(__i386)
-
-	ENTRY(lowbit)
-	bsfl	4(%esp), %eax
-	jz	0f
-	incl	%eax
-	ret
-0:
-	xorl	%eax, %eax
-	ret
-	SET_SIZE(lowbit)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-int
-highbit(ulong_t i)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-highbit64(uint64_t i)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(highbit)
 	ALTENTRY(highbit64)
 	movl	$-1, %eax
@@ -2846,70 +1139,8 @@
 	SET_SIZE(highbit64)
 	SET_SIZE(highbit)
 
-#elif defined(__i386)
-
-	ENTRY(highbit)
-	bsrl	4(%esp), %eax
-	jz	0f
-	incl	%eax
-	ret
-0:
-	xorl	%eax, %eax
-	ret
-	SET_SIZE(highbit)
-
-	ENTRY(highbit64)
-	bsrl	8(%esp), %eax
-	jz	highbit
-	addl	$33, %eax
-	ret
-	SET_SIZE(highbit64)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-rdmsr(uint_t r)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-wrmsr(uint_t r, const uint64_t val)
-{}
-
-/*ARGSUSED*/
-uint64_t
-xrdmsr(uint_t r)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-xwrmsr(uint_t r, const uint64_t val)
-{}
-
-void
-invalidate_cache(void)
-{}
-
-/*ARGSUSED*/
-uint64_t
-get_xcr(uint_t r)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-set_xcr(uint_t r, const uint64_t val)
-{}
-
-#else  /* __lint */
-
 #define	XMSR_ACCESS_VAL		$0x9c5a203a
 
-#if defined(__amd64)
-
 	ENTRY(rdmsr)
 	movl	%edi, %ecx
 	rdmsr
@@ -2971,84 +1202,11 @@
 	ret
 	SET_SIZE(set_xcr)
 
-#elif defined(__i386)
-
-	ENTRY(rdmsr)
-	movl	4(%esp), %ecx
-	rdmsr
-	ret
-	SET_SIZE(rdmsr)
-
-	ENTRY(wrmsr)
-	movl	4(%esp), %ecx
-	movl	8(%esp), %eax
-	movl	12(%esp), %edx
-	wrmsr
-	ret
-	SET_SIZE(wrmsr)
-
-	ENTRY(xrdmsr)
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	8(%esp), %ecx
-	pushl	%edi
-	movl	XMSR_ACCESS_VAL, %edi	/* this value is needed to access MSR */
-	rdmsr
-	popl	%edi
-	leave
-	ret
-	SET_SIZE(xrdmsr)
-
-	ENTRY(xwrmsr)
-	pushl	%ebp
-	movl	%esp, %ebp
-	movl	8(%esp), %ecx
-	movl	12(%esp), %eax
-	movl	16(%esp), %edx
-	pushl	%edi
-	movl	XMSR_ACCESS_VAL, %edi	/* this value is needed to access MSR */
-	wrmsr
-	popl	%edi
-	leave
-	ret
-	SET_SIZE(xwrmsr)
-
-	ENTRY(get_xcr)
-	movl	4(%esp), %ecx
-	#xgetbv
-	.byte	0x0f,0x01,0xd0
-	ret
-	SET_SIZE(get_xcr)
-
-	ENTRY(set_xcr)
-	movl	4(%esp), %ecx
-	movl	8(%esp), %eax
-	movl	12(%esp), %edx
-	#xsetbv
-	.byte	0x0f,0x01,0xd1
-	ret
-	SET_SIZE(set_xcr)
-
-#endif	/* __i386 */
-
 	ENTRY(invalidate_cache)
 	wbinvd
 	ret
 	SET_SIZE(invalidate_cache)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-getcregs(struct cregs *crp)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(getcregs)
 #if defined(__xpv)
 	/*
@@ -3111,68 +1269,7 @@
 
 #undef GETMSR
 
-#elif defined(__i386)
 
-	ENTRY_NP(getcregs)
-#if defined(__xpv)
-	/*
-	 * Only a few of the hardware control registers or descriptor tables
-	 * are directly accessible to us, so just zero the structure.
-	 *
-	 * XXPV	Perhaps it would be helpful for the hypervisor to return
-	 *	virtualized versions of these for post-mortem use.
-	 *	(Need to reevaluate - perhaps it already does!)
-	 */
-	movl	4(%esp), %edx
-	pushl	$CREGSZ
-	pushl	%edx
-	call	bzero
-	addl	$8, %esp
-	movl	4(%esp), %edx
-
-	/*
-	 * Dump what limited information we can
-	 */
-	movl	%cr0, %eax
-	movl	%eax, CREG_CR0(%edx)	/* cr0 */
-	movl	%cr2, %eax
-	movl	%eax, CREG_CR2(%edx)	/* cr2 */
-	movl	%cr3, %eax
-	movl	%eax, CREG_CR3(%edx)	/* cr3 */
-	movl	%cr4, %eax
-	movl	%eax, CREG_CR4(%edx)	/* cr4 */
-
-#else	/* __xpv */
-
-	movl	4(%esp), %edx
-	movw	$0, CREG_GDT+6(%edx)
-	movw	$0, CREG_IDT+6(%edx)
-	sgdt	CREG_GDT(%edx)		/* gdt */
-	sidt	CREG_IDT(%edx)		/* idt */
-	sldt	CREG_LDT(%edx)		/* ldt */
-	str	CREG_TASKR(%edx)	/* task */
-	movl	%cr0, %eax
-	movl	%eax, CREG_CR0(%edx)	/* cr0 */
-	movl	%cr2, %eax
-	movl	%eax, CREG_CR2(%edx)	/* cr2 */
-	movl	%cr3, %eax
-	movl	%eax, CREG_CR3(%edx)	/* cr3 */
-	bt	$X86FSET_LARGEPAGE, x86_featureset
-	jnc	.nocr4
-	movl	%cr4, %eax
-	movl	%eax, CREG_CR4(%edx)	/* cr4 */
-	jmp	.skip
-.nocr4:
-	movl	$0, CREG_CR4(%edx)
-.skip:
-#endif
-	ret
-	SET_SIZE(getcregs)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
 /*
  * A panic trigger is a word which is updated atomically and can only be set
  * once.  We atomically store 0xDEFACEDD and load the old value.  If the
@@ -3181,22 +1278,7 @@
  * has its own version of this function to allow it to panic correctly from
  * probe context.
  */
-#if defined(__lint)
 
-/*ARGSUSED*/
-int
-panic_trigger(int *tp)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-dtrace_panic_trigger(int *tp)
-{ return (0); }
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(panic_trigger)
 	xorl	%eax, %eax
 	movl	$0xdefacedd, %edx
@@ -3223,37 +1305,6 @@
 	ret
 	SET_SIZE(dtrace_panic_trigger)
 
-#elif defined(__i386)
-
-	ENTRY_NP(panic_trigger)
-	movl	4(%esp), %edx		/ %edx = address of trigger
-	movl	$0xdefacedd, %eax	/ %eax = 0xdefacedd
-	lock				/ assert lock
-	xchgl %eax, (%edx)		/ exchange %eax and the trigger
-	cmpl	$0, %eax		/ if (%eax == 0x0)
-	je	0f			/   return (1);
-	movl	$0, %eax		/ else
-	ret				/   return (0);
-0:	movl	$1, %eax
-	ret
-	SET_SIZE(panic_trigger)
-
-	ENTRY_NP(dtrace_panic_trigger)
-	movl	4(%esp), %edx		/ %edx = address of trigger
-	movl	$0xdefacedd, %eax	/ %eax = 0xdefacedd
-	lock				/ assert lock
-	xchgl %eax, (%edx)		/ exchange %eax and the trigger
-	cmpl	$0, %eax		/ if (%eax == 0x0)
-	je	0f			/   return (1);
-	movl	$0, %eax		/ else
-	ret				/   return (0);
-0:	movl	$1, %eax
-	ret
-	SET_SIZE(dtrace_panic_trigger)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * The panic() and cmn_err() functions invoke vpanic() as a common entry point
  * into the panic code implemented in panicsys().  vpanic() is responsible
@@ -3268,22 +1319,7 @@
  * sets up the initial stack as vpanic does, calls dtrace_panic_trigger(), and
  * branches back into vpanic().
  */
-#if defined(__lint)
 
-/*ARGSUSED*/
-void
-vpanic(const char *format, va_list alist)
-{}
-
-/*ARGSUSED*/
-void
-dtrace_vpanic(const char *format, va_list alist)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(vpanic)			/* Initial stack layout: */
 
 	pushq	%rbp				/* | %rip |	0x60	*/
@@ -3433,159 +1469,6 @@
 
 	SET_SIZE(dtrace_vpanic)
 
-#elif defined(__i386)
-
-	ENTRY_NP(vpanic)			/ Initial stack layout:
-
-	pushl	%ebp				/ | %eip | 20
-	movl	%esp, %ebp			/ | %ebp | 16
-	pushl	%eax				/ | %eax | 12
-	pushl	%ebx				/ | %ebx |  8
-	pushl	%ecx				/ | %ecx |  4
-	pushl	%edx				/ | %edx |  0
-
-	movl	%esp, %ebx			/ %ebx = current stack pointer
-
-	lea	panic_quiesce, %eax		/ %eax = &panic_quiesce
-	pushl	%eax				/ push &panic_quiesce
-	call	panic_trigger			/ %eax = panic_trigger()
-	addl	$4, %esp			/ reset stack pointer
-
-vpanic_common:
-	cmpl	$0, %eax			/ if (%eax == 0)
-	je	0f				/   goto 0f;
-
-	/*
-	 * If panic_trigger() was successful, we are the first to initiate a
-	 * panic: we now switch to the reserved panic_stack before continuing.
-	 */
-	lea	panic_stack, %esp		/ %esp  = panic_stack
-	addl	$PANICSTKSIZE, %esp		/ %esp += PANICSTKSIZE
-
-0:	subl	$REGSIZE, %esp			/ allocate struct regs
-
-	/*
-	 * Now that we've got everything set up, store the register values as
-	 * they were when we entered vpanic() to the designated location in
-	 * the regs structure we allocated on the stack.
-	 */
-#if !defined(__GNUC_AS__)
-	movw	%gs, %edx
-	movl	%edx, REGOFF_GS(%esp)
-	movw	%fs, %edx
-	movl	%edx, REGOFF_FS(%esp)
-	movw	%es, %edx
-	movl	%edx, REGOFF_ES(%esp)
-	movw	%ds, %edx
-	movl	%edx, REGOFF_DS(%esp)
-#else	/* __GNUC_AS__ */
-	mov	%gs, %edx
-	mov	%edx, REGOFF_GS(%esp)
-	mov	%fs, %edx
-	mov	%edx, REGOFF_FS(%esp)
-	mov	%es, %edx
-	mov	%edx, REGOFF_ES(%esp)
-	mov	%ds, %edx
-	mov	%edx, REGOFF_DS(%esp)
-#endif	/* __GNUC_AS__ */
-	movl	%edi, REGOFF_EDI(%esp)
-	movl	%esi, REGOFF_ESI(%esp)
-	movl	16(%ebx), %ecx
-	movl	%ecx, REGOFF_EBP(%esp)
-	movl	%ebx, %ecx
-	addl	$20, %ecx
-	movl	%ecx, REGOFF_ESP(%esp)
-	movl	8(%ebx), %ecx
-	movl	%ecx, REGOFF_EBX(%esp)
-	movl	0(%ebx), %ecx
-	movl	%ecx, REGOFF_EDX(%esp)
-	movl	4(%ebx), %ecx
-	movl	%ecx, REGOFF_ECX(%esp)
-	movl	12(%ebx), %ecx
-	movl	%ecx, REGOFF_EAX(%esp)
-	movl	$0, REGOFF_TRAPNO(%esp)
-	movl	$0, REGOFF_ERR(%esp)
-	lea	vpanic, %ecx
-	movl	%ecx, REGOFF_EIP(%esp)
-#if !defined(__GNUC_AS__)
-	movw	%cs, %edx
-#else	/* __GNUC_AS__ */
-	mov	%cs, %edx
-#endif	/* __GNUC_AS__ */
-	movl	%edx, REGOFF_CS(%esp)
-	pushfl
-	popl	%ecx
-#if defined(__xpv)
-	/*
-	 * Synthesize the PS_IE bit from the event mask bit
-	 */
-	CURTHREAD(%edx)
-	KPREEMPT_DISABLE(%edx)
-	EVENT_MASK_TO_IE(%edx, %ecx)
-	CURTHREAD(%edx)
-	KPREEMPT_ENABLE_NOKP(%edx)
-#endif
-	movl	%ecx, REGOFF_EFL(%esp)
-	movl	$0, REGOFF_UESP(%esp)
-#if !defined(__GNUC_AS__)
-	movw	%ss, %edx
-#else	/* __GNUC_AS__ */
-	mov	%ss, %edx
-#endif	/* __GNUC_AS__ */
-	movl	%edx, REGOFF_SS(%esp)
-
-	movl	%esp, %ecx			/ %ecx = &regs
-	pushl	%eax				/ push on_panic_stack
-	pushl	%ecx				/ push &regs
-	movl	12(%ebp), %ecx			/ %ecx = alist
-	pushl	%ecx				/ push alist
-	movl	8(%ebp), %ecx			/ %ecx = format
-	pushl	%ecx				/ push format
-	call	panicsys			/ panicsys();
-	addl	$16, %esp			/ pop arguments
-
-	addl	$REGSIZE, %esp
-	popl	%edx
-	popl	%ecx
-	popl	%ebx
-	popl	%eax
-	leave
-	ret
-	SET_SIZE(vpanic)
-
-	ENTRY_NP(dtrace_vpanic)			/ Initial stack layout:
-
-	pushl	%ebp				/ | %eip | 20
-	movl	%esp, %ebp			/ | %ebp | 16
-	pushl	%eax				/ | %eax | 12
-	pushl	%ebx				/ | %ebx |  8
-	pushl	%ecx				/ | %ecx |  4
-	pushl	%edx				/ | %edx |  0
-
-	movl	%esp, %ebx			/ %ebx = current stack pointer
-
-	lea	panic_quiesce, %eax		/ %eax = &panic_quiesce
-	pushl	%eax				/ push &panic_quiesce
-	call	dtrace_panic_trigger		/ %eax = dtrace_panic_trigger()
-	addl	$4, %esp			/ reset stack pointer
-	jmp	vpanic_common			/ jump back to common code
-
-	SET_SIZE(dtrace_vpanic)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-void
-hres_tick(void)
-{}
-
-int64_t timedelta;
-hrtime_t hrtime_base;
-
-#else	/* __lint */
-
 	DGDEF3(timedelta, 8, 8)
 	.long	0, 0
 
@@ -3599,8 +1482,6 @@
 	DGDEF3(adj_shift, 4, 4)
 	.long	ADJ_SHIFT
 
-#if defined(__amd64)
-
 	ENTRY_NP(hres_tick)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -3653,212 +1534,6 @@
 	ret
 	SET_SIZE(hres_tick)
 
-#elif defined(__i386)
-
-	ENTRY_NP(hres_tick)
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	%esi
-	pushl	%ebx
-
-	/*
-	 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously,
-	 * hres_last_tick can only be modified while holding CLOCK_LOCK).
-	 * At worst, performing this now instead of under CLOCK_LOCK may
-	 * introduce some jitter in pc_gethrestime().
-	 */
-	call	*gethrtimef
-	movl	%eax, %ebx
-	movl	%edx, %esi
-
-	movl	$hres_lock, %eax
-	movl	$-1, %edx
-.CL1:
-	xchgb	%dl, (%eax)
-	testb	%dl, %dl
-	jz	.CL3			/ got it
-.CL2:
-	cmpb	$0, (%eax)		/ possible to get lock?
-	pause
-	jne	.CL2
-	jmp	.CL1			/ yes, try again
-.CL3:
-	/*
-	 * compute the interval since last time hres_tick was called
-	 * and adjust hrtime_base and hrestime accordingly
-	 * hrtime_base is an 8 byte value (in nsec), hrestime is
-	 * timestruc_t (sec, nsec)
-	 */
-
-	lea	hres_last_tick, %eax
-
-	movl	%ebx, %edx
-	movl	%esi, %ecx
-
-	subl	(%eax), %edx
-	sbbl	4(%eax), %ecx
-
-	addl	%edx, hrtime_base	/ add interval to hrtime_base
-	adcl	%ecx, hrtime_base+4
-
-	addl	%edx, hrestime+4	/ add interval to hrestime.tv_nsec
-
-	/
-	/ Now that we have CLOCK_LOCK, we can update hres_last_tick.
-	/
-	movl	%ebx, (%eax)
-	movl	%esi,  4(%eax)
-
-	/ get hrestime at this moment. used as base for pc_gethrestime
-	/
-	/ Apply adjustment, if any
-	/
-	/ #define HRES_ADJ	(NSEC_PER_CLOCK_TICK >> ADJ_SHIFT)
-	/ (max_hres_adj)
-	/
-	/ void
-	/ adj_hrestime()
-	/ {
-	/	long long adj;
-	/
-	/	if (hrestime_adj == 0)
-	/		adj = 0;
-	/	else if (hrestime_adj > 0) {
-	/		if (hrestime_adj < HRES_ADJ)
-	/			adj = hrestime_adj;
-	/		else
-	/			adj = HRES_ADJ;
-	/	}
-	/	else {
-	/		if (hrestime_adj < -(HRES_ADJ))
-	/			adj = -(HRES_ADJ);
-	/		else
-	/			adj = hrestime_adj;
-	/	}
-	/
-	/	timedelta -= adj;
-	/	hrestime_adj = timedelta;
-	/	hrestime.tv_nsec += adj;
-	/
-	/	while (hrestime.tv_nsec >= NANOSEC) {
-	/		one_sec++;
-	/		hrestime.tv_sec++;
-	/		hrestime.tv_nsec -= NANOSEC;
-	/	}
-	/ }
-__adj_hrestime:
-	movl	hrestime_adj, %esi	/ if (hrestime_adj == 0)
-	movl	hrestime_adj+4, %edx
-	andl	%esi, %esi
-	jne	.CL4			/ no
-	andl	%edx, %edx
-	jne	.CL4			/ no
-	subl	%ecx, %ecx		/ yes, adj = 0;
-	subl	%edx, %edx
-	jmp	.CL5
-.CL4:
-	subl	%ecx, %ecx
-	subl	%eax, %eax
-	subl	%esi, %ecx
-	sbbl	%edx, %eax
-	andl	%eax, %eax		/ if (hrestime_adj > 0)
-	jge	.CL6
-
-	/ In the following comments, HRES_ADJ is used, while in the code
-	/ max_hres_adj is used.
-	/
-	/ The test for "hrestime_adj < HRES_ADJ" is complicated because
-	/ hrestime_adj is 64-bits, while HRES_ADJ is 32-bits.  We rely
-	/ on the logical equivalence of:
-	/
-	/	!(hrestime_adj < HRES_ADJ)
-	/
-	/ and the two step sequence:
-	/
-	/	(HRES_ADJ - lsw(hrestime_adj)) generates a Borrow/Carry
-	/
-	/ which computes whether or not the least significant 32-bits
-	/ of hrestime_adj is greater than HRES_ADJ, followed by:
-	/
-	/	Previous Borrow/Carry + -1 + msw(hrestime_adj) generates a Carry
-	/
-	/ which generates a carry whenever step 1 is true or the most
-	/ significant long of the longlong hrestime_adj is non-zero.
-
-	movl	max_hres_adj, %ecx	/ hrestime_adj is positive
-	subl	%esi, %ecx
-	movl	%edx, %eax
-	adcl	$-1, %eax
-	jnc	.CL7
-	movl	max_hres_adj, %ecx	/ adj = HRES_ADJ;
-	subl	%edx, %edx
-	jmp	.CL5
-
-	/ The following computation is similar to the one above.
-	/
-	/ The test for "hrestime_adj < -(HRES_ADJ)" is complicated because
-	/ hrestime_adj is 64-bits, while HRES_ADJ is 32-bits.  We rely
-	/ on the logical equivalence of:
-	/
-	/	(hrestime_adj > -HRES_ADJ)
-	/
-	/ and the two step sequence:
-	/
-	/	(HRES_ADJ + lsw(hrestime_adj)) generates a Carry
-	/
-	/ which means the least significant 32-bits of hrestime_adj is
-	/ greater than -HRES_ADJ, followed by:
-	/
-	/	Previous Carry + 0 + msw(hrestime_adj) generates a Carry
-	/
-	/ which generates a carry only when step 1 is true and the most
-	/ significant long of the longlong hrestime_adj is -1.
-
-.CL6:					/ hrestime_adj is negative
-	movl	%esi, %ecx
-	addl	max_hres_adj, %ecx
-	movl	%edx, %eax
-	adcl	$0, %eax
-	jc	.CL7
-	xor	%ecx, %ecx
-	subl	max_hres_adj, %ecx	/ adj = -(HRES_ADJ);
-	movl	$-1, %edx
-	jmp	.CL5
-.CL7:
-	movl	%esi, %ecx		/ adj = hrestime_adj;
-.CL5:
-	movl	timedelta, %esi
-	subl	%ecx, %esi
-	movl	timedelta+4, %eax
-	sbbl	%edx, %eax
-	movl	%esi, timedelta
-	movl	%eax, timedelta+4	/ timedelta -= adj;
-	movl	%esi, hrestime_adj
-	movl	%eax, hrestime_adj+4	/ hrestime_adj = timedelta;
-	addl	hrestime+4, %ecx
-
-	movl	%ecx, %eax		/ eax = tv_nsec
-1:
-	cmpl	$NANOSEC, %eax		/ if ((unsigned long)tv_nsec >= NANOSEC)
-	jb	.CL8			/ no
-	incl	one_sec			/ yes,  one_sec++;
-	incl	hrestime		/ hrestime.tv_sec++;
-	addl	$-NANOSEC, %eax		/ tv_nsec -= NANOSEC
-	jmp	1b			/ check for more seconds
-
-.CL8:
-	movl	%eax, hrestime+4	/ store final into hrestime.tv_nsec
-	incl	hres_lock		/ release the hres_lock
-
-	popl	%ebx
-	popl	%esi
-	leave
-	ret
-	SET_SIZE(hres_tick)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
 /*
  * void prefetch_smap_w(void *)
  *
@@ -3866,52 +1541,21 @@
  * Not implemented for ia32.  Stub for compatibility.
  */
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-void prefetch_smap_w(void *smp)
-{}
-
-#else	/* __lint */
-
 	ENTRY(prefetch_smap_w)
 	rep;	ret	/* use 2 byte return instruction when branch target */
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(prefetch_smap_w)
 
-#endif	/* __lint */
-
 /*
  * prefetch_page_r(page_t *)
  * issue prefetch instructions for a page_t
  */
-#if defined(__lint)
 
-/*ARGSUSED*/
-void
-prefetch_page_r(void *pp)
-{}
-
-#else	/* __lint */
-
 	ENTRY(prefetch_page_r)
 	rep;	ret	/* use 2 byte return instruction when branch target */
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(prefetch_page_r)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-int
-bcmp(const void *s1, const void *s2, size_t count)
-{ return (0); }
-
-#else   /* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(bcmp)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -3936,100 +1580,12 @@
 	ret
 	SET_SIZE(bcmp)
 
-#elif defined(__i386)
-
-#define	ARG_S1		8
-#define	ARG_S2		12
-#define	ARG_LENGTH	16
-
-	ENTRY(bcmp)
-	pushl	%ebp
-	movl	%esp, %ebp	/ create new stack frame
 #ifdef DEBUG
-	cmpl	$0, ARG_LENGTH(%ebp)
-	je	1f
-	movl    postbootkernelbase, %eax
-	cmpl    %eax, ARG_S1(%ebp)
-	jb	0f
-	cmpl    %eax, ARG_S2(%ebp)
-	jnb	1f
-0:	pushl   $.bcmp_panic_msg
-	call    panic
-1:
-#endif	/* DEBUG */
-
-	pushl	%edi		/ save register variable
-	movl	ARG_S1(%ebp), %eax	/ %eax = address of string 1
-	movl	ARG_S2(%ebp), %ecx	/ %ecx = address of string 2
-	cmpl	%eax, %ecx	/ if the same string
-	je	.equal		/ goto .equal
-	movl	ARG_LENGTH(%ebp), %edi	/ %edi = length in bytes
-	cmpl	$4, %edi	/ if %edi < 4
-	jb	.byte_check	/ goto .byte_check
-	.align	4
-.word_loop:
-	movl	(%ecx), %edx	/ move 1 word from (%ecx) to %edx
-	leal	-4(%edi), %edi	/ %edi -= 4
-	cmpl	(%eax), %edx	/ compare 1 word from (%eax) with %edx
-	jne	.word_not_equal	/ if not equal, goto .word_not_equal
-	leal	4(%ecx), %ecx	/ %ecx += 4 (next word)
-	leal	4(%eax), %eax	/ %eax += 4 (next word)
-	cmpl	$4, %edi	/ if %edi >= 4
-	jae	.word_loop	/ goto .word_loop
-.byte_check:
-	cmpl	$0, %edi	/ if %edi == 0
-	je	.equal		/ goto .equal
-	jmp	.byte_loop	/ goto .byte_loop (checks in bytes)
-.word_not_equal:
-	leal	4(%edi), %edi	/ %edi += 4 (post-decremented)
-	.align	4
-.byte_loop:
-	movb	(%ecx),	%dl	/ move 1 byte from (%ecx) to %dl
-	cmpb	%dl, (%eax)	/ compare %dl with 1 byte from (%eax)
-	jne	.not_equal	/ if not equal, goto .not_equal
-	incl	%ecx		/ %ecx++ (next byte)
-	incl	%eax		/ %eax++ (next byte)
-	decl	%edi		/ %edi--
-	jnz	.byte_loop	/ if not zero, goto .byte_loop
-.equal:
-	xorl	%eax, %eax	/ %eax = 0
-	popl	%edi		/ restore register variable
-	leave			/ restore old stack frame
-	ret			/ return (NULL)
-	.align	4
-.not_equal:
-	movl	$1, %eax	/ return 1
-	popl	%edi		/ restore register variable
-	leave			/ restore old stack frame
-	ret			/ return (NULL)
-	SET_SIZE(bcmp)
-
-#endif	/* __i386 */
-
-#ifdef DEBUG
 	.text
 .bcmp_panic_msg:
 	.string "bcmp: arguments below kernelbase"
 #endif	/* DEBUG */
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-uint_t
-bsrw_insn(uint16_t mask)
-{
-	uint_t index = sizeof (mask) * NBBY - 1;
-
-	while ((mask & (1 << index)) == 0)
-		index--;
-	return (index);
-}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(bsrw_insn)
 	xorl	%eax, %eax
 	bsrw	%di, %ax
@@ -4036,55 +1592,6 @@
 	ret
 	SET_SIZE(bsrw_insn)
 
-#elif defined(__i386)
-
-	ENTRY_NP(bsrw_insn)
-	movw	4(%esp), %cx
-	xorl	%eax, %eax
-	bsrw	%cx, %ax
-	ret
-	SET_SIZE(bsrw_insn)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-uint_t
-atomic_btr32(uint32_t *pending, uint_t pil)
-{
-	return (*pending &= ~(1 << pil));
-}
-
-#else	/* __lint */
-
-#if defined(__i386)
-
-	ENTRY_NP(atomic_btr32)
-	movl	4(%esp), %ecx
-	movl	8(%esp), %edx
-	xorl	%eax, %eax
-	lock
-	btrl	%edx, (%ecx)
-	setc	%al
-	ret
-	SET_SIZE(atomic_btr32)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-switch_sp_and_call(void *newsp, void (*func)(uint_t, uint_t), uint_t arg1,
-	    uint_t arg2)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(switch_sp_and_call)
 	pushq	%rbp
 	movq	%rsp, %rbp		/* set up stack frame */
@@ -4097,33 +1604,6 @@
 	ret
 	SET_SIZE(switch_sp_and_call)
 
-#elif defined(__i386)
-
-	ENTRY_NP(switch_sp_and_call)
-	pushl	%ebp
-	mov	%esp, %ebp		/* set up stack frame */
-	movl	8(%ebp), %esp		/* switch stack pointer */
-	pushl	20(%ebp)		/* push func arg 2 */
-	pushl	16(%ebp)		/* push func arg 1 */
-	call	*12(%ebp)		/* call function */
-	addl	$8, %esp		/* pop arguments */
-	leave				/* restore stack */
-	ret
-	SET_SIZE(switch_sp_and_call)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-void
-kmdb_enter(void)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY_NP(kmdb_enter)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -4145,60 +1625,11 @@
 	ret
 	SET_SIZE(kmdb_enter)
 
-#elif defined(__i386)
-
-	ENTRY_NP(kmdb_enter)
-	pushl	%ebp
-	movl	%esp, %ebp
-
-	/*
-	 * Save flags, do a 'cli' then return the saved flags
-	 */
-	call	intr_clear
-
-	int	$T_DBGENTR
-
-	/*
-	 * Restore the saved flags
-	 */
-	pushl	%eax
-	call	intr_restore
-	addl	$4, %esp
-
-	leave
-	ret
-	SET_SIZE(kmdb_enter)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-void
-return_instr(void)
-{}
-
-#else	/* __lint */
-
 	ENTRY_NP(return_instr)
 	rep;	ret	/* use 2 byte instruction when branch target */
 			/* AMD Software Optimization Guide - Section 6.2 */
 	SET_SIZE(return_instr)
 
-#endif	/* __lint */
-
-#if defined(__lint)
-
-ulong_t
-getflags(void)
-{
-	return (0);
-}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(getflags)
 	pushfq
 	popq	%rax
@@ -4219,42 +1650,6 @@
 	ret
 	SET_SIZE(getflags)
 
-#elif defined(__i386)
-
-	ENTRY(getflags)
-	pushfl
-	popl	%eax
-#if defined(__xpv)
-	CURTHREAD(%ecx)
-	KPREEMPT_DISABLE(%ecx)
-	/*
-	 * Synthesize the PS_IE bit from the event mask bit
-	 */
-	CURVCPU(%edx)
-	andl    $_BITNOT(PS_IE), %eax
-	XEN_TEST_UPCALL_MASK(%edx)
-	jnz	1f
-	orl	$PS_IE, %eax
-1:
-	KPREEMPT_ENABLE_NOKP(%ecx)
-#endif
-	ret
-	SET_SIZE(getflags)
-
-#endif	/* __i386 */
-
-#endif	/* __lint */
-
-#if defined(__lint)
-
-ftrace_icookie_t
-ftrace_interrupt_disable(void)
-{ return (0); }
-
-#else   /* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(ftrace_interrupt_disable)
 	pushfq
 	popq	%rax
@@ -4262,29 +1657,6 @@
 	ret
 	SET_SIZE(ftrace_interrupt_disable)
 
-#elif defined(__i386)
-
-	ENTRY(ftrace_interrupt_disable)
-	pushfl
-	popl	%eax
-	CLI(%edx)
-	ret
-	SET_SIZE(ftrace_interrupt_disable)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-ftrace_interrupt_enable(ftrace_icookie_t cookie)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(ftrace_interrupt_enable)
 	pushq	%rdi
 	popfq
@@ -4291,64 +1663,16 @@
 	ret
 	SET_SIZE(ftrace_interrupt_enable)
 
-#elif defined(__i386)
-
-	ENTRY(ftrace_interrupt_enable)
-	movl	4(%esp), %eax
-	pushl	%eax
-	popfl
-	ret
-	SET_SIZE(ftrace_interrupt_enable)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined (__lint)
-
-/*ARGSUSED*/
-void
-clflush_insn(caddr_t addr)
-{}
-
-#else /* __lint */
-
-#if defined (__amd64)
 	ENTRY(clflush_insn)
 	clflush (%rdi)
 	ret
 	SET_SIZE(clflush_insn)
-#elif defined (__i386)
-	ENTRY(clflush_insn)
-	movl	4(%esp), %eax
-	clflush (%eax)
-	ret
-	SET_SIZE(clflush_insn)
 
-#endif /* __i386 */
-#endif /* __lint */
-
-#if defined (__lint)
-/*ARGSUSED*/
-void
-mfence_insn(void)
-{}
-
-#else /* __lint */
-
-#if defined (__amd64)
 	ENTRY(mfence_insn)
 	mfence
 	ret
 	SET_SIZE(mfence_insn)
-#elif defined (__i386)
-	ENTRY(mfence_insn)
-	mfence
-	ret
-	SET_SIZE(mfence_insn)
 
-#endif /* __i386 */
-#endif /* __lint */
-
 /*
  * VMware implements an I/O port that programs can query to detect if software
  * is running in a VMware hypervisor. This hypervisor port behaves differently
@@ -4358,16 +1682,6 @@
  * References: http://kb.vmware.com/kb/1009458
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-vmware_port(int cmd, uint32_t *regs) { return; }
-
-#else
-
-#if defined(__amd64)
-
 	ENTRY(vmware_port)
 	pushq	%rbx
 	movl	$VMWARE_HVMAGIC, %eax
@@ -4383,25 +1697,3 @@
 	ret
 	SET_SIZE(vmware_port)
 
-#elif defined(__i386)
-
-	ENTRY(vmware_port)
-	pushl	%ebx
-	pushl	%esi
-	movl	$VMWARE_HVMAGIC, %eax
-	movl	$0xffffffff, %ebx
-	movl	12(%esp), %ecx
-	movl	$VMWARE_HVPORT, %edx
-	inl	(%dx)
-	movl	16(%esp), %esi
-	movl	%eax, (%esi)
-	movl	%ebx, 4(%esi)
-	movl	%ecx, 8(%esi)
-	movl	%edx, 12(%esi)
-	popl	%esi
-	popl	%ebx
-	ret
-	SET_SIZE(vmware_port)
-
-#endif /* __i386 */
-#endif /* __lint */
--- old/usr/src/uts/intel/ia32/ml/ia32.il	Thu Nov 14 19:00:26 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,200 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-/
-/ Inline functions for i386 kernels.
-/	Shared between all x86 platform variants.
-/
-
-/
-/ return current thread pointer
-/
-/ NOTE: the "0x10" should be replaced by the computed value of the
-/	offset of "cpu_thread" from the beginning of the struct cpu.
-/	Including "assym.h" does not work, however, since that stuff
-/	is PSM-specific and is only visible to the 'unix' build anyway.
-/	Same with current cpu pointer, where "0xc" should be replaced
-/	by the computed value of the offset of "cpu_self".
-/	Ugh -- what a disaster.
-/
-	.inline	threadp,0
-	movl	%gs:0x10, %eax
-	.end
-
-/
-/ return current cpu pointer
-/
-	.inline	curcpup,0
-	movl	%gs:0xc, %eax
-	.end
-
-/
-/ return caller
-/
-	.inline caller,0
-	movl	4(%ebp), %eax
-	.end
-
-/
-/ convert ipl to spl.  This is the identity function for i86
-/
-	.inline	ipltospl,0
-	movl	(%esp), %eax
-	.end
-
-/
-/ Networking byte order functions (too bad, Intel has the wrong byte order)
-/
-	.inline	htonll,4
-	movl	(%esp), %edx
-	movl	4(%esp), %eax
-	bswap	%edx
-	bswap	%eax
-	.end
-
-	.inline	ntohll,4
-	movl	(%esp), %edx
-	movl	4(%esp), %eax
-	bswap	%edx
-	bswap	%eax
-	.end
-
-	.inline	htonl,4
-	movl	(%esp), %eax
-	bswap	%eax
-	.end
-
-	.inline	ntohl,4
-	movl	(%esp), %eax
-	bswap	%eax
-	.end
-
-	.inline	htons,4
-	movl	(%esp), %eax
-	bswap	%eax
-	shrl	$16, %eax
-	.end
-
-	.inline	ntohs,4
-	movl	(%esp), %eax
-	bswap	%eax
-	shrl	$16, %eax
-	.end
-
-/*
- * multiply two long numbers and yield a u_longlong_t result
- * Provided to manipulate hrtime_t values.
- */
-	.inline mul32, 8
-	movl	4(%esp), %eax
-	movl	(%esp), %ecx
-	mull	%ecx
-	.end
-
-/*
- * Unlock hres_lock and increment the count value. (See clock.h)
- */
-	.inline unlock_hres_lock, 0
-	lock
-	incl	hres_lock
-	.end
-
-	.inline	atomic_orb,8
-	movl	(%esp), %eax
-	movl    4(%esp), %edx
-	lock
-	orb	%dl,(%eax)
-	.end
-
-	.inline	atomic_andb,8
-	movl	(%esp), %eax
-	movl    4(%esp), %edx
-	lock
-	andb	%dl,(%eax)
-	.end
-
-/*
- * atomic inc/dec operations.
- *	void atomic_inc16(uint16_t *addr) { ++*addr; }
- *	void atomic_dec16(uint16_t *addr) { --*addr; }
- */
-	.inline	atomic_inc16,4
-	movl	(%esp), %eax
-	lock
-	incw	(%eax)
-	.end
-
-	.inline	atomic_dec16,4
-	movl	(%esp), %eax
-	lock
-	decw	(%eax)
-	.end
-
-/*
- * Call the pause instruction.  To the Pentium 4 Xeon processor, it acts as
- * a hint that the code sequence is a busy spin-wait loop.  Without a pause
- * instruction in these loops, the P4 Xeon processor may suffer a severe
- * penalty when exiting the loop because the processor detects a possible
- * memory violation.  Inserting the pause instruction significantly reduces
- * the likelihood of a memory order violation, improving performance.
- * The pause instruction is a NOP on all other IA-32 processors.
- */
-	.inline ht_pause, 0
-	rep			/ our compiler doesn't support "pause" yet,
-	nop			/ so we're using "F3 90" opcode directly
-	.end
-
-/*
- * prefetch 64 bytes
- *
- * prefetch is an SSE extension which is not supported on older 32-bit processors
- * so define this as a no-op for now
- */
-
- 	.inline	prefetch_read_many,4
-/	movl		(%esp), %eax
-/	prefetcht0	(%eax)
-/	prefetcht0	32(%eax)
-	.end
-
- 	.inline	prefetch_read_once,4
-/	movl		(%esp), %eax
-/	prefetchnta	(%eax)
-/	prefetchnta	32(%eax)
-	.end
-
- 	.inline	prefetch_write_many,4
-/	movl		(%esp), %eax
-/	prefetcht0	(%eax)
-/	prefetcht0	32(%eax)
-	.end
-
- 	.inline	prefetch_write_once,4
-/	movl		(%esp), %eax
-/	prefetcht0	(%eax)
-/	prefetcht0	32(%eax)
-	.end
-
--- old/usr/src/uts/intel/ia32/ml/lock_prim.s	Thu Nov 14 19:00:26 2019
+++ new/usr/src/uts/intel/ia32/ml/lock_prim.s	Thu Nov 14 19:00:26 2019
@@ -23,16 +23,11 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
+/*
+ * Copyright 2019 Joyent, Inc.
+ */
 
-#if defined(lint) || defined(__lint)
-#include <sys/types.h>
-#include <sys/thread.h>
-#include <sys/cpuvar.h>
-#include <vm/page.h>
-#else	/* __lint */
 #include "assym.h"
-#endif	/* __lint */
 
 #include <sys/mutex_impl.h>
 #include <sys/asm_linkage.h>
@@ -49,28 +44,8 @@
  * ulock_try() is for a lock in the user address space.
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-int
-lock_try(lock_t *lp)
-{ return (0); }
-
-/* ARGSUSED */
-int
-lock_spin_try(lock_t *lp)
-{ return (0); }
-
-/* ARGSUSED */
-int
-ulock_try(lock_t *lp)
-{ return (0); }
-
-#else	/* __lint */
 	.globl	kernelbase
 
-#if defined(__amd64)
-
 	ENTRY(lock_try)
 	movb	$-1, %dl
 	movzbq	%dl, %rax
@@ -118,58 +93,7 @@
 	ret
 	SET_SIZE(ulock_try)
 
-#else
-
-	ENTRY(lock_try)
-	movl	$1,%edx
-	movl	4(%esp),%ecx		/* ecx = lock addr */
-	xorl	%eax,%eax
-	xchgb	%dl, (%ecx)		/* using dl will avoid partial */
-	testb	%dl,%dl			/* stalls on P6 ? */
-	setz	%al
-.lock_try_lockstat_patch_point:
-	ret
-	movl	%gs:CPU_THREAD, %edx	/* edx = thread addr */
-	testl	%eax, %eax
-	jz	0f
-	movl	$LS_LOCK_TRY_ACQUIRE, %eax
-	jmp	lockstat_wrapper
-0:
-	ret
-	SET_SIZE(lock_try)
-
-	ENTRY(lock_spin_try)
-	movl	$-1,%edx
-	movl	4(%esp),%ecx		/* ecx = lock addr */
-	xorl	%eax,%eax
-	xchgb	%dl, (%ecx)		/* using dl will avoid partial */
-	testb	%dl,%dl			/* stalls on P6 ? */
-	setz	%al
-	ret
-	SET_SIZE(lock_spin_try)
-
-	ENTRY(ulock_try)
 #ifdef DEBUG
-	movl	kernelbase, %eax
-	cmpl	%eax, 4(%esp)		/* test uaddr < kernelbase */
-	jb	ulock_pass		/* uaddr < kernelbase, proceed */
-
-	pushl	$.ulock_panic_msg
-	call	panic
-
-#endif /* DEBUG */
-
-ulock_pass:
-	movl	$1,%eax
-	movl	4(%esp),%ecx
-	xchgb	%al, (%ecx)
-	xorb	$1, %al
-	ret
-	SET_SIZE(ulock_try)
-
-#endif	/* !__amd64 */
-
-#ifdef DEBUG
 	.data
 .ulock_panic_msg:
 	.string "ulock_try: Argument is above kernelbase"
@@ -176,29 +100,11 @@
 	.text
 #endif	/* DEBUG */
 
-#endif	/* __lint */
-
 /*
  * lock_clear(lp)
  *	- unlock lock without changing interrupt priority level.
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-lock_clear(lock_t *lp)
-{}
-
-/* ARGSUSED */
-void
-ulock_clear(lock_t *lp)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(lock_clear)
 	movb	$0, (%rdi)
 .lock_clear_lockstat_patch_point:
@@ -227,39 +133,7 @@
 	ret
 	SET_SIZE(ulock_clear)
 
-#else
-
-	ENTRY(lock_clear)
-	movl	4(%esp), %eax
-	movb	$0, (%eax)
-.lock_clear_lockstat_patch_point:
-	ret
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread addr */
-	movl	%eax, %ecx			/* ecx = lock pointer */
-	movl	$LS_LOCK_CLEAR_RELEASE, %eax
-	jmp	lockstat_wrapper
-	SET_SIZE(lock_clear)
-
-	ENTRY(ulock_clear)
 #ifdef DEBUG
-	movl	kernelbase, %ecx
-	cmpl	%ecx, 4(%esp)		/* test uaddr < kernelbase */
-	jb	ulock_clr		/* uaddr < kernelbase, proceed */
-
-	pushl	$.ulock_clear_msg
-	call	panic
-#endif
-
-ulock_clr:
-	movl	4(%esp),%eax
-	xorl	%ecx,%ecx
-	movb	%cl, (%eax)
-	ret
-	SET_SIZE(ulock_clear)
-
-#endif	/* !__amd64 */
-
-#ifdef DEBUG
 	.data
 .ulock_clear_msg:
 	.string "ulock_clear: Argument is above kernelbase"
@@ -267,24 +141,11 @@
 #endif	/* DEBUG */
 
 
-#endif	/* __lint */
-
 /*
  * lock_set_spl(lock_t *lp, int new_pil, u_short *old_pil)
  * Drops lp, sets pil to new_pil, stores old pil in *old_pil.
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-lock_set_spl(lock_t *lp, int new_pil, u_short *old_pil)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(lock_set_spl)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -316,88 +177,21 @@
 	jmp	lock_set_spl_spin
 	SET_SIZE(lock_set_spl)
 
-#else
-
-	ENTRY(lock_set_spl)
-	movl	8(%esp), %eax		/* get priority level */
-	pushl	%eax
-	call	splr			/* raise priority level */
-	movl 	8(%esp), %ecx		/* ecx = lock addr */
-	movl	$-1, %edx
-	addl	$4, %esp
-	xchgb	%dl, (%ecx)		/* try to set lock */
-	testb	%dl, %dl		/* did we get the lock? ... */
-	movl	12(%esp), %edx		/* edx = olp pil addr (ZF unaffected) */
-	jnz	.lss_miss		/* ... no, go to C for the hard case */
-	movw	%ax, (%edx)		/* store old pil */
-.lock_set_spl_lockstat_patch_point:
-	ret
-	movl	%gs:CPU_THREAD, %edx	/* edx = thread addr*/
-	movl	$LS_LOCK_SET_SPL_ACQUIRE, %eax
-	jmp	lockstat_wrapper
-.lss_miss:
-	pushl	%eax			/* original pil */
-	pushl	%edx			/* old_pil addr */
-	pushl	16(%esp)		/* new_pil */
-	pushl	%ecx			/* lock addr */
-	call	lock_set_spl_spin
-	addl	$16, %esp
-	ret
-	SET_SIZE(lock_set_spl)
-
-#endif	/* !__amd64 */
-
-#endif	/* __lint */
-
 /*
  * void
  * lock_init(lp)
  */
 
-#if defined(__lint)
-
-/* ARGSUSED */
-void
-lock_init(lock_t *lp)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(lock_init)
 	movb	$0, (%rdi)
 	ret
 	SET_SIZE(lock_init)
 
-#else
-
-	ENTRY(lock_init)
-	movl	4(%esp), %eax
-	movb	$0, (%eax)
-	ret
-	SET_SIZE(lock_init)
-
-#endif	/* !__amd64 */
-
-#endif	/* __lint */
-
 /*
  * void
  * lock_set(lp)
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-lock_set(lock_t *lp)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(lock_set)
 	movb	$-1, %dl
 	xchgb	%dl, (%rdi)		/* try to set lock */
@@ -411,40 +205,10 @@
 	jmp	lockstat_wrapper
 	SET_SIZE(lock_set)
 
-#else
-
-	ENTRY(lock_set)
-	movl	4(%esp), %ecx		/* ecx = lock addr */
-	movl	$-1, %edx
-	xchgb	%dl, (%ecx)		/* try to set lock */
-	testb	%dl, %dl		/* did we get it? */
-	jnz	lock_set_spin		/* no, go to C for the hard case */
-.lock_set_lockstat_patch_point:
-	ret
-	movl	%gs:CPU_THREAD, %edx	/* edx = thread addr */
-	movl	$LS_LOCK_SET_ACQUIRE, %eax
-	jmp	lockstat_wrapper
-	SET_SIZE(lock_set)
-
-#endif	/* !__amd64 */
-
-#endif	/* __lint */
-
 /*
  * lock_clear_splx(lp, s)
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-lock_clear_splx(lock_t *lp, int s)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(lock_clear_splx)
 	movb	$0, (%rdi)		/* clear lock */
 .lock_clear_splx_lockstat_patch_point:
@@ -466,32 +230,6 @@
 	jmp	lockstat_wrapper
 	SET_SIZE(lock_clear_splx)
 
-#else
-
-	ENTRY(lock_clear_splx)
-	movl	4(%esp), %eax		/* eax = lock addr */
-	movb	$0, (%eax)		/* clear lock */
-.lock_clear_splx_lockstat_patch_point:
-	jmp	0f
-0:
-	movl	8(%esp), %edx		/* edx = desired pil */
-	movl	%edx, 4(%esp)		/* set spl arg up for splx */
-	jmp	splx			/* let splx do it's thing */
-.lock_clear_splx_lockstat:
-	movl	8(%esp), %edx		/* edx = desired pil */
-	pushl	%ebp			/* set up stack frame */
-	movl	%esp, %ebp
-	pushl	%edx
-	call	splx
-	leave				/* unwind stack */
-	movl	4(%esp), %ecx		/* ecx = lock pointer */
-	movl	%gs:CPU_THREAD, %edx	/* edx = thread addr */
-	movl	$LS_LOCK_CLEAR_SPLX_RELEASE, %eax
-	jmp	lockstat_wrapper
-	SET_SIZE(lock_clear_splx)
-
-#endif	/* !__amd64 */
-
 #if defined(__GNUC_AS__)
 #define	LOCK_CLEAR_SPLX_LOCKSTAT_PATCH_VAL	\
 	(.lock_clear_splx_lockstat - .lock_clear_splx_lockstat_patch_point - 2)
@@ -506,8 +244,6 @@
 	[.lock_clear_splx_lockstat_patch_point + 1]
 #endif
 
-#endif	/* __lint */
-
 /*
  * mutex_enter() and mutex_exit().
  *
@@ -531,32 +267,7 @@
  * Note that we don't need to test lockstat_event_mask here -- we won't
  * patch this code in unless we're gathering ADAPTIVE_HOLD lockstats.
  */
-#if defined(lint) || defined(__lint)
 
-/* ARGSUSED */
-void
-mutex_enter(kmutex_t *lp)
-{}
-
-/* ARGSUSED */
-int
-mutex_tryenter(kmutex_t *lp)
-{ return (0); }
-
-/* ARGSUSED */
-int
-mutex_adaptive_tryenter(mutex_impl_t *lp)
-{ return (0); }
-
-/* ARGSUSED */
-void
-mutex_exit(kmutex_t *lp)
-{}
-
-#else
-
-#if defined(__amd64)
-
 	ENTRY_NP(mutex_enter)
 	movq	%gs:CPU_THREAD, %rdx		/* rdx = thread ptr */
 	xorl	%eax, %eax			/* rax = 0 (unheld adaptive) */
@@ -718,181 +429,6 @@
 	.quad	.mutex_exit_critical_end - mutex_exit_critical_start
 	SET_SIZE(mutex_exit_critical_size)
 
-#else
-
-	ENTRY_NP(mutex_enter)
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread ptr */
-	movl	4(%esp), %ecx			/* ecx = lock ptr */
-	xorl	%eax, %eax			/* eax = 0 (unheld adaptive) */
-	lock
-	cmpxchgl %edx, (%ecx)
-	jnz	mutex_vector_enter
-#if defined(OPTERON_WORKAROUND_6323525)
-.mutex_enter_lockstat_patch_point:
-.mutex_enter_6323525_patch_point:
-	ret					/* nop space for lfence */
-	nop
-	nop
-.mutex_enter_lockstat_6323525_patch_point:	/* new patch point if lfence */
-	nop
-#else	/* OPTERON_WORKAROUND_6323525 */
-.mutex_enter_lockstat_patch_point:
-	ret
-#endif	/* OPTERON_WORKAROUND_6323525 */
-	movl	$LS_MUTEX_ENTER_ACQUIRE, %eax
-	ALTENTRY(lockstat_wrapper)	/* expects edx=thread, ecx=lock, */
-					/*   eax=lockstat event */
-	pushl	%ebp				/* buy a frame */
-	movl	%esp, %ebp
-	incb	T_LOCKSTAT(%edx)		/* curthread->t_lockstat++ */
-	pushl	%edx				/* save thread pointer	 */
-	movl	$lockstat_probemap, %edx
-	movl	(%edx, %eax, DTRACE_IDSIZE), %eax
-	testl	%eax, %eax			/* check for non-zero probe */
-	jz	1f
-	pushl	%ecx				/* push lock */
-	pushl	%eax				/* push probe ID */
-	call	*lockstat_probe
-	addl	$8, %esp
-1:
-	popl	%edx				/* restore thread pointer */
-	decb	T_LOCKSTAT(%edx)		/* curthread->t_lockstat-- */
-	movl	$1, %eax			/* return success if tryenter */
-	popl	%ebp				/* pop off frame */
-	ret
-	SET_SIZE(lockstat_wrapper)
-	SET_SIZE(mutex_enter)
-
-	ENTRY(lockstat_wrapper_arg)	/* expects edx=thread, ecx=lock, */
-					/* eax=lockstat event, pushed arg */
-	incb	T_LOCKSTAT(%edx)		/* curthread->t_lockstat++ */
-	pushl	%edx				/* save thread pointer	 */
-	movl	$lockstat_probemap, %edx
-	movl	(%edx, %eax, DTRACE_IDSIZE), %eax
-	testl	%eax, %eax			/* check for non-zero probe */
-	jz	1f
-	pushl	%ebp				/* save %ebp */
-	pushl	8(%esp)				/* push arg1 */
-	movl	%ebp, 12(%esp)			/* fake up the stack frame */
-	movl	%esp, %ebp			/* fake up base pointer */
-	addl	$12, %ebp			/* adjust faked base pointer */
-	pushl	%ecx				/* push lock */
-	pushl	%eax				/* push probe ID */
-	call	*lockstat_probe
-	addl	$12, %esp			/* adjust for arguments */
-	popl	%ebp				/* pop frame */
-1:
-	popl	%edx				/* restore thread pointer */
-	decb	T_LOCKSTAT(%edx)		/* curthread->t_lockstat-- */
-	movl	$1, %eax			/* return success if tryenter */
-	addl	$4, %esp			/* pop argument */
-	ret
-	SET_SIZE(lockstat_wrapper_arg)
-
-
-	ENTRY(mutex_tryenter)
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread ptr */
-	movl	4(%esp), %ecx			/* ecx = lock ptr */
-	xorl	%eax, %eax			/* eax = 0 (unheld adaptive) */
-	lock
-	cmpxchgl %edx, (%ecx)
-	jnz	mutex_vector_tryenter
-	movl	%ecx, %eax
-#if defined(OPTERON_WORKAROUND_6323525)
-.mutex_tryenter_lockstat_patch_point:
-.mutex_tryenter_6323525_patch_point:
-	ret					/* nop space for lfence */
-	nop
-	nop
-.mutex_tryenter_lockstat_6323525_patch_point:	/* new patch point if lfence */
-	nop
-#else	/* OPTERON_WORKAROUND_6323525 */
-.mutex_tryenter_lockstat_patch_point:
-	ret
-#endif	/* OPTERON_WORKAROUND_6323525 */
-	movl	$LS_MUTEX_ENTER_ACQUIRE, %eax
-	jmp	lockstat_wrapper
-	SET_SIZE(mutex_tryenter)
-
-	ENTRY(mutex_adaptive_tryenter)
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread ptr */
-	movl	4(%esp), %ecx			/* ecx = lock ptr */
-	xorl	%eax, %eax			/* eax = 0 (unheld adaptive) */
-	lock
-	cmpxchgl %edx, (%ecx)
-	jnz	0f
-	movl	%ecx, %eax
-#if defined(OPTERON_WORKAROUND_6323525)
-.mutex_atryenter_6323525_patch_point:
-	ret					/* nop space for lfence */
-	nop
-	nop
-	nop
-#else	/* OPTERON_WORKAROUND_6323525 */
-	ret
-#endif	/* OPTERON_WORKAROUND_6323525 */
-0:
-	xorl	%eax, %eax
-	ret
-	SET_SIZE(mutex_adaptive_tryenter)
-
-	.globl	mutex_owner_running_critical_start
-
-	ENTRY(mutex_owner_running)
-mutex_owner_running_critical_start:
-	movl	4(%esp), %eax		/* get owner field */
-	movl	(%eax), %eax
-	andl	$MUTEX_THREAD, %eax	/* remove waiters bit */
-	cmpl	$0, %eax		/* if free, skip */
-	je	1f			/* go return 0 */
-	movl	T_CPU(%eax), %ecx	/* get owner->t_cpu */
-	movl	CPU_THREAD(%ecx), %edx	/* get t_cpu->cpu_thread */
-.mutex_owner_running_critical_end:
-	cmpl	%eax, %edx	/* owner == running thread? */
-	je	2f		/* yes, go return cpu */
-1:
-	xorl	%eax, %eax	/* return 0 */
-	ret
-2:
-	movl	%ecx, %eax	/* return cpu */
-	ret
-
-	SET_SIZE(mutex_owner_running)
-
-	.globl	mutex_owner_running_critical_size
-	.type	mutex_owner_running_critical_size, @object
-	.align	CPTRSIZE
-mutex_owner_running_critical_size:
-	.long	.mutex_owner_running_critical_end - mutex_owner_running_critical_start
-	SET_SIZE(mutex_owner_running_critical_size)
-
-	.globl	mutex_exit_critical_start
-
-	ENTRY(mutex_exit)
-mutex_exit_critical_start:		/* If interrupted, restart here */
-	movl	%gs:CPU_THREAD, %edx
-	movl	4(%esp), %ecx
-	cmpl	%edx, (%ecx)
-	jne	mutex_vector_exit		/* wrong type or wrong owner */
-	movl	$0, (%ecx)			/* clear owner AND lock */
-.mutex_exit_critical_end:
-.mutex_exit_lockstat_patch_point:
-	ret
-	movl	$LS_MUTEX_EXIT_RELEASE, %eax
-	jmp	lockstat_wrapper
-	SET_SIZE(mutex_exit)
-
-	.globl	mutex_exit_critical_size
-	.type	mutex_exit_critical_size, @object
-	.align	CPTRSIZE
-mutex_exit_critical_size:
-	.long	.mutex_exit_critical_end - mutex_exit_critical_start
-	SET_SIZE(mutex_exit_critical_size)
-
-#endif	/* !__amd64 */
-
-#endif	/* __lint */
-
 /*
  * rw_enter() and rw_exit().
  *
@@ -901,22 +437,7 @@
  * and rw_exit (no waiters or not the last reader).  If anything complicated
  * is going on we punt to rw_enter_sleep() and rw_exit_wakeup(), respectively.
  */
-#if defined(lint) || defined(__lint)
 
-/* ARGSUSED */
-void
-rw_enter(krwlock_t *lp, krw_t rw)
-{}
-
-/* ARGSUSED */
-void
-rw_exit(krwlock_t *lp)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(rw_enter)
 	movq	%gs:CPU_THREAD, %rdx		/* rdx = thread ptr */
 	cmpl	$RW_WRITER, %esi
@@ -1003,107 +524,8 @@
 	jmp	lockstat_wrapper_arg
 	SET_SIZE(rw_exit)
 
-#else
-
-	ENTRY(rw_enter)
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread ptr */
-	movl	4(%esp), %ecx			/* ecx = lock ptr */
-	cmpl	$RW_WRITER, 8(%esp)
-	je	.rw_write_enter
-	incl	T_KPRI_REQ(%edx)		/* THREAD_KPRI_REQUEST() */
-	movl	(%ecx), %eax			/* eax = old rw_wwwh value */
-	testl	$RW_WRITE_LOCKED|RW_WRITE_WANTED, %eax
-	jnz	rw_enter_sleep
-	leal	RW_READ_LOCK(%eax), %edx	/* edx = new rw_wwwh value */
-	lock
-	cmpxchgl %edx, (%ecx)			/* try to grab read lock */
-	jnz	rw_enter_sleep
-.rw_read_enter_lockstat_patch_point:
-	ret
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread ptr */
-	movl	$LS_RW_ENTER_ACQUIRE, %eax
-	pushl	$RW_READER
-	jmp	lockstat_wrapper_arg
-.rw_write_enter:
-	orl	$RW_WRITE_LOCKED, %edx		/* edx = write-locked value */
-	xorl	%eax, %eax			/* eax = unheld value */
-	lock
-	cmpxchgl %edx, (%ecx)			/* try to grab write lock */
-	jnz	rw_enter_sleep
-
 #if defined(OPTERON_WORKAROUND_6323525)
-.rw_write_enter_lockstat_patch_point:
-.rw_write_enter_6323525_patch_point:
-	ret
-	nop
-	nop
-.rw_write_enter_lockstat_6323525_patch_point:
-	nop
-#else	/* OPTERON_WORKAROUND_6323525 */
-.rw_write_enter_lockstat_patch_point:
-	ret
-#endif	/* OPTERON_WORKAROUND_6323525 */
 
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread ptr */
-	movl	$LS_RW_ENTER_ACQUIRE, %eax
-	pushl	$RW_WRITER
-	jmp	lockstat_wrapper_arg
-	SET_SIZE(rw_enter)
-
-	ENTRY(rw_exit)
-	movl	4(%esp), %ecx			/* ecx = lock ptr */
-	movl	(%ecx), %eax			/* eax = old rw_wwwh value */
-	cmpl	$RW_READ_LOCK, %eax		/* single-reader, no waiters? */
-	jne	.rw_not_single_reader
-	xorl	%edx, %edx			/* edx = new value (unheld) */
-.rw_read_exit:
-	lock
-	cmpxchgl %edx, (%ecx)			/* try to drop read lock */
-	jnz	rw_exit_wakeup
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread ptr */
-	decl	T_KPRI_REQ(%edx)		/* THREAD_KPRI_RELEASE() */
-.rw_read_exit_lockstat_patch_point:
-	ret
-	movl	$LS_RW_EXIT_RELEASE, %eax
-	pushl	$RW_READER
-	jmp	lockstat_wrapper_arg
-.rw_not_single_reader:
-	testl	$RW_WRITE_LOCKED, %eax	/* write-locked or write-wanted? */
-	jnz	.rw_write_exit
-	leal	-RW_READ_LOCK(%eax), %edx	/* edx = new value */
-	cmpl	$RW_READ_LOCK, %edx
-	jge	.rw_read_exit		/* not last reader, safe to drop */
-	jmp	rw_exit_wakeup			/* last reader with waiters */
-.rw_write_exit:
-	movl	%gs:CPU_THREAD, %eax		/* eax = thread ptr */
-	xorl	%edx, %edx			/* edx = new value (unheld) */
-	orl	$RW_WRITE_LOCKED, %eax		/* eax = write-locked value */
-	lock
-	cmpxchgl %edx, (%ecx)			/* try to drop read lock */
-	jnz	rw_exit_wakeup
-.rw_write_exit_lockstat_patch_point:
-	ret
-	movl	%gs:CPU_THREAD, %edx		/* edx = thread ptr */
-	movl	$LS_RW_EXIT_RELEASE, %eax
-	pushl	$RW_WRITER
-	jmp	lockstat_wrapper_arg
-	SET_SIZE(rw_exit)
-
-#endif	/* !__amd64 */
-
-#endif	/* __lint */
-
-#if defined(OPTERON_WORKAROUND_6323525)
-#if defined(lint) || defined(__lint)
-
-int	workaround_6323525_patched;
-
-void
-patch_workaround_6323525(void)
-{}
-
-#else	/* lint */
-
 /*
  * If it is necessary to patch the lock enter routines with the lfence
  * workaround, workaround_6323525_patched is set to a non-zero value so that
@@ -1113,8 +535,6 @@
 	DGDEF3(workaround_6323525_patched, 4, 4)
 	.long	0
 
-#if defined(__amd64)
-
 #define HOT_MUTEX_PATCH(srcaddr, dstaddr, size)	\
 	movq	$size, %rbx;			\
 	movq	$dstaddr, %r13;			\
@@ -1178,69 +598,9 @@
 	SET_SIZE(patch_workaround_6323525)
 
 
-#else	/* __amd64 */
-
-#define HOT_MUTEX_PATCH(srcaddr, dstaddr, size)	\
-	movl	$size, %ebx;			\
-	movl	$srcaddr, %esi;			\
-	addl	%ebx, %esi;			\
-	movl	$dstaddr, %edi;			\
-	addl	%ebx, %edi;			\
-0:      					\
-	decl	%esi;				\
-	decl	%edi;				\
-	pushl	$1;				\
-	movzbl	(%esi), %eax;			\
-	pushl	%eax;				\
-	pushl	%edi;				\
-	call	hot_patch_kernel_text;		\
-	addl	$12, %esp;			\
-	decl	%ebx;				\
-	testl	%ebx, %ebx;			\
-	jg	0b;
-
-
-	/* see comments above */
-	ENTRY_NP(patch_workaround_6323525)
-	pushl	%ebp
-	movl	%esp, %ebp
-	pushl	%ebx
-	pushl	%esi
-	pushl	%edi
-
-	movl	$1, workaround_6323525_patched
-
-	HOT_MUTEX_PATCH(_lfence_insn, .mutex_enter_6323525_patch_point, 4)
-	HOT_MUTEX_PATCH(_lfence_insn, .mutex_tryenter_6323525_patch_point, 4)
-	HOT_MUTEX_PATCH(_lfence_insn, .mutex_atryenter_6323525_patch_point, 4)
-	HOT_MUTEX_PATCH(_lfence_insn, .rw_write_enter_6323525_patch_point, 4)
-
-	popl	%edi
-	popl	%esi
-	popl	%ebx
-	movl	%ebp, %esp
-	popl	%ebp
-	ret
-_lfence_insn:
-	.byte	0xf, 0xae, 0xe8		/ [lfence instruction]
-	ret
-	SET_SIZE(patch_workaround_6323525)
-
-#endif	/* !__amd64 */
-#endif	/* !lint */
 #endif	/* OPTERON_WORKAROUND_6323525 */
 
 
-#if defined(lint) || defined(__lint)
-
-void
-lockstat_hot_patch(void)
-{}
-
-#else
-
-#if defined(__amd64)
-
 #define	HOT_PATCH(addr, event, active_instr, normal_instr, len)	\
 	movq	$normal_instr, %rsi;		\
 	movq	$active_instr, %rdi;		\
@@ -1254,29 +614,9 @@
 	movq	$addr, %rdi;			\
 	call	hot_patch_kernel_text
 
-#else
-
-#define	HOT_PATCH(addr, event, active_instr, normal_instr, len)	\
-	movl	$normal_instr, %ecx;		\
-	movl	$active_instr, %edx;		\
-	movl	$lockstat_probemap, %eax;	\
-	movl	_MUL(event, DTRACE_IDSIZE)(%eax), %eax;	\
-	testl	%eax, %eax;			\
-	jz	. + 4;				\
-	movl	%edx, %ecx;			\
-	pushl	$len;				\
-	pushl	%ecx;				\
-	pushl	$addr;				\
-	call	hot_patch_kernel_text;		\
-	addl	$12, %esp;
-
-#endif	/* !__amd64 */
-
 	ENTRY(lockstat_hot_patch)
-#if defined(__amd64)
 	pushq	%rbp			/* align stack properly */
 	movq	%rsp, %rbp
-#endif	/* __amd64 */
 
 #if defined(OPTERON_WORKAROUND_6323525)
 	cmpl	$0, workaround_6323525_patched
@@ -1324,42 +664,10 @@
 	HOT_PATCH(LOCK_CLEAR_SPLX_LOCKSTAT_PATCH_POINT,
 		LS_LOCK_CLEAR_SPLX_RELEASE,
 		LOCK_CLEAR_SPLX_LOCKSTAT_PATCH_VAL, 0, 1);
-#if defined(__amd64)
 	leave			/* unwind stack */
-#endif	/* __amd64 */
 	ret
 	SET_SIZE(lockstat_hot_patch)
 
-#endif	/* __lint */
-
-#if defined(lint) || defined(__lint)
-
-/* XX64 membar_*() should be inlines */
-
-void
-membar_sync(void)
-{}
-
-void
-membar_enter(void)
-{}
-
-void
-membar_exit(void)
-{}
-
-void
-membar_producer(void)
-{}
-
-void
-membar_consumer(void)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(membar_enter)
 	ALTENTRY(membar_exit)
 	ALTENTRY(membar_sync)
@@ -1379,44 +687,7 @@
 	ret
 	SET_SIZE(membar_consumer)
 
-#else
-
-	ENTRY(membar_enter)
-	ALTENTRY(membar_exit)
-	ALTENTRY(membar_sync)
-	lock
-	xorl	$0, (%esp)
-	ret
-	SET_SIZE(membar_sync)
-	SET_SIZE(membar_exit)
-	SET_SIZE(membar_enter)
-
 /*
- * On machines that support sfence and lfence, these
- * memory barriers can be more precisely implemented
- * without causing the whole world to stop
- */
-	ENTRY(membar_producer)
-	.globl	_patch_sfence_ret
-_patch_sfence_ret:			/* c.f. membar #StoreStore */
-	lock
-	xorl	$0, (%esp)
-	ret
-	SET_SIZE(membar_producer)
-
-	ENTRY(membar_consumer)
-	.globl	_patch_lfence_ret
-_patch_lfence_ret:			/* c.f. membar #LoadLoad */
-	lock
-	xorl	$0, (%esp)
-	ret
-	SET_SIZE(membar_consumer)
-
-#endif	/* !__amd64 */
-
-#endif	/* __lint */
-
-/*
  * thread_onproc()
  * Set thread in onproc state for the specified CPU.
  * Also set the thread lock pointer to the CPU's onproc lock.
@@ -1423,19 +694,7 @@
  * Since the new lock isn't held, the store ordering is important.
  * If not done in assembler, the compiler could reorder the stores.
  */
-#if defined(lint) || defined(__lint)
 
-void
-thread_onproc(kthread_id_t t, cpu_t *cp)
-{
-	t->t_state = TS_ONPROC;
-	t->t_lockp = &cp->cpu_thread_lock;
-}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(thread_onproc)
 	addq	$CPU_THREAD_LOCK, %rsi	/* pointer to disp_lock while running */
 	movl	$ONPROC_THREAD, T_STATE(%rdi)	/* set state to TS_ONPROC */
@@ -1443,36 +702,11 @@
 	ret
 	SET_SIZE(thread_onproc)
 
-#else
-
-	ENTRY(thread_onproc)
-	movl	4(%esp), %eax
-	movl	8(%esp), %ecx
-	addl	$CPU_THREAD_LOCK, %ecx	/* pointer to disp_lock while running */
-	movl	$ONPROC_THREAD, T_STATE(%eax)	/* set state to TS_ONPROC */
-	movl	%ecx, T_LOCKP(%eax)	/* store new lock pointer */
-	ret
-	SET_SIZE(thread_onproc)
-
-#endif	/* !__amd64 */
-
-#endif	/* __lint */
-
 /*
  * mutex_delay_default(void)
  * Spins for approx a few hundred processor cycles and returns to caller.
  */
 
-#if defined(lint) || defined(__lint)
-
-void
-mutex_delay_default(void)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(mutex_delay_default)
 	movq	$92,%r11
 0:	decq	%r11
@@ -1480,20 +714,3 @@
 	ret
 	SET_SIZE(mutex_delay_default)
 
-#else
-
-	ENTRY(mutex_delay_default)
-	push	%ebp
-	movl	%esp,%ebp
-	andl	$-16,%esp
-	push	%ebx
-	movl	$93,%ebx
-0:	decl	%ebx
-	jg	0b
-	pop	%ebx
-	leave
-	ret
-	SET_SIZE(mutex_delay_default)
-
-#endif	/* !__amd64 */
-#endif	/* __lint */
--- old/usr/src/uts/intel/ia32/ml/modstubs.s	Thu Nov 14 19:00:27 2019
+++ new/usr/src/uts/intel/ia32/ml/modstubs.s	Thu Nov 14 19:00:27 2019
@@ -26,12 +26,6 @@
 
 #include <sys/asm_linkage.h>
 
-#if defined(__lint)
-
-char stubs_base[1], stubs_end[1];
-
-#else	/* __lint */
-
 #include "assym.h"
 
 /*
@@ -1305,4 +1299,3 @@
 	ENTRY_NP(stubs_end)
 	nop
 
-#endif	/* lint */
--- old/usr/src/uts/intel/ia32/ml/ovbcopy.s	Thu Nov 14 19:00:27 2019
+++ new/usr/src/uts/intel/ia32/ml/ovbcopy.s	Thu Nov 14 19:00:27 2019
@@ -3,7 +3,9 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
+/*
+ * Copyright 2019 Joyent, Inc.
+ */
 
 /*-
  * Copyright (c) 1993 The Regents of the University of California.
@@ -42,19 +44,7 @@
 
 #include <sys/asm_linkage.h>
 
-#if defined(__lint)
-
 /*
- * Overlapping bcopy (source and target may overlap arbitrarily).
- */
-/* ARGSUSED */
-void
-ovbcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* __lint */
-
-/*
  * Adapted from fbsd bcopy().
  *
  * bcopy(src, dst, cnt)
@@ -62,8 +52,6 @@
  *  ws@tools.de     (Wolfgang Solfrank, TooLs GmbH) +49-228-985800
  */
 
-#if defined(__amd64)
-
 	ENTRY(ovbcopy)
 	xchgq	%rsi,%rdi
 	movq	%rdx,%rcx
@@ -102,53 +90,3 @@
 	ret
 	SET_SIZE(ovbcopy)
 
-#elif defined(__i386)
-
-	ENTRY(ovbcopy)
-	pushl	%esi
-	pushl	%edi
-	movl	12(%esp),%esi
-	movl	16(%esp),%edi
-	movl	20(%esp),%ecx
-
-	movl	%edi,%eax
-	subl	%esi,%eax
-	cmpl	%ecx,%eax		/* overlapping && src < dst? */
-	jb	reverse
-
-	shrl	$2,%ecx			/* copy by 32-bit words */
-	cld				/* nope, copy forwards */
-	rep
-	movsl
-	movl	20(%esp),%ecx
-	andl	$3,%ecx			/* any bytes left? */
-	rep
-	movsb
-	popl	%edi
-	popl	%esi
-	ret
-
-reverse:
-	addl	%ecx,%edi		/* copy backwards */
-	addl	%ecx,%esi
-	decl	%edi
-	decl	%esi
-	andl	$3,%ecx			/* any fractional bytes? */
-	std
-	rep
-	movsb
-	movl	20(%esp),%ecx		/* copy remainder by 32-bit words */
-	shrl	$2,%ecx
-	subl	$3,%esi
-	subl	$3,%edi
-	rep
-	movsl
-	popl	%edi
-	popl	%esi
-	cld
-	ret
-	SET_SIZE(ovbcopy)
-
-#endif	/* __i386 */
-
-#endif	/* __lint */
--- old/usr/src/uts/intel/ia32/ml/sseblk.s	Thu Nov 14 19:00:27 2019
+++ new/usr/src/uts/intel/ia32/ml/sseblk.s	Thu Nov 14 19:00:27 2019
@@ -23,18 +23,15 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
+/*
+ * Copyright 2019 Joyent, Inc.
+ */
 
 #include <sys/asm_linkage.h>
 #include <sys/regset.h>
 #include <sys/privregs.h>
 
-#if defined(__lint)
-#include <sys/types.h>
-#include <sys/archsystm.h>
-#else
 #include "assym.h"
-#endif
 
 /*
  * Do block operations using Streaming SIMD extensions
@@ -41,7 +38,6 @@
  */
 
 #if defined(DEBUG)
-#if defined(__amd64)
 #define	ASSERT_KPREEMPT_DISABLED(t, r32, msg)	\
 	movq	%gs:CPU_THREAD, t;		\
 	movsbl	T_PREEMPT(t), r32;		\
@@ -53,18 +49,6 @@
 	xorl	%eax, %eax;			\
 	call	panic;				\
 5:
-#elif defined(__i386)
-#define	ASSERT_KPREEMPT_DISABLED(t, r32, msg)	\
-	movl	%gs:CPU_THREAD, t;		\
-	movsbl	T_PREEMPT(t), r32;		\
-	testl	r32, r32;			\
-	jne	5f;				\
-	pushl	%ebp;				\
-	movl	%esp, %ebp;			\
-	pushl	$msg;				\
-	call	panic;				\
-5:
-#endif	/* __i386 */
 #else	/* DEBUG */
 #define	ASSERT_KPREEMPT_DISABLED(t, r32, msg)
 #endif	/* DEBUG */
@@ -77,23 +61,6 @@
 #error	"mucked up constants"
 #endif
 
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-hwblkclr(void *addr, size_t size)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-#define	ADD	addq
-#define	SUB	subq
-#else
-#define	ADD	addl
-#define	SUB	subl
-#endif
-
 #define	SAVE_XMM0(r)				\
 	SAVE_XMM_PROLOG(r, 1);			\
 	movdqa	%xmm0, (r)
@@ -106,8 +73,8 @@
 	movntdq	%xmm0, 0x10(dst);		\
 	movntdq	%xmm0, 0x20(dst);		\
 	movntdq	%xmm0, 0x30(dst);		\
-	ADD	$BLOCKSIZE, dst;		\
-	SUB	$1, cnt
+	addq	$BLOCKSIZE, dst;		\
+	subq	$1, cnt
 
 #define	ZERO_LOOP_FINI_XMM(dst)			\
 	mfence
@@ -116,8 +83,6 @@
 	movdqa	0x0(r), %xmm0;			\
 	RSTOR_XMM_EPILOG(r, 1)
 
-#if defined(__amd64)
-
 	/*
 	 * %rdi		dst
 	 * %rsi		size
@@ -158,66 +123,7 @@
 	jmp	bzero
 	SET_SIZE(hwblkclr)
 
-#elif defined(__i386)
 
-	/*
-	 * %eax		dst
-	 * %ecx		size in bytes, loop count
-	 * %ebx		saved %cr0 (#if DEBUG then t->t_preempt)
-	 * %edi		pointer to %xmm register save area
-	 */
-	ENTRY(hwblkclr)
-	movl	4(%esp), %eax
-	movl	8(%esp), %ecx
-	testl	$BLOCKMASK, %eax	/* address must be BLOCKSIZE aligned */
-	jne	.dobzero
-	cmpl	$BLOCKSIZE, %ecx	/* size must be at least BLOCKSIZE */
-	jl	.dobzero
-	testl	$BLOCKMASK, %ecx 	/* .. and be a multiple of BLOCKSIZE */
-	jne	.dobzero
-	shrl	$BLOCKSHIFT, %ecx
-	movl	0xc(%esp), %edx
-	pushl	%ebx
-
-	pushl	%esi
-	ASSERT_KPREEMPT_DISABLED(%esi, %ebx, .not_disabled)
-	popl	%esi
-	movl	%cr0, %ebx
-	clts
-	testl	$CR0_TS, %ebx
-	jnz	1f
-
-	pushl	%edi
-	SAVE_XMM0(%edi)
-1:	ZERO_LOOP_INIT_XMM(%eax)
-9:	ZERO_LOOP_BODY_XMM(%eax, %ecx)
-	jnz	9b
-	ZERO_LOOP_FINI_XMM(%eax)
-
-	testl	$CR0_TS, %ebx
-	jnz	2f
-	RSTOR_XMM0(%edi)
-	popl	%edi
-2:	movl	%ebx, %cr0
-	popl	%ebx
-	ret
-.dobzero:
-	jmp	bzero
-	SET_SIZE(hwblkclr)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-void
-hwblkpagecopy(const void *src, void *dst)
-{}
-
-#else	/* __lint */
-
 #define	PREFETCH_START(src)			\
 	prefetchnta	0x0(src);		\
 	prefetchnta	0x40(src)
@@ -244,7 +150,7 @@
 	movdqa	0x50(src), %xmm5;		\
 	movdqa	0x60(src), %xmm6;		\
 	movdqa	0x70(src), %xmm7;		\
-	ADD	$0x80, src
+	addq	$0x80, src
 
 #define	COPY_LOOP_BODY_XMM(src, dst, cnt)	\
 	prefetchnta	0x80(src);		\
@@ -265,10 +171,10 @@
 	movntdq	%xmm7, 0x70(dst);		\
 	movdqa	0x40(src), %xmm4;		\
 	movdqa	0x50(src), %xmm5;		\
-	ADD	$0x80, dst;			\
+	addq	$0x80, dst;			\
 	movdqa	0x60(src), %xmm6;		\
 	movdqa	0x70(src), %xmm7;		\
-	ADD	$0x80, src;			\
+	addq	$0x80, src;			\
 	subl	$1, cnt
 
 #define	COPY_LOOP_FINI_XMM(dst)			\
@@ -292,8 +198,6 @@
 	movdqa	0x70(r), %xmm7;			\
 	RSTOR_XMM_EPILOG(r, 8)
 
-#if defined(__amd64)
-
 	/*
 	 * %rdi		src
 	 * %rsi		dst
@@ -330,70 +234,6 @@
 	ret
 	SET_SIZE(hwblkpagecopy)
 
-#elif defined(__i386)
-
-	/*
-	 * %eax		src
-	 * %edx		dst
-	 * %ecx		loop count
-	 * %ebx		saved %cr0 (#if DEBUG then t->t_prempt)
-	 * %edi		pointer to %xmm register save area
-	 * %esi		#if DEBUG temporary thread pointer
-	 */
-	ENTRY(hwblkpagecopy)
-	movl	4(%esp), %eax
-	movl	8(%esp), %edx
-	PREFETCH_START(%eax)
-	pushl	%ebx
-	/*
-	 * PAGESIZE is 4096, each loop moves 128 bytes, but the initial
-	 * load and final store save us one loop count
-	 */
-	movl	$_CONST(32 - 1), %ecx
-	pushl	%esi
-	ASSERT_KPREEMPT_DISABLED(%esi, %ebx, .not_disabled)
-	popl	%esi
-	movl	%cr0, %ebx
-	clts
-	testl	$CR0_TS, %ebx
-	jnz	3f
-	pushl	%edi
-	SAVE_XMMS(%edi)
-3:	COPY_LOOP_INIT_XMM(%eax)
-4:	COPY_LOOP_BODY_XMM(%eax, %edx, %ecx)
-	jnz	4b
-	COPY_LOOP_FINI_XMM(%edx)
-	testl	$CR0_TS, %ebx
-	jnz	5f
-	RSTOR_XMMS(%edi)
-	popl	%edi
-5:	movl	%ebx, %cr0
-	popl	%ebx
-	mfence
-	ret
-	SET_SIZE(hwblkpagecopy)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(__lint)
-
-/*
- * Version of hwblkclr which doesn't use XMM registers.
- * Note that it requires aligned dst and len.
- *
- * XXPV This needs to be performance tuned at some point.
- *	Is 4 the best number of iterations to unroll?
- */
-/*ARGSUSED*/
-void
-block_zero_no_xmm(void *dst, int len)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(block_zero_no_xmm)
 	pushq	%rbp
 	movq	%rsp, %rbp
@@ -412,50 +252,7 @@
 	ret
 	SET_SIZE(block_zero_no_xmm)
 
-#elif defined(__i386)
 
-	ENTRY(block_zero_no_xmm)
-	pushl	%ebp
-	movl	%esp, %ebp
-	xorl	%eax, %eax
-	movl	8(%ebp), %edx
-	movl	12(%ebp), %ecx
-	addl	%ecx, %edx
-	negl	%ecx
-1:
-	movnti	%eax, (%edx, %ecx)
-	movnti	%eax, 4(%edx, %ecx)
-	movnti	%eax, 8(%edx, %ecx)
-	movnti	%eax, 12(%edx, %ecx)
-	addl	$16, %ecx
-	jnz	1b
-	mfence
-	leave
-	ret
-	SET_SIZE(block_zero_no_xmm)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-
-#if defined(__lint)
-
-/*
- * Version of page copy which doesn't use XMM registers.
- *
- * XXPV	This needs to be performance tuned at some point.
- *	Is 4 the right number of iterations to unroll?
- *	Is the load/store order optimal? Should it use prefetch?
- */
-/*ARGSUSED*/
-void
-page_copy_no_xmm(void *dst, void *src)
-{}
-
-#else	/* __lint */
-
-#if defined(__amd64)
-
 	ENTRY(page_copy_no_xmm)
 	movq	$MMU_STD_PAGESIZE, %rcx
 	addq	%rcx, %rdi
@@ -476,36 +273,7 @@
 	ret
 	SET_SIZE(page_copy_no_xmm)
 
-#elif defined(__i386)
-
-	ENTRY(page_copy_no_xmm)
-	pushl	%esi
-	movl	$MMU_STD_PAGESIZE, %ecx
-	movl	8(%esp), %edx
-	movl	12(%esp), %esi
-	addl	%ecx, %edx
-	addl	%ecx, %esi
-	negl	%ecx
-1:
-	movl	(%esi, %ecx), %eax
-	movnti	%eax, (%edx, %ecx)
-	movl	4(%esi, %ecx), %eax
-	movnti	%eax, 4(%edx, %ecx)
-	movl	8(%esi, %ecx), %eax
-	movnti	%eax, 8(%edx, %ecx)
-	movl	12(%esi, %ecx), %eax
-	movnti	%eax, 12(%edx, %ecx)
-	addl	$16, %ecx
-	jnz	1b
-	mfence
-	popl	%esi
-	ret
-	SET_SIZE(page_copy_no_xmm)
-
-#endif	/* __i386 */
-#endif	/* __lint */
-
-#if defined(DEBUG) && !defined(__lint)
+#if defined(DEBUG)
 	.text
 .not_disabled:
 	.string	"sseblk: preemption not disabled!"
--- old/usr/src/uts/intel/ia32/sys/kdi_regs.h	Thu Nov 14 19:00:28 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,73 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- *
- * Copyright 2018 Joyent, Inc.
- */
-
-#ifndef _IA32_SYS_KDI_REGS_H
-#define	_IA32_SYS_KDI_REGS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define	KDIREG_NGREG	21
-
-/*
- * %ss appears in a different place than a typical struct regs, since the
- * machine won't save %ss on a trap entry from the same privilege level.
- */
-
-#define	KDIREG_SAVFP	0
-#define	KDIREG_SAVPC	1
-#define	KDIREG_SS	2
-#define	KDIREG_GS	3
-#define	KDIREG_FS	4
-#define	KDIREG_ES	5
-#define	KDIREG_DS	6
-#define	KDIREG_EDI	7
-#define	KDIREG_ESI	8
-#define	KDIREG_EBP	9
-#define	KDIREG_ESP	10
-#define	KDIREG_EBX	11
-#define	KDIREG_EDX	12
-#define	KDIREG_ECX	13
-#define	KDIREG_EAX	14
-#define	KDIREG_TRAPNO	15
-#define	KDIREG_ERR	16
-#define	KDIREG_EIP	17
-#define	KDIREG_CS	18
-#define	KDIREG_EFLAGS	19
-#define	KDIREG_UESP	20
-
-#define	KDIREG_PC	KDIREG_EIP
-#define	KDIREG_SP	KDIREG_ESP
-#define	KDIREG_FP	KDIREG_EBP
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _IA32_SYS_KDI_REGS_H */
--- old/usr/src/uts/intel/ia32/sys/privmregs.h	Thu Nov 14 19:00:28 2019
+++ /dev/null	Thu Nov 14 17:58:35 2019
@@ -1,67 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-#ifndef	_IA32_SYS_PRIVMREGS_H
-#define	_IA32_SYS_PRIVMREGS_H
-
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(__i386)
-#error	"non-i386 code depends on i386 privileged header!"
-#endif
-
-#ifndef _ASM
-
-#define	PM_GREGS (1 << 0)
-#define	PM_CRREGS (1 << 1)
-#define	PM_DRREGS (1 << 2)
-
-/*
- * This structure is intended to represent a complete machine state for a CPU,
- * when that information is available.  It is only for use internally between
- * KMDB and the kernel, or within MDB.  Note that this isn't yet finished.
- */
-typedef struct privmregs {
-	ulong_t pm_flags;
-	/* general registers */
-	struct regs pm_gregs;
-	/* cr0-8 */
-	ulong_t pm_cr[8];
-	/* dr0-8 */
-	ulong_t pm_dr[8];
-} privmregs_t;
-
-#endif /* !_ASM */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* !_IA32_SYS_PRIVMREGS_H */
--- old/usr/src/uts/intel/io/acpica/osl_ml.s	Thu Nov 14 19:00:28 2019
+++ new/usr/src/uts/intel/io/acpica/osl_ml.s	Thu Nov 14 19:00:28 2019
@@ -23,14 +23,13 @@
  * Use is subject to license terms.
  */
 
+/*
+ * Copyright 2019 Joyent, Inc.
+ */
+
 #include <sys/asm_linkage.h>
 #include <sys/asm_misc.h>
 
-#if defined(lint) || defined(__lint)
-#include <sys/types.h>
-#include "acpi.h"
-#endif	/* lint */
-
 /*
  * Implementation as specific by ACPI 3.0 specification
  * section 5.2.10.1
@@ -54,16 +53,6 @@
 /* Offset of GlobalLock element in FACS structure */
 #define	GlobalLock	0x10
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-UINT32
-__acpi_acquire_global_lock(void *Facs)
-{ return (0); }
-
-#else	/* lint */
-
-#if defined(__amd64)
 	ENTRY(__acpi_acquire_global_lock)
 	movq	$0xff, %rax		/ error return if FACS is null
 	orq	%rdi, %rdi		/ %rdi contains pointer to FACS
@@ -84,44 +73,7 @@
 	ret
 	SET_SIZE(__acpi_acquire_global_lock)
 
-#elif defined(__i386)
 
-	ENTRY(__acpi_acquire_global_lock)
-	movl	$0xff, %eax		/ error return if FACS is null
-	movl	4(%esp), %ecx		/ %ecx contains pointer to FACS
-	orl	%ecx, %ecx
-	jz	1f
-	leal	GlobalLock(%ecx), %ecx	/ make %ecx point at the lock
-0:
-	movl	(%ecx), %eax
-	movl	%eax, %edx
-	andl	$0xFFFFFFFE, %edx
-	btsl	$1, %edx
-	adcl	$0, %edx
-	lock
-	cmpxchgl %edx, (%ecx)
-	jnz	0b
-	cmpb	$3, %dl
-	sbbl	%eax, %eax
-1:
-	ret
-	SET_SIZE(__acpi_acquire_global_lock)
-
-#endif	/* i386 */
-
-#endif	/* lint */
-
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-UINT32
-__acpi_release_global_lock(void *Facs)
-{ return (0); }
-
-#else	/* lint */
-
-#if defined(__amd64)
 	ENTRY(__acpi_release_global_lock)
 	xorq	%rax, %rax	/ error return if FACS is null
 	orq	%rdi, %rdi	/ %rdi contains pointer to FACS
@@ -139,48 +91,13 @@
 	ret
 	SET_SIZE(__acpi_release_global_lock)
 
-#elif defined(__i386)
 
-	ENTRY(__acpi_release_global_lock)
-	xorl	%eax, %eax		/ error return if FACS is null
-	movl	4(%esp), %ecx		/ %ecx contains pointer to FACS
-	orl	%ecx, %ecx
-	jz	1f
-	leal	GlobalLock(%ecx), %ecx	/ make %ecx point at the lock
-0:
-	movl	(%ecx), %eax
-	movl	%eax, %edx
-	andl	$0xFFFFFFFC, %edx
-	lock
-	cmpxchgl %edx, (%ecx)
-	jnz	0b
-	andl	$1, %eax
-1:
-	ret
-	SET_SIZE(__acpi_release_global_lock)
-
-#endif	/* i386 */
-
-#endif	/* lint */
-
-
 /*
  * execute WBINVD instruction
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-__acpi_wbinvd(void)
-{ }
-
-#else	/* lint */
-
 	ENTRY(__acpi_wbinvd)
 	wbinvd
 	ret
 	SET_SIZE(__acpi_wbinvd)
-
-#endif	/* lint */
 
--- old/usr/src/uts/intel/kdi/kdi_asm.s	Thu Nov 14 19:00:28 2019
+++ new/usr/src/uts/intel/kdi/kdi_asm.s	Thu Nov 14 19:00:28 2019
@@ -31,10 +31,6 @@
  * the IDT stubs that drop into here (mainly via kdi_cmnint).
  */
 
-#if defined(__lint)
-#include <sys/types.h>
-#else
-
 #include <sys/segments.h>
 #include <sys/asm_linkage.h>
 #include <sys/controlregs.h>
@@ -716,4 +712,3 @@
 	SETDREG(kdi_setdr6, %dr6)
 	SETDREG(kdi_setdr7, %dr7)
 
-#endif /* !__lint */
--- old/usr/src/uts/intel/kdi/kdi_idthdl.s	Thu Nov 14 19:00:28 2019
+++ new/usr/src/uts/intel/kdi/kdi_idthdl.s	Thu Nov 14 19:00:28 2019
@@ -33,10 +33,6 @@
  * different number.
  */
 
-#if defined(__lint)
-#include <sys/types.h>
-#else
-
 #include <sys/asm_linkage.h>
 #include <sys/asm_misc.h>
 #include <sys/machprivregs.h>
@@ -325,4 +321,3 @@
 	nop
 #endif
 
-#endif /* !__lint */
--- old/usr/src/uts/sfmmu/ml/sfmmu_asm.s	Thu Nov 14 19:00:29 2019
+++ new/usr/src/uts/sfmmu/ml/sfmmu_asm.s	Thu Nov 14 19:00:29 2019
@@ -29,11 +29,7 @@
  * routines.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/machtrap.h>
@@ -67,8 +63,6 @@
 
 #endif /* TRAPTRACE */
 
-#ifndef	lint
-
 #if (TTE_SUSPEND_SHIFT > 0)
 #define	TTE_SUSPEND_INT_SHIFT(reg)				\
 	sllx	reg, TTE_SUSPEND_SHIFT, reg
@@ -76,10 +70,6 @@
 #define	TTE_SUSPEND_INT_SHIFT(reg)
 #endif
 
-#endif /* lint */
-
-#ifndef	lint
-
 /*
  * Assumes TSBE_TAG is 0
  * Assumes TSBE_INTHI is 0
@@ -470,62 +460,7 @@
 	nop				/* for perf reasons */		;\
 	or	tmp, dest, dest		/* contents of patched value */
 
-#endif /* lint */
 
-
-#if defined (lint)
-
-/*
- * sfmmu related subroutines
- */
-uint_t
-sfmmu_disable_intrs()
-{ return(0); }
-
-/* ARGSUSED */
-void
-sfmmu_enable_intrs(uint_t pstate_save)
-{}
-
-/* ARGSUSED */
-int
-sfmmu_alloc_ctx(sfmmu_t *sfmmup, int allocflag, struct cpu *cp, int shflag)
-{ return(0); }
-
-/*
- * Use cas, if tte has changed underneath us then reread and try again.
- * In the case of a retry, it will update sttep with the new original.
- */
-/* ARGSUSED */
-int
-sfmmu_modifytte(tte_t *sttep, tte_t *stmodttep, tte_t *dttep)
-{ return(0); }
-
-/*
- * Use cas, if tte has changed underneath us then return 1, else return 0
- */
-/* ARGSUSED */
-int
-sfmmu_modifytte_try(tte_t *sttep, tte_t *stmodttep, tte_t *dttep)
-{ return(0); }
-
-/* ARGSUSED */
-void
-sfmmu_copytte(tte_t *sttep, tte_t *dttep)
-{}
-
-/*ARGSUSED*/
-struct tsbe *
-sfmmu_get_tsbe(uint64_t tsbeptr, caddr_t vaddr, int vpshift, int tsb_szc)
-{ return(0); }
-
-/*ARGSUSED*/
-uint64_t
-sfmmu_make_tsbtag(caddr_t va)
-{ return(0); }
-
-#else	/* lint */
-
 	.seg	".data"
 	.global	sfmmu_panic1
 sfmmu_panic1:
@@ -931,60 +866,11 @@
 	srln	%o0, TTARGET_VA_SHIFT, %o0
 	SET_SIZE(sfmmu_make_tsbtag)
 
-#endif /* lint */
-
 /*
  * Other sfmmu primitives
  */
 
 
-#if defined (lint)
-void
-sfmmu_patch_ktsb(void)
-{
-}
-
-void
-sfmmu_kpm_patch_tlbm(void)
-{
-}
-
-void
-sfmmu_kpm_patch_tsbm(void)
-{
-}
-
-void
-sfmmu_patch_shctx(void)
-{
-}
-
-/* ARGSUSED */
-void
-sfmmu_load_tsbe(struct tsbe *tsbep, uint64_t vaddr, tte_t *ttep, int phys)
-{
-}
-
-/* ARGSUSED */
-void
-sfmmu_unload_tsbe(struct tsbe *tsbep, uint64_t vaddr, int phys)
-{
-}
-
-/* ARGSUSED */
-void
-sfmmu_kpm_load_tsb(caddr_t addr, tte_t *ttep, int vpshift)
-{
-}
-
-/* ARGSUSED */
-void
-sfmmu_kpm_unload_tsb(caddr_t addr, int vpshift)
-{
-}
-
-#else /* lint */
-
 #define	I_SIZE		4
 
 	ENTRY_NP(sfmmu_fix_ktlb_traptable)
@@ -1562,18 +1448,7 @@
 	  membar	#StoreStore|#StoreLoad
 	SET_SIZE(sfmmu_kpm_unload_tsb)
 
-#endif /* lint */
 
-
-#if defined (lint)
-
-/*ARGSUSED*/
-pfn_t
-sfmmu_ttetopfn(tte_t *tte, caddr_t vaddr)
-{ return(0); }
-
-#else /* lint */
-
 	ENTRY_NP(sfmmu_ttetopfn)
 	ldx	[%o0], %g1			/* read tte */
 	TTETOPFN(%g1, %o1, sfmmu_ttetopfn_l1, %g2, %g3, %g4)
@@ -1584,8 +1459,6 @@
 	mov	%g1, %o0
 	SET_SIZE(sfmmu_ttetopfn)
 
-#endif /* !lint */
-
 /*
  * These macros are used to update global sfmmu hme hash statistics
  * in perf critical paths. It is only enabled in debug kernels or
@@ -1681,36 +1554,6 @@
 #define	KPM_TLBMISS_STAT_INCR(tagacc, val, tsbma, tmp1, label)
 #endif	/* KPM_TLBMISS_STATS_GATHER */
 
-#if defined (lint)
-/*
- * The following routines are jumped to from the mmu trap handlers to do
- * the setting up to call systrap.  They are separate routines instead of
- * being part of the handlers because the handlers would exceed 32
- * instructions and since this is part of the slow path the jump
- * cost is irrelevant.
- */
-void
-sfmmu_pagefault(void)
-{
-}
-
-void
-sfmmu_mmu_trap(void)
-{
-}
-
-void
-sfmmu_window_trap(void)
-{
-}
-
-void
-sfmmu_kpm_exception(void)
-{
-}
-
-#else /* lint */
-
 #ifdef	PTL1_PANIC_DEBUG
 	.seg	".data"
 	.global	test_ptl1_panic
@@ -1960,27 +1803,6 @@
 	mov	-1, %g4
 	SET_SIZE(sfmmu_kpm_exception)
 
-#endif /* lint */
-
-#if defined (lint)
-
-void
-sfmmu_tsb_miss(void)
-{
-}
-
-void
-sfmmu_kpm_dtsb_miss(void)
-{
-}
-
-void
-sfmmu_kpm_dtsb_miss_small(void)
-{
-}
-
-#else /* lint */
-
 #if (IMAP_SEG != 0)
 #error - ism_map->ism_seg offset is not zero
 #endif
@@ -3871,30 +3693,7 @@
 	ba,pt	%icc, sfmmu_window_trap
 	  nop
 	SET_SIZE(sfmmu_tsb_miss)
-#endif  /* lint */
 
-#if defined (lint)
-/*
- * This routine will look for a user or kernel vaddr in the hash
- * structure.  It returns a valid pfn or PFN_INVALID.  It doesn't
- * grab any locks.  It should only be used by other sfmmu routines.
- */
-/* ARGSUSED */
-pfn_t
-sfmmu_vatopfn(caddr_t vaddr, sfmmu_t *sfmmup, tte_t *ttep)
-{
-	return(0);
-}
-
-/* ARGSUSED */
-pfn_t
-sfmmu_kvaszc2pfn(caddr_t vaddr, int hashno)
-{
-	return(0);
-}
-
-#else /* lint */
-
 	ENTRY_NP(sfmmu_vatopfn)
  	/*
  	 * disable interrupts
@@ -4113,12 +3912,8 @@
 
 	SET_SIZE(sfmmu_kvaszc2pfn)
 
-#endif /* lint */
 
 
-
-#if !defined(lint)
-
 /*
  * kpm lock used between trap level tsbmiss handler and kpm C level.
  */
@@ -4663,36 +4458,6 @@
 #error - KPMTSBM_SHIFT does not correspond to size of kpmtsbm struct
 #endif
 
-#endif /* lint */
-
-#ifdef	lint
-/*
- * Enable/disable tsbmiss handling at trap level for a kpm (large) page.
- * Called from C-level, sets/clears "go" indication for trap level handler.
- * khl_lock is a low level spin lock to protect the kp_tsbmtl field.
- * Assumed that &kp->kp_refcntc is checked for zero or -1 at C-level.
- * Assumes khl_mutex is held when called from C-level.
- */
-/* ARGSUSED */
-void
-sfmmu_kpm_tsbmtl(short *kp_refcntc, uint_t *khl_lock, int cmd)
-{
-}
-
-/*
- * kpm_smallpages: stores val to byte at address mapped within
- * low level lock brackets. The old value is returned.
- * Called from C-level.
- */
-/* ARGSUSED */
-int
-sfmmu_kpm_stsbmtl(uchar_t *mapped, uint_t *kshl_lock, int val)
-{
-	return (0);
-}
-
-#else /* lint */
-
 	.seg	".data"
 sfmmu_kpm_tsbmtl_panic:
 	.ascii	"sfmmu_kpm_tsbmtl: interrupts disabled"
@@ -4769,9 +4534,6 @@
 	  wrpr	%g0, %o3, %pstate		/* enable interrupts */
 	SET_SIZE(sfmmu_kpm_stsbmtl)
 
-#endif /* lint */
-
-#ifndef lint
 #ifdef sun4v
 	/*
 	 * User/kernel data miss w// multiple TSBs
@@ -4853,10 +4615,7 @@
 	SET_SIZE(sfmmu_slow_immu_miss)
 
 #endif /* sun4v */
-#endif	/* lint */
 
-#ifndef lint
-
 /*
  * Per-CPU tsbmiss areas to avoid cache misses in TSB miss handlers.
  */
@@ -4870,4 +4629,3 @@
 	.global kpmtsbm_area
 kpmtsbm_area:
 	.skip	(KPMTSBM_SIZE * NCPU)
-#endif	/* lint */
--- old/usr/src/uts/sfmmu/ml/sfmmu_kdi.s	Thu Nov 14 19:00:29 2019
+++ new/usr/src/uts/sfmmu/ml/sfmmu_kdi.s	Thu Nov 14 19:00:29 2019
@@ -24,10 +24,8 @@
  * Use is subject to license terms.
  */
 
-#if !defined(lint)
 #include <sys/asm_linkage.h>
 #include "assym.h"
-#endif
 
 #include <sys/sun4asi.h>
 #include <sys/machparam.h>
@@ -250,21 +248,6 @@
  * }
  */
 
-#if defined(lint)
-/*ARGSUSED*/
-int
-kdi_vatotte(uintptr_t va, int cnum, tte_t *ttep)
-{
-	return (0);
-}
-
-void
-kdi_trap_vatotte(void)
-{
-}
-
-#else
-
 	/*
 	 * Invocation in normal context as a VA-to-TTE translator
 	 * for kernel context only. This routine returns 0 on
@@ -343,4 +326,3 @@
 	nop
 	SET_SIZE(kdi_trap_vatotte)
 
-#endif	/* lint */
--- old/usr/src/uts/sparc/dtrace/dtrace_asm.s	Thu Nov 14 19:00:30 2019
+++ new/usr/src/uts/sparc/dtrace/dtrace_asm.s	Thu Nov 14 19:00:30 2019
@@ -23,72 +23,27 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint) || defined(__lint)
-#include <sys/dtrace_impl.h>
-#else
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
 #include <sys/fsr.h>
 #include <sys/asi.h>
 #include "assym.h"
-#endif
 
-#if defined(lint) || defined(__lint)
-
-int
-dtrace_getipl(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(dtrace_getipl)
 	retl
 	rdpr	%pil, %o0
 	SET_SIZE(dtrace_getipl)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-uint_t
-dtrace_getotherwin(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(dtrace_getotherwin)
 	retl
 	rdpr	%otherwin, %o0
 	SET_SIZE(dtrace_getotherwin)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-uint_t
-dtrace_getfprs(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(dtrace_getfprs)
 	retl
 	rd	%fprs, %o0
 	SET_SIZE(dtrace_getfprs)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-dtrace_getfsr(uint64_t *val)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(dtrace_getfsr)
 	rdpr	%pstate, %o1
 	andcc	%o1, PSTATE_PEF, %g0
@@ -105,31 +60,11 @@
 	stx	%g0, [%o0]
 	SET_SIZE(dtrace_getfsr)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-greg_t
-dtrace_getfp(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(dtrace_getfp)
 	retl
 	mov	%fp, %o0
 	SET_SIZE(dtrace_getfp)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-void
-dtrace_flush_user_windows(void)
-{}
-
-#else
-
 	ENTRY_NP(dtrace_flush_user_windows)
 	rdpr	%otherwin, %g1
 	brz	%g1, 3f
@@ -148,32 +83,6 @@
 	nop
 	SET_SIZE(dtrace_flush_user_windows)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-uint32_t
-dtrace_cas32(uint32_t *target, uint32_t cmp, uint32_t new)
-{
-	uint32_t old;
-
-	if ((old = *target) == cmp)
-		*target = new;
-	return (old);
-}
-
-void *
-dtrace_casptr(void *target, void *cmp, void *new)
-{
-	void *old;
-
-	if ((old = *(void **)target) == cmp)
-		*(void **)target = new;
-	return (old);
-}
-
-#else	/* lint */
-
 	ENTRY(dtrace_cas32)
 	cas	[%o0], %o1, %o2
 	retl
@@ -186,19 +95,6 @@
 	mov	%o2, %o0
 	SET_SIZE(dtrace_casptr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uintptr_t
-dtrace_caller(int aframes)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 	ENTRY(dtrace_caller)
 	sethi	%hi(nwin_minus_one), %g4
 	ld	[%g4 + %lo(nwin_minus_one)], %g4
@@ -233,19 +129,6 @@
 	mov	-1, %o0
 	SET_SIZE(dtrace_caller)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-dtrace_fish(int aframes, int reg, uintptr_t *regval)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 	ENTRY(dtrace_fish)
 
 	rd	%pc, %g5
@@ -311,18 +194,6 @@
 	add	%g2, 1, %o0		! Failure; return deepest frame + 1
 	SET_SIZE(dtrace_fish)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-dtrace_copyin(uintptr_t uaddr, uintptr_t kaddr, size_t size,
-    volatile uint16_t *flags)
-{}
-
-#else
-
 	ENTRY(dtrace_copyin)
 	tst	%o2
 	bz	2f
@@ -348,18 +219,6 @@
 
 	SET_SIZE(dtrace_copyin)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-dtrace_copyinstr(uintptr_t uaddr, uintptr_t kaddr, size_t size,
-    volatile  uint16_t *flags)
-{}
-
-#else
-
 	ENTRY(dtrace_copyinstr)
 	tst	%o2
 	bz	2f
@@ -388,18 +247,6 @@
 
 	SET_SIZE(dtrace_copyinstr)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-dtrace_copyout(uintptr_t kaddr, uintptr_t uaddr, size_t size,
-    volatile  uint16_t *flags)
-{}
-
-#else
-
 	ENTRY(dtrace_copyout)
 	tst	%o2
 	bz	2f
@@ -424,18 +271,6 @@
 	nop
 	SET_SIZE(dtrace_copyout)
 
-#endif
-	
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-dtrace_copyoutstr(uintptr_t kaddr, uintptr_t uaddr, size_t size,
-    volatile  uint16_t *flags)
-{}
-
-#else
-
 	ENTRY(dtrace_copyoutstr)
 	tst	%o2
 	bz	2f
@@ -463,17 +298,6 @@
 	nop
 	SET_SIZE(dtrace_copyoutstr)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uintptr_t
-dtrace_fulword(void *addr)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_fulword)
 	clr	%o1
 	ldna	[%o0]ASI_USER, %o1
@@ -481,17 +305,6 @@
 	mov	%o1, %o0
 	SET_SIZE(dtrace_fulword)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint8_t
-dtrace_fuword8(void *addr)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_fuword8)
 	clr	%o1
 	lduba	[%o0]ASI_USER, %o1
@@ -499,17 +312,6 @@
 	mov	%o1, %o0
 	SET_SIZE(dtrace_fuword8)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint16_t
-dtrace_fuword16(void *addr)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_fuword16)
 	clr	%o1
 	lduha	[%o0]ASI_USER, %o1
@@ -517,17 +319,6 @@
 	mov	%o1, %o0
 	SET_SIZE(dtrace_fuword16)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint32_t
-dtrace_fuword32(void *addr)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_fuword32)
 	clr	%o1
 	lda	[%o0]ASI_USER, %o1
@@ -535,17 +326,6 @@
 	mov	%o1, %o0
 	SET_SIZE(dtrace_fuword32)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint64_t
-dtrace_fuword64(void *addr)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_fuword64)
 	clr	%o1
 	ldxa	[%o0]ASI_USER, %o1
@@ -553,17 +333,6 @@
 	mov	%o1, %o0
 	SET_SIZE(dtrace_fuword64)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-dtrace_getupcstack_top(uint64_t *pcstack, int pcstack_limit, uintptr_t *sp)
-{ return (0); }
-
-#else
-
 	/*
 	 * %g1	pcstack
 	 * %g2	current window
@@ -628,17 +397,6 @@
 	nop
 	SET_SIZE(dtrace_getupcstack_top)
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-dtrace_getustackdepth_top(uintptr_t *sp)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_getustackdepth_top)
 	mov	%o0, %o2
 	rdpr	%otherwin, %o0
@@ -669,17 +427,6 @@
 	nop
 	SET_SIZE(dtrace_getustackdepth_top)
 
-#endif
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-ulong_t
-dtrace_getreg_win(uint_t reg, uint_t depth)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(dtrace_getreg_win)
 	sub	%o0, 16, %o0
 	cmp	%o0, 16			! %o0 must begin in the range [16..32)
@@ -735,17 +482,6 @@
 	mov	%i7, %g1
 	SET_SIZE(dtrace_getreg_win)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-dtrace_putreg_win(uint_t reg, ulong_t value)
-{}
-
-#else	/* lint */
-
 	ENTRY(dtrace_putreg_win)
 	sub	%o0, 16, %o0
 	cmp	%o0, 16			! %o0 must be in the range [16..32)
@@ -802,18 +538,6 @@
 	mov	%g1, %i7
 	SET_SIZE(dtrace_putreg_win)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-dtrace_probe_error(dtrace_state_t *state, dtrace_epid_t epid, int which,
-    int fault, int fltoffs, uintptr_t illval)
-{}
-
-#else	/* lint */
-
 	ENTRY(dtrace_probe_error)
 	save	%sp, -SA(MINFRAME), %sp
 	sethi	%hi(dtrace_probeid_error), %l0
@@ -828,4 +552,3 @@
 	restore
 	SET_SIZE(dtrace_probe_error)
 
-#endif
--- old/usr/src/uts/sparc/ml/fd_asm.s	Thu Nov 14 19:00:30 2019
+++ new/usr/src/uts/sparc/ml/fd_asm.s	Thu Nov 14 19:00:30 2019
@@ -32,18 +32,6 @@
  * dreaded "Empty translation unit"  warning.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-
-/*ARGSUSED*/
-u_int
-fd_intr(caddr_t arg)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/fdreg.h>
 #include <sys/fdvar.h>
@@ -356,4 +344,3 @@
 	nop
 
 
-#endif  /* lint */
--- old/usr/src/uts/sparc/ml/ip_ocsum.s	Thu Nov 14 19:00:30 2019
+++ new/usr/src/uts/sparc/ml/ip_ocsum.s	Thu Nov 14 19:00:30 2019
@@ -28,10 +28,6 @@
 
 #include <sys/asm_linkage.h>
 
-#if defined(lint)
-#include <sys/types.h>
-#endif	/* lint */
-
 /*
  * ip_ocsum(address, halfword_count, sum)
  * Do a 16 bit one's complement sum of a given number of (16-bit)
@@ -43,15 +39,6 @@
  *
  */
 
-#if defined(lint) 
-
-/* ARGSUSED */
-unsigned int
-ip_ocsum(u_short *address, int halfword_count, unsigned int sum)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(ip_ocsum)
 	cmp	%o1, 31		! less than 62 bytes?
 	bl,a	.dohw		!   just do halfwords
@@ -124,4 +111,3 @@
 	addxcc	%o2, 0, %o0	! add in carry if any. result in %o0
 	SET_SIZE(ip_ocsum)
 
-#endif 	/* lint */
--- old/usr/src/uts/sparc/ml/modstubs.s	Thu Nov 14 19:00:31 2019
+++ new/usr/src/uts/sparc/ml/modstubs.s	Thu Nov 14 19:00:31 2019
@@ -25,18 +25,10 @@
  * Copyright (c) 2017, Joyent, Inc. All rights reserved.
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif /* !lint */
 
 #include <sys/asm_linkage.h>
 
-#if defined(lint)
-
-char stubs_base[1], stubs_end[1];
-
-#else	/* lint */
-
 /*
  * WARNING: there is no check for forgetting to write END_MODULE,
  * and if you do, the kernel will most likely crash.  Be careful
@@ -1284,4 +1276,3 @@
 stubs_end:
 	nop
 
-#endif	/* lint */
--- old/usr/src/uts/sparc/ml/sparc_ddi.s	Thu Nov 14 19:00:31 2019
+++ new/usr/src/uts/sparc/ml/sparc_ddi.s	Thu Nov 14 19:00:31 2019
@@ -32,15 +32,6 @@
  * These routines should ONLY be ISA-dependent.
  */
 
-#if defined(lint)
-
-#include <sys/types.h>
-#include <sys/systm.h>
-#include <sys/file.h>
-#include <sys/sunddi.h>
-
-#else	/* lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/clock.h>
 #include <sys/intreg.h>
@@ -47,9 +38,7 @@
 
 #include "assym.h"		/* for FKIOCTL etc. */
 
-#endif	/* lint */
 
-
 /*
  * Layered driver routines.
  *
@@ -72,18 +61,6 @@
 	call	routine;	\
 	mov	%g1, %o7
 
-#ifdef	lint
-
-int
-ddi_copyin(const void *buf, void *kernbuf, size_t size, int flags)
-{
-	if (flags & FKIOCTL)
-		return (kcopy(buf, kernbuf, size) ? -1 : 0);
-	return (copyin(buf, kernbuf, size));
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_copyin)
 	set	FKIOCTL, %o4
 	andcc	%o3, %o4, %g0
@@ -104,20 +81,6 @@
 	restore
 	SET_SIZE(ddi_copyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-int
-ddi_copyout(const void *buf, void *kernbuf, size_t size, int flags)
-{
-	if (flags & FKIOCTL)
-		return (kcopy(buf, kernbuf, size) ? -1 : 0);
-	return (copyout(buf, kernbuf, size));
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_copyout)
 	set	FKIOCTL, %o4
 	andcc	%o3, %o4, %g0
@@ -126,24 +89,11 @@
 	/*NOTREACHED*/
 	SET_SIZE(ddi_copyout)
 
-#endif	/* lint */
-
 /*
  * DDI spine wrapper routines - here so as to not have to
  * buy register windows when climbing the device tree (which cost!)
  */
 
-#if	defined(lint)
-
-/*ARGSUSED*/
-int
-ddi_ctlops(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t op, void *a, void *v)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_ctlops)
 	tst	%o0		! dip != 0?
 	be,pn	%ncc, 2f	! nope
@@ -162,20 +112,6 @@
 	sub	%g0, 1, %o0	! return (DDI_FAILURE);
 	SET_SIZE(ddi_ctlops)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/* ARGSUSED */
-int
-ddi_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attr,
-	int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_allochdl)
 	ldn	[%o0 + DEVI_BUS_DMA_ALLOCHDL], %o0
 			! dip = (dev_info_t *)DEVI(dip)->devi_bus_dma_allochdl;
@@ -187,19 +123,6 @@
 	nop			! as if we had never been here
 	SET_SIZE(ddi_dma_allochdl)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/* ARGSUSED */
-int
-ddi_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handlep)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_freehdl)
 	ldn	[%o0 + DEVI_BUS_DMA_FREEHDL], %o0
 			! dip = (dev_info_t *)DEVI(dip)->devi_bus_dma_freehdl;
@@ -211,21 +134,6 @@
 	nop			! as if we had never been here
 	SET_SIZE(ddi_dma_freehdl)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/* ARGSUSED */
-int
-ddi_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
-	ddi_dma_handle_t handle, struct ddi_dma_req *dmareq,
-	ddi_dma_cookie_t *cp, u_int *ccountp)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_bindhdl)
 	ldn	[%o0 + DEVI_BUS_DMA_BINDHDL], %o0
 			! dip = (dev_info_t *)DEVI(dip)->devi_bus_dma_bindhdl;
@@ -237,20 +145,6 @@
 	nop			! as if we had never been here
 	SET_SIZE(ddi_dma_bindhdl)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/* ARGSUSED */
-int
-ddi_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip,
-	ddi_dma_handle_t handle)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_unbindhdl)
 	ldn	[%o0 + DEVI_BUS_DMA_UNBINDHDL], %o0
 			! dip = (dev_info_t *)DEVI(dip)->devi_bus_dma_unbindhdl;
@@ -262,21 +156,6 @@
 	nop			! as if we had never been here
 	SET_SIZE(ddi_dma_unbindhdl)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/* ARGSUSED */
-int
-ddi_dma_flush(dev_info_t *dip, dev_info_t *rdip,
-	ddi_dma_handle_t handle, off_t off, size_t len,
-	u_int cache_flags)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_flush)
 	ldn	[%o0 + DEVI_BUS_DMA_FLUSH], %o0
 			! dip = (dev_info_t *)DEVI(dip)->devi_bus_dma_flush;
@@ -288,21 +167,6 @@
 	nop			! as if we had never been here
 	SET_SIZE(ddi_dma_flush)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/* ARGSUSED */
-int
-ddi_dma_win(dev_info_t *dip, dev_info_t *rdip,
-	ddi_dma_handle_t handle, uint_t win, off_t *offp,
-	size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_win)
 	ldn	[%o0 + DEVI_BUS_DMA_WIN], %o0
 			! dip = (dev_info_t *)DEVI(dip)->devi_bus_dma_win;
@@ -314,19 +178,6 @@
 	nop			! as if we had never been here
 	SET_SIZE(ddi_dma_win)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/* ARGSUSED */
-int
-ddi_dma_sync(ddi_dma_handle_t h, off_t o, size_t l, u_int whom)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_sync)
 	ld	[%o0 + DMA_HANDLE_RFLAGS], %o4	! hp->dmai_rflags;
 	sethi	%hi(DMP_NOSYNC), %o5
@@ -351,19 +202,6 @@
 	nop			! as if we had never been here
 	SET_SIZE(ddi_dma_sync)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/* ARGSUSED */
-int
-ddi_dma_unbind_handle(ddi_dma_handle_t h)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_unbind_handle)
 	ldn	[%o0 + DMA_HANDLE_RDIP], %o1	! dip = hp->dmai_rdip;
 	mov	%o0, %o2
@@ -374,22 +212,7 @@
 		    ! hdip = (dev_info_t *)DEVI(dip)->devi_bus_dma_unbindhdl;
 	SET_SIZE(ddi_dma_unbind_handle)
 
-#endif	/* lint */
 
-
-#if	defined(lint)
-
-/*ARGSUSED*/
-int
-ddi_dma_mctl(register dev_info_t *dip, dev_info_t *rdip,
-    ddi_dma_handle_t handle, enum ddi_dma_ctlops request,
-    off_t *offp, size_t *lenp, caddr_t *objp, u_int flags)
-{
-	return (DDI_SUCCESS);
-}
-
-#else	/* lint */
-
 	ENTRY(ddi_dma_mctl)
 	ldn	[%o0 + DEVI_BUS_DMA_CTL], %o0
 			! dip = (dev_info_t *)DEVI(dip)->devi_bus_dma_ctl;
@@ -400,4 +223,3 @@
 	nop			! as if we had never been here
 	SET_SIZE(ddi_dma_mctl)
 
-#endif	/* lint */
--- old/usr/src/uts/sparc/v9/ml/crt.s	Thu Nov 14 19:00:31 2019
+++ new/usr/src/uts/sparc/v9/ml/crt.s	Thu Nov 14 19:00:31 2019
@@ -25,12 +25,6 @@
 
 #ident	"%Z%%M%	%I%	%E% SMI"	/* From SunOS 4.1 1.6 */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/regset.h>
-#include <sys/privregs.h>
-#endif  /* lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/trap.h>
 #include <sys/machtrap.h>
@@ -43,8 +37,6 @@
  *	get lint prototypes.
  */
 
-#if !defined(lint)
-
 /*
  * Structure return
  */
@@ -158,4 +150,3 @@
 	srax	%o1, 32, %o0
 	SET_SIZE(__urem64)
 
-#endif /* !lint */
--- old/usr/src/uts/sparc/v9/ml/ddi_v9_asm.s	Thu Nov 14 19:00:31 2019
+++ new/usr/src/uts/sparc/v9/ml/ddi_v9_asm.s	Thu Nov 14 19:00:32 2019
@@ -23,8 +23,6 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/asi.h>
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>
@@ -32,16 +30,8 @@
 #include <sys/ontrap.h>
 #include <sys/dditypes.h>
 
-#ifndef lint
 #include "assym.h"
-#endif
 
-#if defined(lint)
-#include <sys/isa_defs.h>
-#include <sys/types.h>
-#include <sys/sunddi.h>
-#endif  /* lint */
-
 /*
  * This file implements the following ddi common access 
  * functions:
@@ -58,493 +48,6 @@
  * accessible via ld/st instructions.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-uint8_t
-ddi_get8(ddi_acc_handle_t handle, uint8_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint8_t
-ddi_mem_get8(ddi_acc_handle_t handle, uint8_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint8_t
-ddi_io_get8(ddi_acc_handle_t handle, uint8_t *dev_addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-ddi_get16(ddi_acc_handle_t handle, uint16_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-ddi_mem_get16(ddi_acc_handle_t handle, uint16_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-ddi_io_get16(ddi_acc_handle_t handle, uint16_t *dev_addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-ddi_get32(ddi_acc_handle_t handle, uint32_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-ddi_mem_get32(ddi_acc_handle_t handle, uint32_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-ddi_io_get32(ddi_acc_handle_t handle, uint32_t *dev_addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint64_t
-ddi_get64(ddi_acc_handle_t handle, uint64_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint64_t
-ddi_mem_get64(ddi_acc_handle_t handle, uint64_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-void
-ddi_put8(ddi_acc_handle_t handle, uint8_t *addr, uint8_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_mem_put8(ddi_acc_handle_t handle, uint8_t *dev_addr, uint8_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_io_put8(ddi_acc_handle_t handle, uint8_t *dev_addr, uint8_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_put16(ddi_acc_handle_t handle, uint16_t *addr, uint16_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_mem_put16(ddi_acc_handle_t handle, uint16_t *dev_addr, uint16_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_io_put16(ddi_acc_handle_t handle, uint16_t *dev_addr, uint16_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_put32(ddi_acc_handle_t handle, uint32_t *addr, uint32_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_mem_put32(ddi_acc_handle_t handle, uint32_t *dev_addr, uint32_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_io_put32(ddi_acc_handle_t handle, uint32_t *dev_addr, uint32_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_put64(ddi_acc_handle_t handle, uint64_t *addr, uint64_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_mem_put64(ddi_acc_handle_t handle, uint64_t *dev_addr, uint64_t value) {}
-
-/*ARGSUSED*/
-void
-ddi_rep_get8(ddi_acc_handle_t handle, uint8_t *host_addr, uint8_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_rep_get16(ddi_acc_handle_t handle, uint16_t *host_addr, uint16_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_rep_get32(ddi_acc_handle_t handle, uint32_t *host_addr, uint32_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_rep_get64(ddi_acc_handle_t handle, uint64_t *host_addr, uint64_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_rep_put8(ddi_acc_handle_t handle, uint8_t *host_addr, uint8_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_rep_put16(ddi_acc_handle_t handle, uint16_t *host_addr, uint16_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_rep_put32(ddi_acc_handle_t handle, uint32_t *host_addr, uint32_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_rep_put64(ddi_acc_handle_t handle, uint64_t *host_addr, uint64_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_get8(ddi_acc_handle_t handle, uint8_t *host_addr,
-        uint8_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_get16(ddi_acc_handle_t handle, uint16_t *host_addr,
-        uint16_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_get32(ddi_acc_handle_t handle, uint32_t *host_addr,
-        uint32_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_get64(ddi_acc_handle_t handle, uint64_t *host_addr,
-        uint64_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_put8(ddi_acc_handle_t handle, uint8_t *host_addr,
-        uint8_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_put16(ddi_acc_handle_t handle, uint16_t *host_addr,
-        uint16_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_put32(ddi_acc_handle_t handle, uint32_t *host_addr,
-        uint32_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_mem_rep_put64(ddi_acc_handle_t handle, uint64_t *host_addr,
-        uint64_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-ddi_io_rep_get8(ddi_acc_handle_t handle,
-	uint8_t *host_addr, uint8_t *dev_addr, size_t repcount) {}
- 
-/*ARGSUSED*/
-void
-ddi_io_rep_get16(ddi_acc_handle_t handle,
-	uint16_t *host_addr, uint16_t *dev_addr, size_t repcount) {}
- 
-/*ARGSUSED*/
-void
-ddi_io_rep_get32(ddi_acc_handle_t handle,
-	uint32_t *host_addr, uint32_t *dev_addr, size_t repcount) {}
- 
-/*ARGSUSED*/
-void
-ddi_io_rep_put8(ddi_acc_handle_t handle,
-	uint8_t *host_addr, uint8_t *dev_addr, size_t repcount) {}
- 
-/*ARGSUSED*/
-void
-ddi_io_rep_put16(ddi_acc_handle_t handle,
-	uint16_t *host_addr, uint16_t *dev_addr, size_t repcount) {}
- 
-
-/*ARGSUSED*/
-void
-ddi_io_rep_put32(ddi_acc_handle_t handle,
-	uint32_t *host_addr, uint32_t *dev_addr, size_t repcount) {}
-
-/*ARGSUSED*/
-uint8_t
-i_ddi_get8(ddi_acc_impl_t *hdlp, uint8_t *addr) 
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-i_ddi_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-i_ddi_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint64_t
-i_ddi_get64(ddi_acc_impl_t *hdlp, uint64_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-void
-i_ddi_put8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value) {}
-
-/*ARGSUSED*/
-void
-i_ddi_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value) {}
-
-/*ARGSUSED*/
-void
-i_ddi_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value) {}
-
-/*ARGSUSED*/
-void
-i_ddi_put64(ddi_acc_impl_t *hdlp, uint64_t *addr, uint64_t value) {}
-
-/*ARGSUSED*/
-void
-i_ddi_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, uint8_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 
-	uint16_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 
-	uint32_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 
-	uint64_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, uint8_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 
-	uint16_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 
-	uint32_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 
-	uint64_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-uint8_t
-i_ddi_prot_get8(ddi_acc_impl_t *hdlp, uint8_t *addr) 
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint16_t
-i_ddi_prot_get16(ddi_acc_impl_t *hdlp, uint16_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint32_t
-i_ddi_prot_get32(ddi_acc_impl_t *hdlp, uint32_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-uint64_t
-i_ddi_prot_get64(ddi_acc_impl_t *hdlp, uint64_t *addr)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_put8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value) {}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value) {}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value) {}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_put64(ddi_acc_impl_t *hdlp, uint64_t *addr, uint64_t value) {}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, uint8_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 
-	uint16_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 
-	uint32_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 
-	uint64_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, uint8_t *dev_addr,
-        size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 
-	uint16_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 
-	uint32_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_prot_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 
-	uint64_t *dev_addr, size_t repcount, uint_t flags)
-{
-}
-
-/*ARGSUSED*/
-int
-i_ddi_ontrap(ddi_acc_handle_t handle)
-{
-	return (0);
-}
-
-/*ARGSUSED*/
-void
-i_ddi_notrap(ddi_acc_handle_t handle)
-{
-}
-
-/*ARGSUSED*/
-void
-i_ddi_caut_get(size_t getsz, void *addr, void *value)
-{
-}
-
-#else
-
 /*
  * The functionality of each of the ddi_get/put routines is performed by
  * the respective indirect function defined in the access handle.  Use of
@@ -1555,4 +1058,3 @@
 	nop
 	SET_SIZE(i_ddi_caut_get)
 
-#endif	/* lint	*/
--- old/usr/src/uts/sparc/v9/ml/float.s	Thu Nov 14 19:00:32 2019
+++ new/usr/src/uts/sparc/v9/ml/float.s	Thu Nov 14 19:00:32 2019
@@ -32,9 +32,7 @@
 #include <sys/machsig.h>
 #include <sys/machthread.h>
 
-#if !defined(lint) && !defined(__lint)
 #include "assym.h"
-#endif	/* lint */
 
 /*
  * Floating point trap handling.
@@ -81,16 +79,6 @@
  *		that appear to be a kaos bug, so don't use them!
  */
 
-#if defined(lint) || defined(__lint)
-
-#ifdef FP_DISABLED
-int fpu_exists = 0;
-#else
-int fpu_exists = 1;
-#endif
-
-#else	/* lint */
-
 	.section ".data"
 	.align	8
 fsrholder:
@@ -107,8 +95,6 @@
 	DGDEF(fpu_version)
 	.word	-1
 
-#endif	/* lint */
-
 /*
  * FPU probe - read the %fsr and get fpu_version.
  * Called from autoconf. If a %fq is created for
@@ -116,15 +102,6 @@
  * could be created by this function.
  */
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-fpu_probe(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fpu_probe)
 	wr	%g0, FPRS_FEF, %fprs	! enable fpu in fprs
 	rdpr	%pstate, %g2		! read pstate, save value in %g2
@@ -144,8 +121,6 @@
 	wr	%g0, %g0, %fprs		! disable fpu and clear fprs
 	SET_SIZE(fpu_probe)
 
-#endif	/* lint */
-
 /*
  * fp_clearregs(fp)
  *	struct v9_fpu *fp;
@@ -156,15 +131,6 @@
  * so when the return to userland is made, the fpu is enabled.
  */
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-fp_clearregs(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fp_clearregs)
 	ldx	[%o0 + FPU_FSR], %fsr		! load fsr
 
@@ -205,8 +171,6 @@
 	ldd	[%o0], %d62
 	SET_SIZE(fp_clearregs)
 
-#endif	/* lint */
-
 /*
  * void _fp_read_pfreg(pf, n)
  *	uint32_t	*pf;	Old freg value.
@@ -226,20 +190,6 @@
  * }
  */
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-_fp_read_pfreg(uint32_t *pf, u_int n)
-{}
-
-/*ARGSUSED*/
-void
-_fp_write_pfreg(uint32_t *pf, u_int n)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_read_pfreg)
 	sll	%o1, 3, %o1		! Table entries are 8 bytes each.
 	set	.stable, %g1		! g1 gets base of table.
@@ -326,8 +276,6 @@
 	SET_SIZE(_fp_read_pfreg)
 	SET_SIZE(_fp_write_pfreg)
 
-#endif	/* lint */
-
 /*
  * void _fp_read_pdreg(
  *	uint64_t	*pd,	Old dreg value.
@@ -347,20 +295,6 @@
  * }
  */
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-_fp_read_pdreg(uint64_t *pd, u_int n)
-{}
-
-/*ARGSUSED*/
-void
-_fp_write_pdreg(uint64_t *pd, u_int n)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_read_pdreg)
 	sll	%o1, 3, %o1		! Table entries are 8 bytes each.
 	set	.dstable, %g1		! g1 gets base of table.
@@ -447,79 +381,26 @@
 	SET_SIZE(_fp_read_pdreg)
 	SET_SIZE(_fp_write_pdreg)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-_fp_write_pfsr(uint64_t *fsr)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_write_pfsr)
 	retl
 	ldx	[%o0], %fsr
 	SET_SIZE(_fp_write_pfsr)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-_fp_read_pfsr(uint64_t *fsr)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_read_pfsr)
 	retl
 	stx	%fsr, [%o0]
 	SET_SIZE(_fp_read_pfsr)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-_fp_write_fprs(u_int fprs_val)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_write_fprs)
 	retl
 	wr	%o0, %g0, %fprs			! write fprs
 	SET_SIZE(_fp_write_fprs)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-unsigned
-_fp_read_fprs(void)
-{return 0;}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_read_fprs)
 	retl
 	rd	%fprs, %o0			! save fprs
 	SET_SIZE(_fp_read_fprs)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-unsigned
-_fp_subcc_ccr(void)
-{return 0;}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_subcc_ccr)
 	subcc	%o0, %o1, %g0
 	retl
@@ -526,8 +407,6 @@
 	rd	%ccr, %o0			! save ccr
 	SET_SIZE(_fp_subcc_ccr)
 
-#endif	/* lint */
-
 /*
  * Floating Point Exceptions handled according to type:
  *	2) unfinished_fpop
@@ -547,15 +426,6 @@
  * (ie, Spitfire-specific) module code before final release.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-_fp_exception(struct regs *rp, uint64_t fsr)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_exception)
 	mov	%o7, %l0		! saved return address
 	mov	%o0, %l1		! saved *rp
@@ -615,8 +485,6 @@
 	.asciz	"No floating point ftt, fsr %llx"
 #endif	/* DEBUG */
 
-#endif	/* lint */
-
 /*
  * Floating Point Exceptions.
  * handled according to type:
@@ -628,15 +496,6 @@
  * for execution of kernel code.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-_fp_ieee_exception(struct regs *rp, uint64_t fsr)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_ieee_exception)
 	mov	%o7, %l0		! saved return address
 	mov	%o0, %l1		! saved *rp
@@ -723,4 +582,3 @@
 .badfpcexcmsg:
 	.asciz	"No floating point exception, fsr %llx"
 
-#endif	/* lint */
--- old/usr/src/uts/sparc/v9/ml/lock_prim.s	Thu Nov 14 19:00:32 2019
+++ new/usr/src/uts/sparc/v9/ml/lock_prim.s	Thu Nov 14 19:00:32 2019
@@ -23,15 +23,7 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/thread.h>
-#include <sys/cpuvar.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/t_lock.h>
 #include <sys/mutex.h>
@@ -58,48 +50,15 @@
  * Store 0xFF at the specified location, and return its previous content.
  */
 
-#if defined(lint)
-uint8_t
-ldstub(uint8_t *cp)
-{
-	uint8_t	rv;
-	rv = *cp;
-	*cp = 0xFF;
-	return rv;
-}
-#else	/* lint */
-
 	ENTRY(ldstub)
 	retl
 	ldstub	[%o0], %o0
 	SET_SIZE(ldstub)
 
-#endif	/* lint */
-
 /************************************************************************
  *		MEMORY BARRIERS -- see atomic.h for full descriptions.
  */
 
-#if defined(lint)
-
-void
-membar_enter(void)
-{}
-
-void
-membar_exit(void)
-{}
-
-void
-membar_producer(void)
-{}
-
-void
-membar_consumer(void)
-{}
-
-#else	/* lint */
-
 #ifdef SF_ERRATA_51
 	.align 32
 	ENTRY(membar_return)
@@ -131,70 +90,10 @@
 	membar	#LoadLoad
 	SET_SIZE(membar_consumer)
 
-#endif	/* lint */
-
 /************************************************************************
  *		MINIMUM LOCKS
  */
 
-#if defined(lint)
-
-/*
- * lock_try(lp), ulock_try(lp)
- *	- returns non-zero on success.
- *	- doesn't block interrupts so don't use this to spin on a lock.
- *	- uses "0xFF is busy, anything else is free" model.
- *
- *      ulock_try() is for a lock in the user address space.
- *      For all V7/V8 sparc systems they are same since the kernel and
- *      user are mapped in a user' context.
- *      For V9 platforms the lock_try and ulock_try are different impl.
- */
-
-int
-lock_try(lock_t *lp)
-{
-	return (0xFF ^ ldstub(lp));
-}
-
-int
-lock_spin_try(lock_t *lp)
-{
-	return (0xFF ^ ldstub(lp));
-}
-
-void
-lock_set(lock_t *lp)
-{
-	extern void lock_set_spin(lock_t *);
-
-	if (!lock_try(lp))
-		lock_set_spin(lp);
-	membar_enter();
-}
-
-void
-lock_clear(lock_t *lp)
-{
-	membar_exit();
-	*lp = 0;
-}
-
-int
-ulock_try(lock_t *lp)
-{
-	return (0xFF ^ ldstub(lp));
-}
-
-void
-ulock_clear(lock_t *lp)
-{
-	membar_exit();
-	*lp = 0;
-}
-
-#else	/* lint */
-
 	.align	32
 	ENTRY(lock_try)
 	ldstub	[%o0], %o1		! try to set lock, get value in %o1
@@ -255,35 +154,12 @@
 	  stba	%g0, [%o0]ASI_USER	! clear lock
 	SET_SIZE(ulock_clear)
 
-#endif	/* lint */
 
-
 /*
  * lock_set_spl(lp, new_pil, *old_pil_addr)
  * 	Sets pil to new_pil, grabs lp, stores old pil in *old_pil_addr.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-lock_set_spl(lock_t *lp, int new_pil, u_short *old_pil_addr)
-{
-	extern int splr(int);
-	extern void lock_set_spl_spin(lock_t *, int, u_short *, int);
-	int old_pil;
-
-	old_pil = splr(new_pil);
-	if (!lock_try(lp)) {
-		lock_set_spl_spin(lp, new_pil, old_pil_addr, old_pil);
-	} else {
-		*old_pil_addr = (u_short)old_pil;
-		membar_enter();
-	}
-}
-
-#else	/* lint */
-
 	ENTRY(lock_set_spl)
 	rdpr	%pil, %o3			! %o3 = current pil
 	cmp	%o3, %o1			! is current pil high enough?
@@ -302,25 +178,10 @@
 	nop					! delay: do nothing
 	SET_SIZE(lock_set_spl)
 
-#endif	/* lint */
-
 /*
  * lock_clear_splx(lp, s)
  */
 
-#if defined(lint)
-
-void
-lock_clear_splx(lock_t *lp, int s)
-{
-	extern void splx(int);
-
-	lock_clear(lp);
-	splx(s);
-}
-
-#else	/* lint */
-
 	ENTRY(lock_clear_splx)
 	ldn	[THREAD_REG + T_CPU], %o2	! get CPU pointer
 	membar	#LoadStore|#StoreStore
@@ -333,8 +194,6 @@
 	wrpr	%g0, %o2, %pil
 	SET_SIZE(lock_clear_splx)
 
-#endif	/* lint */
-
 /*
  * mutex_enter() and mutex_exit().
  * 
@@ -359,29 +218,6 @@
  * patch this code in unless we're gathering ADAPTIVE_HOLD lockstats.
  */
 
-#if defined (lint)
-
-/* ARGSUSED */
-void
-mutex_enter(kmutex_t *lp)
-{}
-
-/* ARGSUSED */
-int
-mutex_tryenter(kmutex_t *lp)
-{ return (0); }
-
-/* ARGSUSED */
-void
-mutex_exit(kmutex_t *lp)
-{}
-
-/* ARGSUSED */
-void *
-mutex_owner_running(mutex_impl_t *lp)
-{ return (NULL); }
-
-#else
 	.align	32
 	ENTRY(mutex_enter)
 	mov	THREAD_REG, %o1
@@ -473,8 +309,6 @@
 	mov	%o2, %o0		! owner running, return cpu
 	SET_SIZE(mutex_owner_running)
 
-#endif	/* lint */
-
 /*
  * rw_enter() and rw_exit().
  * 
@@ -483,20 +317,7 @@
  * and rw_exit (no waiters or not the last reader).  If anything complicated
  * is going on we punt to rw_enter_sleep() and rw_exit_wakeup(), respectively.
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-rw_enter(krwlock_t *lp, krw_t rw)
-{}
-
-/* ARGSUSED */
-void
-rw_exit(krwlock_t *lp)
-{}
-
-#else
-
 	.align	16
 	ENTRY(rw_enter)
 	cmp	%o1, RW_WRITER			! entering as writer?
@@ -580,16 +401,6 @@
 	nop
 	SET_SIZE(rw_exit)
 
-#endif
-
-#if defined(lint)
-
-void
-lockstat_hot_patch(void)
-{}
-
-#else
-
 #define	RETL			0x81c3e008
 #define	NOP			0x01000000
 #define BA			0x10800000
@@ -677,8 +488,6 @@
 	restore
 	SET_SIZE(lockstat_hot_patch)
 
-#endif	/* lint */
-
 /*
  * asm_mutex_spin_enter(mutex_t *)
  *
@@ -692,7 +501,6 @@
  * 		%l7 - address of call (returns to %l7+8)
  * Uses:	%l6, %l5
  */
-#ifndef lint
 	.align 16
 	ENTRY_NP(asm_mutex_spin_enter)
 	ldstub	[%l6 + M_SPINLOCK], %l5	! try to set lock, get value in %l5
@@ -722,7 +530,6 @@
 	b	4b
 	ldub	[%l6 + M_SPINLOCK], %l5	! delay - reload lock
 	SET_SIZE(asm_mutex_spin_enter)
-#endif /* lint */
 
 /*
  * asm_mutex_spin_exit(mutex_t *)
@@ -735,13 +542,11 @@
  * 		%l7 - address of call (returns to %l7+8)
  * Uses:	none
  */
-#ifndef lint
 	ENTRY_NP(asm_mutex_spin_exit)
 	membar	#LoadStore|#StoreStore
 	jmp	%l7 + 8			! return
 	clrb	[%l6 + M_SPINLOCK]	! delay - clear lock
 	SET_SIZE(asm_mutex_spin_exit)
-#endif /* lint */
 
 /*
  * thread_onproc()
@@ -750,17 +555,7 @@
  * Since the new lock isn't held, the store ordering is important.
  * If not done in assembler, the compiler could reorder the stores.
  */
-#if defined(lint)
 
-void
-thread_onproc(kthread_id_t t, cpu_t *cp)
-{
-	t->t_state = TS_ONPROC;
-	t->t_lockp = &cp->cpu_thread_lock;
-}
-
-#else	/* lint */
-
 	ENTRY(thread_onproc)
 	set	TS_ONPROC, %o2		! TS_ONPROC state
 	st	%o2, [%o0 + T_STATE]	! store state
@@ -769,16 +564,7 @@
 	stn	%o3, [%o0 + T_LOCKP]	! delay - store new lock pointer
 	SET_SIZE(thread_onproc)
 
-#endif	/* lint */
-
 /* delay function used in some mutex code - just do 3 nop cas ops */
-#if defined(lint)
-
-/* ARGSUSED */
-void
-cas_delay(void *addr)
-{}
-#else	/* lint */
 	ENTRY(cas_delay)
 	casx [%o0], %g0, %g0
 	casx [%o0], %g0, %g0
@@ -785,19 +571,7 @@
 	retl
 	casx [%o0], %g0, %g0
 	SET_SIZE(cas_delay)
-#endif	/* lint */
 
-#if defined(lint)
-
-/*
- * alternative delay function for some niagara processors.   The rd
- * instruction uses less resources than casx on those cpus.
- */
-/* ARGSUSED */
-void
-rdccr_delay(void)
-{}
-#else	/* lint */
 	ENTRY(rdccr_delay)
 	rd	%ccr, %g0
 	rd	%ccr, %g0
@@ -804,20 +578,12 @@
 	retl
 	rd	%ccr, %g0
 	SET_SIZE(rdccr_delay)
-#endif	/* lint */
 
 /*
  * mutex_delay_default(void)
  * Spins for approx a few hundred processor cycles and returns to caller.
  */
-#if defined(lint)
 
-void
-mutex_delay_default(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(mutex_delay_default)
 	mov	72,%o0
 1:	brgz	%o0, 1b
@@ -826,4 +592,3 @@
 	nop
 	SET_SIZE(mutex_delay_default)
 
-#endif  /* lint */
--- old/usr/src/uts/sparc/v9/ml/sparcv9_subr.s	Thu Nov 14 19:00:33 2019
+++ new/usr/src/uts/sparc/v9/ml/sparcv9_subr.s	Thu Nov 14 19:00:33 2019
@@ -35,17 +35,6 @@
  * name has something to do with the routine you are moving.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/scb.h>
-#include <sys/systm.h>
-#include <sys/regset.h>
-#include <sys/sunddi.h>
-#include <sys/lockstat.h>
-#include <sys/dtrace.h>
-#include <sys/ftrace.h>
-#endif	/* lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
 #include <sys/machparam.h>	/* To get SYSBASE and PAGESIZE */
@@ -58,7 +47,6 @@
 #include <sys/machlock.h>
 #include <sys/ontrap.h>
 
-#if !defined(lint)
 #include "assym.h"
 
 	.seg	".text"
@@ -134,8 +122,6 @@
 	retl;								\
 	mov	%o1, %o0		/* return old PIL */
 
-#endif	/* lint */
-
 	/*
 	 * Berkley 4.3 introduced symbolically named interrupt levels
 	 * as a way deal with priority in a machine independent fashion.
@@ -178,18 +164,6 @@
 	 *	spl0()		Used to lower priority to 0.
 	 */
 
-#if defined(lint)
-
-int spl0(void)		{ return (0); }
-int spl6(void)		{ return (0); }
-int spl7(void)		{ return (0); }
-int spl8(void)		{ return (0); }
-int splhi(void)		{ return (0); }
-int splhigh(void)	{ return (0); }
-int splzs(void)		{ return (0); }
-
-#else	/* lint */
-
 	/* locks out all interrupts, including memory errors */
 	ENTRY(spl8)
 	SETPRI_HIGH(15)
@@ -224,22 +198,11 @@
 	SETPRI(0)
 	SET_SIZE(spl0)
 
-#endif	/* lint */
-
 /*
  * splx - set PIL back to that indicated by the old %pil passed as an argument,
  * or to the CPU's base priority, whichever is higher.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-splx(int level)
-{}
-
-#else	/* lint */
-
 	ENTRY(splx)
 	ALTENTRY(i_ddi_splx)
 	SETPRI(%o0)		/* set PIL */
@@ -246,8 +209,6 @@
 	SET_SIZE(i_ddi_splx)
 	SET_SIZE(splx)
 
-#endif	/* level */
-
 /*
  * splr()
  *
@@ -258,20 +219,10 @@
  * look at CPU->cpu_base_pri.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-splr(int level)
-{ return (0); }
-
-#else	/* lint */
 	ENTRY(splr)
 	RAISE(%o0)
 	SET_SIZE(splr)
 
-#endif	/* lint */
-
 /*
  * on_fault()
  * Catch lofault faults. Like setjmp except it returns one
@@ -279,15 +230,6 @@
  * by calling no_fault().
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-on_fault(label_t *ljb)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(on_fault)
 	membar	#Sync			! sync error barrier (see copy.s)
 	stn	%o0, [THREAD_REG + T_ONFAULT]
@@ -304,21 +246,11 @@
 	stn	%g0, [THREAD_REG + T_LOFAULT]	! turn off lofault
 	SET_SIZE(on_fault)
 
-#endif	/* lint */
-
 /*
  * no_fault()
  * turn off fault catching.
  */
 
-#if defined(lint)
-
-void
-no_fault(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(no_fault)
 	membar	#Sync				! sync error barrier
 	stn	%g0, [THREAD_REG + T_ONFAULT]
@@ -326,8 +258,6 @@
 	stn	%g0, [THREAD_REG + T_LOFAULT]	! turn off lofault
 	SET_SIZE(no_fault)
 
-#endif	/* lint */
-
 /*
  * Default trampoline code for on_trap() (see <sys/ontrap.h>).  On sparcv9,
  * the trap code will complete trap processing but reset the return %pc to
@@ -334,14 +264,7 @@
  * ot_trampoline, which will by default be set to the address of this code.
  * We longjmp(&curthread->t_ontrap->ot_jmpbuf) to return back to on_trap().
  */
-#if defined(lint)
 
-void 
-on_trap_trampoline(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(on_trap_trampoline)
 	ldn	[THREAD_REG + T_ONTRAP], %o0    
 	b	longjmp                 
@@ -348,8 +271,6 @@
 	add	%o0, OT_JMPBUF, %o0
 	SET_SIZE(on_trap_trampoline)
 
-#endif	/* lint */
-
 /*
  * Push a new element on to the t_ontrap stack.  Refer to <sys/ontrap.h> for
  * more information about the on_trap() mechanism.  If the on_trap_data is the
@@ -359,15 +280,7 @@
  * we go any further.  We want these errors to be processed before we modify
  * our current error protection.
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-int
-on_trap(on_trap_data_t *otp, uint_t prot)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(on_trap)
 	membar	#Sync				! force error barrier
 	sth	%o1, [%o0 + OT_PROT]		! ot_prot = prot
@@ -388,22 +301,11 @@
 	add	%o0, OT_JMPBUF, %o0		! %o0 = &ot_jmpbuf
 	SET_SIZE(on_trap)
 
-#endif	/* lint */
-
 /*
  * Setjmp and longjmp implement non-local gotos using state vectors
  * type label_t.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-setjmp(label_t *lp)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(setjmp)
 	stn	%o7, [%o0 + L_PC]	! save return address
 	stn	%sp, [%o0 + L_SP]	! save stack ptr
@@ -411,18 +313,7 @@
 	clr	%o0			! return 0
 	SET_SIZE(setjmp)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-longjmp(label_t *lp)
-{}
-
-#else	/* lint */
-
 	ENTRY(longjmp)
 	!
         ! The following save is required so that an extra register
@@ -442,8 +333,6 @@
 	restore	%g0, 1, %o0		! takes underflow, switches stacks
 	SET_SIZE(longjmp)
 
-#endif	/* lint */
-
 /*
  * movtuc(length, from, to, table)
  *
@@ -450,15 +339,6 @@
  * VAX movtuc instruction (sort of).
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-movtuc(size_t length, u_char *from, u_char *to, u_char table[])
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(movtuc)
 	tst     %o0
 	ble,pn	%ncc, 2f		! check length
@@ -483,8 +363,6 @@
 	mov     %o4, %o0
 	SET_SIZE(movtuc)
 
-#endif	/* lint */
-
 /*
  * scanc(length, string, table, mask)
  *
@@ -491,15 +369,6 @@
  * VAX scanc instruction.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-scanc(size_t length, u_char *string, u_char table[], u_char mask)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(scanc)
 	tst	%o0	
 	ble,pn	%ncc, 1f		! check length
@@ -517,86 +386,44 @@
 	sub	%o0, %o4, %o0
 	SET_SIZE(scanc)
 
-#endif	/* lint */
-
 /*
  * if a() calls b() calls caller(),
  * caller() returns return address in a().
  */
 
-#if defined(lint)
-
-caddr_t
-caller(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(caller)
 	retl
 	mov	%i7, %o0
 	SET_SIZE(caller)
 
-#endif	/* lint */
-
 /*
  * if a() calls callee(), callee() returns the
  * return address in a();
  */
 
-#if defined(lint)
-
-caddr_t
-callee(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(callee)
 	retl
 	mov	%o7, %o0
 	SET_SIZE(callee)
 
-#endif	/* lint */
-
 /*
  * return the current frame pointer
  */
 
-#if defined(lint)
-
-greg_t
-getfp(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(getfp)
 	retl
 	mov	%fp, %o0
 	SET_SIZE(getfp)
 
-#endif	/* lint */
-
 /*
  * Get vector base register
  */
 
-#if defined(lint)
-
-greg_t
-gettbr(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(gettbr)
 	retl
 	mov     %tbr, %o0
 	SET_SIZE(gettbr)
 
-#endif	/* lint */
-
 /*
  * Get processor state register, V9 faked to look like V8.
  * Note: does not provide ccr.xcc and provides FPRS.FEF instead of
@@ -604,14 +431,6 @@
  * libc_psr memcpy routines to run without hitting the fp_disabled trap.
  */
 
-#if defined(lint)
-
-greg_t
-getpsr(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(getpsr)
 	rd	%ccr, %o1			! get ccr
         sll	%o1, PSR_ICC_SHIFT, %o0		! move icc to V8 psr.icc
@@ -624,44 +443,21 @@
         or	%o0, %o1, %o0			! or into psr.impl/ver
 	SET_SIZE(getpsr)
 
-#endif	/* lint */
-
 /*
  * Get current processor interrupt level
  */
 
-#if defined(lint)
-
-u_int
-getpil(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(getpil)
 	retl
 	rdpr	%pil, %o0
 	SET_SIZE(getpil)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-setpil(u_int pil)
-{}
-
-#else	/* lint */
-
 	ENTRY(setpil)
 	retl
 	wrpr	%g0, %o0, %pil
 	SET_SIZE(setpil)
 
-#endif	/* lint */
 
-
 /*
  * _insque(entryp, predp)
  *
@@ -668,15 +464,6 @@
  * Insert entryp after predp in a doubly linked list.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-_insque(caddr_t entryp, caddr_t predp)
-{}
-
-#else	/* lint */
-
 	ENTRY(_insque)
 	ldn	[%o1], %g1		! predp->forw
 	stn	%o1, [%o0 + CPTRSIZE]	! entryp->back = predp
@@ -686,8 +473,6 @@
 	stn	%o0, [%g1 + CPTRSIZE]	! predp->forw->back = entryp
 	SET_SIZE(_insque)
 
-#endif	/* lint */
-
 /*
  * _remque(entryp)
  *
@@ -694,15 +479,6 @@
  * Remove entryp from a doubly linked list
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-_remque(caddr_t entryp)
-{}
-
-#else	/* lint */
-
 	ENTRY(_remque)
 	ldn	[%o0], %g1		! entryp->forw
 	ldn	[%o0 + CPTRSIZE], %g2	! entryp->back
@@ -711,9 +487,7 @@
 	stn	%g2, [%g1 + CPTRSIZE]	! entryp->forw->back = entryp->back
 	SET_SIZE(_remque)
 
-#endif	/* lint */
 
-
 /*
  * strlen(str)
  *
@@ -723,15 +497,6 @@
  *	  why does it have local labels which don't start with a `.'?
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-size_t
-strlen(const char *str)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(strlen)
 	mov	%o0, %o1
 	andcc	%o1, 3, %o3		! is src word aligned
@@ -816,91 +581,10 @@
 	inc	3, %o0
 	SET_SIZE(strlen)
 
-#endif	/* lint */
-
 /*
  * Provide a C callable interface to the membar instruction.
  */
 
-#if defined(lint)
-
-void
-membar_ldld(void)
-{}
-
-void
-membar_stld(void)
-{}
-
-void
-membar_ldst(void)
-{}
-
-void
-membar_stst(void)
-{}
-
-void
-membar_ldld_ldst(void)
-{}
-
-void
-membar_ldld_stld(void)
-{}
-
-void
-membar_ldld_stst(void)
-{}
-
-void
-membar_stld_ldld(void)
-{}
-
-void
-membar_stld_ldst(void)
-{}
-
-void
-membar_stld_stst(void)
-{}
-
-void
-membar_ldst_ldld(void)
-{}
-
-void
-membar_ldst_stld(void)
-{}
-
-void
-membar_ldst_stst(void)
-{}
-
-void
-membar_stst_ldld(void)
-{}
-
-void
-membar_stst_stld(void)
-{}
-
-void
-membar_stst_ldst(void)
-{}
-
-void
-membar_lookaside(void)
-{}
-
-void
-membar_memissue(void)
-{}
-
-void
-membar_sync(void)
-{}
-
-#else
 	ENTRY(membar_ldld)
 	retl
 	membar	#LoadLoad
@@ -978,43 +662,7 @@
 	membar	#Sync
 	SET_SIZE(membar_sync)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-fuword64(const void *addr, uint64_t *dst)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-fuword32(const void *addr, uint32_t *dst)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-fuword16(const void *addr, uint16_t *dst)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-fuword8(const void *addr, uint8_t *dst)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-dtrace_ft_fuword64(const void *addr, uint64_t *dst)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-dtrace_ft_fuword32(const void *addr, uint32_t *dst)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * Since all of the fuword() variants are so similar, we have a macro to spit
  * them out.
@@ -1052,33 +700,7 @@
 	FUWORD(fuword16, lduha, sth, CP_FUWORD16)
 	FUWORD(fuword8, lduba, stb, CP_FUWORD8)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-suword64(void *addr, uint64_t value)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-suword32(void *addr, uint32_t value)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-suword16(void *addr, uint16_t value)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-suword8(void *addr, uint8_t value)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * Since all of the suword() variants are so similar, we have a macro to spit
  * them out.
@@ -1115,32 +737,6 @@
 	SUWORD(suword16, stha, CP_SUWORD16)
 	SUWORD(suword8, stba, CP_SUWORD8)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-fuword8_noerr(const void *addr, uint8_t *dst)
-{}
-
-/*ARGSUSED*/
-void
-fuword16_noerr(const void *addr, uint16_t *dst)
-{}
-
-/*ARGSUSED*/
-void
-fuword32_noerr(const void *addr, uint32_t *dst)
-{}
-
-/*ARGSUSED*/
-void
-fuword64_noerr(const void *addr, uint64_t *dst)
-{}
-
-#else	/* lint */
-
 	ENTRY(fuword8_noerr)
 	lduba	[%o0]ASI_USER, %o0	
 	retl
@@ -1165,32 +761,6 @@
 	stx	%o0, [%o1]
 	SET_SIZE(fuword64_noerr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-suword8_noerr(void *addr, uint8_t value)
-{}
-
-/*ARGSUSED*/
-void
-suword16_noerr(void *addr, uint16_t value)
-{}
-
-/*ARGSUSED*/
-void
-suword32_noerr(void *addr, uint32_t value)
-{}
-
-/*ARGSUSED*/
-void
-suword64_noerr(void *addr, uint64_t value)
-{}
-
-#else	/* lint */
-
 	ENTRY(suword8_noerr)
 	retl
 	stba	%o1, [%o0]ASI_USER
@@ -1211,42 +781,6 @@
 	stxa	%o1, [%o0]ASI_USER
 	SET_SIZE(suword64_noerr)
 
-#endif	/* lint */
-
-#if defined(__lint)
-
-/*ARGSUSED*/
-int
-subyte(void *addr, uchar_t value)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-subyte_noerr(void *addr, uchar_t value)
-{}
-
-/*ARGSUSED*/
-int
-fulword(const void *addr, ulong_t *valuep)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-fulword_noerr(const void *addr, ulong_t *valuep)
-{}
-
-/*ARGSUSED*/
-int
-sulword(void *addr, ulong_t valuep)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-sulword_noerr(void *addr, ulong_t valuep)
-{}
-
-#else
-
 	.weak	subyte
 	subyte=suword8
 	.weak	subyte_noerr
@@ -1271,8 +805,6 @@
 	sulword_noerr=suword32_noerr
 #endif	/* LP64 */
 
-#endif	/* lint */
-
 /*
  * We define rdtick here, but not for sun4v. On sun4v systems, the %tick
  * and %stick should not be read directly without considering the tick
@@ -1281,35 +813,17 @@
  */
 #if !defined (sun4v)
 
-#if defined (lint)
-
-hrtime_t
-rdtick()
-{ return (0); }
-
-#else /* lint */
-
 	ENTRY(rdtick)
 	retl
 	rd	%tick, %o0
         SET_SIZE(rdtick)
 
-#endif /* lint */
-
 #endif /* !sun4v */
 
 /*
  * Set tba to given address, no side effects.
  */
-#if defined (lint)
 
-/*ARGSUSED*/
-void *
-set_tba(void *new_tba)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(set_tba)
 	mov	%o0, %o1
 	rdpr	%tba, %o0
@@ -1318,63 +832,21 @@
 	nop
 	SET_SIZE(set_tba)
 
-#endif	/* lint */
-
-#if defined (lint)
-
-/*ARGSUSED*/
-void *
-get_tba()
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(get_tba)
 	retl
 	rdpr	%tba, %o0
 	SET_SIZE(get_tba)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-setpstate(u_int pstate)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(setpstate)
 	retl
 	wrpr	%g0, %o0, %pstate
 	SET_SIZE(setpstate)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-u_int
-getpstate(void)
-{ return(0); }
-
-#else	/* lint */
-
 	ENTRY_NP(getpstate)
 	retl
 	rdpr	%pstate, %o0
 	SET_SIZE(getpstate)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-dtrace_icookie_t
-dtrace_interrupt_disable(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(dtrace_interrupt_disable)
 	rdpr	%pstate, %o0
 	andn	%o0, PSTATE_IE, %o1
@@ -1382,36 +854,11 @@
 	wrpr	%g0, %o1, %pstate
 	SET_SIZE(dtrace_interrupt_disable)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-dtrace_interrupt_enable(dtrace_icookie_t cookie)
-{}
-
-#else
-
 	ENTRY_NP(dtrace_interrupt_enable)
 	retl
 	wrpr	%g0, %o0, %pstate 
 	SET_SIZE(dtrace_interrupt_enable)
 
-#endif /* lint*/
-
-#if defined(lint)
-
-void
-dtrace_membar_producer(void)
-{}
-
-void
-dtrace_membar_consumer(void)
-{}
-
-#else	/* lint */
-
 #ifdef SF_ERRATA_51
 	.align 32
 	ENTRY(dtrace_membar_return)
@@ -1433,34 +880,11 @@
 	membar	#LoadLoad
 	SET_SIZE(dtrace_membar_consumer)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-void
-dtrace_flush_windows(void)
-{}
-
-#else
-
 	ENTRY_NP(dtrace_flush_windows)
 	retl
 	flushw
 	SET_SIZE(dtrace_flush_windows)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-getpcstack_top(pc_t *pcstack, int limit, uintptr_t *lastfp, pc_t *lastpc)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 	/*
 	 * %g1	pcstack
 	 * %g2	iteration count
@@ -1531,41 +955,18 @@
 	ldn	[%fp + STACK_BIAS + 15*CLONGSIZE], %g4	! and pc
 	SET_SIZE(getpcstack_top)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-setwstate(u_int wstate)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(setwstate)
 	retl
 	wrpr	%g0, %o0, %wstate
 	SET_SIZE(setwstate)
 
-#endif	/* lint */
 
-
-#if defined(lint) || defined(__lint)
-
-u_int
-getwstate(void)
-{ return(0); }
-
-#else	/* lint */
-
 	ENTRY_NP(getwstate)
 	retl
 	rdpr	%wstate, %o0
 	SET_SIZE(getwstate)
 
-#endif	/* lint */
 
-
 /*
  * int panic_trigger(int *tp)
  *
@@ -1576,16 +977,7 @@
  * partially corrupt trigger to still trigger correctly.  DTrace has its own
  * version of this function to allow it to panic correctly from probe context.
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-int panic_trigger(int *tp) { return (0); }
-
-/*ARGSUSED*/
-int dtrace_panic_trigger(int *tp) { return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(panic_trigger)
 	ldstub	[%o0], %o0		! store 0xFF, load byte into %o0
 	cmp	%o0, 0xFF		! compare %o0 to 0xFF
@@ -1606,8 +998,6 @@
 	mov	%o1, %o0		! return (%o1);
 	SET_SIZE(dtrace_panic_trigger)
 
-#endif	/* lint */
-
 /*
  * void vpanic(const char *format, va_list alist)
  *
@@ -1624,16 +1014,7 @@
  * sets up the initial stack as vpanic does, calls dtrace_panic_trigger(), and
  * branches back into vpanic().
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-void vpanic(const char *format, va_list alist) {}
-
-/*ARGSUSED*/
-void dtrace_vpanic(const char *format, va_list alist) {}
-
-#else	/* lint */
-
 	ENTRY_NP(vpanic)
 
 	save	%sp, -SA(MINFRAME + REGSIZE), %sp	! save and allocate regs
@@ -1761,18 +1142,6 @@
 	ba,a	vpanic_common
 	SET_SIZE(dtrace_vpanic)
 	
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-
-uint_t
-get_subcc_ccr( uint64_t addrl, uint64_t addrr)
-{ return (0); }
-
-#else   /* lint */
-
 	ENTRY(get_subcc_ccr)
 	wr	%g0, %ccr	! clear condition codes
 	subcc	%o0, %o1, %g0
@@ -1780,16 +1149,6 @@
 	rd	%ccr, %o0	! return condition codes
 	SET_SIZE(get_subcc_ccr)
 
-#endif  /* lint */
-
-#if defined(lint) || defined(__lint)
-
-ftrace_icookie_t
-ftrace_interrupt_disable(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(ftrace_interrupt_disable)
 	rdpr	%pstate, %o0
 	andn	%o0, PSTATE_IE, %o1
@@ -1797,20 +1156,8 @@
 	wrpr	%g0, %o1, %pstate
 	SET_SIZE(ftrace_interrupt_disable)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-ftrace_interrupt_enable(ftrace_icookie_t cookie)
-{}
-
-#else
-
 	ENTRY_NP(ftrace_interrupt_enable)
 	retl
 	wrpr	%g0, %o0, %pstate 
 	SET_SIZE(ftrace_interrupt_enable)
 
-#endif /* lint*/
--- old/usr/src/uts/sparc/v9/ml/syscall_trap.s	Thu Nov 14 19:00:33 2019
+++ new/usr/src/uts/sparc/v9/ml/syscall_trap.s	Thu Nov 14 19:00:33 2019
@@ -35,23 +35,12 @@
 #include <sys/pcb.h>
 #include <sys/machparam.h>
 
-#if !defined(lint) && !defined(__lint)
 #include "assym.h"
-#endif
 
 #ifdef TRAPTRACE
 #include <sys/traptrace.h>
 #endif /* TRAPTRACE */
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-void
-syscall_trap(struct regs *rp)	/* for tags only; not called from C */
-{}
-
-#else /* lint */
-
 #if (1 << SYSENT_SHIFT) != SYSENT_SIZE
 #error	"SYSENT_SHIFT does not correspond to size of sysent structure"
 #endif
@@ -290,16 +279,7 @@
 	jmp	%l0 + 8				! return to user_rtt
 	nop
 	SET_SIZE(syscall_trap)
-#endif	/* lint */
 
-#if defined(lint) || defined(__lint)
-
-void
-syscall_trap32(void)	/* for tags only - trap handler - not called from C */
-{}
-
-#else /* lint */
-
 /*
  * System call trap handler for ILP32 processes.
  *
@@ -550,9 +530,7 @@
 	nop
 	SET_SIZE(syscall_trap32)
 
-#endif /* lint */
 
-
 /*
  * lwp_rtt - start execution in newly created LWP.
  *	Here with t_post_sys set by lwp_create, and lwp_eosys == JUSTRETURN,
@@ -560,17 +538,6 @@
  *	simply be restored.
  *	This must go out through sys_rtt instead of syscall_rtt.
  */
-#if defined(lint) || defined(__lint)
-
-void
-lwp_rtt_initial(void)
-{}
-
-void
-lwp_rtt(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(lwp_rtt_initial)
 	ldn	[THREAD_REG + T_STACK], %l7
 	call	__dtrace_probe___proc_start
@@ -592,4 +559,3 @@
 	SET_SIZE(lwp_rtt)
 	SET_SIZE(lwp_rtt_initial)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4/brand/common/brand_solaris.s	Thu Nov 14 19:00:33 2019
+++ new/usr/src/uts/sun4/brand/common/brand_solaris.s	Thu Nov 14 19:00:33 2019
@@ -31,22 +31,6 @@
  * use brand-specific #defines to replace the XXX_brand_... definitions.
  */ 
 
-#ifdef lint
-
-#include <sys/systm.h>
-
-void
-XXX_brand_syscall32_callback(void)
-{
-}
-
-void
-XXX_brand_syscall_callback(void)
-{
-}
-
-#else   /* !lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>
 #include <sys/privregs.h>
@@ -299,4 +283,3 @@
 SET_SIZE(XXX_brand_syscall_callback_common)
 
 #endif	/* _ASM */
-#endif	/* !lint */
--- old/usr/src/uts/sun4/conf/genalign.s	Thu Nov 14 19:00:34 2019
+++ new/usr/src/uts/sun4/conf/genalign.s	Thu Nov 14 19:00:34 2019
@@ -24,14 +24,6 @@
  * All rights reserved.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-
-/*LINTED: empty translation unit*/
-
-#else
-
 #include "assym.h"
 #include <sys/machparam.h>
 
@@ -56,4 +48,3 @@
 .desc_end:
 	.align		4
 
-#endif /* !lint */
--- old/usr/src/uts/sun4/ml/copy.s	Thu Nov 14 19:00:34 2019
+++ new/usr/src/uts/sun4/ml/copy.s	Thu Nov 14 19:00:34 2019
@@ -23,8 +23,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/param.h>
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
@@ -35,9 +33,7 @@
 #include <sys/fsr.h>
 #include <sys/privregs.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 /*
  * Error barrier:
@@ -60,15 +56,6 @@
  *	u_int maxlength, *lencopied;
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-copystr(const char *from, char *to, size_t maxlength, size_t *lencopied)
-{ return(0); }
-
-#else	/* lint */
-
 	ENTRY(copystr)
 	orcc	%o2, %g0, %o4		! save original count
 	bg,a	%ncc, 1f
@@ -113,23 +100,12 @@
 	nop
 	SET_SIZE(copystr)
 
-#endif	/* lint */
 
-
 /*
  * Copy a null terminated string from the user address space into
  * the kernel address space.
  */
-#if defined(lint)
 
-/* ARGSUSED */
-int
-copyinstr(const char *uaddr, char *kaddr, size_t maxlength,
-    size_t *lencopied)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyinstr)
 	sethi	%hi(.copyinstr_err), %o4
 	ldn	[THREAD_REG + T_LOFAULT], %o5	! catch faults
@@ -194,18 +170,7 @@
 	retl
 	stn	%o5, [THREAD_REG + T_LOFAULT]	! stop catching faults
 	SET_SIZE(copyinstr)
-#endif
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-copyinstr_noerr(const char *uaddr, char *kaddr, size_t maxlength,
-    size_t *lencopied)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyinstr_noerr)
 	mov	%o2, %o4		! save original count
 
@@ -247,23 +212,11 @@
 	nop
 	SET_SIZE(copyinstr_noerr)
 
-#endif	/* lint */
-
 /*
  * Copy a null terminated string from the kernel
  * address space to the user address space.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-copyoutstr(const char *kaddr, char *uaddr, size_t maxlength,
-    size_t *lencopied)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyoutstr)
 	sethi	%hi(.copyoutstr_err), %o5
 	ldn	[THREAD_REG + T_LOFAULT], %o4	! catch faults
@@ -330,18 +283,6 @@
 	stn	%o5, [THREAD_REG + T_LOFAULT]	! stop catching faults
 	SET_SIZE(copyoutstr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-int
-copyoutstr_noerr(const char *kaddr, char *uaddr, size_t maxlength,
-    size_t *lencopied)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyoutstr_noerr)
 	mov	%o2, %o4		! save original count
 
@@ -382,9 +323,7 @@
 	nop
 	SET_SIZE(copyoutstr_noerr)
 
-#endif	/* lint */
 
-
 /*
  * Copy a block of storage.  If the source and target regions overlap,
  * one or both of the regions will be silently corrupted.
@@ -391,15 +330,6 @@
  * No fault handler installed (to be called under on_fault())
  */
 
-#if defined(lint)
- 
-/* ARGSUSED */
-void
-ucopy(const void *ufrom, void *uto, size_t ulength)
-{}
- 
-#else /* lint */
- 
 	ENTRY(ucopy)
 	save	%sp, -SA(MINFRAME), %sp ! get another window
 
@@ -417,7 +347,6 @@
 	restore %g0, 0, %o0		! return (0)
 
 	SET_SIZE(ucopy)
-#endif /* lint */
 
 /*
  * Copy a user-land string.  If the source and target regions overlap,
@@ -425,15 +354,6 @@
  * No fault handler installed (to be called under on_fault())
  */
 
-#if defined(lint)
- 
-/* ARGSUSED */
-void
-ucopystr(const char *ufrom, char *uto, size_t umaxlength, size_t *ulencopied)
-{}
- 
-#else /* lint */
- 
 	ENTRY(ucopystr)
 	save	%sp, -SA(MINFRAME), %sp ! get another window
 
@@ -455,4 +375,3 @@
 	restore %g0, 0, %o0		! return (0)
 
 	SET_SIZE(ucopystr)
-#endif /* lint */
--- old/usr/src/uts/sun4/ml/cpc_hwreg.s	Thu Nov 14 19:00:34 2019
+++ new/usr/src/uts/sun4/ml/cpc_hwreg.s	Thu Nov 14 19:00:34 2019
@@ -30,31 +30,6 @@
 
 #include <sys/asm_linkage.h>
 
-#if defined(lint) || defined(__lint)
-
-#include <sys/cpc_ultra.h>
-
-/*ARGSUSED*/
-void
-ultra_setpcr(uint64_t pcr)
-{}
-
-/*ARGSUSED*/
-uint64_t
-ultra_getpcr(void)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-ultra_setpic(uint64_t pic)
-{}
-
-uint64_t
-ultra_getpic(void)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	ENTRY(ultra_setpcr)
 	retl
 	wr	%o0, %pcr
@@ -85,4 +60,3 @@
 	rd	%pic, %o0
 	SET_SIZE(ultra_getpic)
 
-#endif	/* lint || __lint */
--- old/usr/src/uts/sun4/ml/interrupt.s	Thu Nov 14 19:00:35 2019
+++ new/usr/src/uts/sun4/ml/interrupt.s	Thu Nov 14 19:00:35 2019
@@ -22,12 +22,7 @@
  * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/thread.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/cmn_err.h>
 #include <sys/ftrace.h>
@@ -41,16 +36,7 @@
 #include <sys/traptrace.h>
 #endif /* TRAPTRACE */
 
-#if defined(lint)
 
-/* ARGSUSED */
-void
-pil_interrupt(int level)
-{}
-
-#else	/* lint */
-
-
 /*
  * (TT 0x40..0x4F, TL>0) Interrupt Level N Handler (N == 1..15)
  * 	Register passed from LEVEL_INTERRUPT(level)
@@ -160,10 +146,7 @@
 	SET_SIZE(pil_interrupt_common)
 	SET_SIZE(pil_interrupt)
 
-#endif	/* lint */
 
-
-#ifndef	lint
 _spurious:
 	.asciz	"!interrupt 0x%x at level %d not serviced"
 
@@ -329,17 +312,6 @@
 #define SERVE_INTR_TRACE2(inum, os1, os2, os3, os4)
 #endif	/* TRAPTRACE */
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-intr_thread(struct regs *regs, uint64_t iv_p, uint_t pil)
-{}
-
-#else	/* lint */
-
 #define	INTRCNT_LIMIT 16
 
 /*
@@ -892,39 +864,7 @@
 intr_thread_t_intr_start_zero:
 	.asciz	"intr_thread():	t_intr_start zero upon handler return"
 #endif /* DEBUG */
-#endif	/* lint */
 
-#if defined(lint)
-
-/*
- * Handle an interrupt in the current thread
- *	Entry:
- *		%o0       = pointer to regs structure
- *		%o1       = pointer to current intr_vec_t (iv) to be processed
- *		%o2       = pil
- *		%sp       = on current thread's kernel stack
- *		%o7       = return linkage to trap code
- *		%g7       = current thread
- *		%pstate   = normal globals, interrupts enabled, 
- *		            privileged, fp disabled
- *		%pil      = PIL_MAX
- *
- *	Register Usage
- *		%l0       = return linkage
- *		%l1       = old stack
- *		%l2 - %l3 = scratch
- *		%l4 - %l7 = reserved for sys_trap
- *		%o3       = cpu
- *		%o0       = scratch
- *		%o4 - %o5 = scratch
- */
-/* ARGSUSED */
-void
-current_thread(struct regs *regs, uint64_t iv_p, uint_t pil)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(current_thread)
 	
 	mov	%o7, %l0
@@ -1398,7 +1338,6 @@
 current_thread_nested_PIL_not_found:
 	.asciz	"current_thread: couldn't find nested high-level PIL"
 #endif /* DEBUG */
-#endif /* lint */
 
 /*
  * Return a thread's interrupt level.
@@ -1412,31 +1351,11 @@
  *	kthread_id_t	t;
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-intr_level(kthread_id_t t)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(intr_level)
 	retl
 	ldub	[%o0 + T_PIL], %o0		! return saved pil
 	SET_SIZE(intr_level)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-int
-disable_pil_intr()
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(disable_pil_intr)
 	rdpr	%pil, %o0
 	retl
@@ -1443,33 +1362,11 @@
 	wrpr	%g0, PIL_MAX, %pil		! disable interrupts (1-15)
 	SET_SIZE(disable_pil_intr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-enable_pil_intr(int pil_save)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(enable_pil_intr)
 	retl
 	wrpr	%o0, %pil
 	SET_SIZE(enable_pil_intr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-uint_t
-disable_vec_intr(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(disable_vec_intr)
 	rdpr	%pstate, %o0
 	andn	%o0, PSTATE_IE, %g1
@@ -1477,32 +1374,11 @@
 	wrpr	%g0, %g1, %pstate		! disable interrupt
 	SET_SIZE(disable_vec_intr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-enable_vec_intr(uint_t pstate_save)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(enable_vec_intr)
 	retl
 	wrpr	%g0, %o0, %pstate
 	SET_SIZE(enable_vec_intr)
 
-#endif	/* lint */
-
-#if defined(lint)
- 
-void
-cbe_level14(void)
-{}
-
-#else   /* lint */
-
 	ENTRY_NP(cbe_level14)
 	save    %sp, -SA(MINFRAME), %sp ! get a new window
 	!
@@ -1522,18 +1398,7 @@
 	restore	%g0, 1, %o0
 	SET_SIZE(cbe_level14)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-kdi_setsoftint(uint64_t iv_p)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(kdi_setsoftint)
 	save	%sp, -SA(MINFRAME), %sp	! get a new window 
 	rdpr	%pstate, %l5
@@ -1607,17 +1472,6 @@
 	restore
 	SET_SIZE(kdi_setsoftint)
 	
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-setsoftint_tl1(uint64_t iv_p, uint64_t dummy)
-{}
-
-#else	/* lint */
-
 	!
 	! Register usage
 	!	Arguments:
@@ -1702,17 +1556,6 @@
 	retry
 	SET_SIZE(setsoftint_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-setvecint_tl1(uint64_t inum, uint64_t dummy)
-{}
-
-#else	/* lint */
-
 	!
 	! Register usage
 	!	Arguments:
@@ -1845,33 +1688,11 @@
 	mov	PIL_15, %g4
 	SET_SIZE(setvecint_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-wr_clr_softint(uint_t value)
-{}
-
-#else
-
 	ENTRY_NP(wr_clr_softint)
 	retl
 	wr	%o0, CLEAR_SOFTINT
 	SET_SIZE(wr_clr_softint)
 
-#endif /* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-intr_enqueue_req(uint_t pil, uint64_t inum)
-{}
-
-#else   /* lint */
-
 /*
  * intr_enqueue_req
  *
@@ -1921,21 +1742,11 @@
 	nop
 	SET_SIZE(intr_enqueue_req)
 
-#endif  /* lint */
-
 /*
  * Set CPU's base SPL level, based on which interrupt levels are active.
  * 	Called at spl7 or above.
  */
 
-#if defined(lint)
-
-void
-set_base_spl(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(set_base_spl)
 	ldn	[THREAD_REG + T_CPU], %o2	! load CPU pointer
 	ld	[%o2 + CPU_INTR_ACTV], %o5	! load active interrupts mask
@@ -1986,8 +1797,6 @@
 	.byte	5, 5, 5, 5,	5, 5, 5, 5,	5, 5, 5, 5,	5, 5, 5, 5
 	.align	4
 
-#endif	/* lint */
-
 /*
  * int
  * intr_passivate(from, to)
@@ -1995,15 +1804,6 @@
  *	kthread_id_t	to;		interrupted thread
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-intr_passivate(kthread_id_t from, kthread_id_t to)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(intr_passivate)
 	save	%sp, -SA(MINFRAME), %sp	! get a new window 
 
@@ -2060,77 +1860,6 @@
 	restore
 	SET_SIZE(intr_passivate)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*
- * intr_get_time() is a resource for interrupt handlers to determine how
- * much time has been spent handling the current interrupt. Such a function
- * is needed because higher level interrupts can arrive during the
- * processing of an interrupt, thus making direct comparisons of %tick by
- * the handler inaccurate. intr_get_time() only returns time spent in the
- * current interrupt handler.
- *
- * The caller must be calling from an interrupt handler running at a pil
- * below or at lock level. Timings are not provided for high-level
- * interrupts.
- *
- * The first time intr_get_time() is called while handling an interrupt,
- * it returns the time since the interrupt handler was invoked. Subsequent
- * calls will return the time since the prior call to intr_get_time(). Time
- * is returned as ticks, adjusted for any clock divisor due to power 
- * management. Use tick2ns() to convert ticks to nsec. Warning: ticks may 
- * not be the same across CPUs.
- *
- * Theory Of Intrstat[][]:
- *
- * uint64_t intrstat[pil][0..1] is an array indexed by pil level, with two
- * uint64_ts per pil.
- *
- * intrstat[pil][0] is a cumulative count of the number of ticks spent
- * handling all interrupts at the specified pil on this CPU. It is
- * exported via kstats to the user.
- *
- * intrstat[pil][1] is always a count of ticks less than or equal to the
- * value in [0]. The difference between [1] and [0] is the value returned
- * by a call to intr_get_time(). At the start of interrupt processing,
- * [0] and [1] will be equal (or nearly so). As the interrupt consumes
- * time, [0] will increase, but [1] will remain the same. A call to
- * intr_get_time() will return the difference, then update [1] to be the
- * same as [0]. Future calls will return the time since the last call.
- * Finally, when the interrupt completes, [1] is updated to the same as [0].
- *
- * Implementation:
- *
- * intr_get_time() works much like a higher level interrupt arriving. It
- * "checkpoints" the timing information by incrementing intrstat[pil][0]
- * to include elapsed running time, and by setting t_intr_start to %tick.
- * It then sets the return value to intrstat[pil][0] - intrstat[pil][1],
- * and updates intrstat[pil][1] to be the same as the new value of
- * intrstat[pil][0].
- *
- * In the normal handling of interrupts, after an interrupt handler returns
- * and the code in intr_thread() updates intrstat[pil][0], it then sets
- * intrstat[pil][1] to the new value of intrstat[pil][0]. When [0] == [1],
- * the timings are reset, i.e. intr_get_time() will return [0] - [1] which
- * is 0.
- *
- * Whenever interrupts arrive on a CPU which is handling a lower pil
- * interrupt, they update the lower pil's [0] to show time spent in the
- * handler that they've interrupted. This results in a growing discrepancy
- * between [0] and [1], which is returned the next time intr_get_time() is
- * called. Time spent in the higher-pil interrupt will not be returned in
- * the next intr_get_time() call from the original interrupt, because
- * the higher-pil interrupt's time is accumulated in intrstat[higherpil][].
- */
-
-/*ARGSUSED*/
-uint64_t
-intr_get_time(void)
-{ return 0; }
-#else	/* lint */
-
 	ENTRY_NP(intr_get_time)
 #ifdef DEBUG
 	!
@@ -2239,4 +1968,3 @@
 intr_get_time_no_start_time:
 	.asciz	"intr_get_time(): t_intr_start == 0"
 #endif /* DEBUG */
-#endif  /* lint */
--- old/usr/src/uts/sun4/ml/ip_ocsum.s	Thu Nov 14 19:00:35 2019
+++ new/usr/src/uts/sun4/ml/ip_ocsum.s	Thu Nov 14 19:00:35 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/param.h>
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
@@ -33,11 +31,7 @@
 #include <sys/machthread.h>
 #include <sys/machparam.h>
 
-#if defined(lint)
-#include <sys/types.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 /*
  * Prefetch considerations
@@ -75,15 +69,6 @@
  *
  */
 
-#if defined(lint) 
-
-/* ARGSUSED */
-unsigned int
-ip_ocsum(u_short *address, int halfword_count, unsigned int sum)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(ip_ocsum)
 
 /*
@@ -461,4 +446,3 @@
 
 	SET_SIZE(ip_ocsum_long)	! 64-bit version
 
-#endif 	/* lint */
--- old/usr/src/uts/sun4/ml/locore.s	Thu Nov 14 19:00:35 2019
+++ new/usr/src/uts/sun4/ml/locore.s	Thu Nov 14 19:00:35 2019
@@ -24,15 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/t_lock.h>
-#include <sys/promif.h>
-#include <sys/prom_isa.h>
-#endif	/* lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
 #include <sys/scb.h>
@@ -39,17 +30,8 @@
 #include <sys/machparam.h>
 #include <sys/machthread.h>
 
-#if defined(lint)
-
-#include <sys/thread.h>
-#include <sys/time.h>
-
-#else	/* lint */
-
 #include "assym.h"
 
-#endif	/* lint */
-
 /*
  * void
  * reestablish_curthread(void)
@@ -59,14 +41,6 @@
  *	The CPU_ADDR macro figures out the cpuid by reading hardware registers.
  */
 
-#if defined(lint)
-
-void
-reestablish_curthread(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(reestablish_curthread)
 
 	CPU_ADDR(%o0, %o1)
@@ -75,28 +49,17 @@
 	SET_SIZE(reestablish_curthread)
 
 
-#endif	/* lint */
-
 /*
  * Return the current THREAD pointer.
  * This is also available as an inline function.
  */
-#if defined(lint)
 
-kthread_id_t
-threadp(void)
-{ return ((kthread_id_t)0); }
-
-#else	/* lint */
-
 	ENTRY_NP(threadp)
 	retl
 	mov	THREAD_REG, %o0
 	SET_SIZE(threadp)
 
-#endif	/* lint */
 
-
 /*
  * The IEEE 1275-1994 callback handler for a 64-bit SPARC V9 PROM calling
  * a 32 bit client program. The PROM calls us with a 64 bit stack and a
@@ -109,18 +72,6 @@
  * the prom's window handlers are mixed mode handlers.
  */
 
-#if defined(lint)
-
-int
-callback_handler(cell_t *arg_array)
-{
-	extern int vx_handler(cell_t *arg_array);
-
-	return (vx_handler(arg_array));
-}
-
-#else	/* lint */
-
 	ENTRY_NP(callback_handler)
 	!
 	! We assume we are called with a 64 bit stack with PSTATE_AM clear
@@ -153,6 +104,4 @@
 	ret					! return result in %o0
 	restore					! back to a 64 bit stack
 	SET_SIZE(callback_handler)
-
-#endif	/* lint */
 
--- old/usr/src/uts/sun4/ml/proc_init.s	Thu Nov 14 19:00:36 2019
+++ new/usr/src/uts/sun4/ml/proc_init.s	Thu Nov 14 19:00:36 2019
@@ -23,11 +23,7 @@
  * Use is subject to license terms.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>
@@ -39,15 +35,11 @@
 #include <sys/clock.h>
 #include <vm/hat_sfmmu.h>	
 
-#if !defined(lint)
 	.weak	cpu_feature_init
 	.type	cpu_feature_init, #function
-#endif	/* lint */
 
-#if !defined(lint)
 	.weak	cpu_early_feature_init
 	.type	cpu_early_feature_init, #function
-#endif	/* lint */
 
 /*
  * Processor initialization
@@ -57,15 +49,6 @@
  * prom's trap table.  It expects the cpuid as its first parameter.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-cpu_startup(int cpuid)
-{}
-
-#else	/* lint */
-
 	! allocate a temporary stack to run on while we figure who and
 	! what we are.
 	.seg	".data"
@@ -154,4 +137,3 @@
 	restore				! WILL cause underflow
 	SET_SIZE(cpu_startup)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4/ml/subr_asm.s	Thu Nov 14 19:00:36 2019
+++ new/usr/src/uts/sun4/ml/subr_asm.s	Thu Nov 14 19:00:36 2019
@@ -23,19 +23,11 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * General machine architecture & implementation specific
  * assembly language routines.
  */
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/machsystm.h>
-#include <sys/t_lock.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/async.h>
@@ -43,14 +35,6 @@
 #include <sys/vis.h>
 #include <sys/machsig.h>
 
-#if defined(lint)
-caddr_t
-set_trap_table(void)
-{
-	return ((caddr_t)0);
-}
-#else /* lint */
-
 	ENTRY(set_trap_table)
 	set	trap_table, %o1
 	rdpr	%tba, %o0
@@ -59,72 +43,6 @@
 	wrpr	%g0, WSTATE_KERN, %wstate
 	SET_SIZE(set_trap_table)
 
-#endif /* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-stphys(uint64_t physaddr, int value)
-{}
-
-/*ARGSUSED*/
-int
-ldphys(uint64_t physaddr)
-{ return (0); }
-
-/*ARGSUSED*/
-void
-stdphys(uint64_t physaddr, uint64_t value)
-{}
-
-/*ARGSUSED*/
-uint64_t
-lddphys(uint64_t physaddr)
-{ return (0x0ull); }
-
-/* ARGSUSED */
-void
-stphysio(u_longlong_t physaddr, uint_t value)
-{}
-
-/* ARGSUSED */
-uint_t
-ldphysio(u_longlong_t physaddr)
-{ return(0); }
-
-/* ARGSUSED */
-void
-sthphysio(u_longlong_t physaddr, ushort_t value)
-{}
-
-/* ARGSUSED */
-ushort_t
-ldhphysio(u_longlong_t physaddr)
-{ return(0); }
-
-/* ARGSUSED */
-void
-stbphysio(u_longlong_t physaddr, uchar_t value)
-{}
-
-/* ARGSUSED */
-uchar_t
-ldbphysio(u_longlong_t physaddr)
-{ return(0); }
-
-/*ARGSUSED*/
-void
-stdphysio(u_longlong_t physaddr, u_longlong_t value)
-{}
-
-/*ARGSUSED*/
-u_longlong_t
-lddphysio(u_longlong_t physaddr)
-{ return (0ull); }
-
-#else
-
 	! Store long word value at physical address
 	!
 	! void  stdphys(uint64_t physaddr, uint64_t value)
@@ -300,7 +218,6 @@
 	retl
 	wrpr	%g0, %o4, %pstate	/* restore pstate */
 	SET_SIZE(ldbphysio)
-#endif  /* lint */
 
 /*
  * save_gsr(kfpu_t *fp)
@@ -307,15 +224,6 @@
  * Store the graphics status register
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-save_gsr(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(save_gsr)
 	rd	%gsr, %g2			! save gsr
 	retl
@@ -322,17 +230,6 @@
 	stx	%g2, [%o0 + FPU_GSR]
 	SET_SIZE(save_gsr)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-restore_gsr(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(restore_gsr)
 	ldx	[%o0 + FPU_GSR], %g2
 	wr	%g2, %g0, %gsr
@@ -340,8 +237,6 @@
 	nop
 	SET_SIZE(restore_gsr)
 
-#endif	/* lint */
-
 /*
  * uint64_t
  * _fp_read_pgsr()
@@ -348,23 +243,12 @@
  * Get the graphics status register info from fp and return it
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-uint64_t
-_fp_read_pgsr(kfpu_t *fp)
-{ return 0; }
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_read_pgsr)
 	retl
 	rd	%gsr, %o0
 	SET_SIZE(_fp_read_pgsr)
 
-#endif	/* lint */
 
-
 /*
  * uint64_t
  * get_gsr(kfpu_t *fp)
@@ -371,72 +255,31 @@
  * Get the graphics status register info from fp and return it
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-uint64_t
-get_gsr(kfpu_t *fp)
-{ return 0; }
-
-#else	/* lint */
-
 	ENTRY_NP(get_gsr)
 	retl
 	ldx	[%o0 + FPU_GSR], %o0
 	SET_SIZE(get_gsr)
 
-#endif
-
 /*
  * _fp_write_pgsr(uint64_t *buf, kfpu_t *fp)
  * Set the graphics status register info to fp from buf
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-_fp_write_pgsr(uint64_t buf, kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(_fp_write_pgsr)
 	retl
 	mov	%o0, %gsr
 	SET_SIZE(_fp_write_pgsr)
 
-#endif	/* lint */
-
 /*	
  * set_gsr(uint64_t buf, kfpu_t *fp)
  * Set the graphics status register info to fp from buf
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-set_gsr(uint64_t buf, kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(set_gsr)
 	retl
 	stx	%o0, [%o1 + FPU_GSR]
 	SET_SIZE(set_gsr)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-void
-kdi_cpu_index(void)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(kdi_cpu_index)
 	CPU_INDEX(%g1, %g2)
 	jmp	%g7
@@ -443,16 +286,6 @@
 	nop
 	SET_SIZE(kdi_cpu_index)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-void
-kmdb_enter(void)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(kmdb_enter)
 	t	ST_KMDB_TRAP
 	retl
@@ -459,8 +292,6 @@
 	nop
 	SET_SIZE(kmdb_enter)
 
-#endif	/* lint */
-
 /*
  * The Spitfire floating point code has been changed not to use install/
  * save/restore/fork/freectx() because of the special memcpy library
@@ -492,20 +323,6 @@
  * Store the floating point registers.
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-fp_save(kfpu_t *fp)
-{}
-
-/* ARGSUSED */
-void
-fp_fksave(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fp_save)
 	ALTENTRY(fp_fksave)
 	BSTORE_FPREGS(%o0, %o1)			! store V9 regs
@@ -514,8 +331,6 @@
 	SET_SIZE(fp_fksave)
 	SET_SIZE(fp_save)
 
-#endif	/* lint */
-
 /*
  * fp_v8_fksave(kfpu_t *fp)
  *
@@ -522,15 +337,6 @@
  * This is like the above routine but only saves the lower half.
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-fp_v8_fksave(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fp_v8_fksave)
 	BSTORE_V8_FPREGS(%o0, %o1)		! store V8 regs
 	retl
@@ -537,8 +343,6 @@
 	stx	%fsr, [%o0 + FPU_FSR]		! store fsr
 	SET_SIZE(fp_v8_fksave)
 
-#endif	/* lint */
-
 /*
  * fp_v8p_fksave(kfpu_t *fp)
  *
@@ -545,15 +349,6 @@
  * This is like the above routine but only saves the upper half.
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-fp_v8p_fksave(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fp_v8p_fksave)
 	BSTORE_V8P_FPREGS(%o0, %o1)		! store V9 extra regs
 	retl
@@ -560,21 +355,10 @@
 	stx	%fsr, [%o0 + FPU_FSR]		! store fsr
 	SET_SIZE(fp_v8p_fksave)
 
-#endif	/* lint */
-
 /*
  * fp_restore(kfpu_t *fp)
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-fp_restore(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fp_restore)
 	BLOAD_FPREGS(%o0, %o1)			! load V9 regs
 	retl
@@ -581,21 +365,10 @@
 	ldx	[%o0 + FPU_FSR], %fsr		! restore fsr
 	SET_SIZE(fp_restore)
 
-#endif	/* lint */
-
 /*
  * fp_v8_load(kfpu_t *fp)
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-fp_v8_load(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fp_v8_load)
 	BLOAD_V8_FPREGS(%o0, %o1)		! load V8 regs
 	retl
@@ -602,21 +375,10 @@
 	ldx	[%o0 + FPU_FSR], %fsr		! restore fsr
 	SET_SIZE(fp_v8_load)
 
-#endif	/* lint */
-
 /*
  * fp_v8p_load(kfpu_t *fp)
  */
 
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-void
-fp_v8p_load(kfpu_t *fp)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fp_v8p_load)
 	BLOAD_V8P_FPREGS(%o0, %o1)		! load V9 extra regs
 	retl
@@ -623,4 +385,3 @@
 	ldx	[%o0 + FPU_FSR], %fsr		! restore fsr
 	SET_SIZE(fp_v8p_load)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4/ml/swtch.s	Thu Nov 14 19:00:36 2019
+++ new/usr/src/uts/sun4/ml/swtch.s	Thu Nov 14 19:00:36 2019
@@ -26,11 +26,7 @@
  * Process switching routines.
  */
 
-#if !defined(lint)
 #include "assym.h"
-#else	/* lint */
-#include <sys/thread.h>
-#endif	/* lint */
 
 #include <sys/param.h>
 #include <sys/asm_linkage.h>
@@ -69,15 +65,6 @@
  * off the stack.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-resume(kthread_id_t t)
-{}
-
-#else	/* lint */
-
 	ENTRY(resume)
 	save	%sp, -SA(MINFRAME), %sp		! save ins and locals
 
@@ -454,17 +441,6 @@
 	SET_SIZE(_resume_from_idle)
 	SET_SIZE(resume)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-resume_from_zombie(kthread_id_t t)
-{}
-
-#else	/* lint */
-
 	ENTRY(resume_from_zombie)
 	save	%sp, -SA(MINFRAME), %sp		! save ins and locals
 
@@ -509,17 +485,6 @@
 	ldn	[%i0 + T_PROCP], %i3		! new process
 	SET_SIZE(resume_from_zombie)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-resume_from_intr(kthread_id_t t)
-{}
-
-#else	/* lint */
-
 	ENTRY(resume_from_intr)
 	save	%sp, -SA(MINFRAME), %sp		! save ins and locals
 
@@ -614,9 +579,7 @@
 	nop
 	SET_SIZE(resume_from_intr)
 
-#endif /* lint */
 
-
 /*
  * thread_start()
  *
@@ -628,14 +591,6 @@
  * procedure.
  */
 
-#if defined(lint)
-
-void
-thread_start(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(thread_start)
 	mov	%i0, %o0
 	jmpl 	%i7, %o7	! call thread_run()'s start() procedure.
@@ -645,5 +600,3 @@
 	nop
 	unimp 0
 	SET_SIZE(thread_start)
-
-#endif	/* lint */
--- old/usr/src/uts/sun4/ml/xc.s	Thu Nov 14 19:00:37 2019
+++ new/usr/src/uts/sun4/ml/xc.s	Thu Nov 14 19:00:37 2019
@@ -24,14 +24,7 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/cpuvar.h>
-#else	/*lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/param.h>
 #include <sys/asm_linkage.h>
@@ -50,14 +43,6 @@
 #endif /* TRAPTRACE */
 
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-send_self_xcall(struct cpu *cpu, uint64_t arg1, uint64_t arg2, xcfunc_t *func)
-{}
-
-#else
 /*
  * For a x-trap request to the same processor, just send a fast trap.
  * Does not accept inums.
@@ -67,13 +52,7 @@
 	retl
 	nop
 	SET_SIZE(send_self_xcall)
-#endif	/* lint */
 
-#if defined(lint)
-void
-idle_stop_xcall(void)
-{}
-#else
 /*
  * idle or stop xcall handler.
  *
@@ -98,6 +77,4 @@
 	ba,pt	%xcc, sys_trap
 	  movl	%xcc, XCALL_PIL, %g4
 	SET_SIZE(idle_stop_xcall)
-
-#endif	/* lint */
 
--- old/usr/src/uts/sun4u/cherrystone/ml/cherrystone_asm.s	Thu Nov 14 19:00:37 2019
+++ new/usr/src/uts/sun4u/cherrystone/ml/cherrystone_asm.s	Thu Nov 14 19:00:37 2019
@@ -24,13 +24,7 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#else
 #include "assym.h"
-#endif /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/param.h>
@@ -55,24 +49,6 @@
  * be a good idea to move this up to sun4u/ml.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-uint64_t
-lddmcdecode(uint64_t physaddr)
-{
-	return (0x0ull);
-}
-
-/* ARGSUSED */
-uint64_t
-lddsafaddr(uint64_t physaddr)
-{
-	return (0x0ull);
-}
-
-#else /* !lint */
-
 !
 ! Load the safari address for a specific cpu
 !
@@ -121,4 +97,3 @@
 	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
 	SET_SIZE(lddmcdecode)
 
-#endif /* lint */
--- old/usr/src/uts/sun4u/cpu/cheetah_copy.s	Thu Nov 14 19:00:38 2019
+++ new/usr/src/uts/sun4u/cpu/cheetah_copy.s	Thu Nov 14 19:00:38 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/param.h>
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
@@ -37,9 +35,7 @@
 #include <sys/privregs.h>
 #include <sys/fpras_impl.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 /*
  * Pseudo-code to aid in understanding the control flow of the
@@ -621,7 +617,6 @@
  * of the copy code to membar #Sync immediately after copy is complete
  * and before using the BLD_*_FROMSTACK macro.
  */
-#if !defined(lint)
 #define BST_FPQ1Q3_TOSTACK(tmp1)				\
 	/* membar #Sync	*/					;\
 	add	%fp, STACK_BIAS - SAVED_FPREGS_ADJUST, tmp1	;\
@@ -657,7 +652,6 @@
 	add	tmp1, VIS_BLOCKSIZE, tmp1			;\
 	ldda	[tmp1]ASI_BLK_P, %f48				;\
 	membar	#Sync
-#endif
 
 /*
  * FP_NOMIGRATE and FP_ALLOWMIGRATE.  Prevent migration (or, stronger,
@@ -737,15 +731,6 @@
  * Returns errno value on pagefault error, 0 if all ok
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-kcopy(const void *from, void *to, size_t count)
-{ return(0); }
-
-#else	/* lint */
-
 	.seg	".text"
 	.align	4
 
@@ -913,7 +898,6 @@
 	  mov	%g0, %o0			! 
 
 	SET_SIZE(kcopy)
-#endif	/* lint */
 
 
 /*
@@ -924,15 +908,7 @@
  * Copy a page of memory.
  * Assumes double word alignment and a count >= 256.
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-bcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(bcopy)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -1502,21 +1478,10 @@
 
 	SET_SIZE(bcopy_more)
 
-#endif	/* lint */
-
 /*
  * Block copy with possibly overlapped operands.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-ovbcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(ovbcopy)
 	tst	%o2			! check count
 	bgu,a	%ncc, 1f		! nothing to do or bad arguments
@@ -1560,9 +1525,7 @@
 
 	SET_SIZE(ovbcopy)
 
-#endif	/* lint */
 
-
 /*
  * hwblkpagecopy()
  *
@@ -1570,12 +1533,6 @@
  * has already disabled kernel preemption and has checked
  * use_hw_bcopy.  Preventing preemption also prevents cpu migration.
  */
-#ifdef lint
-/*ARGSUSED*/
-void
-hwblkpagecopy(const void *src, void *dst)
-{ }
-#else /* lint */
 	ENTRY(hwblkpagecopy)
 	! get another window w/space for three aligned blocks of saved fpregs
 	save	%sp, -SA(MINFRAME + HWCOPYFRAMESIZE), %sp
@@ -1703,7 +1660,6 @@
 	  restore	%g0, 0, %o0
 
 	SET_SIZE(hwblkpagecopy)
-#endif	/* lint */
 
 
 /*
@@ -1762,10 +1718,6 @@
  * Copy kernel data to user space (copyout/xcopyout/xcopyout_little).
  */
 
-#if defined(lint)
-
-
-#else	/* lint */
 /*
  * We save the arguments in the following registers in case of a fault:
  *	kaddr - %l1
@@ -1832,17 +1784,6 @@
 	SET_SIZE(copyio_fault)
 
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyout)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -2467,18 +2408,7 @@
 
 	SET_SIZE(copyout_more)
 
-#endif	/* lint */
 
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout)
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
 	bleu,pt	%ncc, .xcopyout_small		! go to larger cases
@@ -2583,17 +2513,6 @@
 
 	SET_SIZE(xcopyout)
 
-#endif	/* lint */
-	
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout_little(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout_little)
 	sethi	%hi(.xcopyio_err), %o5
 	or	%o5, %lo(.xcopyio_err), %o5
@@ -2624,21 +2543,10 @@
 
 	SET_SIZE(xcopyout_little)
 
-#endif	/* lint */
-
 /*
  * Copy user data to kernel space (copyin/xcopyin/xcopyin_little)
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyin)
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
 	bleu,pt	%ncc, .copyin_small		! go to larger cases
@@ -3254,17 +3162,6 @@
 
 	SET_SIZE(copyin_more)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -3370,17 +3267,6 @@
 
 	SET_SIZE(xcopyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin_little(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin_little)
 	sethi	%hi(.xcopyio_err), %o5
 	or	%o5, %lo(.xcopyio_err), %o5
@@ -3417,21 +3303,11 @@
 
 	SET_SIZE(xcopyin_little)
 
-#endif	/* lint */
 
-
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  * No fault handler installed (to be called under on_fault())
  */
-#if defined(lint)
-
-/* ARGSUSED */
-void
-copyin_noerr(const void *ufrom, void *kto, size_t count)
-{}
-
-#else	/* lint */
 	ENTRY(copyin_noerr)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -3515,7 +3391,6 @@
 	  nop
 
 	SET_SIZE(copyin_noerr)
-#endif /* lint */
 
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
@@ -3522,14 +3397,6 @@
  * No fault handler installed (to be called under on_fault())
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-copyout_noerr(const void *kfrom, void *uto, size_t count)
-{}
-
-#else	/* lint */
 	ENTRY(copyout_noerr)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -3603,7 +3470,6 @@
 	  or	REAL_LOFAULT, %lo(.copyio_noerr), REAL_LOFAULT
 
 	SET_SIZE(copyout_noerr)
-#endif /* lint */
 
 
 /*
@@ -3614,14 +3480,6 @@
  * Caller is responsible for ensuring use_hw_bzero is true and that
  * kpreempt_disable() has been called.
  */
-#ifdef lint
-/*ARGSUSED*/
-int
-hwblkclr(void *addr, size_t len)
-{ 
-	return(0);
-}
-#else /* lint */
 	! %i0 - start address
 	! %i1 - length of region (multiple of 64)
 	! %l0 - saved fprs
@@ -3722,14 +3580,7 @@
 	  restore	%g0, 0, %o0		! return (bzero or not)
 
 	SET_SIZE(hwblkclr)
-#endif	/* lint */
 
-#ifdef lint
-/*ARGSUSED*/
-void
-hw_pa_bcopy32(uint64_t src, uint64_t dst)
-{}
-#else /*!lint */
 	/*
 	 * Copy 32 bytes of data from src (%o0) to dst (%o1)
 	 * using physical addresses.
@@ -3764,19 +3615,6 @@
 
 	SET_SIZE(hw_pa_bcopy32)
 
-#endif /* lint */
-
-#if defined(lint)
-
-int use_hw_bcopy = 1;
-int use_hw_bzero = 1;
-uint_t hw_copy_limit_1 = 0;
-uint_t hw_copy_limit_2 = 0;
-uint_t hw_copy_limit_4 = 0;
-uint_t hw_copy_limit_8 = 0;
-
-#else /* !lint */
-
 	DGDEF(use_hw_bcopy)
 	.word	1
 	DGDEF(use_hw_bzero)
@@ -3792,4 +3630,3 @@
 
 	.align	64
 	.section ".text"
-#endif /* !lint */
--- old/usr/src/uts/sun4u/cpu/common_asm.s	Thu Nov 14 19:00:38 2019
+++ new/usr/src/uts/sun4u/cpu/common_asm.s	Thu Nov 14 19:00:38 2019
@@ -22,9 +22,7 @@
  * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* !lint */
 
 /*
  * General assembly language routines.
@@ -213,16 +211,7 @@
 
 #include <sys/clock.h>
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/scb.h>
-#include <sys/systm.h>
-#include <sys/regset.h>
-#include <sys/sunddi.h>
-#include <sys/lockstat.h>
-#endif	/* lint */
 
-
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
 #include <sys/machparam.h>	/* To get SYSBASE and PAGESIZE */
@@ -234,18 +223,8 @@
 #include <sys/dditypes.h>
 #include <sys/intr.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* !lint */
 
-#if defined(lint)
-
-uint_t
-get_impl(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(get_impl)
 	GET_CPU_IMPL(%o0)
 	retl
@@ -252,20 +231,6 @@
 	nop
 	SET_SIZE(get_impl)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * Softint generated when counter field of tick reg matches value field 
- * of tick_cmpr reg
- */
-/*ARGSUSED*/
-void
-tickcmpr_set(uint64_t clock_cycles)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(tickcmpr_set)
 	! get 64-bit clock_cycles interval
 	mov	%o0, %o2
@@ -287,16 +252,6 @@
 	nop
 	SET_SIZE(tickcmpr_set)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-tickcmpr_disable(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(tickcmpr_disable)
 	mov	1, %g1
 	sllx	%g1, TICKINT_DIS_SHFT, %o0
@@ -305,25 +260,6 @@
 	nop
 	SET_SIZE(tickcmpr_disable)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*
- * tick_write_delta() increments %tick by the specified delta.  This should
- * only be called after a CPR event to assure that gethrtime() continues to
- * increase monotonically.  Obviously, writing %tick needs to de done very
- * carefully to avoid introducing unnecessary %tick skew across CPUs.  For
- * this reason, we make sure we're i-cache hot before actually writing to
- * %tick.
- */
-/*ARGSUSED*/
-void
-tick_write_delta(uint64_t delta)
-{}
-
-#else	/* lint */
-
 #ifdef DEBUG
 	.seg	".text"
 tick_write_panic:
@@ -350,19 +286,7 @@
 
 	retl				! Return
 	wrpr	%g0, %g1, %pstate	!     delay: Re-enable interrupts
-#endif	/* lint */
 
-#if defined(lint)
-/*
- *  return 1 if disabled
- */
-
-int
-tickcmpr_disabled(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY_NP(tickcmpr_disabled)
 	RD_TICKCMPR(%g1, %o0)
 	retl
@@ -369,23 +293,10 @@
 	srlx	%g1, TICKINT_DIS_SHFT, %o0
 	SET_SIZE(tickcmpr_disabled)
 
-#endif	/* lint */
-
 /*
  * Get current tick
  */
-#if defined(lint)
 
-u_longlong_t
-gettick(void)
-{ return (0); }
-
-u_longlong_t
-randtick(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(gettick)
 	ALTENTRY(randtick)
 	GET_NATIVE_TIME(%o0, %o2, %o3)
@@ -394,21 +305,11 @@
 	SET_SIZE(randtick)
 	SET_SIZE(gettick)
 
-#endif	/* lint */
 
-
 /*
  * Return the counter portion of the tick register.
  */
 
-#if defined(lint)
-
-uint64_t
-gettick_counter(void)
-{ return(0); }
-
-#else	/* lint */
-
 	ENTRY_NP(gettick_counter)
 	rdpr	%tick, %o0
 	sllx	%o0, 1, %o0
@@ -415,7 +316,6 @@
 	retl
 	srlx	%o0, 1, %o0		! shake off npt bit
 	SET_SIZE(gettick_counter)
-#endif	/* lint */
 
 /*
  * Provide a C callable interface to the trap that reads the hi-res timer.
@@ -422,65 +322,6 @@
  * Returns 64-bit nanosecond timestamp in %o0 and %o1.
  */
 
-#if defined(lint)
-
-hrtime_t
-gethrtime(void)
-{
-	return ((hrtime_t)0);
-}
-
-hrtime_t
-gethrtime_unscaled(void)
-{
-	return ((hrtime_t)0);
-}
-
-hrtime_t
-gethrtime_max(void)
-{
-	return ((hrtime_t)0);
-}
-
-void
-scalehrtime(hrtime_t *hrt)
-{
-	*hrt = 0;
-}
-
-void
-gethrestime(timespec_t *tp)
-{
-	tp->tv_sec = 0;
-	tp->tv_nsec = 0;
-}
-
-time_t
-gethrestime_sec(void)
-{
-	return (0);
-}
-
-void
-gethrestime_lasttick(timespec_t *tp)
-{
-	tp->tv_sec = 0;
-	tp->tv_nsec = 0;
-}
-
-/*ARGSUSED*/
-void
-hres_tick(void)
-{
-}
-
-void
-panic_hres_tick(void)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(gethrtime)
 	GET_HRTIME(%g1, %o0, %o1, %o2, %o3, %o4, %o5, %g2)
 							! %g1 = hrtime
@@ -772,10 +613,6 @@
 
 	SET_SIZE(hres_tick)
 
-#endif	/* lint */
-
-#if !defined(lint) && !defined(__lint)
-
 	.seg	".text"
 kstat_q_panic_msg:
 	.asciz	"kstat_q_exit: qlen == 0"
@@ -885,20 +722,6 @@
 	KSTAT_Q_UPDATE(add, BRZPT, 1f, 1:retl, KSTAT_IO_W)
 	SET_SIZE(kstat_runq_back_to_waitq)
 
-#endif	/* !(lint || __lint) */
-
-#ifdef lint	
-
-int64_t timedelta;
-hrtime_t hres_last_tick;
-volatile timestruc_t hrestime;
-int64_t hrestime_adj;
-volatile int hres_lock;
-uint_t nsec_scale;
-hrtime_t hrtime_base;
-int traptrace_use_stick;
-
-#else	/* lint */
 	/*
 	 *  -- WARNING --
 	 *
@@ -936,9 +759,7 @@
 adj_shift:
 	.word	ADJ_SHIFT
 
-#endif	/* lint */
 
-
 /*
  * drv_usecwait(clock_t n)	[DDI/DKI - section 9F]
  * usec_delay(int n)		[compatibility - should go one day]
@@ -958,20 +779,6 @@
  * We chose less code duplication for this.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-drv_usecwait(clock_t n)
-{}
-
-/*ARGSUSED*/
-void
-usec_delay(int n)
-{}
-
-#else	/* lint */
-
 	ENTRY(drv_usecwait)
 	ALTENTRY(usec_delay)
 	brlez,a,pn %o0, 0f
@@ -996,17 +803,7 @@
 	nop
 	SET_SIZE(usec_delay)
 	SET_SIZE(drv_usecwait)
-#endif	/* lint */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-pil14_interrupt(int level)
-{}
-
-#else	/* lint */
-
 /*
  * Level-14 interrupt prologue.
  */
@@ -1096,17 +893,6 @@
 	nop
 	SET_SIZE(tick_rtt)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-pil15_interrupt(int level)
-{}
-
-#else  /* lint */
-
 /*
  * Level-15 interrupt prologue.
  */
@@ -1124,19 +910,6 @@
        stn     %g0, [%g1 + CPU_CPCPROFILE_UPC] ! zero user PC
        SET_SIZE(pil15_interrupt)
 
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-uint64_t
-find_cpufrequency(volatile uchar_t *clock_ptr)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 #ifdef DEBUG
 	.seg	".text"
 find_cpufreq_panic:
@@ -1184,24 +957,6 @@
 	sub	%o5, %o3, %o0		! return the difference in ticks
 	SET_SIZE(find_cpufrequency)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * Prefetch a page_t for write or read, this assumes a linear
- * scan of sequential page_t's.
- */
-/*ARGSUSED*/
-void
-prefetch_page_w(void *pp)
-{}
-
-/*ARGSUSED*/
-void
-prefetch_page_r(void *pp)
-{}
-#else	/* lint */
-
 #if defined(CHEETAH) || defined(CHEETAH_PLUS) || defined(JALAPENO) || \
 	defined(SERRANO)
 	!
@@ -1358,18 +1113,6 @@
 
 #endif	/* OLYMPUS_C */
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * Prefetch struct smap for write. 
- */
-/*ARGSUSED*/
-void
-prefetch_smap_w(void *smp)
-{}
-#else	/* lint */
-
 #if defined(CHEETAH) || defined(CHEETAH_PLUS) || defined(JALAPENO) || \
 	defined(SERRANO)
 
@@ -1421,20 +1164,8 @@
 	prefetch	[%o0-SMAP_STRIDE], #n_writes
 	SET_SIZE(prefetch_smap_w)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-uint64_t
-getidsr(void)
-{ return 0; }
-
-#else	/* lint */
-
 	ENTRY_NP(getidsr)
 	retl
 	ldxa	[%g0]ASI_INTR_DISPATCH_STATUS, %o0
 	SET_SIZE(getidsr)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/cpu/opl_olympus_asm.s	Thu Nov 14 19:00:39 2019
+++ new/usr/src/uts/sun4u/cpu/opl_olympus_asm.s	Thu Nov 14 19:00:39 2019
@@ -25,9 +25,7 @@
  * Assembly code support for the Olympus-C module
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -67,15 +65,6 @@
  * SPARC64-VI MMU and Cache operations.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flushpage(caddr_t vaddr, uint64_t sfmmup)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushpage)
 	/*
 	 * flush page from the tlb
@@ -144,17 +133,7 @@
 	wrpr	%g0, %o5, %pstate		/* enable interrupts */
 	SET_SIZE(vtag_flushpage)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-void
-vtag_flushall(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP2(vtag_flushall, demap_all)
 	/*
 	 * flush the tlb
@@ -169,18 +148,7 @@
 	SET_SIZE(demap_all)
 	SET_SIZE(vtag_flushall)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushpage_tl1)
 	/*
 	 * x-trap to flush page from tlb and tsb
@@ -225,18 +193,7 @@
 	retry
 	SET_SIZE(vtag_flushpage_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flush_pgcnt_tl1)
 	/*
 	 * x-trap to flush pgcnt MMU_PAGESIZE pages from tlb
@@ -315,18 +272,7 @@
 	retry
 	SET_SIZE(vtag_flush_pgcnt_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushall_tl1)
 	/*
 	 * x-trap to flush tlb
@@ -337,9 +283,7 @@
 	retry
 	SET_SIZE(vtag_flushall_tl1)
 
-#endif	/* lint */
 
-
 /*
  * VAC (virtual address conflict) does not apply to OPL.
  * VAC resolution is managed by the Olympus processor hardware.
@@ -346,81 +290,27 @@
  * As a result, all OPL VAC flushing routines are no-ops.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushpage(pfn_t pfnum, int vcolor)
-{}
-
-#else	/* lint */
-
 	ENTRY(vac_flushpage)
 	retl
 	  nop
 	SET_SIZE(vac_flushpage)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vac_flushpage_tl1)
 	retry
 	SET_SIZE(vac_flushpage_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushcolor(int vcolor, pfn_t pfnum)
-{}
-
-#else	/* lint */
-
 	ENTRY(vac_flushcolor)
 	retl
 	 nop
 	SET_SIZE(vac_flushcolor)
 
-#endif  /* lint */
 
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushcolor_tl1(uint64_t vcolor, uint64_t pfnum)
-{}
-
-#else	/* lint */
-
 	ENTRY(vac_flushcolor_tl1)
 	retry
 	SET_SIZE(vac_flushcolor_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-int
-idsr_busy(void)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 /*
  * Determine whether or not the IDSR is busy.
  * Entry: no arguments
@@ -437,22 +327,6 @@
 	nop
 	SET_SIZE(idsr_busy)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-/* ARGSUSED */
-void
-init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-#else	/* lint */
-
 	.global _dispatch_status_busy
 _dispatch_status_busy:
 	.asciz	"ASI_INTR_DISPATCH_STATUS error: busy"
@@ -506,18 +380,7 @@
 	SET_SIZE(init_mondo_nocheck)
 	SET_SIZE(init_mondo)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-shipit(int upaid, int bn)
-{ return; }
-
-#else	/* lint */
-
 /*
  * Ship mondo to aid using busy/nack pair bn
  */
@@ -532,18 +395,7 @@
 	nop
 	SET_SIZE(shipit)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-flush_instr_mem(caddr_t vaddr, size_t len)
-{}
-
-#else	/* lint */
-
 /*
  * flush_instr_mem:
  *	Flush 1 page of the I-$ starting at vaddr
@@ -563,9 +415,7 @@
 	nop
 	SET_SIZE(flush_instr_mem)
 
-#endif	/* lint */
 
-
 /*
  * flush_ecache:
  *	%o0 - 64 bit physical address
@@ -572,15 +422,7 @@
  *	%o1 - ecache size
  *	%o2 - ecache linesize
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-void
-flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
-{}
-
-#else /* !lint */
-
 	ENTRY(flush_ecache)
 
 	/*
@@ -591,19 +433,6 @@
 	nop
 	SET_SIZE(flush_ecache)
 
-#endif /* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-kdi_flush_idcache(int dcache_size, int dcache_lsize, int icache_size,
-    int icache_lsize)
-{
-}
-
-#else	/* lint */
-
 	/*
 	 * I/D cache flushing is not needed for OPL processors
 	 */
@@ -612,8 +441,6 @@
 	nop
 	SET_SIZE(kdi_flush_idcache)
 
-#endif	/* lint */
-
 #ifdef	TRAPTRACE
 /*
  * Simplified trap trace macro for OPL. Adapted from us3.
@@ -1001,7 +828,6 @@
  * registers.
  */
 
-#if !defined(lint)
 #define	RESET_MMU_REGS(tmp1, tmp2, tmp3)			\
 	FLUSH_ALL_TLB(tmp1)					;\
 	set	MMU_PCONTEXT, tmp1				;\
@@ -1023,7 +849,6 @@
 	stxa	%g0, [tmp]ASI_IMMU				;\
 	stxa	%g0, [tmp]ASI_DMMU				;\
 	membar	#Sync
-#endif /* lint */
 
 /*
  * In case of errors in the MMU_TSB_PREFETCH registers we have to
@@ -1031,7 +856,6 @@
  * the "V" bit of the registers to 0, which will disable the prefetch
  * so the values of the other fields are irrelevant.
  */
-#if !defined(lint)
 #define	RESET_TSB_PREFETCH(tmp)			\
 	set	VA_UTSBPREF_8K, tmp 		;\
 	stxa	%g0, [tmp]ASI_ITSB_PREFETCH	;\
@@ -1049,7 +873,6 @@
 	stxa	%g0, [tmp]ASI_DTSB_PREFETCH	;\
 	set	VA_KTSBPREF_4M, tmp 		;\
 	stxa	%g0, [tmp]ASI_DTSB_PREFETCH
-#endif /* lint */
 
 /*
  * In case of errors in the MMU_SHARED_CONTEXT register we have to
@@ -1057,11 +880,9 @@
  * 0 in the IV field disabling the shared context support, and
  * making values of all the other fields of the register irrelevant.
  */
-#if !defined(lint)
 #define	RESET_SHARED_CTXT(tmp)			\
 	set	MMU_SHARED_CONTEXT, tmp		;\
 	stxa	%g0, [tmp]ASI_DMMU
-#endif /* lint */
 
 /*
  * RESET_TO_PRIV()
@@ -1125,14 +946,6 @@
 	wrpr	%g0, %tpc
 
 
-#if defined(lint)
-
-void
-ce_err(void)
-{}
-
-#else	/* lint */
-
 /*
  * We normally don't expect CE traps since we disable the
  * 0x63 trap reporting at the start of day. There is a
@@ -1160,17 +973,7 @@
 	sub	%g0, 1, %g4
 	SET_SIZE(ce_err)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-void
-ce_err_tl1(void)
-{}
-
-#else	/* lint */
-
 /*
  * We don't use trap for CE detection.
  */
@@ -1182,17 +985,7 @@
 	sub	%g0, 1, %g4
 	SET_SIZE(ce_err_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-void
-async_err(void)
-{}
-
-#else	/* lint */
-
 /*
  * async_err is the default handler for IAE/DAE traps.
  * For OPL, we patch in the right handler at start of day.
@@ -1207,14 +1000,6 @@
 	sub	%g0, 1, %g4
 	SET_SIZE(async_err)
 
-#endif	/* lint */
-
-#if defined(lint)
-void
-opl_sync_trap(void)
-{}
-#else	/* lint */
-
 	.seg	".data"
 	.global	opl_clr_freg
 	.global opl_cpu0_err_log
@@ -1401,13 +1186,7 @@
 	jmp	%g5 + %lo(sys_trap)
 	 mov	PIL_15, %g4
 	SET_SIZE(opl_sync_trap)
-#endif	/* lint */
 
-#if defined(lint)
-void
-opl_uger_trap(void)
-{}
-#else	/* lint */
 /*
  * Common Urgent error trap handler (tt=0x40)
  * All TL=0 and TL>0 0x40 traps vector to this handler.
@@ -1622,16 +1401,7 @@
 	jmp	%g5 + %lo(sys_trap)
 	 mov	PIL_15, %g4
 	SET_SIZE(opl_uger_trap)
-#endif	/* lint */
 
-#if defined(lint)
-void
-opl_ta3_trap(void)
-{}
-void
-opl_cleanw_subr(void)
-{}
-#else	/* lint */
 /*
  * OPL ta3 support (note please, that win_reg
  * area size for each cpu is 2^7 bytes)
@@ -1727,15 +1497,7 @@
 	jmp	%g7
 	  nop
 	SET_SIZE(opl_cleanw_subr)
-#endif	/* lint */
 
-#if defined(lint)
-
-void
-opl_serr_instr(void)
-{}
-
-#else	/* lint */
 /*
  * The actual trap handler for tt=0x0a, and tt=0x32
  */
@@ -1747,15 +1509,6 @@
 	.align  32
 	SET_SIZE(opl_serr_instr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-opl_ugerr_instr(void)
-{}
-
-#else	/* lint */
 /*
  * The actual trap handler for tt=0x40
  */
@@ -1766,15 +1519,6 @@
 	.align  32
 	SET_SIZE(opl_ugerr_instr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-opl_ta3_instr(void)
-{}
-
-#else	/* lint */
 /*
  * The actual trap handler for tt=0x103 (flushw)
  */
@@ -1785,15 +1529,6 @@
 	.align  32
 	SET_SIZE(opl_ta3_instr)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-opl_ta4_instr(void)
-{}
-
-#else	/* lint */
 /*
  * The patch for the .clean_windows code
  */
@@ -1807,20 +1542,6 @@
 	nop
 	SET_SIZE(opl_ta4_instr)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- *  Get timestamp (stick).
- */
-/* ARGSUSED */
-void
-stick_timestamp(int64_t *ts)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(stick_timestamp)
 	rd	STICK, %g1	! read stick reg
 	sllx	%g1, 1, %g1
@@ -1830,21 +1551,7 @@
 	stx	%g1, [%o0]	! store the timestamp
 	SET_SIZE(stick_timestamp)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * Set STICK adjusted by skew.
- */
-/* ARGSUSED */
-void
-stick_adj(int64_t skew)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(stick_adj)
 	rdpr	%pstate, %g1		! save processor state
 	andn	%g1, PSTATE_IE, %g3
@@ -1862,21 +1569,6 @@
 	wrpr	%g1, %pstate		! restore processor state
 	SET_SIZE(stick_adj)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * Debugger-specific stick retrieval
- */
-/*ARGSUSED*/
-int
-kdi_get_stick(uint64_t *stickp)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 	ENTRY_NP(kdi_get_stick)
 	rd	STICK, %g1
 	stx	%g1, [%o0]
@@ -1884,17 +1576,6 @@
 	mov	%g0, %o0
 	SET_SIZE(kdi_get_stick)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_blksuword32)
 	save	%sp, -SA(MINFRAME + 4), %sp
 
@@ -1959,15 +1640,7 @@
 	restore
 
 	SET_SIZE(dtrace_blksuword32)
-#endif /* lint */
 
-#if defined(lint)
-/*ARGSUSED*/
-void
-ras_cntr_reset(void *arg)
-{
-}
-#else
 	ENTRY_NP(ras_cntr_reset)
 	set	OPL_SCRATCHPAD_ERRLOG, %o1
 	ldxa	[%o1]ASI_SCRATCHPAD, %o0
@@ -1975,16 +1648,7 @@
 	retl
 	 stxa	%o0, [%o1]ASI_SCRATCHPAD
 	SET_SIZE(ras_cntr_reset)
-#endif /* lint */
 
-#if defined(lint)
-/* ARGSUSED */
-void
-opl_error_setup(uint64_t cpu_err_log_pa)
-{
-}
-
-#else	/* lint */
 	ENTRY_NP(opl_error_setup)
 	/*
 	 * Initialize the error log scratchpad register
@@ -2007,15 +1671,7 @@
 	retl
 	  stxa	%o0, [%o1]ASI_AFSR
 	SET_SIZE(opl_error_setup)
-#endif /* lint */
 
-#if defined(lint)
-/* ARGSUSED */
-void
-cpu_early_feature_init(void)
-{
-}
-#else	/* lint */
 	ENTRY_NP(cpu_early_feature_init)
 	/*
 	 * Enable MMU translating multiple page sizes for
@@ -2035,18 +1691,7 @@
 	retl
 	  flush	%o1
 	SET_SIZE(cpu_early_feature_init)
-#endif /* lint */
 
-#if	defined(lint)
-/*
- * This function is called for each (enabled) CPU. We use it to
- * initialize error handling related registers.
- */
-/*ARGSUSED*/
-void
-cpu_feature_init(void)
-{}
-#else	/* lint */
 	ENTRY(cpu_feature_init)
 	!
 	! get the device_id and store the device_id
@@ -2064,15 +1709,7 @@
 	ba	opl_cpu_reg_init
 	nop
 	SET_SIZE(cpu_feature_init)
-#endif	/* lint */
 
-#if defined(lint)
-
-void
-cpu_cleartickpnt(void)
-{}
-
-#else	/* lint */
 	/*
 	 * Clear the NPT (non-privileged trap) bit in the %tick/%stick
 	 * registers. In an effort to make the change in the
@@ -2112,20 +1749,6 @@
 
 	SET_SIZE(cpu_clearticknpt)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-cpu_halt_cpu(void)
-{}
-
-void
-cpu_smt_pause(void)
-{}
-
-#else	/* lint */
-
 	/*
 	 * Halt the current strand with the suspend instruction.
 	 * The compiler/asm currently does not support this suspend
@@ -2148,4 +1771,3 @@
 	nop
 	SET_SIZE(cpu_smt_pause)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/cpu/opl_olympus_copy.s	Thu Nov 14 19:00:39 2019
+++ new/usr/src/uts/sun4u/cpu/opl_olympus_copy.s	Thu Nov 14 19:00:39 2019
@@ -33,9 +33,7 @@
 #include <sys/fsr.h>
 #include <sys/privregs.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 /*
  * Pseudo-code to aid in understanding the control flow of the
@@ -586,7 +584,6 @@
  * of the copy code to membar #Sync immediately after copy is complete
  * and before using the BLD_*_FROMSTACK macro.
  */
-#if !defined(lint)
 #define BST_FPQ1Q3_TOSTACK(tmp1)				\
 	/* membar #Sync	*/					;\
 	add	%fp, STACK_BIAS - SAVED_FPREGS_ADJUST, tmp1	;\
@@ -622,7 +619,6 @@
 	add	tmp1, VIS_BLOCKSIZE, tmp1			;\
 	ldda	[tmp1]ASI_BLK_P, %f48				;\
 	membar	#Sync
-#endif
 
 /*
  * FP_NOMIGRATE and FP_ALLOWMIGRATE.  Prevent migration (or, stronger,
@@ -692,15 +688,6 @@
  * Returns errno value on pagefault error, 0 if all ok
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-kcopy(const void *from, void *to, size_t count)
-{ return(0); }
-
-#else	/* lint */
-
 	.seg	".text"
 	.align	4
 
@@ -868,7 +855,6 @@
 	  mov	%g0, %o0			!
 
 	SET_SIZE(kcopy)
-#endif	/* lint */
 
 
 /*
@@ -879,15 +865,7 @@
  * Copy a page of memory.
  * Assumes double word alignment and a count >= 256.
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-bcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(bcopy)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -1444,21 +1422,10 @@
 
 	SET_SIZE(bcopy_more)
 
-#endif	/* lint */
-
 /*
  * Block copy with possibly overlapped operands.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-ovbcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(ovbcopy)
 	tst	%o2			! check count
 	bgu,a	%ncc, 1f		! nothing to do or bad arguments
@@ -1502,9 +1469,7 @@
 
 	SET_SIZE(ovbcopy)
 
-#endif	/* lint */
 
-
 /*
  * hwblkpagecopy()
  *
@@ -1512,12 +1477,6 @@
  * has already disabled kernel preemption and has checked
  * use_hw_bcopy.  Preventing preemption also prevents cpu migration.
  */
-#ifdef lint
-/*ARGSUSED*/
-void
-hwblkpagecopy(const void *src, void *dst)
-{ }
-#else /* lint */
 	ENTRY(hwblkpagecopy)
 	! get another window w/space for three aligned blocks of saved fpregs
 	prefetch [%o0], #n_reads
@@ -1635,7 +1594,6 @@
 	  restore	%g0, 0, %o0
 
 	SET_SIZE(hwblkpagecopy)
-#endif	/* lint */
 
 
 /*
@@ -1694,10 +1652,6 @@
  * Copy kernel data to user space (copyout/xcopyout/xcopyout_little).
  */
 
-#if defined(lint)
-
-
-#else	/* lint */
 /*
  * We save the arguments in the following registers in case of a fault:
  *	kaddr - %l1
@@ -1764,17 +1718,6 @@
 	SET_SIZE(copyio_fault)
 
 
-#endif
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyout)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -2390,18 +2333,7 @@
 
 	SET_SIZE(copyout_more)
 
-#endif	/* lint */
 
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout)
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
 	bleu,pt	%ncc, .xcopyout_small		! go to larger cases
@@ -2506,17 +2438,6 @@
 
 	SET_SIZE(xcopyout)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout_little(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout_little)
 	sethi	%hi(.xcopyio_err), %o5
 	or	%o5, %lo(.xcopyio_err), %o5
@@ -2547,21 +2468,10 @@
 
 	SET_SIZE(xcopyout_little)
 
-#endif	/* lint */
-
 /*
  * Copy user data to kernel space (copyin/xcopyin/xcopyin_little)
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyin)
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
 	bleu,pt	%ncc, .copyin_small		! go to larger cases
@@ -3168,17 +3078,6 @@
 
 	SET_SIZE(copyin_more)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -3284,17 +3183,6 @@
 
 	SET_SIZE(xcopyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin_little(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin_little)
 	sethi	%hi(.xcopyio_err), %o5
 	or	%o5, %lo(.xcopyio_err), %o5
@@ -3331,21 +3219,11 @@
 
 	SET_SIZE(xcopyin_little)
 
-#endif	/* lint */
 
-
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  * No fault handler installed (to be called under on_fault())
  */
-#if defined(lint)
-
-/* ARGSUSED */
-void
-copyin_noerr(const void *ufrom, void *kto, size_t count)
-{}
-
-#else	/* lint */
 	ENTRY(copyin_noerr)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -3429,7 +3307,6 @@
 	  nop
 
 	SET_SIZE(copyin_noerr)
-#endif /* lint */
 
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
@@ -3436,14 +3313,6 @@
  * No fault handler installed (to be called under on_fault())
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-copyout_noerr(const void *kfrom, void *uto, size_t count)
-{}
-
-#else	/* lint */
 	ENTRY(copyout_noerr)
 
 	cmp	%o2, VIS_COPY_THRESHOLD		! check for leaf rtn case
@@ -3517,7 +3386,6 @@
 	  or	REAL_LOFAULT, %lo(.copyio_noerr), REAL_LOFAULT
 
 	SET_SIZE(copyout_noerr)
-#endif /* lint */
 
 
 /*
@@ -3528,14 +3396,6 @@
  * Caller is responsible for ensuring use_hw_bzero is true and that
  * kpreempt_disable() has been called.
  */
-#ifdef lint
-/*ARGSUSED*/
-int
-hwblkclr(void *addr, size_t len)
-{
-	return(0);
-}
-#else /* lint */
 	! %i0 - start address
 	! %i1 - length of region (multiple of 64)
 	! %l0 - saved fprs
@@ -3636,14 +3496,7 @@
 	  restore	%g0, 0, %o0		! return (bzero or not)
 
 	SET_SIZE(hwblkclr)
-#endif	/* lint */
 
-#ifdef lint
-/*ARGSUSED*/
-void
-hw_pa_bcopy32(uint64_t src, uint64_t dst)
-{}
-#else /*!lint */
 	/*
 	 * Copy 32 bytes of data from src (%o0) to dst (%o1)
 	 * using physical addresses.
@@ -3676,19 +3529,6 @@
 
 	SET_SIZE(hw_pa_bcopy32)
 
-#endif /* lint */
-
-#if defined(lint)
-
-int use_hw_bcopy = 1;
-int use_hw_bzero = 1;
-uint_t hw_copy_limit_1 = 0;
-uint_t hw_copy_limit_2 = 0;
-uint_t hw_copy_limit_4 = 0;
-uint_t hw_copy_limit_8 = 0;
-
-#else /* !lint */
-
 	DGDEF(use_hw_bcopy)
 	.word	1
 	DGDEF(use_hw_bzero)
@@ -3704,4 +3544,3 @@
 
 	.align	64
 	.section ".text"
-#endif /* !lint */
--- old/usr/src/uts/sun4u/cpu/spitfire_asm.s	Thu Nov 14 19:00:40 2019
+++ new/usr/src/uts/sun4u/cpu/spitfire_asm.s	Thu Nov 14 19:00:40 2019
@@ -23,11 +23,7 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -48,8 +44,6 @@
 #include <sys/traptrace.h>
 #endif /* TRAPTRACE */
 
-#ifndef	lint
-
 /* BEGIN CSTYLED */
 #define	DCACHE_FLUSHPAGE(arg1, arg2, tmp1, tmp2, tmp3)			\
 	ldxa	[%g0]ASI_LSU, tmp1					;\
@@ -347,102 +341,10 @@
 
 /* END CSTYLED */
 
-#endif	/* !lint */
-
 /*
  * Spitfire MMU and Cache operations.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-vtag_flushpage(caddr_t vaddr, uint64_t sfmmup)
-{}
-
-/*ARGSUSED*/
-void
-vtag_flushall(void)
-{}
-	
-/*ARGSUSED*/
-void
-vtag_flushall_uctxs(void)
-{}
-		
-/*ARGSUSED*/
-void
-vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup)
-{}
-
-/*ARGSUSED*/
-void
-vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt)
-{}
-
-/*ARGSUSED*/
-void
-vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2)
-{}
-
-/*ARGSUSED*/
-void
-vac_flushpage(pfn_t pfnum, int vcolor)
-{}
-
-/*ARGSUSED*/
-void
-vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor)
-{}
-
-/*ARGSUSED*/
-void
-init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-/*ARGSUSED*/
-void
-init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-/*ARGSUSED*/
-void
-flush_instr_mem(caddr_t vaddr, size_t len)
-{}
-
-/*ARGSUSED*/
-void
-flush_ecache(uint64_t physaddr, size_t size, size_t linesize)
-{}
-
-/*ARGSUSED*/
-void
-get_ecache_dtag(uint32_t ecache_idx, uint64_t *ecache_data,
-		uint64_t *ecache_tag, uint64_t *oafsr, uint64_t *acc_afsr)
-{}
-
-/* ARGSUSED */
-uint64_t
-get_ecache_tag(uint32_t id, uint64_t *nafsr, uint64_t *acc_afsr)
-{
-	return ((uint64_t)0);
-}
-
-/* ARGSUSED */
-uint64_t
-check_ecache_line(uint32_t id, uint64_t *acc_afsr)
-{
-	return ((uint64_t)0);
-}
-
-/*ARGSUSED*/
-void
-kdi_flush_idcache(int dcache_size, int dcache_lsize,
-    int icache_size, int icache_lsize)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushpage)
 	/*
 	 * flush page from the tlb
@@ -956,64 +858,7 @@
 	ret
 	  restore
 	SET_SIZE(get_ecache_dtag)
-#endif /* lint */
 
-#if defined(lint)
-/*
- * The ce_err function handles trap type 0x63 (corrected_ECC_error) at tl=0.
- * Steps: 1. GET AFSR  2. Get AFAR <40:4> 3. Get datapath error status
- *	  4. Clear datapath error bit(s) 5. Clear AFSR error bit
- *	  6. package data in %g2 and %g3 7. call cpu_ce_error vis sys_trap
- * %g2: [ 52:43 UDB lower | 42:33 UDB upper | 32:0 afsr ] - arg #3/arg #1
- * %g3: [ 40:4 afar ] - sys_trap->have_win: arg #4/arg #2
- */
-void
-ce_err(void)
-{}
-
-void
-ce_err_tl1(void)
-{}
-
-
-/*
- * The async_err function handles trap types 0x0A (instruction_access_error)
- * and 0x32 (data_access_error) at TL = 0 and TL > 0.  When we branch here,
- * %g5 will have the trap type (with 0x200 set if we're at TL > 0).
- *
- * Steps: 1. Get AFSR 2. Get AFAR <40:4> 3. If not UE error skip UDP registers.
- *	  4. Else get and clear datapath error bit(s) 4. Clear AFSR error bits
- *	  6. package data in %g2 and %g3 7. disable all cpu errors, because
- *	  trap is likely to be fatal 8. call cpu_async_error vis sys_trap
- *
- * %g3: [ 63:53 tt | 52:43 UDB_L | 42:33 UDB_U | 32:0 afsr ] - arg #3/arg #1
- * %g2: [ 40:4 afar ] - sys_trap->have_win: arg #4/arg #2
- */
-void
-async_err(void)
-{}
-
-/*
- * The clr_datapath function clears any error bits set in the UDB regs.
- */
-void
-clr_datapath(void)
-{}
-
-/*
- * The get_udb_errors() function gets the current value of the
- * Datapath Error Registers.
- */
-/*ARGSUSED*/
-void
-get_udb_errors(uint64_t *udbh, uint64_t *udbl)
-{
-	*udbh = 0;
-	*udbl = 0;
-}
-
-#else 	/* lint */
-
 	ENTRY_NP(ce_err)
 	ldxa	[%g0]ASI_AFSR, %g3	! save afsr in g3
 
@@ -1219,28 +1064,7 @@
 	  stx	%o2, [%o1]
 	SET_SIZE(get_udb_errors)
 
-#endif /* lint */
-
-#if defined(lint)
 /*
- * The itlb_rd_entry and dtlb_rd_entry functions return the tag portion of the
- * tte, the virtual address, and the ctxnum of the specified tlb entry.  They
- * should only be used in places where you have no choice but to look at the
- * tlb itself.
- *
- * Note: These two routines are required by the Estar "cpr" loadable module.
- */
-/*ARGSUSED*/
-void
-itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag)
-{}
-
-/*ARGSUSED*/
-void
-dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag)
-{}
-#else 	/* lint */
-/*
  * NB - In Spitfire cpus, when reading a tte from the hardware, we
  * need to clear [42-41] because the general definitions in pte.h
  * define the PA to be [42-13] whereas Spitfire really uses [40-13].
@@ -1286,26 +1110,7 @@
 	retl
 	  stx	%o5, [%o2]
 	SET_SIZE(dtlb_rd_entry)
-#endif /* lint */
 
-#if defined(lint)
-
-/*
- * routines to get and set the LSU register
- */
-uint64_t
-get_lsu(void)
-{
-	return ((uint64_t)0);
-}
-
-/*ARGSUSED*/
-void
-set_lsu(uint64_t lsu)
-{}
-
-#else /* lint */
-
 	ENTRY(set_lsu)
 	stxa	%o0, [%g0]ASI_LSU		! store to LSU
 	retl
@@ -1317,9 +1122,6 @@
 	ldxa	[%g0]ASI_LSU, %o0		! load LSU
 	SET_SIZE(get_lsu)
 
-#endif /* lint */
-
-#ifndef lint
 	/*
 	 * Clear the NPT (non-privileged trap) bit in the %tick
 	 * registers. In an effort to make the change in the
@@ -1458,31 +1260,13 @@
 	retl
 	wrpr	%g0, %o5, %pstate
 	SET_SIZE(check_ecache_line)
-#endif /* lint */
 
-#if defined(lint)
-uint64_t
-read_and_clear_afsr()
-{
-	return ((uint64_t)0);
-}
-#else	/* lint */
 	ENTRY(read_and_clear_afsr)
 	ldxa	[%g0]ASI_AFSR, %o0
 	retl
 	  stxa	%o0, [%g0]ASI_AFSR		! clear AFSR
 	SET_SIZE(read_and_clear_afsr)
-#endif	/* lint */
 
-#if defined(lint)
-/* ARGSUSED */
-void
-scrubphys(uint64_t paddr, int ecache_size)
-{
-}
-
-#else	/* lint */
-
 /*
  * scrubphys - Pass in the aligned physical memory address that you want
  * to scrub, along with the ecache size.
@@ -1609,26 +1393,6 @@
 	membar	#Sync			! move the data out of the load buffer
 	SET_SIZE(scrubphys)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*
- * clearphys - Pass in the aligned physical memory address that you want
- * to push out, as a 64 byte block of zeros, from the ecache zero-filled.
- * Since this routine does not bypass the ecache, it is possible that
- * it could generate a UE error while trying to clear the a bad line.
- * This routine clears and restores the error enable flag.
- * TBD - Hummingbird may need similar protection
- */
-/* ARGSUSED */
-void
-clearphys(uint64_t paddr, int ecache_size, int ecache_linesize)
-{
-}
-
-#else	/* lint */
-
 	ENTRY(clearphys)
 	or	%o2, %g0, %o3	! ecache linesize
 	or	%o1, %g0, %o2	! ecache size
@@ -1759,16 +1523,6 @@
 	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
 	SET_SIZE(clearphys)
 
-#endif	/* lint */
-
-#if defined(lint)
-/* ARGSUSED */
-void
-flushecacheline(uint64_t paddr, int ecache_size)
-{
-}
-
-#else	/* lint */
 /*
  * flushecacheline - This is a simpler version of scrubphys
  * which simply does a displacement flush of the line in
@@ -1882,16 +1636,6 @@
         wrpr    %g0, %o4, %pstate       
         SET_SIZE(flushecacheline)
 
-#endif	/* lint */
-
-#if defined(lint)
-/* ARGSUSED */
-void
-ecache_scrubreq_tl1(uint64_t inum, uint64_t dummy)
-{
-}
-
-#else	/* lint */
 /*
  * ecache_scrubreq_tl1 is the crosstrap handler called at ecache_calls_a_sec Hz
  * from the clock CPU.  It atomically increments the outstanding request
@@ -1928,15 +1672,6 @@
 	retry
 	SET_SIZE(ecache_scrubreq_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*ARGSUSED*/
-void
-write_ec_tag_parity(uint32_t id)
-{}
-#else /* lint */
-
 	/*
          * write_ec_tag_parity(), which zero's the ecache tag,
          * marks the state as invalid and writes good parity to the tag.
@@ -1976,15 +1711,6 @@
         wrpr    %g0, %o5, %pstate
         SET_SIZE(write_ec_tag_parity)
 
-#endif /* lint */
-
-#if defined(lint)
-/*ARGSUSED*/
-void
-write_hb_ec_tag_parity(uint32_t id)
-{}
-#else /* lint */
-
 	/*
          * write_hb_ec_tag_parity(), which zero's the ecache tag,
          * marks the state as invalid and writes good parity to the tag.
@@ -2029,19 +1755,8 @@
         wrpr    %g0, %o5, %pstate
         SET_SIZE(write_hb_ec_tag_parity)
 
-#endif /* lint */
-
 #define	VIS_BLOCKSIZE		64
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_blksuword32)
 	save	%sp, -SA(MINFRAME + 4), %sp
 
@@ -2106,4 +1821,3 @@
 
 	SET_SIZE(dtrace_blksuword32)
 
-#endif /* lint */
--- old/usr/src/uts/sun4u/cpu/spitfire_copy.s	Thu Nov 14 19:00:40 2019
+++ new/usr/src/uts/sun4u/cpu/spitfire_copy.s	Thu Nov 14 19:00:40 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/param.h>
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
@@ -36,9 +34,7 @@
 #include <sys/fsr.h>
 #include <sys/privregs.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 
 /*
@@ -482,15 +478,6 @@
 
 
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-kcopy(const void *from, void *to, size_t count)
-{ return(0); }
-
-#else	/* lint */
-
 	.seg	".text"
 	.align	4
 
@@ -617,7 +604,6 @@
 	call	panic
 	  nop
 	SET_SIZE(kcopy)
-#endif	/* lint */
 
 
 /*
@@ -627,15 +613,7 @@
  * Copy a page of memory.
  * Assumes double word alignment and a count >= 256.
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-bcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(bcopy)
 
 	save	%sp, -SA(MINFRAME + HWCOPYFRAMESIZE), %sp
@@ -1870,21 +1848,10 @@
 	andn	%i2, %o0, %i3		! return size of aligned bytes
 	SET_SIZE(bcopy)
 
-#endif	/* lint */
-
 /*
  * Block copy with possibly overlapped operands.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-ovbcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(ovbcopy)
 	tst	%o2			! check count
 	bgu,a	%ncc, 1f		! nothing to do or bad arguments
@@ -1927,8 +1894,6 @@
 	nop
 	SET_SIZE(ovbcopy)
 
-#endif	/* lint */
-
 /*
  * hwblkpagecopy()
  *
@@ -1936,12 +1901,6 @@
  * has already disabled kernel preemption and has checked
  * use_hw_bcopy.
  */
-#ifdef lint
-/*ARGSUSED*/
-void
-hwblkpagecopy(const void *src, void *dst)
-{ }
-#else /* lint */
 	ENTRY(hwblkpagecopy)
 	! get another window w/space for three aligned blocks of saved fpregs
 	save	%sp, -SA(MINFRAME + 4*64), %sp
@@ -2019,7 +1978,6 @@
 	ret
 	restore	%g0, 0, %o0
 	SET_SIZE(hwblkpagecopy)
-#endif	/* lint */
 
 
 /*
@@ -2131,15 +2089,6 @@
  * Copy kernel data to user space (copyout/xcopyout/xcopyout_little).
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * We save the arguments in the following registers in case of a fault:
  * 	kaddr - %g2
@@ -3392,18 +3341,7 @@
 	mov	-1, %o0
 	SET_SIZE(copyout)
 
-#endif	/* lint */
 
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout)
 	sethi	%hi(.xcopyout_err), REAL_LOFAULT
 	b	.do_copyout
@@ -3420,17 +3358,6 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyout)
 
-#endif	/* lint */
-	
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout_little(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout_little)
 	sethi	%hi(.little_err), %o4
 	ldn	[THREAD_REG + T_LOFAULT], %o5
@@ -3458,21 +3385,10 @@
 	mov	%g0, %o0		! return (0)
 	SET_SIZE(xcopyout_little)
 
-#endif	/* lint */
-
 /*
  * Copy user data to kernel space (copyin/xcopyin/xcopyin_little)
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyin)
 	sethi	%hi(.copyin_err), REAL_LOFAULT
 	or	REAL_LOFAULT, %lo(.copyin_err), REAL_LOFAULT
@@ -4630,17 +4546,6 @@
 	mov	-1, %o0
 	SET_SIZE(copyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin)
 	sethi	%hi(.xcopyin_err), REAL_LOFAULT
 	b	.do_copyin
@@ -4657,17 +4562,6 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin_little(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin_little)
 	sethi	%hi(.little_err), %o4
 	ldn	[THREAD_REG + T_LOFAULT], %o5
@@ -4701,22 +4595,12 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyin_little)
 
-#endif	/* lint */
 
-
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  * No fault handler installed (to be called under on_fault())
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-copyin_noerr(const void *ufrom, void *kto, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(copyin_noerr)
 	sethi	%hi(.copyio_noerr), REAL_LOFAULT
 	b	.do_copyin
@@ -4726,22 +4610,11 @@
 	  nop
 	SET_SIZE(copyin_noerr)
 
-#endif /* lint */
-
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  * No fault handler installed (to be called under on_fault())
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-copyout_noerr(const void *kfrom, void *uto, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(copyout_noerr)
 	sethi	%hi(.copyio_noerr), REAL_LOFAULT
 	b	.do_copyout
@@ -4748,20 +4621,6 @@
 	  or	REAL_LOFAULT, %lo(.copyio_noerr), REAL_LOFAULT
 	SET_SIZE(copyout_noerr)
 
-#endif /* lint */
-
-#if defined(lint)
-
-int use_hw_bcopy = 1;
-int use_hw_copyio = 1;
-int use_hw_bzero = 1;
-uint_t hw_copy_limit_1 = 0;
-uint_t hw_copy_limit_2 = 0;
-uint_t hw_copy_limit_4 = 0;
-uint_t hw_copy_limit_8 = 0;
-
-#else /* !lint */
-
 	.align	4
 	DGDEF(use_hw_bcopy)
 	.word	1
@@ -4780,7 +4639,6 @@
 
 	.align	64
 	.section ".text"
-#endif /* !lint */
 
 
 /*
@@ -4791,14 +4649,6 @@
  * Caller is responsible for ensuring use_hw_bzero is true and that
  * kpreempt_disable() has been called.
  */
-#ifdef lint
-/*ARGSUSED*/
-int
-hwblkclr(void *addr, size_t len)
-{ 
-	return(0);
-}
-#else /* lint */
 	! %i0 - start address
 	! %i1 - length of region (multiple of 64)
 	! %l0 - saved fprs
@@ -4898,16 +4748,7 @@
 	ret
 	restore	%g0, 0, %o0		! return (bzero or not)
 	SET_SIZE(hwblkclr)
-#endif	/* lint */
 
-#ifdef	lint
-/* Copy 32 bytes of data from src to dst using physical addresses */
-/*ARGSUSED*/
-void
-hw_pa_bcopy32(uint64_t src, uint64_t dst)
-{}
-#else	/*!lint */
-
 	/*
 	 * Copy 32 bytes of data from src (%o0) to dst (%o1)
 	 * using physical addresses.
@@ -4936,4 +4777,3 @@
 	retl
 	  wrpr    %g0, %g1, %pstate
 	SET_SIZE(hw_pa_bcopy32)
-#endif /* lint */
--- old/usr/src/uts/sun4u/cpu/us3_cheetah_asm.s	Thu Nov 14 19:00:41 2019
+++ new/usr/src/uts/sun4u/cpu/us3_cheetah_asm.s	Thu Nov 14 19:00:41 2019
@@ -26,11 +26,7 @@
  * Assembly code support for the Cheetah module
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -54,8 +50,6 @@
 #include <sys/traptrace.h>
 #endif /* TRAPTRACE */
 
-#if !defined(lint)
-
 /* BEGIN CSTYLED */
 
 /*
@@ -75,9 +69,7 @@
 
 /* END CSTYLED */
 
-#endif	/* !lint */
 
-
 /*
  * Fast ECC error at TL>0 handler
  * We get here via trap 70 at TL>0->Software trap 0 at TL>0.  We enter
@@ -86,14 +78,7 @@
  * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
  * us3_common_asm.s
  */
-#if defined(lint)
 
-void
-fast_ecc_tl1_err(void)
-{}
-
-#else	/* lint */
-
 	.section ".text"
 	.align	64
 	ENTRY_NP(fast_ecc_tl1_err)
@@ -312,38 +297,7 @@
 
 	SET_SIZE(fast_ecc_tl1_err)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * scrubphys - Pass in the aligned physical memory address
- * that you want to scrub, along with the ecache set size.
- *
- *	1) Displacement flush the E$ line corresponding to %addr.
- *	   The first ldxa guarantees that the %addr is no longer in
- *	   M, O, or E (goes to I or S (if instruction fetch also happens).
- *	2) "Write" the data using a CAS %addr,%g0,%g0.
- *	   The casxa guarantees a transition from I to M or S to M.
- *	3) Displacement flush the E$ line corresponding to %addr.
- *	   The second ldxa pushes the M line out of the ecache, into the
- *	   writeback buffers, on the way to memory.
- *	4) The "membar #Sync" pushes the cache line out of the writeback
- *	   buffers onto the bus, on the way to dram finally.
- *
- * This is a modified version of the algorithm suggested by Gary Lauterbach.
- * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
- * as modified, but then we found out that for spitfire, if it misses in the
- * E$ it will probably install as an M, but if it hits in the E$, then it
- * will stay E, if the store doesn't happen. So the first displacement flush
- * should ensure that the CAS will miss in the E$.  Arrgh.
- */
-/* ARGSUSED */
-void
-scrubphys(uint64_t paddr, int ecache_set_size)
-{}
-
-#else	/* lint */
 	ENTRY(scrubphys)
 	rdpr	%pstate, %o4
 	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
@@ -359,27 +313,7 @@
 	membar	#Sync			! move the data out of the load buffer
 	SET_SIZE(scrubphys)
 
-#endif	/* lint */
 
-
-#if defined(lint)
- /*
- * clearphys - Pass in the physical memory address of the checkblock
- * that you want to push out, cleared with a recognizable pattern,
- * from the ecache.
- *
- * To ensure that the ecc gets recalculated after the bad data is cleared,
- * we must write out enough data to fill the w$ line (64 bytes). So we read
- * in an entire ecache subblock's worth of data, and write it back out.
- * Then we overwrite the 16 bytes of bad data with the pattern.
- */
-/* ARGSUSED */
-void
-clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
-{
-}
-
-#else	/* lint */
 	ENTRY(clearphys)
 	/* turn off IE, AM bits */
 	rdpr	%pstate, %o4
@@ -427,23 +361,7 @@
 	  wrpr	%g0, %o4, %pstate
 	SET_SIZE(clearphys)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * Cheetah Ecache displacement flush the specified line from the E$
- *
- * Register usage:
- *	%o0 - 64 bit physical address for flushing
- *	%o1 - Ecache set size
- */
-/*ARGSUSED*/
-void
-ecache_flush_line(uint64_t flushaddr, int ec_set_size)
-{
-}
-#else	/* lint */
 	ENTRY(ecache_flush_line)
 
 	ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
@@ -451,22 +369,10 @@
 	retl
 	  nop
 	SET_SIZE(ecache_flush_line)
-#endif	/* lint */
 
 
-#if defined(lint)
-/*
- * This routine will not be called in Cheetah systems.
- */
-void
-flush_ipb(void)
-{ return; }
-
-#else	/* lint */
-
 	ENTRY(flush_ipb)
 	retl
 	nop
 	SET_SIZE(flush_ipb)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/cpu/us3_cheetahplus_asm.s	Thu Nov 14 19:00:42 2019
+++ new/usr/src/uts/sun4u/cpu/us3_cheetahplus_asm.s	Thu Nov 14 19:00:42 2019
@@ -25,11 +25,7 @@
  * Assembly code support for the Cheetah+ module
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -55,8 +51,6 @@
 #endif /* TRAPTRACE */
 
 
-#if !defined(lint)
-
 /* BEGIN CSTYLED */
 
 /*
@@ -147,8 +141,6 @@
 	or	l2_idx_out, scr3, l2_idx_out;					\
 	PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
 
-#endif	/* !lint */
-
 /*
  * Fast ECC error at TL>0 handler
  * We get here via trap 70 at TL>0->Software trap 0 at TL>0.  We enter
@@ -157,14 +149,7 @@
  * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
  * us3_common_asm.s
  */
-#if defined(lint)
 
-void
-fast_ecc_tl1_err(void)
-{}
-
-#else	/* lint */
-
 	.section ".text"
 	.align	64
 	ENTRY_NP(fast_ecc_tl1_err)
@@ -413,38 +398,7 @@
 
 	SET_SIZE(fast_ecc_tl1_err)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * scrubphys - Pass in the aligned physical memory address
- * that you want to scrub, along with the ecache set size.
- *
- *	1) Displacement flush the E$ line corresponding to %addr.
- *	   The first ldxa guarantees that the %addr is no longer in
- *	   M, O, or E (goes to I or S (if instruction fetch also happens).
- *	2) "Write" the data using a CAS %addr,%g0,%g0.
- *	   The casxa guarantees a transition from I to M or S to M.
- *	3) Displacement flush the E$ line corresponding to %addr.
- *	   The second ldxa pushes the M line out of the ecache, into the
- *	   writeback buffers, on the way to memory.
- *	4) The "membar #Sync" pushes the cache line out of the writeback
- *	   buffers onto the bus, on the way to dram finally.
- *
- * This is a modified version of the algorithm suggested by Gary Lauterbach.
- * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
- * as modified, but then we found out that for spitfire, if it misses in the
- * E$ it will probably install as an M, but if it hits in the E$, then it
- * will stay E, if the store doesn't happen. So the first displacement flush
- * should ensure that the CAS will miss in the E$.  Arrgh.
- */
-/* ARGSUSED */
-void
-scrubphys(uint64_t paddr, int ecache_set_size)
-{}
-
-#else	/* lint */
 	ENTRY(scrubphys)
 	rdpr	%pstate, %o4
 	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
@@ -470,27 +424,7 @@
 	membar	#Sync			! move the data out of the load buffer
 	SET_SIZE(scrubphys)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * clearphys - Pass in the physical memory address of the checkblock
- * that you want to push out, cleared with a recognizable pattern,
- * from the ecache.
- *
- * To ensure that the ecc gets recalculated after the bad data is cleared,
- * we must write out enough data to fill the w$ line (64 bytes). So we read
- * in an entire ecache subblock's worth of data, and write it back out.
- * Then we overwrite the 16 bytes of bad data with the pattern.
- */
-/* ARGSUSED */
-void
-clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
-{
-}
-
-#else	/* lint */
 	ENTRY(clearphys)
 	/* turn off IE, AM bits */
 	rdpr	%pstate, %o4
@@ -548,26 +482,7 @@
 	  wrpr	%g0, %o4, %pstate
 	SET_SIZE(clearphys)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * Cheetah+ Ecache displacement flush the specified line from the E$
- *
- * For Panther, this means flushing the specified line from both the
- * L2 cache and L3 cache.
- *
- * Register usage:
- *	%o0 - 64 bit physical address for flushing
- *	%o1 - Ecache set size
- */
-/*ARGSUSED*/
-void
-ecache_flush_line(uint64_t flushaddr, int ec_set_size)
-{
-}
-#else	/* lint */
 	ENTRY(ecache_flush_line)
 
 	GET_CPU_IMPL(%o3)		! Panther Ecache is flushed differently
@@ -584,16 +499,7 @@
 	retl
 	  nop
 	SET_SIZE(ecache_flush_line)
-#endif	/* lint */
 
-#if defined(lint)
-void
-set_afsr_ext(uint64_t afsr_ext)
-{
-	afsr_ext = afsr_ext;
-}
-#else /* lint */
-
 	ENTRY(set_afsr_ext)
 	set	ASI_AFSR_EXT_VA, %o1
 	stxa	%o0, [%o1]ASI_AFSR		! afsr_ext reg
@@ -602,36 +508,7 @@
 	nop
 	SET_SIZE(set_afsr_ext)
 
-#endif /* lint */
 
-
-#if defined(lint)
-/*
- * The CPU jumps here from the MMU exception handler if an ITLB parity
- * error is detected and we are running on Panther.
- *
- * In this routine we collect diagnostic information and write it to our
- * logout structure (if possible) and clear all ITLB entries that may have
- * caused our parity trap.
- * Then we call cpu_tlb_parity_error via systrap in order to drop down to TL0
- * and log any error messages. As for parameters to cpu_tlb_parity_error, we
- * send two:
- *
- * %g2	- Contains the VA whose lookup in the ITLB caused the parity error
- * %g3	- Contains the tlo_info field of the pn_tlb_logout logout struct,
- *	  regardless of whether or not we actually used the logout struct.
- *
- * In the TL0 handler (cpu_tlb_parity_error) we will compare those two
- * parameters to the data contained in the logout structure in order to
- * determine whether the logout information is valid for this particular
- * error or not.
- */
-void
-itlb_parity_trap(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(itlb_parity_trap)
 	/*
 	 * Collect important information about the trap which will be
@@ -754,35 +631,6 @@
 	  nop
 	SET_SIZE(itlb_parity_trap)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * The CPU jumps here from the MMU exception handler if a DTLB parity
- * error is detected and we are running on Panther.
- *
- * In this routine we collect diagnostic information and write it to our
- * logout structure (if possible) and clear all DTLB entries that may have
- * caused our parity trap.
- * Then we call cpu_tlb_parity_error via systrap in order to drop down to TL0
- * and log any error messages. As for parameters to cpu_tlb_parity_error, we
- * send two:
- *
- * %g2	- Contains the VA whose lookup in the DTLB caused the parity error
- * %g3	- Contains the tlo_info field of the pn_tlb_logout logout struct,
- *	  regardless of whether or not we actually used the logout struct.
- *
- * In the TL0 handler (cpu_tlb_parity_error) we will compare those two
- * parameters to the data contained in the logout structure in order to
- * determine whether the logout information is valid for this particular
- * error or not.
- */
-void
-dtlb_parity_trap(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(dtlb_parity_trap)
 	/*
 	 * Collect important information about the trap which will be
@@ -967,24 +815,7 @@
 	  nop
 	SET_SIZE(dtlb_parity_trap)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * Calculates the Panther TLB index based on a virtual address and page size
- *
- * Register usage:
- *	%o0 - virtual address whose index we want
- *	%o1 - Page Size of the TLB in question as encoded in the
- *	      ASI_[D|I]MMU_TAG_ACCESS_EXT register.
- */
-uint64_t
-pn_get_tlb_index(uint64_t va, uint64_t pg_sz)
-{
-	return ((va + pg_sz)-(va + pg_sz));
-}
-#else	/* lint */
 	ENTRY(pn_get_tlb_index)
 
 	PN_GET_TLB_INDEX(%o0, %o1)
@@ -992,20 +823,8 @@
 	retl
 	  nop
 	SET_SIZE(pn_get_tlb_index)
-#endif	/* lint */
 
 
-#if defined(lint)
-/*
- * For Panther CPUs we need to flush the IPB after any I$ or D$
- * parity errors are detected.
- */
-void
-flush_ipb(void)
-{ return; }
-
-#else	/* lint */
-
 	ENTRY(flush_ipb)
 	clr	%o0
 
@@ -1022,6 +841,4 @@
 	nop
 	SET_SIZE(flush_ipb)
 
-#endif	/* lint */
 
-
--- old/usr/src/uts/sun4u/cpu/us3_common_asm.s	Thu Nov 14 19:00:42 2019
+++ new/usr/src/uts/sun4u/cpu/us3_common_asm.s	Thu Nov 14 19:00:42 2019
@@ -25,9 +25,7 @@
  * Assembly code support for Cheetah/Cheetah+ modules
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* !lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -51,8 +49,6 @@
 #include <sys/traptrace.h>
 #endif /* TRAPTRACE */
 
-#if !defined(lint)
-
 /* BEGIN CSTYLED */
 
 #define	DCACHE_FLUSHPAGE(arg1, arg2, tmp1, tmp2, tmp3)			\
@@ -169,21 +165,10 @@
 
 /* END CSTYLED */
 
-#endif	/* !lint */
-
 /*
  * Cheetah MMU and Cache operations.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flushpage(caddr_t vaddr, uint64_t sfmmup)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushpage)
 	/*
 	 * flush page from the tlb
@@ -252,16 +237,6 @@
 	wrpr	%g0, %o5, %pstate		/* enable interrupts */
 	SET_SIZE(vtag_flushpage)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-vtag_flushall(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP2(vtag_flushall, demap_all)
 	/*
 	 * flush the tlb
@@ -276,18 +251,7 @@
 	SET_SIZE(demap_all)
 	SET_SIZE(vtag_flushall)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushpage_tl1)
 	/*
 	 * x-trap to flush page from tlb and tsb
@@ -332,18 +296,7 @@
 	retry
 	SET_SIZE(vtag_flushpage_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flush_pgcnt_tl1)
 	/*
 	 * x-trap to flush pgcnt MMU_PAGESIZE pages from tlb
@@ -422,17 +375,6 @@
 	retry
 	SET_SIZE(vtag_flush_pgcnt_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushall_tl1)
 	/*
 	 * x-trap to flush tlb
@@ -443,18 +385,7 @@
 	retry
 	SET_SIZE(vtag_flushall_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushpage(pfn_t pfnum, int vcolor)
-{}
-
-#else	/* lint */
-
 /*
  * vac_flushpage(pfnum, color)
  *	Flush 1 8k page of the D-$ with physical page = pfnum
@@ -479,18 +410,7 @@
 	  nop
 	SET_SIZE(vac_flushpage)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vac_flushpage_tl1)
 	/*
 	 * x-trap to flush page from the d$
@@ -501,18 +421,7 @@
 	retry
 	SET_SIZE(vac_flushpage_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushcolor(int vcolor, pfn_t pfnum)
-{}
-
-#else	/* lint */
-
 	ENTRY(vac_flushcolor)
 	/*
 	 * %o0 = vcolor
@@ -525,18 +434,7 @@
 	  nop
 	SET_SIZE(vac_flushcolor)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushcolor_tl1(uint64_t vcolor, uint64_t pfnum)
-{}
-
-#else	/* lint */
-
 	ENTRY(vac_flushcolor_tl1)
 	/*
 	 * %g1 = vcolor
@@ -548,18 +446,6 @@
 	retry
 	SET_SIZE(vac_flushcolor_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
- 
-int
-idsr_busy(void)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 /*
  * Determine whether or not the IDSR is busy.
  * Entry: no arguments
@@ -576,22 +462,6 @@
 	nop
 	SET_SIZE(idsr_busy)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-/* ARGSUSED */
-void
-init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-#else	/* lint */
-
 	.global _dispatch_status_busy
 _dispatch_status_busy:
 	.asciz	"ASI_INTR_DISPATCH_STATUS error: busy"
@@ -645,20 +515,9 @@
 	SET_SIZE(init_mondo_nocheck)
 	SET_SIZE(init_mondo)
 
-#endif	/* lint */
 
-
 #if !(defined(JALAPENO) || defined(SERRANO))
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-shipit(int upaid, int bn)
-{ return; }
-
-#else	/* lint */
-
 /*
  * Ship mondo to aid using busy/nack pair bn
  */
@@ -673,20 +532,9 @@
 	nop
 	SET_SIZE(shipit)
 
-#endif	/* lint */
-
 #endif	/* !(JALAPENO || SERRANO) */
 
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-flush_instr_mem(caddr_t vaddr, size_t len)
-{}
-
-#else	/* lint */
-
 /*
  * flush_instr_mem:
  *	Flush 1 page of the I-$ starting at vaddr
@@ -705,20 +553,9 @@
 	nop
 	SET_SIZE(flush_instr_mem)
 
-#endif	/* lint */
 
-
 #if defined(CPU_IMP_ECACHE_ASSOC)
 
-#if defined(lint)
-
-/* ARGSUSED */
-uint64_t
-get_ecache_ctrl(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(get_ecache_ctrl)
 	GET_CPU_IMPL(%o0)
 	cmp	%o0, JAGUAR_IMPL
@@ -738,8 +575,6 @@
 	  nop
 	SET_SIZE(get_ecache_ctrl)
 
-#endif	/* lint */
-
 #endif	/* CPU_IMP_ECACHE_ASSOC */
 
 
@@ -751,15 +586,7 @@
  *	%o1 - ecache size
  *	%o2 - ecache linesize
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-void
-flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
-{}
-
-#else /* !lint */
-
 	ENTRY(flush_ecache)
 
 	/*
@@ -777,19 +604,9 @@
 	nop
 	SET_SIZE(flush_ecache)
 
-#endif /* lint */
-
 #endif	/* !(JALAPENO || SERRANO) */
 
 
-#if defined(lint)
-
-void
-flush_dcache(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(flush_dcache)
 	ASM_LD(%o0, dcache_size)
 	ASM_LD(%o1, dcache_linesize)
@@ -798,17 +615,7 @@
 	nop
 	SET_SIZE(flush_dcache)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-void
-flush_icache(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(flush_icache)
 	GET_CPU_PRIVATE_PTR(%g0, %o0, %o2, flush_icache_1);
 	ld	[%o0 + CHPR_ICACHE_LINESIZE], %o1
@@ -823,19 +630,6 @@
 	nop
 	SET_SIZE(flush_icache)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-kdi_flush_idcache(int dcache_size, int dcache_lsize, int icache_size, 
-    int icache_lsize)
-{
-}
-
-#else	/* lint */
-
 	ENTRY(kdi_flush_idcache)
 	CH_DCACHE_FLUSHALL(%o0, %o1, %g1)
 	CH_ICACHE_FLUSHALL(%o2, %o3, %g1, %g2)
@@ -844,16 +638,6 @@
 	nop
 	SET_SIZE(kdi_flush_idcache)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-flush_pcache(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(flush_pcache)
 	PCACHE_FLUSHALL(%o0, %o1, %o2)
 	retl
@@ -860,20 +644,9 @@
 	nop
 	SET_SIZE(flush_pcache)
 
-#endif	/* lint */
 
-
 #if defined(CPU_IMP_L1_CACHE_PARITY)
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-get_dcache_dtag(uint32_t dcache_idx, uint64_t *data)
-{}
-
-#else	/* lint */
-
 /*
  * Get dcache data and tag.  The Dcache data is a pointer to a ch_dc_data_t
  * structure (see cheetahregs.h):
@@ -951,18 +724,7 @@
 	  wrpr	%g0, %o5, %pstate	
 	SET_SIZE(get_dcache_dtag)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-get_icache_dtag(uint32_t ecache_idx, uint64_t *data)
-{}
-
-#else	/* lint */
-
 /*
  * Get icache data and tag.  The data argument is a pointer to a ch_ic_data_t
  * structure (see cheetahregs.h):
@@ -1004,17 +766,6 @@
 	  wrpr	%g0, %o5, %pstate	
 	SET_SIZE(get_icache_dtag)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-get_pcache_dtag(uint32_t pcache_idx, uint64_t *data)
-{}
-
-#else	/* lint */
-
 /*
  * Get pcache data and tags.
  * inputs:
@@ -1050,19 +801,8 @@
 	  wrpr	%g0, %o5, %pstate	
 	SET_SIZE(get_pcache_dtag)
 
-#endif	/* lint */
-
 #endif	/* CPU_IMP_L1_CACHE_PARITY */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-set_dcu(uint64_t dcu)
-{}
-
-#else	/* lint */
-
 /*
  * re-enable the i$, d$, w$, and p$ according to bootup cache state.
  * Turn on WE, HPE, SPE, PE, IC, and DC bits defined as DCU_CACHE.
@@ -1075,19 +815,7 @@
 	nop
 	SET_SIZE(set_dcu)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-uint64_t
-get_dcu(void)
-{
-	return ((uint64_t)0);
-}
-
-#else	/* lint */
-
 /*
  * Return DCU register.
  */
@@ -1097,8 +825,6 @@
 	nop
 	SET_SIZE(get_dcu)
 
-#endif	/* lint */
-
 /*
  * Cheetah/Cheetah+ level 15 interrupt handler trap table entry.
  *
@@ -1109,29 +835,12 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
 
-void
-ch_pil15_interrupt_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(ch_pil15_interrupt_instr)
 	ASM_JMP(%g1, ch_pil15_interrupt)
 	SET_SIZE(ch_pil15_interrupt_instr)
 
-#endif
 
-
-#if defined(lint)
-
-void
-ch_pil15_interrupt(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(ch_pil15_interrupt)
 
 	/*
@@ -1185,7 +894,6 @@
 	  mov	PIL_15, %g4
 
 	SET_SIZE(ch_pil15_interrupt)
-#endif
 
 
 /*
@@ -1278,14 +986,6 @@
  *     be relocatable.
  */
 
-#if defined(lint)
-
-void
-fecc_err_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fecc_err_instr)
 	membar	#Sync			! Cheetah requires membar #Sync
 
@@ -1300,19 +1000,9 @@
 	ASM_JMP(%g4, fast_ecc_err)
 	SET_SIZE(fecc_err_instr)
 
-#endif	/* lint */
 
-
 #if !(defined(JALAPENO) || defined(SERRANO))
 
-#if defined(lint)
-
-void
-fast_ecc_err(void)
-{}
-
-#else	/* lint */
-
 	.section ".text"
 	.align	64
 	ENTRY_NP(fast_ecc_err)
@@ -1452,8 +1142,6 @@
 
 	SET_SIZE(fast_ecc_err)
 
-#endif	/* lint */
-
 #endif	/* !(JALAPENO || SERRANO) */
 
 
@@ -1511,20 +1199,10 @@
  *     be relocatable.
  */
 
-#if defined(lint)
-
-void
-fecc_err_tl1_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fecc_err_tl1_instr)
 	CH_ERR_TL1_TRAPENTRY(SWTRAP_0);
 	SET_SIZE(fecc_err_tl1_instr)
 
-#endif	/* lint */
-
 /*
  * Software trap 0 at TL>0.
  * tt1_swtrap0 is replaced by fecc_err_tl1_cont_instr in cpu_init_trap of
@@ -1537,29 +1215,12 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
 
-void
-fecc_err_tl1_cont_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fecc_err_tl1_cont_instr)
 	CH_ERR_TL1_SWTRAPENTRY(fast_ecc_tl1_err)
 	SET_SIZE(fecc_err_tl1_cont_instr)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-void
-ce_err(void)
-{}
-
-#else	/* lint */
-
 /*
  * The ce_err function handles disrupting trap type 0x63 at TL=0.
  *
@@ -1738,21 +1399,7 @@
 	  movl	%icc, PIL_14, %g4
 	SET_SIZE(ce_err)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/*
- * This trap cannot happen at TL>0 which means this routine will never
- * actually be called and so we treat this like a BAD TRAP panic.
- */
-void
-ce_err_tl1(void)
-{}
-
-#else	/* lint */
-
 	.align	64
 	ENTRY_NP(ce_err_tl1)
 
@@ -1761,17 +1408,7 @@
 
 	SET_SIZE(ce_err_tl1)
 
-#endif	/* lint */
-
 	
-#if defined(lint)
-
-void
-async_err(void)
-{}
-
-#else	/* lint */
-
 /*
  * The async_err function handles deferred trap types 0xA 
  * (instruction_access_error) and 0x32 (data_access_error) at TL>=0.
@@ -1969,8 +1606,6 @@
 	  mov	PIL_15, %g4		! run at pil 15
 	SET_SIZE(async_err)
 
-#endif	/* lint */
-
 #if defined(CPU_IMP_L1_CACHE_PARITY)
 
 /*
@@ -1981,13 +1616,6 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-dcache_parity_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(dcache_parity_instr)
 	membar	#Sync			! Cheetah+ requires membar #Sync
 	set	cpu_parity_error, %g1
@@ -1998,9 +1626,7 @@
 	  mov	PIL_15, %g4		! run at pil 15
 	SET_SIZE(dcache_parity_instr)
 
-#endif	/* lint */
 
-
 /*
  * D$ parity error trap (trap 71) at TL>0.
  * tt1_dperr is replaced by dcache_parity_tl1_instr in cpu_init_trap of
@@ -2010,20 +1636,11 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-dcache_parity_tl1_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(dcache_parity_tl1_instr)
 	CH_ERR_TL1_TRAPENTRY(SWTRAP_1);
 	SET_SIZE(dcache_parity_tl1_instr)
 
-#endif	/* lint */
 
-
 /*
  * Software trap 1 at TL>0.
  * tt1_swtrap1 is replaced by dcache_parity_tl1_cont_instr in cpu_init_trap
@@ -2036,32 +1653,16 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-dcache_parity_tl1_cont_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(dcache_parity_tl1_cont_instr)
 	CH_ERR_TL1_SWTRAPENTRY(dcache_parity_tl1_err);
 	SET_SIZE(dcache_parity_tl1_cont_instr)
 
-#endif	/* lint */
-
 /*
  * D$ parity error at TL>0 handler
  * We get here via trap 71 at TL>0->Software trap 1 at TL>0.  We enter
  * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
  */
-#if defined(lint)
 
-void
-dcache_parity_tl1_err(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(dcache_parity_tl1_err)
 
 	/*
@@ -2152,8 +1753,6 @@
 	CH_ERR_TL1_EXIT;
 	SET_SIZE(dcache_parity_tl1_err)
 
-#endif	/* lint */
-
 /*
  * I$ parity error trap (trap 72) at TL=0.
  * tt0_iperr is replaced by icache_parity_instr in cpu_init_trap of
@@ -2162,14 +1761,7 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
 
-void
-icache_parity_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(icache_parity_instr)
 	membar	#Sync			! Cheetah+ requires membar #Sync
 	set	cpu_parity_error, %g1
@@ -2180,8 +1772,6 @@
 	  mov	PIL_15, %g4		! run at pil 15
 	SET_SIZE(icache_parity_instr)
 
-#endif	/* lint */
-
 /*
  * I$ parity error trap (trap 72) at TL>0.
  * tt1_iperr is replaced by icache_parity_tl1_instr in cpu_init_trap of
@@ -2191,19 +1781,10 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-icache_parity_tl1_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(icache_parity_tl1_instr)
 	CH_ERR_TL1_TRAPENTRY(SWTRAP_2);
 	SET_SIZE(icache_parity_tl1_instr)
 
-#endif	/* lint */
-
 /*
  * Software trap 2 at TL>0.
  * tt1_swtrap2 is replaced by icache_parity_tl1_cont_instr in cpu_init_trap
@@ -2216,33 +1797,17 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-icache_parity_tl1_cont_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(icache_parity_tl1_cont_instr)
 	CH_ERR_TL1_SWTRAPENTRY(icache_parity_tl1_err);
 	SET_SIZE(icache_parity_tl1_cont_instr)
 
-#endif	/* lint */
 
-
 /*
  * I$ parity error at TL>0 handler
  * We get here via trap 72 at TL>0->Software trap 2 at TL>0.  We enter
  * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
  */
-#if defined(lint)
 
-void
-icache_parity_tl1_err(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(icache_parity_tl1_err)
 
 	/*
@@ -2318,8 +1883,6 @@
 
 	SET_SIZE(icache_parity_tl1_err)
 
-#endif	/* lint */
-
 #endif	/* CPU_IMP_L1_CACHE_PARITY */
 
 
@@ -2332,15 +1895,6 @@
  * Note: These two routines are required by the Estar "cpr" loadable module.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(itlb_rd_entry)
 	sllx	%o0, 3, %o0
 	ldxa	[%o0]ASI_ITLB_ACCESS, %g1
@@ -2352,18 +1906,7 @@
 	  stx	%o5, [%o2]
 	SET_SIZE(itlb_rd_entry)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(dtlb_rd_entry)
 	sllx	%o0, 3, %o0
 	ldxa	[%o0]ASI_DTLB_ACCESS, %g1
@@ -2374,19 +1917,10 @@
 	retl
 	  stx	%o5, [%o2]
 	SET_SIZE(dtlb_rd_entry)
-#endif	/* lint */
 
 
 #if !(defined(JALAPENO) || defined(SERRANO))
 
-#if defined(lint)
-
-uint64_t
-get_safari_config(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(get_safari_config)
 	ldxa	[%g0]ASI_SAFARI_CONFIG, %o0
 	retl
@@ -2393,18 +1927,7 @@
 	nop
 	SET_SIZE(get_safari_config)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-set_safari_config(uint64_t safari_config)
-{}
-
-#else	/* lint */
-
 	ENTRY(set_safari_config)
 	stxa	%o0, [%g0]ASI_SAFARI_CONFIG
 	membar	#Sync
@@ -2412,18 +1935,9 @@
 	nop
 	SET_SIZE(set_safari_config)
 
-#endif	/* lint */
-
 #endif	/* !(JALAPENO || SERRANO) */
 
 
-#if defined(lint)
-
-void
-cpu_cleartickpnt(void)
-{}
-
-#else	/* lint */
 	/*
 	 * Clear the NPT (non-privileged trap) bit in the %tick/%stick
 	 * registers. In an effort to make the change in the
@@ -2463,26 +1977,9 @@
 	
 	SET_SIZE(cpu_clearticknpt)
 
-#endif	/* lint */
 
-
 #if defined(CPU_IMP_L1_CACHE_PARITY)
 
-#if defined(lint)
-/*
- * correct_dcache_parity(size_t size, size_t linesize)
- *
- * Correct D$ data parity by zeroing the data and initializing microtag
- * for all indexes and all ways of the D$.
- * 
- */
-/* ARGSUSED */
-void
-correct_dcache_parity(size_t size, size_t linesize)
-{}
-
-#else	/* lint */
-
 	ENTRY(correct_dcache_parity)
 	/*
 	 * Register Usage:
@@ -2544,23 +2041,9 @@
 	  nop
 	SET_SIZE(correct_dcache_parity)
 
-#endif	/* lint */
-
 #endif	/* CPU_IMP_L1_CACHE_PARITY */
 
 
-#if defined(lint)
-/*
- *  Get timestamp (stick).
- */
-/* ARGSUSED */
-void
-stick_timestamp(int64_t *ts)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(stick_timestamp)
 	rd	STICK, %g1	! read stick reg
 	sllx	%g1, 1, %g1
@@ -2570,21 +2053,7 @@
 	stx     %g1, [%o0]	! store the timestamp
 	SET_SIZE(stick_timestamp)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * Set STICK adjusted by skew.
- */
-/* ARGSUSED */	
-void
-stick_adj(int64_t skew)
-{
-}
-
-#else	/* lint */
-		
 	ENTRY_NP(stick_adj)
 	rdpr	%pstate, %g1		! save processor state
 	andn	%g1, PSTATE_IE, %g3
@@ -2602,21 +2071,6 @@
 	wrpr	%g1, %pstate		! restore processor state
 	SET_SIZE(stick_adj)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * Debugger-specific stick retrieval
- */
-/*ARGSUSED*/
-int
-kdi_get_stick(uint64_t *stickp)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 	ENTRY_NP(kdi_get_stick)
 	rd	STICK, %g1
 	stx	%g1, [%o0]
@@ -2624,47 +2078,6 @@
 	mov	%g0, %o0
 	SET_SIZE(kdi_get_stick)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * Invalidate the specified line from the D$.
- *
- * Register usage:
- *	%o0 - index for the invalidation, specifies DC_way and DC_addr
- *
- * ASI_DC_TAG, 0x47, is used in the following manner. A 64-bit value is
- * stored to a particular DC_way and DC_addr in ASI_DC_TAG.
- *
- * The format of the stored 64-bit value is:
- *
- *	+----------+--------+----------+
- *	| Reserved | DC_tag | DC_valid |
- *	+----------+--------+----------+
- *       63      31 30     1	      0
- *
- * DC_tag is the 30-bit physical tag of the associated line.
- * DC_valid is the 1-bit valid field for both the physical and snoop tags.
- *
- * The format of the 64-bit DC_way and DC_addr into ASI_DC_TAG is:
- *
- *	+----------+--------+----------+----------+
- *	| Reserved | DC_way | DC_addr  | Reserved |
- *	+----------+--------+----------+----------+
- *       63      16 15    14 13       5 4        0
- *
- * DC_way is a 2-bit index that selects one of the 4 ways.
- * DC_addr is a 9-bit index that selects one of 512 tag/valid fields.
- *
- * Setting the DC_valid bit to zero for the specified DC_way and
- * DC_addr index into the D$ results in an invalidation of a D$ line.
- */
-/*ARGSUSED*/
-void
-dcache_inval_line(int index)
-{
-}
-#else	/* lint */
 	ENTRY(dcache_inval_line)
 	sll	%o0, 5, %o0		! shift index into DC_way and DC_addr
 	stxa	%g0, [%o0]ASI_DC_TAG	! zero the DC_valid and DC_tag bits
@@ -2672,62 +2085,7 @@
 	retl
 	nop
 	SET_SIZE(dcache_inval_line)
-#endif	/* lint */
 
-#if defined(lint)
-/*
- * Invalidate the entire I$
- *
- * Register usage:
- *	%o0 - specifies IC_way, IC_addr, IC_tag
- *	%o1 - scratch
- *	%o2 - used to save and restore DCU value
- *	%o3 - scratch
- *	%o5 - used to save and restore PSTATE
- *
- * Due to the behavior of the I$ control logic when accessing ASI_IC_TAG,
- * the I$ should be turned off. Accesses to ASI_IC_TAG may collide and
- * block out snoops and invalidates to the I$, causing I$ consistency
- * to be broken. Before turning on the I$, all I$ lines must be invalidated.
- *
- * ASI_IC_TAG, 0x67, is used in the following manner. A 64-bit value is
- * stored to a particular IC_way, IC_addr, IC_tag in ASI_IC_TAG. The
- * info below describes store (write) use of ASI_IC_TAG. Note that read
- * use of ASI_IC_TAG behaves differently.
- *
- * The format of the stored 64-bit value is:
- *
- *	+----------+--------+---------------+-----------+
- *	| Reserved | Valid  | IC_vpred<7:0> | Undefined |
- *	+----------+--------+---------------+-----------+
- *       63      55    54    53           46 45        0
- *
- * Valid is the 1-bit valid field for both the physical and snoop tags.
- * IC_vpred is the 8-bit LPB bits for 8 instructions starting at
- *	the 32-byte boundary aligned address specified by IC_addr.
- *
- * The format of the 64-bit IC_way, IC_addr, IC_tag into ASI_IC_TAG is:
- *
- *	+----------+--------+---------+--------+---------+
- *	| Reserved | IC_way | IC_addr | IC_tag |Reserved |
- *	+----------+--------+---------+--------+---------+
- *       63      16 15    14 13      5 4      3 2       0
- *
- * IC_way is a 2-bit index that selects one of the 4 ways.
- * IC_addr[13:6] is an 8-bit index that selects one of 256 valid fields.
- * IC_addr[5] is a "don't care" for a store.
- * IC_tag set to 2 specifies that the stored value is to be interpreted
- *	as containing Valid and IC_vpred as described above.
- *
- * Setting the Valid bit to zero for the specified IC_way and
- * IC_addr index into the I$ results in an invalidation of an I$ line.
- */
-/*ARGSUSED*/
-void
-icache_inval_all(void)
-{
-}
-#else	/* lint */
 	ENTRY(icache_inval_all)
 	rdpr	%pstate, %o5
 	andn	%o5, PSTATE_IE, %o3
@@ -2746,17 +2104,8 @@
 	retl
 	wrpr	%g0, %o5, %pstate	! restore earlier pstate
 	SET_SIZE(icache_inval_all)
-#endif	/* lint */
 
 
-#if defined(lint)
-/* ARGSUSED */
-void
-cache_scrubreq_tl1(uint64_t inum, uint64_t index)
-{
-}
-
-#else	/* lint */
 /*
  * cache_scrubreq_tl1 is the crosstrap handler called on offlined cpus via a 
  * crosstrap.  It atomically increments the outstanding request counter and,
@@ -2794,18 +2143,7 @@
 	retry
 	SET_SIZE(cache_scrubreq_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-get_cpu_error_state(ch_cpu_errors_t *cpu_error_regs)
-{}
-
-#else	/* lint */
-
 /*
  * Get the error state for the processor.
  * Note that this must not be used at TL>0
@@ -2853,27 +2191,7 @@
 	retl
 	stx	%o1, [%o0 + CH_CPU_ERRORS_AFAR]
 	SET_SIZE(get_cpu_error_state)
-#endif	/* lint */
 
-#if defined(lint)
-
-/*
- * Check a page of memory for errors.
- *
- * Load each 64 byte block from physical memory.
- * Check AFSR after each load to see if an error
- * was caused. If so, log/scrub that error.
- *
- * Used to determine if a page contains
- * CEs when CEEN is disabled.
- */
-/*ARGSUSED*/
-void
-cpu_check_block(caddr_t va, uint_t psz)
-{}
-
-#else	/* lint */
-
 	ENTRY(cpu_check_block)
 	!
 	! get a new window with room for the error regs
@@ -2912,22 +2230,6 @@
 
 	SET_SIZE(cpu_check_block)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*
- * Perform a cpu logout called from C.  This is used where we did not trap
- * for the error but still want to gather "what we can".  Caller must make
- * sure cpu private area exists and that the indicated logout area is free
- * for use, and that we are unable to migrate cpus.
- */
-/*ARGSUSED*/
-void
-cpu_delayed_logout(uint64_t afar, ch_cpu_logout_t *clop)
-{ }
-
-#else
 	ENTRY(cpu_delayed_logout)
 	rdpr	%pstate, %o2
 	andn	%o2, PSTATE_IE, %o2
@@ -2946,17 +2248,6 @@
 	  nop
 	SET_SIZE(cpu_delayed_logout)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_blksuword32)
 	save	%sp, -SA(MINFRAME + 4), %sp
 
@@ -3021,19 +2312,8 @@
 
 	SET_SIZE(dtrace_blksuword32)
 
-#endif /* lint */
-
 #ifdef	CHEETAHPLUS_ERRATUM_25
 
-#if	defined(lint)
-/*
- * Claim a chunk of physical address space.
- */
-/*ARGSUSED*/
-void
-claimlines(uint64_t pa, size_t sz, int stride)
-{}
-#else	/* lint */
 	ENTRY(claimlines)
 1:
 	subcc	%o1, %o2, %o1
@@ -3044,19 +2324,7 @@
 	retl
 	nop
 	SET_SIZE(claimlines)
-#endif	/* lint */
 
-#if	defined(lint)
-/*
- * CPU feature initialization,
- * turn BPE off,
- * get device id.
- */
-/*ARGSUSED*/
-void
-cpu_feature_init(void)
-{}
-#else	/* lint */
 	ENTRY(cpu_feature_init)
 	save	%sp, -SA(MINFRAME), %sp
 	sethi	%hi(cheetah_bpe_off), %o0
@@ -3089,18 +2357,7 @@
 	ret
 	  restore
 	SET_SIZE(cpu_feature_init)
-#endif	/* lint */
 
-#if	defined(lint)
-/*
- * Copy a tsb entry atomically, from src to dest.
- * src must be 128 bit aligned.
- */
-/*ARGSUSED*/
-void
-copy_tsb_entry(uintptr_t src, uintptr_t dest)
-{}
-#else	/* lint */
 	ENTRY(copy_tsb_entry)
 	ldda	[%o0]ASI_NQUAD_LD, %o2		! %o2 = tag, %o3 = data
 	stx	%o2, [%o1]
@@ -3108,21 +2365,11 @@
 	retl
 	nop
 	SET_SIZE(copy_tsb_entry)
-#endif	/* lint */
 
 #endif	/* CHEETAHPLUS_ERRATUM_25 */
 
 #ifdef	CHEETAHPLUS_ERRATUM_34
 
-#if	defined(lint)
-
-/*ARGSUSED*/
-void
-itlb_erratum34_fixup(void)
-{}
-
-#else	/* lint */
-
 	!
 	! In Cheetah+ erratum 34, under certain conditions an ITLB locked
 	! index 0 TTE will erroneously be displaced when a new TTE is
@@ -3187,17 +2434,6 @@
 	  wrpr	%g0, %o3, %pstate		! Enable interrupts
 	SET_SIZE(itlb_erratum34_fixup)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/*ARGSUSED*/
-void
-dtlb_erratum34_fixup(void)
-{}
-
-#else	/* lint */
-
 	!
 	! In Cheetah+ erratum 34, under certain conditions a DTLB locked
 	! index 0 TTE will erroneously be displaced when a new TTE is
@@ -3256,7 +2492,5 @@
 	  wrpr	%g0, %o3, %pstate		! Enable interrupts
 	SET_SIZE(dtlb_erratum34_fixup)
 
-#endif	/* lint */
-
 #endif	/* CHEETAHPLUS_ERRATUM_34 */
 
--- old/usr/src/uts/sun4u/cpu/us3_jalapeno_asm.s	Thu Nov 14 19:00:43 2019
+++ new/usr/src/uts/sun4u/cpu/us3_jalapeno_asm.s	Thu Nov 14 19:00:43 2019
@@ -26,11 +26,7 @@
  * Assembly code support for the jalapeno module
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -54,8 +50,6 @@
 #include <sys/traptrace.h>
 #endif /* TRAPTRACE */
 
-#if !defined(lint)
-
 /* BEGIN CSTYLED */
 
 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
@@ -324,17 +318,6 @@
 
 /* END CSTYLED */
 
-#endif	/* !lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-shipit(int upaid, int bn)
-{ return; }
-
-#else	/* lint */
-
 /*
  * Ship mondo to aid using implicit busy/nack pair (bn ignored)
  */
@@ -347,9 +330,7 @@
 	nop
 	SET_SIZE(shipit)
 
-#endif	/* lint */
 
-
 /*
  * flush_ecache:
  *	%o0 - 64 bit physical address
@@ -356,15 +337,7 @@
  *	%o1 - ecache size
  *	%o2 - ecache linesize
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-void
-flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
-{}
-
-#else /* !lint */
-
 	ENTRY(flush_ecache)
 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
 	CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_1);
@@ -387,17 +360,7 @@
 	nop
 	SET_SIZE(flush_ecache)
 
-#endif /* lint */
 
-
-#if defined(lint)
-
-void
-fast_ecc_err(void)
-{}
-
-#else	/* lint */
-
 	.section ".text"
 	.align	64
 	ENTRY_NP(fast_ecc_err)
@@ -528,9 +491,7 @@
 
 	SET_SIZE(fast_ecc_err)
 
-#endif	/* lint */
 
-
 /*
  * Fast ECC error at TL>0 handler
  * We get here via trap 70 at TL>0->Software trap 0 at TL>0.  We enter
@@ -539,14 +500,7 @@
  * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
  * us3_common_asm.s
  */
-#if defined(lint)
 
-void
-fast_ecc_tl1_err(void)
-{}
-
-#else	/* lint */
-
 	.section ".text"
 	.align	64
 	ENTRY_NP(fast_ecc_tl1_err)
@@ -770,31 +724,7 @@
 
 	SET_SIZE(fast_ecc_tl1_err)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-uint64_t
-get_jbus_config(void)
-{ return (0); }
-
-/* ARGSUSED */
-void
-set_jbus_config(uint64_t jbus_config)
-{}
-
-/* ARGSUSED */
-void
-set_mcu_ctl_reg1(uint64_t mcu_ctl)
-{}
-
-uint64_t
-get_mcu_ctl_reg1(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(get_jbus_config)
 	ldxa	[%g0]ASI_JBUS_CONFIG, %o0
 	retl
@@ -823,38 +753,7 @@
 	nop
 	SET_SIZE(set_mcu_ctl_reg1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * scrubphys - Pass in the aligned physical memory address
- * that you want to scrub, along with the ecache set size.
- *
- *	1) Displacement flush the E$ line corresponding to %addr.
- *	   The first ldxa guarantees that the %addr is no longer in
- *	   M, O, or E (goes to I or S (if instruction fetch also happens).
- *	2) "Write" the data using a CAS %addr,%g0,%g0.
- *	   The casxa guarantees a transition from I to M or S to M.
- *	3) Displacement flush the E$ line corresponding to %addr.
- *	   The second ldxa pushes the M line out of the ecache, into the
- *	   writeback buffers, on the way to memory.
- *	4) The "membar #Sync" pushes the cache line out of the writeback
- *	   buffers onto the bus, on the way to dram finally.
- *
- * This is a modified version of the algorithm suggested by Gary Lauterbach.
- * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
- * as modified, but then we found out that for spitfire, if it misses in the
- * E$ it will probably install as an M, but if it hits in the E$, then it
- * will stay E, if the store doesn't happen. So the first displacement flush
- * should ensure that the CAS will miss in the E$.  Arrgh.
- */
-/* ARGSUSED */
-void
-scrubphys(uint64_t paddr, int ecache_set_size)
-{}
-
-#else	/* lint */
 	ENTRY(scrubphys)
 	rdpr	%pstate, %o4
 	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
@@ -882,27 +781,7 @@
 	membar	#Sync			! move the data out of the load buffer
 	SET_SIZE(scrubphys)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * clearphys - Pass in the physical memory address of the checkblock
- * that you want to push out, cleared with a recognizable pattern,
- * from the ecache.
- *
- * To ensure that the ecc gets recalculated after the bad data is cleared,
- * we must write out enough data to fill the w$ line (64 bytes). So we read
- * in an entire ecache subblock's worth of data, and write it back out.
- * Then we overwrite the 16 bytes of bad data with the pattern.
- */
-/* ARGSUSED */
-void
-clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
-{
-}
-
-#else	/* lint */
 	ENTRY(clearphys)
 	/* turn off IE, AM bits */
 	rdpr	%pstate, %o4
@@ -962,23 +841,7 @@
 	  wrpr	%g0, %o4, %pstate
 	SET_SIZE(clearphys)
 
-#endif	/* lint */
-	
 
-#if defined(lint)
-/*
- * Jalapeno Ecache displacement flush the specified line from the E$
- *
- * Register usage:
- *	%o0 - 64 bit physical address for flushing
- *	%o1 - Ecache set size
- */
-/*ARGSUSED*/
-void
-ecache_flush_line(uint64_t flushaddr, int ec_set_size)
-{
-}
-#else	/* lint */
 	ENTRY(ecache_flush_line)
 
 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
@@ -998,7 +861,6 @@
 	retl
 	  nop
 	SET_SIZE(ecache_flush_line)
-#endif	/* lint */
 
 
 /*
@@ -1007,12 +869,6 @@
  * CPU's internal "invalidate FIFOs" are flushed.
  */
 
-#if defined(lint)
-void
-jbus_stst_order()
-{}
-#else	/* lint */
-
 #define	VIS_BLOCKSIZE	64
 
 	.seg    ".data"
@@ -1035,21 +891,8 @@
 	membar  #Sync
 	SET_SIZE(jbus_stst_order)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * This routine will not be called in Jalapeno systems.
- */
-void
-flush_ipb(void)
-{ return; }
-
-#else	/* lint */
-
 	ENTRY(flush_ipb)
 	retl
 	nop
 	SET_SIZE(flush_ipb)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/daktari/ml/daktari_asm.s	Thu Nov 14 19:00:43 2019
+++ new/usr/src/uts/sun4u/daktari/ml/daktari_asm.s	Thu Nov 14 19:00:43 2019
@@ -24,13 +24,7 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#else
 #include "assym.h"
-#endif /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/param.h>
@@ -49,24 +43,6 @@
 #include <sys/fsr.h>
 #include <sys/cheetahregs.h>
 
-#if defined(lint)
-
-/* ARGSUSED */
-uint64_t
-lddmcdecode(uint64_t physaddr)
-{
-	return (0x0ull);
-}
-
-/* ARGSUSED */
-uint64_t
-lddsafaddr(uint64_t physaddr)
-{
-	return (0x0ull);
-}
-
-#else /* !lint */
-
 !
 ! Load the safari address for a specific cpu
 !
@@ -115,4 +91,3 @@
 	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
 	SET_SIZE(lddmcdecode)
 
-#endif /* lint */
--- old/usr/src/uts/sun4u/io/panther_asm.s	Thu Nov 14 19:00:44 2019
+++ new/usr/src/uts/sun4u/io/panther_asm.s	Thu Nov 14 19:00:44 2019
@@ -25,11 +25,7 @@
  * Assembly code support for the Cheetah+ module
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -54,8 +50,6 @@
 #endif /* TRAPTRACE */
 
 
-#if !defined(lint)
-
 	.global retire_l2_start
 	.global retire_l2_end
 	.global unretire_l2_start
@@ -127,16 +121,6 @@
 	PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
 
 
-#endif	/* !lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-retire_l2(uint64_t tag_addr, uint64_t pattern)
-{return 0;}
-
-#else
 	.align 4096
 	ENTRY(retire_l2)
 retire_l2_start:
@@ -198,18 +182,6 @@
 retire_l2_end:
 	SET_SIZE(retire_l2)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*
- */
-/*ARGSUSED*/
-int
-unretire_l2(uint64_t tag_addr, uint64_t pattern)
-{return 0;}
-
-#else
 	ENTRY(unretire_l2)
 unretire_l2_start:
 
@@ -257,16 +229,6 @@
 unretire_l2_end:
 	SET_SIZE(unretire_l2)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-retire_l3(uint64_t tag_addr, uint64_t pattern)
-{return 0;}
-
-#else
 	ENTRY(retire_l3)
 retire_l3_start:
 
@@ -323,18 +285,6 @@
 retire_l3_end:
 	SET_SIZE(retire_l3)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*
- */
-/*ARGSUSED*/
-int
-unretire_l3(uint64_t tag_addr, uint64_t pattern)
-{return 0;}
-
-#else
 	ENTRY(unretire_l3)
 unretire_l3_start:
 
@@ -382,16 +332,6 @@
 unretire_l3_end:
 	SET_SIZE(unretire_l3)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-retire_l2_alternate(uint64_t tag_addr, uint64_t pattern)
-{return 0;}
-
-#else
 	.align 2048
 
 	ENTRY(retire_l2_alternate)
@@ -452,18 +392,6 @@
 	 dec	%o5
 	SET_SIZE(retire_l2_alternate)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*
- */
-/*ARGSUSED*/
-int
-unretire_l2_alternate(uint64_t tag_addr, uint64_t pattern)
-{return 0;}
-
-#else
 	ENTRY(unretire_l2_alternate)
 
 	! since we disable interrupts, we don't need to do kpreempt_disable()
@@ -509,16 +437,6 @@
 	 mov	%o5, %o0
 	SET_SIZE(unretire_l2_alternate)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-retire_l3_alternate(uint64_t tag_addr, uint64_t pattern)
-{return 0;}
-
-#else
 	ENTRY(retire_l3_alternate)
 
 	! since we disable interrupts, we don't need to do kpreempt_disable()
@@ -573,18 +491,6 @@
 	 dec	%o5
 	SET_SIZE(retire_l3_alternate)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*
- */
-/*ARGSUSED*/
-int
-unretire_l3_alternate(uint64_t tag_addr, uint64_t pattern)
-{return 0;}
-
-#else
 	ENTRY(unretire_l3_alternate)
 
 	! since we disable interrupts, we don't need to do kpreempt_disable()
@@ -630,16 +536,6 @@
 	 mov	%o5, %o0
 	SET_SIZE(unretire_l3_alternate)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-get_ecache_dtags_tl1(uint64_t afar, ch_cpu_logout_t *clop)
-{ }
-
-#else
 	ENTRY(get_ecache_dtags_tl1)
 
 
@@ -654,15 +550,6 @@
 	retry
 	SET_SIZE(get_ecache_dtags_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*ARGSUSED*/
-void
-get_l2_tag_tl1(uint64_t tag_addr, uint64_t tag_data_ptr)
-{ }
-
-#else
 	ENTRY(get_l2_tag_tl1)
 
 	/*
@@ -674,15 +561,6 @@
 	retry
 	SET_SIZE(get_l2_tag_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*ARGSUSED*/
-void
-get_l3_tag_tl1(uint64_t tag_addr, uint64_t tag_data_ptr)
-{ }
-
-#else
 	ENTRY(get_l3_tag_tl1)
 
 	/*
@@ -693,6 +571,4 @@
 
 	retry
 	SET_SIZE(get_l3_tag_tl1)
-
-#endif	/* lint */
 
--- old/usr/src/uts/sun4u/io/pci/pci_asm.s	Thu Nov 14 19:00:44 2019
+++ new/usr/src/uts/sun4u/io/pci/pci_asm.s	Thu Nov 14 19:00:44 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Assembly language support for physical big/little endian access of pcitool
  * in the PCI drivers.
@@ -37,17 +35,6 @@
 
 /*LINTLIBRARY*/
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int pci_do_phys_peek(size_t size, uint64_t paddr, uint64_t *value, int type)
-{ return (0); }
-
-int pci_do_phys_poke(size_t size, uint64_t paddr, uint64_t *value, int type)
-{ return (0); }
-
-#else /* lint */
-
 ! pci_do_phys_peek: Do physical address read.
 !
 ! %o0 is size in bytes - Must be 8, 4, 2 or 1.  Invalid sizes default to 1.
@@ -164,4 +151,3 @@
 	mov	%g0, %o0
 	SET_SIZE(pci_do_phys_poke)
  
-#endif
--- old/usr/src/uts/sun4u/io/pci/pcisch_asm.s	Thu Nov 14 19:00:45 2019
+++ new/usr/src/uts/sun4u/io/pci/pcisch_asm.s	Thu Nov 14 19:00:45 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>
 #include <sys/fsr.h>
@@ -34,14 +32,6 @@
 
 #define	VIS_BLOCKSIZE	64
 
-#if defined(lint)
-
-void
-tomatillo_store_store_order()
-{}
-
-#else /* lint */
-
 	.seg    ".data"
 	.align  VIS_BLOCKSIZE
 	.type   sync_buf, #object
@@ -62,4 +52,3 @@
 	membar  #Sync
 	SET_SIZE(tomatillo_store_store_order)
 
-#endif /* lint */
--- old/usr/src/uts/sun4u/io/px/px_asm_4u.s	Thu Nov 14 19:00:45 2019
+++ new/usr/src/uts/sun4u/io/px/px_asm_4u.s	Thu Nov 14 19:00:45 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Assembly language support for px driver
  */
@@ -36,20 +34,6 @@
 
 /*LINTLIBRARY*/
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-px_phys_peek_4u(size_t size, uint64_t paddr, uint64_t *value, int type)
-{ return (0); }
-
-/*ARGSUSED*/
-int
-px_phys_poke_4u(size_t size, uint64_t paddr, uint64_t *value, int type)
-{ return (0); }
-
-#else /* lint */
-
 ! px_phys_peek_4u: Do physical address read.
 !
 ! %o0 is size in bytes - Must be 8, 4, 2 or 1.  Invalid sizes default to 1.
@@ -167,4 +151,3 @@
 	mov	%g0, %o0
 	SET_SIZE(px_phys_poke_4u)
  
-#endif
--- old/usr/src/uts/sun4u/lw8/ml/lw8_platmod_asm.s	Thu Nov 14 19:00:45 2019
+++ new/usr/src/uts/sun4u/lw8/ml/lw8_platmod_asm.s	Thu Nov 14 19:00:45 2019
@@ -24,13 +24,7 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#else
 #include "assym.h"
-#endif /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/param.h>
@@ -49,24 +43,6 @@
 #include <sys/fsr.h>
 #include <sys/cheetahregs.h>
 
-#if defined(lint)
-
-/* ARGSUSED */
-uint64_t
-lddmcdecode(uint64_t physaddr)
-{
-	return (0x0ull);
-}
-
-/* ARGSUSED */
-uint64_t
-lddsafaddr(uint64_t physaddr)
-{
-	return (0x0ull);
-}
-
-#else /* !lint */
-
 !
 ! Load the safari address for a specific cpu
 !
@@ -93,4 +69,3 @@
 	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
 	SET_SIZE(lddmcdecode)
 
-#endif /* lint */
--- old/usr/src/uts/sun4u/ml/cpr_resume_setup.s	Thu Nov 14 19:00:46 2019
+++ new/usr/src/uts/sun4u/ml/cpr_resume_setup.s	Thu Nov 14 19:00:46 2019
@@ -24,13 +24,7 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#else   /* lint */
 #include "assym.h"
-#endif  /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>		/* for reg definition */
@@ -62,30 +56,6 @@
  * require changes to cprboot_srt0.s
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-i_cpr_resume_setup(void *cookie, csu_md_t *mdp)
-{}
-
-/* ARGSUSED */
-int
-i_cpr_cif_wrapper(void *args)
-{ return (0); }
-
-/* ARGSUSED */
-void
-dtlb_wr_entry(uint_t index, tte_t *tte, uint64_t *va_tag)
-{}
-
-/* ARGSUSED */
-void
-itlb_wr_entry(uint_t index, tte_t *tte, uint64_t *va_tag)
-{}
-
-#else	/* lint */
-
 	!
 	! reserve 4k for cpr tmp stack; tstack should be first,
 	! any new data symbols should be added after tstack.
@@ -280,4 +250,3 @@
 	nop
 	SET_SIZE(itlb_wr_entry)
 
-#endif /* !lint */
--- old/usr/src/uts/sun4u/ml/mach_copy.s	Thu Nov 14 19:00:46 2019
+++ new/usr/src/uts/sun4u/ml/mach_copy.s	Thu Nov 14 19:00:46 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/param.h>
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
@@ -36,9 +34,7 @@
 #include <sys/fsr.h>
 #include <sys/privregs.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 #define	FP_USED 1
 #define	LOFAULT_SET 2
@@ -60,20 +56,6 @@
  * uzero is used by the kernel to zero a block in user address space.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-kzero(void *addr, size_t count)
-{ return(0); }
-
-/* ARGSUSED */
-void
-uzero(void *addr, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(uzero)
 	!
 	! Set a new lo_fault handler only if we came in with one
@@ -154,21 +136,10 @@
 	SET_SIZE(kzero)
 	SET_SIZE(uzero)
 
-#endif	/* lint */
-
 /*
  * Zero a block of storage.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-bzero(void *addr, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(bzero)
 	wr	%g0, ASI_P, %asi
 
@@ -474,4 +445,3 @@
 	clr	%o0			! return (0)
 
 	SET_SIZE(bzero)
-#endif	/* lint */
--- old/usr/src/uts/sun4u/ml/mach_interrupt.s	Thu Nov 14 19:00:46 2019
+++ new/usr/src/uts/sun4u/ml/mach_interrupt.s	Thu Nov 14 19:00:46 2019
@@ -23,12 +23,7 @@
  * Use is subject to license terms.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/thread.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>
@@ -42,14 +37,6 @@
 #endif /* TRAPTRACE */
 
 
-#if defined(lint)
-
-void
-vec_interrupt(void)
-{}
-
-#else	/* lint */
-
 vec_uiii_irdr_tab:
         .byte   UIII_IRDR_0, UIII_IRDR_1, UIII_IRDR_2, UIII_IRDR_3
         .byte   UIII_IRDR_4, UIII_IRDR_5, UIII_IRDR_6, UIII_IRDR_7
@@ -272,16 +259,6 @@
 	retry
 	SET_SIZE(dmv_vector)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-vec_intr_spurious(void)
-{}
-
-#else	/* lint */
-
 	DGDEF(vec_spurious_cnt)
 	.word	0
 
@@ -340,4 +317,3 @@
 
 _not_ready:	.asciz	"Interrupt Vector Receive Register not READY"
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/ml/mach_locore.s	Thu Nov 14 19:00:47 2019
+++ new/usr/src/uts/sun4u/ml/mach_locore.s	Thu Nov 14 19:00:47 2019
@@ -23,15 +23,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/t_lock.h>
-#include <sys/promif.h>
-#include <sys/prom_isa.h>
-#endif	/* lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/intreg.h>
 #include <sys/ivintr.h>
@@ -46,13 +37,7 @@
 #include <sys/machasi.h>
 #include <sys/clock.h>
 #include <vm/hat_sfmmu.h>
-#if defined(lint)
 
-#include <sys/thread.h>
-#include <sys/time.h>
-
-#else	/* lint */
-
 #include "assym.h"
 
 
@@ -174,16 +159,6 @@
 _local_p1275cis:
 	.nword	0
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-_start(void)
-{}
-
-#else /* lint */
-
 	.seg	".data"
 
 	.global nwindows, nwin_minus_one, winmask
@@ -356,9 +331,7 @@
 	.asciz	"main returned"
 	.align	4
 
-#endif	/* lint */
 
-
 /*
  * Generic system trap handler.
  *
@@ -394,14 +367,6 @@
  *	    uint32_t arg2 [%g3.l], uint32_t arg3 [%g3.h], uint32_t [%g2.h])
  */
 
-#if defined(lint)
-
-void
-sys_trap(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(sys_trap)
 	!
 	! force tl=1, update %cwp, branch to correct handler
@@ -875,10 +840,6 @@
 	SET_SIZE(priv_rtt)
 	SET_SIZE(ktl0)
 
-#endif	/* lint */
-
-#ifndef lint
-
 #ifdef DEBUG
 	.seg	".data"
 	.align	4
@@ -899,7 +860,6 @@
 	mov	%o3, %o2
 	SET_SIZE(bad_g4)
 #endif /* DEBUG */
-#endif /* lint */
 
 /*
  * sys_tl1_panic can be called by traps at tl1 which
@@ -906,13 +866,6 @@
  * really want to panic, but need the rearrangement of
  * the args as provided by this wrapper routine.
  */
-#if defined(lint)
-
-void
-sys_tl1_panic(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(sys_tl1_panic)
 	mov	%o1, %o0
 	mov	%o2, %o1
@@ -919,7 +872,6 @@
 	call	panic
 	mov	%o3, %o2
 	SET_SIZE(sys_tl1_panic)
-#endif /* lint */
 
 /*
  * Turn on or off bits in the auxiliary i/o register.
@@ -932,15 +884,6 @@
  * used to turn on/off the led.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-set_auxioreg(int bit, int flag)
-{}
-
-#else	/* lint */
-
 	.seg	".data"
 	.align	4
 auxio_panic:
@@ -980,8 +923,6 @@
 	 wrpr	%g0, %o2, %pstate	/* enable interrupt */
 	SET_SIZE(set_auxioreg)
 
-#endif /* lint */
-
 /*
  * Flush all windows to memory, except for the one we entered in.
  * We do this by doing NWINDOW-2 saves then the same number of restores.
@@ -989,29 +930,11 @@
  * This is used for context switching.
  */
 
-#if defined(lint)
-
-void
-flush_windows(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(flush_windows)
 	retl
 	flushw
 	SET_SIZE(flush_windows)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-debug_flush_windows(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(debug_flush_windows)
 	set	nwindows, %g1
 	ld	[%g1], %g1
@@ -1033,20 +956,10 @@
 
 	SET_SIZE(debug_flush_windows)
 
-#endif	/* lint */
-
 /*
  * flush user windows to memory.
  */
 
-#if defined(lint)
-
-void
-flush_user_windows(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(flush_user_windows)
 	rdpr	%otherwin, %g1
 	brz	%g1, 3f
@@ -1065,8 +978,6 @@
 	nop
 	SET_SIZE(flush_user_windows)
 
-#endif	/* lint */
-
 /*
  * Throw out any user windows in the register file.
  * Used by setregs (exec) to clean out old user.
@@ -1074,14 +985,6 @@
  * signal.
  */
 
-#if defined(lint)
-
-void
-trash_user_windows(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(trash_user_windows)
 	rdpr	%otherwin, %g1
 	brz	%g1, 3f			! no user windows?
@@ -1107,43 +1010,16 @@
 	SET_SIZE(trash_user_windows)
 
 
-#endif	/* lint */
-
 /*
  * Setup g7 via the CPU data structure.
  */
-#if defined(lint)
 
-struct scb *
-set_tbr(struct scb *s)
-{ return (s); }
-
-#else	/* lint */
-
 	ENTRY_NP(set_tbr)
 	retl
 	ta	72		! no tbr, stop simulation
 	SET_SIZE(set_tbr)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * These need to be defined somewhere to lint and there is no "hicore.s"...
- */
-char etext[1], end[1];
-#endif	/* lint*/
-
-#if defined (lint)
-
-/* ARGSUSED */
-void
-ptl1_panic(u_int reason)
-{}
-
-#else /* lint */
-
 #define	PTL1_SAVE_WINDOW(RP)						\
 	stxa	%l0, [RP + RW64_LOCAL + (0 * RW64_LOCAL_INCR)] %asi;	\
 	stxa	%l1, [RP + RW64_LOCAL + (1 * RW64_LOCAL_INCR)] %asi;	\
@@ -1418,25 +1294,9 @@
 	  mov	%l1, %o0
 	/*NOTREACHED*/
 	SET_SIZE(ptl1_panic)
-#endif /* lint */
 
 #ifdef	PTL1_PANIC_DEBUG
-#if defined (lint)
-/*
- * ptl1_recurse() calls itself a number of times to either set up a known
- * stack or to cause a kernel stack overflow. It decrements the arguments 
- * on each recursion.
- * It's called by #ifdef PTL1_PANIC_DEBUG code in startup.c to set the
- * registers to a known state to facilitate debugging.
- */
 
-/* ARGSUSED */
-void 
-ptl1_recurse(int count_threshold, int trap_threshold)
-{}
-
-#else /* lint */
-
 	ENTRY_NP(ptl1_recurse)
 	save    %sp, -SA(MINFRAME), %sp
 
@@ -1501,16 +1361,6 @@
 	  nop 					! NOTREACHED 
         SET_SIZE(ptl1_recurse)
 
-#endif /* lint */
-
-#if defined (lint)
-
-/* ARGSUSED */
-void
-ptl1_panic_xt(int arg1, int arg2)
-{}
-
-#else /* lint */
 	/*
 	 * Asm function to handle a cross trap to call ptl1_panic()
 	 */
@@ -1519,20 +1369,10 @@
 	  mov	PTL1_BAD_DEBUG, %g1
         SET_SIZE(ptl1_panic_xt)
 
-#endif /* lint */
-
 #endif	/* PTL1_PANIC_DEBUG */
 
 #ifdef	TRAPTRACE
-#if	defined (lint)
 
-void
-trace_ptr_panic(void)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(trace_ptr_panic)
 	!
 	! freeze the trap trace to disable the assertions.  Otherwise,
@@ -1554,24 +1394,8 @@
 	mov	PTL1_BAD_TRACE_PTR, %g1
 	SET_SIZE(trace_ptr_panic)
 
-#endif	/* lint */
 #endif	/* TRAPTRACE */
         
-#if	defined (lint)
-/*
- * set_kcontextreg() sets PCONTEXT to kctx
- * if PCONTEXT==kctx, do nothing
- * if N_pgsz0|N_pgsz1 differ, do demap all first
- */
-
-/* ARGSUSED */
-void
-set_kcontextreg()
-{
-}
-
-#else	/* lint */
-
         ENTRY_NP(set_kcontextreg)
 	! SET_KCONTEXTREG(reg0, reg1, reg2, reg3, reg4, label1, label2, label3)
 	SET_KCONTEXTREG(%o0, %o1, %o2, %o3, %o4, l1, l2, l3)
@@ -1579,8 +1403,6 @@
         nop
 	SET_SIZE(set_kcontextreg)
 	
-#endif /* lint */
-	
 
 /*
  * The interface for a 32-bit client program that takes over the TBA
@@ -1587,15 +1409,6 @@
  * calling the 64-bit romvec OBP.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-client_handler(void *cif_handler, void *arg_array)
-{ return 0; }
-
-#else	/* lint */
-
 	ENTRY(client_handler)
 	save	%sp, -SA64(MINFRAME64), %sp	! 32 bit frame, 64 bit sized
 	sethi	%hi(tba_taken_over), %l2
@@ -1665,5 +1478,3 @@
 	restore	%o0, %g0, %o0			! delay; result in %o0
 	SET_SIZE(client_handler)
 
-#endif	/* lint */
-	
--- old/usr/src/uts/sun4u/ml/mach_subr_asm.s	Thu Nov 14 19:00:47 2019
+++ new/usr/src/uts/sun4u/ml/mach_subr_asm.s	Thu Nov 14 19:00:47 2019
@@ -27,12 +27,7 @@
  * General machine architecture & implementation specific
  * assembly language routines.
  */
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/t_lock.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/machsystm.h>
@@ -42,14 +37,6 @@
 #include <sys/clock.h>
 #include <sys/fpras.h>
 
-#if defined(lint)
-
-uint64_t
-ultra_gettick(void)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * This isn't the routine you're looking for.
  *
@@ -63,17 +50,6 @@
 	rdpr	%tick, %o0
 	SET_SIZE(ultra_gettick)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-getprocessorid(void)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * Get the processor ID.
  * === MID reg as specified in 15dec89 sun4u spec, sec 5.4.3
@@ -85,26 +61,6 @@
 	nop
 	SET_SIZE(getprocessorid)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*ARGSUSED*/
-void
-set_error_enable_tl1(uint64_t neer, uint64_t action)
-{}
-
-/* ARGSUSED */
-void
-set_error_enable(uint64_t neer)
-{}
-
-uint64_t
-get_error_enable()
-{
-	return ((uint64_t)0);
-}
-#else /* lint */
-
 	ENTRY(set_error_enable_tl1)
 	cmp	%g2, EER_SET_ABSOLUTE
 	be	%xcc, 1f
@@ -133,16 +89,6 @@
 	ldxa	[%g0]ASI_ESTATE_ERR, %o0	/* ecache error enable reg */
 	SET_SIZE(get_error_enable)
 
-#endif /* lint */
-
-#if defined(lint)
-void
-get_asyncflt(uint64_t *afsr)
-{
-	afsr = afsr;
-}
-#else /* lint */
-
 	ENTRY(get_asyncflt)
 	ldxa	[%g0]ASI_AFSR, %o1		! afsr reg
 	retl
@@ -149,16 +95,6 @@
 	stx	%o1, [%o0]
 	SET_SIZE(get_asyncflt)
 
-#endif /* lint */
-
-#if defined(lint)
-void
-set_asyncflt(uint64_t afsr)
-{
-	afsr = afsr;
-}
-#else /* lint */
-
 	ENTRY(set_asyncflt)
 	stxa	%o0, [%g0]ASI_AFSR		! afsr reg
 	membar	#Sync
@@ -166,16 +102,6 @@
 	nop
 	SET_SIZE(set_asyncflt)
 
-#endif /* lint */
-
-#if defined(lint)
-void
-get_asyncaddr(uint64_t *afar)
-{
-	afar = afar;
-}
-#else /* lint */
-
 	ENTRY(get_asyncaddr)
 	ldxa	[%g0]ASI_AFAR, %o1		! afar reg
 	retl
@@ -182,17 +108,6 @@
 	stx	%o1, [%o0]
 	SET_SIZE(get_asyncaddr)
 
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-hrtime_t
-tick2ns(hrtime_t tick, uint_t cpuid)
-{ return 0; }
-
-#else	/* lint */
-
 	ENTRY_NP(tick2ns)
 	sethi	%hi(cpunodes), %o4
 	or	%o4, %lo(cpunodes), %o4		! %o4 = &cpunodes
@@ -210,17 +125,6 @@
 	nop
 	SET_SIZE(tick2ns)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-set_cmp_error_steering(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(set_cmp_error_steering)
 	membar	#Sync
 	set	ASI_CORE_ID, %o0		! %o0 = ASI_CORE_ID
@@ -233,34 +137,11 @@
 	nop
 	SET_SIZE(set_cmp_error_steering)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-uint64_t
-ultra_getver(void)
-{
-	return (0); 
-}
-
-#else /* lint */
-
 	ENTRY(ultra_getver)
 	retl
 	rdpr	%ver, %o0
 	SET_SIZE(ultra_getver)
 
-#endif /* lint */
-
-#if defined(lint)
-
-int
-fpras_chkfn_type1(void)
-{ return 0; }
-
-#else	/* lint */
-
 	/*
 	 * Check instructions using just the AX pipelines, designed by
 	 * C.B. Liaw of PNP.
@@ -421,20 +302,10 @@
 	  mov	FPRAS_BADTRAP, %o0	! 16, how detected
 	SET_SIZE(fpras_chkfn_type1)
 
-#endif	/* lint */
-
 /*
  * fp_zero() - clear all fp data registers and the fsr
  */
 
-#if defined(lint) || defined(__lint)
-
-void
-fp_zero(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fp_zero)
 	std	%g0, [%sp + ARGPUSH + STACK_BIAS]
 	fzero	%f0
@@ -473,4 +344,3 @@
 	fmuld	%f0, %f2, %f62
 	SET_SIZE(fp_zero)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/ml/mach_xc.s	Thu Nov 14 19:00:47 2019
+++ new/usr/src/uts/sun4u/ml/mach_xc.s	Thu Nov 14 19:00:47 2019
@@ -23,12 +23,7 @@
  * Use is subject to license terms.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/cpuvar.h>
-#else	/*lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
@@ -40,15 +35,6 @@
 #endif /* TRAPTRACE */
 
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-self_xcall(struct cpu *cpu, uint64_t arg1, uint64_t arg2, xcfunc_t *func)
-{}
-
-#else
-
 /*
  * Entered by the software trap (TT=ST_SELFXCALL, TL>0) thru send_self_xcall().
  * Emulate the mondo handler - vec_interrupt().
@@ -102,18 +88,7 @@
 	/* Not Reached */
 	SET_SIZE(self_xcall)
 
-#endif	/* lint */
-
 #ifdef  TRAPTRACE
-#if defined(lint)
-
-/* ARGSUSED */
-void
-xc_trace(u_int traptype, cpuset_t *cpu_set, xcfunc_t *func,
-	uint64_t arg1, uint64_t arg2)
-{}
-
-#else	/* lint */
 	ENTRY(xc_trace)
 	rdpr	%pstate, %g1
 	andn	%g1, PSTATE_IE | PSTATE_AM, %g2
@@ -186,17 +161,8 @@
 	wrpr	%g0, %g1, %pstate			/* enable interrupts */
 	SET_SIZE(xc_trace)
 
-#endif	/* lint */
 #endif	/* TRAPTRACE */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-xt_sync_tl1(uint64_t *cpu_sync_addr)
-{}
-
-#else
 /*
  * This dummy tl1 function is there to ensure that previously called
  * xtrap handlers have exececuted. The hardware (mondo dispatch
@@ -210,4 +176,3 @@
 	retry
 	SET_SIZE(xt_sync_tl1)
 
-#endif  /* lint */
--- old/usr/src/uts/sun4u/ml/mc-us3_asm.s	Thu Nov 14 19:00:48 2019
+++ new/usr/src/uts/sun4u/ml/mc-us3_asm.s	Thu Nov 14 19:00:48 2019
@@ -26,29 +26,11 @@
  * Assembly code support for Memory Control driver
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
 #include <sys/mc-us3.h>
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 
-#if defined(lint)
-
-/*
- * routine to get value of Memory Control Registers
- */
-/* ARGSUSED */
-uint64_t
-get_mcr(int offset)
-{
-	return ((uint64_t)0);
-}
-
-#else	/* lint */
-
  	! This routine is to get content of Memory Control Registers
  	ENTRY(get_mcr)
  	! input
@@ -59,4 +41,3 @@
  	  nop
  	SET_SIZE(get_mcr)
  
-#endif /* lint */
--- old/usr/src/uts/sun4u/ml/memscrub_asm.s	Thu Nov 14 19:00:48 2019
+++ new/usr/src/uts/sun4u/ml/memscrub_asm.s	Thu Nov 14 19:00:48 2019
@@ -23,19 +23,11 @@
  * Copyright (c) 2007 by Sun Microsystems, Inc.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * General machine architecture & implementation specific
  * assembly language routines.
  */
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/machsystm.h>
-#include <sys/t_lock.h>
-#else   /* lint */
 #include "assym.h"
-#endif  /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/eeprom.h>
@@ -47,15 +39,6 @@
 #include <sys/privregs.h>
 #include <sys/archsystm.h>
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-memscrub_read(caddr_t vaddr, u_int blks)
-{}
-
-#else	/* lint */
-
 	!
 	! void	memscrub_read(caddr_t src, u_int blks)
 	!
@@ -88,4 +71,3 @@
 	wr	%o2, 0, %fprs			! restore fprs (disabled)
 	SET_SIZE(memscrub_read)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/ml/trap_table.s	Thu Nov 14 19:00:48 2019
+++ new/usr/src/uts/sun4u/ml/trap_table.s	Thu Nov 14 19:00:48 2019
@@ -23,9 +23,7 @@
  * Use is subject to license terms.
  */
  
-#if !defined(lint)
 #include "assym.h"
-#endif /* !lint */
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
 #include <sys/sun4asi.h>
@@ -117,9 +115,7 @@
  * NOT is used for traps that just shouldn't happen.
  * It comes in both single and quadruple flavors.
  */
-#if !defined(lint)
 	.global	trap
-#endif /* !lint */
 #define	NOT			\
 	TT_TRACE(trace_gen)	;\
 	set	trap, %g1	;\
@@ -149,9 +145,7 @@
  * TRAP vectors to the trap() function.
  * It's main use is for user errors.
  */
-#if !defined(lint)
 	.global	trap
-#endif /* !lint */
 #define	TRAP(arg)		\
 	TT_TRACE(trace_gen)	;\
 	set	trap, %g1	;\
@@ -280,8 +274,6 @@
 	clr %o4; clr %o5; clr %o6; clr %o7			;\
 	retry; .align 128
 
-#if !defined(lint)
-
 /*
  * If we get an unresolved tlb miss while in a window handler, the fault
  * handler will resume execution at the last instruction of the window
@@ -700,8 +692,6 @@
 	ba,a,pt	%xcc, fault_64bit_/**/tail			;\
 	.empty
 
-#endif /* !lint */
-
 /*
  * SPILL_mixed spills either size window, depending on
  * whether %sp is even or odd, to a 32-bit address space.
@@ -845,7 +835,6 @@
 	nop				;\
 	.align	32
 
-#if !defined(lint)
 /*
  * asynchronous traps at level 0 and level 1
  *
@@ -871,8 +860,6 @@
 table_name:				;\
 	BAD
 
-#endif /* !lint */
-
 /*
  * illegal instruction trap
  */
@@ -1319,13 +1306,6 @@
 #define TRACE_TSBHIT(ttextra)
 #endif
 
-#if defined(lint)
-
-struct scb	trap_table;
-struct scb	scb;		/* trap_table/scb are the same object */
-
-#else /* lint */
-
 /*
  * =======================================================================
  *		SPARC V9 TRAP TABLE
@@ -3065,4 +3045,3 @@
 	SYSCALL_NOTT(syscall_trap)
 	SET_SIZE(syscall_wrapper)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/ml/wbuf.s	Thu Nov 14 19:00:49 2019
+++ new/usr/src/uts/sun4u/ml/wbuf.s	Thu Nov 14 19:00:49 2019
@@ -23,8 +23,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>
 #include <sys/privregs.h>
@@ -35,7 +33,6 @@
 #include <sys/machtrap.h>
 #include <sys/traptrace.h>
 
-#if !defined(lint)
 #include "assym.h"
 
 	/*
@@ -453,4 +450,3 @@
 	mov	PTL1_BAD_WTRAP, %g1
 	SET_SIZE(fault_32bit_not)
 	SET_SIZE(fault_64bit_not)
-#endif /* !lint */
--- old/usr/src/uts/sun4u/opl/ml/drmach_asm.s	Thu Nov 14 19:00:49 2019
+++ new/usr/src/uts/sun4u/opl/ml/drmach_asm.s	Thu Nov 14 19:00:49 2019
@@ -30,12 +30,8 @@
  * only by DR for the copy-rename sequence.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#else
 #include "assym.h"
 #include "drmach_offsets.h"
-#endif /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/param.h>
@@ -51,8 +47,6 @@
 #include <sys/drmach.h>
 #include <sys/sbd_ioctl.h>
 
-#if !defined(lint)
-
 /*
  * turn off speculative mode to prevent unwanted memory access
  * when we are in the FMEM loops
@@ -68,15 +62,8 @@
 	or	tmp1, tmp2, tmp1					;\
 	stxa	tmp1, [%g0]ASI_MCNTL					;\
 	membar #Sync
-#endif
 
 
-#if defined(lint)
-/*ARGSUSED*/
-void
-drmach_fmem_loop_script(caddr_t critical, int size, caddr_t stat)
-{ return; }
-#else /* lint */
 	.align  8
 	ENTRY_NP(drmach_fmem_loop_script)
 	/* turn off speculative mode */
@@ -158,14 +145,7 @@
 	ba	2b
 .word	 0x81b01060
 	SET_SIZE(drmach_fmem_loop_script)
-#endif /* lint */
 
-#if defined(lint)
-/*ARGSUSED*/
-void
-drmach_flush_icache(void)
-{ return; }
-#else /* lint */
 	.align  8
 	ENTRY_NP(drmach_flush_icache)
 	stxa	%g0, [%g0]ASI_ALL_FLUSH_L1I
@@ -173,14 +153,7 @@
 	retl
 	 nop
 	SET_SIZE(drmach_flush_icache)
-#endif
 
-#if defined(lint)
-/*ARGSUSED*/
-int
-drmach_fmem_exec_script(caddr_t critical, int size)
-{ return (0); }
-#else /* lint */
 .align 32
 	ENTRY_NP(drmach_fmem_exec_script)
 	/* turn off speculative mode */
@@ -455,29 +428,11 @@
 	ba,a	1b
 	 nop
 	SET_SIZE(drmach_fmem_exec_script)
-#endif /* lint */
 
-#if defined(lint)
-/*ARGSUSED*/
-void
-drmach_fmem_exec_script_end(caddr_t critical, int size)
-{ return; }
-#else /* lint */
 	ENTRY_NP(drmach_fmem_exec_script_end)
 	nop
 	SET_SIZE(drmach_fmem_exec_script_end)
-#endif /* lint */
 
-#if defined(lint)
-uint64_t
-patch_inst(uint64_t *x, uint64_t y)
-{
-	*x = y;
-	return (0);
-}
-
-#else   /* lint */
-
 	ENTRY_NP(patch_inst)
 	ldx	[%o0], %o2
 	casx	[%o0], %o2, %o1
@@ -488,14 +443,6 @@
 	 mov	%o2, %o0
 	SET_SIZE(patch_inst)
 
-#endif /* lint */
-
-#if defined(lint)
-void
-drmach_sys_trap()
-{
-}
-#else   /* lint */
 	ENTRY_NP(drmach_sys_trap)
 	mov	-1, %g4
 	set	sys_trap, %g5
@@ -502,28 +449,12 @@
 	jmp	%g5
 	 nop
 	SET_SIZE(drmach_sys_trap)
-#endif /* lint */
 
-#if defined(lint)
-uint64_t
-drmach_get_stick()
-{
-	return (0);
-}
-#else   /* lint */
 	ENTRY_NP(drmach_get_stick)
 	retl
 	rd	STICK, %o0
 	SET_SIZE(drmach_get_stick)
-#endif /* lint */
 
-#if defined(lint)
-/*ARGSUSED*/
-void
-drmach_flush(drmach_copy_rename_critical_t *x, uint_t y)
-{}
-
-#else /* lint */
 	ENTRY_NP(drmach_flush)
 	mov	%o0, %o2
 0:
@@ -534,4 +465,3 @@
 	retl
 	 nop
 	SET_SIZE(drmach_flush)
-#endif /* lint */
--- old/usr/src/uts/sun4u/opl/ml/mc-opl_asm.s	Thu Nov 14 19:00:49 2019
+++ new/usr/src/uts/sun4u/opl/ml/mc-opl_asm.s	Thu Nov 14 19:00:49 2019
@@ -26,20 +26,8 @@
  * All Rights Reserved, Copyright (c) FUJITSU LIMITED 2006
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#else
 #include <sys/asm_linkage.h>
-#endif	/* lint */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-mc_prefetch(caddr_t va)
-{ return; }
-
-#else
 	/* issue a strong prefetch to cause MI error */
 	ENTRY(mc_prefetch)
 	prefetch	[%o0],0x16
@@ -46,4 +34,3 @@
 	retl
 	nop
 	SET_SIZE(mc_prefetch)
-#endif
--- old/usr/src/uts/sun4u/serengeti/ml/sbdp_asm.s	Thu Nov 14 19:00:50 2019
+++ new/usr/src/uts/sun4u/serengeti/ml/sbdp_asm.s	Thu Nov 14 19:00:50 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * This file is through cpp before being used as
  * an inline.  It contains support routines used
@@ -32,13 +30,7 @@
  * only by DR for the copy-rename sequence.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/sbd_ioctl.h>
-#include <sys/sbdp_priv.h>
-#else
 #include "assym.h"
-#endif /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/param.h>
@@ -58,8 +50,6 @@
 #include <sys/cheetahregs.h>
 #include <sys/cheetahasm.h>
 
-#ifndef lint
-
 /*
  * Invalidating the E$ tags is only needed on Cheetah following
  * the manual displacement flush.  The internal flush ASI used by
@@ -109,17 +99,6 @@
 	set	CH_ICACHE_LSIZE, reg2				;\
 2:
 
-#endif  /* !lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-sbdp_shutdown_asm(sbdp_shutdown_t *shutshown)
-{}
-
-#else /* lint */
-
         ENTRY_NP(sbdp_shutdown_asm)
         ! %o0 = address of sbdp_shutdown_t structure passed in
         !
@@ -215,31 +194,11 @@
 
 sbdp_shutdown_asm_end:
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #define	TT_HSM	0x99
 
-#if defined(lint)
-/* ARGSUSED */
-void
-sgdr_mem_blkcopy(caddr_t src, caddr_t dst, u_int linecount, u_int linesize)
-{}
-
-void
-stdmcdecode(uint64_t physaddr, uint64_t value)
-{
-	physaddr = physaddr;
-	value = value;
-}
-
-#else /* !lint */
 !
 ! Move a single cache line of data.  Survive UE and CE on the read
 !
@@ -322,4 +281,3 @@
         wrpr    %g0, %o4, %pstate       ! restore earlier pstate register value
         SET_SIZE(stdmcdecode)
 
-#endif /* lint */
--- old/usr/src/uts/sun4u/serengeti/ml/serengeti_asm.s	Thu Nov 14 19:00:50 2019
+++ new/usr/src/uts/sun4u/serengeti/ml/serengeti_asm.s	Thu Nov 14 19:00:50 2019
@@ -24,13 +24,7 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
-#if defined(lint)
-#include <sys/types.h>
-#else
 #include "assym.h"
-#endif /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/param.h>
@@ -49,24 +43,6 @@
 #include <sys/fsr.h>
 #include <sys/cheetahregs.h>
 
-#if defined(lint)
-
-/* ARGSUSED */
-uint64_t
-lddmcdecode(uint64_t physaddr)
-{
-	return (0x0ull);
-}
-
-/* ARGSUSED */
-uint64_t
-lddsafaddr(uint64_t physaddr)
-{
-	return (0x0ull);
-}
-
-#else /* !lint */
-
 !
 ! Load the safari address for a specific cpu
 !
@@ -93,4 +69,3 @@
 	wrpr	%g0, %o4, %pstate	! restore earlier pstate register value
 	SET_SIZE(lddmcdecode)
 
-#endif /* lint */
--- old/usr/src/uts/sun4u/sunfire/ml/ac_asm.s	Thu Nov 14 19:00:50 2019
+++ new/usr/src/uts/sun4u/sunfire/ml/ac_asm.s	Thu Nov 14 19:00:50 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/param.h>
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
@@ -39,20 +37,10 @@
 #include <sys/mmu.h>
 #include <sys/spitregs.h>
 
-#if defined(lint)
-
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #define	TT_HSM	0x99
 
-#if defined(lint)
-/* ARGSUSED */
-void
-ac_blkcopy(caddr_t src, caddr_t dst, u_int linecount, u_int linesize)
-{}
-#else /* !lint */
 !
 ! Move a single cache line of data.  Survive UE and CE on the read
 !
@@ -117,4 +105,3 @@
 	ret
 	 restore
 	SET_SIZE(ac_blkcopy)
-#endif /* lint */
--- old/usr/src/uts/sun4u/sunfire/ml/fhc_asm.s	Thu Nov 14 19:00:50 2019
+++ new/usr/src/uts/sun4u/sunfire/ml/fhc_asm.s	Thu Nov 14 19:00:50 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/param.h>
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
@@ -34,11 +32,7 @@
 #include <sys/privregs.h>
 #include <sys/spitregs.h>
 
-#if defined(lint)
-
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 /*
  * fhc_shutdown_asm(u_longlong_t base, int size)
@@ -57,15 +51,7 @@
  * function must be position independent code that doesn't reference 
  * cacheable real memory.
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-void
-fhc_shutdown_asm(u_longlong_t base, int size)
-{}
-
-#else	/* lint */
-
 	ENTRY(fhc_shutdown_asm)
 	! turn off errors (we'll be writing to non-existent memory)
 	stxa	%g0, [%g0]ASI_ESTATE_ERR
@@ -94,4 +80,3 @@
 	.global	fhc_shutdown_asm_end
 fhc_shutdown_asm_end:
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/sunfire/ml/sysctrl_asm.s	Thu Nov 14 19:00:51 2019
+++ new/usr/src/uts/sun4u/sunfire/ml/sysctrl_asm.s	Thu Nov 14 19:00:51 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma	ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/param.h>
 #include <sys/errno.h>
 #include <sys/asm_linkage.h>
@@ -39,19 +37,10 @@
 #include <sys/mmu.h>
 #include <sys/spitregs.h>
 
-#if defined(lint)
-
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #define	TT_HSM	0x99
 
-#if defined(lint)
-void
-sysctrl_freeze(void)
-{}
-#else /* lint */
 /*
  * This routine quiets a cpu and has it spin on a barrier.
  * It is used during memory sparing so that no memory operation
@@ -89,4 +78,3 @@
 	membar	#Sync
 	SET_SIZE(sysctrl_freeze)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4u/vm/mach_sfmmu_asm.s	Thu Nov 14 19:00:51 2019
+++ new/usr/src/uts/sun4u/vm/mach_sfmmu_asm.s	Thu Nov 14 19:00:51 2019
@@ -23,18 +23,12 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * SFMMU primitives.  These primitives should only be used by sfmmu
  * routines.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/machtrap.h>
@@ -56,48 +50,7 @@
  * sfmmu related subroutines
  */
 
-#if defined (lint)
-
 /*
- * sfmmu related subroutines
- */
-/* ARGSUSED */
-void
-sfmmu_raise_tsb_exception(uint64_t sfmmup, uint64_t rctx)
-{}
-
-/* ARGSUSED */
-void
-sfmmu_itlb_ld_kva(caddr_t vaddr, tte_t *tte)
-{}
-
-/* ARGSUSED */
-void
-sfmmu_dtlb_ld_kva(caddr_t vaddr, tte_t *tte)
-{}
-
-int
-sfmmu_getctx_pri()
-{ return(0); }
-
-int
-sfmmu_getctx_sec()
-{ return(0); }
-
-/* ARGSUSED */
-void
-sfmmu_setctx_sec(uint_t ctx)
-{}
-
-/* ARGSUSED */
-void
-sfmmu_load_mmustate(sfmmu_t *sfmmup)
-{
-}
-
-#else	/* lint */
-
-/*
  * Invalidate either the context of a specific victim or any process
  * currently running on this CPU. 
  *
@@ -609,27 +562,6 @@
           nop
         SET_SIZE(sfmmu_load_mmustate)
 
-#endif /* lint */
-
-#if defined (lint)
-/*
- * Invalidate all of the entries within the tsb, by setting the inv bit
- * in the tte_tag field of each tsbe.
- *
- * We take advantage of the fact TSBs are page aligned and a multiple of
- * PAGESIZE to use block stores.
- *
- * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
- * (in short, we set all bits in the upper word of the tag, and we give the
- * invalid bit precedence over other tag bits in both places).
- */
-/* ARGSUSED */
-void
-sfmmu_inv_tsb_fast(caddr_t tsb_base, uint_t tsb_bytes)
-{}
-
-#else /* lint */
-
 #define	VIS_BLOCKSIZE	64
 
 	ENTRY(sfmmu_inv_tsb_fast)
@@ -707,33 +639,6 @@
 	  restore
 	SET_SIZE(sfmmu_inv_tsb_fast)
 
-#endif /* lint */
-
-#if defined(lint)
-
-/*
- * Prefetch "struct tsbe" while walking TSBs.
- * prefetch 7 cache lines ahead of where we are at now.
- * #n_reads is being used since #one_read only applies to
- * floating point reads, and we are not doing floating point
- * reads.  However, this has the negative side effect of polluting
- * the ecache.
- * The 448 comes from (7 * 64) which is how far ahead of our current
- * address, we want to prefetch.
- */
-/*ARGSUSED*/
-void
-prefetch_tsbe_read(struct tsbe *tsbep)
-{}
-
-/* Prefetch the tsbe that we are about to write */
-/*ARGSUSED*/
-void
-prefetch_tsbe_write(struct tsbe *tsbep)
-{}
-
-#else /* lint */
-
 	ENTRY(prefetch_tsbe_read)
 	retl
 	  prefetch	[%o0+448], #n_reads
@@ -743,5 +648,4 @@
 	retl
 	  prefetch	[%o0], #n_writes
 	SET_SIZE(prefetch_tsbe_write)
-#endif /* lint */
 
--- old/usr/src/uts/sun4v/cpu/common_asm.s	Thu Nov 14 19:00:51 2019
+++ new/usr/src/uts/sun4v/cpu/common_asm.s	Thu Nov 14 19:00:51 2019
@@ -22,9 +22,7 @@
  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif
 
 /*
  * General assembly language routines.
@@ -44,16 +42,7 @@
 #include <sys/machclock.h>
 #include <sys/clock.h>
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/scb.h>
-#include <sys/systm.h>
-#include <sys/regset.h>
-#include <sys/sunddi.h>
-#include <sys/lockstat.h>
-#endif	/* lint */
 
-
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
 #include <vm/hat_sfmmu.h>
@@ -67,24 +56,10 @@
 #include <sys/intr.h>
 #include <sys/hypervisor_api.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif
 
 #define	ICACHE_FLUSHSZ	0x20
 
-#if defined(lint)
-/*
- * Softint generated when counter field of tick reg matches value field 
- * of tick_cmpr reg
- */
-/*ARGSUSED*/
-void
-tickcmpr_set(uint64_t clock_cycles)
-{}
-
-#else   /* lint */
-
 	ENTRY_NP(tickcmpr_set)
 	! get 64-bit clock_cycles interval
 	mov	%o0, %o2
@@ -106,16 +81,6 @@
 	  nop
 	SET_SIZE(tickcmpr_set)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-void
-tickcmpr_disable(void)
-{}
-
-#else
-
 	ENTRY_NP(tickcmpr_disable)
 	mov	1, %g1
 	sllx	%g1, TICKINT_DIS_SHFT, %o0
@@ -124,29 +89,6 @@
 	  nop
 	SET_SIZE(tickcmpr_disable)
 
-#endif
-
-#if defined(lint)
-
-/*
- * tick_write_delta() is intended to increment %stick by the specified delta,
- * but %stick is only writeable in hyperprivileged mode and at present there
- * is no provision for this. tick_write_delta is called by the cylic subsystem
- * if a negative %stick delta is observed after cyclic processing is resumed
- * after an event such as an OS suspend/resume. On sun4v, the suspend/resume
- * routines should adjust the %stick offset preventing the cyclic subsystem
- * from detecting a negative delta. If a negative delta is detected, panic the
- * system. The negative delta could be caused by improper %stick
- * synchronization after a suspend/resume.
- */
-
-/*ARGSUSED*/
-void
-tick_write_delta(uint64_t delta)
-{}
-
-#else	/* lint */
-
 	.seg	".text"
 tick_write_delta_panic:
 	.asciz	"tick_write_delta: not supported, delta: 0x%lx"
@@ -160,19 +102,7 @@
 	/*NOTREACHED*/
 	retl
 	  nop
-#endif
 
-#if defined(lint)
-/*
- *  return 1 if disabled
- */
-
-int
-tickcmpr_disabled(void)
-{ return (0); }
-
-#else   /* lint */
-
 	ENTRY_NP(tickcmpr_disabled)
 	RD_TICKCMPR(%g1,%o0,%o1,__LINE__)
 	retl
@@ -179,23 +109,10 @@
 	  srlx	%g1, TICKINT_DIS_SHFT, %o0
 	SET_SIZE(tickcmpr_disabled)
 
-#endif  /* lint */
-
 /*
  * Get current tick
  */
-#if defined(lint)
 
-u_longlong_t
-gettick(void)
-{ return (0); }
-
-u_longlong_t
-randtick(void)
-{ return (0); }
-
-#else   /* lint */
-
 	ENTRY(gettick)
 	ALTENTRY(randtick)
 	GET_NATIVE_TIME(%o0,%o2,%o3,__LINE__)
@@ -204,23 +121,13 @@
 	SET_SIZE(randtick)
 	SET_SIZE(gettick)
 
-#endif  /* lint */
-
 /*
  * Get current tick. For trapstat use only.
  */
-#if defined (lint)
-
-hrtime_t
-rdtick()
-{ return (0); }
-
-#else
 	ENTRY(rdtick)
 	retl
 	RD_TICK_PHYSICAL(%o0)
 	SET_SIZE(rdtick)
-#endif /* lint */
 
 
 /*
@@ -227,22 +134,6 @@
  * Return the counter portion of the tick register.
  */
 
-#if defined(lint)
-
-uint64_t
-gettick_counter(void)
-{ return(0); }
-
-uint64_t
-gettick_npt(void)
-{ return(0); }
-
-uint64_t
-getstick_npt(void)
-{ return(0); }
-
-#else	/* lint */
-
 	ENTRY_NP(gettick_counter)
 	RD_TICK(%o0,%o1,%o2,__LINE__)
 	retl
@@ -260,7 +151,6 @@
 	retl
 	srlx	%o0, 63, %o0
 	SET_SIZE(getstick_npt)
-#endif	/* lint */
 
 /*
  * Provide a C callable interface to the trap that reads the hi-res timer.
@@ -267,65 +157,6 @@
  * Returns 64-bit nanosecond timestamp in %o0 and %o1.
  */
 
-#if defined(lint)
-
-hrtime_t
-gethrtime(void)
-{
-	return ((hrtime_t)0);
-}
-
-hrtime_t
-gethrtime_unscaled(void)
-{
-	return ((hrtime_t)0);
-}
-
-hrtime_t
-gethrtime_max(void)
-{
-	return ((hrtime_t)0);
-}
-
-void
-scalehrtime(hrtime_t *hrt)
-{
-	*hrt = 0;
-}
-
-void
-gethrestime(timespec_t *tp)
-{
-	tp->tv_sec = 0;
-	tp->tv_nsec = 0;
-}
-
-time_t
-gethrestime_sec(void)
-{
-	return (0);
-}
-
-void
-gethrestime_lasttick(timespec_t *tp)
-{
-	tp->tv_sec = 0;
-	tp->tv_nsec = 0;
-}
-
-/*ARGSUSED*/
-void
-hres_tick(void)
-{
-}
-
-void
-panic_hres_tick(void)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(gethrtime)
 	GET_HRTIME(%g1,%o0,%o1,%o2,%o3,%o4,%o5,%g2,__LINE__)
 							! %g1 = hrtime
@@ -618,10 +449,6 @@
 
 	SET_SIZE(hres_tick)
 
-#endif	/* lint */
-
-#if !defined(lint) && !defined(__lint)
-
 	.seg	".text"
 kstat_q_panic_msg:
 	.asciz	"kstat_q_exit: qlen == 0"
@@ -731,20 +558,6 @@
 	KSTAT_Q_UPDATE(add, BRZPT, 1f, 1:retl, KSTAT_IO_W)
 	SET_SIZE(kstat_runq_back_to_waitq)
 
-#endif /* lint */
-
-#ifdef lint	
-
-int64_t timedelta;
-hrtime_t hres_last_tick;
-volatile timestruc_t hrestime;
-int64_t hrestime_adj;
-volatile int hres_lock;
-uint_t nsec_scale;
-hrtime_t hrtime_base;
-int traptrace_use_stick;
-
-#else
 	/*
 	 *  -- WARNING --
 	 *
@@ -788,9 +601,7 @@
 native_stick_offset:
 	.word	0, 0
 
-#endif
 
-
 /*
  * drv_usecwait(clock_t n)	[DDI/DKI - section 9F]
  * usec_delay(int n)		[compatibility - should go one day]
@@ -803,20 +614,6 @@
  * use %stick to implement this routine.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-drv_usecwait(clock_t n)
-{}
-
-/*ARGSUSED*/
-void
-usec_delay(int n)
-{}
-
-#else	/* lint */
-
 	ENTRY(drv_usecwait)
 	ALTENTRY(usec_delay)
 	brlez,a,pn %o0, 0f
@@ -837,17 +634,7 @@
 	  nop
 	SET_SIZE(usec_delay)
 	SET_SIZE(drv_usecwait)
-#endif	/* lint */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-pil14_interrupt(int level)
-{}
-
-#else
-
 /*
  * Level-14 interrupt prologue.
  */
@@ -933,17 +720,6 @@
 	  nop
 	SET_SIZE(tick_rtt)
 
-#endif /* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-pil15_interrupt(int level)
-{}
-
-#else   /* lint */
-
 /*
  * Level-15 interrupt prologue.
  */
@@ -961,24 +737,6 @@
        stn     %g0, [%g1 + CPU_CPCPROFILE_UPC] ! zero user PC
        SET_SIZE(pil15_interrupt)
 
-#endif  /* lint */
-
-#if defined(lint)
-/*
- * Prefetch a page_t for write or read, this assumes a linear
- * scan of sequential page_t's.
- */
-/*ARGSUSED*/
-void
-prefetch_page_w(void *pp)
-{}
-
-/*ARGSUSED*/
-void
-prefetch_page_r(void *pp)
-{}
-#else	/* lint */
-
 /* XXXQ These should be inline templates, not functions */
         ENTRY(prefetch_page_w)
         retl
@@ -990,18 +748,6 @@
 	  nop
         SET_SIZE(prefetch_page_r)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * Prefetch struct smap for write. 
- */
-/*ARGSUSED*/
-void
-prefetch_smap_w(void *smp)
-{}
-#else	/* lint */
-
 /* XXXQ These should be inline templates, not functions */
 	ENTRY(prefetch_smap_w)
 	retl
@@ -1008,61 +754,10 @@
 	  nop
 	SET_SIZE(prefetch_smap_w)
 
-#endif	/* lint */
-
 /*
  * Generic sun4v MMU and Cache operations.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-vtag_flushpage(caddr_t vaddr, uint64_t sfmmup)
-{}
-
-/*ARGSUSED*/
-void
-vtag_flushall(void)
-{}
-
-/*ARGSUSED*/
-void
-vtag_unmap_perm_tl1(uint64_t vaddr, uint64_t ctxnum)
-{}
-
-/*ARGSUSED*/
-void
-vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup)
-{}
-
-/*ARGSUSED*/
-void
-vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt)
-{}
-
-/*ARGSUSED*/
-void
-vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2)
-{}
-
-/*ARGSUSED*/
-void
-vac_flushpage(pfn_t pfnum, int vcolor)
-{}
-
-/*ARGSUSED*/
-void
-vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor)
-{}
-
-/*ARGSUSED*/
-void
-flush_instr_mem(caddr_t vaddr, size_t len)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushpage)
 	/*
 	 * flush page from the tlb
@@ -1262,8 +957,6 @@
 	  nop
 	SET_SIZE(flush_instr_mem)
 
-#endif /* !lint */
-
 #if !defined(CUSTOM_FPZERO)
 
 /*
@@ -1270,14 +963,6 @@
  * fp_zero() - clear all fp data registers and the fsr
  */
 
-#if defined(lint) || defined(__lint)
-
-void
-fp_zero(void)
-{}
-
-#else	/* lint */
-
 .global	fp_zero_zero
 .align 8
 fp_zero_zero:
@@ -1321,5 +1006,4 @@
 	fmovd	%f0, %f62
 	SET_SIZE(fp_zero)
 
-#endif	/* lint */
 #endif  /* CUSTOM_FPZERO */
--- old/usr/src/uts/sun4v/cpu/generic_copy.s	Thu Nov 14 19:00:52 2019
+++ new/usr/src/uts/sun4v/cpu/generic_copy.s	Thu Nov 14 19:00:52 2019
@@ -35,9 +35,7 @@
 #include <sys/fsr.h>
 #include <sys/privregs.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 
 /*
@@ -60,15 +58,6 @@
 
 
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-kcopy(const void *from, void *to, size_t count)
-{ return(0); }
-
-#else	/* lint */
-
 	.seg	".text"
 	.align	4
 
@@ -97,21 +86,12 @@
 	restore	%g1, 0, %o0
 
 	SET_SIZE(kcopy)
-#endif	/* lint */
 
 
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-bcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(bcopy)
 
 	save	%sp, -SA(MINFRAME), %sp
@@ -375,21 +355,10 @@
 	andn	%i2, %o0, %i3		! return size of aligned bytes
 	SET_SIZE(bcopy)
 
-#endif	/* lint */
-
 /*
  * Block copy with possibly overlapped operands.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-ovbcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(ovbcopy)
 	tst	%o2			! check count
 	bgu,a	%ncc, 1f		! nothing to do or bad arguments
@@ -432,8 +401,6 @@
 	nop
 	SET_SIZE(ovbcopy)
 
-#endif	/* lint */
-
 /*
  * hwblkpagecopy()
  *
@@ -441,12 +408,6 @@
  * has already disabled kernel preemption and has checked
  * use_hw_bcopy.
  */
-#ifdef lint
-/*ARGSUSED*/
-void
-hwblkpagecopy(const void *src, void *dst)
-{ }
-#else /* lint */
 	ENTRY(hwblkpagecopy)
 	save	%sp, -SA(MINFRAME), %sp
 
@@ -509,7 +470,6 @@
 	ret
 	restore	%g0, 0, %o0
 	SET_SIZE(hwblkpagecopy)
-#endif	/* lint */
 
 
 /*
@@ -579,15 +539,6 @@
  * Copy kernel data to user space (copyout/xcopyout/xcopyout_little).
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * We save the arguments in the following registers in case of a fault:
  * 	kaddr - %g2
@@ -821,18 +772,7 @@
 	mov	-1, %o0
 	SET_SIZE(copyout)
 
-#endif	/* lint */
 
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout)
 	sethi	%hi(.xcopyout_err), REAL_LOFAULT
 	b	.do_copyout
@@ -849,17 +789,6 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyout)
 
-#endif	/* lint */
-	
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout_little(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout_little)
 	sethi	%hi(.little_err), %o4
 	ldn	[THREAD_REG + T_LOFAULT], %o5
@@ -887,21 +816,10 @@
 	mov	%g0, %o0		! return (0)
 	SET_SIZE(xcopyout_little)
 
-#endif	/* lint */
-
 /*
  * Copy user data to kernel space (copyin/xcopyin/xcopyin_little)
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyin)
 	sethi	%hi(.copyin_err), REAL_LOFAULT
 	or	REAL_LOFAULT, %lo(.copyin_err), REAL_LOFAULT
@@ -1091,17 +1009,6 @@
 	mov	-1, %o0
 	SET_SIZE(copyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin)
 	sethi	%hi(.xcopyin_err), REAL_LOFAULT
 	b	.do_copyin
@@ -1118,17 +1025,6 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin_little(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin_little)
 	sethi	%hi(.little_err), %o4
 	ldn	[THREAD_REG + T_LOFAULT], %o5
@@ -1162,22 +1058,12 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyin_little)
 
-#endif	/* lint */
 
-
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  * No fault handler installed (to be called under on_fault())
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-copyin_noerr(const void *ufrom, void *kto, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(copyin_noerr)
 	sethi	%hi(.copyio_noerr), REAL_LOFAULT
 	b	.do_copyin
@@ -1187,22 +1073,11 @@
 	  nop
 	SET_SIZE(copyin_noerr)
 
-#endif /* lint */
-
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  * No fault handler installed (to be called under on_fault())
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-copyout_noerr(const void *kfrom, void *uto, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(copyout_noerr)
 	sethi	%hi(.copyio_noerr), REAL_LOFAULT
 	b	.do_copyout
@@ -1209,15 +1084,6 @@
 	  or	REAL_LOFAULT, %lo(.copyio_noerr), REAL_LOFAULT
 	SET_SIZE(copyout_noerr)
 
-#endif /* lint */
-
-#if defined(lint)
-
-int use_hw_bcopy = 1;
-int use_hw_bzero = 1;
-
-#else /* !lint */
-
 	.align	4
 	DGDEF(use_hw_bcopy)
 	.word	1
@@ -1226,7 +1092,6 @@
 
 	.align	64
 	.section ".text"
-#endif /* !lint */
 
 
 /*
@@ -1237,14 +1102,6 @@
  * Caller is responsible for ensuring use_hw_bzero is true and that
  * kpreempt_disable() has been called.
  */
-#ifdef lint
-/*ARGSUSED*/
-int
-hwblkclr(void *addr, size_t len)
-{ 
-	return(0);
-}
-#else /* lint */
 	! %i0 - start address
 	! %i1 - length of region (multiple of 64)
 
@@ -1259,16 +1116,7 @@
 	restore	%g0, 1, %o0	! return (1) - did not use block operations
 
 	SET_SIZE(hwblkclr)
-#endif	/* lint */
 
-#ifdef	lint
-/* Copy 32 bytes of data from src to dst using physical addresses */
-/*ARGSUSED*/
-void
-hw_pa_bcopy32(uint64_t src, uint64_t dst)
-{}
-#else	/*!lint */
-
 	/*
 	 * Copy 32 bytes of data from src (%o0) to dst (%o1)
 	 * using physical addresses.
@@ -1297,7 +1145,6 @@
 	retl
 	  wrpr    %g0, %g1, %pstate
 	SET_SIZE(hw_pa_bcopy32)
-#endif /* lint */
 
 /*
  * Zero a block of storage.
@@ -1306,20 +1153,6 @@
  */
 
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-kzero(void *addr, size_t count)
-{ return(0); }
-
-/* ARGSUSED */
-void
-uzero(void *addr, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(uzero)
 	!
 	! Set a new lo_fault handler only if we came in with one
@@ -1392,21 +1225,10 @@
 	SET_SIZE(kzero)
 	SET_SIZE(uzero)
 
-#endif	/* lint */
-
 /*
  * Zero a block of storage.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-bzero(void *addr, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(bzero)
 	wr	%g0, ASI_P, %asi
 
@@ -1596,4 +1418,3 @@
 	clr	%o0			! return (0)
 
 	SET_SIZE(bzero)
-#endif	/* lint */
--- old/usr/src/uts/sun4v/cpu/niagara2_asm.s	Thu Nov 14 19:00:52 2019
+++ new/usr/src/uts/sun4v/cpu/niagara2_asm.s	Thu Nov 14 19:00:52 2019
@@ -23,9 +23,7 @@
  * Use is subject to license terms.
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif
 
 /*
  * Niagara2 processor specific assembly routines
@@ -40,19 +38,6 @@
 #include <sys/niagaraasi.h>
 #include <vm/hat_sfmmu.h>
 
-#if defined(lint)
-/*ARGSUSED*/
-uint64_t
-hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niagara_setperf(uint64_t perfreg, uint64_t data)
-{ return (0); }
-
-#else   /* lint */
-
 	/*
 	 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
 	 */
@@ -89,27 +74,6 @@
 	nop
 	SET_SIZE(hv_niagara_setperf)
 
-#endif /* !lint */
-
-#if defined (lint)
-/*
- * Invalidate all of the entries within the TSB, by setting the inv bit
- * in the tte_tag field of each tsbe.
- *
- * We take advantage of the fact that the TSBs are page aligned and a
- * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
- *
- * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
- * (in short, we set all bits in the upper word of the tag, and we give the
- * invalid bit precedence over other tag bits in both places).
- */
-/*ARGSUSED*/
-void
-cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
-{}
-
-#else /* lint */
-
 	ENTRY(cpu_inv_tsb)
 
 	/*
@@ -151,18 +115,7 @@
 	nop
 
 	SET_SIZE(cpu_inv_tsb)
-#endif /* lint */
 
-#if defined (lint)
-/*
- * This is CPU specific delay routine for atomic backoff. It is used in case
- * of Niagara2 and VF CPUs. The rd instruction uses less resources than casx
- * on these CPUs.
- */
-void
-cpu_atomic_delay(void)
-{}
-#else	/* lint */
 	ENTRY(cpu_atomic_delay)
 	rd	%ccr, %g0
 	rd	%ccr, %g0
@@ -169,4 +122,3 @@
 	retl
 	rd	%ccr, %g0
 	SET_SIZE(cpu_atomic_delay)
-#endif	/* lint */
--- old/usr/src/uts/sun4v/cpu/niagara_asm.s	Thu Nov 14 19:00:52 2019
+++ new/usr/src/uts/sun4v/cpu/niagara_asm.s	Thu Nov 14 19:00:52 2019
@@ -23,11 +23,7 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
-#endif
 
 /*
  * Niagara processor specific assembly routines
@@ -42,19 +38,6 @@
 #include <sys/niagaraasi.h>
 #include <vm/hat_sfmmu.h>
 
-#if defined(lint)
-/*ARGSUSED*/
-uint64_t
-hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niagara_setperf(uint64_t perfreg, uint64_t data)
-{ return (0); }
-
-#else   /* lint */
-
 	/*
 	 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
 	 */
@@ -79,27 +62,6 @@
 	nop
 	SET_SIZE(hv_niagara_setperf)
 
-#endif /* !lint */
-
-#if defined (lint)
-/*
- * Invalidate all of the entries within the TSB, by setting the inv bit
- * in the tte_tag field of each tsbe.
- *
- * We take advantage of the fact that the TSBs are page aligned and a
- * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
- *
- * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
- * (in short, we set all bits in the upper word of the tag, and we give the
- * invalid bit precedence over other tag bits in both places).
- */
-/*ARGSUSED*/
-void
-cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
-{}
-
-#else /* lint */
-
 	ENTRY(cpu_inv_tsb)
 
 	/*
@@ -141,21 +103,7 @@
 	nop
 
 	SET_SIZE(cpu_inv_tsb)
-#endif /* lint */
 
-#if defined(lint)
-/*ARGSUSED*/
-uint64_t
-hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_niagara_mmustat_info(uint64_t *buf)
-{ return (0); }
-
-#else   /* lint */
-
 	/*
 	 * hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf)
 	 */
@@ -178,4 +126,3 @@
 	stx	%o1, [%o4]
 	SET_SIZE(hv_niagara_mmustat_info)
 
-#endif /* !lint */
--- old/usr/src/uts/sun4v/cpu/niagara_copy.s	Thu Nov 14 19:00:53 2019
+++ new/usr/src/uts/sun4v/cpu/niagara_copy.s	Thu Nov 14 19:00:53 2019
@@ -35,9 +35,7 @@
 #include <sys/machasi.h>
 #include <sys/niagaraasi.h>
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 
 /*
@@ -374,8 +372,6 @@
 	faddd	%f0, %f2, %f60		;\
 	fmuld	%f0, %f2, %f62
 
-#if !defined(lint)
-
 /*
  * Macros to save and restore fp registers to/from the stack.
  * Used to save and restore in-use fp registers when we want to use FP.
@@ -401,9 +397,8 @@
 	add	tmp1, VIS_BLOCKSIZE, tmp1			;\
 	ldda	[tmp1]ASI_BLK_P, %f48				;\
 	membar	#Sync
-#endif	/* NIAGARA_IMPL */
 
-#endif	/* lint */
+#endif
 /*
  * Copy a block of storage, returning an error code if `from' or
  * `to' takes a kernel pagefault which cannot be resolved.
@@ -410,15 +405,6 @@
  * Returns errno value on pagefault error, 0 if all ok
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-kcopy(const void *from, void *to, size_t count)
-{ return(0); }
-
-#else	/* lint */
-
 	.seg	".text"
 	.align	4
 
@@ -592,21 +578,12 @@
 #endif	/* NIAGARA_IMPL */
 
 	SET_SIZE(kcopy)
-#endif	/* lint */
 
 
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-bcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(bcopy)
 #if !defined(NIAGARA_IMPL)
 	cmp	%o2, FP_COPY			! check for small copy/leaf case
@@ -2686,21 +2663,10 @@
 
 #endif	/* NIAGARA_IMPL */
 
-#endif	/* lint */
-
 /*
  * Block copy with possibly overlapped operands.
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-ovbcopy(const void *from, void *to, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(ovbcopy)
 	tst	%o2			! check count
 	bgu,a	%ncc, 1f		! nothing to do or bad arguments
@@ -2743,8 +2709,6 @@
 	nop
 	SET_SIZE(ovbcopy)
 
-#endif	/* lint */
-
 /*
  * hwblkpagecopy()
  *
@@ -2752,12 +2716,6 @@
  * has already disabled kernel preemption and has checked
  * use_hw_bcopy.
  */
-#ifdef lint
-/*ARGSUSED*/
-void
-hwblkpagecopy(const void *src, void *dst)
-{ }
-#else /* lint */
 	ENTRY(hwblkpagecopy)
 	save	%sp, -SA(MINFRAME), %sp
 
@@ -2810,7 +2768,6 @@
 	ret
 	restore	%g0, 0, %o0
 	SET_SIZE(hwblkpagecopy)
-#endif	/* lint */
 
 
 /*
@@ -2904,15 +2861,6 @@
  * Copy kernel data to user space (copyout/xcopyout/xcopyout_little).
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * We save the arguments in the following registers in case of a fault:
  * 	kaddr - %g2
@@ -5099,18 +5047,7 @@
 #endif	/* NIAGARA_IMPL */
 	SET_SIZE(copyout)
 
-#endif	/* lint */
 
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout)
 	sethi	%hi(.xcopyout_err), REAL_LOFAULT
 	b	.do_copyout
@@ -5127,17 +5064,6 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyout)
 
-#endif	/* lint */
-	
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyout_little(const void *kaddr, void *uaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyout_little)
 	sethi	%hi(.little_err), %o4
 	ldn	[THREAD_REG + T_LOFAULT], %o5
@@ -5165,21 +5091,10 @@
 	mov	%g0, %o0		! return (0)
 	SET_SIZE(xcopyout_little)
 
-#endif	/* lint */
-
 /*
  * Copy user data to kernel space (copyin/xcopyin/xcopyin_little)
  */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-copyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(copyin)
 	sethi	%hi(.copyin_err), REAL_LOFAULT
 	or	REAL_LOFAULT, %lo(.copyin_err), REAL_LOFAULT
@@ -7283,17 +7198,6 @@
 #endif	/* NIAGARA_IMPL */
 	SET_SIZE(copyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin)
 	sethi	%hi(.xcopyin_err), REAL_LOFAULT
 	b	.do_copyin
@@ -7310,17 +7214,6 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyin)
 
-#endif	/* lint */
-
-#ifdef	lint
-
-/*ARGSUSED*/
-int
-xcopyin_little(const void *uaddr, void *kaddr, size_t count)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(xcopyin_little)
 	sethi	%hi(.little_err), %o4
 	ldn	[THREAD_REG + T_LOFAULT], %o5
@@ -7354,22 +7247,12 @@
 	mov	%g1, %o0
 	SET_SIZE(xcopyin_little)
 
-#endif	/* lint */
 
-
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  * No fault handler installed (to be called under on_fault())
  */
-#if defined(lint)
 
-/* ARGSUSED */
-void
-copyin_noerr(const void *ufrom, void *kto, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(copyin_noerr)
 	sethi	%hi(.copyio_noerr), REAL_LOFAULT
 	b	.do_copyin
@@ -7379,22 +7262,11 @@
 	nop
 	SET_SIZE(copyin_noerr)
 
-#endif /* lint */
-
 /*
  * Copy a block of storage - must not overlap (from + len <= to).
  * No fault handler installed (to be called under on_fault())
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-copyout_noerr(const void *kfrom, void *uto, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(copyout_noerr)
 	sethi	%hi(.copyio_noerr), REAL_LOFAULT
 	b	.do_copyout
@@ -7401,19 +7273,6 @@
 	or	REAL_LOFAULT, %lo(.copyio_noerr), REAL_LOFAULT
 	SET_SIZE(copyout_noerr)
 
-#endif /* lint */
-
-#if defined(lint)
-
-int use_hw_bcopy = 1;
-int use_hw_bzero = 1;
-uint_t hw_copy_limit_1 = 0x100;
-uint_t hw_copy_limit_2 = 0x200;
-uint_t hw_copy_limit_4 = 0x400;
-uint_t hw_copy_limit_8 = 0x400;
-
-#else /* !lint */
-
 	.align	4
 	DGDEF(use_hw_bcopy)
 	.word	1
@@ -7430,7 +7289,6 @@
 
 	.align	64
 	.section ".text"
-#endif /* !lint */
 
 /*
  * hwblkclr - clears block-aligned, block-multiple-sized regions that are
@@ -7440,14 +7298,6 @@
  * Caller is responsible for ensuring use_hw_bzero is true and that
  * kpreempt_disable() has been called.
  */
-#ifdef lint
-/*ARGSUSED*/
-int
-hwblkclr(void *addr, size_t len)
-{ 
-	return(0);
-}
-#else /* lint */
 	! %i0 - start address
 	! %i1 - length of region (multiple of 64)
 
@@ -7545,16 +7395,7 @@
 	ret
 	restore	%g0, 0, %o0		! return (bzero or not)
 	SET_SIZE(hwblkclr)
-#endif	/* lint */
 
-#ifdef	lint
-/* Copy 32 bytes of data from src to dst using physical addresses */
-/*ARGSUSED*/
-void
-hw_pa_bcopy32(uint64_t src, uint64_t dst)
-{}
-#else	/*!lint */
-
 	/*
 	 * Copy 32 bytes of data from src (%o0) to dst (%o1)
 	 * using physical addresses.
@@ -7583,7 +7424,6 @@
 	retl
 	wrpr	%g0, %g1, %pstate
 	SET_SIZE(hw_pa_bcopy32)
-#endif /* lint */
 
 /*
  * Zero a block of storage.
@@ -7608,20 +7448,6 @@
  *	Store as many 8-byte chunks, followed by trailing bytes.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-kzero(void *addr, size_t count)
-{ return(0); }
-
-/* ARGSUSED */
-void
-uzero(void *addr, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(uzero)
 	!
 	! Set a new lo_fault handler only if we came in with one
@@ -7694,21 +7520,10 @@
 	SET_SIZE(kzero)
 	SET_SIZE(uzero)
 
-#endif	/* lint */
-
 /*
  * Zero a block of storage.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-bzero(void *addr, size_t count)
-{}
-
-#else	/* lint */
-
 	ENTRY(bzero)
 	wr	%g0, ASI_P, %asi
 
@@ -7919,4 +7734,3 @@
 	clr	%o0			! return (0)
 
 	SET_SIZE(bzero)
-#endif	/* lint */
--- old/usr/src/uts/sun4v/io/ds_pri_hcall.s	Thu Nov 14 19:00:54 2019
+++ new/usr/src/uts/sun4v/io/ds_pri_hcall.s	Thu Nov 14 19:00:54 2019
@@ -31,15 +31,6 @@
 #include <sys/asm_linkage.h>
 #include <sys/hypervisor_api.h>
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-hv_mach_pri(uint64_t buffer_ra, uint64_t *buffer_sizep)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	/*
 	 * MACH_PRI
 	 * arg0 buffer real address
@@ -56,4 +47,3 @@
 	stx	%o1, [%o4]
 	SET_SIZE(hv_mach_pri)
 
-#endif	/* lint || __lint */
--- old/usr/src/uts/sun4v/io/fpc/fpc-asm-4v.s	Thu Nov 14 19:00:54 2019
+++ new/usr/src/uts/sun4v/io/fpc/fpc-asm-4v.s	Thu Nov 14 19:00:54 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Assembly language support for sun4v px driver
  */
@@ -38,22 +36,6 @@
 
 /*LINTLIBRARY*/
 
-#if defined(lint)
-
-#include "fpc-impl-4v.h"
-
-/*ARGSUSED*/	
-int
-fpc_get_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t *data)
-{ return (0); }
-
-/*ARGSUSED*/	
-int
-fpc_set_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t data)
-{ return (0); }
-
-#else /* lint */
-
 	/*
 	 * fpc_get_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t *data)
 	 */
@@ -77,4 +59,3 @@
 	SET_SIZE(fpc_set_fire_perfreg)
 
 
-#endif
--- old/usr/src/uts/sun4v/io/glvc/glvc_hcall.s	Thu Nov 14 19:00:54 2019
+++ new/usr/src/uts/sun4v/io/glvc/glvc_hcall.s	Thu Nov 14 19:00:54 2019
@@ -23,8 +23,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Hypervisor calls called by glvc driver.
 */
@@ -33,37 +31,6 @@
 #include <sys/hypervisor_api.h>
 #include <sys/glvc.h>
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-hv_service_recv(uint64_t s_id, uint64_t buf_pa, uint64_t size,
-    uint64_t *recv_bytes)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_service_send(uint64_t s_id, uint64_t buf_pa, uint64_t size,
-    uint64_t *send_bytes)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_service_getstatus(uint64_t s_id, uint64_t *vreg)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_service_setstatus(uint64_t s_id, uint64_t bits)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_service_clrstatus(uint64_t s_id, uint64_t bits)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	/*
 	 * hv_service_recv(uint64_t s_id, uint64_t buf_pa,
 	 *     uint64_t size, uint64_t *recv_bytes);
@@ -138,4 +105,3 @@
 	nop
 	SET_SIZE(hv_service_clrstatus)
 
-#endif	/* lint || __lint */
--- old/usr/src/uts/sun4v/io/iospc/rfios_asm.s	Thu Nov 14 19:00:54 2019
+++ new/usr/src/uts/sun4v/io/iospc/rfios_asm.s	Thu Nov 14 19:00:54 2019
@@ -34,20 +34,6 @@
 
 /*LINTLIBRARY*/
 
-#if defined(lint)
-
-/*ARGSUSED*/	
-int
-rfiospc_get_perfreg(cntr_handle_t handle, int regid, uint64_t *data)
-{ return (0); }
-
-/*ARGSUSED*/	
-int
-rfiospc_set_perfreg(cntr_handle_t handle, int regid, uint64_t data)
-{ return (0); }
-
-#else /* lint */
-
 	ENTRY(rfiospc_get_perfreg)
 	mov	RFIOS_GET_PERFREG, %o5
 	ta	FAST_TRAP
@@ -64,4 +50,3 @@
 	nop
 	SET_SIZE(rfiospc_set_perfreg)
 
-#endif
--- old/usr/src/uts/sun4v/io/n2piupc/n2piupc_asm.s	Thu Nov 14 19:00:55 2019
+++ new/usr/src/uts/sun4v/io/n2piupc/n2piupc_asm.s	Thu Nov 14 19:00:55 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Assembly language support for the n2piupc N2 PIU performance counter driver.
  */
@@ -36,20 +34,6 @@
 
 /*LINTLIBRARY*/
 
-#if defined(lint)
-
-/*ARGSUSED*/	
-int
-n2piupc_get_perfreg(cntr_handle_t handle, int regid, uint64_t *data)
-{ return (0); }
-
-/*ARGSUSED*/	
-int
-n2piupc_set_perfreg(cntr_handle_t handle, int regid, uint64_t data)
-{ return (0); }
-
-#else /* lint */
-
 	ENTRY(n2piupc_get_perfreg)
 	mov	N2PIU_GET_PERFREG, %o5
 	ta	FAST_TRAP
@@ -66,4 +50,3 @@
 	nop
 	SET_SIZE(n2piupc_set_perfreg)
 
-#endif
--- old/usr/src/uts/sun4v/io/n2rng/n2rng_hcall.s	Thu Nov 14 19:00:55 2019
+++ new/usr/src/uts/sun4v/io/n2rng/n2rng_hcall.s	Thu Nov 14 19:00:55 2019
@@ -23,8 +23,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Hypervisor calls called by ncp driver.
  */
@@ -33,54 +31,6 @@
 #include <sys/hypervisor_api.h>
 #include <sys/n2rng.h>
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-hv_rng_get_diag_control()
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_rng_ctl_read(uint64_t ctlregsptr_ra, uint64_t *rstate, uint64_t *tdelta)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_rng_ctl_read_v2(uint64_t ctlregsptr_ra, uint64_t rngid, uint64_t *rstate,
-		uint64_t *tdelta, uint64_t *wdelta, uint64_t *wstate)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_rng_ctl_write(uint64_t ctlregsptr_ra, uint64_t nstate, uint64_t wtimeout,
-		uint64_t *tdelta)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_rng_ctl_write_v2(uint64_t ctlregsptr_ra, uint64_t nstate, uint64_t wtimeout,
-		uint64_t rngid)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_rng_data_read_diag(uint64_t buffer_ra, uint64_t sz, uint64_t *tdelta)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_rng_data_read_diag_v2(uint64_t buffer_ra, uint64_t sz, uint64_t rngid,
-		uint64_t *tdelta)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_rng_data_read(uint64_t buffer_ra, uint64_t *tdelta)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	/*
 	 * hv_rng_get_diag_control()
 	 */
@@ -183,4 +133,3 @@
 	stx	%o1, [%o4]
 	SET_SIZE(hv_rng_data_read)
 
-#endif	/* lint || __lint */
--- old/usr/src/uts/sun4v/io/pciex/pci_cfgacc_asm.s	Thu Nov 14 19:00:55 2019
+++ new/usr/src/uts/sun4v/io/pciex/pci_cfgacc_asm.s	Thu Nov 14 19:00:55 2019
@@ -35,22 +35,6 @@
 #include <io/px/px_ioapi.h>
 #include <io/px/px_lib4v.h>
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 
-    pci_config_size_t size, pci_cfg_data_t *data_p)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 
-    pci_config_size_t size, pci_cfg_data_t data)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	/*
 	 * arg0 - devhandle
 	 * arg1 - pci_device
@@ -90,4 +74,3 @@
 	retl
 	nop
 	SET_SIZE(hvio_config_put)
-#endif
--- old/usr/src/uts/sun4v/io/px/px_hcall.s	Thu Nov 14 19:00:56 2019
+++ new/usr/src/uts/sun4v/io/px/px_hcall.s	Thu Nov 14 19:00:56 2019
@@ -34,186 +34,6 @@
 #include <px_ioapi.h>
 #include "px_lib4v.h"
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
-    io_attributes_t attr, io_page_list_t *io_page_list_p,
-    pages_t *pages_mapped)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
-    pages_t *pages_demapped)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p,
-    r_addr_t *r_addr_p)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr,
-    io_addr_t *io_addr_p)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status,
-    uint64_t *data_p)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data,
-    r_addr_t ra2, uint32_t *rdbk_status)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes,
-    io_sync_direction_t io_sync_direction, size_t *bytes_synched)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra,
-    uint_t msiq_rec_cnt)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p,
-    uint_t *msiq_rec_cnt_p)
-{ return (0); }
-	
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
-    pci_msiq_valid_state_t *msiq_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
-    pci_msiq_valid_state_t msiq_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
-    pci_msiq_state_t *msiq_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
-    pci_msiq_state_t msiq_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
-    msiqhead_t *msiq_head)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
-    msiqhead_t msiq_head)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
-    msiqtail_t *msiq_tail)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
-    msiqid_t *msiq_id)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
-    msiqid_t msiq_id, msi_type_t msitype)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
-    pci_msi_valid_state_t *msi_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
-    pci_msi_valid_state_t msi_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
-    pci_msi_state_t *msi_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
-    pci_msi_state_t msi_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
-    msiqid_t *msiq_id)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
-    msiqid_t msiq_id)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
-    pcie_msg_valid_state_t *msg_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
-    pcie_msg_valid_state_t msg_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-pci_error_send(devhandle_t dev_hdl, devino_t devino, pci_device_t bdf)
-{ return (0); }
-
-/*
- * First arg to both of these functions is a dummy, to accomodate how
- * hv_hpriv() works.
- */
-/*ARGSUSED*/
-int
-px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-pci_iov_root_configured(devhandle_t dev_hdl)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	/*
 	 * arg0 - devhandle
 	 * arg1 - tsbid
@@ -707,4 +527,3 @@
 	nop
 	SET_SIZE(pci_iov_root_configured)
 
-#endif	/* lint || __lint */
--- old/usr/src/uts/sun4v/io/vnet_dds_hcall.s	Thu Nov 14 19:00:56 2019
+++ new/usr/src/uts/sun4v/io/vnet_dds_hcall.s	Thu Nov 14 19:00:56 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Hypervisor calls called by niu leaf driver.
 */
@@ -43,35 +41,6 @@
 #define N2NIU_VRTX_SET_INO	0x151
 
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-vdds_hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-vdds_hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-vdds_hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-vdds_hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vch_idx, uint32_t ino)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-vdds_hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vch_idx, uint32_t ino)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	/*
 	 * vdds_hv_niu_vr_getinfo(uint32_t cookie, uint64_t &real_start,
 	 *     uint64_t &size)
@@ -128,4 +97,3 @@
 	nop
 	SET_SIZE(vdds_hv_niu_vrtx_set_ino)
 
-#endif	/* lint || __lint */
--- old/usr/src/uts/sun4v/ml/hcall.s	Thu Nov 14 19:00:56 2019
+++ new/usr/src/uts/sun4v/ml/hcall.s	Thu Nov 14 19:00:56 2019
@@ -32,341 +32,6 @@
 #include <sys/machparam.h>
 #include <sys/hypervisor_api.h>
 
-#if defined(lint) || defined(__lint)
-
-/*ARGSUSED*/
-uint64_t
-hv_mach_exit(uint64_t exit_code)
-{ return (0); }
-
-uint64_t
-hv_mach_sir(void)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_cpu_stop(uint64_t cpuid)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_cpu_set_rtba(uint64_t *rtba)
-{ return (0); }
-
-/*ARGSUSED*/
-int64_t
-hv_cnputchar(uint8_t ch)
-{ return (0); }
-
-/*ARGSUSED*/
-int64_t
-hv_cngetchar(uint8_t *ch)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_tod_get(uint64_t *seconds)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_tod_set(uint64_t seconds)
-{ return (0);}
-
-/*ARGSUSED*/
-uint64_t
-hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags)
-{ return (0); }
-
-/*ARGSUSED */
-uint64_t
-hv_mmu_fault_area_conf(void *raddr)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra)
-{ return (0); }
-
-#ifdef SET_MMU_STATS
-/*ARGSUSED*/
-uint64_t
-hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size)
-{ return (0); }
-#endif /* SET_MMU_STATS */
-
-/*ARGSUSED*/
-uint64_t
-hv_cpu_qconf(int queue, uint64_t paddr, int size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_intr_setvalid(uint64_t sysino, int intr_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_intr_getstate(uint64_t sysino, int *intr_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_intr_setstate(uint64_t sysino, int intr_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvio_intr_settarget(uint64_t sysino, uint32_t cpuid)
-{ return (0); }
-
-uint64_t
-hv_cpu_yield(void)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_ra2pa(uint64_t ra)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_tx_get_state(uint64_t channel, 
-	uint64_t *headp, uint64_t *tailp, uint64_t *state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_rx_get_state(uint64_t channel, 
-	uint64_t *headp, uint64_t *tailp, uint64_t *state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie,
-	uint64_t raddr, uint64_t length, uint64_t *lengthp)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor,
-    uint64_t *supported_minor)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_tm_enable(uint64_t enable)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining)
-{ return (0); }
-
-/*ARGSUSED*/
-int64_t
-hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount)
-{ return (0); }
-
-/*ARGSUSED*/
-int64_t
-hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount)
-{ return (0); }
-
-/*ARGSUSED*/
-uint64_t
-hv_soft_state_set(uint64_t state, uint64_t string)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_soft_state_get(uint64_t string, uint64_t *state)
-{ return (0); }uint64_t
-hv_guest_suspend(void)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_tick_set_npt(uint64_t npt)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_stick_set_npt(uint64_t npt)
-{ return (0); }
-
-/*ARGSUSED*/	
-uint64_t
-hv_reboot_data_set(uint64_t buffer_ra, uint64_t buffer_len)
-{ return (0); }
-
-#else	/* lint || __lint */
-
 	/*
 	 * int hv_mach_exit(uint64_t exit_code)
 	 */
@@ -1298,4 +963,3 @@
 	nop
 	SET_SIZE(hv_reboot_data_set)
 
-#endif	/* lint || __lint */
--- old/usr/src/uts/sun4v/ml/mach_interrupt.s	Thu Nov 14 19:00:57 2019
+++ new/usr/src/uts/sun4v/ml/mach_interrupt.s	Thu Nov 14 19:00:57 2019
@@ -23,12 +23,7 @@
  * Use is subject to license terms.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/thread.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>
@@ -47,15 +42,7 @@
 #include <sys/traptrace.h>
 #endif /* TRAPTRACE */
 
-#if defined(lint)
 
-void
-cpu_mondo(void)
-{}
-
-#else	/* lint */
-
-
 /*
  * (TT 0x7c, TL>0) CPU Mondo Queue Handler
  *	Globals are the Interrupt Globals.
@@ -195,17 +182,7 @@
 	/* Never Reached */
 	SET_SIZE(cpu_mondo)
 
-#endif /* lint */
 
-#if defined(lint)
-
-void
-dev_mondo(void)
-{}
-
-#else	/* lint */
-
-
 /*
  * (TT 0x7d, TL>0) Dev Mondo Queue Handler
  *	Globals are the Interrupt Globals.
@@ -344,11 +321,7 @@
 
 	/* Never Reached */
 	SET_SIZE(dev_mondo)
-#endif /* lint */
 
-#if defined(lint)
-uint64_t cpu_mondo_inval;
-#else /* lint */
 	.seg	".data"
 	.global	cpu_mondo_inval
 	.align	8
@@ -356,17 +329,8 @@
 	.skip	8
 
 	.seg	".text"
-#endif	/* lint */
 
 
-#if defined(lint)
-
-void
-resumable_error(void)
-{}
-
-#else	/* lint */
-
 /*
  * (TT 0x7e, TL>0) Resumeable Error Queue Handler
  *	We keep a shadow copy of the queue in kernel buf.
@@ -482,16 +446,7 @@
 
 	/*NOTREACHED*/
 	SET_SIZE(resumable_error)
-#endif /* lint */
 
-#if defined(lint)
-
-void
-nonresumable_error(void)
-{}
-
-#else	/* lint */
-
 /*
  * (TT 0x7f, TL>0) Non-resumeable Error Queue Handler
  *	We keep a shadow copy of the queue in kernel buf.
@@ -663,4 +618,3 @@
 
 	/*NOTREACHED*/
 	SET_SIZE(nonresumable_error)
-#endif /* lint */
--- old/usr/src/uts/sun4v/ml/mach_locore.s	Thu Nov 14 19:00:57 2019
+++ new/usr/src/uts/sun4v/ml/mach_locore.s	Thu Nov 14 19:00:57 2019
@@ -23,13 +23,6 @@
  * Use is subject to license terms.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/t_lock.h>
-#include <sys/promif.h>
-#include <sys/prom_isa.h>
-#endif	/* lint */
-
 #include <sys/asm_linkage.h>
 #include <sys/intreg.h>
 #include <sys/ivintr.h>
@@ -46,13 +39,6 @@
 #include <sys/hypervisor_api.h>
 #include <sys/clock.h>
 
-#if defined(lint)
-
-#include <sys/thread.h>
-#include <sys/time.h>
-
-#else	/* lint */
-
 #include "assym.h"
 
 
@@ -182,16 +168,6 @@
 _local_p1275cis:
 	.nword	0
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-_start(void)
-{}
-
-#else /* lint */
-
 	.seg	".data"
 
 	.global nwindows, nwin_minus_one, winmask
@@ -364,9 +340,7 @@
 	.asciz	"main returned"
 	.align	4
 
-#endif	/* lint */
 
-
 /*
  * Generic system trap handler.
  *
@@ -402,14 +376,6 @@
  *	    uint32_t arg2 [%g3.l], uint32_t arg3 [%g3.h], uint32_t [%g2.h])
  */
 
-#if defined(lint)
-
-void
-sys_trap(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(sys_trap)
 #ifdef DEBUG
 	! Assert gl == 1
@@ -1047,10 +1013,6 @@
 	SET_SIZE(priv_rtt)
 	SET_SIZE(ktl0)
 
-#endif	/* lint */
-
-#ifndef lint
-
 #ifdef DEBUG
 	.seg	".data"
 	.align	4
@@ -1071,7 +1033,6 @@
 	mov	%o3, %o2
 	SET_SIZE(bad_g4)
 #endif /* DEBUG */
-#endif /* lint */
 
 /*
  * sys_tl1_panic can be called by traps at tl1 which
@@ -1078,13 +1039,6 @@
  * really want to panic, but need the rearrangement of
  * the args as provided by this wrapper routine.
  */
-#if defined(lint)
-
-void
-sys_tl1_panic(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(sys_tl1_panic)
 	mov	%o1, %o0
 	mov	%o2, %o1
@@ -1091,7 +1045,6 @@
 	call	panic
 	mov	%o3, %o2
 	SET_SIZE(sys_tl1_panic)
-#endif /* lint */
 
 
 /*
@@ -1101,29 +1054,11 @@
  * This is used for context switching.
  */
 
-#if defined(lint)
-
-void
-flush_windows(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(flush_windows)
 	retl
 	flushw
 	SET_SIZE(flush_windows)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-debug_flush_windows(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(debug_flush_windows)
 	set	nwindows, %g1
 	ld	[%g1], %g1
@@ -1145,20 +1080,10 @@
 
 	SET_SIZE(debug_flush_windows)
 
-#endif	/* lint */
-
 /*
  * flush user windows to memory.
  */
 
-#if defined(lint)
-
-void
-flush_user_windows(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(flush_user_windows)
 	rdpr	%otherwin, %g1
 	brz	%g1, 3f
@@ -1177,8 +1102,6 @@
 	nop
 	SET_SIZE(flush_user_windows)
 
-#endif	/* lint */
-
 /*
  * Throw out any user windows in the register file.
  * Used by setregs (exec) to clean out old user.
@@ -1186,14 +1109,6 @@
  * signal.
  */
 
-#if defined(lint)
-
-void
-trash_user_windows(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(trash_user_windows)
 	rdpr	%otherwin, %g1
 	brz	%g1, 3f			! no user windows?
@@ -1219,43 +1134,16 @@
 	SET_SIZE(trash_user_windows)
 
 
-#endif	/* lint */
-
 /*
  * Setup g7 via the CPU data structure.
  */
-#if defined(lint)
 
-struct scb *
-set_tbr(struct scb *s)
-{ return (s); }
-
-#else	/* lint */
-
 	ENTRY_NP(set_tbr)
 	retl
 	ta	72		! no tbr, stop simulation
 	SET_SIZE(set_tbr)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * These need to be defined somewhere to lint and there is no "hicore.s"...
- */
-char etext[1], end[1];
-#endif	/* lint*/
-
-#if defined (lint)
-
-/* ARGSUSED */
-void
-ptl1_panic(u_int reason)
-{}
-
-#else /* lint */
-
 #define	PTL1_SAVE_WINDOW(RP)						\
 	stxa	%l0, [RP + RW64_LOCAL + (0 * RW64_LOCAL_INCR)] %asi;	\
 	stxa	%l1, [RP + RW64_LOCAL + (1 * RW64_LOCAL_INCR)] %asi;	\
@@ -1497,25 +1385,9 @@
 	  mov	%l1, %o0
 	/*NOTREACHED*/
 	SET_SIZE(ptl1_panic)
-#endif /* lint */
 
 #ifdef	PTL1_PANIC_DEBUG
-#if defined (lint)
-/*
- * ptl1_recurse() calls itself a number of times to either set up a known
- * stack or to cause a kernel stack overflow. It decrements the arguments 
- * on each recursion.
- * It's called by #ifdef PTL1_PANIC_DEBUG code in startup.c to set the
- * registers to a known state to facilitate debugging.
- */
 
-/* ARGSUSED */
-void 
-ptl1_recurse(int count_threshold, int trap_threshold)
-{}
-
-#else /* lint */
-
 	ENTRY_NP(ptl1_recurse)
 	save    %sp, -SA(MINFRAME), %sp
 
@@ -1580,16 +1452,6 @@
 	  nop 					! NOTREACHED 
         SET_SIZE(ptl1_recurse)
 
-#endif /* lint */
-
-#if defined (lint)
-
-/* ARGSUSED */
-void
-ptl1_panic_xt(int arg1, int arg2)
-{}
-
-#else /* lint */
 	/*
 	 * Asm function to handle a cross trap to call ptl1_panic()
 	 */
@@ -1598,20 +1460,10 @@
 	  mov	PTL1_BAD_DEBUG, %g1
         SET_SIZE(ptl1_panic_xt)
 
-#endif /* lint */
-
 #endif	/* PTL1_PANIC_DEBUG */
 
 #ifdef	TRAPTRACE
-#if	defined (lint)
 
-void
-trace_ptr_panic(void)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(trace_ptr_panic)
 	!
 	! freeze the trap trace to disable the assertions.  Otherwise,
@@ -1633,7 +1485,6 @@
 	mov	PTL1_BAD_TRACE_PTR, %g1
 	SET_SIZE(trace_ptr_panic)
 
-#endif	/* lint */
 #endif	/* TRAPTRACE */
 
 /*
@@ -1641,15 +1492,6 @@
  * calling the 64-bit romvec OBP.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-int
-client_handler(void *cif_handler, void *arg_array)
-{ return 0; }
-
-#else	/* lint */
-
 	ENTRY(client_handler)
 	save	%sp, -SA64(MINFRAME64), %sp	! 32 bit frame, 64 bit sized
 	sethi	%hi(tba_taken_over), %l2
@@ -1672,17 +1514,6 @@
 	restore	%o0, %g0, %o0			! delay; result in %o0
 	SET_SIZE(client_handler)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-panic_bad_hcall(uint64_t err, uint64_t hcall)
-{}
-
-#else   /* lint */
-
 	.seg	".text"
 bad_hcall_error:
 	.asciz	"hypervisor call 0x%x returned an unexpected error %d"
@@ -1703,4 +1534,3 @@
 	mov	%o3, %o7
 	SET_SIZE(panic_bad_hcall)
 
-#endif  /* lint */
--- old/usr/src/uts/sun4v/ml/mach_proc_init.s	Thu Nov 14 19:00:58 2019
+++ new/usr/src/uts/sun4v/ml/mach_proc_init.s	Thu Nov 14 19:00:58 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * sun4v processor initialization
  *
@@ -33,9 +31,7 @@
  * directly from the hypervisor. i.e. without going through OBP.
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif /* !lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/hypervisor_api.h>
@@ -45,15 +41,6 @@
 #include <sys/mmu.h>
 #include <sys/lpad.h>
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-mach_cpu_startup(uint64_t rabase, uint64_t memsz)
-{}
-
-#else	/* lint */
-
 	/*
 	 * %o0 - hcall specified arg (cpuid)
 	 * %i0 - real memory base
@@ -208,4 +195,3 @@
 	.global mach_cpu_startup_end
 mach_cpu_startup_end:
 
-#endif	/* lint */
--- old/usr/src/uts/sun4v/ml/mach_subr_asm.s	Thu Nov 14 19:00:58 2019
+++ new/usr/src/uts/sun4v/ml/mach_subr_asm.s	Thu Nov 14 19:00:58 2019
@@ -26,12 +26,7 @@
  * General machine architecture & implementation specific
  * assembly language routines.
  */
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/t_lock.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #define CPU_MODULE /* need it for NSEC_SHIFT used by NATIVE_TIME_TO_NSEC() */
 
@@ -45,14 +40,6 @@
 #include <sys/fpras.h>
 #include <sys/soft_state.h>
 
-#if defined(lint)
-
-uint64_t
-ultra_gettick(void)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * This isn't the routine you're looking for.
  *
@@ -67,47 +54,20 @@
 	nop
 	SET_SIZE(ultra_gettick)
 
-#endif	/* lint */
-
-#if defined(lint)
-/* ARGSUSED */
-void
-set_mmfsa_scratchpad(caddr_t vaddr)
-{ }
-
-#else	/* lint */
-
 	ENTRY(set_mmfsa_scratchpad)
 	stxa	%o0, [%g0]ASI_SCRATCHPAD 
 	retl
 	nop
 	SET_SIZE(set_mmfsa_scratchpad)
-#endif	/* lint */
 
-#if defined(lint)
-caddr_t
-get_mmfsa_scratchpad()
-{  return (0); }
-
-#else	/* lint */
-
 	ENTRY(get_mmfsa_scratchpad)
 	ldxa	[%g0]ASI_SCRATCHPAD, %o0 
 	retl
 	nop
 	SET_SIZE(get_mmfsa_scratchpad)
-#endif	/* lint */
 
 
 
-#if defined(lint)
-/* ARGSUSED */
-void
-cpu_intrq_unregister_powerdown(uint64_t doneflag_va)
-{}
-
-#else	/* lint */
-
 /*
  * Called from a x-trap at tl1 must use %g1 as arg
  * and save/restore %o0-%o5 after hypervisor calls
@@ -169,17 +129,8 @@
 	ba,a	0b
 
 	SET_SIZE(cpu_intrq_unregister_powerdown)
-#endif	/* lint */
 
 
-#if defined(lint)
-/* ARGSUSED */
-int
-getprocessorid(void)
-{ return (0); }
-
-#else	/* lint */
-
 /*
  * Get the processor ID.
  * === MID reg as specified in 15dec89 sun4u spec, sec 5.4.3
@@ -191,17 +142,6 @@
 	nop
 	SET_SIZE(getprocessorid)
 
-#endif	/* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-hrtime_t
-tick2ns(hrtime_t tick, uint_t cpuid)
-{ return 0; }
-
-#else	/* lint */
-
 	ENTRY_NP(tick2ns)
 	!
 	! Use nsec_scale for sun4v which is based on %stick
@@ -211,50 +151,16 @@
 	nop
 	SET_SIZE(tick2ns)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-set_cmp_error_steering(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(set_cmp_error_steering)
 	retl
 	nop
 	SET_SIZE(set_cmp_error_steering)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-uint64_t
-ultra_getver(void)
-{
-	return (0); 
-}
-
-#else /* lint */
-
 	ENTRY(ultra_getver)
 	retl
 	mov	-1, %o0		! XXXQ no version available
 	SET_SIZE(ultra_getver)
 
-#endif /* lint */
-
-#if defined(lint)
-
-int
-fpras_chkfn_type1(void)
-{ return 0; }
-
-#else	/* lint */
-
 	/*
 	 * Check instructions using just the AX pipelines, designed by
 	 * C.B. Liaw of PNP.
@@ -414,11 +320,7 @@
 	retl				! 15
 	  mov	FPRAS_BADTRAP, %o0	! 16, how detected
 	SET_SIZE(fpras_chkfn_type1)
-#endif	/* lint */
 
-#if defined(lint)
-char	soft_state_message_strings[SOLARIS_SOFT_STATE_MSG_CNT][SSM_SIZE];
-#else	/* lint */
 	.seg	".data"
 	.global soft_state_message_strings
 
@@ -442,4 +344,3 @@
 	.nword	0
 
 	.seg	".text"
-#endif	/* lint */
--- old/usr/src/uts/sun4v/ml/mach_xc.s	Thu Nov 14 19:00:58 2019
+++ new/usr/src/uts/sun4v/ml/mach_xc.s	Thu Nov 14 19:00:58 2019
@@ -23,12 +23,7 @@
  * Use is subject to license terms.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/cpuvar.h>
-#else	/*lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
@@ -42,15 +37,6 @@
 #endif /* TRAPTRACE */
 
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-self_xcall(struct cpu *cpu, uint64_t arg1, uint64_t arg2, xcfunc_t *func)
-{}
-
-#else
-
 /*
  * Entered by the software trap (TT=ST_SELFXCALL, TL>0) thru send_self_xcall().
  * Emulate the mondo handler - vec_interrupt().
@@ -104,18 +90,7 @@
 	/* Not Reached */
 	SET_SIZE(self_xcall)
 
-#endif	/* lint */
-
 #ifdef  TRAPTRACE
-#if defined(lint)
-
-/* ARGSUSED */
-void
-xc_trace(u_int traptype, cpuset_t *cpu_set, xcfunc_t *func,
-	uint64_t arg1, uint64_t arg2)
-{}
-
-#else	/* lint */
 	ENTRY(xc_trace)
 	rdpr	%pstate, %g1
 	andn	%g1, PSTATE_IE | PSTATE_AM, %g2
@@ -188,22 +163,8 @@
 	wrpr	%g0, %g1, %pstate			/* enable interrupts */
 	SET_SIZE(xc_trace)
 
-#endif	/* lint */
 #endif	/* TRAPTRACE */
 
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-/*ARGSUSED*/
-int
-shipit(int n, uint64_t cpuid)
-{ return(0); }
-
-#else	/* lint */
 /*
  * Setup interrupt dispatch data registers
  * Entry:
@@ -241,16 +202,6 @@
 	membar	#Sync
 	SET_SIZE(shipit)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-uint64_t
-get_cpuaddr(uint64_t reg, uint64_t scr)
-{ return (0);}
-
-#else	/* lint */
 /*
  * Get cpu structure
  * Entry:
@@ -263,15 +214,6 @@
 	nop
 	SET_SIZE(get_cpuaddr)
 
-#endif	/* lint */
-
-#if defined(lint)
-/* ARGSUSED */
-void
-xt_sync_tl1(uint64_t *cpu_sync_addr)
-{}
-
-#else /* lint */
 /*
  * This is to ensure that previously called xtrap handlers have executed on
  * sun4v. We zero out the byte corresponding to its cpuid in the
@@ -286,4 +228,3 @@
 	retry
 	SET_SIZE(xt_sync_tl1)
 
-#endif  /* lint */
--- old/usr/src/uts/sun4v/ml/trap_table.s	Thu Nov 14 19:00:59 2019
+++ new/usr/src/uts/sun4v/ml/trap_table.s	Thu Nov 14 19:00:59 2019
@@ -24,9 +24,7 @@
  * Use is subject to license terms.
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif /* !lint */
 #include <sys/asm_linkage.h>
 #include <sys/privregs.h>
 #include <sys/sun4asi.h>
@@ -118,9 +116,7 @@
  * NOT is used for traps that just shouldn't happen.
  * It comes in both single and quadruple flavors.
  */
-#if !defined(lint)
 	.global	trap
-#endif /* !lint */
 #define	NOT			\
 	TT_TRACE(trace_gen)	;\
 	set	trap, %g1	;\
@@ -154,9 +150,7 @@
  * TRAP vectors to the trap() function.
  * It's main use is for user errors.
  */
-#if !defined(lint)
 	.global	trap
-#endif /* !lint */
 #define	TRAP(arg)		\
 	TT_TRACE(trace_gen)	;\
 	set	trap, %g1	;\
@@ -273,8 +267,6 @@
 	clr %o4; clr %o5; clr %o6; clr %o7			;\
 	retry; .align 128
 
-#if !defined(lint)
-
 /*
  * If we get an unresolved tlb miss while in a window handler, the fault
  * handler will resume execution at the last instruction of the window
@@ -584,8 +576,6 @@
 	.empty
 
 
-#endif /* !lint */
-
 /*
  * SPILL_mixed spills either size window, depending on
  * whether %sp is even or odd, to a 32-bit address space.
@@ -725,8 +715,6 @@
 	nop				;\
 	.align	32
 
-#if !defined(lint)
-
 /*
  * ECACHE_ECC error traps at level 0 and level 1
  */
@@ -740,8 +728,6 @@
 	sub	%g0, 1, %g4		;\
 	.align	32
 
-#endif /* !lint */
-
 /*
  * illegal instruction trap
  */
@@ -1087,13 +1073,6 @@
 #endif
 
 
-#if defined(lint)
-
-struct scb	trap_table;
-struct scb	scb;		/* trap_table/scb are the same object */
-
-#else /* lint */
-
 /*
  * =======================================================================
  *		SPARC V9 TRAP TABLE
@@ -2897,4 +2876,3 @@
 	SYSCALL_NOTT(syscall_trap)
 	SET_SIZE(syscall_wrapper)
 
-#endif	/* lint */
--- old/usr/src/uts/sun4v/ml/wbuf.s	Thu Nov 14 19:00:59 2019
+++ new/usr/src/uts/sun4v/ml/wbuf.s	Thu Nov 14 19:00:59 2019
@@ -24,8 +24,6 @@
  * Use is subject to license terms.
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #include <sys/asm_linkage.h>
 #include <sys/machthread.h>
 #include <sys/privregs.h>
@@ -36,7 +34,6 @@
 #include <sys/machtrap.h>
 #include <sys/traptrace.h>
 
-#if !defined(lint)
 #include "assym.h"
 
 	/*
@@ -513,4 +510,3 @@
 	mov	PTL1_BAD_WTRAP, %g1
 	SET_SIZE(fault_32bit_not)
 	SET_SIZE(fault_64bit_not)
-#endif /* !lint */
--- old/usr/src/uts/sun4v/vm/mach_sfmmu_asm.s	Thu Nov 14 19:01:00 2019
+++ new/usr/src/uts/sun4v/vm/mach_sfmmu_asm.s	Thu Nov 14 19:01:00 2019
@@ -28,11 +28,7 @@
  * routines.
  */
 
-#if defined(lint)
-#include <sys/types.h>
-#else	/* lint */
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/machtrap.h>
@@ -54,34 +50,6 @@
  * sfmmu related subroutines
  */
 
-#if defined (lint)
-
-/* ARGSUSED */
-void
-sfmmu_raise_tsb_exception(uint64_t sfmmup, uint64_t rctx)
-{}
-
-int
-sfmmu_getctx_pri()
-{ return(0); }
-
-int
-sfmmu_getctx_sec()
-{ return(0); }
-
-/* ARGSUSED */
-void
-sfmmu_setctx_sec(uint_t ctx)
-{}
-
-/* ARGSUSED */
-void
-sfmmu_load_mmustate(sfmmu_t *sfmmup)
-{
-}
-
-#else	/* lint */
-
 /*
  * Invalidate either the context of a specific victim or any process
  * currently running on this CPU. 
@@ -430,24 +398,6 @@
 
 	SET_SIZE(sfmmu_load_mmustate)
 	
-#endif /* lint */
-
-#if defined(lint)
-
-/* Prefetch "struct tsbe" while walking TSBs */
-/*ARGSUSED*/
-void
-prefetch_tsbe_read(struct tsbe *tsbep)
-{}
-
-/* Prefetch the tsbe that we are about to write */
-/*ARGSUSED*/
-void
-prefetch_tsbe_write(struct tsbe *tsbep)
-{}
-
-#else /* lint */
-
 	ENTRY(prefetch_tsbe_read)
 	retl
 	nop
@@ -457,4 +407,3 @@
 	retl
 	nop
 	SET_SIZE(prefetch_tsbe_write)
-#endif /* lint */
