1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * This file is part of the Chelsio T4 support code.
14 *
15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
20 * release for licensing terms and conditions.
21 */
22
23 #ifndef __CXGBE_ADAPTER_H
24 #define __CXGBE_ADAPTER_H
25
26 #include <sys/ddi.h>
27 #include <sys/mac_provider.h>
28 #include <sys/ethernet.h>
29 #include <sys/queue.h>
30 #include <sys/containerof.h>
31
32 #include "offload.h"
33 #include "firmware/t4fw_interface.h"
34 #include "shared.h"
35
36 struct adapter;
37 typedef struct adapter adapter_t;
38
39 enum {
40 FW_IQ_QSIZE = 256,
41 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
42
43 RX_IQ_QSIZE = 1024,
44 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
45
46 EQ_ESIZE = 64, /* All egres queues use this entry size */
47
48 RX_FL_ESIZE = 64, /* 8 64bit addresses */
49
50 FL_BUF_SIZES = 4,
51
52 CTRL_EQ_QSIZE = 128,
53
54 TX_EQ_QSIZE = 1024,
55 TX_SGL_SEGS = 36,
56 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
57 };
58
59 enum {
60 /* adapter flags */
61 FULL_INIT_DONE = (1 << 0),
62 FW_OK = (1 << 1),
63 INTR_FWD = (1 << 2),
64 INTR_ALLOCATED = (1 << 3),
65 MASTER_PF = (1 << 4),
66
67 CXGBE_BUSY = (1 << 9),
68
69 /* port flags */
70 DOOMED = (1 << 0),
71 PORT_INIT_DONE = (1 << 1),
72 };
73
74 enum {
75 /* Features */
76 CXGBE_HW_LSO = (1 << 0),
77 CXGBE_HW_CSUM = (1 << 1),
78 };
79
80 enum {
81 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */
82 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */
83 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */
84 };
85
86 #define IS_DOOMED(pi) (pi->flags & DOOMED)
87 #define SET_DOOMED(pi) do { pi->flags |= DOOMED; } while (0)
88 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY)
89 #define SET_BUSY(sc) do { sc->flags |= CXGBE_BUSY; } while (0)
90 #define CLR_BUSY(sc) do { sc->flags &= ~CXGBE_BUSY; } while (0)
91
92 struct port_info {
93 PORT_INFO_HDR;
94
95 kmutex_t lock;
96 struct adapter *adapter;
97
98 #ifdef TCP_OFFLOAD_ENABLE
99 void *tdev;
100 #endif
101
102 unsigned int flags;
103
104 uint16_t viid;
105 int16_t xact_addr_filt; /* index of exact MAC address filter */
106 uint16_t rss_size; /* size of VI's RSS table slice */
107 uint16_t ntxq; /* # of tx queues */
108 uint16_t first_txq; /* index of first tx queue */
109 uint16_t nrxq; /* # of rx queues */
110 uint16_t first_rxq; /* index of first rx queue */
111 #ifdef TCP_OFFLOAD_ENABLE
112 uint16_t nofldtxq; /* # of offload tx queues */
113 uint16_t first_ofld_txq; /* index of first offload tx queue */
114 uint16_t nofldrxq; /* # of offload rx queues */
115 uint16_t first_ofld_rxq; /* index of first offload rx queue */
116 #endif
117 uint8_t lport; /* associated offload logical port */
118 int8_t mdio_addr;
119 uint8_t port_type;
120 uint8_t mod_type;
121 uint8_t port_id;
122 uint8_t tx_chan;
123 uint8_t rx_chan;
124 uint8_t instance; /* Associated adapter instance */
125 uint8_t child_inst; /* Associated child instance */
126 uint8_t tmr_idx;
127 int8_t pktc_idx;
128 struct link_config link_cfg;
129 struct port_stats stats;
130 uint32_t features;
131 uint8_t macaddr_cnt;
132 u8 rss_mode;
133 u16 viid_mirror;
134 kstat_t *ksp_config;
135 kstat_t *ksp_info;
136 };
137
138 struct fl_sdesc {
139 struct rxbuf *rxb;
140 };
141
142 struct tx_desc {
143 __be64 flit[8];
144 };
145
146 /* DMA maps used for tx */
147 struct tx_maps {
148 ddi_dma_handle_t *map;
149 uint32_t map_total; /* # of DMA maps */
150 uint32_t map_pidx; /* next map to be used */
151 uint32_t map_cidx; /* reclaimed up to this index */
152 uint32_t map_avail; /* # of available maps */
153 };
154
155 struct tx_sdesc {
156 mblk_t *m;
157 uint32_t txb_used; /* # of bytes of tx copy buffer used */
158 uint16_t hdls_used; /* # of dma handles used */
159 uint16_t desc_used; /* # of hardware descriptors used */
160 };
161
162 enum {
163 /* iq flags */
164 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
165 IQ_INTR = (1 << 1), /* iq takes direct interrupt */
166 IQ_HAS_FL = (1 << 2), /* iq has fl */
167
168 /* iq state */
169 IQS_DISABLED = 0,
170 IQS_BUSY = 1,
171 IQS_IDLE = 2,
172 };
173
174 /*
175 * Ingress Queue: T4 is producer, driver is consumer.
176 */
177 struct sge_iq {
178 unsigned int flags;
179 ddi_dma_handle_t dhdl;
180 ddi_acc_handle_t ahdl;
181
182 volatile uint_t state;
183 __be64 *desc; /* KVA of descriptor ring */
184 uint64_t ba; /* bus address of descriptor ring */
185 const __be64 *cdesc; /* current descriptor */
186 struct adapter *adapter; /* associated adapter */
187 uint8_t gen; /* generation bit */
188 uint8_t intr_params; /* interrupt holdoff parameters */
189 int8_t intr_pktc_idx; /* packet count threshold index */
190 uint8_t intr_next; /* holdoff for next interrupt */
191 uint8_t esize; /* size (bytes) of each entry in the queue */
192 uint16_t qsize; /* size (# of entries) of the queue */
193 uint16_t cidx; /* consumer index */
194 uint16_t pending; /* # of descs processed since last doorbell */
195 uint16_t cntxt_id; /* SGE context id for the iq */
196 uint16_t abs_id; /* absolute SGE id for the iq */
197 kmutex_t lock; /* Rx access lock */
198 uint8_t polling;
199
200 STAILQ_ENTRY(sge_iq) link;
201 };
202
203 enum {
204 EQ_CTRL = 1,
205 EQ_ETH = 2,
206 #ifdef TCP_OFFLOAD_ENABLE
207 EQ_OFLD = 3,
208 #endif
209
210 /* eq flags */
211 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
212 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
213 EQ_DOOMED = (1 << 4), /* about to be destroyed */
214 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
215 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
216 EQ_MTX = (1 << 7), /* mutex has been initialized */
217 EQ_STARTED = (1 << 8), /* started */
218 };
219
220 /* Listed in order of preference. Update t4_sysctls too if you change these */
221 enum {DOORBELL_UDB=0x1 , DOORBELL_WCWR=0x2, DOORBELL_UDBWC=0x4, DOORBELL_KDB=0x8};
222
223 /*
224 * Egress Queue: driver is producer, T4 is consumer.
225 *
226 * Note: A free list is an egress queue (driver produces the buffers and T4
227 * consumes them) but it's special enough to have its own struct (see sge_fl).
228 */
229 struct sge_eq {
230 ddi_dma_handle_t desc_dhdl;
231 ddi_acc_handle_t desc_ahdl;
232 unsigned int flags;
233 kmutex_t lock;
234
235 struct tx_desc *desc; /* KVA of descriptor ring */
236 uint64_t ba; /* bus address of descriptor ring */
237 struct sge_qstat *spg; /* status page, for convenience */
238 int doorbells;
239 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
240 u_int udb_qid; /* relative qid within the doorbell page */
241 uint16_t cap; /* max # of desc, for convenience */
242 uint16_t avail; /* available descriptors, for convenience */
243 uint16_t qsize; /* size (# of entries) of the queue */
244 uint16_t cidx; /* consumer idx (desc idx) */
245 uint16_t pidx; /* producer idx (desc idx) */
246 uint16_t pending; /* # of descriptors used since last doorbell */
247 uint16_t iqid; /* iq that gets egr_update for the eq */
248 uint8_t tx_chan; /* tx channel used by the eq */
249 uint32_t cntxt_id; /* SGE context id for the eq */
250 };
251
252 enum {
253 /* fl flags */
254 FL_MTX = (1 << 0), /* mutex has been initialized */
255 FL_STARVING = (1 << 1), /* on the list of starving fl's */
256 FL_DOOMED = (1 << 2), /* about to be destroyed */
257 };
258
259 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
260 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
261
262 struct sge_fl {
263 unsigned int flags;
264 kmutex_t lock;
265 ddi_dma_handle_t dhdl;
266 ddi_acc_handle_t ahdl;
267
268 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
269 uint64_t ba; /* bus address of descriptor ring */
270 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
271 uint32_t cap; /* max # of buffers, for convenience */
272 uint16_t qsize; /* size (# of entries) of the queue */
273 uint16_t cntxt_id; /* SGE context id for the freelist */
274 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
275 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
276 uint32_t needed; /* # of buffers needed to fill up fl. */
277 uint32_t lowat; /* # of buffers <= this means fl needs help */
278 uint32_t pending; /* # of bufs allocated since last doorbell */
279 uint32_t offset; /* current packet within the larger buffer */
280 uint16_t copy_threshold; /* anything this size or less is copied up */
281
282 uint64_t copied_up; /* # of frames copied into mblk and handed up */
283 uint64_t passed_up; /* # of frames wrapped in mblk and handed up */
284
285 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
286 };
287
288 /* txq: SGE egress queue + miscellaneous items */
289 struct sge_txq {
290 struct sge_eq eq; /* MUST be first */
291
292 struct port_info *port; /* the port this txq belongs to */
293 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
294 mac_ring_handle_t ring_handle;
295
296 /* DMA handles used for tx */
297 ddi_dma_handle_t *tx_dhdl;
298 uint32_t tx_dhdl_total; /* Total # of handles */
299 uint32_t tx_dhdl_pidx; /* next handle to be used */
300 uint32_t tx_dhdl_cidx; /* reclaimed up to this index */
301 uint32_t tx_dhdl_avail; /* # of available handles */
302
303 /* Copy buffers for tx */
304 ddi_dma_handle_t txb_dhdl;
305 ddi_acc_handle_t txb_ahdl;
306 caddr_t txb_va; /* KVA of copy buffers area */
307 uint64_t txb_ba; /* bus address of copy buffers area */
308 uint32_t txb_size; /* total size */
309 uint32_t txb_next; /* offset of next useable area in the buffer */
310 uint32_t txb_avail; /* # of bytes available */
311 uint16_t copy_threshold; /* anything this size or less is copied up */
312
313 uint64_t txpkts; /* # of ethernet packets */
314 uint64_t txbytes; /* # of ethernet bytes */
315 kstat_t *ksp;
316
317 /* stats for common events first */
318
319 uint64_t txcsum; /* # of times hardware assisted with checksum */
320 uint64_t tso_wrs; /* # of IPv4 TSO work requests */
321 uint64_t imm_wrs; /* # of work requests with immediate data */
322 uint64_t sgl_wrs; /* # of work requests with direct SGL */
323 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
324 uint64_t txpkts_wrs; /* # of coalesced tx work requests */
325 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
326 uint64_t txb_used; /* # of tx copy buffers used (64 byte each) */
327 uint64_t hdl_used; /* # of DMA handles used */
328
329 /* stats for not-that-common events */
330
331 uint32_t txb_full; /* txb ran out of space */
332 uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */
333 uint32_t dma_map_failed; /* couldn't obtain DMA mapping */
334 uint32_t qfull; /* out of hardware descriptors */
335 uint32_t qflush; /* # of SGE_EGR_UPDATE notifications for txq */
336 uint32_t pullup_early; /* # of pullups before starting frame's SGL */
337 uint32_t pullup_late; /* # of pullups while building frame's SGL */
338 uint32_t pullup_failed; /* # of failed pullups */
339 };
340
341 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
342 struct sge_rxq {
343 struct sge_iq iq; /* MUST be first */
344 struct sge_fl fl;
345
346 struct port_info *port; /* the port this rxq belongs to */
347 kstat_t *ksp;
348
349 mac_ring_handle_t ring_handle;
350 uint64_t ring_gen_num;
351
352 /* stats for common events first */
353
354 uint64_t rxcsum; /* # of times hardware assisted with checksum */
355 uint64_t rxpkts; /* # of ethernet packets */
356 uint64_t rxbytes; /* # of ethernet bytes */
357
358 /* stats for not-that-common events */
359
360 uint32_t nomem; /* mblk allocation during rx failed */
361 };
362
363 #ifdef TCP_OFFLOAD_ENABLE
364 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
365 struct sge_ofld_rxq {
366 struct sge_iq iq; /* MUST be first */
367 struct sge_fl fl;
368 };
369
370 /*
371 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
372 * and offload tx queues are of this type.
373 */
374 struct sge_wrq {
375 struct sge_eq eq; /* MUST be first */
376
377 struct adapter *adapter;
378
379 /* List of WRs held up due to lack of tx descriptors */
380 struct mblk_pair wr_list;
381
382 /* stats for common events first */
383
384 uint64_t tx_wrs; /* # of tx work requests */
385
386 /* stats for not-that-common events */
387
388 uint32_t no_desc; /* out of hardware descriptors */
389 };
390 #endif
391
392 struct sge {
393 int fl_starve_threshold;
394 int s_qpp;
395
396 int nrxq; /* total rx queues (all ports and the rest) */
397 int ntxq; /* total tx queues (all ports and the rest) */
398 #ifdef TCP_OFFLOAD_ENABLE
399 int nofldrxq; /* total # of TOE rx queues */
400 int nofldtxq; /* total # of TOE tx queues */
401 #endif
402 int niq; /* total ingress queues */
403 int neq; /* total egress queues */
404 int stat_len; /* length of status page at ring end */
405 int pktshift; /* padding between CPL & packet data */
406 int fl_align; /* response queue message alignment */
407
408 struct sge_iq fwq; /* Firmware event queue */
409 #ifdef TCP_OFFLOAD_ENABLE
410 struct sge_wrq mgmtq; /* Management queue (Control queue) */
411 #endif
412 struct sge_txq *txq; /* NIC tx queues */
413 struct sge_rxq *rxq; /* NIC rx queues */
414 #ifdef TCP_OFFLOAD_ENABLE
415 struct sge_wrq *ctrlq; /* Control queues */
416 struct sge_wrq *ofld_txq; /* TOE tx queues */
417 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
418 #endif
419
420 uint16_t iq_start;
421 int eq_start;
422 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
423 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
424
425 /* Device access and DMA attributes for all the descriptor rings */
426 ddi_device_acc_attr_t acc_attr_desc;
427 ddi_dma_attr_t dma_attr_desc;
428
429 /* Device access and DMA attributes for tx buffers */
430 ddi_device_acc_attr_t acc_attr_tx;
431 ddi_dma_attr_t dma_attr_tx;
432
433 /* Device access and DMA attributes for rx buffers are in rxb_params */
434 kmem_cache_t *rxbuf_cache;
435 struct rxbuf_cache_params rxb_params;
436 };
437
438 struct driver_properties {
439 /* There is a driver.conf variable for each of these */
440 int max_ntxq_10g;
441 int max_nrxq_10g;
442 int max_ntxq_1g;
443 int max_nrxq_1g;
444 #ifdef TCP_OFFLOAD_ENABLE
445 int max_nofldtxq_10g;
446 int max_nofldrxq_10g;
447 int max_nofldtxq_1g;
448 int max_nofldrxq_1g;
449 #endif
450 int intr_types;
451 int tmr_idx_10g;
452 int pktc_idx_10g;
453 int tmr_idx_1g;
454 int pktc_idx_1g;
455 int qsize_txq;
456 int qsize_rxq;
457
458 int timer_val[SGE_NTIMERS];
459 int counter_val[SGE_NCOUNTERS];
460
461 int wc;
462
463 int multi_rings;
464 int t4_fw_install;
465 };
466
467 struct rss_header;
468 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
469 mblk_t *);
470 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
471
472 struct adapter {
473 SLIST_ENTRY(adapter) link;
474 dev_info_t *dip;
475 dev_t dev;
476
477 unsigned int pf;
478 unsigned int mbox;
479
480 unsigned int vpd_busy;
481 unsigned int vpd_flag;
482
483 u32 t4_bar0;
484
485 uint_t open; /* character device is open */
486
487 /* PCI config space access handle */
488 ddi_acc_handle_t pci_regh;
489
490 /* MMIO register access handle */
491 ddi_acc_handle_t regh;
492 caddr_t regp;
493 /* BAR1 register access handle */
494 ddi_acc_handle_t reg1h;
495 caddr_t reg1p;
496
497 /* Interrupt information */
498 int intr_type;
499 int intr_count;
500 int intr_cap;
501 uint_t intr_pri;
502 ddi_intr_handle_t *intr_handle;
503
504 struct driver_properties props;
505 kstat_t *ksp;
506 kstat_t *ksp_stat;
507
508 struct sge sge;
509
510 struct port_info *port[MAX_NPORTS];
511 ddi_taskq_t *tq[NCHAN];
512 uint8_t chan_map[NCHAN];
513 uint32_t filter_mode;
514
515 struct l2t_data *l2t; /* L2 table */
516 struct tid_info tids;
517
518 int doorbells;
519 int registered_device_map;
520 int open_device_map;
521 int flags;
522
523 unsigned int cfcsum;
524 struct adapter_params params;
525 struct t4_virt_res vres;
526
527 #ifdef TCP_OFFLOAD_ENABLE
528 struct uld_softc tom;
529 struct tom_tunables tt;
530 #endif
531
532 #ifdef TCP_OFFLOAD_ENABLE
533 int offload_map;
534 #endif
535 uint16_t linkcaps;
536 uint16_t niccaps;
537 uint16_t toecaps;
538 uint16_t rdmacaps;
539 uint16_t iscsicaps;
540 uint16_t fcoecaps;
541
542 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
543 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
544
545 kmutex_t lock;
546 kcondvar_t cv;
547
548 /* Starving free lists */
549 kmutex_t sfl_lock; /* same cache-line as sc_lock? but that's ok */
550 TAILQ_HEAD(, sge_fl) sfl;
551 timeout_id_t sfl_timer;
552 };
553
554 enum {
555 NIC_H = 0,
556 TOM_H,
557 IW_H,
558 ISCSI_H
559 };
560
561 struct memwin {
562 uint32_t base;
563 uint32_t aperture;
564 };
565
566 #define ADAPTER_LOCK(sc) mutex_enter(&(sc)->lock)
567 #define ADAPTER_UNLOCK(sc) mutex_exit(&(sc)->lock)
568 #define ADAPTER_LOCK_ASSERT_OWNED(sc) ASSERT(mutex_owned(&(sc)->lock))
569 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock))
570
571 #define PORT_LOCK(pi) mutex_enter(&(pi)->lock)
572 #define PORT_UNLOCK(pi) mutex_exit(&(pi)->lock)
573 #define PORT_LOCK_ASSERT_OWNED(pi) ASSERT(mutex_owned(&(pi)->lock))
574 #define PORT_LOCK_ASSERT_NOTOWNED(pi) ASSERT(!mutex_owned(&(pi)->lock))
575
576 #define IQ_LOCK(iq) mutex_enter(&(iq)->lock)
577 #define IQ_UNLOCK(iq) mutex_exit(&(iq)->lock)
578 #define IQ_LOCK_ASSERT_OWNED(iq) ASSERT(mutex_owned(&(iq)->lock))
579 #define IQ_LOCK_ASSERT_NOTOWNED(iq) ASSERT(!mutex_owned(&(iq)->lock))
580
581 #define FL_LOCK(fl) mutex_enter(&(fl)->lock)
582 #define FL_UNLOCK(fl) mutex_exit(&(fl)->lock)
583 #define FL_LOCK_ASSERT_OWNED(fl) ASSERT(mutex_owned(&(fl)->lock))
584 #define FL_LOCK_ASSERT_NOTOWNED(fl) ASSERT(!mutex_owned(&(fl)->lock))
585
586 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq)
587 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq)
588 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq)
589 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq)
590
591 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
592 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
593 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
594 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
595
596 #define EQ_LOCK(eq) mutex_enter(&(eq)->lock)
597 #define EQ_UNLOCK(eq) mutex_exit(&(eq)->lock)
598 #define EQ_LOCK_ASSERT_OWNED(eq) ASSERT(mutex_owned(&(eq)->lock))
599 #define EQ_LOCK_ASSERT_NOTOWNED(eq) ASSERT(!mutex_owned(&(eq)->lock))
600
601 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
602 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
603 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
604 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
605
606 #define for_each_txq(pi, iter, txq) \
607 txq = &pi->adapter->sge.txq[pi->first_txq]; \
608 for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
609 #define for_each_rxq(pi, iter, rxq) \
610 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
611 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
612 #define for_each_ofld_txq(pi, iter, ofld_txq) \
613 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \
614 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq)
615 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \
616 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \
617 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq)
618
619 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1)
620
621 /* One for errors, one for firmware events */
622 #define T4_EXTRA_INTR 2
623
624 /* Presently disabling locking around mbox access
625 * We may need to reenable it later
626 */
627 typedef int t4_os_lock_t;
628 static inline void t4_os_lock(t4_os_lock_t *lock)
629 {
630
631 }
632 static inline void t4_os_unlock(t4_os_lock_t *lock)
633 {
634
635 }
636
637 static inline uint32_t
638 t4_read_reg(struct adapter *sc, uint32_t reg)
639 {
640 /* LINTED: E_BAD_PTR_CAST_ALIGN */
641 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg)));
642 }
643
644 static inline void
645 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
646 {
647 /* LINTED: E_BAD_PTR_CAST_ALIGN */
648 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val);
649 }
650
651 static inline void
652 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
653 {
654 *val = pci_config_get8(sc->pci_regh, reg);
655 }
656
657 static inline void
658 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
659 {
660 pci_config_put8(sc->pci_regh, reg, val);
661 }
662
663 static inline void
664 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
665 {
666 *val = pci_config_get16(sc->pci_regh, reg);
667 }
668
669 static inline void
670 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
671 {
672 pci_config_put16(sc->pci_regh, reg, val);
673 }
674
675 static inline void
676 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
677 {
678 *val = pci_config_get32(sc->pci_regh, reg);
679 }
680
681 static inline void
682 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
683 {
684 pci_config_put32(sc->pci_regh, reg, val);
685 }
686
687 static inline uint64_t
688 t4_read_reg64(struct adapter *sc, uint32_t reg)
689 {
690 /* LINTED: E_BAD_PTR_CAST_ALIGN */
691 return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg)));
692 }
693
694 static inline void
695 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
696 {
697 /* LINTED: E_BAD_PTR_CAST_ALIGN */
698 ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val);
699 }
700
701 static inline struct port_info *
702 adap2pinfo(struct adapter *sc, int idx)
703 {
704 return (sc->port[idx]);
705 }
706
707 static inline void
708 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
709 {
710 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL);
711 }
712
713 static inline bool
714 is_10G_port(const struct port_info *pi)
715 {
716 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
717 }
718
719 static inline struct sge_rxq *
720 iq_to_rxq(struct sge_iq *iq)
721 {
722 return (__containerof(iq, struct sge_rxq, iq));
723 }
724
725 static inline bool
726 is_25G_port(const struct port_info *pi)
727 {
728 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
729 }
730
731 static inline bool
732 is_40G_port(const struct port_info *pi)
733 {
734 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
735 }
736
737 static inline bool
738 is_100G_port(const struct port_info *pi)
739 {
740 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
741 }
742
743 static inline bool
744 is_10XG_port(const struct port_info *pi)
745 {
746 return (is_10G_port(pi) || is_40G_port(pi) ||
747 is_25G_port(pi) || is_100G_port(pi));
748 }
749
750 static inline char *
751 print_port_speed(const struct port_info *pi)
752 {
753 if (!pi)
754 return "-";
755
756 if (is_100G_port(pi))
757 return "100G";
758 else if (is_40G_port(pi))
759 return "40G";
760 else if (is_25G_port(pi))
761 return "25G";
762 else if (is_10G_port(pi))
763 return "10G";
764 else
765 return "1G";
766 }
767
768 #ifdef TCP_OFFLOAD_ENABLE
769 int t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0);
770
771 static inline int
772 t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m)
773 {
774 int rc;
775
776 TXQ_LOCK(wrq);
777 rc = t4_wrq_tx_locked(sc, wrq, m);
778 TXQ_UNLOCK(wrq);
779 return (rc);
780 }
781 #endif
782
783 /**
784 * t4_os_pci_read_seeprom - read four bytes of SEEPROM/VPD contents
785 * @adapter: the adapter
786 * @addr: SEEPROM/VPD Address to read
787 * @valp: where to store the value read
788 *
789 * Read a 32-bit value from the given address in the SEEPROM/VPD. The address
790 * must be four-byte aligned. Returns 0 on success, a negative erro number
791 * on failure.
792 */
793 static inline int t4_os_pci_read_seeprom(adapter_t *adapter,
794 int addr, u32 *valp)
795 {
796 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
797 int ret;
798
799 ret = t4_seeprom_read(adapter, addr, valp);
800
801 return ret >= 0 ? 0 : ret;
802 }
803
804 /**
805 * t4_os_pci_write_seeprom - write four bytes of SEEPROM/VPD contents
806 * @adapter: the adapter
807 * @addr: SEEPROM/VPD Address to write
808 * @val: the value write
809 *
810 * Write a 32-bit value to the given address in the SEEPROM/VPD. The address
811 * must be four-byte aligned. Returns 0 on success, a negative erro number
812 * on failure.
813 */
814 static inline int t4_os_pci_write_seeprom(adapter_t *adapter,
815 int addr, u32 val)
816 {
817 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
818 int ret;
819
820 ret = t4_seeprom_write(adapter, addr, val);
821
822 return ret >= 0 ? 0 : ret;
823 }
824
825 static inline int t4_os_pci_set_vpd_size(struct adapter *adapter, size_t len)
826 {
827 return 0;
828 }
829
830 static inline unsigned int t4_use_ldst(struct adapter *adap)
831 {
832 return (adap->flags & FW_OK);
833 }
834 #define t4_os_alloc(_size) kmem_alloc(_size, KM_SLEEP)
835
836 static inline void t4_db_full(struct adapter *adap) {}
837 static inline void t4_db_dropped(struct adapter *adap) {}
838
839 /* t4_nexus.c */
840 int t4_os_find_pci_capability(struct adapter *sc, int cap);
841 void t4_os_portmod_changed(const struct adapter *sc, int idx);
842 int adapter_full_init(struct adapter *sc);
843 int adapter_full_uninit(struct adapter *sc);
844 int port_full_init(struct port_info *pi);
845 int port_full_uninit(struct port_info *pi);
846 void enable_port_queues(struct port_info *pi);
847 void disable_port_queues(struct port_info *pi);
848 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h);
849 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
850 void t4_iterate(void (*func)(int, void *), void *arg);
851
852 /* t4_sge.c */
853 void t4_sge_init(struct adapter *sc);
854 int t4_setup_adapter_queues(struct adapter *sc);
855 int t4_teardown_adapter_queues(struct adapter *sc);
856 int t4_setup_port_queues(struct port_info *pi);
857 int t4_teardown_port_queues(struct port_info *pi);
858 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2);
859 uint_t t4_intr(caddr_t arg1, caddr_t arg2);
860 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2);
861 int t4_mgmt_tx(struct adapter *sc, mblk_t *m);
862 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *);
863 uint32_t position_memwin(struct adapter *, int, uint32_t);
864
865 mblk_t *t4_eth_tx(void *, mblk_t *);
866 mblk_t *t4_mc_tx(void *arg, mblk_t *m);
867 mblk_t *t4_ring_rx(struct sge_rxq *rxq, int poll_bytes);
868 int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count,
869 int flags);
870
871 /* t4_mac.c */
872 void t4_mc_init(struct port_info *pi);
873 void t4_mc_cb_init(struct port_info *);
874 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat);
875 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m);
876 void t4_mac_tx_update(struct port_info *pi, struct sge_txq *txq);
877 int t4_addmac(void *arg, const uint8_t *ucaddr);
878
879 /* t4_ioctl.c */
880 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode);
881
882 struct l2t_data *t4_init_l2t(struct adapter *sc);
883 #endif /* __CXGBE_ADAPTER_H */