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9724 qede needs updates for newer GCC
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--- old/usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dcbx.c
+++ new/usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dcbx.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, v.1, (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://opensource.org/licenses/CDDL-1.0.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2014-2017 Cavium, Inc.
24 24 * The contents of this file are subject to the terms of the Common Development
25 25 * and Distribution License, v.1, (the "License").
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26 26
27 27 * You may not use this file except in compliance with the License.
28 28
29 29 * You can obtain a copy of the License at available
30 30 * at http://opensource.org/licenses/CDDL-1.0
31 31
32 32 * See the License for the specific language governing permissions and
33 33 * limitations under the License.
34 34 */
35 35
36 +/*
37 + * Copyright 2018 Joyent, Inc.
38 + */
39 +
36 40 #include "bcm_osal.h"
37 41 #include "ecore.h"
38 42 #include "ecore_sp_commands.h"
39 43 #include "ecore_dcbx.h"
40 44 #include "ecore_cxt.h"
41 45 #include "ecore_gtt_reg_addr.h"
42 46 #include "ecore_iro.h"
43 47 #ifdef CONFIG_ECORE_ROCE
44 48 #include "ecore_roce.h"
45 49 #endif
46 50 #include "ecore_iov_api.h"
47 51
48 52 #define ECORE_DCBX_MAX_MIB_READ_TRY (100)
49 53 #define ECORE_ETH_TYPE_DEFAULT (0)
50 54 #define ECORE_ETH_TYPE_ROCE (0x8915)
51 55 #define ECORE_UDP_PORT_TYPE_ROCE_V2 (0x12B7)
52 56 #define ECORE_ETH_TYPE_FCOE (0x8906)
53 57 #define ECORE_TCP_PORT_ISCSI (0xCBC)
54 58
55 59 #define ECORE_DCBX_INVALID_PRIORITY 0xFF
56 60
57 61 /* Get Traffic Class from priority traffic class table, 4 bits represent
58 62 * the traffic class corresponding to the priority.
59 63 */
60 64 #define ECORE_DCBX_PRIO2TC(prio_tc_tbl, prio) \
61 65 ((u32)(prio_tc_tbl >> ((7 - prio) * 4)) & 0x7)
62 66
63 67 static bool ecore_dcbx_app_ethtype(u32 app_info_bitmap)
64 68 {
65 69 return !!(ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF) ==
66 70 DCBX_APP_SF_ETHTYPE);
67 71 }
68 72
69 73 static bool ecore_dcbx_ieee_app_ethtype(u32 app_info_bitmap)
70 74 {
71 75 u8 mfw_val = ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
72 76
73 77 /* Old MFW */
74 78 if (mfw_val == DCBX_APP_SF_IEEE_RESERVED)
75 79 return ecore_dcbx_app_ethtype(app_info_bitmap);
76 80
77 81 return !!(mfw_val == DCBX_APP_SF_IEEE_ETHTYPE);
78 82 }
79 83
80 84 static bool ecore_dcbx_app_port(u32 app_info_bitmap)
81 85 {
82 86 return !!(ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF) ==
83 87 DCBX_APP_SF_PORT);
84 88 }
85 89
86 90 static bool ecore_dcbx_ieee_app_port(u32 app_info_bitmap, u8 type)
87 91 {
88 92 u8 mfw_val = ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
89 93
90 94 /* Old MFW */
91 95 if (mfw_val == DCBX_APP_SF_IEEE_RESERVED)
92 96 return ecore_dcbx_app_port(app_info_bitmap);
93 97
94 98 return !!(mfw_val == type || mfw_val == DCBX_APP_SF_IEEE_TCP_UDP_PORT);
95 99 }
96 100
97 101 static bool ecore_dcbx_default_tlv(u32 app_info_bitmap, u16 proto_id, bool ieee)
98 102 {
99 103 bool ethtype;
100 104
101 105 if (ieee)
102 106 ethtype = ecore_dcbx_ieee_app_ethtype(app_info_bitmap);
103 107 else
104 108 ethtype = ecore_dcbx_app_ethtype(app_info_bitmap);
105 109
106 110 return !!(ethtype && (proto_id == ECORE_ETH_TYPE_DEFAULT));
107 111 }
108 112
109 113 static bool ecore_dcbx_iscsi_tlv(u32 app_info_bitmap, u16 proto_id, bool ieee)
110 114 {
111 115 bool port;
112 116
113 117 if (ieee)
114 118 port = ecore_dcbx_ieee_app_port(app_info_bitmap,
115 119 DCBX_APP_SF_IEEE_TCP_PORT);
116 120 else
117 121 port = ecore_dcbx_app_port(app_info_bitmap);
118 122
119 123 return !!(port && (proto_id == ECORE_TCP_PORT_ISCSI));
120 124 }
121 125
122 126 static bool ecore_dcbx_fcoe_tlv(u32 app_info_bitmap, u16 proto_id, bool ieee)
123 127 {
124 128 bool ethtype;
125 129
126 130 if (ieee)
127 131 ethtype = ecore_dcbx_ieee_app_ethtype(app_info_bitmap);
128 132 else
129 133 ethtype = ecore_dcbx_app_ethtype(app_info_bitmap);
130 134
131 135 return !!(ethtype && (proto_id == ECORE_ETH_TYPE_FCOE));
132 136 }
133 137
134 138 static bool ecore_dcbx_roce_tlv(u32 app_info_bitmap, u16 proto_id, bool ieee)
135 139 {
136 140 bool ethtype;
137 141
138 142 if (ieee)
139 143 ethtype = ecore_dcbx_ieee_app_ethtype(app_info_bitmap);
140 144 else
141 145 ethtype = ecore_dcbx_app_ethtype(app_info_bitmap);
142 146
143 147 return !!(ethtype && (proto_id == ECORE_ETH_TYPE_ROCE));
144 148 }
145 149
146 150 static bool ecore_dcbx_roce_v2_tlv(u32 app_info_bitmap, u16 proto_id, bool ieee)
147 151 {
148 152 bool port;
149 153
150 154 if (ieee)
151 155 port = ecore_dcbx_ieee_app_port(app_info_bitmap,
152 156 DCBX_APP_SF_IEEE_UDP_PORT);
153 157 else
154 158 port = ecore_dcbx_app_port(app_info_bitmap);
155 159
156 160 return !!(port && (proto_id == ECORE_UDP_PORT_TYPE_ROCE_V2));
157 161 }
158 162
159 163 static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
160 164 u16 proto_id, bool ieee)
161 165 {
162 166 bool port;
163 167
164 168 if (!p_hwfn->p_dcbx_info->iwarp_port)
165 169 return false;
166 170
167 171 if (ieee)
168 172 port = ecore_dcbx_ieee_app_port(app_info_bitmap,
169 173 DCBX_APP_SF_IEEE_TCP_PORT);
170 174 else
171 175 port = ecore_dcbx_app_port(app_info_bitmap);
172 176
173 177 return !!(port && (proto_id == p_hwfn->p_dcbx_info->iwarp_port));
174 178 }
175 179
176 180 static void
177 181 ecore_dcbx_dp_protocol(struct ecore_hwfn *p_hwfn,
178 182 struct ecore_dcbx_results *p_data)
179 183 {
180 184 enum dcbx_protocol_type id;
181 185 int i;
182 186
183 187 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "DCBX negotiated: %d\n",
184 188 p_data->dcbx_enabled);
185 189
186 190 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) {
187 191 id = ecore_dcbx_app_update[i].id;
188 192
189 193 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
190 194 "%s info: update %d, enable %d, prio %d, tc %d, num_active_tc %d dscp_enable = %d dscp_val = %d\n",
191 195 ecore_dcbx_app_update[i].name, p_data->arr[id].update,
192 196 p_data->arr[id].enable, p_data->arr[id].priority,
193 197 p_data->arr[id].tc, p_hwfn->hw_info.num_active_tc,
194 198 p_data->arr[id].dscp_enable,
195 199 p_data->arr[id].dscp_val);
196 200 }
197 201 }
198 202
199 203 static void
200 204 ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,
201 205 struct ecore_hwfn *p_hwfn,
202 206 bool enable, u8 prio, u8 tc,
203 207 enum dcbx_protocol_type type,
204 208 enum ecore_pci_personality personality)
205 209 {
206 210 struct ecore_dcbx_dscp_params *dscp = &p_hwfn->p_dcbx_info->get.dscp;
207 211
208 212 /* PF update ramrod data */
209 213 p_data->arr[type].enable = enable;
210 214 p_data->arr[type].priority = prio;
211 215 p_data->arr[type].tc = tc;
212 216 p_data->arr[type].dscp_enable = dscp->enabled;
213 217 if (p_data->arr[type].dscp_enable) {
214 218 u8 i;
215 219
216 220 for (i = 0; i < ECORE_DCBX_DSCP_SIZE; i++)
217 221 if (prio == dscp->dscp_pri_map[i]) {
218 222 p_data->arr[type].dscp_val = i;
219 223 break;
220 224 }
221 225 }
222 226
223 227 if (enable && p_data->arr[type].dscp_enable)
224 228 p_data->arr[type].update = UPDATE_DCB_DSCP;
225 229 else if (enable)
226 230 p_data->arr[type].update = UPDATE_DCB;
227 231 else
228 232 p_data->arr[type].update = DONT_UPDATE_DCB_DSCP;
229 233
230 234 /* QM reconf data */
231 235 if (p_hwfn->hw_info.personality == personality)
232 236 p_hwfn->hw_info.offload_tc = tc;
233 237 }
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234 238
235 239 /* Update app protocol data and hw_info fields with the TLV info */
236 240 static void
237 241 ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data,
238 242 struct ecore_hwfn *p_hwfn,
239 243 bool enable, u8 prio, u8 tc,
240 244 enum dcbx_protocol_type type)
241 245 {
242 246 enum ecore_pci_personality personality;
243 247 enum dcbx_protocol_type id;
244 - char *name;
245 248 int i;
246 249
247 250 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) {
248 251 id = ecore_dcbx_app_update[i].id;
249 252
250 253 if (type != id)
251 254 continue;
252 255
253 256 personality = ecore_dcbx_app_update[i].personality;
254 - name = ecore_dcbx_app_update[i].name;
255 257
256 258 ecore_dcbx_set_params(p_data, p_hwfn, enable,
257 259 prio, tc, type, personality);
258 260 }
259 261 }
260 262
261 263 static enum _ecore_status_t
262 264 ecore_dcbx_get_app_priority(u8 pri_bitmap, u8 *priority)
263 265 {
264 266 u32 pri_mask, pri = ECORE_MAX_PFC_PRIORITIES;
265 267 u32 index = ECORE_MAX_PFC_PRIORITIES - 1;
266 268 enum _ecore_status_t rc = ECORE_SUCCESS;
267 269
268 270 /* Bitmap 1 corresponds to priority 0, return priority 0 */
269 271 if (pri_bitmap == 1) {
270 272 *priority = 0;
271 273 return rc;
272 274 }
273 275
274 276 /* Choose the highest priority */
275 277 while ((ECORE_MAX_PFC_PRIORITIES == pri) && index) {
276 278 pri_mask = 1 << index;
277 279 if (pri_bitmap & pri_mask)
278 280 pri = index;
279 281 index--;
280 282 }
281 283
282 284 if (pri < ECORE_MAX_PFC_PRIORITIES)
283 285 *priority = (u8)pri;
284 286 else
285 287 rc = ECORE_INVAL;
286 288
287 289 return rc;
288 290 }
289 291
290 292 static bool
291 293 ecore_dcbx_get_app_protocol_type(struct ecore_hwfn *p_hwfn,
292 294 u32 app_prio_bitmap, u16 id,
293 295 enum dcbx_protocol_type *type, bool ieee)
294 296 {
295 297 if (ecore_dcbx_fcoe_tlv(app_prio_bitmap, id, ieee)) {
296 298 *type = DCBX_PROTOCOL_FCOE;
297 299 } else if (ecore_dcbx_roce_tlv(app_prio_bitmap, id, ieee)) {
298 300 *type = DCBX_PROTOCOL_ROCE;
299 301 } else if (ecore_dcbx_iscsi_tlv(app_prio_bitmap, id, ieee)) {
300 302 *type = DCBX_PROTOCOL_ISCSI;
301 303 } else if (ecore_dcbx_default_tlv(app_prio_bitmap, id, ieee)) {
302 304 *type = DCBX_PROTOCOL_ETH;
303 305 } else if (ecore_dcbx_roce_v2_tlv(app_prio_bitmap, id, ieee)) {
304 306 *type = DCBX_PROTOCOL_ROCE_V2;
305 307 } else if (ecore_dcbx_iwarp_tlv(p_hwfn, app_prio_bitmap, id, ieee)) {
306 308 *type = DCBX_PROTOCOL_IWARP;
307 309 } else {
308 310 *type = DCBX_MAX_PROTOCOL_TYPE;
309 311 DP_ERR(p_hwfn,
310 312 "No action required, App TLV id = 0x%x app_prio_bitmap = 0x%x\n",
311 313 id, app_prio_bitmap);
312 314 return false;
313 315 }
314 316
315 317 return true;
316 318 }
317 319
318 320 /* Parse app TLV's to update TC information in hw_info structure for
319 321 * reconfiguring QM. Get protocol specific data for PF update ramrod command.
320 322 */
321 323 static enum _ecore_status_t
322 324 ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn,
323 325 struct ecore_dcbx_results *p_data,
324 326 struct dcbx_app_priority_entry *p_tbl, u32 pri_tc_tbl,
325 327 int count, u8 dcbx_version)
326 328 {
327 329 enum dcbx_protocol_type type;
328 330 u8 tc, priority_map;
329 331 bool enable, ieee;
330 332 u16 protocol_id;
331 333 u8 priority;
332 334 enum _ecore_status_t rc = ECORE_SUCCESS;
333 335 int i;
334 336
335 337 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
336 338 "Num APP entries = %d pri_tc_tbl = 0x%x dcbx_version = %u\n",
337 339 count, pri_tc_tbl, dcbx_version);
338 340
339 341 ieee = (dcbx_version == DCBX_CONFIG_VERSION_IEEE);
340 342 /* Parse APP TLV */
341 343 for (i = 0; i < count; i++) {
342 344 protocol_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
343 345 DCBX_APP_PROTOCOL_ID);
344 346 priority_map = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
345 347 DCBX_APP_PRI_MAP);
346 348 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Id = 0x%x pri_map = %u\n",
347 349 protocol_id, priority_map);
348 350 rc = ecore_dcbx_get_app_priority(priority_map, &priority);
349 351 if (rc == ECORE_INVAL) {
350 352 DP_ERR(p_hwfn, "Invalid priority\n");
351 353 return ECORE_INVAL;
352 354 }
353 355
354 356 tc = ECORE_DCBX_PRIO2TC(pri_tc_tbl, priority);
355 357 if (ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry,
356 358 protocol_id, &type,
357 359 ieee)) {
358 360 /* ETH always have the enable bit reset, as it gets
359 361 * vlan information per packet. For other protocols,
360 362 * should be set according to the dcbx_enabled
361 363 * indication, but we only got here if there was an
362 364 * app tlv for the protocol, so dcbx must be enabled.
363 365 */
364 366 enable = !(type == DCBX_PROTOCOL_ETH);
365 367
366 368 ecore_dcbx_update_app_info(p_data, p_hwfn, enable,
367 369 priority, tc, type);
368 370 }
369 371 }
370 372
371 373 /* Update ramrod protocol data and hw_info fields
372 374 * with default info when corresponding APP TLV's are not detected.
373 375 * The enabled field has a different logic for ethernet as only for
374 376 * ethernet dcb should disabled by default, as the information arrives
375 377 * from the OS (unless an explicit app tlv was present).
376 378 */
377 379 tc = p_data->arr[DCBX_PROTOCOL_ETH].tc;
378 380 priority = p_data->arr[DCBX_PROTOCOL_ETH].priority;
379 381 for (type = 0; type < DCBX_MAX_PROTOCOL_TYPE; type++) {
380 382 if (p_data->arr[type].update)
381 383 continue;
382 384
383 385 enable = (type == DCBX_PROTOCOL_ETH) ? false : !!dcbx_version;
384 386 ecore_dcbx_update_app_info(p_data, p_hwfn, enable,
385 387 priority, tc, type);
386 388 }
387 389
388 390 return ECORE_SUCCESS;
389 391 }
390 392
391 393 /* Parse app TLV's to update TC information in hw_info structure for
392 394 * reconfiguring QM. Get protocol specific data for PF update ramrod command.
393 395 */
394 396 static enum _ecore_status_t
395 397 ecore_dcbx_process_mib_info(struct ecore_hwfn *p_hwfn)
396 398 {
397 399 struct dcbx_app_priority_feature *p_app;
398 400 enum _ecore_status_t rc = ECORE_SUCCESS;
399 401 struct ecore_dcbx_results data = { 0 };
400 402 struct dcbx_app_priority_entry *p_tbl;
401 403 struct dcbx_ets_feature *p_ets;
402 404 struct ecore_hw_info *p_info;
403 405 u32 pri_tc_tbl, flags;
404 406 u8 dcbx_version;
405 407 int num_entries;
406 408
407 409 flags = p_hwfn->p_dcbx_info->operational.flags;
408 410 dcbx_version = ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION);
409 411
410 412 p_app = &p_hwfn->p_dcbx_info->operational.features.app;
411 413 p_tbl = p_app->app_pri_tbl;
412 414
413 415 p_ets = &p_hwfn->p_dcbx_info->operational.features.ets;
414 416 pri_tc_tbl = p_ets->pri_tc_tbl[0];
415 417
416 418 p_info = &p_hwfn->hw_info;
417 419 num_entries = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_NUM_ENTRIES);
418 420
419 421 rc = ecore_dcbx_process_tlv(p_hwfn, &data, p_tbl, pri_tc_tbl,
420 422 num_entries, dcbx_version);
421 423 if (rc != ECORE_SUCCESS)
422 424 return rc;
423 425
424 426 p_info->num_active_tc = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS);
425 427 p_hwfn->qm_info.ooo_tc = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_OOO_TC);
426 428 data.pf_id = p_hwfn->rel_pf_id;
427 429 data.dcbx_enabled = !!dcbx_version;
428 430
429 431 ecore_dcbx_dp_protocol(p_hwfn, &data);
430 432
431 433 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->results, &data,
432 434 sizeof(struct ecore_dcbx_results));
433 435
434 436 return ECORE_SUCCESS;
435 437 }
436 438
437 439 static enum _ecore_status_t
438 440 ecore_dcbx_copy_mib(struct ecore_hwfn *p_hwfn,
439 441 struct ecore_ptt *p_ptt,
440 442 struct ecore_dcbx_mib_meta_data *p_data,
441 443 enum ecore_mib_read_type type)
442 444 {
443 445 enum _ecore_status_t rc = ECORE_SUCCESS;
444 446 u32 prefix_seq_num, suffix_seq_num;
445 447 int read_count = 0;
446 448
447 449 /* The data is considered to be valid only if both sequence numbers are
448 450 * the same.
449 451 */
450 452 do {
451 453 if (type == ECORE_DCBX_REMOTE_LLDP_MIB) {
452 454 ecore_memcpy_from(p_hwfn, p_ptt, p_data->lldp_remote,
453 455 p_data->addr, p_data->size);
454 456 prefix_seq_num = p_data->lldp_remote->prefix_seq_num;
455 457 suffix_seq_num = p_data->lldp_remote->suffix_seq_num;
456 458 } else {
457 459 ecore_memcpy_from(p_hwfn, p_ptt, p_data->mib,
458 460 p_data->addr, p_data->size);
459 461 prefix_seq_num = p_data->mib->prefix_seq_num;
460 462 suffix_seq_num = p_data->mib->suffix_seq_num;
461 463 }
462 464 read_count++;
463 465
464 466 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
465 467 "mib type = %d, try count = %d prefix seq num = %d suffix seq num = %d\n",
466 468 type, read_count, prefix_seq_num, suffix_seq_num);
467 469 } while ((prefix_seq_num != suffix_seq_num) &&
468 470 (read_count < ECORE_DCBX_MAX_MIB_READ_TRY));
469 471
470 472 if (read_count >= ECORE_DCBX_MAX_MIB_READ_TRY) {
471 473 DP_ERR(p_hwfn,
472 474 "MIB read err, mib type = %d, try count = %d prefix seq num = %d suffix seq num = %d\n",
473 475 type, read_count, prefix_seq_num, suffix_seq_num);
474 476 rc = ECORE_IO;
475 477 }
476 478
477 479 return rc;
478 480 }
479 481
480 482 static void
481 483 ecore_dcbx_get_priority_info(struct ecore_hwfn *p_hwfn,
482 484 struct ecore_dcbx_app_prio *p_prio,
483 485 struct ecore_dcbx_results *p_results)
484 486 {
485 487 u8 val;
486 488
487 489 p_prio->roce = ECORE_DCBX_INVALID_PRIORITY;
488 490 p_prio->roce_v2 = ECORE_DCBX_INVALID_PRIORITY;
489 491 p_prio->iscsi = ECORE_DCBX_INVALID_PRIORITY;
490 492 p_prio->fcoe = ECORE_DCBX_INVALID_PRIORITY;
491 493
492 494 if (p_results->arr[DCBX_PROTOCOL_ROCE].update &&
493 495 p_results->arr[DCBX_PROTOCOL_ROCE].enable)
494 496 p_prio->roce = p_results->arr[DCBX_PROTOCOL_ROCE].priority;
495 497
496 498 if (p_results->arr[DCBX_PROTOCOL_ROCE_V2].update &&
497 499 p_results->arr[DCBX_PROTOCOL_ROCE_V2].enable) {
498 500 val = p_results->arr[DCBX_PROTOCOL_ROCE_V2].priority;
499 501 p_prio->roce_v2 = val;
500 502 }
501 503
502 504 if (p_results->arr[DCBX_PROTOCOL_ISCSI].update &&
503 505 p_results->arr[DCBX_PROTOCOL_ISCSI].enable)
504 506 p_prio->iscsi = p_results->arr[DCBX_PROTOCOL_ISCSI].priority;
505 507
506 508 if (p_results->arr[DCBX_PROTOCOL_FCOE].update &&
507 509 p_results->arr[DCBX_PROTOCOL_FCOE].enable)
508 510 p_prio->fcoe = p_results->arr[DCBX_PROTOCOL_FCOE].priority;
509 511
510 512 if (p_results->arr[DCBX_PROTOCOL_ETH].update &&
511 513 p_results->arr[DCBX_PROTOCOL_ETH].enable)
512 514 p_prio->eth = p_results->arr[DCBX_PROTOCOL_ETH].priority;
513 515
514 516 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
515 517 "Priorities: iscsi %d, roce %d, roce v2 %d, fcoe %d, eth %d\n",
516 518 p_prio->iscsi, p_prio->roce, p_prio->roce_v2, p_prio->fcoe,
517 519 p_prio->eth);
518 520 }
519 521
520 522 static void
521 523 ecore_dcbx_get_app_data(struct ecore_hwfn *p_hwfn,
522 524 struct dcbx_app_priority_feature *p_app,
523 525 struct dcbx_app_priority_entry *p_tbl,
524 526 struct ecore_dcbx_params *p_params, bool ieee)
525 527 {
526 528 struct ecore_app_entry *entry;
527 529 u8 pri_map;
528 530 int i;
529 531
530 532 p_params->app_willing = ECORE_MFW_GET_FIELD(p_app->flags,
531 533 DCBX_APP_WILLING);
532 534 p_params->app_valid = ECORE_MFW_GET_FIELD(p_app->flags,
533 535 DCBX_APP_ENABLED);
534 536 p_params->app_error = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_ERROR);
535 537 p_params->num_app_entries = ECORE_MFW_GET_FIELD(p_app->flags,
536 538 DCBX_APP_NUM_ENTRIES);
537 539 for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
538 540 entry = &p_params->app_entry[i];
539 541 if (ieee) {
540 542 u8 sf_ieee;
541 543 u32 val;
542 544
543 545 sf_ieee = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
544 546 DCBX_APP_SF_IEEE);
545 547 switch (sf_ieee) {
546 548 case DCBX_APP_SF_IEEE_RESERVED:
547 549 /* Old MFW */
548 550 val = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
549 551 DCBX_APP_SF);
550 552 entry->sf_ieee = val ?
551 553 ECORE_DCBX_SF_IEEE_TCP_UDP_PORT :
552 554 ECORE_DCBX_SF_IEEE_ETHTYPE;
553 555 break;
554 556 case DCBX_APP_SF_IEEE_ETHTYPE:
555 557 entry->sf_ieee = ECORE_DCBX_SF_IEEE_ETHTYPE;
556 558 break;
557 559 case DCBX_APP_SF_IEEE_TCP_PORT:
558 560 entry->sf_ieee = ECORE_DCBX_SF_IEEE_TCP_PORT;
559 561 break;
560 562 case DCBX_APP_SF_IEEE_UDP_PORT:
561 563 entry->sf_ieee = ECORE_DCBX_SF_IEEE_UDP_PORT;
562 564 break;
563 565 case DCBX_APP_SF_IEEE_TCP_UDP_PORT:
564 566 entry->sf_ieee = ECORE_DCBX_SF_IEEE_TCP_UDP_PORT;
565 567 break;
566 568 }
567 569 } else {
568 570 entry->ethtype = !(ECORE_MFW_GET_FIELD(p_tbl[i].entry,
569 571 DCBX_APP_SF));
570 572 }
571 573
572 574 pri_map = ECORE_MFW_GET_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP);
573 575 ecore_dcbx_get_app_priority(pri_map, &entry->prio);
574 576 entry->proto_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
575 577 DCBX_APP_PROTOCOL_ID);
576 578 ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry,
577 579 entry->proto_id,
578 580 &entry->proto_type, ieee);
579 581 }
580 582
581 583 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
582 584 "APP params: willing %d, valid %d error = %d\n",
583 585 p_params->app_willing, p_params->app_valid,
584 586 p_params->app_error);
585 587 }
586 588
587 589 static void
588 590 ecore_dcbx_get_pfc_data(struct ecore_hwfn *p_hwfn,
589 591 u32 pfc, struct ecore_dcbx_params *p_params)
590 592 {
591 593 u8 pfc_map;
592 594
593 595 p_params->pfc.willing = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_WILLING);
594 596 p_params->pfc.max_tc = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_CAPS);
595 597 p_params->pfc.enabled = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_ENABLED);
596 598 pfc_map = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_PRI_EN_BITMAP);
597 599 p_params->pfc.prio[0] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_0);
598 600 p_params->pfc.prio[1] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_1);
599 601 p_params->pfc.prio[2] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_2);
600 602 p_params->pfc.prio[3] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_3);
601 603 p_params->pfc.prio[4] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_4);
602 604 p_params->pfc.prio[5] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_5);
603 605 p_params->pfc.prio[6] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_6);
604 606 p_params->pfc.prio[7] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_7);
605 607
606 608 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
607 609 "PFC params: willing %d, pfc_bitmap %u max_tc = %u enabled = %d\n",
608 610 p_params->pfc.willing, pfc_map, p_params->pfc.max_tc,
609 611 p_params->pfc.enabled);
610 612 }
611 613
612 614 static void
613 615 ecore_dcbx_get_ets_data(struct ecore_hwfn *p_hwfn,
614 616 struct dcbx_ets_feature *p_ets,
615 617 struct ecore_dcbx_params *p_params)
616 618 {
617 619 u32 bw_map[2], tsa_map[2], pri_map;
618 620 int i;
619 621
620 622 p_params->ets_willing = ECORE_MFW_GET_FIELD(p_ets->flags,
621 623 DCBX_ETS_WILLING);
622 624 p_params->ets_enabled = ECORE_MFW_GET_FIELD(p_ets->flags,
623 625 DCBX_ETS_ENABLED);
624 626 p_params->ets_cbs = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_ETS_CBS);
625 627 p_params->max_ets_tc = ECORE_MFW_GET_FIELD(p_ets->flags,
626 628 DCBX_ETS_MAX_TCS);
627 629 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
628 630 "ETS params: willing %d, enabled = %d ets_cbs %d pri_tc_tbl_0 %x max_ets_tc %d\n",
629 631 p_params->ets_willing, p_params->ets_enabled,
630 632 p_params->ets_cbs, p_ets->pri_tc_tbl[0],
631 633 p_params->max_ets_tc);
632 634 if (p_params->ets_enabled && !p_params->max_ets_tc)
633 635 {
634 636 p_params->max_ets_tc = ECORE_MAX_PFC_PRIORITIES;
635 637 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
636 638 "ETS params: max_ets_tc is forced to %d\n",
637 639 p_params->max_ets_tc);
638 640 }
639 641 /* 8 bit tsa and bw data corresponding to each of the 8 TC's are
640 642 * encoded in a type u32 array of size 2.
641 643 */
642 644 bw_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[0]);
643 645 bw_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[1]);
644 646 tsa_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[0]);
645 647 tsa_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[1]);
646 648 pri_map = p_ets->pri_tc_tbl[0];
647 649 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) {
648 650 p_params->ets_tc_bw_tbl[i] = ((u8 *)bw_map)[i];
649 651 p_params->ets_tc_tsa_tbl[i] = ((u8 *)tsa_map)[i];
650 652 p_params->ets_pri_tc_tbl[i] = ECORE_DCBX_PRIO2TC(pri_map, i);
651 653 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
652 654 "elem %d bw_tbl %x tsa_tbl %x\n",
653 655 i, p_params->ets_tc_bw_tbl[i],
654 656 p_params->ets_tc_tsa_tbl[i]);
655 657 }
656 658 }
657 659
658 660 static void
659 661 ecore_dcbx_get_common_params(struct ecore_hwfn *p_hwfn,
660 662 struct dcbx_app_priority_feature *p_app,
661 663 struct dcbx_app_priority_entry *p_tbl,
662 664 struct dcbx_ets_feature *p_ets,
663 665 u32 pfc, struct ecore_dcbx_params *p_params,
664 666 bool ieee)
665 667 {
666 668 ecore_dcbx_get_app_data(p_hwfn, p_app, p_tbl, p_params, ieee);
667 669 ecore_dcbx_get_ets_data(p_hwfn, p_ets, p_params);
668 670 ecore_dcbx_get_pfc_data(p_hwfn, pfc, p_params);
669 671 }
670 672
671 673 static void
672 674 ecore_dcbx_get_local_params(struct ecore_hwfn *p_hwfn,
673 675 struct ecore_ptt *p_ptt,
674 676 struct ecore_dcbx_get *params)
675 677 {
676 678 struct dcbx_features *p_feat;
677 679
678 680 p_feat = &p_hwfn->p_dcbx_info->local_admin.features;
679 681 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app,
680 682 p_feat->app.app_pri_tbl, &p_feat->ets,
681 683 p_feat->pfc, ¶ms->local.params, false);
682 684 params->local.valid = true;
683 685 }
684 686
685 687 static void
686 688 ecore_dcbx_get_remote_params(struct ecore_hwfn *p_hwfn,
687 689 struct ecore_ptt *p_ptt,
688 690 struct ecore_dcbx_get *params)
689 691 {
690 692 struct dcbx_features *p_feat;
691 693
692 694 p_feat = &p_hwfn->p_dcbx_info->remote.features;
693 695 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app,
694 696 p_feat->app.app_pri_tbl, &p_feat->ets,
695 697 p_feat->pfc, ¶ms->remote.params,
696 698 false);
697 699 params->remote.valid = true;
698 700 }
699 701
700 702 static enum _ecore_status_t
701 703 ecore_dcbx_get_operational_params(struct ecore_hwfn *p_hwfn,
702 704 struct ecore_ptt *p_ptt,
703 705 struct ecore_dcbx_get *params)
704 706 {
705 707 struct ecore_dcbx_operational_params *p_operational;
706 708 struct ecore_dcbx_results *p_results;
707 709 struct dcbx_features *p_feat;
708 710 bool enabled, err;
709 711 u32 flags;
710 712 bool val;
711 713
712 714 flags = p_hwfn->p_dcbx_info->operational.flags;
713 715
714 716 /* If DCBx version is non zero, then negotiation
715 717 * was successfuly performed
716 718 */
717 719 p_operational = ¶ms->operational;
718 720 enabled = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) !=
719 721 DCBX_CONFIG_VERSION_DISABLED);
720 722 if (!enabled) {
721 723 p_operational->enabled = enabled;
722 724 p_operational->valid = false;
723 725 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Dcbx is disabled\n");
724 726 return ECORE_INVAL;
725 727 }
726 728
727 729 p_feat = &p_hwfn->p_dcbx_info->operational.features;
728 730 p_results = &p_hwfn->p_dcbx_info->results;
729 731
730 732 val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
731 733 DCBX_CONFIG_VERSION_IEEE);
732 734 p_operational->ieee = val;
733 735
734 736 val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
735 737 DCBX_CONFIG_VERSION_CEE);
736 738 p_operational->cee = val;
737 739
738 740 val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
739 741 DCBX_CONFIG_VERSION_STATIC);
740 742 p_operational->local = val;
741 743
742 744 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
743 745 "Version support: ieee %d, cee %d, static %d\n",
744 746 p_operational->ieee, p_operational->cee,
745 747 p_operational->local);
746 748
747 749 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app,
748 750 p_feat->app.app_pri_tbl, &p_feat->ets,
749 751 p_feat->pfc, ¶ms->operational.params,
750 752 p_operational->ieee);
751 753 ecore_dcbx_get_priority_info(p_hwfn, &p_operational->app_prio,
752 754 p_results);
753 755 err = ECORE_MFW_GET_FIELD(p_feat->app.flags, DCBX_APP_ERROR);
754 756 p_operational->err = err;
755 757 p_operational->enabled = enabled;
756 758 p_operational->valid = true;
757 759
758 760 return ECORE_SUCCESS;
759 761 }
760 762
761 763 static void
762 764 ecore_dcbx_get_dscp_params(struct ecore_hwfn *p_hwfn,
763 765 struct ecore_ptt *p_ptt,
764 766 struct ecore_dcbx_get *params)
765 767 {
766 768 struct ecore_dcbx_dscp_params *p_dscp;
767 769 struct dcb_dscp_map *p_dscp_map;
768 770 int i, j, entry;
769 771 u32 pri_map;
770 772
771 773 p_dscp = ¶ms->dscp;
772 774 p_dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
773 775 p_dscp->enabled = ECORE_MFW_GET_FIELD(p_dscp_map->flags,
774 776 DCB_DSCP_ENABLE);
775 777 /* MFW encodes 64 dscp entries into 8 element array of u32 entries,
776 778 * where each entry holds the 4bit priority map for 8 dscp entries.
777 779 */
778 780 for (i = 0, entry = 0; i < ECORE_DCBX_DSCP_SIZE / 8; i++) {
779 781 pri_map = OSAL_BE32_TO_CPU(p_dscp_map->dscp_pri_map[i]);
780 782 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "elem %d pri_map 0x%x\n",
781 783 entry, pri_map);
782 784 for (j = 0; j < ECORE_DCBX_DSCP_SIZE / 8; j++, entry++)
783 785 p_dscp->dscp_pri_map[entry] = (u32)(pri_map >>
784 786 (j * 4)) & 0xf;
785 787 }
786 788 }
787 789
788 790 static void
789 791 ecore_dcbx_get_local_lldp_params(struct ecore_hwfn *p_hwfn,
790 792 struct ecore_ptt *p_ptt,
791 793 struct ecore_dcbx_get *params)
792 794 {
793 795 struct lldp_config_params_s *p_local;
794 796
795 797 p_local = &p_hwfn->p_dcbx_info->lldp_local[LLDP_NEAREST_BRIDGE];
796 798
797 799 OSAL_MEMCPY(params->lldp_local.local_chassis_id,
798 800 p_local->local_chassis_id,
799 801 OSAL_ARRAY_SIZE(p_local->local_chassis_id));
800 802 OSAL_MEMCPY(params->lldp_local.local_port_id, p_local->local_port_id,
801 803 OSAL_ARRAY_SIZE(p_local->local_port_id));
802 804 }
803 805
804 806 static void
805 807 ecore_dcbx_get_remote_lldp_params(struct ecore_hwfn *p_hwfn,
806 808 struct ecore_ptt *p_ptt,
807 809 struct ecore_dcbx_get *params)
808 810 {
809 811 struct lldp_status_params_s *p_remote;
810 812
811 813 p_remote = &p_hwfn->p_dcbx_info->lldp_remote[LLDP_NEAREST_BRIDGE];
812 814
813 815 OSAL_MEMCPY(params->lldp_remote.peer_chassis_id,
814 816 p_remote->peer_chassis_id,
815 817 OSAL_ARRAY_SIZE(p_remote->peer_chassis_id));
816 818 OSAL_MEMCPY(params->lldp_remote.peer_port_id, p_remote->peer_port_id,
817 819 OSAL_ARRAY_SIZE(p_remote->peer_port_id));
818 820 }
819 821
820 822 static enum _ecore_status_t
821 823 ecore_dcbx_get_params(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
822 824 struct ecore_dcbx_get *p_params,
823 825 enum ecore_mib_read_type type)
824 826 {
825 827 enum _ecore_status_t rc = ECORE_SUCCESS;
826 828
827 829 switch (type) {
828 830 case ECORE_DCBX_REMOTE_MIB:
829 831 ecore_dcbx_get_remote_params(p_hwfn, p_ptt, p_params);
830 832 break;
831 833 case ECORE_DCBX_LOCAL_MIB:
832 834 ecore_dcbx_get_local_params(p_hwfn, p_ptt, p_params);
833 835 break;
834 836 case ECORE_DCBX_OPERATIONAL_MIB:
835 837 ecore_dcbx_get_operational_params(p_hwfn, p_ptt, p_params);
836 838 break;
837 839 case ECORE_DCBX_REMOTE_LLDP_MIB:
838 840 ecore_dcbx_get_remote_lldp_params(p_hwfn, p_ptt, p_params);
839 841 break;
840 842 case ECORE_DCBX_LOCAL_LLDP_MIB:
841 843 ecore_dcbx_get_local_lldp_params(p_hwfn, p_ptt, p_params);
842 844 break;
843 845 default:
844 846 DP_ERR(p_hwfn, "MIB read err, unknown mib type %d\n", type);
845 847 return ECORE_INVAL;
846 848 }
847 849
848 850 return rc;
849 851 }
850 852
851 853 static enum _ecore_status_t
852 854 ecore_dcbx_read_local_lldp_mib(struct ecore_hwfn *p_hwfn,
853 855 struct ecore_ptt *p_ptt)
854 856 {
855 857 struct ecore_dcbx_mib_meta_data data;
856 858 enum _ecore_status_t rc = ECORE_SUCCESS;
857 859
858 860 OSAL_MEM_ZERO(&data, sizeof(data));
859 861 data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port,
860 862 lldp_config_params);
861 863 data.lldp_local = p_hwfn->p_dcbx_info->lldp_local;
862 864 data.size = sizeof(struct lldp_config_params_s);
863 865 ecore_memcpy_from(p_hwfn, p_ptt, data.lldp_local, data.addr, data.size);
864 866
865 867 return rc;
866 868 }
867 869
868 870 static enum _ecore_status_t
869 871 ecore_dcbx_read_remote_lldp_mib(struct ecore_hwfn *p_hwfn,
870 872 struct ecore_ptt *p_ptt,
871 873 enum ecore_mib_read_type type)
872 874 {
873 875 struct ecore_dcbx_mib_meta_data data;
874 876 enum _ecore_status_t rc = ECORE_SUCCESS;
875 877
876 878 OSAL_MEM_ZERO(&data, sizeof(data));
877 879 data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port,
878 880 lldp_status_params);
879 881 data.lldp_remote = p_hwfn->p_dcbx_info->lldp_remote;
880 882 data.size = sizeof(struct lldp_status_params_s);
881 883 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);
882 884
883 885 return rc;
884 886 }
885 887
886 888 static enum _ecore_status_t
887 889 ecore_dcbx_read_operational_mib(struct ecore_hwfn *p_hwfn,
888 890 struct ecore_ptt *p_ptt,
889 891 enum ecore_mib_read_type type)
890 892 {
891 893 struct ecore_dcbx_mib_meta_data data;
892 894 enum _ecore_status_t rc = ECORE_SUCCESS;
893 895
894 896 OSAL_MEM_ZERO(&data, sizeof(data));
895 897 data.addr = p_hwfn->mcp_info->port_addr +
896 898 offsetof(struct public_port, operational_dcbx_mib);
897 899 data.mib = &p_hwfn->p_dcbx_info->operational;
898 900 data.size = sizeof(struct dcbx_mib);
899 901 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);
900 902
901 903 return rc;
902 904 }
903 905
904 906 static enum _ecore_status_t
905 907 ecore_dcbx_read_remote_mib(struct ecore_hwfn *p_hwfn,
906 908 struct ecore_ptt *p_ptt,
907 909 enum ecore_mib_read_type type)
908 910 {
909 911 struct ecore_dcbx_mib_meta_data data;
910 912 enum _ecore_status_t rc = ECORE_SUCCESS;
911 913
912 914 OSAL_MEM_ZERO(&data, sizeof(data));
913 915 data.addr = p_hwfn->mcp_info->port_addr +
914 916 offsetof(struct public_port, remote_dcbx_mib);
915 917 data.mib = &p_hwfn->p_dcbx_info->remote;
916 918 data.size = sizeof(struct dcbx_mib);
917 919 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);
918 920
919 921 return rc;
920 922 }
921 923
922 924 static enum _ecore_status_t
923 925 ecore_dcbx_read_local_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
924 926 {
925 927 struct ecore_dcbx_mib_meta_data data;
926 928 enum _ecore_status_t rc = ECORE_SUCCESS;
927 929
928 930 OSAL_MEM_ZERO(&data, sizeof(data));
929 931 data.addr = p_hwfn->mcp_info->port_addr +
930 932 offsetof(struct public_port, local_admin_dcbx_mib);
931 933 data.local_admin = &p_hwfn->p_dcbx_info->local_admin;
932 934 data.size = sizeof(struct dcbx_local_params);
933 935 ecore_memcpy_from(p_hwfn, p_ptt, data.local_admin,
934 936 data.addr, data.size);
935 937
936 938 return rc;
937 939 }
938 940
939 941 static void
940 942 ecore_dcbx_read_dscp_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
941 943 {
942 944 struct ecore_dcbx_mib_meta_data data;
943 945
944 946 data.addr = p_hwfn->mcp_info->port_addr +
945 947 offsetof(struct public_port, dcb_dscp_map);
946 948 data.dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
947 949 data.size = sizeof(struct dcb_dscp_map);
948 950 ecore_memcpy_from(p_hwfn, p_ptt, data.dscp_map, data.addr, data.size);
949 951 }
950 952
951 953 static enum _ecore_status_t ecore_dcbx_read_mib(struct ecore_hwfn *p_hwfn,
952 954 struct ecore_ptt *p_ptt,
953 955 enum ecore_mib_read_type type)
954 956 {
955 957 enum _ecore_status_t rc = ECORE_INVAL;
956 958
957 959 switch (type) {
958 960 case ECORE_DCBX_OPERATIONAL_MIB:
959 961 ecore_dcbx_read_dscp_mib(p_hwfn, p_ptt);
960 962 rc = ecore_dcbx_read_operational_mib(p_hwfn, p_ptt, type);
961 963 break;
962 964 case ECORE_DCBX_REMOTE_MIB:
963 965 rc = ecore_dcbx_read_remote_mib(p_hwfn, p_ptt, type);
964 966 break;
965 967 case ECORE_DCBX_LOCAL_MIB:
966 968 rc = ecore_dcbx_read_local_mib(p_hwfn, p_ptt);
967 969 break;
968 970 case ECORE_DCBX_REMOTE_LLDP_MIB:
969 971 rc = ecore_dcbx_read_remote_lldp_mib(p_hwfn, p_ptt, type);
970 972 break;
971 973 case ECORE_DCBX_LOCAL_LLDP_MIB:
972 974 rc = ecore_dcbx_read_local_lldp_mib(p_hwfn, p_ptt);
973 975 break;
974 976 default:
975 977 DP_ERR(p_hwfn, "MIB read err, unknown mib type %d\n", type);
976 978 }
977 979
978 980 return rc;
979 981 }
980 982
981 983 /*
982 984 * Read updated MIB.
983 985 * Reconfigure QM and invoke PF update ramrod command if operational MIB
984 986 * change is detected.
985 987 */
986 988 enum _ecore_status_t
987 989 ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
988 990 enum ecore_mib_read_type type)
989 991 {
990 992 enum _ecore_status_t rc = ECORE_SUCCESS;
991 993
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992 994 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);
993 995 if (rc)
994 996 return rc;
995 997
996 998 if (type == ECORE_DCBX_OPERATIONAL_MIB) {
997 999 ecore_dcbx_get_dscp_params(p_hwfn, p_ptt,
998 1000 &p_hwfn->p_dcbx_info->get);
999 1001
1000 1002 rc = ecore_dcbx_process_mib_info(p_hwfn);
1001 1003 if (!rc) {
1002 - bool enabled;
1004 + bool enabled __unused;
1003 1005
1004 1006 /* reconfigure tcs of QM queues according
1005 1007 * to negotiation results
1006 1008 */
1007 1009 ecore_qm_reconf(p_hwfn, p_ptt);
1008 1010
1009 1011 /* update storm FW with negotiation results */
1010 1012 ecore_sp_pf_update_dcbx(p_hwfn);
1011 1013
1012 1014 /* set eagle enigne 1 flow control workaround
1013 1015 * according to negotiation results
1014 1016 */
1015 1017 enabled = p_hwfn->p_dcbx_info->results.dcbx_enabled;
1016 1018
1017 1019 #ifdef CONFIG_ECORE_ROCE
1018 1020 /* for roce PFs, we may want to enable/disable DPM
1019 1021 * when DCBx change occurs
1020 1022 */
1021 1023 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn))
1022 1024 ecore_roce_dpm_dcbx(p_hwfn, p_ptt);
1023 1025 #endif
1024 1026 }
1025 1027 }
1026 1028
1027 1029 ecore_dcbx_get_params(p_hwfn, p_ptt, &p_hwfn->p_dcbx_info->get, type);
1028 1030
1029 1031 if (type == ECORE_DCBX_OPERATIONAL_MIB) {
1030 1032 struct ecore_dcbx_results *p_data;
1031 1033 u16 val;
1032 1034
1033 1035 /* Update the DSCP to TC mapping bit if required */
1034 1036 if (p_hwfn->p_dcbx_info->dscp_nig_update) {
1035 1037 ecore_wr(p_hwfn, p_ptt, NIG_REG_DSCP_TO_TC_MAP_ENABLE,
1036 1038 0x1);
1037 1039 p_hwfn->p_dcbx_info->dscp_nig_update = false;
1038 1040 }
1039 1041
1040 1042 /* Configure in NIG which protocols support EDPM and should
1041 1043 * honor PFC.
1042 1044 */
1043 1045 p_data = &p_hwfn->p_dcbx_info->results;
1044 1046 val = (0x1 << p_data->arr[DCBX_PROTOCOL_ROCE].tc) |
1045 1047 (0x1 << p_data->arr[DCBX_PROTOCOL_ROCE_V2].tc);
1046 1048 val <<= NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT;
1047 1049 val |= NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN;
1048 1050 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_EDPM_CTRL, val);
1049 1051 }
1050 1052
1051 1053 OSAL_DCBX_AEN(p_hwfn, type);
1052 1054
1053 1055 return rc;
1054 1056 }
1055 1057
1056 1058 enum _ecore_status_t ecore_dcbx_info_alloc(struct ecore_hwfn *p_hwfn)
1057 1059 {
1058 1060 #ifndef __EXTRACT__LINUX__
1059 1061 OSAL_BUILD_BUG_ON(ECORE_LLDP_CHASSIS_ID_STAT_LEN !=
1060 1062 LLDP_CHASSIS_ID_STAT_LEN);
1061 1063 OSAL_BUILD_BUG_ON(ECORE_LLDP_PORT_ID_STAT_LEN !=
1062 1064 LLDP_PORT_ID_STAT_LEN);
1063 1065 OSAL_BUILD_BUG_ON(ECORE_DCBX_MAX_APP_PROTOCOL !=
1064 1066 DCBX_MAX_APP_PROTOCOL);
1065 1067 #endif
1066 1068
1067 1069 p_hwfn->p_dcbx_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1068 1070 sizeof(*p_hwfn->p_dcbx_info));
1069 1071 if (!p_hwfn->p_dcbx_info) {
1070 1072 DP_NOTICE(p_hwfn, true,
1071 1073 "Failed to allocate `struct ecore_dcbx_info'");
1072 1074 return ECORE_NOMEM;
1073 1075 }
1074 1076
1075 1077 p_hwfn->p_dcbx_info->iwarp_port =
1076 1078 p_hwfn->pf_params.rdma_pf_params.iwarp_port;
1077 1079
1078 1080 return ECORE_SUCCESS;
1079 1081 }
1080 1082
1081 1083 void ecore_dcbx_info_free(struct ecore_hwfn *p_hwfn)
1082 1084 {
1083 1085 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_dcbx_info);
1084 1086 p_hwfn->p_dcbx_info = OSAL_NULL;
1085 1087 }
1086 1088
1087 1089 static void ecore_dcbx_update_protocol_data(struct protocol_dcb_data *p_data,
1088 1090 struct ecore_dcbx_results *p_src,
1089 1091 enum dcbx_protocol_type type)
1090 1092 {
1091 1093 p_data->dcb_enable_flag = p_src->arr[type].enable;
1092 1094 p_data->dcb_priority = p_src->arr[type].priority;
1093 1095 p_data->dcb_tc = p_src->arr[type].tc;
1094 1096 p_data->dscp_enable_flag = p_src->arr[type].dscp_enable;
1095 1097 p_data->dscp_val = p_src->arr[type].dscp_val;
1096 1098 }
1097 1099
1098 1100 /* Set pf update ramrod command params */
1099 1101 void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src,
1100 1102 struct pf_update_ramrod_data *p_dest)
1101 1103 {
1102 1104 struct protocol_dcb_data *p_dcb_data;
1103 1105 u8 update_flag;
1104 1106
1105 1107 p_dest->pf_id = p_src->pf_id;
1106 1108
1107 1109 update_flag = p_src->arr[DCBX_PROTOCOL_FCOE].update;
1108 1110 p_dest->update_fcoe_dcb_data_mode = update_flag;
1109 1111
1110 1112 update_flag = p_src->arr[DCBX_PROTOCOL_ROCE].update;
1111 1113 p_dest->update_roce_dcb_data_mode = update_flag;
1112 1114
1113 1115 update_flag = p_src->arr[DCBX_PROTOCOL_ROCE_V2].update;
1114 1116 p_dest->update_rroce_dcb_data_mode = update_flag;
1115 1117
1116 1118 update_flag = p_src->arr[DCBX_PROTOCOL_ISCSI].update;
1117 1119 p_dest->update_iscsi_dcb_data_mode = update_flag;
1118 1120 update_flag = p_src->arr[DCBX_PROTOCOL_ETH].update;
1119 1121 p_dest->update_eth_dcb_data_mode = update_flag;
1120 1122 update_flag = p_src->arr[DCBX_PROTOCOL_IWARP].update;
1121 1123 p_dest->update_iwarp_dcb_data_mode = update_flag;
1122 1124
1123 1125 p_dcb_data = &p_dest->fcoe_dcb_data;
1124 1126 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_FCOE);
1125 1127 p_dcb_data = &p_dest->roce_dcb_data;
1126 1128 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_ROCE);
1127 1129 p_dcb_data = &p_dest->rroce_dcb_data;
1128 1130 ecore_dcbx_update_protocol_data(p_dcb_data, p_src,
1129 1131 DCBX_PROTOCOL_ROCE_V2);
1130 1132 p_dcb_data = &p_dest->iscsi_dcb_data;
1131 1133 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_ISCSI);
1132 1134 p_dcb_data = &p_dest->eth_dcb_data;
1133 1135 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_ETH);
1134 1136 p_dcb_data = &p_dest->iwarp_dcb_data;
1135 1137 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_IWARP);
1136 1138 }
1137 1139
1138 1140 enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
1139 1141 struct ecore_dcbx_get *p_get,
1140 1142 enum ecore_mib_read_type type)
1141 1143 {
1142 1144 struct ecore_ptt *p_ptt;
1143 1145 enum _ecore_status_t rc;
1144 1146
1145 1147 if (IS_VF(p_hwfn->p_dev))
1146 1148 return ECORE_INVAL;
1147 1149
1148 1150 p_ptt = ecore_ptt_acquire(p_hwfn);
1149 1151 if (!p_ptt) {
1150 1152 rc = ECORE_TIMEOUT;
1151 1153 DP_ERR(p_hwfn, "rc = %d\n", rc);
1152 1154 return rc;
1153 1155 }
1154 1156
1155 1157 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);
1156 1158 if (rc != ECORE_SUCCESS)
1157 1159 goto out;
1158 1160
1159 1161 rc = ecore_dcbx_get_params(p_hwfn, p_ptt, p_get, type);
1160 1162
1161 1163 out:
1162 1164 ecore_ptt_release(p_hwfn, p_ptt);
1163 1165 return rc;
1164 1166 }
1165 1167
1166 1168 static void
1167 1169 ecore_dcbx_set_pfc_data(struct ecore_hwfn *p_hwfn,
1168 1170 u32 *pfc, struct ecore_dcbx_params *p_params)
1169 1171 {
1170 1172 u8 pfc_map = 0;
1171 1173 int i;
1172 1174
1173 1175 *pfc &= ~DCBX_PFC_ERROR_MASK;
1174 1176
1175 1177 if (p_params->pfc.willing)
1176 1178 *pfc |= DCBX_PFC_WILLING_MASK;
1177 1179 else
1178 1180 *pfc &= ~DCBX_PFC_WILLING_MASK;
1179 1181
1180 1182 if (p_params->pfc.enabled)
1181 1183 *pfc |= DCBX_PFC_ENABLED_MASK;
1182 1184 else
1183 1185 *pfc &= ~DCBX_PFC_ENABLED_MASK;
1184 1186
1185 1187 *pfc &= ~DCBX_PFC_CAPS_MASK;
1186 1188 *pfc |= (u32)p_params->pfc.max_tc << DCBX_PFC_CAPS_SHIFT;
1187 1189
1188 1190 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++)
1189 1191 if (p_params->pfc.prio[i])
1190 1192 pfc_map |= (1 << i);
1191 1193 *pfc &= ~DCBX_PFC_PRI_EN_BITMAP_MASK;
1192 1194 *pfc |= (pfc_map << DCBX_PFC_PRI_EN_BITMAP_SHIFT);
1193 1195
1194 1196 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "pfc = 0x%x\n", *pfc);
1195 1197 }
1196 1198
1197 1199 static void
1198 1200 ecore_dcbx_set_ets_data(struct ecore_hwfn *p_hwfn,
1199 1201 struct dcbx_ets_feature *p_ets,
1200 1202 struct ecore_dcbx_params *p_params)
1201 1203 {
1202 1204 u8 *bw_map, *tsa_map;
1203 1205 u32 val;
1204 1206 int i;
1205 1207
1206 1208 if (p_params->ets_willing)
1207 1209 p_ets->flags |= DCBX_ETS_WILLING_MASK;
1208 1210 else
1209 1211 p_ets->flags &= ~DCBX_ETS_WILLING_MASK;
1210 1212
1211 1213 if (p_params->ets_cbs)
1212 1214 p_ets->flags |= DCBX_ETS_CBS_MASK;
1213 1215 else
1214 1216 p_ets->flags &= ~DCBX_ETS_CBS_MASK;
1215 1217
1216 1218 if (p_params->ets_enabled)
1217 1219 p_ets->flags |= DCBX_ETS_ENABLED_MASK;
1218 1220 else
1219 1221 p_ets->flags &= ~DCBX_ETS_ENABLED_MASK;
1220 1222
1221 1223 p_ets->flags &= ~DCBX_ETS_MAX_TCS_MASK;
1222 1224 p_ets->flags |= (u32)p_params->max_ets_tc << DCBX_ETS_MAX_TCS_SHIFT;
1223 1225
1224 1226 bw_map = (u8 *)&p_ets->tc_bw_tbl[0];
1225 1227 tsa_map = (u8 *)&p_ets->tc_tsa_tbl[0];
1226 1228 p_ets->pri_tc_tbl[0] = 0;
1227 1229 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) {
1228 1230 bw_map[i] = p_params->ets_tc_bw_tbl[i];
1229 1231 tsa_map[i] = p_params->ets_tc_tsa_tbl[i];
1230 1232 /* Copy the priority value to the corresponding 4 bits in the
1231 1233 * traffic class table.
1232 1234 */
1233 1235 val = (((u32)p_params->ets_pri_tc_tbl[i]) << ((7 - i) * 4));
1234 1236 p_ets->pri_tc_tbl[0] |= val;
1235 1237 }
1236 1238 for (i = 0; i < 2; i++) {
1237 1239 p_ets->tc_bw_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_bw_tbl[i]);
1238 1240 p_ets->tc_tsa_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_tsa_tbl[i]);
1239 1241 }
1240 1242
1241 1243 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1242 1244 "flags = 0x%x pri_tc = 0x%x tc_bwl[] = {0x%x, 0x%x} tc_tsa = {0x%x, 0x%x}\n",
1243 1245 p_ets->flags, p_ets->pri_tc_tbl[0], p_ets->tc_bw_tbl[0],
1244 1246 p_ets->tc_bw_tbl[1], p_ets->tc_tsa_tbl[0],
1245 1247 p_ets->tc_tsa_tbl[1]);
1246 1248 }
1247 1249
1248 1250 static void
1249 1251 ecore_dcbx_set_app_data(struct ecore_hwfn *p_hwfn,
1250 1252 struct dcbx_app_priority_feature *p_app,
1251 1253 struct ecore_dcbx_params *p_params, bool ieee)
1252 1254 {
1253 1255 u32 *entry;
1254 1256 int i;
1255 1257
1256 1258 if (p_params->app_willing)
1257 1259 p_app->flags |= DCBX_APP_WILLING_MASK;
1258 1260 else
1259 1261 p_app->flags &= ~DCBX_APP_WILLING_MASK;
1260 1262
1261 1263 if (p_params->app_valid)
1262 1264 p_app->flags |= DCBX_APP_ENABLED_MASK;
1263 1265 else
1264 1266 p_app->flags &= ~DCBX_APP_ENABLED_MASK;
1265 1267
1266 1268 p_app->flags &= ~DCBX_APP_NUM_ENTRIES_MASK;
1267 1269 p_app->flags |= (u32)p_params->num_app_entries <<
1268 1270 DCBX_APP_NUM_ENTRIES_SHIFT;
1269 1271
1270 1272 for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
1271 1273 entry = &p_app->app_pri_tbl[i].entry;
1272 1274 *entry = 0;
1273 1275 if (ieee) {
1274 1276 *entry &= ~(DCBX_APP_SF_IEEE_MASK | DCBX_APP_SF_MASK);
1275 1277 switch (p_params->app_entry[i].sf_ieee) {
1276 1278 case ECORE_DCBX_SF_IEEE_ETHTYPE:
1277 1279 *entry |= ((u32)DCBX_APP_SF_IEEE_ETHTYPE <<
1278 1280 DCBX_APP_SF_IEEE_SHIFT);
1279 1281 *entry |= ((u32)DCBX_APP_SF_ETHTYPE <<
1280 1282 DCBX_APP_SF_SHIFT);
1281 1283 break;
1282 1284 case ECORE_DCBX_SF_IEEE_TCP_PORT:
1283 1285 *entry |= ((u32)DCBX_APP_SF_IEEE_TCP_PORT <<
1284 1286 DCBX_APP_SF_IEEE_SHIFT);
1285 1287 *entry |= ((u32)DCBX_APP_SF_PORT <<
1286 1288 DCBX_APP_SF_SHIFT);
1287 1289 break;
1288 1290 case ECORE_DCBX_SF_IEEE_UDP_PORT:
1289 1291 *entry |= ((u32)DCBX_APP_SF_IEEE_UDP_PORT <<
1290 1292 DCBX_APP_SF_IEEE_SHIFT);
1291 1293 *entry |= ((u32)DCBX_APP_SF_PORT <<
1292 1294 DCBX_APP_SF_SHIFT);
1293 1295 break;
1294 1296 case ECORE_DCBX_SF_IEEE_TCP_UDP_PORT:
1295 1297 *entry |= (u32)DCBX_APP_SF_IEEE_TCP_UDP_PORT <<
1296 1298 DCBX_APP_SF_IEEE_SHIFT;
1297 1299 *entry |= ((u32)DCBX_APP_SF_PORT <<
1298 1300 DCBX_APP_SF_SHIFT);
1299 1301 break;
1300 1302 }
1301 1303 } else {
1302 1304 *entry &= ~DCBX_APP_SF_MASK;
1303 1305 if (p_params->app_entry[i].ethtype)
1304 1306 *entry |= ((u32)DCBX_APP_SF_ETHTYPE <<
1305 1307 DCBX_APP_SF_SHIFT);
1306 1308 else
1307 1309 *entry |= ((u32)DCBX_APP_SF_PORT <<
1308 1310 DCBX_APP_SF_SHIFT);
1309 1311 }
1310 1312 *entry &= ~DCBX_APP_PROTOCOL_ID_MASK;
1311 1313 *entry |= ((u32)p_params->app_entry[i].proto_id <<
1312 1314 DCBX_APP_PROTOCOL_ID_SHIFT);
1313 1315 *entry &= ~DCBX_APP_PRI_MAP_MASK;
1314 1316 *entry |= ((u32)(p_params->app_entry[i].prio) <<
1315 1317 DCBX_APP_PRI_MAP_SHIFT);
1316 1318 }
1317 1319
1318 1320 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_app->flags);
1319 1321 }
1320 1322
1321 1323 static enum _ecore_status_t
1322 1324 ecore_dcbx_set_local_params(struct ecore_hwfn *p_hwfn,
1323 1325 struct dcbx_local_params *local_admin,
1324 1326 struct ecore_dcbx_set *params)
1325 1327 {
1326 1328 bool ieee = false;
1327 1329
1328 1330 local_admin->flags = 0;
1329 1331 OSAL_MEMCPY(&local_admin->features,
1330 1332 &p_hwfn->p_dcbx_info->operational.features,
1331 1333 sizeof(local_admin->features));
1332 1334
1333 1335 if (params->enabled) {
1334 1336 local_admin->config = params->ver_num;
1335 1337 ieee = !!(params->ver_num & DCBX_CONFIG_VERSION_IEEE);
1336 1338 } else
1337 1339 local_admin->config = DCBX_CONFIG_VERSION_DISABLED;
1338 1340
1339 1341 if (params->override_flags & ECORE_DCBX_OVERRIDE_PFC_CFG)
1340 1342 ecore_dcbx_set_pfc_data(p_hwfn, &local_admin->features.pfc,
1341 1343 ¶ms->config.params);
1342 1344
1343 1345 if (params->override_flags & ECORE_DCBX_OVERRIDE_ETS_CFG)
1344 1346 ecore_dcbx_set_ets_data(p_hwfn, &local_admin->features.ets,
1345 1347 ¶ms->config.params);
1346 1348
1347 1349 if (params->override_flags & ECORE_DCBX_OVERRIDE_APP_CFG)
1348 1350 ecore_dcbx_set_app_data(p_hwfn, &local_admin->features.app,
1349 1351 ¶ms->config.params, ieee);
1350 1352
1351 1353 return ECORE_SUCCESS;
1352 1354 }
1353 1355
1354 1356 static enum _ecore_status_t
1355 1357 ecore_dcbx_set_dscp_params(struct ecore_hwfn *p_hwfn,
1356 1358 struct dcb_dscp_map *p_dscp_map,
1357 1359 struct ecore_dcbx_set *p_params)
1358 1360 {
1359 1361 int entry, i, j;
1360 1362 u32 val;
1361 1363
1362 1364 OSAL_MEMCPY(p_dscp_map, &p_hwfn->p_dcbx_info->dscp_map,
1363 1365 sizeof(*p_dscp_map));
1364 1366
1365 1367 p_dscp_map->flags &= ~DCB_DSCP_ENABLE_MASK;
1366 1368 if (p_params->dscp.enabled)
1367 1369 p_dscp_map->flags |= DCB_DSCP_ENABLE_MASK;
1368 1370
1369 1371 for (i = 0, entry = 0; i < 8; i++) {
1370 1372 val = 0;
1371 1373 for (j = 0; j < 8; j++, entry++)
1372 1374 val |= (((u32)p_params->dscp.dscp_pri_map[entry]) <<
1373 1375 (j * 4));
1374 1376
1375 1377 p_dscp_map->dscp_pri_map[i] = OSAL_CPU_TO_BE32(val);
1376 1378 }
1377 1379
1378 1380 p_hwfn->p_dcbx_info->dscp_nig_update = true;
1379 1381
1380 1382 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_dscp_map->flags);
1381 1383
1382 1384 return ECORE_SUCCESS;
1383 1385 }
1384 1386
1385 1387 enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *p_hwfn,
1386 1388 struct ecore_ptt *p_ptt,
1387 1389 struct ecore_dcbx_set *params,
1388 1390 bool hw_commit)
1389 1391 {
1390 1392 struct dcbx_local_params local_admin;
1391 1393 struct ecore_dcbx_mib_meta_data data;
1392 1394 struct dcb_dscp_map dscp_map;
1393 1395 u32 resp = 0, param = 0;
1394 1396 enum _ecore_status_t rc = ECORE_SUCCESS;
1395 1397
1396 1398 if (!hw_commit) {
1397 1399 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set, params,
1398 1400 sizeof(p_hwfn->p_dcbx_info->set));
1399 1401 return ECORE_SUCCESS;
1400 1402 }
1401 1403
1402 1404 /* clear set-parmas cache */
1403 1405 OSAL_MEMSET(&p_hwfn->p_dcbx_info->set, 0,
1404 1406 sizeof(struct ecore_dcbx_set));
1405 1407
1406 1408 OSAL_MEMSET(&local_admin, 0, sizeof(local_admin));
1407 1409 ecore_dcbx_set_local_params(p_hwfn, &local_admin, params);
1408 1410
1409 1411 data.addr = p_hwfn->mcp_info->port_addr +
1410 1412 offsetof(struct public_port, local_admin_dcbx_mib);
1411 1413 data.local_admin = &local_admin;
1412 1414 data.size = sizeof(struct dcbx_local_params);
1413 1415 ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.local_admin, data.size);
1414 1416
1415 1417 if (params->override_flags & ECORE_DCBX_OVERRIDE_DSCP_CFG) {
1416 1418 OSAL_MEMSET(&dscp_map, 0, sizeof(dscp_map));
1417 1419 ecore_dcbx_set_dscp_params(p_hwfn, &dscp_map, params);
1418 1420
1419 1421 data.addr = p_hwfn->mcp_info->port_addr +
1420 1422 offsetof(struct public_port, dcb_dscp_map);
1421 1423 data.dscp_map = &dscp_map;
1422 1424 data.size = sizeof(struct dcb_dscp_map);
1423 1425 ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.dscp_map,
1424 1426 data.size);
1425 1427 }
1426 1428
1427 1429 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_DCBX,
1428 1430 1 << DRV_MB_PARAM_LLDP_SEND_SHIFT, &resp, ¶m);
1429 1431 if (rc != ECORE_SUCCESS) {
1430 1432 DP_NOTICE(p_hwfn, false,
1431 1433 "Failed to send DCBX update request\n");
1432 1434 return rc;
1433 1435 }
1434 1436
1435 1437 return rc;
1436 1438 }
1437 1439
1438 1440 enum _ecore_status_t ecore_dcbx_get_config_params(struct ecore_hwfn *p_hwfn,
1439 1441 struct ecore_dcbx_set *params)
1440 1442 {
1441 1443 struct ecore_dcbx_get *dcbx_info;
1442 1444 int rc;
1443 1445
1444 1446 if (p_hwfn->p_dcbx_info->set.config.valid) {
1445 1447 OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set,
1446 1448 sizeof(struct ecore_dcbx_set));
1447 1449 return ECORE_SUCCESS;
1448 1450 }
1449 1451
1450 1452 dcbx_info = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1451 1453 sizeof(*dcbx_info));
1452 1454 if (!dcbx_info) {
1453 1455 DP_ERR(p_hwfn, "Failed to allocate struct ecore_dcbx_info\n");
1454 1456 return ECORE_NOMEM;
1455 1457 }
1456 1458
1457 1459 OSAL_MEMSET(dcbx_info, 0, sizeof(*dcbx_info));
1458 1460 rc = ecore_dcbx_query_params(p_hwfn, dcbx_info,
1459 1461 ECORE_DCBX_OPERATIONAL_MIB);
1460 1462 if (rc) {
1461 1463 OSAL_FREE(p_hwfn->p_dev, dcbx_info);
1462 1464 return rc;
1463 1465 }
1464 1466 p_hwfn->p_dcbx_info->set.override_flags = 0;
1465 1467
1466 1468 p_hwfn->p_dcbx_info->set.ver_num = DCBX_CONFIG_VERSION_DISABLED;
1467 1469 if (dcbx_info->operational.cee)
1468 1470 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_CEE;
1469 1471 if (dcbx_info->operational.ieee)
1470 1472 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_IEEE;
1471 1473 if (dcbx_info->operational.local)
1472 1474 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_STATIC;
1473 1475
1474 1476 p_hwfn->p_dcbx_info->set.enabled = dcbx_info->operational.enabled;
1475 1477 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.config.params,
1476 1478 &dcbx_info->operational.params,
1477 1479 sizeof(struct ecore_dcbx_admin_params));
1478 1480 p_hwfn->p_dcbx_info->set.config.valid = true;
1479 1481
1480 1482 OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set,
1481 1483 sizeof(struct ecore_dcbx_set));
1482 1484
1483 1485 OSAL_FREE(p_hwfn->p_dev, dcbx_info);
1484 1486
1485 1487 return ECORE_SUCCESS;
1486 1488 }
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