--- old/usr/src/uts/sun4u/cpu/us3_common_asm.s	Fri Feb 28 06:15:57 2020
+++ new/usr/src/uts/sun4u/cpu/us3_common_asm.s	Fri Feb 28 06:15:57 2020
@@ -25,9 +25,7 @@
  * Assembly code support for Cheetah/Cheetah+ modules
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif	/* !lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -51,8 +49,6 @@
 #include <sys/traptrace.h>
 #endif /* TRAPTRACE */
 
-#if !defined(lint)
-
 /* BEGIN CSTYLED */
 
 #define	DCACHE_FLUSHPAGE(arg1, arg2, tmp1, tmp2, tmp3)			\
@@ -169,21 +165,10 @@
 
 /* END CSTYLED */
 
-#endif	/* !lint */
-
 /*
  * Cheetah MMU and Cache operations.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flushpage(caddr_t vaddr, uint64_t sfmmup)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushpage)
 	/*
 	 * flush page from the tlb
@@ -252,16 +237,6 @@
 	wrpr	%g0, %o5, %pstate		/* enable interrupts */
 	SET_SIZE(vtag_flushpage)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-vtag_flushall(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP2(vtag_flushall, demap_all)
 	/*
 	 * flush the tlb
@@ -276,18 +251,7 @@
 	SET_SIZE(demap_all)
 	SET_SIZE(vtag_flushall)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushpage_tl1)
 	/*
 	 * x-trap to flush page from tlb and tsb
@@ -332,18 +296,7 @@
 	retry
 	SET_SIZE(vtag_flushpage_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flush_pgcnt_tl1)
 	/*
 	 * x-trap to flush pgcnt MMU_PAGESIZE pages from tlb
@@ -422,17 +375,6 @@
 	retry
 	SET_SIZE(vtag_flush_pgcnt_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vtag_flushall_tl1)
 	/*
 	 * x-trap to flush tlb
@@ -443,18 +385,7 @@
 	retry
 	SET_SIZE(vtag_flushall_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushpage(pfn_t pfnum, int vcolor)
-{}
-
-#else	/* lint */
-
 /*
  * vac_flushpage(pfnum, color)
  *	Flush 1 8k page of the D-$ with physical page = pfnum
@@ -479,18 +410,7 @@
 	  nop
 	SET_SIZE(vac_flushpage)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(vac_flushpage_tl1)
 	/*
 	 * x-trap to flush page from the d$
@@ -501,18 +421,7 @@
 	retry
 	SET_SIZE(vac_flushpage_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushcolor(int vcolor, pfn_t pfnum)
-{}
-
-#else	/* lint */
-
 	ENTRY(vac_flushcolor)
 	/*
 	 * %o0 = vcolor
@@ -525,18 +434,7 @@
 	  nop
 	SET_SIZE(vac_flushcolor)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushcolor_tl1(uint64_t vcolor, uint64_t pfnum)
-{}
-
-#else	/* lint */
-
 	ENTRY(vac_flushcolor_tl1)
 	/*
 	 * %g1 = vcolor
@@ -548,18 +446,6 @@
 	retry
 	SET_SIZE(vac_flushcolor_tl1)
 
-#endif	/* lint */
-
-#if defined(lint)
- 
-int
-idsr_busy(void)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 /*
  * Determine whether or not the IDSR is busy.
  * Entry: no arguments
@@ -576,22 +462,6 @@
 	nop
 	SET_SIZE(idsr_busy)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-/* ARGSUSED */
-void
-init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-#else	/* lint */
-
 	.global _dispatch_status_busy
 _dispatch_status_busy:
 	.asciz	"ASI_INTR_DISPATCH_STATUS error: busy"
@@ -645,20 +515,9 @@
 	SET_SIZE(init_mondo_nocheck)
 	SET_SIZE(init_mondo)
 
-#endif	/* lint */
 
-
 #if !(defined(JALAPENO) || defined(SERRANO))
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-shipit(int upaid, int bn)
-{ return; }
-
-#else	/* lint */
-
 /*
  * Ship mondo to aid using busy/nack pair bn
  */
@@ -673,20 +532,9 @@
 	nop
 	SET_SIZE(shipit)
 
-#endif	/* lint */
-
 #endif	/* !(JALAPENO || SERRANO) */
 
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-flush_instr_mem(caddr_t vaddr, size_t len)
-{}
-
-#else	/* lint */
-
 /*
  * flush_instr_mem:
  *	Flush 1 page of the I-$ starting at vaddr
@@ -705,20 +553,9 @@
 	nop
 	SET_SIZE(flush_instr_mem)
 
-#endif	/* lint */
 
-
 #if defined(CPU_IMP_ECACHE_ASSOC)
 
-#if defined(lint)
-
-/* ARGSUSED */
-uint64_t
-get_ecache_ctrl(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(get_ecache_ctrl)
 	GET_CPU_IMPL(%o0)
 	cmp	%o0, JAGUAR_IMPL
@@ -738,8 +575,6 @@
 	  nop
 	SET_SIZE(get_ecache_ctrl)
 
-#endif	/* lint */
-
 #endif	/* CPU_IMP_ECACHE_ASSOC */
 
 
@@ -751,15 +586,7 @@
  *	%o1 - ecache size
  *	%o2 - ecache linesize
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-void
-flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
-{}
-
-#else /* !lint */
-
 	ENTRY(flush_ecache)
 
 	/*
@@ -777,19 +604,9 @@
 	nop
 	SET_SIZE(flush_ecache)
 
-#endif /* lint */
-
 #endif	/* !(JALAPENO || SERRANO) */
 
 
-#if defined(lint)
-
-void
-flush_dcache(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(flush_dcache)
 	ASM_LD(%o0, dcache_size)
 	ASM_LD(%o1, dcache_linesize)
@@ -798,17 +615,7 @@
 	nop
 	SET_SIZE(flush_dcache)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-void
-flush_icache(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(flush_icache)
 	GET_CPU_PRIVATE_PTR(%g0, %o0, %o2, flush_icache_1);
 	ld	[%o0 + CHPR_ICACHE_LINESIZE], %o1
@@ -823,19 +630,6 @@
 	nop
 	SET_SIZE(flush_icache)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-kdi_flush_idcache(int dcache_size, int dcache_lsize, int icache_size, 
-    int icache_lsize)
-{
-}
-
-#else	/* lint */
-
 	ENTRY(kdi_flush_idcache)
 	CH_DCACHE_FLUSHALL(%o0, %o1, %g1)
 	CH_ICACHE_FLUSHALL(%o2, %o3, %g1, %g2)
@@ -844,16 +638,6 @@
 	nop
 	SET_SIZE(kdi_flush_idcache)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-void
-flush_pcache(void)
-{}
-
-#else	/* lint */
-
 	ENTRY(flush_pcache)
 	PCACHE_FLUSHALL(%o0, %o1, %o2)
 	retl
@@ -860,20 +644,9 @@
 	nop
 	SET_SIZE(flush_pcache)
 
-#endif	/* lint */
 
-
 #if defined(CPU_IMP_L1_CACHE_PARITY)
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-get_dcache_dtag(uint32_t dcache_idx, uint64_t *data)
-{}
-
-#else	/* lint */
-
 /*
  * Get dcache data and tag.  The Dcache data is a pointer to a ch_dc_data_t
  * structure (see cheetahregs.h):
@@ -951,18 +724,7 @@
 	  wrpr	%g0, %o5, %pstate	
 	SET_SIZE(get_dcache_dtag)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-get_icache_dtag(uint32_t ecache_idx, uint64_t *data)
-{}
-
-#else	/* lint */
-
 /*
  * Get icache data and tag.  The data argument is a pointer to a ch_ic_data_t
  * structure (see cheetahregs.h):
@@ -1004,17 +766,6 @@
 	  wrpr	%g0, %o5, %pstate	
 	SET_SIZE(get_icache_dtag)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-get_pcache_dtag(uint32_t pcache_idx, uint64_t *data)
-{}
-
-#else	/* lint */
-
 /*
  * Get pcache data and tags.
  * inputs:
@@ -1050,19 +801,8 @@
 	  wrpr	%g0, %o5, %pstate	
 	SET_SIZE(get_pcache_dtag)
 
-#endif	/* lint */
-
 #endif	/* CPU_IMP_L1_CACHE_PARITY */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-set_dcu(uint64_t dcu)
-{}
-
-#else	/* lint */
-
 /*
  * re-enable the i$, d$, w$, and p$ according to bootup cache state.
  * Turn on WE, HPE, SPE, PE, IC, and DC bits defined as DCU_CACHE.
@@ -1075,19 +815,7 @@
 	nop
 	SET_SIZE(set_dcu)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-uint64_t
-get_dcu(void)
-{
-	return ((uint64_t)0);
-}
-
-#else	/* lint */
-
 /*
  * Return DCU register.
  */
@@ -1097,8 +825,6 @@
 	nop
 	SET_SIZE(get_dcu)
 
-#endif	/* lint */
-
 /*
  * Cheetah/Cheetah+ level 15 interrupt handler trap table entry.
  *
@@ -1109,29 +835,12 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
 
-void
-ch_pil15_interrupt_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(ch_pil15_interrupt_instr)
 	ASM_JMP(%g1, ch_pil15_interrupt)
 	SET_SIZE(ch_pil15_interrupt_instr)
 
-#endif
 
-
-#if defined(lint)
-
-void
-ch_pil15_interrupt(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(ch_pil15_interrupt)
 
 	/*
@@ -1185,7 +894,6 @@
 	  mov	PIL_15, %g4
 
 	SET_SIZE(ch_pil15_interrupt)
-#endif
 
 
 /*
@@ -1278,14 +986,6 @@
  *     be relocatable.
  */
 
-#if defined(lint)
-
-void
-fecc_err_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fecc_err_instr)
 	membar	#Sync			! Cheetah requires membar #Sync
 
@@ -1300,19 +1000,9 @@
 	ASM_JMP(%g4, fast_ecc_err)
 	SET_SIZE(fecc_err_instr)
 
-#endif	/* lint */
 
-
 #if !(defined(JALAPENO) || defined(SERRANO))
 
-#if defined(lint)
-
-void
-fast_ecc_err(void)
-{}
-
-#else	/* lint */
-
 	.section ".text"
 	.align	64
 	ENTRY_NP(fast_ecc_err)
@@ -1452,8 +1142,6 @@
 
 	SET_SIZE(fast_ecc_err)
 
-#endif	/* lint */
-
 #endif	/* !(JALAPENO || SERRANO) */
 
 
@@ -1511,20 +1199,10 @@
  *     be relocatable.
  */
 
-#if defined(lint)
-
-void
-fecc_err_tl1_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fecc_err_tl1_instr)
 	CH_ERR_TL1_TRAPENTRY(SWTRAP_0);
 	SET_SIZE(fecc_err_tl1_instr)
 
-#endif	/* lint */
-
 /*
  * Software trap 0 at TL>0.
  * tt1_swtrap0 is replaced by fecc_err_tl1_cont_instr in cpu_init_trap of
@@ -1537,29 +1215,12 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
 
-void
-fecc_err_tl1_cont_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(fecc_err_tl1_cont_instr)
 	CH_ERR_TL1_SWTRAPENTRY(fast_ecc_tl1_err)
 	SET_SIZE(fecc_err_tl1_cont_instr)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-void
-ce_err(void)
-{}
-
-#else	/* lint */
-
 /*
  * The ce_err function handles disrupting trap type 0x63 at TL=0.
  *
@@ -1738,21 +1399,11 @@
 	  movl	%icc, PIL_14, %g4
 	SET_SIZE(ce_err)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
 /*
  * This trap cannot happen at TL>0 which means this routine will never
  * actually be called and so we treat this like a BAD TRAP panic.
  */
-void
-ce_err_tl1(void)
-{}
-
-#else	/* lint */
-
 	.align	64
 	ENTRY_NP(ce_err_tl1)
 
@@ -1761,17 +1412,7 @@
 
 	SET_SIZE(ce_err_tl1)
 
-#endif	/* lint */
-
 	
-#if defined(lint)
-
-void
-async_err(void)
-{}
-
-#else	/* lint */
-
 /*
  * The async_err function handles deferred trap types 0xA 
  * (instruction_access_error) and 0x32 (data_access_error) at TL>=0.
@@ -1969,8 +1610,6 @@
 	  mov	PIL_15, %g4		! run at pil 15
 	SET_SIZE(async_err)
 
-#endif	/* lint */
-
 #if defined(CPU_IMP_L1_CACHE_PARITY)
 
 /*
@@ -1981,13 +1620,6 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-dcache_parity_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(dcache_parity_instr)
 	membar	#Sync			! Cheetah+ requires membar #Sync
 	set	cpu_parity_error, %g1
@@ -1998,9 +1630,7 @@
 	  mov	PIL_15, %g4		! run at pil 15
 	SET_SIZE(dcache_parity_instr)
 
-#endif	/* lint */
 
-
 /*
  * D$ parity error trap (trap 71) at TL>0.
  * tt1_dperr is replaced by dcache_parity_tl1_instr in cpu_init_trap of
@@ -2010,20 +1640,11 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-dcache_parity_tl1_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(dcache_parity_tl1_instr)
 	CH_ERR_TL1_TRAPENTRY(SWTRAP_1);
 	SET_SIZE(dcache_parity_tl1_instr)
 
-#endif	/* lint */
 
-
 /*
  * Software trap 1 at TL>0.
  * tt1_swtrap1 is replaced by dcache_parity_tl1_cont_instr in cpu_init_trap
@@ -2036,32 +1657,16 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-dcache_parity_tl1_cont_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(dcache_parity_tl1_cont_instr)
 	CH_ERR_TL1_SWTRAPENTRY(dcache_parity_tl1_err);
 	SET_SIZE(dcache_parity_tl1_cont_instr)
 
-#endif	/* lint */
-
 /*
  * D$ parity error at TL>0 handler
  * We get here via trap 71 at TL>0->Software trap 1 at TL>0.  We enter
  * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
  */
-#if defined(lint)
 
-void
-dcache_parity_tl1_err(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(dcache_parity_tl1_err)
 
 	/*
@@ -2152,8 +1757,6 @@
 	CH_ERR_TL1_EXIT;
 	SET_SIZE(dcache_parity_tl1_err)
 
-#endif	/* lint */
-
 /*
  * I$ parity error trap (trap 72) at TL=0.
  * tt0_iperr is replaced by icache_parity_instr in cpu_init_trap of
@@ -2162,14 +1765,7 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
 
-void
-icache_parity_instr(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(icache_parity_instr)
 	membar	#Sync			! Cheetah+ requires membar #Sync
 	set	cpu_parity_error, %g1
@@ -2180,8 +1776,6 @@
 	  mov	PIL_15, %g4		! run at pil 15
 	SET_SIZE(icache_parity_instr)
 
-#endif	/* lint */
-
 /*
  * I$ parity error trap (trap 72) at TL>0.
  * tt1_iperr is replaced by icache_parity_tl1_instr in cpu_init_trap of
@@ -2191,19 +1785,10 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-icache_parity_tl1_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(icache_parity_tl1_instr)
 	CH_ERR_TL1_TRAPENTRY(SWTRAP_2);
 	SET_SIZE(icache_parity_tl1_instr)
 
-#endif	/* lint */
-
 /*
  * Software trap 2 at TL>0.
  * tt1_swtrap2 is replaced by icache_parity_tl1_cont_instr in cpu_init_trap
@@ -2216,33 +1801,17 @@
  * NB: Must be 8 instructions or less to fit in trap table and code must
  *     be relocatable.
  */
-#if defined(lint)
-
-void
-icache_parity_tl1_cont_instr(void)
-{}
-
-#else	/* lint */
 	ENTRY_NP(icache_parity_tl1_cont_instr)
 	CH_ERR_TL1_SWTRAPENTRY(icache_parity_tl1_err);
 	SET_SIZE(icache_parity_tl1_cont_instr)
 
-#endif	/* lint */
 
-
 /*
  * I$ parity error at TL>0 handler
  * We get here via trap 72 at TL>0->Software trap 2 at TL>0.  We enter
  * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
  */
-#if defined(lint)
 
-void
-icache_parity_tl1_err(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(icache_parity_tl1_err)
 
 	/*
@@ -2318,8 +1887,6 @@
 
 	SET_SIZE(icache_parity_tl1_err)
 
-#endif	/* lint */
-
 #endif	/* CPU_IMP_L1_CACHE_PARITY */
 
 
@@ -2332,15 +1899,6 @@
  * Note: These two routines are required by the Estar "cpr" loadable module.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(itlb_rd_entry)
 	sllx	%o0, 3, %o0
 	ldxa	[%o0]ASI_ITLB_ACCESS, %g1
@@ -2352,18 +1910,7 @@
 	  stx	%o5, [%o2]
 	SET_SIZE(itlb_rd_entry)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(dtlb_rd_entry)
 	sllx	%o0, 3, %o0
 	ldxa	[%o0]ASI_DTLB_ACCESS, %g1
@@ -2374,19 +1921,10 @@
 	retl
 	  stx	%o5, [%o2]
 	SET_SIZE(dtlb_rd_entry)
-#endif	/* lint */
 
 
 #if !(defined(JALAPENO) || defined(SERRANO))
 
-#if defined(lint)
-
-uint64_t
-get_safari_config(void)
-{ return (0); }
-
-#else	/* lint */
-
 	ENTRY(get_safari_config)
 	ldxa	[%g0]ASI_SAFARI_CONFIG, %o0
 	retl
@@ -2393,18 +1931,7 @@
 	nop
 	SET_SIZE(get_safari_config)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-set_safari_config(uint64_t safari_config)
-{}
-
-#else	/* lint */
-
 	ENTRY(set_safari_config)
 	stxa	%o0, [%g0]ASI_SAFARI_CONFIG
 	membar	#Sync
@@ -2412,18 +1939,9 @@
 	nop
 	SET_SIZE(set_safari_config)
 
-#endif	/* lint */
-
 #endif	/* !(JALAPENO || SERRANO) */
 
 
-#if defined(lint)
-
-void
-cpu_cleartickpnt(void)
-{}
-
-#else	/* lint */
 	/*
 	 * Clear the NPT (non-privileged trap) bit in the %tick/%stick
 	 * registers. In an effort to make the change in the
@@ -2463,26 +1981,16 @@
 	
 	SET_SIZE(cpu_clearticknpt)
 
-#endif	/* lint */
 
-
 #if defined(CPU_IMP_L1_CACHE_PARITY)
 
-#if defined(lint)
 /*
  * correct_dcache_parity(size_t size, size_t linesize)
  *
  * Correct D$ data parity by zeroing the data and initializing microtag
  * for all indexes and all ways of the D$.
- * 
+ *
  */
-/* ARGSUSED */
-void
-correct_dcache_parity(size_t size, size_t linesize)
-{}
-
-#else	/* lint */
-
 	ENTRY(correct_dcache_parity)
 	/*
 	 * Register Usage:
@@ -2544,23 +2052,9 @@
 	  nop
 	SET_SIZE(correct_dcache_parity)
 
-#endif	/* lint */
-
 #endif	/* CPU_IMP_L1_CACHE_PARITY */
 
 
-#if defined(lint)
-/*
- *  Get timestamp (stick).
- */
-/* ARGSUSED */
-void
-stick_timestamp(int64_t *ts)
-{
-}
-
-#else	/* lint */
-
 	ENTRY_NP(stick_timestamp)
 	rd	STICK, %g1	! read stick reg
 	sllx	%g1, 1, %g1
@@ -2570,21 +2064,7 @@
 	stx     %g1, [%o0]	! store the timestamp
 	SET_SIZE(stick_timestamp)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-/*
- * Set STICK adjusted by skew.
- */
-/* ARGSUSED */	
-void
-stick_adj(int64_t skew)
-{
-}
-
-#else	/* lint */
-		
 	ENTRY_NP(stick_adj)
 	rdpr	%pstate, %g1		! save processor state
 	andn	%g1, PSTATE_IE, %g3
@@ -2602,21 +2082,6 @@
 	wrpr	%g1, %pstate		! restore processor state
 	SET_SIZE(stick_adj)
 
-#endif	/* lint */
-
-#if defined(lint)
-/*
- * Debugger-specific stick retrieval
- */
-/*ARGSUSED*/
-int
-kdi_get_stick(uint64_t *stickp)
-{
-	return (0);
-}
-
-#else	/* lint */
-
 	ENTRY_NP(kdi_get_stick)
 	rd	STICK, %g1
 	stx	%g1, [%o0]
@@ -2624,9 +2089,6 @@
 	mov	%g0, %o0
 	SET_SIZE(kdi_get_stick)
 
-#endif	/* lint */
-
-#if defined(lint)
 /*
  * Invalidate the specified line from the D$.
  *
@@ -2659,12 +2121,6 @@
  * Setting the DC_valid bit to zero for the specified DC_way and
  * DC_addr index into the D$ results in an invalidation of a D$ line.
  */
-/*ARGSUSED*/
-void
-dcache_inval_line(int index)
-{
-}
-#else	/* lint */
 	ENTRY(dcache_inval_line)
 	sll	%o0, 5, %o0		! shift index into DC_way and DC_addr
 	stxa	%g0, [%o0]ASI_DC_TAG	! zero the DC_valid and DC_tag bits
@@ -2672,9 +2128,7 @@
 	retl
 	nop
 	SET_SIZE(dcache_inval_line)
-#endif	/* lint */
 
-#if defined(lint)
 /*
  * Invalidate the entire I$
  *
@@ -2722,12 +2176,6 @@
  * Setting the Valid bit to zero for the specified IC_way and
  * IC_addr index into the I$ results in an invalidation of an I$ line.
  */
-/*ARGSUSED*/
-void
-icache_inval_all(void)
-{
-}
-#else	/* lint */
 	ENTRY(icache_inval_all)
 	rdpr	%pstate, %o5
 	andn	%o5, PSTATE_IE, %o3
@@ -2746,17 +2194,8 @@
 	retl
 	wrpr	%g0, %o5, %pstate	! restore earlier pstate
 	SET_SIZE(icache_inval_all)
-#endif	/* lint */
 
 
-#if defined(lint)
-/* ARGSUSED */
-void
-cache_scrubreq_tl1(uint64_t inum, uint64_t index)
-{
-}
-
-#else	/* lint */
 /*
  * cache_scrubreq_tl1 is the crosstrap handler called on offlined cpus via a 
  * crosstrap.  It atomically increments the outstanding request counter and,
@@ -2794,18 +2233,7 @@
 	retry
 	SET_SIZE(cache_scrubreq_tl1)
 
-#endif	/* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-get_cpu_error_state(ch_cpu_errors_t *cpu_error_regs)
-{}
-
-#else	/* lint */
-
 /*
  * Get the error state for the processor.
  * Note that this must not be used at TL>0
@@ -2853,10 +2281,7 @@
 	retl
 	stx	%o1, [%o0 + CH_CPU_ERRORS_AFAR]
 	SET_SIZE(get_cpu_error_state)
-#endif	/* lint */
 
-#if defined(lint)
-
 /*
  * Check a page of memory for errors.
  *
@@ -2867,13 +2292,6 @@
  * Used to determine if a page contains
  * CEs when CEEN is disabled.
  */
-/*ARGSUSED*/
-void
-cpu_check_block(caddr_t va, uint_t psz)
-{}
-
-#else	/* lint */
-
 	ENTRY(cpu_check_block)
 	!
 	! get a new window with room for the error regs
@@ -2912,10 +2330,6 @@
 
 	SET_SIZE(cpu_check_block)
 
-#endif	/* lint */
-
-#if defined(lint)
-
 /*
  * Perform a cpu logout called from C.  This is used where we did not trap
  * for the error but still want to gather "what we can".  Caller must make
@@ -2922,12 +2336,6 @@
  * sure cpu private area exists and that the indicated logout area is free
  * for use, and that we are unable to migrate cpus.
  */
-/*ARGSUSED*/
-void
-cpu_delayed_logout(uint64_t afar, ch_cpu_logout_t *clop)
-{ }
-
-#else
 	ENTRY(cpu_delayed_logout)
 	rdpr	%pstate, %o2
 	andn	%o2, PSTATE_IE, %o2
@@ -2946,17 +2354,6 @@
 	  nop
 	SET_SIZE(cpu_delayed_logout)
 
-#endif	/* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain)
-{ return (0); }
-
-#else
-
 	ENTRY(dtrace_blksuword32)
 	save	%sp, -SA(MINFRAME + 4), %sp
 
@@ -3021,19 +2418,8 @@
 
 	SET_SIZE(dtrace_blksuword32)
 
-#endif /* lint */
-
 #ifdef	CHEETAHPLUS_ERRATUM_25
 
-#if	defined(lint)
-/*
- * Claim a chunk of physical address space.
- */
-/*ARGSUSED*/
-void
-claimlines(uint64_t pa, size_t sz, int stride)
-{}
-#else	/* lint */
 	ENTRY(claimlines)
 1:
 	subcc	%o1, %o2, %o1
@@ -3044,19 +2430,7 @@
 	retl
 	nop
 	SET_SIZE(claimlines)
-#endif	/* lint */
 
-#if	defined(lint)
-/*
- * CPU feature initialization,
- * turn BPE off,
- * get device id.
- */
-/*ARGSUSED*/
-void
-cpu_feature_init(void)
-{}
-#else	/* lint */
 	ENTRY(cpu_feature_init)
 	save	%sp, -SA(MINFRAME), %sp
 	sethi	%hi(cheetah_bpe_off), %o0
@@ -3089,18 +2463,11 @@
 	ret
 	  restore
 	SET_SIZE(cpu_feature_init)
-#endif	/* lint */
 
-#if	defined(lint)
 /*
  * Copy a tsb entry atomically, from src to dest.
  * src must be 128 bit aligned.
  */
-/*ARGSUSED*/
-void
-copy_tsb_entry(uintptr_t src, uintptr_t dest)
-{}
-#else	/* lint */
 	ENTRY(copy_tsb_entry)
 	ldda	[%o0]ASI_NQUAD_LD, %o2		! %o2 = tag, %o3 = data
 	stx	%o2, [%o1]
@@ -3108,21 +2475,11 @@
 	retl
 	nop
 	SET_SIZE(copy_tsb_entry)
-#endif	/* lint */
 
 #endif	/* CHEETAHPLUS_ERRATUM_25 */
 
 #ifdef	CHEETAHPLUS_ERRATUM_34
 
-#if	defined(lint)
-
-/*ARGSUSED*/
-void
-itlb_erratum34_fixup(void)
-{}
-
-#else	/* lint */
-
 	!
 	! In Cheetah+ erratum 34, under certain conditions an ITLB locked
 	! index 0 TTE will erroneously be displaced when a new TTE is
@@ -3187,17 +2544,6 @@
 	  wrpr	%g0, %o3, %pstate		! Enable interrupts
 	SET_SIZE(itlb_erratum34_fixup)
 
-#endif	/* lint */
-
-#if	defined(lint)
-
-/*ARGSUSED*/
-void
-dtlb_erratum34_fixup(void)
-{}
-
-#else	/* lint */
-
 	!
 	! In Cheetah+ erratum 34, under certain conditions a DTLB locked
 	! index 0 TTE will erroneously be displaced when a new TTE is
@@ -3256,7 +2602,5 @@
 	  wrpr	%g0, %o3, %pstate		! Enable interrupts
 	SET_SIZE(dtlb_erratum34_fixup)
 
-#endif	/* lint */
-
 #endif	/* CHEETAHPLUS_ERRATUM_34 */
 
