--- old/usr/src/uts/sun4u/cpu/us3_cheetahplus_asm.s	Fri Feb 28 06:15:56 2020
+++ new/usr/src/uts/sun4u/cpu/us3_cheetahplus_asm.s	Fri Feb 28 06:15:56 2020
@@ -25,11 +25,7 @@
  * Assembly code support for the Cheetah+ module
  */
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#if !defined(lint)
 #include "assym.h"
-#endif	/* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
@@ -55,8 +51,6 @@
 #endif /* TRAPTRACE */
 
 
-#if !defined(lint)
-
 /* BEGIN CSTYLED */
 
 /*
@@ -147,8 +141,6 @@
 	or	l2_idx_out, scr3, l2_idx_out;					\
 	PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
 
-#endif	/* !lint */
-
 /*
  * Fast ECC error at TL>0 handler
  * We get here via trap 70 at TL>0->Software trap 0 at TL>0.  We enter
@@ -157,14 +149,7 @@
  * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
  * us3_common_asm.s
  */
-#if defined(lint)
 
-void
-fast_ecc_tl1_err(void)
-{}
-
-#else	/* lint */
-
 	.section ".text"
 	.align	64
 	ENTRY_NP(fast_ecc_tl1_err)
@@ -413,10 +398,7 @@
 
 	SET_SIZE(fast_ecc_tl1_err)
 
-#endif	/* lint */
 
-
-#if defined(lint)
 /*
  * scrubphys - Pass in the aligned physical memory address
  * that you want to scrub, along with the ecache set size.
@@ -439,12 +421,6 @@
  * will stay E, if the store doesn't happen. So the first displacement flush
  * should ensure that the CAS will miss in the E$.  Arrgh.
  */
-/* ARGSUSED */
-void
-scrubphys(uint64_t paddr, int ecache_set_size)
-{}
-
-#else	/* lint */
 	ENTRY(scrubphys)
 	rdpr	%pstate, %o4
 	andn	%o4, PSTATE_IE | PSTATE_AM, %o5
@@ -470,10 +446,7 @@
 	membar	#Sync			! move the data out of the load buffer
 	SET_SIZE(scrubphys)
 
-#endif	/* lint */
 
-
-#if defined(lint)
 /*
  * clearphys - Pass in the physical memory address of the checkblock
  * that you want to push out, cleared with a recognizable pattern,
@@ -484,13 +457,6 @@
  * in an entire ecache subblock's worth of data, and write it back out.
  * Then we overwrite the 16 bytes of bad data with the pattern.
  */
-/* ARGSUSED */
-void
-clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
-{
-}
-
-#else	/* lint */
 	ENTRY(clearphys)
 	/* turn off IE, AM bits */
 	rdpr	%pstate, %o4
@@ -548,10 +514,7 @@
 	  wrpr	%g0, %o4, %pstate
 	SET_SIZE(clearphys)
 
-#endif	/* lint */
 
-
-#if defined(lint)
 /*
  * Cheetah+ Ecache displacement flush the specified line from the E$
  *
@@ -562,12 +525,6 @@
  *	%o0 - 64 bit physical address for flushing
  *	%o1 - Ecache set size
  */
-/*ARGSUSED*/
-void
-ecache_flush_line(uint64_t flushaddr, int ec_set_size)
-{
-}
-#else	/* lint */
 	ENTRY(ecache_flush_line)
 
 	GET_CPU_IMPL(%o3)		! Panther Ecache is flushed differently
@@ -584,16 +541,7 @@
 	retl
 	  nop
 	SET_SIZE(ecache_flush_line)
-#endif	/* lint */
 
-#if defined(lint)
-void
-set_afsr_ext(uint64_t afsr_ext)
-{
-	afsr_ext = afsr_ext;
-}
-#else /* lint */
-
 	ENTRY(set_afsr_ext)
 	set	ASI_AFSR_EXT_VA, %o1
 	stxa	%o0, [%o1]ASI_AFSR		! afsr_ext reg
@@ -602,10 +550,7 @@
 	nop
 	SET_SIZE(set_afsr_ext)
 
-#endif /* lint */
 
-
-#if defined(lint)
 /*
  * The CPU jumps here from the MMU exception handler if an ITLB parity
  * error is detected and we are running on Panther.
@@ -626,12 +571,6 @@
  * determine whether the logout information is valid for this particular
  * error or not.
  */
-void
-itlb_parity_trap(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(itlb_parity_trap)
 	/*
 	 * Collect important information about the trap which will be
@@ -754,9 +693,6 @@
 	  nop
 	SET_SIZE(itlb_parity_trap)
 
-#endif	/* lint */
-
-#if defined(lint)
 /*
  * The CPU jumps here from the MMU exception handler if a DTLB parity
  * error is detected and we are running on Panther.
@@ -777,12 +713,6 @@
  * determine whether the logout information is valid for this particular
  * error or not.
  */
-void
-dtlb_parity_trap(void)
-{}
-
-#else	/* lint */
-
 	ENTRY_NP(dtlb_parity_trap)
 	/*
 	 * Collect important information about the trap which will be
@@ -967,10 +897,7 @@
 	  nop
 	SET_SIZE(dtlb_parity_trap)
 
-#endif	/* lint */
 
-
-#if defined(lint)
 /*
  * Calculates the Panther TLB index based on a virtual address and page size
  *
@@ -979,12 +906,6 @@
  *	%o1 - Page Size of the TLB in question as encoded in the
  *	      ASI_[D|I]MMU_TAG_ACCESS_EXT register.
  */
-uint64_t
-pn_get_tlb_index(uint64_t va, uint64_t pg_sz)
-{
-	return ((va + pg_sz)-(va + pg_sz));
-}
-#else	/* lint */
 	ENTRY(pn_get_tlb_index)
 
 	PN_GET_TLB_INDEX(%o0, %o1)
@@ -992,20 +913,12 @@
 	retl
 	  nop
 	SET_SIZE(pn_get_tlb_index)
-#endif	/* lint */
 
 
-#if defined(lint)
 /*
  * For Panther CPUs we need to flush the IPB after any I$ or D$
  * parity errors are detected.
  */
-void
-flush_ipb(void)
-{ return; }
-
-#else	/* lint */
-
 	ENTRY(flush_ipb)
 	clr	%o0
 
@@ -1022,6 +935,4 @@
 	nop
 	SET_SIZE(flush_ipb)
 
-#endif	/* lint */
 
-
