1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
  23  * Copyright (c) 2011 by Delphix. All rights reserved.
  24  */
  25 /*
  26  * Copyright (c) 2010, Intel Corporation.
  27  * All rights reserved.
  28  */
  29 /*
  30  * Copyright 2019, Joyent, Inc.
  31  * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
  32  * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
  33  * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
  34  * Copyright 2018 Nexenta Systems, Inc.
  35  */
  36 
  37 #ifndef _SYS_X86_ARCHEXT_H
  38 #define _SYS_X86_ARCHEXT_H
  39 
  40 #if !defined(_ASM)
  41 #include <sys/regset.h>
  42 #include <sys/processor.h>
  43 #include <vm/seg_enum.h>
  44 #include <vm/page.h>
  45 #endif  /* _ASM */
  46 
  47 #ifdef  __cplusplus
  48 extern "C" {
  49 #endif
  50 
  51 /*
  52  * cpuid instruction feature flags in %edx (standard function 1)
  53  */
  54 
  55 #define CPUID_INTC_EDX_FPU      0x00000001      /* x87 fpu present */
  56 #define CPUID_INTC_EDX_VME      0x00000002      /* virtual-8086 extension */
  57 #define CPUID_INTC_EDX_DE       0x00000004      /* debugging extensions */
  58 #define CPUID_INTC_EDX_PSE      0x00000008      /* page size extension */
  59 #define CPUID_INTC_EDX_TSC      0x00000010      /* time stamp counter */
  60 #define CPUID_INTC_EDX_MSR      0x00000020      /* rdmsr and wrmsr */
  61 #define CPUID_INTC_EDX_PAE      0x00000040      /* physical addr extension */
  62 #define CPUID_INTC_EDX_MCE      0x00000080      /* machine check exception */
  63 #define CPUID_INTC_EDX_CX8      0x00000100      /* cmpxchg8b instruction */
  64 #define CPUID_INTC_EDX_APIC     0x00000200      /* local APIC */
  65                                                 /* 0x400 - reserved */
  66 #define CPUID_INTC_EDX_SEP      0x00000800      /* sysenter and sysexit */
  67 #define CPUID_INTC_EDX_MTRR     0x00001000      /* memory type range reg */
  68 #define CPUID_INTC_EDX_PGE      0x00002000      /* page global enable */
  69 #define CPUID_INTC_EDX_MCA      0x00004000      /* machine check arch */
  70 #define CPUID_INTC_EDX_CMOV     0x00008000      /* conditional move insns */
  71 #define CPUID_INTC_EDX_PAT      0x00010000      /* page attribute table */
  72 #define CPUID_INTC_EDX_PSE36    0x00020000      /* 36-bit pagesize extension */
  73 #define CPUID_INTC_EDX_PSN      0x00040000      /* processor serial number */
  74 #define CPUID_INTC_EDX_CLFSH    0x00080000      /* clflush instruction */
  75                                                 /* 0x100000 - reserved */
  76 #define CPUID_INTC_EDX_DS       0x00200000      /* debug store exists */
  77 #define CPUID_INTC_EDX_ACPI     0x00400000      /* monitoring + clock ctrl */
  78 #define CPUID_INTC_EDX_MMX      0x00800000      /* MMX instructions */
  79 #define CPUID_INTC_EDX_FXSR     0x01000000      /* fxsave and fxrstor */
  80 #define CPUID_INTC_EDX_SSE      0x02000000      /* streaming SIMD extensions */
  81 #define CPUID_INTC_EDX_SSE2     0x04000000      /* SSE extensions */
  82 #define CPUID_INTC_EDX_SS       0x08000000      /* self-snoop */
  83 #define CPUID_INTC_EDX_HTT      0x10000000      /* Hyper Thread Technology */
  84 #define CPUID_INTC_EDX_TM       0x20000000      /* thermal monitoring */
  85 #define CPUID_INTC_EDX_IA64     0x40000000      /* Itanium emulating IA32 */
  86 #define CPUID_INTC_EDX_PBE      0x80000000      /* Pending Break Enable */
  87 
  88 /*
  89  * cpuid instruction feature flags in %ecx (standard function 1)
  90  */
  91 
  92 #define CPUID_INTC_ECX_SSE3     0x00000001      /* Yet more SSE extensions */
  93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002     /* PCLMULQDQ insn */
  94 #define CPUID_INTC_ECX_DTES64   0x00000004      /* 64-bit DS area */
  95 #define CPUID_INTC_ECX_MON      0x00000008      /* MONITOR/MWAIT */
  96 #define CPUID_INTC_ECX_DSCPL    0x00000010      /* CPL-qualified debug store */
  97 #define CPUID_INTC_ECX_VMX      0x00000020      /* Hardware VM extensions */
  98 #define CPUID_INTC_ECX_SMX      0x00000040      /* Secure mode extensions */
  99 #define CPUID_INTC_ECX_EST      0x00000080      /* enhanced SpeedStep */
 100 #define CPUID_INTC_ECX_TM2      0x00000100      /* thermal monitoring */
 101 #define CPUID_INTC_ECX_SSSE3    0x00000200      /* Supplemental SSE3 insns */
 102 #define CPUID_INTC_ECX_CID      0x00000400      /* L1 context ID */
 103                                                 /* 0x00000800 - reserved */
 104 #define CPUID_INTC_ECX_FMA      0x00001000      /* Fused Multiply Add */
 105 #define CPUID_INTC_ECX_CX16     0x00002000      /* cmpxchg16 */
 106 #define CPUID_INTC_ECX_ETPRD    0x00004000      /* extended task pri messages */
 107 #define CPUID_INTC_ECX_PDCM     0x00008000      /* Perf/Debug Capability MSR */
 108                                                 /* 0x00010000 - reserved */
 109 #define CPUID_INTC_ECX_PCID     0x00020000      /* process-context ids */
 110 #define CPUID_INTC_ECX_DCA      0x00040000      /* direct cache access */
 111 #define CPUID_INTC_ECX_SSE4_1   0x00080000      /* SSE4.1 insns */
 112 #define CPUID_INTC_ECX_SSE4_2   0x00100000      /* SSE4.2 insns */
 113 #define CPUID_INTC_ECX_X2APIC   0x00200000      /* x2APIC */
 114 #define CPUID_INTC_ECX_MOVBE    0x00400000      /* MOVBE insn */
 115 #define CPUID_INTC_ECX_POPCNT   0x00800000      /* POPCNT insn */
 116 #define CPUID_INTC_ECX_TSCDL    0x01000000      /* Deadline TSC */
 117 #define CPUID_INTC_ECX_AES      0x02000000      /* AES insns */
 118 #define CPUID_INTC_ECX_XSAVE    0x04000000      /* XSAVE/XRESTOR insns */
 119 #define CPUID_INTC_ECX_OSXSAVE  0x08000000      /* OS supports XSAVE insns */
 120 #define CPUID_INTC_ECX_AVX      0x10000000      /* AVX supported */
 121 #define CPUID_INTC_ECX_F16C     0x20000000      /* F16C supported */
 122 #define CPUID_INTC_ECX_RDRAND   0x40000000      /* RDRAND supported */
 123 #define CPUID_INTC_ECX_HV       0x80000000      /* Hypervisor */
 124 
 125 /*
 126  * cpuid instruction feature flags in %edx (extended function 0x80000001)
 127  */
 128 
 129 #define CPUID_AMD_EDX_FPU       0x00000001      /* x87 fpu present */
 130 #define CPUID_AMD_EDX_VME       0x00000002      /* virtual-8086 extension */
 131 #define CPUID_AMD_EDX_DE        0x00000004      /* debugging extensions */
 132 #define CPUID_AMD_EDX_PSE       0x00000008      /* page size extensions */
 133 #define CPUID_AMD_EDX_TSC       0x00000010      /* time stamp counter */
 134 #define CPUID_AMD_EDX_MSR       0x00000020      /* rdmsr and wrmsr */
 135 #define CPUID_AMD_EDX_PAE       0x00000040      /* physical addr extension */
 136 #define CPUID_AMD_EDX_MCE       0x00000080      /* machine check exception */
 137 #define CPUID_AMD_EDX_CX8       0x00000100      /* cmpxchg8b instruction */
 138 #define CPUID_AMD_EDX_APIC      0x00000200      /* local APIC */
 139                                                 /* 0x00000400 - sysc on K6m6 */
 140 #define CPUID_AMD_EDX_SYSC      0x00000800      /* AMD: syscall and sysret */
 141 #define CPUID_AMD_EDX_MTRR      0x00001000      /* memory type and range reg */
 142 #define CPUID_AMD_EDX_PGE       0x00002000      /* page global enable */
 143 #define CPUID_AMD_EDX_MCA       0x00004000      /* machine check arch */
 144 #define CPUID_AMD_EDX_CMOV      0x00008000      /* conditional move insns */
 145 #define CPUID_AMD_EDX_PAT       0x00010000      /* K7: page attribute table */
 146 #define CPUID_AMD_EDX_FCMOV     0x00010000      /* FCMOVcc etc. */
 147 #define CPUID_AMD_EDX_PSE36     0x00020000      /* 36-bit pagesize extension */
 148                                 /* 0x00040000 - reserved */
 149                                 /* 0x00080000 - reserved */
 150 #define CPUID_AMD_EDX_NX        0x00100000      /* AMD: no-execute page prot */
 151                                 /* 0x00200000 - reserved */
 152 #define CPUID_AMD_EDX_MMXamd    0x00400000      /* AMD: MMX extensions */
 153 #define CPUID_AMD_EDX_MMX       0x00800000      /* MMX instructions */
 154 #define CPUID_AMD_EDX_FXSR      0x01000000      /* fxsave and fxrstor */
 155 #define CPUID_AMD_EDX_FFXSR     0x02000000      /* fast fxsave/fxrstor */
 156 #define CPUID_AMD_EDX_1GPG      0x04000000      /* 1GB page */
 157 #define CPUID_AMD_EDX_TSCP      0x08000000      /* rdtscp instruction */
 158                                 /* 0x10000000 - reserved */
 159 #define CPUID_AMD_EDX_LM        0x20000000      /* AMD: long mode */
 160 #define CPUID_AMD_EDX_3DNowx    0x40000000      /* AMD: extensions to 3DNow! */
 161 #define CPUID_AMD_EDX_3DNow     0x80000000      /* AMD: 3DNow! instructions */
 162 
 163 /*
 164  * AMD extended function 0x80000001 %ecx
 165  */
 166 
 167 #define CPUID_AMD_ECX_AHF64     0x00000001      /* LAHF and SAHF in long mode */
 168 #define CPUID_AMD_ECX_CMP_LGCY  0x00000002      /* AMD: multicore chip */
 169 #define CPUID_AMD_ECX_SVM       0x00000004      /* AMD: secure VM */
 170 #define CPUID_AMD_ECX_EAS       0x00000008      /* extended apic space */
 171 #define CPUID_AMD_ECX_CR8D      0x00000010      /* AMD: 32-bit mov %cr8 */
 172 #define CPUID_AMD_ECX_LZCNT     0x00000020      /* AMD: LZCNT insn */
 173 #define CPUID_AMD_ECX_SSE4A     0x00000040      /* AMD: SSE4A insns */
 174 #define CPUID_AMD_ECX_MAS       0x00000080      /* AMD: MisAlignSse mnode */
 175 #define CPUID_AMD_ECX_3DNP      0x00000100      /* AMD: 3DNowPrefectch */
 176 #define CPUID_AMD_ECX_OSVW      0x00000200      /* AMD: OSVW */
 177 #define CPUID_AMD_ECX_IBS       0x00000400      /* AMD: IBS */
 178 #define CPUID_AMD_ECX_XOP       0x00000800      /* AMD: Extended Operation */
 179 #define CPUID_AMD_ECX_SKINIT    0x00001000      /* AMD: SKINIT */
 180 #define CPUID_AMD_ECX_WDT       0x00002000      /* AMD: WDT */
 181                                 /* 0x00004000 - reserved */
 182 #define CPUID_AMD_ECX_LWP       0x00008000      /* AMD: Lightweight profiling */
 183 #define CPUID_AMD_ECX_FMA4      0x00010000      /* AMD: 4-operand FMA support */
 184                                 /* 0x00020000 - reserved */
 185                                 /* 0x00040000 - reserved */
 186 #define CPUID_AMD_ECX_NIDMSR    0x00080000      /* AMD: Node ID MSR */
 187                                 /* 0x00100000 - reserved */
 188 #define CPUID_AMD_ECX_TBM       0x00200000      /* AMD: trailing bit manips. */
 189 #define CPUID_AMD_ECX_TOPOEXT   0x00400000      /* AMD: Topology Extensions */
 190 #define CPUID_AMD_ECX_PCEC      0x00800000      /* AMD: Core ext perf counter */
 191 #define CUPID_AMD_ECX_PCENB     0x01000000      /* AMD: NB ext perf counter */
 192                                 /* 0x02000000 - reserved */
 193 #define CPUID_AMD_ECX_DBKP      0x40000000      /* AMD: Data breakpoint */
 194 #define CPUID_AMD_ECX_PERFTSC   0x08000000      /* AMD: TSC Perf Counter */
 195 #define CPUID_AMD_ECX_PERFL3    0x10000000      /* AMD: L3 Perf Counter */
 196 #define CPUID_AMD_ECX_MONITORX  0x20000000      /* AMD: clzero */
 197                                 /* 0x40000000 - reserved */
 198                                 /* 0x80000000 - reserved */
 199 
 200 /*
 201  * AMD uses %ebx for some of their features (extended function 0x80000008).
 202  */
 203 #define CPUID_AMD_EBX_CLZERO            0x000000001 /* AMD: CLZERO instr */
 204 #define CPUID_AMD_EBX_IRCMSR            0x000000002 /* AMD: Ret. instrs MSR */
 205 #define CPUID_AMD_EBX_ERR_PTR_ZERO      0x000000004 /* AMD: FP Err. Ptr. Zero */
 206 #define CPUID_AMD_EBX_IBPB              0x000001000 /* AMD: IBPB */
 207 #define CPUID_AMD_EBX_IBRS              0x000004000 /* AMD: IBRS */
 208 #define CPUID_AMD_EBX_STIBP             0x000008000 /* AMD: STIBP */
 209 #define CPUID_AMD_EBX_IBRS_ALL          0x000010000 /* AMD: Enhanced IBRS */
 210 #define CPUID_AMD_EBX_STIBP_ALL         0x000020000 /* AMD: STIBP ALL */
 211 #define CPUID_AMD_EBX_PREFER_IBRS       0x000040000 /* AMD: Don't retpoline */
 212 #define CPUID_AMD_EBX_SSBD              0x001000000 /* AMD: SSBD */
 213 #define CPUID_AMD_EBX_VIRT_SSBD         0x002000000 /* AMD: VIRT SSBD */
 214 #define CPUID_AMD_EBX_SSB_NO            0x004000000 /* AMD: SSB Fixed */
 215 
 216 /*
 217  * Intel now seems to have claimed part of the "extended" function
 218  * space that we previously for non-Intel implementors to use.
 219  * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
 220  * is available in long mode i.e. what AMD indicate using bit 0.
 221  * On the other hand, everything else is labelled as reserved.
 222  */
 223 #define CPUID_INTC_ECX_AHF64    0x00100000      /* LAHF and SAHF in long mode */
 224 
 225 /*
 226  * Intel also uses cpuid leaf 7 to have additional instructions and features.
 227  * Like some other leaves, but unlike the current ones we care about, it
 228  * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
 229  * with the potential use of additional sub-leaves in the future, we now
 230  * specifically label the EBX features with their leaf and sub-leaf.
 231  */
 232 #define CPUID_INTC_EBX_7_0_FSGSBASE     0x00000001      /* FSGSBASE */
 233 #define CPUID_INTC_EBX_7_0_TSC_ADJ      0x00000002      /* TSC adjust MSR */
 234 #define CPUID_INTC_EBX_7_0_SGX          0x00000004      /* SGX */
 235 #define CPUID_INTC_EBX_7_0_BMI1         0x00000008      /* BMI1 instrs */
 236 #define CPUID_INTC_EBX_7_0_HLE          0x00000010      /* HLE */
 237 #define CPUID_INTC_EBX_7_0_AVX2         0x00000020      /* AVX2 supported */
 238 /* Bit 6 is reserved */
 239 #define CPUID_INTC_EBX_7_0_SMEP         0x00000080      /* SMEP in CR4 */
 240 #define CPUID_INTC_EBX_7_0_BMI2         0x00000100      /* BMI2 instrs */
 241 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV  0x00000200      /* Enhanced REP MOVSB */
 242 #define CPUID_INTC_EBX_7_0_INVPCID      0x00000400      /* invpcid instr */
 243 #define CPUID_INTC_EBX_7_0_RTM          0x00000800      /* RTM instrs */
 244 #define CPUID_INTC_EBX_7_0_PQM          0x00001000      /* QoS Monitoring */
 245 #define CPUID_INTC_EBX_7_0_DEP_CSDS     0x00002000      /* Deprecates CS/DS */
 246 #define CPUID_INTC_EBX_7_0_MPX          0x00004000      /* Mem. Prot. Ext. */
 247 #define CPUID_INTC_EBX_7_0_PQE          0x00080000      /* QoS Enforcement */
 248 #define CPUID_INTC_EBX_7_0_AVX512F      0x00010000      /* AVX512 foundation */
 249 #define CPUID_INTC_EBX_7_0_AVX512DQ     0x00020000      /* AVX512DQ */
 250 #define CPUID_INTC_EBX_7_0_RDSEED       0x00040000      /* RDSEED instr */
 251 #define CPUID_INTC_EBX_7_0_ADX          0x00080000      /* ADX instrs */
 252 #define CPUID_INTC_EBX_7_0_SMAP         0x00100000      /* SMAP in CR 4 */
 253 #define CPUID_INTC_EBX_7_0_AVX512IFMA   0x00200000      /* AVX512IFMA */
 254 /* Bit 22 is reserved */
 255 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT   0x00800000      /* CLFLUSOPT */
 256 #define CPUID_INTC_EBX_7_0_CLWB         0x01000000      /* CLWB */
 257 #define CPUID_INTC_EBX_7_0_PTRACE       0x02000000      /* Processor Trace */
 258 #define CPUID_INTC_EBX_7_0_AVX512PF     0x04000000      /* AVX512PF */
 259 #define CPUID_INTC_EBX_7_0_AVX512ER     0x08000000      /* AVX512ER */
 260 #define CPUID_INTC_EBX_7_0_AVX512CD     0x10000000      /* AVX512CD */
 261 #define CPUID_INTC_EBX_7_0_SHA          0x20000000      /* SHA extensions */
 262 #define CPUID_INTC_EBX_7_0_AVX512BW     0x40000000      /* AVX512BW */
 263 #define CPUID_INTC_EBX_7_0_AVX512VL     0x80000000      /* AVX512VL */
 264 
 265 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
 266         (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
 267         CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
 268         CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
 269         CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
 270 
 271 #define CPUID_INTC_ECX_7_0_PREFETCHWT1  0x00000001      /* PREFETCHWT1 */
 272 #define CPUID_INTC_ECX_7_0_AVX512VBMI   0x00000002      /* AVX512VBMI */
 273 #define CPUID_INTC_ECX_7_0_UMIP         0x00000004      /* UMIP */
 274 #define CPUID_INTC_ECX_7_0_PKU          0x00000008      /* umode prot. keys */
 275 #define CPUID_INTC_ECX_7_0_OSPKE        0x00000010      /* OSPKE */
 276 #define CPUID_INTC_ECX_7_0_WAITPKG      0x00000020      /* WAITPKG */
 277 #define CPUID_INTC_ECX_7_0_AVX512VBMI2  0x00000040      /* AVX512 VBMI2 */
 278 /* bit 7 is reserved */
 279 #define CPUID_INTC_ECX_7_0_GFNI         0x00000100      /* GFNI */
 280 #define CPUID_INTC_ECX_7_0_VAES         0x00000200      /* VAES */
 281 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ   0x00000400      /* VPCLMULQDQ */
 282 #define CPUID_INTC_ECX_7_0_AVX512VNNI   0x00000800      /* AVX512 VNNI */
 283 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000      /* AVX512 BITALG */
 284 /* bit 13 is reserved */
 285 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000     /* AVX512 VPOPCNTDQ */
 286 /* bits 15-16 are reserved */
 287 /* bits 17-21 are the value of MAWAU */
 288 #define CPUID_INTC_ECX_7_0_RDPID        0x00400000      /* RPID, IA32_TSC_AUX */
 289 /* bits 23-24 are reserved */
 290 #define CPUID_INTC_ECX_7_0_CLDEMOTE     0x02000000      /* Cache line demote */
 291 /* bit 26 is resrved */
 292 #define CPUID_INTC_ECX_7_0_MOVDIRI      0x08000000      /* MOVDIRI insn */
 293 #define CPUID_INTC_ECX_7_0_MOVDIR64B    0x10000000      /* MOVDIR64B insn */
 294 /* bit 29 is reserved */
 295 #define CPUID_INTC_ECX_7_0_SGXLC        0x40000000      /* SGX Launch config */
 296 /* bit 31 is reserved */
 297 
 298 /*
 299  * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and
 300  * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still
 301  * valid when AVX512 is not. However, the following flags all are only valid
 302  * when AVX512 is present.
 303  */
 304 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
 305         (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \
 306         CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
 307 
 308 /* bits 0-1 are reserved */
 309 #define CPUID_INTC_EDX_7_0_AVX5124NNIW  0x00000004      /* AVX512 4NNIW */
 310 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008      /* AVX512 4FMAPS */
 311 #define CPUID_INTC_EDX_7_0_FSREPMOV     0x00000010      /* fast short rep mov */
 312 /* bits 5-17 are resreved */
 313 #define CPUID_INTC_EDX_7_0_PCONFIG      0x00040000      /* PCONFIG */
 314 /* bits 19-26 are reserved */
 315 #define CPUID_INTC_EDX_7_0_SPEC_CTRL    0x04000000      /* Spec, IBPB, IBRS */
 316 #define CPUID_INTC_EDX_7_0_STIBP        0x08000000      /* STIBP */
 317 #define CPUID_INTC_EDX_7_0_FLUSH_CMD    0x10000000      /* IA32_FLUSH_CMD */
 318 #define CPUID_INTC_EDX_7_0_ARCH_CAPS    0x20000000      /* IA32_ARCH_CAPS */
 319 #define CPUID_INTC_EDX_7_0_SSBD         0x80000000      /* SSBD */
 320 
 321 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
 322         (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
 323 
 324 /*
 325  * Intel also uses cpuid leaf 0xd to report additional instructions and features
 326  * when the sub-leaf in %ecx == 1. We label these using the same convention as
 327  * with leaf 7.
 328  */
 329 #define CPUID_INTC_EAX_D_1_XSAVEOPT     0x00000001      /* xsaveopt inst. */
 330 #define CPUID_INTC_EAX_D_1_XSAVEC       0x00000002      /* xsavec inst. */
 331 #define CPUID_INTC_EAX_D_1_XSAVES       0x00000008      /* xsaves inst. */
 332 
 333 #define REG_PAT                 0x277
 334 #define REG_TSC                 0x10    /* timestamp counter */
 335 #define REG_APIC_BASE_MSR       0x1b
 336 #define REG_X2APIC_BASE_MSR     0x800   /* The MSR address offset of x2APIC */
 337 
 338 #if !defined(__xpv)
 339 /*
 340  * AMD C1E
 341  */
 342 #define MSR_AMD_INT_PENDING_CMP_HALT    0xC0010055
 343 #define AMD_ACTONCMPHALT_SHIFT  27
 344 #define AMD_ACTONCMPHALT_MASK   3
 345 #endif
 346 
 347 #define MSR_DEBUGCTL            0x1d9
 348 
 349 #define DEBUGCTL_LBR            0x01
 350 #define DEBUGCTL_BTF            0x02
 351 
 352 /* Intel P6, AMD */
 353 #define MSR_LBR_FROM            0x1db
 354 #define MSR_LBR_TO              0x1dc
 355 #define MSR_LEX_FROM            0x1dd
 356 #define MSR_LEX_TO              0x1de
 357 
 358 /* Intel P4 (pre-Prescott, non P4 M) */
 359 #define MSR_P4_LBSTK_TOS        0x1da
 360 #define MSR_P4_LBSTK_0          0x1db
 361 #define MSR_P4_LBSTK_1          0x1dc
 362 #define MSR_P4_LBSTK_2          0x1dd
 363 #define MSR_P4_LBSTK_3          0x1de
 364 
 365 /* Intel Pentium M */
 366 #define MSR_P6M_LBSTK_TOS       0x1c9
 367 #define MSR_P6M_LBSTK_0         0x040
 368 #define MSR_P6M_LBSTK_1         0x041
 369 #define MSR_P6M_LBSTK_2         0x042
 370 #define MSR_P6M_LBSTK_3         0x043
 371 #define MSR_P6M_LBSTK_4         0x044
 372 #define MSR_P6M_LBSTK_5         0x045
 373 #define MSR_P6M_LBSTK_6         0x046
 374 #define MSR_P6M_LBSTK_7         0x047
 375 
 376 /* Intel P4 (Prescott) */
 377 #define MSR_PRP4_LBSTK_TOS      0x1da
 378 #define MSR_PRP4_LBSTK_FROM_0   0x680
 379 #define MSR_PRP4_LBSTK_FROM_1   0x681
 380 #define MSR_PRP4_LBSTK_FROM_2   0x682
 381 #define MSR_PRP4_LBSTK_FROM_3   0x683
 382 #define MSR_PRP4_LBSTK_FROM_4   0x684
 383 #define MSR_PRP4_LBSTK_FROM_5   0x685
 384 #define MSR_PRP4_LBSTK_FROM_6   0x686
 385 #define MSR_PRP4_LBSTK_FROM_7   0x687
 386 #define MSR_PRP4_LBSTK_FROM_8   0x688
 387 #define MSR_PRP4_LBSTK_FROM_9   0x689
 388 #define MSR_PRP4_LBSTK_FROM_10  0x68a
 389 #define MSR_PRP4_LBSTK_FROM_11  0x68b
 390 #define MSR_PRP4_LBSTK_FROM_12  0x68c
 391 #define MSR_PRP4_LBSTK_FROM_13  0x68d
 392 #define MSR_PRP4_LBSTK_FROM_14  0x68e
 393 #define MSR_PRP4_LBSTK_FROM_15  0x68f
 394 #define MSR_PRP4_LBSTK_TO_0     0x6c0
 395 #define MSR_PRP4_LBSTK_TO_1     0x6c1
 396 #define MSR_PRP4_LBSTK_TO_2     0x6c2
 397 #define MSR_PRP4_LBSTK_TO_3     0x6c3
 398 #define MSR_PRP4_LBSTK_TO_4     0x6c4
 399 #define MSR_PRP4_LBSTK_TO_5     0x6c5
 400 #define MSR_PRP4_LBSTK_TO_6     0x6c6
 401 #define MSR_PRP4_LBSTK_TO_7     0x6c7
 402 #define MSR_PRP4_LBSTK_TO_8     0x6c8
 403 #define MSR_PRP4_LBSTK_TO_9     0x6c9
 404 #define MSR_PRP4_LBSTK_TO_10    0x6ca
 405 #define MSR_PRP4_LBSTK_TO_11    0x6cb
 406 #define MSR_PRP4_LBSTK_TO_12    0x6cc
 407 #define MSR_PRP4_LBSTK_TO_13    0x6cd
 408 #define MSR_PRP4_LBSTK_TO_14    0x6ce
 409 #define MSR_PRP4_LBSTK_TO_15    0x6cf
 410 
 411 /*
 412  * General Xeon based MSRs
 413  */
 414 #define MSR_PPIN_CTL            0x04e
 415 #define MSR_PPIN                0x04f
 416 #define MSR_PLATFORM_INFO       0x0ce
 417 
 418 #define MSR_PLATFORM_INFO_PPIN  (1 << 23)
 419 #define MSR_PPIN_CTL_MASK       0x03
 420 #define MSR_PPIN_CTL_LOCKED     0x01
 421 #define MSR_PPIN_CTL_ENABLED    0x02
 422 
 423 /*
 424  * Intel IA32_ARCH_CAPABILITIES MSR.
 425  */
 426 #define MSR_IA32_ARCH_CAPABILITIES              0x10a
 427 #define IA32_ARCH_CAP_RDCL_NO                   0x0001
 428 #define IA32_ARCH_CAP_IBRS_ALL                  0x0002
 429 #define IA32_ARCH_CAP_RSBA                      0x0004
 430 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY        0x0008
 431 #define IA32_ARCH_CAP_SSB_NO                    0x0010
 432 
 433 /*
 434  * Intel Speculation related MSRs
 435  */
 436 #define MSR_IA32_SPEC_CTRL      0x48
 437 #define IA32_SPEC_CTRL_IBRS     0x01
 438 #define IA32_SPEC_CTRL_STIBP    0x02
 439 #define IA32_SPEC_CTRL_SSBD     0x04
 440 
 441 #define MSR_IA32_PRED_CMD       0x49
 442 #define IA32_PRED_CMD_IBPB      0x01
 443 
 444 #define MSR_IA32_FLUSH_CMD      0x10b
 445 #define IA32_FLUSH_CMD_L1D      0x01
 446 
 447 #define MCI_CTL_VALUE           0xffffffff
 448 
 449 #define MTRR_TYPE_UC            0
 450 #define MTRR_TYPE_WC            1
 451 #define MTRR_TYPE_WT            4
 452 #define MTRR_TYPE_WP            5
 453 #define MTRR_TYPE_WB            6
 454 #define MTRR_TYPE_UC_           7
 455 
 456 /*
 457  * For Solaris we set up the page attritubute table in the following way:
 458  * PAT0 Write-Back
 459  * PAT1 Write-Through
 460  * PAT2 Unchacheable-
 461  * PAT3 Uncacheable
 462  * PAT4 Write-Back
 463  * PAT5 Write-Through
 464  * PAT6 Write-Combine
 465  * PAT7 Uncacheable
 466  * The only difference from h/w default is entry 6.
 467  */
 468 #define PAT_DEFAULT_ATTRIBUTE                   \
 469         ((uint64_t)MTRR_TYPE_WB |               \
 470         ((uint64_t)MTRR_TYPE_WT << 8) |           \
 471         ((uint64_t)MTRR_TYPE_UC_ << 16) | \
 472         ((uint64_t)MTRR_TYPE_UC << 24) |  \
 473         ((uint64_t)MTRR_TYPE_WB << 32) |  \
 474         ((uint64_t)MTRR_TYPE_WT << 40) |  \
 475         ((uint64_t)MTRR_TYPE_WC << 48) |  \
 476         ((uint64_t)MTRR_TYPE_UC << 56))
 477 
 478 #define X86FSET_LARGEPAGE       0
 479 #define X86FSET_TSC             1
 480 #define X86FSET_MSR             2
 481 #define X86FSET_MTRR            3
 482 #define X86FSET_PGE             4
 483 #define X86FSET_DE              5
 484 #define X86FSET_CMOV            6
 485 #define X86FSET_MMX             7
 486 #define X86FSET_MCA             8
 487 #define X86FSET_PAE             9
 488 #define X86FSET_CX8             10
 489 #define X86FSET_PAT             11
 490 #define X86FSET_SEP             12
 491 #define X86FSET_SSE             13
 492 #define X86FSET_SSE2            14
 493 #define X86FSET_HTT             15
 494 #define X86FSET_ASYSC           16
 495 #define X86FSET_NX              17
 496 #define X86FSET_SSE3            18
 497 #define X86FSET_CX16            19
 498 #define X86FSET_CMP             20
 499 #define X86FSET_TSCP            21
 500 #define X86FSET_MWAIT           22
 501 #define X86FSET_SSE4A           23
 502 #define X86FSET_CPUID           24
 503 #define X86FSET_SSSE3           25
 504 #define X86FSET_SSE4_1          26
 505 #define X86FSET_SSE4_2          27
 506 #define X86FSET_1GPG            28
 507 #define X86FSET_CLFSH           29
 508 #define X86FSET_64              30
 509 #define X86FSET_AES             31
 510 #define X86FSET_PCLMULQDQ       32
 511 #define X86FSET_XSAVE           33
 512 #define X86FSET_AVX             34
 513 #define X86FSET_VMX             35
 514 #define X86FSET_SVM             36
 515 #define X86FSET_TOPOEXT         37
 516 #define X86FSET_F16C            38
 517 #define X86FSET_RDRAND          39
 518 #define X86FSET_X2APIC          40
 519 #define X86FSET_AVX2            41
 520 #define X86FSET_BMI1            42
 521 #define X86FSET_BMI2            43
 522 #define X86FSET_FMA             44
 523 #define X86FSET_SMEP            45
 524 #define X86FSET_SMAP            46
 525 #define X86FSET_ADX             47
 526 #define X86FSET_RDSEED          48
 527 #define X86FSET_MPX             49
 528 #define X86FSET_AVX512F         50
 529 #define X86FSET_AVX512DQ        51
 530 #define X86FSET_AVX512PF        52
 531 #define X86FSET_AVX512ER        53
 532 #define X86FSET_AVX512CD        54
 533 #define X86FSET_AVX512BW        55
 534 #define X86FSET_AVX512VL        56
 535 #define X86FSET_AVX512FMA       57
 536 #define X86FSET_AVX512VBMI      58
 537 #define X86FSET_AVX512VPOPCDQ   59
 538 #define X86FSET_AVX512NNIW      60
 539 #define X86FSET_AVX512FMAPS     61
 540 #define X86FSET_XSAVEOPT        62
 541 #define X86FSET_XSAVEC          63
 542 #define X86FSET_XSAVES          64
 543 #define X86FSET_SHA             65
 544 #define X86FSET_UMIP            66
 545 #define X86FSET_PKU             67
 546 #define X86FSET_OSPKE           68
 547 #define X86FSET_PCID            69
 548 #define X86FSET_INVPCID         70
 549 #define X86FSET_IBRS            71
 550 #define X86FSET_IBPB            72
 551 #define X86FSET_STIBP           73
 552 #define X86FSET_SSBD            74
 553 #define X86FSET_SSBD_VIRT       75
 554 #define X86FSET_RDCL_NO         76
 555 #define X86FSET_IBRS_ALL        77
 556 #define X86FSET_RSBA            78
 557 #define X86FSET_SSB_NO          79
 558 #define X86FSET_STIBP_ALL       80
 559 #define X86FSET_FLUSH_CMD       81
 560 #define X86FSET_L1D_VM_NO       82
 561 #define X86FSET_FSGSBASE        83
 562 #define X86FSET_CLFLUSHOPT      84
 563 #define X86FSET_CLWB            85
 564 #define X86FSET_MONITORX        86
 565 #define X86FSET_CLZERO          87
 566 #define X86FSET_XOP             88
 567 #define X86FSET_FMA4            89
 568 #define X86FSET_TBM             90
 569 #define X86FSET_AVX512VNNI      91
 570 #define X86FSET_AMD_PCEC        92
 571 
 572 /*
 573  * Intel Deep C-State invariant TSC in leaf 0x80000007.
 574  */
 575 #define CPUID_TSC_CSTATE_INVARIANCE     (0x100)
 576 
 577 /*
 578  * Intel Deep C-state always-running local APIC timer
 579  */
 580 #define CPUID_CSTATE_ARAT       (0x4)
 581 
 582 /*
 583  * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
 584  */
 585 #define CPUID_EPB_SUPPORT       (1 << 3)
 586 
 587 /*
 588  * Intel TSC deadline timer
 589  */
 590 #define CPUID_DEADLINE_TSC      (1 << 24)
 591 
 592 /*
 593  * x86_type is a legacy concept; this is supplanted
 594  * for most purposes by x86_featureset; modern CPUs
 595  * should be X86_TYPE_OTHER
 596  */
 597 #define X86_TYPE_OTHER          0
 598 #define X86_TYPE_486            1
 599 #define X86_TYPE_P5             2
 600 #define X86_TYPE_P6             3
 601 #define X86_TYPE_CYRIX_486      4
 602 #define X86_TYPE_CYRIX_6x86L    5
 603 #define X86_TYPE_CYRIX_6x86     6
 604 #define X86_TYPE_CYRIX_GXm      7
 605 #define X86_TYPE_CYRIX_6x86MX   8
 606 #define X86_TYPE_CYRIX_MediaGX  9
 607 #define X86_TYPE_CYRIX_MII      10
 608 #define X86_TYPE_VIA_CYRIX_III  11
 609 #define X86_TYPE_P4             12
 610 
 611 /*
 612  * x86_vendor allows us to select between
 613  * implementation features and helps guide
 614  * the interpretation of the cpuid instruction.
 615  */
 616 #define X86_VENDOR_Intel        0
 617 #define X86_VENDORSTR_Intel     "GenuineIntel"
 618 
 619 #define X86_VENDOR_IntelClone   1
 620 
 621 #define X86_VENDOR_AMD          2
 622 #define X86_VENDORSTR_AMD       "AuthenticAMD"
 623 
 624 #define X86_VENDOR_Cyrix        3
 625 #define X86_VENDORSTR_CYRIX     "CyrixInstead"
 626 
 627 #define X86_VENDOR_UMC          4
 628 #define X86_VENDORSTR_UMC       "UMC UMC UMC "
 629 
 630 #define X86_VENDOR_NexGen       5
 631 #define X86_VENDORSTR_NexGen    "NexGenDriven"
 632 
 633 #define X86_VENDOR_Centaur      6
 634 #define X86_VENDORSTR_Centaur   "CentaurHauls"
 635 
 636 #define X86_VENDOR_Rise         7
 637 #define X86_VENDORSTR_Rise      "RiseRiseRise"
 638 
 639 #define X86_VENDOR_SiS          8
 640 #define X86_VENDORSTR_SiS       "SiS SiS SiS "
 641 
 642 #define X86_VENDOR_TM           9
 643 #define X86_VENDORSTR_TM        "GenuineTMx86"
 644 
 645 #define X86_VENDOR_NSC          10
 646 #define X86_VENDORSTR_NSC       "Geode by NSC"
 647 
 648 /*
 649  * Vendor string max len + \0
 650  */
 651 #define X86_VENDOR_STRLEN       13
 652 
 653 /*
 654  * Some vendor/family/model/stepping ranges are commonly grouped under
 655  * a single identifying banner by the vendor.  The following encode
 656  * that "revision" in a uint32_t with the 8 most significant bits
 657  * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
 658  * family, and the remaining 16 typically forming a bitmask of revisions
 659  * within that family with more significant bits indicating "later" revisions.
 660  */
 661 
 662 #define _X86_CHIPREV_VENDOR_MASK        0xff000000u
 663 #define _X86_CHIPREV_VENDOR_SHIFT       24
 664 #define _X86_CHIPREV_FAMILY_MASK        0x00ff0000u
 665 #define _X86_CHIPREV_FAMILY_SHIFT       16
 666 #define _X86_CHIPREV_REV_MASK           0x0000ffffu
 667 
 668 #define _X86_CHIPREV_VENDOR(x) \
 669         (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
 670 #define _X86_CHIPREV_FAMILY(x) \
 671         (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
 672 #define _X86_CHIPREV_REV(x) \
 673         ((x) & _X86_CHIPREV_REV_MASK)
 674 
 675 /* True if x matches in vendor and family and if x matches the given rev mask */
 676 #define X86_CHIPREV_MATCH(x, mask) \
 677         (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
 678         _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
 679         ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
 680 
 681 /* True if x matches in vendor and family, and rev is at least minx */
 682 #define X86_CHIPREV_ATLEAST(x, minx) \
 683         (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
 684         _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
 685         _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
 686 
 687 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
 688         ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
 689         (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
 690 
 691 /* True if x matches in vendor, and family is at least minx */
 692 #define X86_CHIPFAM_ATLEAST(x, minx) \
 693         (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
 694         _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
 695 
 696 /* Revision default */
 697 #define X86_CHIPREV_UNKNOWN     0x0
 698 
 699 /*
 700  * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
 701  * sufficiently different that we will distinguish them; in all other
 702  * case we will identify the major revision.
 703  */
 704 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
 705 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
 706 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
 707 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
 708 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
 709 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
 710 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
 711 
 712 /*
 713  * Definitions for AMD Family 0x10.  Rev A was Engineering Samples only.
 714  */
 715 #define X86_CHIPREV_AMD_10_REV_A \
 716         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
 717 #define X86_CHIPREV_AMD_10_REV_B \
 718         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
 719 #define X86_CHIPREV_AMD_10_REV_C2 \
 720         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
 721 #define X86_CHIPREV_AMD_10_REV_C3 \
 722         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
 723 #define X86_CHIPREV_AMD_10_REV_D0 \
 724         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
 725 #define X86_CHIPREV_AMD_10_REV_D1 \
 726         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
 727 #define X86_CHIPREV_AMD_10_REV_E \
 728         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
 729 
 730 /*
 731  * Definitions for AMD Family 0x11.
 732  */
 733 #define X86_CHIPREV_AMD_11_REV_B \
 734         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
 735 
 736 /*
 737  * Definitions for AMD Family 0x12.
 738  */
 739 #define X86_CHIPREV_AMD_12_REV_B \
 740         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
 741 
 742 /*
 743  * Definitions for AMD Family 0x14.
 744  */
 745 #define X86_CHIPREV_AMD_14_REV_B \
 746         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
 747 #define X86_CHIPREV_AMD_14_REV_C \
 748         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
 749 
 750 /*
 751  * Definitions for AMD Family 0x15
 752  */
 753 #define X86_CHIPREV_AMD_15OR_REV_B2 \
 754         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
 755 
 756 #define X86_CHIPREV_AMD_15TN_REV_A1 \
 757         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
 758 
 759 #define X86_CHIPREV_AMD_150R_REV_C0 \
 760         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0003)
 761 
 762 #define X86_CHIPREV_AMD_15KV_REV_A1 \
 763         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0004)
 764 
 765 #define X86_CHIPREV_AMD_15F60 \
 766         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0005)
 767 
 768 #define X86_CHIPREV_AMD_15ST_REV_A0 \
 769         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0006)
 770 
 771 /*
 772  * Definitions for AMD Family 0x16
 773  */
 774 #define X86_CHIPREV_AMD_16_KB_A1 \
 775         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0001)
 776 
 777 #define X86_CHIPREV_AMD_16_ML_A1 \
 778         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0002)
 779 
 780 /*
 781  * Definitions for AMD Family 0x17
 782  */
 783 
 784 #define X86_CHIPREV_AMD_17_ZP_B1 \
 785         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0001)
 786 
 787 #define X86_CHIPREV_AMD_17_ZP_B2 \
 788         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0002)
 789 
 790 #define X86_CHIPREV_AMD_17_PiR_B2 \
 791         _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0003)
 792 
 793 /*
 794  * Various socket/package types, extended as the need to distinguish
 795  * a new type arises.  The top 8 byte identfies the vendor and the
 796  * remaining 24 bits describe 24 socket types.
 797  */
 798 
 799 #define _X86_SOCKET_VENDOR_SHIFT        24
 800 #define _X86_SOCKET_VENDOR(x)   ((x) >> _X86_SOCKET_VENDOR_SHIFT)
 801 #define _X86_SOCKET_TYPE_MASK   0x00ffffff
 802 #define _X86_SOCKET_TYPE(x)             ((x) & _X86_SOCKET_TYPE_MASK)
 803 
 804 #define _X86_SOCKET_MKVAL(vendor, bitval) \
 805         ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
 806 
 807 #define X86_SOCKET_MATCH(s, mask) \
 808         (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
 809         (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
 810 
 811 #define X86_SOCKET_UNKNOWN 0x0
 812         /*
 813          * AMD socket types
 814          */
 815 #define X86_SOCKET_754          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01)
 816 #define X86_SOCKET_939          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02)
 817 #define X86_SOCKET_940          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03)
 818 #define X86_SOCKET_S1g1         _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04)
 819 #define X86_SOCKET_AM2          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05)
 820 #define X86_SOCKET_F1207        _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06)
 821 #define X86_SOCKET_S1g2         _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07)
 822 #define X86_SOCKET_S1g3         _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08)
 823 #define X86_SOCKET_AM           _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09)
 824 #define X86_SOCKET_AM2R2        _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a)
 825 #define X86_SOCKET_AM3          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b)
 826 #define X86_SOCKET_G34          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c)
 827 #define X86_SOCKET_ASB2         _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d)
 828 #define X86_SOCKET_C32          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e)
 829 #define X86_SOCKET_S1g4         _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f)
 830 #define X86_SOCKET_FT1          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10)
 831 #define X86_SOCKET_FM1          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11)
 832 #define X86_SOCKET_FS1          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12)
 833 #define X86_SOCKET_AM3R2        _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13)
 834 #define X86_SOCKET_FP2          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14)
 835 #define X86_SOCKET_FS1R2        _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15)
 836 #define X86_SOCKET_FM2          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16)
 837 #define X86_SOCKET_FP3          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17)
 838 #define X86_SOCKET_FM2R2        _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18)
 839 #define X86_SOCKET_FP4          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19)
 840 #define X86_SOCKET_AM4          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a)
 841 #define X86_SOCKET_FT3          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b)
 842 #define X86_SOCKET_FT4          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c)
 843 #define X86_SOCKET_FS1B         _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d)
 844 #define X86_SOCKET_FT3B         _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e)
 845 #define X86_SOCKET_SP3          _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f)
 846 #define X86_SOCKET_SP3R2        _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20)
 847 #define X86_NUM_SOCKETS_AMD     0x21
 848 
 849 
 850 /*
 851  * Definitions for Intel processor models. These are all for Family 6
 852  * processors. This list and the Atom set below it are not exhuastive.
 853  */
 854 #define INTC_MODEL_MEROM                0x0f
 855 #define INTC_MODEL_PENRYN               0x17
 856 #define INTC_MODEL_DUNNINGTON           0x1d
 857 
 858 #define INTC_MODEL_NEHALEM              0x1e
 859 #define INTC_MODEL_NEHALEM2             0x1f
 860 #define INTC_MODEL_NEHALEM_EP           0x1a
 861 #define INTC_MODEL_NEHALEM_EX           0x2e
 862 
 863 #define INTC_MODEL_WESTMERE             0x25
 864 #define INTC_MODEL_WESTMERE_EP          0x2c
 865 #define INTC_MODEL_WESTMERE_EX          0x2f
 866 
 867 #define INTC_MODEL_SANDYBRIDGE          0x2a
 868 #define INTC_MODEL_SANDYBRIDGE_XEON     0x2d
 869 #define INTC_MODEL_IVYBRIDGE            0x3a
 870 #define INTC_MODEL_IVYBRIDGE_XEON       0x3e
 871 
 872 #define INTC_MODEL_HASWELL              0x3c
 873 #define INTC_MODEL_HASWELL_ULT          0x45
 874 #define INTC_MODEL_HASWELL_GT3E         0x46
 875 #define INTC_MODEL_HASWELL_XEON         0x3f
 876 
 877 #define INTC_MODEL_BROADWELL            0x3d
 878 #define INTC_MODEL_BROADELL_2           0x47
 879 #define INTC_MODEL_BROADWELL_XEON       0x4f
 880 #define INTC_MODEL_BROADWELL_XEON_D     0x56
 881 
 882 #define INCC_MODEL_SKYLAKE_MOBILE       0x4e
 883 #define INTC_MODEL_SKYLAKE_XEON         0x55
 884 #define INTC_MODEL_SKYLAKE_DESKTOP      0x5e
 885 
 886 #define INTC_MODEL_KABYLAKE_MOBILE      0x8e
 887 #define INTC_MODEL_KABYLAKE_DESKTOP     0x9e
 888 
 889 /*
 890  * Atom Processors
 891  */
 892 #define INTC_MODEL_SILVERTHORNE         0x1c
 893 #define INTC_MODEL_LINCROFT             0x26
 894 #define INTC_MODEL_PENWELL              0x27
 895 #define INTC_MODEL_CLOVERVIEW           0x35
 896 #define INTC_MODEL_CEDARVIEW            0x36
 897 #define INTC_MODEL_BAY_TRAIL            0x37
 898 #define INTC_MODEL_AVATON               0x4d
 899 #define INTC_MODEL_AIRMONT              0x4c
 900 #define INTC_MODEL_GOLDMONT             0x5c
 901 #define INTC_MODEL_DENVERTON            0x5f
 902 #define INTC_MODEL_GEMINI_LAKE          0x7a
 903 
 904 /*
 905  * xgetbv/xsetbv support
 906  * See section 13.3 in vol. 1 of the Intel devlopers manual.
 907  */
 908 
 909 #define XFEATURE_ENABLED_MASK   0x0
 910 /*
 911  * XFEATURE_ENABLED_MASK values (eax)
 912  * See setup_xfem().
 913  */
 914 #define XFEATURE_LEGACY_FP      0x1
 915 #define XFEATURE_SSE            0x2
 916 #define XFEATURE_AVX            0x4
 917 #define XFEATURE_MPX            0x18    /* 2 bits, both 0 or 1 */
 918 #define XFEATURE_AVX512         0xe0    /* 3 bits, all 0 or 1 */
 919         /* bit 8 unused */
 920 #define XFEATURE_PKRU           0x200
 921 #define XFEATURE_FP_ALL \
 922         (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
 923         XFEATURE_AVX512 | XFEATURE_PKRU)
 924 
 925 /*
 926  * Define the set of xfeature flags that should be considered valid in the xsave
 927  * state vector when we initialize an lwp. This is distinct from the full set so
 928  * that all of the processor's normal logic and tracking of the xsave state is
 929  * usable. This should correspond to the state that's been initialized by the
 930  * ABI to hold meaningful values. Adding additional bits here can have serious
 931  * performance implications and cause performance degradations when using the
 932  * FPU vector (xmm) registers.
 933  */
 934 #define XFEATURE_FP_INITIAL     (XFEATURE_LEGACY_FP | XFEATURE_SSE)
 935 
 936 #if !defined(_ASM)
 937 
 938 #if defined(_KERNEL) || defined(_KMEMUSER)
 939 
 940 #define NUM_X86_FEATURES        93
 941 extern uchar_t x86_featureset[];
 942 
 943 extern void free_x86_featureset(void *featureset);
 944 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
 945 extern void add_x86_feature(void *featureset, uint_t feature);
 946 extern void remove_x86_feature(void *featureset, uint_t feature);
 947 extern boolean_t compare_x86_featureset(void *setA, void *setB);
 948 extern void print_x86_featureset(void *featureset);
 949 
 950 
 951 extern uint_t x86_type;
 952 extern uint_t x86_vendor;
 953 extern uint_t x86_clflush_size;
 954 
 955 extern uint_t pentiumpro_bug4046376;
 956 
 957 extern const char CyrixInstead[];
 958 
 959 extern void (*spec_l1d_flush)(void);
 960 
 961 #endif
 962 
 963 #if defined(_KERNEL)
 964 
 965 /*
 966  * This structure is used to pass arguments and get return values back
 967  * from the CPUID instruction in __cpuid_insn() routine.
 968  */
 969 struct cpuid_regs {
 970         uint32_t        cp_eax;
 971         uint32_t        cp_ebx;
 972         uint32_t        cp_ecx;
 973         uint32_t        cp_edx;
 974 };
 975 
 976 extern int x86_use_pcid;
 977 extern int x86_use_invpcid;
 978 
 979 /*
 980  * Utility functions to get/set extended control registers (XCR)
 981  * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
 982  */
 983 extern uint64_t get_xcr(uint_t);
 984 extern void set_xcr(uint_t, uint64_t);
 985 
 986 extern uint64_t rdmsr(uint_t);
 987 extern void wrmsr(uint_t, const uint64_t);
 988 extern uint64_t xrdmsr(uint_t);
 989 extern void xwrmsr(uint_t, const uint64_t);
 990 extern int checked_rdmsr(uint_t, uint64_t *);
 991 extern int checked_wrmsr(uint_t, uint64_t);
 992 
 993 extern void invalidate_cache(void);
 994 extern ulong_t getcr4(void);
 995 extern void setcr4(ulong_t);
 996 
 997 extern void mtrr_sync(void);
 998 
 999 extern void cpu_fast_syscall_enable(void);
1000 extern void cpu_fast_syscall_disable(void);
1001 
1002 struct cpu;
1003 
1004 extern int cpuid_checkpass(struct cpu *, int);
1005 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
1006 extern uint32_t __cpuid_insn(struct cpuid_regs *);
1007 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
1008 extern int cpuid_getidstr(struct cpu *, char *, size_t);
1009 extern const char *cpuid_getvendorstr(struct cpu *);
1010 extern uint_t cpuid_getvendor(struct cpu *);
1011 extern uint_t cpuid_getfamily(struct cpu *);
1012 extern uint_t cpuid_getmodel(struct cpu *);
1013 extern uint_t cpuid_getstep(struct cpu *);
1014 extern uint_t cpuid_getsig(struct cpu *);
1015 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
1016 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
1017 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
1018 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
1019 extern int cpuid_get_chipid(struct cpu *);
1020 extern id_t cpuid_get_coreid(struct cpu *);
1021 extern int cpuid_get_pkgcoreid(struct cpu *);
1022 extern int cpuid_get_clogid(struct cpu *);
1023 extern int cpuid_get_cacheid(struct cpu *);
1024 extern uint32_t cpuid_get_apicid(struct cpu *);
1025 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
1026 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
1027 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
1028 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
1029 extern size_t cpuid_get_xsave_size();
1030 extern boolean_t cpuid_need_fp_excp_handling();
1031 extern int cpuid_is_cmt(struct cpu *);
1032 extern int cpuid_syscall32_insn(struct cpu *);
1033 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
1034 
1035 extern uint32_t cpuid_getchiprev(struct cpu *);
1036 extern const char *cpuid_getchiprevstr(struct cpu *);
1037 extern uint32_t cpuid_getsockettype(struct cpu *);
1038 extern const char *cpuid_getsocketstr(struct cpu *);
1039 
1040 extern int cpuid_have_cr8access(struct cpu *);
1041 
1042 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
1043 
1044 struct cpuid_info;
1045 
1046 extern void setx86isalist(void);
1047 extern void cpuid_alloc_space(struct cpu *);
1048 extern void cpuid_free_space(struct cpu *);
1049 extern void cpuid_pass1(struct cpu *, uchar_t *);
1050 extern void cpuid_pass2(struct cpu *);
1051 extern void cpuid_pass3(struct cpu *);
1052 extern void cpuid_pass4(struct cpu *, uint_t *);
1053 extern void cpuid_set_cpu_properties(void *, processorid_t,
1054     struct cpuid_info *);
1055 extern void cpuid_pass_ucode(struct cpu *, uchar_t *);
1056 extern void cpuid_post_ucodeadm(void);
1057 
1058 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
1059 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
1060 
1061 #if !defined(__xpv)
1062 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
1063 extern void cpuid_mwait_free(struct cpu *);
1064 extern int cpuid_deep_cstates_supported(void);
1065 extern int cpuid_arat_supported(void);
1066 extern int cpuid_iepb_supported(struct cpu *);
1067 extern int cpuid_deadline_tsc_supported(void);
1068 extern void vmware_port(int, uint32_t *);
1069 #endif
1070 
1071 struct cpu_ucode_info;
1072 
1073 extern void ucode_alloc_space(struct cpu *);
1074 extern void ucode_free_space(struct cpu *);
1075 extern void ucode_check(struct cpu *);
1076 extern void ucode_cleanup();
1077 
1078 #if !defined(__xpv)
1079 extern  char _tsc_mfence_start;
1080 extern  char _tsc_mfence_end;
1081 extern  char _tscp_start;
1082 extern  char _tscp_end;
1083 extern  char _no_rdtsc_start;
1084 extern  char _no_rdtsc_end;
1085 extern  char _tsc_lfence_start;
1086 extern  char _tsc_lfence_end;
1087 #endif
1088 
1089 #if !defined(__xpv)
1090 extern  char bcopy_patch_start;
1091 extern  char bcopy_patch_end;
1092 extern  char bcopy_ck_size;
1093 #endif
1094 
1095 extern void post_startup_cpu_fixups(void);
1096 
1097 extern uint_t workaround_errata(struct cpu *);
1098 
1099 #if defined(OPTERON_ERRATUM_93)
1100 extern int opteron_erratum_93;
1101 #endif
1102 
1103 #if defined(OPTERON_ERRATUM_91)
1104 extern int opteron_erratum_91;
1105 #endif
1106 
1107 #if defined(OPTERON_ERRATUM_100)
1108 extern int opteron_erratum_100;
1109 #endif
1110 
1111 #if defined(OPTERON_ERRATUM_121)
1112 extern int opteron_erratum_121;
1113 #endif
1114 
1115 #if defined(OPTERON_WORKAROUND_6323525)
1116 extern int opteron_workaround_6323525;
1117 extern void patch_workaround_6323525(void);
1118 #endif
1119 
1120 #if !defined(__xpv)
1121 extern void determine_platform(void);
1122 #endif
1123 extern int get_hwenv(void);
1124 extern int is_controldom(void);
1125 
1126 extern void enable_pcid(void);
1127 
1128 extern void xsave_setup_msr(struct cpu *);
1129 
1130 #if !defined(__xpv)
1131 extern void reset_gdtr_limit(void);
1132 #endif
1133 
1134 /*
1135  * Hypervisor signatures
1136  */
1137 #define HVSIG_XEN_HVM   "XenVMMXenVMM"
1138 #define HVSIG_VMWARE    "VMwareVMware"
1139 #define HVSIG_KVM       "KVMKVMKVM"
1140 #define HVSIG_MICROSOFT "Microsoft Hv"
1141 #define HVSIG_BHYVE     "bhyve bhyve "
1142 
1143 /*
1144  * Defined hardware environments
1145  */
1146 #define HW_NATIVE       (1 << 0)  /* Running on bare metal */
1147 #define HW_XEN_PV       (1 << 1)  /* Running on Xen PVM */
1148 
1149 #define HW_XEN_HVM      (1 << 2)  /* Running on Xen HVM */
1150 #define HW_VMWARE       (1 << 3)  /* Running on VMware hypervisor */
1151 #define HW_KVM          (1 << 4)  /* Running on KVM hypervisor */
1152 #define HW_MICROSOFT    (1 << 5)  /* Running on Microsoft hypervisor */
1153 #define HW_BHYVE        (1 << 6)  /* Running on bhyve hypervisor */
1154 
1155 #define HW_VIRTUAL      (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \
1156             HW_BHYVE)
1157 
1158 #endif  /* _KERNEL */
1159 
1160 #endif  /* !_ASM */
1161 
1162 /*
1163  * VMware hypervisor related defines
1164  */
1165 #define VMWARE_HVMAGIC          0x564d5868
1166 #define VMWARE_HVPORT           0x5658
1167 #define VMWARE_HVCMD_GETVERSION 0x0a
1168 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
1169 
1170 #ifdef  __cplusplus
1171 }
1172 #endif
1173 
1174 #endif  /* _SYS_X86_ARCHEXT_H */