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10686 Debug macros causes smatch issues
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--- old/usr/src/uts/common/sys/pcie_impl.h
+++ new/usr/src/uts/common/sys/pcie_impl.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 +/*
26 + * Copyright 2019, Joyent, Inc.
27 + */
28 +
25 29 #ifndef _SYS_PCIE_IMPL_H
26 30 #define _SYS_PCIE_IMPL_H
27 31
28 32 #ifdef __cplusplus
29 33 extern "C" {
30 34 #endif
31 35
32 36 #include <sys/pcie.h>
33 37 #include <sys/pciev.h>
34 38
35 39 #define PCI_GET_BDF(dip) \
36 40 PCIE_DIP2BUS(dip)->bus_bdf
37 41 #define PCI_GET_SEC_BUS(dip) \
38 42 PCIE_DIP2BUS(dip)->bus_bdg_secbus
39 43 #define PCI_GET_PCIE2PCI_SECBUS(dip) \
40 44 PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus
41 45
42 46 #define DEVI_PORT_TYPE_PCI \
43 47 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \
44 48 PCI_BRIDGE_PCI_IF_PCI2PCI)
45 49
46 50 #define PCIE_DIP2BUS(dip) \
47 51 (ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \
48 52 PCIE_DIP2UPBUS(dip) : \
49 53 ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \
50 54 PCIE_DIP2DOWNBUS(dip) : NULL)
51 55
52 56 #define PCIE_DIP2UPBUS(dip) \
53 57 ((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE))
54 58 #define PCIE_DIP2DOWNBUS(dip) \
55 59 ((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE))
56 60 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd
57 61 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p
58 62 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip
59 63 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip
60 64 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p))
61 65 #define PCIE_BUS2DOM(bus_p) bus_p->bus_dom
62 66 #define PCIE_DIP2DOM(dip) PCIE_BUS2DOM(PCIE_DIP2BUS(dip))
63 67
64 68 /*
65 69 * These macros depend on initialization of type related data in bus_p.
66 70 */
67 71 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off)
68 72 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off)
69 73 #define PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p))
70 74 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off)
71 75 /* IS_ROOT = is RC or RP */
72 76 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p))
73 77
74 78 #define PCIE_IS_HOTPLUG_CAPABLE(dip) \
75 79 (PCIE_DIP2BUS(dip)->bus_hp_sup_modes)
76 80
77 81 #define PCIE_IS_HOTPLUG_ENABLED(dip) \
78 82 ((PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_PCI_HP_MODE) || \
79 83 (PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE))
80 84
81 85 /*
82 86 * This is a pseudo pcie "device type", but it's needed to explain describe
83 87 * nodes such as PX and NPE, which aren't really PCI devices but do control or
84 88 * interaction with PCI error handling.
85 89 */
86 90 #define PCIE_IS_RC(bus_p) \
87 91 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO)
88 92 #define PCIE_IS_RP(bus_p) \
89 93 ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \
90 94 PCIE_IS_PCIE(bus_p))
91 95 #define PCIE_IS_SWU(bus_p) \
92 96 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP)
93 97 #define PCIE_IS_SWD(bus_p) \
94 98 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN)
95 99 #define PCIE_IS_SW(bus_p) \
96 100 (PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p))
97 101 #define PCIE_IS_BDG(bus_p) (bus_p->bus_hdr_type == PCI_HEADER_ONE)
98 102 #define PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p))
99 103 #define PCIE_IS_PCIE_BDG(bus_p) \
100 104 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI)
101 105 #define PCIE_IS_PCI2PCIE(bus_p) \
102 106 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)
103 107 #define PCIE_IS_PCIE_SEC(bus_p) \
104 108 (PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p))
105 109 #define PCIX_ECC_VERSION_CHECK(bus_p) \
106 110 ((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \
107 111 (bus_p->bus_ecc_ver == PCI_PCIX_VER_2))
108 112
109 113 #define PCIE_VENID(bus_p) (bus_p->bus_dev_ven_id & 0xffff)
110 114 #define PCIE_DEVID(bus_p) ((bus_p->bus_dev_ven_id >> 16) & 0xffff)
111 115
112 116 /* PCIE Cap/AER shortcuts */
113 117 #define PCIE_GET(sz, bus_p, off) \
114 118 pci_config_get ## sz(bus_p->bus_cfg_hdl, off)
115 119 #define PCIE_PUT(sz, bus_p, off, val) \
116 120 pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val)
117 121 #define PCIE_CAP_GET(sz, bus_p, off) \
118 122 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcie_off, off)
119 123 #define PCIE_CAP_PUT(sz, bus_p, off, val) \
120 124 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcie_off, off, \
121 125 val)
122 126 #define PCIE_AER_GET(sz, bus_p, off) \
123 127 PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_aer_off, off)
124 128 #define PCIE_AER_PUT(sz, bus_p, off, val) \
125 129 PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_aer_off, off, \
126 130 val)
127 131 #define PCIX_CAP_GET(sz, bus_p, off) \
128 132 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcix_off, off)
129 133 #define PCIX_CAP_PUT(sz, bus_p, off, val) \
130 134 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcix_off, off, \
131 135 val)
132 136
133 137 /* Translate PF error return values to DDI_FM values */
134 138 #define PF_ERR2DDIFM_ERR(sts) \
135 139 (sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL : \
136 140 (sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL))
137 141
138 142 /*
139 143 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue.
140 144 * This flag will be used both by px and pcieb nexus drivers.
141 145 */
142 146 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000
143 147
144 148 /*
145 149 * PCI(e/-X) structures used to to gather and report errors detected by
146 150 * PCI(e/-X) compliant devices. These registers only contain "dynamic" data.
147 151 * Static data such as Capability Offsets and Version #s is saved in the parent
148 152 * private data.
149 153 */
150 154 #define PCI_ERR_REG(pfd_p) pfd_p->pe_pci_regs
151 155 #define PCI_BDG_ERR_REG(pfd_p) PCI_ERR_REG(pfd_p)->pci_bdg_regs
152 156 #define PCIX_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcix_regs
153 157 #define PCIX_ECC_REG(pfd_p) PCIX_ERR_REG(pfd_p)->pcix_ecc_regs
154 158 #define PCIX_BDG_ERR_REG(pfd_p) pfd_p->pe_pcix_bdg_regs
155 159 #define PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n]
156 160 #define PCIE_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcie_regs
157 161 #define PCIE_RP_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_rp_regs
158 162 #define PCIE_ROOT_FAULT(pfd_p) pfd_p->pe_root_fault
159 163 #define PCIE_ROOT_EH_SRC(pfd_p) pfd_p->pe_root_eh_src
160 164 #define PCIE_ADV_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_adv_regs
161 165 #define PCIE_ADV_HDR(pfd_p, n) PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n]
162 166 #define PCIE_ADV_BDG_REG(pfd_p) \
163 167 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs
164 168 #define PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n]
165 169 #define PCIE_ADV_RP_REG(pfd_p) \
166 170 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs
167 171 #define PFD_AFFECTED_DEV(pfd_p) pfd_p->pe_affected_dev
168 172 #define PFD_SET_AFFECTED_FLAG(pfd_p, aff_flag) \
169 173 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = aff_flag
170 174 #define PFD_SET_AFFECTED_BDF(pfd_p, bdf) \
171 175 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = bdf
172 176
173 177 #define PFD_IS_ROOT(pfd_p) PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p))
174 178 #define PFD_IS_RC(pfd_p) PCIE_IS_RC(PCIE_PFD2BUS(pfd_p))
175 179 #define PFD_IS_RP(pfd_p) PCIE_IS_RP(PCIE_PFD2BUS(pfd_p))
176 180
177 181 /* bus_hp_mode field */
178 182 typedef enum {
179 183 PCIE_NONE_HP_MODE = 0x0,
180 184 PCIE_ACPI_HP_MODE = 0x1,
181 185 PCIE_PCI_HP_MODE = 0x2,
182 186 PCIE_NATIVE_HP_MODE = 0x4
183 187 } pcie_hp_mode_t;
184 188
185 189 typedef struct pf_pci_bdg_err_regs {
186 190 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */
187 191 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */
188 192 } pf_pci_bdg_err_regs_t;
189 193
190 194 typedef struct pf_pci_err_regs {
191 195 uint16_t pci_err_status; /* pci status register */
192 196 uint16_t pci_cfg_comm; /* pci command register */
193 197 pf_pci_bdg_err_regs_t *pci_bdg_regs;
194 198 } pf_pci_err_regs_t;
195 199
196 200 typedef struct pf_pcix_ecc_regs {
197 201 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */
198 202 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */
199 203 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */
200 204 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */
201 205 } pf_pcix_ecc_regs_t;
202 206
203 207 typedef struct pf_pcix_err_regs {
204 208 uint16_t pcix_command; /* pcix command register */
205 209 uint32_t pcix_status; /* pcix status register */
206 210 pf_pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */
207 211 } pf_pcix_err_regs_t;
208 212
209 213 typedef struct pf_pcix_bdg_err_regs {
210 214 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */
211 215 uint32_t pcix_bdg_stat; /* pcix bridge status reg */
212 216 pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */
213 217 } pf_pcix_bdg_err_regs_t;
214 218
215 219 typedef struct pf_pcie_adv_bdg_err_regs {
216 220 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */
217 221 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */
218 222 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */
219 223 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */
220 224 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */
221 225 uint32_t pcie_sue_tgt_trans; /* Fault trans type from SAER Logs */
222 226 uint64_t pcie_sue_tgt_addr; /* Fault addr from SAER Logs */
223 227 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */
224 228 } pf_pcie_adv_bdg_err_regs_t;
225 229
226 230 typedef struct pf_pcie_adv_rp_err_regs {
227 231 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */
228 232 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */
229 233 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */
230 234 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */
231 235 } pf_pcie_adv_rp_err_regs_t;
232 236
233 237 typedef struct pf_pcie_adv_err_regs {
234 238 uint32_t pcie_adv_ctl; /* pcie advanced control reg */
235 239 uint32_t pcie_ue_status; /* pcie ue error status reg */
236 240 uint32_t pcie_ue_mask; /* pcie ue error mask reg */
237 241 uint32_t pcie_ue_sev; /* pcie ue error severity reg */
238 242 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */
239 243 uint32_t pcie_ce_status; /* pcie ce error status reg */
240 244 uint32_t pcie_ce_mask; /* pcie ce error mask reg */
241 245 union {
242 246 pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */
243 247 pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs; /* rp regs */
244 248 } pcie_ext;
245 249 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */
246 250 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */
247 251 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from AER Logs */
248 252 } pf_pcie_adv_err_regs_t;
249 253
250 254 typedef struct pf_pcie_rp_err_regs {
251 255 uint32_t pcie_rp_status; /* root complex status register */
252 256 uint16_t pcie_rp_ctl; /* root complex control register */
253 257 } pf_pcie_rp_err_regs_t;
254 258
255 259 typedef struct pf_pcie_err_regs {
256 260 uint16_t pcie_err_status; /* pcie device status register */
257 261 uint16_t pcie_err_ctl; /* pcie error control register */
258 262 uint32_t pcie_dev_cap; /* pcie device capabilities register */
259 263 pf_pcie_rp_err_regs_t *pcie_rp_regs; /* pcie root complex regs */
260 264 pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */
261 265 } pf_pcie_err_regs_t;
262 266
263 267 typedef enum {
264 268 PF_INTR_TYPE_NONE = 0,
265 269 PF_INTR_TYPE_FABRIC = 1, /* Fabric Message */
266 270 PF_INTR_TYPE_DATA, /* Data Access Failure, failed loads */
267 271 PF_INTR_TYPE_AER, /* Root Port AER MSI */
268 272 PF_INTR_TYPE_INTERNAL /* Chip specific internal errors */
269 273 } pf_intr_type_t;
270 274
271 275 typedef struct pf_root_eh_src {
272 276 pf_intr_type_t intr_type;
273 277 void *intr_data; /* Interrupt Data */
274 278 } pf_root_eh_src_t;
275 279
276 280 typedef struct pf_root_fault {
277 281 pcie_req_id_t scan_bdf; /* BDF from error logs */
278 282 uint64_t scan_addr; /* Addr from error logs */
279 283 boolean_t full_scan; /* Option to do a full scan */
280 284 } pf_root_fault_t;
281 285
282 286 typedef struct pf_data pf_data_t;
283 287
284 288 /*
285 289 * For hot plugged device, these data are init'ed during during probe
286 290 * For non-hotplugged device, these data are init'ed in pci_autoconfig (on x86),
287 291 * or in px_attach()(on sparc).
288 292 *
289 293 * For root complex the fields are initialized in pcie_rc_init_bus();
290 294 * for others part of the fields are initialized in pcie_init_bus(),
291 295 * and part of fields initialized in pcie_post_init_bus(). See comments
292 296 * on top of respective functions for details.
293 297 */
294 298 typedef struct pcie_bus {
295 299 /* Needed for PCI/PCIe fabric error handling */
296 300 dev_info_t *bus_dip;
297 301 dev_info_t *bus_rp_dip;
298 302 ddi_acc_handle_t bus_cfg_hdl; /* error handling acc hdle */
299 303 uint_t bus_fm_flags;
300 304 uint_t bus_soft_state;
301 305
302 306 /* Static PCI/PCIe information */
303 307 pcie_req_id_t bus_bdf;
304 308 pcie_req_id_t bus_rp_bdf; /* BDF of device's Root Port */
305 309 uint32_t bus_dev_ven_id; /* device/vendor ID */
306 310 uint8_t bus_rev_id; /* revision ID */
307 311 uint8_t bus_hdr_type; /* pci header type, see pci.h */
308 312 uint16_t bus_dev_type; /* PCI-E dev type, see pcie.h */
309 313 uint8_t bus_bdg_secbus; /* Bridge secondary bus num */
310 314 uint16_t bus_pcie_off; /* PCIe Capability Offset */
311 315 uint16_t bus_aer_off; /* PCIe Advanced Error Offset */
312 316 uint16_t bus_pcix_off; /* PCIx Capability Offset */
313 317 uint16_t bus_pci_hp_off; /* PCI HP (SHPC) Cap Offset */
314 318 uint16_t bus_ecc_ver; /* PCIX ecc version */
315 319 pci_bus_range_t bus_bus_range; /* pci bus-range property */
316 320 ppb_ranges_t *bus_addr_ranges; /* pci range property */
317 321 int bus_addr_entries; /* number of range prop */
318 322 pci_regspec_t *bus_assigned_addr; /* "assigned-address" prop */
319 323 int bus_assigned_entries; /* number of prop entries */
320 324
321 325 /* Cache of last fault data */
322 326 pf_data_t *bus_pfd;
323 327 pcie_domain_t *bus_dom;
324 328
325 329 int bus_mps; /* Maximum Payload Size */
326 330
327 331 void *bus_plat_private; /* Platform specific */
328 332 /* Hotplug specific fields */
329 333 pcie_hp_mode_t bus_hp_sup_modes; /* HP modes supported */
330 334 pcie_hp_mode_t bus_hp_curr_mode; /* HP mode used */
331 335 void *bus_hp_ctrl; /* HP bus ctrl data */
332 336 int bus_ari; /* ARI device */
333 337
334 338 uint64_t bus_cfgacc_base; /* config space base address */
335 339
336 340 /* workaround for PCI/PCI-X devs behind PCIe2PCI Bridge */
337 341 pcie_req_id_t bus_pcie2pci_secbus;
338 342 } pcie_bus_t;
339 343
340 344 /*
341 345 * Data structure to log what devices are affected in relationship to the
342 346 * severity after all the errors bits have been analyzed.
343 347 */
344 348 #define PF_AFFECTED_ROOT (1 << 0) /* RP/RC is affected */
345 349 #define PF_AFFECTED_SELF (1 << 1) /* Reporting Device is affected */
346 350 #define PF_AFFECTED_PARENT (1 << 2) /* Parent device is affected */
347 351 #define PF_AFFECTED_CHILDREN (1 << 3) /* All children below are affected */
348 352 #define PF_AFFECTED_BDF (1 << 4) /* See affected_bdf */
349 353 #define PF_AFFECTED_AER (1 << 5) /* See AER Registers */
350 354 #define PF_AFFECTED_SAER (1 << 6) /* See SAER Registers */
351 355 #define PF_AFFECTED_ADDR (1 << 7) /* Device targeted by addr */
352 356
353 357 #define PF_MAX_AFFECTED_FLAG PF_AFFECTED_ADDR
354 358
355 359 typedef struct pf_affected_dev {
356 360 uint16_t pe_affected_flags;
357 361 pcie_req_id_t pe_affected_bdf;
358 362 } pf_affected_dev_t;
359 363
360 364 struct pf_data {
361 365 boolean_t pe_lock;
362 366 boolean_t pe_valid;
363 367 uint32_t pe_severity_flags; /* Severity of error */
364 368 uint32_t pe_orig_severity_flags; /* Original severity */
365 369 pf_affected_dev_t *pe_affected_dev;
366 370 pcie_bus_t *pe_bus_p;
367 371 pf_root_fault_t *pe_root_fault; /* Only valid for RC and RP */
368 372 pf_root_eh_src_t *pe_root_eh_src; /* Only valid for RC and RP */
369 373 pf_pci_err_regs_t *pe_pci_regs; /* PCI error reg */
370 374 union {
371 375 pf_pcix_err_regs_t *pe_pcix_regs; /* PCI-X error reg */
372 376 pf_pcie_err_regs_t *pe_pcie_regs; /* PCIe error reg */
373 377 } pe_ext;
374 378 pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */
375 379 pf_data_t *pe_prev; /* Next error in queue */
376 380 pf_data_t *pe_next; /* Next error in queue */
377 381 boolean_t pe_rber_fatal;
378 382 };
379 383
380 384 /* Information used while handling errors in the fabric. */
381 385 typedef struct pf_impl {
382 386 ddi_fm_error_t *pf_derr;
383 387 pf_root_fault_t *pf_fault; /* captured fault bdf/addr to scan */
384 388 pf_data_t *pf_dq_head_p; /* ptr to fault data queue */
385 389 pf_data_t *pf_dq_tail_p; /* ptr pt last fault data q */
386 390 uint32_t pf_total; /* total non RC pf_datas */
387 391 } pf_impl_t;
388 392
389 393 /* bus_fm_flags field */
390 394 #define PF_FM_READY (1 << 0) /* bus_fm_lock initialized */
391 395 #define PF_FM_IS_NH (1 << 1) /* known as non-hardened */
392 396
393 397 /*
394 398 * PCIe fabric handle lookup address flags. Used to define what type of
395 399 * transaction the address is for. These same value are defined again in
396 400 * fabric-xlate FM module. Do not modify these variables, without modifying
397 401 * those.
398 402 */
399 403 #define PF_ADDR_DMA (1 << 0)
400 404 #define PF_ADDR_PIO (1 << 1)
401 405 #define PF_ADDR_CFG (1 << 2)
402 406
403 407 /* PCIe fabric error scanning status flags */
404 408 #define PF_SCAN_SUCCESS (1 << 0)
405 409 #define PF_SCAN_CB_FAILURE (1 << 1) /* hardened device callback failure */
406 410 #define PF_SCAN_NO_ERR_IN_CHILD (1 << 2) /* no errors in bridge sec stat reg */
407 411 #define PF_SCAN_IN_DQ (1 << 3) /* already present in the faultq */
408 412 #define PF_SCAN_DEADLOCK (1 << 4) /* deadlock detected */
409 413 #define PF_SCAN_BAD_RESPONSE (1 << 5) /* Incorrect device response */
410 414
411 415 /* PCIe fabric error handling severity return flags */
412 416 #define PF_ERR_NO_ERROR (1 << 0) /* No error seen */
413 417 #define PF_ERR_CE (1 << 1) /* Correctable Error */
414 418 #define PF_ERR_NO_PANIC (1 << 2) /* Error should not panic sys */
415 419 #define PF_ERR_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */
416 420 #define PF_ERR_MATCHED_RC (1 << 4) /* Error Handled By RC */
417 421 #define PF_ERR_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */
418 422 #define PF_ERR_PANIC (1 << 6) /* Error should panic system */
419 423 #define PF_ERR_PANIC_DEADLOCK (1 << 7) /* deadlock detected */
420 424 #define PF_ERR_PANIC_BAD_RESPONSE (1 << 8) /* Device no response */
421 425 #define PF_ERR_MATCH_DOM (1 << 9) /* Error Handled By IO domain */
422 426
423 427 #define PF_ERR_FATAL_FLAGS \
424 428 (PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK | PF_ERR_PANIC_BAD_RESPONSE)
425 429
426 430 #define PF_HDL_FOUND 1
427 431 #define PF_HDL_NOTFOUND 2
428 432
429 433 /*
430 434 * PCIe Capability Device Type Pseudo Definitions.
431 435 *
432 436 * PCI_PSEUDO is used on real PCI devices. The Legacy PCI definition in the
433 437 * PCIe spec really refers to PCIe devices that *require* IO Space access. IO
434 438 * Space access is usually frowned upon now in PCIe, but there for legacy
435 439 * purposes.
436 440 */
437 441 #define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100
438 442 #define PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO 0x101
439 443
440 444 #define PCIE_INVALID_BDF 0xFFFF
441 445 #define PCIE_CHECK_VALID_BDF(x) (x != PCIE_INVALID_BDF)
442 446
443 447 typedef struct {
444 448 dev_info_t *dip;
445 449 int highest_common_mps;
446 450 } pcie_max_supported_t;
447 451
448 452 /*
449 453 * Default interrupt priority for all PCI and PCIe nexus drivers including
450 454 * hotplug interrupts.
451 455 */
452 456 #define PCIE_INTR_PRI (LOCK_LEVEL - 1)
453 457
454 458 /*
455 459 * XXX - PCIE_IS_PCIE check is required in order not to invoke these macros
456 460 * for non-standard PCI or PCI Express Hotplug Controllers.
457 461 */
458 462 #define PCIE_ENABLE_ERRORS(dip) \
459 463 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \
460 464 pcie_enable_errors(dip); \
461 465 (void) pcie_enable_ce(dip); \
462 466 }
463 467
464 468 #define PCIE_DISABLE_ERRORS(dip) \
465 469 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \
466 470 pcie_disable_errors(dip); \
467 471 }
468 472
469 473 /*
470 474 * pcie_init_buspcie_fini_bus specific flags
471 475 */
472 476 #define PCIE_BUS_INITIAL 0x0001
473 477 #define PCIE_BUS_FINAL 0x0002
474 478 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL)
475 479
476 480 #ifdef DEBUG
477 481 #define PCIE_DBG pcie_dbg
478 482 /* Common Debugging shortcuts */
479 483 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \
480 484 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
481 485 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
482 486 PCIE_GET(sz, bus_p, off))
483 487 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \
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484 488 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
485 489 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
486 490 PCIE_CAP_GET(sz, bus_p, off))
487 491 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \
488 492 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
489 493 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
490 494 PCIE_AER_GET(sz, bus_p, off))
491 495
492 496 #else /* DEBUG */
493 497
494 -#define PCIE_DBG_CFG 0 &&
495 -#define PCIE_DBG 0 &&
496 -#define PCIE_ARI_DBG 0 &&
497 -#define PCIE_DBG_CAP 0 &&
498 -#define PCIE_DBG_AER 0 &&
498 +#define PCIE_DBG_CFG(...)
499 +#define PCIE_DBG(...)
500 +#define PCIE_ARI_DBG(...)
501 +#define PCIE_DBG_CAP(...)
502 +#define PCIE_DBG_AER(...)
499 503
500 504 #endif /* DEBUG */
501 505
502 506 /* PCIe Friendly Functions */
503 507 extern int pcie_init(dev_info_t *dip, caddr_t arg);
504 508 extern int pcie_uninit(dev_info_t *dip);
505 509 extern int pcie_hpintr_enable(dev_info_t *dip);
506 510 extern int pcie_hpintr_disable(dev_info_t *dip);
507 511 extern int pcie_intr(dev_info_t *dip);
508 512 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp,
509 513 cred_t *credp);
510 514 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp,
511 515 cred_t *credp);
512 516 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg,
513 517 int mode, cred_t *credp, int *rvalp);
514 518 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
515 519 int flags, char *name, caddr_t valuep, int *lengthp);
516 520
517 521 extern void pcie_init_root_port_mps(dev_info_t *dip);
518 522 extern int pcie_initchild(dev_info_t *dip);
519 523 extern void pcie_uninitchild(dev_info_t *dip);
520 524 extern int pcie_init_cfghdl(dev_info_t *dip);
521 525 extern void pcie_fini_cfghdl(dev_info_t *dip);
522 526 extern void pcie_clear_errors(dev_info_t *dip);
523 527 extern int pcie_postattach_child(dev_info_t *dip);
524 528 extern void pcie_enable_errors(dev_info_t *dip);
525 529 extern void pcie_disable_errors(dev_info_t *dip);
526 530 extern int pcie_enable_ce(dev_info_t *dip);
527 531 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *);
528 532
529 533 extern pcie_bus_t *pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf,
530 534 uint8_t flags);
531 535 extern void pcie_fini_bus(dev_info_t *dip, uint8_t flags);
532 536 extern void pcie_fab_init_bus(dev_info_t *dip, uint8_t flags);
533 537 extern void pcie_fab_fini_bus(dev_info_t *dip, uint8_t flags);
534 538 extern void pcie_rc_init_bus(dev_info_t *dip);
535 539 extern void pcie_rc_fini_bus(dev_info_t *dip);
536 540 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd);
537 541 extern void pcie_rc_fini_pfd(pf_data_t *pfd);
538 542 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip);
539 543 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf);
540 544 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
541 545 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip);
542 546 extern int pcie_dev(dev_info_t *dip);
543 547 extern void pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip,
544 548 int *max_supported);
545 549 extern int pcie_root_port(dev_info_t *dip);
546 550 extern int pcie_initchild_mps(dev_info_t *dip);
547 551 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val);
548 552 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip);
549 553
550 554 extern uint32_t pcie_get_aer_uce_mask();
551 555 extern uint32_t pcie_get_aer_ce_mask();
552 556 extern uint32_t pcie_get_aer_suce_mask();
553 557 extern uint32_t pcie_get_serr_mask();
554 558 extern void pcie_set_aer_uce_mask(uint32_t mask);
555 559 extern void pcie_set_aer_ce_mask(uint32_t mask);
556 560 extern void pcie_set_aer_suce_mask(uint32_t mask);
557 561 extern void pcie_set_serr_mask(uint32_t mask);
558 562 extern void pcie_init_plat(dev_info_t *dip);
559 563 extern void pcie_fini_plat(dev_info_t *dip);
560 564 extern int pcie_read_only_probe(dev_info_t *, char *, dev_info_t **);
561 565 extern dev_info_t *pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function);
562 566 extern int pcie_ari_disable(dev_info_t *dip);
563 567 extern int pcie_ari_enable(dev_info_t *dip);
564 568
565 569 #define PCIE_ARI_FORW_NOT_SUPPORTED 0
566 570 #define PCIE_ARI_FORW_SUPPORTED 1
567 571
568 572 extern int pcie_ari_supported(dev_info_t *dip);
569 573
570 574 #define PCIE_ARI_FORW_DISABLED 0
571 575 #define PCIE_ARI_FORW_ENABLED 1
572 576
573 577 extern int pcie_ari_is_enabled(dev_info_t *dip);
574 578
575 579 #define PCIE_NOT_ARI_DEVICE 0
576 580 #define PCIE_ARI_DEVICE 1
577 581
578 582 extern int pcie_ari_device(dev_info_t *dip);
579 583 extern int pcie_ari_get_next_function(dev_info_t *dip, int *func);
580 584
581 585 /* PCIe error handling functions */
582 586 extern void pf_eh_enter(pcie_bus_t *bus_p);
583 587 extern void pf_eh_exit(pcie_bus_t *bus_p);
584 588 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr,
585 589 pf_data_t *root_pfd_p);
586 590 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t);
587 591 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t);
588 592 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t,
589 593 pcie_req_id_t);
590 594 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *);
591 595 extern void pcie_force_fullscan();
592 596
593 597 #ifdef DEBUG
594 598 extern uint_t pcie_debug_flags;
595 599 extern void pcie_dbg(char *fmt, ...);
596 600 #endif /* DEBUG */
597 601
598 602 /* PCIe IOV functions */
599 603 extern dev_info_t *pcie_find_dip_by_bdf(dev_info_t *rootp, pcie_req_id_t bdf);
600 604
601 605 extern boolean_t pf_in_bus_range(pcie_bus_t *, pcie_req_id_t);
602 606 extern boolean_t pf_in_assigned_addr(pcie_bus_t *, uint64_t);
603 607 extern int pf_pci_decode(pf_data_t *, uint16_t *);
604 608 extern pcie_bus_t *pf_find_busp_by_bdf(pf_impl_t *, pcie_req_id_t);
605 609 extern pcie_bus_t *pf_find_busp_by_addr(pf_impl_t *, uint64_t);
606 610 extern pcie_bus_t *pf_find_busp_by_aer(pf_impl_t *, pf_data_t *);
607 611 extern pcie_bus_t *pf_find_busp_by_saer(pf_impl_t *, pf_data_t *);
608 612
609 613 extern int pciev_eh(pf_data_t *, pf_impl_t *);
610 614 extern pcie_bus_t *pciev_get_affected_dev(pf_impl_t *, pf_data_t *,
611 615 uint16_t, uint16_t);
612 616 extern void pciev_eh_exit(pf_data_t *, uint_t);
613 617 extern boolean_t pcie_in_domain(pcie_bus_t *, uint_t);
614 618
615 619 #define PCIE_ZALLOC(data) kmem_zalloc(sizeof (data), KM_SLEEP)
616 620
617 621
618 622 #ifdef __cplusplus
619 623 }
620 624 #endif
621 625
622 626 #endif /* _SYS_PCIE_IMPL_H */
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