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10686 Debug macros causes smatch issues
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--- old/usr/src/uts/common/io/pciex/pcieb.h
+++ new/usr/src/uts/common/io/pciex/pcieb.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 +/*
26 + * Copyright 2019, Joyent, Inc.
27 + */
28 +
25 29 #ifndef _SYS_PCIEB_H
26 30 #define _SYS_PCIEB_H
27 31
28 32 #ifdef __cplusplus
29 33 extern "C" {
30 34 #endif
31 35
32 36 #if defined(DEBUG)
33 37 #define PCIEB_DEBUG pcieb_dbg
34 38 extern void pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...);
35 39 #else /* DEBUG */
36 -#define PCIEB_DEBUG 0 &&
40 +#define PCIEB_DEBUG(...)
37 41 #endif /* DEBUG */
38 42
39 43 typedef enum { /* same sequence as pcieb_debug_sym[] */
40 44 /* 0 */ DBG_ATTACH,
41 45 /* 1 */ DBG_PWR,
42 46 /* 2 */ DBG_INTR
43 47 } pcieb_debug_bit_t;
44 48
45 49 /*
46 50 * Intel specific register offsets with bit definitions.
47 51 */
48 52 #define PCIEB_PX_CAPABILITY_ID 0x44
49 53 #define PCIEB_BRIDGE_CONF 0x40
50 54
51 55 /*
52 56 * PCI/PCI-E Configuration register specific values.
53 57 */
54 58 #define PX_PMODE 0x4000 /* PCI/PCIX Mode */
55 59 #define PX_PFREQ_66 0x200 /* PCI clock frequency */
56 60 #define PX_PFREQ_100 0x400
57 61 #define PX_PFREQ_133 0x600
58 62 #define PX_PMRE 0x80 /* Peer memory read enable */
59 63
60 64 /*
61 65 * Downstream delayed transaction resource partitioning.
62 66 */
63 67 #define PX_ODTP 0x40 /* Max. of two entries PX and PCI */
64 68
65 69 /*
66 70 * Maximum upstream delayed transaction.
67 71 */
68 72 #define PX_MDT_44 0x00
69 73 #define PX_MDT_11 0x01
70 74 #define PX_MDT_22 0x10
71 75
72 76 #define NUM_LOGICAL_SLOTS 32
73 77 #define PCIEB_RANGE_LEN 2
74 78 #define PCIEB_32BIT_IO 1
75 79 #define PCIEB_32bit_MEM 1
76 80 #define PCIEB_MEMGRAIN 0x100000
77 81 #define PCIEB_IOGRAIN 0x1000
78 82
79 83 #define PCIEB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8))
80 84 #define PCIEB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo))
81 85 #define PCIEB_32bit_MEMADDR(addr) (PCIEB_LADDR(0, ((uint16_t)(addr) & 0xFFF0)))
82 86
83 87 /*
84 88 * Intel 41210 PCIe-to-PCI Bridge has two Functions F0 and F2:
85 89 * VID: 0x8086
86 90 * DID: F0 = 0x340, F2 = 0x341
87 91 */
88 92 #define PCIEB_IS_41210_F0(bus_dev_ven_id) (bus_dev_ven_id == 0x3408086)
89 93 #define PCIEB_IS_41210_F2(bus_dev_ven_id) (bus_dev_ven_id == 0x3418086)
90 94 #define PCIEB_IS_41210_BRIDGE(bus_dev_ven_id) \
91 95 (PCIEB_IS_41210_F0(bus_dev_ven_id) || PCIEB_IS_41210_F2(bus_dev_ven_id))
92 96
93 97 typedef struct {
94 98 dev_info_t *pcieb_dip;
95 99
96 100 /* Interrupt support */
97 101 ddi_intr_handle_t *pcieb_htable; /* Intr Handlers */
98 102 int pcieb_htable_size; /* htable size */
99 103 int pcieb_intr_count; /* Num of Intr */
100 104 uint_t pcieb_intr_priority; /* Intr Priority */
101 105 int pcieb_intr_type; /* (MSI | FIXED) */
102 106 int pcieb_isr_tab[4]; /* MSI source offset */
103 107
104 108 int pcieb_init_flags;
105 109 kmutex_t pcieb_mutex; /* Soft state mutex */
106 110 kmutex_t pcieb_intr_mutex; /* Intr handler mutex */
107 111 kmutex_t pcieb_err_mutex; /* Error mutex */
108 112 kmutex_t pcieb_peek_poke_mutex; /* Peekpoke mutex */
109 113
110 114 /* FMA */
111 115 boolean_t pcieb_no_aer_msi;
112 116 ddi_iblock_cookie_t pcieb_fm_ibc;
113 117 } pcieb_devstate_t;
114 118
115 119 /*
116 120 * soft state pointer
117 121 */
118 122 extern void *pcieb_state;
119 123
120 124 /* soft state flags */
121 125 #define PCIEB_SOFT_STATE_CLOSED 0x00
122 126 #define PCIEB_SOFT_STATE_OPEN 0x01
123 127 #define PCIEB_SOFT_STATE_OPEN_EXCL 0x02
124 128
125 129 /* init flags */
126 130 #define PCIEB_INIT_MUTEX 0x01
127 131 #define PCIEB_INIT_HTABLE 0x02
128 132 #define PCIEB_INIT_ALLOC 0x04
129 133 #define PCIEB_INIT_HANDLER 0x08
130 134 #define PCIEB_INIT_ENABLE 0x10
131 135 #define PCIEB_INIT_BLOCK 0x20
132 136 #define PCIEB_INIT_FM 0x40
133 137
134 138 #define PCIEB_INTR_SRC_UNKNOWN 0x0 /* must be 0 */
135 139 #define PCIEB_INTR_SRC_HP 0x1
136 140 #define PCIEB_INTR_SRC_PME 0x2
137 141 #define PCIEB_INTR_SRC_AER 0x4
138 142
139 143 /*
140 144 * Need to put vendor ids in a common file and not platform specific files
141 145 * as is done today. Until then putting this vendor id define here.
142 146 */
143 147 #define NVIDIA_VENDOR_ID 0x10de /* Nvidia Vendor Id */
144 148
145 149 #ifdef PCIEB_BCM
146 150
147 151 /* Workaround for address space limitation in Broadcom 5714/5715 */
148 152 #define PCIEB_ADDR_LIMIT_LO 0ull
149 153 #define PCIEB_ADDR_LIMIT_HI ((1ull << 40) - 1)
150 154
151 155 #endif /* PCIEB_BCM */
152 156
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153 157 /*
154 158 * The following values are used to initialize the cache line size
155 159 * and latency timer registers for PCI, PCI-X and PCIe2PCI devices.
156 160 */
157 161 #define PCIEB_CACHE_LINE_SIZE 0x10 /* 64 bytes in # of DWORDs */
158 162 #define PCIEB_LATENCY_TIMER 0x40 /* 64 PCI cycles */
159 163
160 164 extern void pcieb_set_pci_perf_parameters(dev_info_t *dip,
161 165 ddi_acc_handle_t config_handle);
162 166 extern void pcieb_plat_attach_workaround(dev_info_t *dip);
163 -extern void pcieb_plat_intr_attach(pcieb_devstate_t *pcieb);
164 -extern void pcieb_plat_initchild(dev_info_t *child);
165 -extern void pcieb_plat_uninitchild(dev_info_t *child);
167 +extern void pcieb_plat_intr_attach(pcieb_devstate_t *pcieb);
168 +extern void pcieb_plat_initchild(dev_info_t *child);
169 +extern void pcieb_plat_uninitchild(dev_info_t *child);
166 170 extern int pcieb_plat_ctlops(dev_info_t *rdip, ddi_ctl_enum_t ctlop,
167 171 void *arg);
168 -extern int pcieb_plat_pcishpc_probe(dev_info_t *dip,
172 +extern int pcieb_plat_pcishpc_probe(dev_info_t *dip,
169 173 ddi_acc_handle_t config_handle);
170 174 extern int pcieb_plat_peekpoke(dev_info_t *dip, dev_info_t *rdip,
171 175 ddi_ctl_enum_t ctlop, void *arg, void *result);
172 176 extern void pcieb_set_prot_scan(dev_info_t *dip, ddi_acc_impl_t *hdlp);
173 177 extern int pcieb_plat_intr_ops(dev_info_t *dip, dev_info_t *rdip,
174 178 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result);
175 179 extern boolean_t pcieb_plat_msi_supported(dev_info_t *dip);
176 180 extern boolean_t pcieb_plat_pwr_disable(dev_info_t *dip);
177 181
178 182 #if defined(__i386) || defined(__amd64)
179 183 extern void pcieb_intel_error_workaround(dev_info_t *dip);
180 184 extern void pcieb_intel_serr_workaround(dev_info_t *dip, boolean_t mcheck);
181 185 extern void pcieb_intel_rber_workaround(dev_info_t *dip);
182 186 extern void pcieb_intel_sw_workaround(dev_info_t *dip);
183 187 extern void pcieb_intel_mps_workaround(dev_info_t *dip);
184 188 extern void pcieb_init_osc(dev_info_t *dip);
185 189 extern void pcieb_peekpoke_cb(dev_info_t *, ddi_fm_error_t *);
186 190 extern int pcishpc_init(dev_info_t *dip);
187 191 extern int pcishpc_uninit(dev_info_t *dip);
188 192 extern int pcishpc_intr(dev_info_t *dip);
189 193 #endif /* defined(__i386) || defined(__amd64) */
190 194
191 195 #ifdef PX_PLX
192 196 extern void pcieb_attach_plx_workarounds(pcieb_devstate_t *pcieb);
193 197 extern int pcieb_init_plx_workarounds(pcieb_devstate_t *pcieb,
194 198 dev_info_t *child);
195 199 #endif /* PX_PLX */
196 200
197 201 #ifdef __cplusplus
198 202 }
199 203 #endif
200 204
201 205 #endif /* _SYS_PCIEB_H */
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