10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2018 Joyent, Inc.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 * Copyright 2018 Nexenta Systems, Inc.
35 */
36
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define _SYS_X86_ARCHEXT_H
39
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif /* _ASM */
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
237
238 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
239 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
240 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
241 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
242 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
243
244 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
245 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
246 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
247 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
248 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
249
250 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
251 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
252
253 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
254 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
255 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */
256 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */
257 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */
258 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */
259
260 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
261 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
262
263 /*
264 * Intel also uses cpuid leaf 0xd to report additional instructions and features
265 * when the sub-leaf in %ecx == 1. We label these using the same convention as
266 * with leaf 7.
267 */
268 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
269 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
270 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
271
272 #define REG_PAT 0x277
273 #define REG_TSC 0x10 /* timestamp counter */
274 #define REG_APIC_BASE_MSR 0x1b
275 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
276
337 #define MSR_PRP4_LBSTK_TO_4 0x6c4
338 #define MSR_PRP4_LBSTK_TO_5 0x6c5
339 #define MSR_PRP4_LBSTK_TO_6 0x6c6
340 #define MSR_PRP4_LBSTK_TO_7 0x6c7
341 #define MSR_PRP4_LBSTK_TO_8 0x6c8
342 #define MSR_PRP4_LBSTK_TO_9 0x6c9
343 #define MSR_PRP4_LBSTK_TO_10 0x6ca
344 #define MSR_PRP4_LBSTK_TO_11 0x6cb
345 #define MSR_PRP4_LBSTK_TO_12 0x6cc
346 #define MSR_PRP4_LBSTK_TO_13 0x6cd
347 #define MSR_PRP4_LBSTK_TO_14 0x6ce
348 #define MSR_PRP4_LBSTK_TO_15 0x6cf
349
350 /*
351 * Intel IA32_ARCH_CAPABILITIES MSR.
352 */
353 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
354 #define IA32_ARCH_CAP_RDCL_NO 0x0001
355 #define IA32_ARCH_CAP_IBRS_ALL 0x0002
356 #define IA32_ARCH_CAP_RSBA 0x0004
357 #define IA32_ARCH_CAP_SSB_NO 0x0010
358
359 /*
360 * Intel Speculation related MSRs
361 */
362 #define MSR_IA32_SPEC_CTRL 0x48
363 #define IA32_SPEC_CTRL_IBRS 0x01
364 #define IA32_SPEC_CTRL_STIBP 0x02
365 #define IA32_SPEC_CTRL_SSBD 0x04
366
367 #define MSR_IA32_PRED_CMD 0x49
368 #define IA32_PRED_CMD_IBPB 0x01
369
370 #define MCI_CTL_VALUE 0xffffffff
371
372 #define MTRR_TYPE_UC 0
373 #define MTRR_TYPE_WC 1
374 #define MTRR_TYPE_WT 4
375 #define MTRR_TYPE_WP 5
376 #define MTRR_TYPE_WB 6
377 #define MTRR_TYPE_UC_ 7
378
379 /*
380 * For Solaris we set up the page attritubute table in the following way:
381 * PAT0 Write-Back
382 * PAT1 Write-Through
383 * PAT2 Unchacheable-
384 * PAT3 Uncacheable
385 * PAT4 Write-Back
386 * PAT5 Write-Through
387 * PAT6 Write-Combine
388 * PAT7 Uncacheable
389 * The only difference from h/w default is entry 6.
462 #define X86FSET_AVX512FMAPS 61
463 #define X86FSET_XSAVEOPT 62
464 #define X86FSET_XSAVEC 63
465 #define X86FSET_XSAVES 64
466 #define X86FSET_SHA 65
467 #define X86FSET_UMIP 66
468 #define X86FSET_PKU 67
469 #define X86FSET_OSPKE 68
470 #define X86FSET_PCID 69
471 #define X86FSET_INVPCID 70
472 #define X86FSET_IBRS 71
473 #define X86FSET_IBPB 72
474 #define X86FSET_STIBP 73
475 #define X86FSET_SSBD 74
476 #define X86FSET_SSBD_VIRT 75
477 #define X86FSET_RDCL_NO 76
478 #define X86FSET_IBRS_ALL 77
479 #define X86FSET_RSBA 78
480 #define X86FSET_SSB_NO 79
481 #define X86FSET_STIBP_ALL 80
482
483 /*
484 * Intel Deep C-State invariant TSC in leaf 0x80000007.
485 */
486 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
487
488 /*
489 * Intel Deep C-state always-running local APIC timer
490 */
491 #define CPUID_CSTATE_ARAT (0x4)
492
493 /*
494 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
495 */
496 #define CPUID_EPB_SUPPORT (1 << 3)
497
498 /*
499 * Intel TSC deadline timer
500 */
501 #define CPUID_DEADLINE_TSC (1 << 24)
731 #define XFEATURE_PKRU 0x200
732 #define XFEATURE_FP_ALL \
733 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
734 XFEATURE_AVX512 | XFEATURE_PKRU)
735
736 /*
737 * Define the set of xfeature flags that should be considered valid in the xsave
738 * state vector when we initialize an lwp. This is distinct from the full set so
739 * that all of the processor's normal logic and tracking of the xsave state is
740 * usable. This should correspond to the state that's been initialized by the
741 * ABI to hold meaningful values. Adding additional bits here can have serious
742 * performance implications and cause performance degradations when using the
743 * FPU vector (xmm) registers.
744 */
745 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
746
747 #if !defined(_ASM)
748
749 #if defined(_KERNEL) || defined(_KMEMUSER)
750
751 #define NUM_X86_FEATURES 81
752 extern uchar_t x86_featureset[];
753
754 extern void free_x86_featureset(void *featureset);
755 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
756 extern void add_x86_feature(void *featureset, uint_t feature);
757 extern void remove_x86_feature(void *featureset, uint_t feature);
758 extern boolean_t compare_x86_featureset(void *setA, void *setB);
759 extern void print_x86_featureset(void *featureset);
760
761
762 extern uint_t x86_type;
763 extern uint_t x86_vendor;
764 extern uint_t x86_clflush_size;
765
766 extern uint_t pentiumpro_bug4046376;
767
768 extern const char CyrixInstead[];
769
770 #endif
771
|
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright (c) 2019, Joyent, Inc.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 * Copyright 2018 Nexenta Systems, Inc.
35 */
36
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define _SYS_X86_ARCHEXT_H
39
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif /* _ASM */
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
237
238 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
239 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
240 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
241 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
242 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
243
244 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
245 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
246 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
247 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
248 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
249
250 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
251 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
252
253 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
254 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
255 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */
256 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */
257 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */
258 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */
259 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */
260
261 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
262 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
263
264 /*
265 * Intel also uses cpuid leaf 0xd to report additional instructions and features
266 * when the sub-leaf in %ecx == 1. We label these using the same convention as
267 * with leaf 7.
268 */
269 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
270 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
271 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
272
273 #define REG_PAT 0x277
274 #define REG_TSC 0x10 /* timestamp counter */
275 #define REG_APIC_BASE_MSR 0x1b
276 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
277
338 #define MSR_PRP4_LBSTK_TO_4 0x6c4
339 #define MSR_PRP4_LBSTK_TO_5 0x6c5
340 #define MSR_PRP4_LBSTK_TO_6 0x6c6
341 #define MSR_PRP4_LBSTK_TO_7 0x6c7
342 #define MSR_PRP4_LBSTK_TO_8 0x6c8
343 #define MSR_PRP4_LBSTK_TO_9 0x6c9
344 #define MSR_PRP4_LBSTK_TO_10 0x6ca
345 #define MSR_PRP4_LBSTK_TO_11 0x6cb
346 #define MSR_PRP4_LBSTK_TO_12 0x6cc
347 #define MSR_PRP4_LBSTK_TO_13 0x6cd
348 #define MSR_PRP4_LBSTK_TO_14 0x6ce
349 #define MSR_PRP4_LBSTK_TO_15 0x6cf
350
351 /*
352 * Intel IA32_ARCH_CAPABILITIES MSR.
353 */
354 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
355 #define IA32_ARCH_CAP_RDCL_NO 0x0001
356 #define IA32_ARCH_CAP_IBRS_ALL 0x0002
357 #define IA32_ARCH_CAP_RSBA 0x0004
358 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008
359 #define IA32_ARCH_CAP_SSB_NO 0x0010
360
361 /*
362 * Intel Speculation related MSRs
363 */
364 #define MSR_IA32_SPEC_CTRL 0x48
365 #define IA32_SPEC_CTRL_IBRS 0x01
366 #define IA32_SPEC_CTRL_STIBP 0x02
367 #define IA32_SPEC_CTRL_SSBD 0x04
368
369 #define MSR_IA32_PRED_CMD 0x49
370 #define IA32_PRED_CMD_IBPB 0x01
371
372 #define MSR_IA32_FLUSH_CMD 0x10b
373 #define IA32_FLUSH_CMD_L1D 0x01
374
375 #define MCI_CTL_VALUE 0xffffffff
376
377 #define MTRR_TYPE_UC 0
378 #define MTRR_TYPE_WC 1
379 #define MTRR_TYPE_WT 4
380 #define MTRR_TYPE_WP 5
381 #define MTRR_TYPE_WB 6
382 #define MTRR_TYPE_UC_ 7
383
384 /*
385 * For Solaris we set up the page attritubute table in the following way:
386 * PAT0 Write-Back
387 * PAT1 Write-Through
388 * PAT2 Unchacheable-
389 * PAT3 Uncacheable
390 * PAT4 Write-Back
391 * PAT5 Write-Through
392 * PAT6 Write-Combine
393 * PAT7 Uncacheable
394 * The only difference from h/w default is entry 6.
467 #define X86FSET_AVX512FMAPS 61
468 #define X86FSET_XSAVEOPT 62
469 #define X86FSET_XSAVEC 63
470 #define X86FSET_XSAVES 64
471 #define X86FSET_SHA 65
472 #define X86FSET_UMIP 66
473 #define X86FSET_PKU 67
474 #define X86FSET_OSPKE 68
475 #define X86FSET_PCID 69
476 #define X86FSET_INVPCID 70
477 #define X86FSET_IBRS 71
478 #define X86FSET_IBPB 72
479 #define X86FSET_STIBP 73
480 #define X86FSET_SSBD 74
481 #define X86FSET_SSBD_VIRT 75
482 #define X86FSET_RDCL_NO 76
483 #define X86FSET_IBRS_ALL 77
484 #define X86FSET_RSBA 78
485 #define X86FSET_SSB_NO 79
486 #define X86FSET_STIBP_ALL 80
487 #define X86FSET_FLUSH_CMD 81
488 #define X86FSET_L1D_VM_NO 82
489
490 /*
491 * Intel Deep C-State invariant TSC in leaf 0x80000007.
492 */
493 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
494
495 /*
496 * Intel Deep C-state always-running local APIC timer
497 */
498 #define CPUID_CSTATE_ARAT (0x4)
499
500 /*
501 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
502 */
503 #define CPUID_EPB_SUPPORT (1 << 3)
504
505 /*
506 * Intel TSC deadline timer
507 */
508 #define CPUID_DEADLINE_TSC (1 << 24)
738 #define XFEATURE_PKRU 0x200
739 #define XFEATURE_FP_ALL \
740 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
741 XFEATURE_AVX512 | XFEATURE_PKRU)
742
743 /*
744 * Define the set of xfeature flags that should be considered valid in the xsave
745 * state vector when we initialize an lwp. This is distinct from the full set so
746 * that all of the processor's normal logic and tracking of the xsave state is
747 * usable. This should correspond to the state that's been initialized by the
748 * ABI to hold meaningful values. Adding additional bits here can have serious
749 * performance implications and cause performance degradations when using the
750 * FPU vector (xmm) registers.
751 */
752 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
753
754 #if !defined(_ASM)
755
756 #if defined(_KERNEL) || defined(_KMEMUSER)
757
758 #define NUM_X86_FEATURES 83
759 extern uchar_t x86_featureset[];
760
761 extern void free_x86_featureset(void *featureset);
762 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
763 extern void add_x86_feature(void *featureset, uint_t feature);
764 extern void remove_x86_feature(void *featureset, uint_t feature);
765 extern boolean_t compare_x86_featureset(void *setA, void *setB);
766 extern void print_x86_featureset(void *featureset);
767
768
769 extern uint_t x86_type;
770 extern uint_t x86_vendor;
771 extern uint_t x86_clflush_size;
772
773 extern uint_t pentiumpro_bug4046376;
774
775 extern const char CyrixInstead[];
776
777 #endif
778
|