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10208 Add x86 features for L1TF

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          --- old/usr/src/uts/i86pc/os/cpuid.c
          +++ new/usr/src/uts/i86pc/os/cpuid.c
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  25   25   * Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net>
  26   26   */
  27   27  /*
  28   28   * Copyright (c) 2010, Intel Corporation.
  29   29   * All rights reserved.
  30   30   */
  31   31  /*
  32   32   * Portions Copyright 2009 Advanced Micro Devices, Inc.
  33   33   */
  34   34  /*
  35      - * Copyright 2018 Joyent, Inc.
       35 + * Copyright (c) 2019, Joyent, Inc.
  36   36   */
  37   37  /*
  38   38   * Various routines to handle identification
  39   39   * and classification of x86 processors.
  40   40   */
  41   41  
  42   42  #include <sys/types.h>
  43   43  #include <sys/archsystm.h>
  44   44  #include <sys/x86_archext.h>
  45   45  #include <sys/kmem.h>
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 210  210          "invpcid",
 211  211          "ibrs",
 212  212          "ibpb",
 213  213          "stibp",
 214  214          "ssbd",
 215  215          "ssbd_virt",
 216  216          "rdcl_no",
 217  217          "ibrs_all",
 218  218          "rsba",
 219  219          "ssb_no",
 220      -        "stibp_all"
      220 +        "stibp_all",
      221 +        "flush_cmd",
      222 +        "l1d_vmentry_no"
 221  223  };
 222  224  
 223  225  boolean_t
 224  226  is_x86_feature(void *featureset, uint_t feature)
 225  227  {
 226  228          ASSERT(feature < NUM_X86_FEATURES);
 227  229          return (BT_TEST((ulong_t *)featureset, feature));
 228  230  }
 229  231  
 230  232  void
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1044 1046                                              X86FSET_RDCL_NO);
1045 1047                                  }
1046 1048                                  if (reg & IA32_ARCH_CAP_IBRS_ALL) {
1047 1049                                          add_x86_feature(featureset,
1048 1050                                              X86FSET_IBRS_ALL);
1049 1051                                  }
1050 1052                                  if (reg & IA32_ARCH_CAP_RSBA) {
1051 1053                                          add_x86_feature(featureset,
1052 1054                                              X86FSET_RSBA);
1053 1055                                  }
     1056 +                                if (reg & IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) {
     1057 +                                        add_x86_feature(featureset,
     1058 +                                            X86FSET_L1D_VM_NO);
     1059 +                                }
1054 1060                                  if (reg & IA32_ARCH_CAP_SSB_NO) {
1055 1061                                          add_x86_feature(featureset,
1056 1062                                              X86FSET_SSB_NO);
1057 1063                                  }
1058 1064                          }
1059 1065                          no_trap();
1060 1066                  }
1061 1067  #endif  /* !__xpv */
1062 1068  
1063 1069                  if (ecp->cp_edx & CPUID_INTC_EDX_7_0_SSBD)
1064 1070                          add_x86_feature(featureset, X86FSET_SSBD);
     1071 +
     1072 +                if (ecp->cp_edx & CPUID_INTC_EDX_7_0_FLUSH_CMD)
     1073 +                        add_x86_feature(featureset, X86FSET_FLUSH_CMD);
1065 1074          }
1066 1075  }
1067 1076  
1068 1077  /*
1069 1078   * Setup XFeature_Enabled_Mask register. Required by xsave feature.
1070 1079   */
1071 1080  void
1072 1081  setup_xfem(void)
1073 1082  {
1074 1083          uint64_t flags = XFEATURE_LEGACY_FP;
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4116 4125  static const char itlb424_str[] = "itlb-4K-2M-4M";
4117 4126  static const char itlb24_str[] = "itlb-2M-4M";
4118 4127  static const char dtlb44_str[] = "dtlb-4K-4M";
4119 4128  static const char sl1_dcache_str[] = "sectored-l1-dcache";
4120 4129  static const char sl2_cache_str[] = "sectored-l2-cache";
4121 4130  static const char itrace_str[] = "itrace-cache";
4122 4131  static const char sl3_cache_str[] = "sectored-l3-cache";
4123 4132  static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
4124 4133  
4125 4134  static const struct cachetab {
4126      -        uint8_t ct_code;
     4135 +        uint8_t         ct_code;
4127 4136          uint8_t         ct_assoc;
4128 4137          uint16_t        ct_line_size;
4129 4138          size_t          ct_size;
4130 4139          const char      *ct_label;
4131 4140  } intel_ctab[] = {
4132 4141          /*
4133 4142           * maintain descending order!
4134 4143           *
4135 4144           * Codes ignored - Reason
4136 4145           * ----------------------
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