4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 /*
27 * This plugin creates memory configuration nodes and properties in the
28 * PICL tree for Cheetah platforms.
29 *
30 * Subtree of memory-controller in the physical aspect.
31 * memory-controller --- memory-module-group --- memory-module
32 *
33 * Subtree of memory in the logical aspect.
34 * memory --- memory-segment --- memory-bank
35 * Add property _memory-module-group_ at memory-segment referring to the
36 * memory-module-group if InterleaveFactor is one, or at memory-bank
37 * if InterleaveFactor is greater than one.
38 *
39 * Undo strategy:
40 * Create all nodes and properties, or none if it fails in physical and
41 * logical memory tree respectively. It keeps on creating logic
42 * memory tree although it falis on physical logic tree, but no link to
43 * memory module group.
405 for (i = 0; i < nsegments; i++) {
406 mcseg->id = mcmem->segmentids[i].globalid;
407 mcseg->nbanks = nbanks;
408
409 if (ioctl(fd, MCIOC_SEG, mcseg) == -1)
410 break;
411
412 /*
413 * Create memory-segment node under memory node
414 */
415 err = ptree_create_and_add_node(memh, PICL_NAME_MEMORY_SEGMENT,
416 PICL_CLASS_MEMORY_SEGMENT, &msegh);
417 if (err != PICL_SUCCESS)
418 break;
419
420 msegh_info[i] = msegh;
421
422 /*
423 * Add property, Size to memory-segment node
424 */
425 if ((ptree_init_propinfo(&propinfo, PTREE_PROPINFO_VERSION,
426 PICL_PTYPE_UNSIGNED_INT, PICL_READ, sizeof (mcseg->size),
427 PICL_PROP_SIZE, NULL, NULL)) != PICL_SUCCESS)
428 if (err != PICL_SUCCESS)
429 break;
430
431 memsize += mcseg->size;
432 err = ptree_create_and_add_prop(msegh, &propinfo, &mcseg->size,
433 NULL);
434 if (err != PICL_SUCCESS)
435 break;
436
437 /*
438 * Add property, BaseAddress to memory-segment node
439 */
440 err = ptree_init_propinfo(&propinfo, PTREE_PROPINFO_VERSION,
441 PICL_PTYPE_UNSIGNED_INT, PICL_READ, sizeof (mcseg->base),
442 PICL_PROP_BASEADDRESS, NULL, NULL);
443 if (err != PICL_SUCCESS)
444 break;
445
446 err = ptree_create_and_add_prop(msegh, &propinfo, &mcseg->base,
447 NULL);
|
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 *
25 * Copyright (c) 2018, Joyent, Inc.
26 */
27
28 /*
29 * This plugin creates memory configuration nodes and properties in the
30 * PICL tree for Cheetah platforms.
31 *
32 * Subtree of memory-controller in the physical aspect.
33 * memory-controller --- memory-module-group --- memory-module
34 *
35 * Subtree of memory in the logical aspect.
36 * memory --- memory-segment --- memory-bank
37 * Add property _memory-module-group_ at memory-segment referring to the
38 * memory-module-group if InterleaveFactor is one, or at memory-bank
39 * if InterleaveFactor is greater than one.
40 *
41 * Undo strategy:
42 * Create all nodes and properties, or none if it fails in physical and
43 * logical memory tree respectively. It keeps on creating logic
44 * memory tree although it falis on physical logic tree, but no link to
45 * memory module group.
407 for (i = 0; i < nsegments; i++) {
408 mcseg->id = mcmem->segmentids[i].globalid;
409 mcseg->nbanks = nbanks;
410
411 if (ioctl(fd, MCIOC_SEG, mcseg) == -1)
412 break;
413
414 /*
415 * Create memory-segment node under memory node
416 */
417 err = ptree_create_and_add_node(memh, PICL_NAME_MEMORY_SEGMENT,
418 PICL_CLASS_MEMORY_SEGMENT, &msegh);
419 if (err != PICL_SUCCESS)
420 break;
421
422 msegh_info[i] = msegh;
423
424 /*
425 * Add property, Size to memory-segment node
426 */
427 err = ptree_init_propinfo(&propinfo, PTREE_PROPINFO_VERSION,
428 PICL_PTYPE_UNSIGNED_INT, PICL_READ, sizeof (mcseg->size),
429 PICL_PROP_SIZE, NULL, NULL);
430 if (err != PICL_SUCCESS)
431 break;
432
433 memsize += mcseg->size;
434 err = ptree_create_and_add_prop(msegh, &propinfo, &mcseg->size,
435 NULL);
436 if (err != PICL_SUCCESS)
437 break;
438
439 /*
440 * Add property, BaseAddress to memory-segment node
441 */
442 err = ptree_init_propinfo(&propinfo, PTREE_PROPINFO_VERSION,
443 PICL_PTYPE_UNSIGNED_INT, PICL_READ, sizeof (mcseg->base),
444 PICL_PROP_BASEADDRESS, NULL, NULL);
445 if (err != PICL_SUCCESS)
446 break;
447
448 err = ptree_create_and_add_prop(msegh, &propinfo, &mcseg->base,
449 NULL);
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