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10086 ixgbe_m_propinfo() is missing an 'else'
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_gld.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_gld.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21
22 22 /*
23 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
29 29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 - * Copyright (c) 2017, Joyent, Inc.
30 + * Copyright (c) 2018, Joyent, Inc.
31 31 */
32 32
33 33 #include "ixgbe_sw.h"
34 34
35 35 /*
36 36 * Bring the device out of the reset/quiesced state that it
37 37 * was in when the interface was registered.
38 38 */
39 39 int
40 40 ixgbe_m_start(void *arg)
41 41 {
42 42 ixgbe_t *ixgbe = (ixgbe_t *)arg;
43 43
44 44 mutex_enter(&ixgbe->gen_lock);
45 45
46 46 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
47 47 mutex_exit(&ixgbe->gen_lock);
48 48 return (ECANCELED);
49 49 }
50 50
51 51 if (ixgbe_start(ixgbe, B_TRUE) != IXGBE_SUCCESS) {
52 52 mutex_exit(&ixgbe->gen_lock);
53 53 return (EIO);
54 54 }
55 55
56 56 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_STARTED);
57 57
58 58 mutex_exit(&ixgbe->gen_lock);
59 59
60 60 /*
61 61 * Enable and start the watchdog timer
62 62 */
63 63 ixgbe_enable_watchdog_timer(ixgbe);
64 64
65 65 return (0);
66 66 }
67 67
68 68 /*
69 69 * Stop the device and put it in a reset/quiesced state such
70 70 * that the interface can be unregistered.
71 71 */
72 72 void
73 73 ixgbe_m_stop(void *arg)
74 74 {
75 75 ixgbe_t *ixgbe = (ixgbe_t *)arg;
76 76
77 77 mutex_enter(&ixgbe->gen_lock);
78 78
79 79 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
80 80 mutex_exit(&ixgbe->gen_lock);
81 81 return;
82 82 }
83 83
84 84 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_STARTED);
85 85
86 86 ixgbe_stop(ixgbe, B_TRUE);
87 87
88 88 mutex_exit(&ixgbe->gen_lock);
89 89
90 90 /*
91 91 * Disable and stop the watchdog timer
92 92 */
93 93 ixgbe_disable_watchdog_timer(ixgbe);
94 94 }
95 95
96 96 /*
97 97 * Set the promiscuity of the device.
98 98 */
99 99 int
100 100 ixgbe_m_promisc(void *arg, boolean_t on)
101 101 {
102 102 ixgbe_t *ixgbe = (ixgbe_t *)arg;
103 103 uint32_t reg_val;
104 104 struct ixgbe_hw *hw = &ixgbe->hw;
105 105
106 106 mutex_enter(&ixgbe->gen_lock);
107 107
108 108 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
109 109 mutex_exit(&ixgbe->gen_lock);
110 110 return (ECANCELED);
111 111 }
112 112 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
113 113
114 114 if (on)
115 115 reg_val |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
116 116 else
117 117 reg_val &= (~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE));
118 118
119 119 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_FCTRL, reg_val);
120 120
121 121 mutex_exit(&ixgbe->gen_lock);
122 122
123 123 return (0);
124 124 }
125 125
126 126 /*
127 127 * Add/remove the addresses to/from the set of multicast
128 128 * addresses for which the device will receive packets.
129 129 */
130 130 int
131 131 ixgbe_m_multicst(void *arg, boolean_t add, const uint8_t *mcst_addr)
132 132 {
133 133 ixgbe_t *ixgbe = (ixgbe_t *)arg;
134 134 int result;
135 135
136 136 mutex_enter(&ixgbe->gen_lock);
137 137
138 138 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
139 139 mutex_exit(&ixgbe->gen_lock);
140 140 return (ECANCELED);
141 141 }
142 142
143 143 result = (add) ? ixgbe_multicst_add(ixgbe, mcst_addr)
144 144 : ixgbe_multicst_remove(ixgbe, mcst_addr);
145 145
146 146 mutex_exit(&ixgbe->gen_lock);
147 147
148 148 return (result);
149 149 }
150 150
151 151 /*
152 152 * Pass on M_IOCTL messages passed to the DLD, and support
153 153 * private IOCTLs for debugging and ndd.
154 154 */
155 155 void
156 156 ixgbe_m_ioctl(void *arg, queue_t *q, mblk_t *mp)
157 157 {
158 158 ixgbe_t *ixgbe = (ixgbe_t *)arg;
159 159 struct iocblk *iocp;
160 160 enum ioc_reply status;
161 161
162 162 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr;
163 163 iocp->ioc_error = 0;
164 164
165 165 mutex_enter(&ixgbe->gen_lock);
166 166 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
167 167 mutex_exit(&ixgbe->gen_lock);
168 168 miocnak(q, mp, 0, EINVAL);
169 169 return;
170 170 }
171 171 mutex_exit(&ixgbe->gen_lock);
172 172
173 173 switch (iocp->ioc_cmd) {
174 174 case LB_GET_INFO_SIZE:
175 175 case LB_GET_INFO:
176 176 case LB_GET_MODE:
177 177 case LB_SET_MODE:
178 178 status = ixgbe_loopback_ioctl(ixgbe, iocp, mp);
179 179 break;
180 180
181 181 default:
182 182 status = IOC_INVAL;
183 183 break;
184 184 }
185 185
186 186 /*
187 187 * Decide how to reply
188 188 */
189 189 switch (status) {
190 190 default:
191 191 case IOC_INVAL:
192 192 /*
193 193 * Error, reply with a NAK and EINVAL or the specified error
194 194 */
195 195 miocnak(q, mp, 0, iocp->ioc_error == 0 ?
196 196 EINVAL : iocp->ioc_error);
197 197 break;
198 198
199 199 case IOC_DONE:
200 200 /*
201 201 * OK, reply already sent
202 202 */
203 203 break;
204 204
205 205 case IOC_ACK:
206 206 /*
207 207 * OK, reply with an ACK
208 208 */
209 209 miocack(q, mp, 0, 0);
210 210 break;
211 211
212 212 case IOC_REPLY:
213 213 /*
214 214 * OK, send prepared reply as ACK or NAK
215 215 */
216 216 mp->b_datap->db_type = iocp->ioc_error == 0 ?
217 217 M_IOCACK : M_IOCNAK;
218 218 qreply(q, mp);
219 219 break;
220 220 }
221 221 }
222 222
223 223 static int
224 224 ixgbe_led_set(void *arg, mac_led_mode_t mode, uint_t flags)
225 225 {
226 226 ixgbe_t *ixgbe = arg;
227 227 struct ixgbe_hw *hw = &ixgbe->hw;
228 228 uint32_t lidx = ixgbe->ixgbe_led_index;
229 229
230 230 if (flags != 0)
231 231 return (EINVAL);
232 232
233 233 if (mode != MAC_LED_DEFAULT &&
234 234 mode != MAC_LED_IDENT &&
235 235 mode != MAC_LED_OFF &&
236 236 mode != MAC_LED_ON)
237 237 return (ENOTSUP);
238 238
239 239 if (ixgbe->ixgbe_led_blink && mode != MAC_LED_IDENT) {
240 240 if (ixgbe_blink_led_stop(hw, lidx) != IXGBE_SUCCESS) {
241 241 return (EIO);
242 242 }
243 243 ixgbe->ixgbe_led_blink = B_FALSE;
244 244 }
245 245
246 246 if (mode != MAC_LED_DEFAULT && !ixgbe->ixgbe_led_active) {
247 247 ixgbe->ixgbe_led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
248 248 ixgbe->ixgbe_led_active = B_TRUE;
249 249 }
250 250
251 251 switch (mode) {
252 252 case MAC_LED_DEFAULT:
253 253 if (ixgbe->ixgbe_led_active) {
254 254 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ixgbe->ixgbe_led_reg);
255 255 ixgbe->ixgbe_led_active = B_FALSE;
256 256 }
257 257 break;
258 258 case MAC_LED_IDENT:
259 259 if (ixgbe_blink_led_start(hw, lidx) != IXGBE_SUCCESS)
260 260 return (EIO);
261 261 ixgbe->ixgbe_led_blink = B_TRUE;
262 262 break;
263 263 case MAC_LED_OFF:
264 264 if (ixgbe_led_off(hw, lidx) != IXGBE_SUCCESS)
265 265 return (EIO);
266 266 break;
267 267 case MAC_LED_ON:
268 268 if (ixgbe_led_on(hw, lidx) != IXGBE_SUCCESS)
269 269 return (EIO);
270 270 break;
271 271 default:
272 272 return (ENOTSUP);
273 273 }
274 274
275 275 return (0);
276 276 }
277 277
278 278 /*
279 279 * Obtain the MAC's capabilities and associated data from
280 280 * the driver.
281 281 */
282 282 boolean_t
283 283 ixgbe_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
284 284 {
285 285 ixgbe_t *ixgbe = (ixgbe_t *)arg;
286 286
287 287 switch (cap) {
288 288 case MAC_CAPAB_HCKSUM: {
289 289 uint32_t *tx_hcksum_flags = cap_data;
290 290
291 291 /*
292 292 * We advertise our capabilities only if tx hcksum offload is
293 293 * enabled. On receive, the stack will accept checksummed
294 294 * packets anyway, even if we haven't said we can deliver
295 295 * them.
296 296 */
297 297 if (!ixgbe->tx_hcksum_enable)
298 298 return (B_FALSE);
299 299
300 300 *tx_hcksum_flags = HCKSUM_INET_PARTIAL | HCKSUM_IPHDRCKSUM;
301 301 break;
302 302 }
303 303 case MAC_CAPAB_LSO: {
304 304 mac_capab_lso_t *cap_lso = cap_data;
305 305
306 306 if (ixgbe->lso_enable) {
307 307 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4;
308 308 cap_lso->lso_basic_tcp_ipv4.lso_max = IXGBE_LSO_MAXLEN;
309 309 break;
310 310 } else {
311 311 return (B_FALSE);
312 312 }
313 313 }
314 314 case MAC_CAPAB_RINGS: {
315 315 mac_capab_rings_t *cap_rings = cap_data;
316 316
317 317 switch (cap_rings->mr_type) {
318 318 case MAC_RING_TYPE_RX:
319 319 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
320 320 cap_rings->mr_rnum = ixgbe->num_rx_rings;
321 321 cap_rings->mr_gnum = ixgbe->num_rx_groups;
322 322 cap_rings->mr_rget = ixgbe_fill_ring;
323 323 cap_rings->mr_gget = ixgbe_fill_group;
324 324 cap_rings->mr_gaddring = NULL;
325 325 cap_rings->mr_gremring = NULL;
326 326 break;
327 327 case MAC_RING_TYPE_TX:
328 328 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
329 329 cap_rings->mr_rnum = ixgbe->num_tx_rings;
330 330 cap_rings->mr_gnum = 0;
331 331 cap_rings->mr_rget = ixgbe_fill_ring;
332 332 cap_rings->mr_gget = NULL;
333 333 break;
334 334 default:
335 335 break;
336 336 }
337 337 break;
338 338 }
339 339 case MAC_CAPAB_TRANSCEIVER: {
340 340 mac_capab_transceiver_t *mct = cap_data;
341 341
342 342 /*
343 343 * Rather than try and guess based on the media type whether or
344 344 * not we have a transceiver we can read, we instead will let
345 345 * the actual function calls figure that out for us.
346 346 */
347 347 mct->mct_flags = 0;
348 348 mct->mct_ntransceivers = 1;
349 349 mct->mct_info = ixgbe_transceiver_info;
350 350 mct->mct_read = ixgbe_transceiver_read;
351 351 return (B_TRUE);
352 352 }
353 353 case MAC_CAPAB_LED: {
354 354 mac_capab_led_t *mcl = cap_data;
355 355
356 356 mcl->mcl_flags = 0;
357 357 mcl->mcl_modes = MAC_LED_DEFAULT | MAC_LED_ON | MAC_LED_OFF |
358 358 MAC_LED_IDENT;
359 359 mcl->mcl_set = ixgbe_led_set;
360 360 break;
361 361
362 362 }
363 363 default:
364 364 return (B_FALSE);
365 365 }
366 366 return (B_TRUE);
367 367 }
368 368
369 369 int
370 370 ixgbe_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num,
371 371 uint_t pr_valsize, const void *pr_val)
372 372 {
373 373 ixgbe_t *ixgbe = (ixgbe_t *)arg;
374 374 struct ixgbe_hw *hw = &ixgbe->hw;
375 375 int err = 0;
376 376 uint32_t flow_control;
377 377 uint32_t cur_mtu, new_mtu;
378 378 uint32_t rx_size;
379 379 uint32_t tx_size;
380 380 ixgbe_link_speed speeds = 0;
381 381
382 382 mutex_enter(&ixgbe->gen_lock);
383 383 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
384 384 mutex_exit(&ixgbe->gen_lock);
385 385 return (ECANCELED);
386 386 }
387 387
388 388 /*
389 389 * We cannot always rely on the common code maintaining
390 390 * hw->phy.speeds_supported, therefore we fall back to use the recorded
391 391 * supported speeds which were obtained during instance init in
392 392 * ixgbe_init_params().
393 393 */
394 394 speeds = hw->phy.speeds_supported;
395 395 if (speeds == 0)
396 396 speeds = ixgbe->speeds_supported;
397 397
398 398 if (ixgbe->loopback_mode != IXGBE_LB_NONE &&
399 399 ixgbe_param_locked(pr_num)) {
400 400 /*
401 401 * All en_* parameters are locked (read-only)
402 402 * while the device is in any sort of loopback mode.
403 403 */
404 404 mutex_exit(&ixgbe->gen_lock);
405 405 return (EBUSY);
406 406 }
407 407
408 408 /*
409 409 * We allow speed changes only on baseT PHYs. MAC_PROP_EN_* are marked
410 410 * read-only on non-baseT PHYs.
411 411 */
412 412 switch (pr_num) {
413 413 case MAC_PROP_EN_10GFDX_CAP:
414 414 if (hw->phy.media_type == ixgbe_media_type_copper &&
415 415 speeds & IXGBE_LINK_SPEED_10GB_FULL) {
416 416 ixgbe->param_en_10000fdx_cap = *(uint8_t *)pr_val;
417 417 goto setup_link;
418 418 } else {
419 419 err = ENOTSUP;
420 420 break;
421 421 }
422 422 case MAC_PROP_EN_5000FDX_CAP:
423 423 if (hw->phy.media_type == ixgbe_media_type_copper &&
424 424 speeds & IXGBE_LINK_SPEED_5GB_FULL) {
425 425 ixgbe->param_en_5000fdx_cap = *(uint8_t *)pr_val;
426 426 goto setup_link;
427 427 } else {
428 428 err = ENOTSUP;
429 429 break;
430 430 }
431 431 case MAC_PROP_EN_2500FDX_CAP:
432 432 if (hw->phy.media_type == ixgbe_media_type_copper &&
433 433 speeds & IXGBE_LINK_SPEED_2_5GB_FULL) {
434 434 ixgbe->param_en_2500fdx_cap = *(uint8_t *)pr_val;
435 435 goto setup_link;
436 436 } else {
437 437 err = ENOTSUP;
438 438 break;
439 439 }
440 440 case MAC_PROP_EN_1000FDX_CAP:
441 441 if (hw->phy.media_type == ixgbe_media_type_copper &&
442 442 speeds & IXGBE_LINK_SPEED_1GB_FULL) {
443 443 ixgbe->param_en_1000fdx_cap = *(uint8_t *)pr_val;
444 444 goto setup_link;
445 445 } else {
446 446 err = ENOTSUP;
447 447 break;
448 448 }
449 449 case MAC_PROP_EN_100FDX_CAP:
450 450 if (hw->phy.media_type == ixgbe_media_type_copper &&
451 451 speeds & IXGBE_LINK_SPEED_100_FULL) {
452 452 ixgbe->param_en_100fdx_cap = *(uint8_t *)pr_val;
453 453 goto setup_link;
454 454 } else {
455 455 err = ENOTSUP;
456 456 break;
457 457 }
458 458 case MAC_PROP_AUTONEG:
459 459 if (ixgbe->hw.phy.media_type != ixgbe_media_type_copper) {
460 460 err = ENOTSUP;
461 461 break;
462 462 } else {
463 463 ixgbe->param_adv_autoneg_cap = *(uint8_t *)pr_val;
464 464 goto setup_link;
465 465 }
466 466 case MAC_PROP_FLOWCTRL:
467 467 bcopy(pr_val, &flow_control, sizeof (flow_control));
468 468
469 469 switch (flow_control) {
470 470 default:
471 471 err = EINVAL;
472 472 break;
473 473 case LINK_FLOWCTRL_NONE:
474 474 hw->fc.requested_mode = ixgbe_fc_none;
475 475 break;
476 476 case LINK_FLOWCTRL_RX:
477 477 hw->fc.requested_mode = ixgbe_fc_rx_pause;
478 478 break;
479 479 case LINK_FLOWCTRL_TX:
480 480 hw->fc.requested_mode = ixgbe_fc_tx_pause;
481 481 break;
482 482 case LINK_FLOWCTRL_BI:
483 483 hw->fc.requested_mode = ixgbe_fc_full;
484 484 break;
485 485 }
486 486 setup_link:
487 487 if (err == 0) {
488 488 if (ixgbe_driver_setup_link(ixgbe, B_TRUE) !=
489 489 IXGBE_SUCCESS)
490 490 err = EINVAL;
491 491 }
492 492 break;
493 493 case MAC_PROP_ADV_10GFDX_CAP:
494 494 case MAC_PROP_ADV_5000FDX_CAP:
495 495 case MAC_PROP_ADV_2500FDX_CAP:
496 496 case MAC_PROP_ADV_1000FDX_CAP:
497 497 case MAC_PROP_ADV_100FDX_CAP:
498 498 case MAC_PROP_STATUS:
499 499 case MAC_PROP_SPEED:
500 500 case MAC_PROP_DUPLEX:
501 501 err = ENOTSUP; /* read-only prop. Can't set this. */
502 502 break;
503 503 case MAC_PROP_MTU:
504 504 cur_mtu = ixgbe->default_mtu;
505 505 bcopy(pr_val, &new_mtu, sizeof (new_mtu));
506 506 if (new_mtu == cur_mtu) {
507 507 err = 0;
508 508 break;
509 509 }
510 510
511 511 if (new_mtu < DEFAULT_MTU || new_mtu > ixgbe->capab->max_mtu) {
512 512 err = EINVAL;
513 513 break;
514 514 }
515 515
516 516 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
517 517 err = EBUSY;
518 518 break;
519 519 }
520 520
521 521 err = mac_maxsdu_update(ixgbe->mac_hdl, new_mtu);
522 522 if (err == 0) {
523 523 ixgbe->default_mtu = new_mtu;
524 524 ixgbe->max_frame_size = ixgbe->default_mtu +
525 525 sizeof (struct ether_vlan_header) + ETHERFCSL;
526 526
527 527 /*
528 528 * Set rx buffer size
529 529 */
530 530 rx_size = ixgbe->max_frame_size + IPHDR_ALIGN_ROOM;
531 531 ixgbe->rx_buf_size = ((rx_size >> 10) + ((rx_size &
532 532 (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
533 533
534 534 /*
535 535 * Set tx buffer size
536 536 */
537 537 tx_size = ixgbe->max_frame_size;
538 538 ixgbe->tx_buf_size = ((tx_size >> 10) + ((tx_size &
539 539 (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
540 540 }
541 541 break;
542 542 case MAC_PROP_PRIVATE:
543 543 err = ixgbe_set_priv_prop(ixgbe, pr_name, pr_valsize, pr_val);
544 544 break;
545 545 default:
546 546 err = ENOTSUP;
547 547 break;
548 548 }
549 549 mutex_exit(&ixgbe->gen_lock);
550 550 return (err);
551 551 }
552 552
553 553 int
554 554 ixgbe_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num,
555 555 uint_t pr_valsize, void *pr_val)
556 556 {
557 557 ixgbe_t *ixgbe = (ixgbe_t *)arg;
558 558 struct ixgbe_hw *hw = &ixgbe->hw;
559 559 int err = 0;
560 560 uint32_t flow_control;
561 561 uint64_t tmp = 0;
562 562 ixgbe_link_speed speeds = 0;
563 563
564 564 /*
565 565 * We cannot always rely on the common code maintaining
566 566 * hw->phy.speeds_supported, therefore we fall back to use the recorded
567 567 * supported speeds which were obtained during instance init in
568 568 * ixgbe_init_params().
569 569 */
570 570 speeds = hw->phy.speeds_supported;
571 571 if (speeds == 0)
572 572 speeds = ixgbe->speeds_supported;
573 573
574 574 switch (pr_num) {
575 575 case MAC_PROP_DUPLEX:
576 576 ASSERT(pr_valsize >= sizeof (link_duplex_t));
577 577 bcopy(&ixgbe->link_duplex, pr_val,
578 578 sizeof (link_duplex_t));
579 579 break;
580 580 case MAC_PROP_SPEED:
581 581 ASSERT(pr_valsize >= sizeof (uint64_t));
582 582 tmp = ixgbe->link_speed * 1000000ull;
583 583 bcopy(&tmp, pr_val, sizeof (tmp));
584 584 break;
585 585 case MAC_PROP_AUTONEG:
586 586 *(uint8_t *)pr_val = ixgbe->param_adv_autoneg_cap;
587 587 break;
588 588 case MAC_PROP_FLOWCTRL:
589 589 ASSERT(pr_valsize >= sizeof (uint32_t));
590 590
591 591 switch (hw->fc.requested_mode) {
592 592 case ixgbe_fc_none:
593 593 flow_control = LINK_FLOWCTRL_NONE;
594 594 break;
595 595 case ixgbe_fc_rx_pause:
596 596 flow_control = LINK_FLOWCTRL_RX;
597 597 break;
598 598 case ixgbe_fc_tx_pause:
599 599 flow_control = LINK_FLOWCTRL_TX;
600 600 break;
601 601 case ixgbe_fc_full:
602 602 flow_control = LINK_FLOWCTRL_BI;
603 603 break;
604 604 }
605 605 bcopy(&flow_control, pr_val, sizeof (flow_control));
606 606 break;
607 607 case MAC_PROP_ADV_10GFDX_CAP:
608 608 if (speeds & IXGBE_LINK_SPEED_10GB_FULL)
609 609 *(uint8_t *)pr_val = ixgbe->param_adv_10000fdx_cap;
610 610 else
611 611 err = ENOTSUP;
612 612 break;
613 613 case MAC_PROP_EN_10GFDX_CAP:
614 614 if (speeds & IXGBE_LINK_SPEED_10GB_FULL)
615 615 *(uint8_t *)pr_val = ixgbe->param_en_10000fdx_cap;
616 616 else
617 617 err = ENOTSUP;
618 618 break;
619 619 case MAC_PROP_ADV_5000FDX_CAP:
620 620 if (speeds & IXGBE_LINK_SPEED_5GB_FULL)
621 621 *(uint8_t *)pr_val = ixgbe->param_adv_5000fdx_cap;
622 622 else
623 623 err = ENOTSUP;
624 624 break;
625 625 case MAC_PROP_EN_5000FDX_CAP:
626 626 if (speeds & IXGBE_LINK_SPEED_5GB_FULL)
627 627 *(uint8_t *)pr_val = ixgbe->param_en_5000fdx_cap;
628 628 else
629 629 err = ENOTSUP;
630 630 break;
631 631 case MAC_PROP_ADV_2500FDX_CAP:
632 632 if (speeds & IXGBE_LINK_SPEED_2_5GB_FULL)
633 633 *(uint8_t *)pr_val = ixgbe->param_adv_2500fdx_cap;
634 634 else
635 635 err = ENOTSUP;
636 636 break;
637 637 case MAC_PROP_EN_2500FDX_CAP:
638 638 if (speeds & IXGBE_LINK_SPEED_2_5GB_FULL)
639 639 *(uint8_t *)pr_val = ixgbe->param_en_2500fdx_cap;
640 640 else
641 641 err = ENOTSUP;
642 642 break;
643 643 case MAC_PROP_ADV_1000FDX_CAP:
644 644 if (speeds & IXGBE_LINK_SPEED_1GB_FULL)
645 645 *(uint8_t *)pr_val = ixgbe->param_adv_1000fdx_cap;
646 646 else
647 647 err = ENOTSUP;
648 648 break;
649 649 case MAC_PROP_EN_1000FDX_CAP:
650 650 if (speeds & IXGBE_LINK_SPEED_1GB_FULL)
651 651 *(uint8_t *)pr_val = ixgbe->param_en_1000fdx_cap;
652 652 else
653 653 err = ENOTSUP;
654 654 break;
655 655 case MAC_PROP_ADV_100FDX_CAP:
656 656 if (speeds & IXGBE_LINK_SPEED_100_FULL)
657 657 *(uint8_t *)pr_val = ixgbe->param_adv_100fdx_cap;
658 658 else
659 659 err = ENOTSUP;
660 660 break;
661 661 case MAC_PROP_EN_100FDX_CAP:
662 662 if (speeds & IXGBE_LINK_SPEED_100_FULL)
663 663 *(uint8_t *)pr_val = ixgbe->param_en_100fdx_cap;
664 664 else
665 665 err = ENOTSUP;
666 666 break;
667 667 case MAC_PROP_PRIVATE:
668 668 err = ixgbe_get_priv_prop(ixgbe, pr_name,
669 669 pr_valsize, pr_val);
670 670 break;
671 671 default:
672 672 err = ENOTSUP;
673 673 break;
674 674 }
675 675 return (err);
676 676 }
677 677
678 678 void
679 679 ixgbe_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num,
680 680 mac_prop_info_handle_t prh)
681 681 {
682 682 ixgbe_t *ixgbe = (ixgbe_t *)arg;
683 683 struct ixgbe_hw *hw = &ixgbe->hw;
684 684 uint_t perm;
685 685 uint8_t value;
686 686 ixgbe_link_speed speeds = 0;
687 687
688 688 /*
689 689 * We cannot always rely on the common code maintaining
690 690 * hw->phy.speeds_supported, therefore we fall back to use the
691 691 * recorded supported speeds which were obtained during instance init in
692 692 * ixgbe_init_params().
693 693 */
694 694 speeds = hw->phy.speeds_supported;
695 695 if (speeds == 0)
696 696 speeds = ixgbe->speeds_supported;
697 697
698 698 switch (pr_num) {
699 699 case MAC_PROP_DUPLEX:
700 700 case MAC_PROP_SPEED:
701 701 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
702 702 break;
703 703
704 704 case MAC_PROP_ADV_100FDX_CAP:
705 705 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
706 706 value = (speeds & IXGBE_LINK_SPEED_100_FULL) ? 1 : 0;
707 707 mac_prop_info_set_default_uint8(prh, value);
708 708 break;
709 709
710 710 case MAC_PROP_ADV_1000FDX_CAP:
711 711 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
712 712 value = (speeds & IXGBE_LINK_SPEED_1GB_FULL) ? 1 : 0;
713 713 mac_prop_info_set_default_uint8(prh, value);
714 714 break;
715 715
716 716 case MAC_PROP_ADV_2500FDX_CAP:
717 717 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
718 718 value = (speeds & IXGBE_LINK_SPEED_2_5GB_FULL) ? 1 : 0;
719 719 mac_prop_info_set_default_uint8(prh, value);
720 720 break;
721 721
722 722 case MAC_PROP_ADV_5000FDX_CAP:
723 723 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
724 724 value = (speeds & IXGBE_LINK_SPEED_5GB_FULL) ? 1 : 0;
725 725 mac_prop_info_set_default_uint8(prh, value);
726 726 break;
727 727
728 728 case MAC_PROP_ADV_10GFDX_CAP:
729 729 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
730 730 value = (speeds & IXGBE_LINK_SPEED_10GB_FULL) ? 1 : 0;
731 731 mac_prop_info_set_default_uint8(prh, value);
732 732 break;
733 733
734 734 /*
735 735 * We allow speed changes only on baseT PHYs. MAC_PROP_EN_* are marked
736 736 * read-only on non-baseT (SFP) PHYs.
737 737 */
738 738 case MAC_PROP_AUTONEG:
739 739 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
740 740 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
741 741 mac_prop_info_set_perm(prh, perm);
742 742 mac_prop_info_set_default_uint8(prh, 1);
743 743 break;
744 744
745 745 case MAC_PROP_EN_10GFDX_CAP:
746 746 if (speeds & IXGBE_LINK_SPEED_10GB_FULL) {
747 747 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
748 748 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
749 749 mac_prop_info_set_perm(prh, perm);
750 750 mac_prop_info_set_default_uint8(prh, 1);
751 751 }
752 752 break;
753 753
754 754 case MAC_PROP_EN_5000FDX_CAP:
755 755 if (speeds & IXGBE_LINK_SPEED_5GB_FULL) {
756 756 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
757 757 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
758 758 mac_prop_info_set_perm(prh, perm);
759 759 mac_prop_info_set_default_uint8(prh, 1);
760 760 }
761 761 break;
762 762
763 763 case MAC_PROP_EN_2500FDX_CAP:
764 764 if (speeds & IXGBE_LINK_SPEED_2_5GB_FULL) {
765 765 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
766 766 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
767 767 mac_prop_info_set_perm(prh, perm);
768 768 mac_prop_info_set_default_uint8(prh, 1);
769 769 }
770 770 break;
771 771
772 772 case MAC_PROP_EN_1000FDX_CAP:
773 773 if (speeds & IXGBE_LINK_SPEED_1GB_FULL) {
774 774 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
775 775 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
776 776 mac_prop_info_set_perm(prh, perm);
777 777 mac_prop_info_set_default_uint8(prh, 1);
778 778 }
779 779 break;
780 780
781 781 case MAC_PROP_EN_100FDX_CAP:
782 782 if (speeds & IXGBE_LINK_SPEED_100_FULL) {
783 783 perm = (hw->phy.media_type == ixgbe_media_type_copper) ?
784 784 MAC_PROP_PERM_RW : MAC_PROP_PERM_READ;
785 785 mac_prop_info_set_perm(prh, perm);
786 786 mac_prop_info_set_default_uint8(prh, 1);
787 787 }
788 788 break;
789 789
790 790 case MAC_PROP_FLOWCTRL:
791 791 mac_prop_info_set_default_link_flowctrl(prh,
792 792 LINK_FLOWCTRL_NONE);
793 793 break;
794 794
795 795 case MAC_PROP_MTU:
796 796 mac_prop_info_set_range_uint32(prh,
797 797 DEFAULT_MTU, ixgbe->capab->max_mtu);
798 798 break;
799 799
800 800 case MAC_PROP_PRIVATE: {
801 801 char valstr[64];
802 802 int value;
803 803
804 804 bzero(valstr, sizeof (valstr));
805 805
806 806 if (strcmp(pr_name, "_adv_pause_cap") == 0 ||
807 807 strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
808 808 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
809 809 return;
810 810 }
811 811
812 812 if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
813 813 value = DEFAULT_TX_COPY_THRESHOLD;
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814 814 } else if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
815 815 value = DEFAULT_TX_RECYCLE_THRESHOLD;
816 816 } else if (strcmp(pr_name, "_tx_overload_thresh") == 0) {
817 817 value = DEFAULT_TX_OVERLOAD_THRESHOLD;
818 818 } else if (strcmp(pr_name, "_tx_resched_thresh") == 0) {
819 819 value = DEFAULT_TX_RESCHED_THRESHOLD;
820 820 } else if (strcmp(pr_name, "_rx_copy_thresh") == 0) {
821 821 value = DEFAULT_RX_COPY_THRESHOLD;
822 822 } else if (strcmp(pr_name, "_rx_limit_per_intr") == 0) {
823 823 value = DEFAULT_RX_LIMIT_PER_INTR;
824 - } if (strcmp(pr_name, "_intr_throttling") == 0) {
824 + } else if (strcmp(pr_name, "_intr_throttling") == 0) {
825 825 value = ixgbe->capab->def_intr_throttle;
826 826 } else {
827 827 return;
828 828 }
829 829
830 830 (void) snprintf(valstr, sizeof (valstr), "%x", value);
831 831 }
832 832 }
833 833 }
834 834
835 835 boolean_t
836 836 ixgbe_param_locked(mac_prop_id_t pr_num)
837 837 {
838 838 /*
839 839 * All en_* parameters are locked (read-only) while
840 840 * the device is in any sort of loopback mode ...
841 841 */
842 842 switch (pr_num) {
843 843 case MAC_PROP_EN_10GFDX_CAP:
844 844 case MAC_PROP_EN_5000FDX_CAP:
845 845 case MAC_PROP_EN_2500FDX_CAP:
846 846 case MAC_PROP_EN_1000FDX_CAP:
847 847 case MAC_PROP_EN_100FDX_CAP:
848 848 case MAC_PROP_AUTONEG:
849 849 case MAC_PROP_FLOWCTRL:
850 850 return (B_TRUE);
851 851 }
852 852 return (B_FALSE);
853 853 }
854 854
855 855 /* ARGSUSED */
856 856 int
857 857 ixgbe_set_priv_prop(ixgbe_t *ixgbe, const char *pr_name,
858 858 uint_t pr_valsize, const void *pr_val)
859 859 {
860 860 int err = 0;
861 861 long result;
862 862 struct ixgbe_hw *hw = &ixgbe->hw;
863 863 int i;
864 864
865 865 if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
866 866 if (pr_val == NULL) {
867 867 err = EINVAL;
868 868 return (err);
869 869 }
870 870 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
871 871 if (result < MIN_TX_COPY_THRESHOLD ||
872 872 result > MAX_TX_COPY_THRESHOLD)
873 873 err = EINVAL;
874 874 else {
875 875 ixgbe->tx_copy_thresh = (uint32_t)result;
876 876 }
877 877 return (err);
878 878 }
879 879 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
880 880 if (pr_val == NULL) {
881 881 err = EINVAL;
882 882 return (err);
883 883 }
884 884 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
885 885 if (result < MIN_TX_RECYCLE_THRESHOLD ||
886 886 result > MAX_TX_RECYCLE_THRESHOLD)
887 887 err = EINVAL;
888 888 else {
889 889 ixgbe->tx_recycle_thresh = (uint32_t)result;
890 890 }
891 891 return (err);
892 892 }
893 893 if (strcmp(pr_name, "_tx_overload_thresh") == 0) {
894 894 if (pr_val == NULL) {
895 895 err = EINVAL;
896 896 return (err);
897 897 }
898 898 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
899 899 if (result < MIN_TX_OVERLOAD_THRESHOLD ||
900 900 result > MAX_TX_OVERLOAD_THRESHOLD)
901 901 err = EINVAL;
902 902 else {
903 903 ixgbe->tx_overload_thresh = (uint32_t)result;
904 904 }
905 905 return (err);
906 906 }
907 907 if (strcmp(pr_name, "_tx_resched_thresh") == 0) {
908 908 if (pr_val == NULL) {
909 909 err = EINVAL;
910 910 return (err);
911 911 }
912 912 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
913 913 if (result < MIN_TX_RESCHED_THRESHOLD ||
914 914 result > MAX_TX_RESCHED_THRESHOLD)
915 915 err = EINVAL;
916 916 else {
917 917 ixgbe->tx_resched_thresh = (uint32_t)result;
918 918 }
919 919 return (err);
920 920 }
921 921 if (strcmp(pr_name, "_rx_copy_thresh") == 0) {
922 922 if (pr_val == NULL) {
923 923 err = EINVAL;
924 924 return (err);
925 925 }
926 926 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
927 927 if (result < MIN_RX_COPY_THRESHOLD ||
928 928 result > MAX_RX_COPY_THRESHOLD)
929 929 err = EINVAL;
930 930 else {
931 931 ixgbe->rx_copy_thresh = (uint32_t)result;
932 932 }
933 933 return (err);
934 934 }
935 935 if (strcmp(pr_name, "_rx_limit_per_intr") == 0) {
936 936 if (pr_val == NULL) {
937 937 err = EINVAL;
938 938 return (err);
939 939 }
940 940 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
941 941 if (result < MIN_RX_LIMIT_PER_INTR ||
942 942 result > MAX_RX_LIMIT_PER_INTR)
943 943 err = EINVAL;
944 944 else {
945 945 ixgbe->rx_limit_per_intr = (uint32_t)result;
946 946 }
947 947 return (err);
948 948 }
949 949 if (strcmp(pr_name, "_intr_throttling") == 0) {
950 950 if (pr_val == NULL) {
951 951 err = EINVAL;
952 952 return (err);
953 953 }
954 954 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
955 955
956 956 if (result < ixgbe->capab->min_intr_throttle ||
957 957 result > ixgbe->capab->max_intr_throttle)
958 958 err = EINVAL;
959 959 else {
960 960 ixgbe->intr_throttling[0] = (uint32_t)result;
961 961
962 962 /*
963 963 * 82599, X540 and X550 require the interrupt throttling
964 964 * rate is a multiple of 8. This is enforced by the
965 965 * register definiton.
966 966 */
967 967 if (hw->mac.type == ixgbe_mac_82599EB ||
968 968 hw->mac.type == ixgbe_mac_X540 ||
969 969 hw->mac.type == ixgbe_mac_X550 ||
970 970 hw->mac.type == ixgbe_mac_X550EM_x) {
971 971 ixgbe->intr_throttling[0] =
972 972 ixgbe->intr_throttling[0] & 0xFF8;
973 973 }
974 974
975 975 for (i = 0; i < MAX_INTR_VECTOR; i++)
976 976 ixgbe->intr_throttling[i] =
977 977 ixgbe->intr_throttling[0];
978 978
979 979 /* Set interrupt throttling rate */
980 980 for (i = 0; i < ixgbe->intr_cnt; i++)
981 981 IXGBE_WRITE_REG(hw, IXGBE_EITR(i),
982 982 ixgbe->intr_throttling[i]);
983 983 }
984 984 return (err);
985 985 }
986 986 return (ENOTSUP);
987 987 }
988 988
989 989 int
990 990 ixgbe_get_priv_prop(ixgbe_t *ixgbe, const char *pr_name,
991 991 uint_t pr_valsize, void *pr_val)
992 992 {
993 993 int err = ENOTSUP;
994 994 int value;
995 995
996 996 if (strcmp(pr_name, "_adv_pause_cap") == 0) {
997 997 value = ixgbe->param_adv_pause_cap;
998 998 err = 0;
999 999 goto done;
1000 1000 }
1001 1001 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
1002 1002 value = ixgbe->param_adv_asym_pause_cap;
1003 1003 err = 0;
1004 1004 goto done;
1005 1005 }
1006 1006 if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
1007 1007 value = ixgbe->tx_copy_thresh;
1008 1008 err = 0;
1009 1009 goto done;
1010 1010 }
1011 1011 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
1012 1012 value = ixgbe->tx_recycle_thresh;
1013 1013 err = 0;
1014 1014 goto done;
1015 1015 }
1016 1016 if (strcmp(pr_name, "_tx_overload_thresh") == 0) {
1017 1017 value = ixgbe->tx_overload_thresh;
1018 1018 err = 0;
1019 1019 goto done;
1020 1020 }
1021 1021 if (strcmp(pr_name, "_tx_resched_thresh") == 0) {
1022 1022 value = ixgbe->tx_resched_thresh;
1023 1023 err = 0;
1024 1024 goto done;
1025 1025 }
1026 1026 if (strcmp(pr_name, "_rx_copy_thresh") == 0) {
1027 1027 value = ixgbe->rx_copy_thresh;
1028 1028 err = 0;
1029 1029 goto done;
1030 1030 }
1031 1031 if (strcmp(pr_name, "_rx_limit_per_intr") == 0) {
1032 1032 value = ixgbe->rx_limit_per_intr;
1033 1033 err = 0;
1034 1034 goto done;
1035 1035 }
1036 1036 if (strcmp(pr_name, "_intr_throttling") == 0) {
1037 1037 value = ixgbe->intr_throttling[0];
1038 1038 err = 0;
1039 1039 goto done;
1040 1040 }
1041 1041 done:
1042 1042 if (err == 0) {
1043 1043 (void) snprintf(pr_val, pr_valsize, "%d", value);
1044 1044 }
1045 1045 return (err);
1046 1046 }
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