164 #define RRD_PROD_SHIFT 0
165
166 /*
167 * All descriptors and CMB/SMB share the same high address.
168 */
169 #define L1_DESC_ADDR_HI 0x1540
170 #define L1_DESC_RD_ADDR_LO 0x1544
171 #define L1_DESC_RRD_ADDR_LO 0x1548
172 #define L1_DESC_TPD_ADDR_LO 0x154C
173 #define L1_DESC_CMB_ADDR_LO 0x1550
174 #define L1_DESC_SMB_ADDR_LO 0x1554
175 #define L1_DESC_RRD_RD_CNT 0x1558
176 #define DESC_RRD_CNT_SHIFT 16
177 #define DESC_RRD_CNT_MASK 0x07FF0000
178 #define DESC_RD_CNT_SHIFT 0
179 #define DESC_RD_CNT_MASK 0x000007FF
180
181 /*
182 * PHY registers.
183 */
184 #define L1_CSMB_CTRL 0x15D0
185 #define PHY_CDTS_STAT_OK 0x0000
186 #define PHY_CDTS_STAT_SHORT 0x0100
187 #define PHY_CDTS_STAT_OPEN 0x0200
188 #define PHY_CDTS_STAT_INVAL 0x0300
189 #define PHY_CDTS_STAT_MASK 0x0300
190
191 /*
192 * DMA CFG registers (L1 specific)
193 */
194 #define DMA_CFG_RD_ENB 0x00000400
195 #define DMA_CFG_WR_ENB 0x00000800
196 #define DMA_CFG_RD_BURST_MASK 0x07
197 #define DMA_CFG_RD_BURST_SHIFT 4
198 #define DMA_CFG_WR_BURST_MASK 0x07
199 #define DMA_CFG_WR_BURST_SHIFT 7
200
201 #define RXQ_CFG_ENB 0x80000000
202
203 #define L1_RD_LEN_MASK 0x0000FFFF
204 #define L1_RD_LEN_SHIFT 0
205
206 #define L1_SRAM_RD_ADDR 0x1500
207 #define L1_SRAM_RD_LEN 0x1504
208 #define L1_SRAM_RRD_ADDR 0x1508
209 #define L1_SRAM_RRD_LEN 0x150C
210 #define L1_SRAM_TPD_ADDR 0x1510
211 #define L1_SRAM_TPD_LEN 0x1514
212 #define L1_SRAM_TRD_ADDR 0x1518
213 #define L1_SRAM_TRD_LEN 0x151C
214 #define L1_SRAM_RX_FIFO_ADDR 0x1520
215 #define L1_SRAM_RX_FIFO_LEN 0x1524
216 #define L1_SRAM_TX_FIFO_ADDR 0x1528
217 #define L1_SRAM_TX_FIFO_LEN 0x152C
218
219 #define RXQ_CFG_RD_BURST_MASK 0x000000FF
220 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00
221 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000
222 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
223 #define RXQ_CFG_ENB 0x80000000
224 #define RXQ_CFG_RD_BURST_SHIFT 0
225 #define RXQ_CFG_RD_BURST_DEFAULT 8
226 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8
227 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8
228 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16
229 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1
230
231 #define TXQ_CFG_ENB 0x00000020
232 #define TXQ_CFG_ENHANCED_MODE 0x00000040
233 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
234 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
235 #define TXQ_CFG_TPD_BURST_SHIFT 0
236 #define TXQ_CFG_TPD_BURST_DEFAULT 4
237 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8
238 #define TXQ_CFG_TPD_FETCH_DEFAULT 16
239 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
240 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
241
242 #define L1_TX_JUMBO_TPD_TH_IPG 0x1584
243 #define TX_JUMBO_TPD_TH_MASK 0x000007FF
244 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000
245 #define TX_JUMBO_TPD_TH_SHIFT 0
246 #define TX_JUMBO_TPD_IPG_SHIFT 16
247 #define TX_JUMBO_TPD_IPG_DEFAULT 1
248
249 /* CMB DMA Write Threshold Register */
250 #define L1_CMB_WR_THRESH 0x15D4
251 #define CMB_WR_THRESH_RRD_MASK 0x000007FF
252 #define CMB_WR_THRESH_TPD_MASK 0x07FF0000
253 #define CMB_WR_THRESH_RRD_SHIFT 0
254 #define CMB_WR_THRESH_RRD_DEFAULT 4
255 #define CMB_WR_THRESH_TPD_SHIFT 16
256 #define CMB_WR_THRESH_TPD_DEFAULT 4
257
258 /* SMB auto DMA timer register */
259 #define L1_SMB_TIMER 0x15E4
260
261 #define L1_CSMB_CTRL 0x15D0
262 #define CSMB_CTRL_CMB_KICK 0x00000001
263 #define CSMB_CTRL_SMB_KICK 0x00000002
264 #define CSMB_CTRL_CMB_ENB 0x00000004
265 #define CSMB_CTRL_SMB_ENB 0x00000008
266
267 #define INTR_TX_FIFO_UNDERRUN 0x00000040
268 #define INTR_RX_FIFO_OFLOW 0x00000008
269 #define INTR_TX_DMA 0x00040000
270 #define INTR_RX_DMA 0x00080000
271 #define INTR_CMB_RX 0x00100000
272 #define INTR_CMB_TX 0x00200000
273 #define INTR_MAC_RX 0x00400000
274 #define INTR_MAC_TX 0x00800000
275 #define INTR_UNDERRUN 0x01000000
276 #define INTR_FRAME_ERROR 0x02000000
277 #define INTR_FRAME_OK 0x04000000
278 #define INTR_CSUM_ERROR 0x08000000
279 #define INTR_PHY_LINK_DOWN 0x10000000
280 #define INTR_DIS_SMB 0x20000000
281 #define INTR_DIS_DMA 0x40000000
282 #define INTR_DIS_INT 0x80000000
283
284 #define L1_INTRS \
285 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
286 INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN)
287
288 #define L1_RXQ_RRD_PAUSE_THRESH 0x15AC
289 #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF
290 #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000
291 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0
292 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16
293
294 /* RX/TX count-down timer to trigger CMB-write. */
295 #define L1_CMB_WR_TIMER 0x15D8
296 #define CMB_WR_TIMER_RX_MASK 0x0000FFFF
297 #define CMB_WR_TIMER_TX_MASK 0xFFFF0000
298 #define CMB_WR_TIMER_RX_SHIFT 0
299 #define CMB_WR_TIMER_TX_SHIFT 16
300
301 /*
302 * Useful macros.
|
164 #define RRD_PROD_SHIFT 0
165
166 /*
167 * All descriptors and CMB/SMB share the same high address.
168 */
169 #define L1_DESC_ADDR_HI 0x1540
170 #define L1_DESC_RD_ADDR_LO 0x1544
171 #define L1_DESC_RRD_ADDR_LO 0x1548
172 #define L1_DESC_TPD_ADDR_LO 0x154C
173 #define L1_DESC_CMB_ADDR_LO 0x1550
174 #define L1_DESC_SMB_ADDR_LO 0x1554
175 #define L1_DESC_RRD_RD_CNT 0x1558
176 #define DESC_RRD_CNT_SHIFT 16
177 #define DESC_RRD_CNT_MASK 0x07FF0000
178 #define DESC_RD_CNT_SHIFT 0
179 #define DESC_RD_CNT_MASK 0x000007FF
180
181 /*
182 * PHY registers.
183 */
184 #define PHY_CDTS_STAT_OK 0x0000
185 #define PHY_CDTS_STAT_SHORT 0x0100
186 #define PHY_CDTS_STAT_OPEN 0x0200
187 #define PHY_CDTS_STAT_INVAL 0x0300
188 #define PHY_CDTS_STAT_MASK 0x0300
189
190 /*
191 * DMA CFG registers (L1 specific)
192 */
193 #define DMA_CFG_RD_ENB 0x00000400
194 #define DMA_CFG_WR_ENB 0x00000800
195 #define DMA_CFG_RD_BURST_MASK 0x07
196 #define DMA_CFG_RD_BURST_SHIFT 4
197 #define DMA_CFG_WR_BURST_MASK 0x07
198 #define DMA_CFG_WR_BURST_SHIFT 7
199
200 #define L1_RD_LEN_MASK 0x0000FFFF
201 #define L1_RD_LEN_SHIFT 0
202
203 #define L1_SRAM_RD_ADDR 0x1500
204 #define L1_SRAM_RD_LEN 0x1504
205 #define L1_SRAM_RRD_ADDR 0x1508
206 #define L1_SRAM_RRD_LEN 0x150C
207 #define L1_SRAM_TPD_ADDR 0x1510
208 #define L1_SRAM_TPD_LEN 0x1514
209 #define L1_SRAM_TRD_ADDR 0x1518
210 #define L1_SRAM_TRD_LEN 0x151C
211 #define L1_SRAM_RX_FIFO_ADDR 0x1520
212 #define L1_SRAM_RX_FIFO_LEN 0x1524
213 #define L1_SRAM_TX_FIFO_ADDR 0x1528
214 #define L1_SRAM_TX_FIFO_LEN 0x152C
215
216 #define RXQ_CFG_RD_BURST_MASK 0x000000FF
217 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00
218 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000
219 #define RXQ_CFG_RD_BURST_SHIFT 0
220 #define RXQ_CFG_RD_BURST_DEFAULT 8
221 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8
222 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8
223 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16
224 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1
225
226 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
227 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8
228 #define TXQ_CFG_TPD_FETCH_DEFAULT 16
229
230 #define L1_TX_JUMBO_TPD_TH_IPG 0x1584
231 #define TX_JUMBO_TPD_TH_MASK 0x000007FF
232 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000
233 #define TX_JUMBO_TPD_TH_SHIFT 0
234 #define TX_JUMBO_TPD_IPG_SHIFT 16
235 #define TX_JUMBO_TPD_IPG_DEFAULT 1
236
237 /* CMB DMA Write Threshold Register */
238 #define L1_CMB_WR_THRESH 0x15D4
239 #define CMB_WR_THRESH_RRD_MASK 0x000007FF
240 #define CMB_WR_THRESH_TPD_MASK 0x07FF0000
241 #define CMB_WR_THRESH_RRD_SHIFT 0
242 #define CMB_WR_THRESH_RRD_DEFAULT 4
243 #define CMB_WR_THRESH_TPD_SHIFT 16
244 #define CMB_WR_THRESH_TPD_DEFAULT 4
245
246 /* SMB auto DMA timer register */
247 #define L1_SMB_TIMER 0x15E4
248
249 #define L1_CSMB_CTRL 0x15D0
250 #define CSMB_CTRL_CMB_KICK 0x00000001
251 #define CSMB_CTRL_SMB_KICK 0x00000002
252 #define CSMB_CTRL_CMB_ENB 0x00000004
253 #define CSMB_CTRL_SMB_ENB 0x00000008
254
255 #define INTR_RX_DMA 0x00080000
256 #define INTR_CMB_RX 0x00100000
257 #define INTR_CMB_TX 0x00200000
258 #define INTR_DIS_SMB 0x20000000
259
260 #define L1_INTRS \
261 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
262 INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN)
263
264 #define L1_RXQ_RRD_PAUSE_THRESH 0x15AC
265 #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF
266 #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000
267 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0
268 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16
269
270 /* RX/TX count-down timer to trigger CMB-write. */
271 #define L1_CMB_WR_TIMER 0x15D8
272 #define CMB_WR_TIMER_RX_MASK 0x0000FFFF
273 #define CMB_WR_TIMER_TX_MASK 0xFFFF0000
274 #define CMB_WR_TIMER_RX_SHIFT 0
275 #define CMB_WR_TIMER_TX_SHIFT 16
276
277 /*
278 * Useful macros.
|