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OS-2366 ddi_periodic_add(9F) is entirely rubbish
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--- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
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19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 +/*
30 + * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 + */
29 32
30 33 /*
31 34 * To understand how the pcplusmp module interacts with the interrupt subsystem
32 35 * read the theory statement in uts/i86pc/os/intr.c.
33 36 */
34 37
35 38 /*
36 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
37 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
38 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
39 42 * PSMI 1.5 extensions are supported in Solaris Nevada.
40 43 * PSMI 1.6 extensions are supported in Solaris Nevada.
41 44 * PSMI 1.7 extensions are supported in Solaris Nevada.
42 45 */
43 46 #define PSMI_1_7
44 47
45 48 #include <sys/processor.h>
46 49 #include <sys/time.h>
47 50 #include <sys/psm.h>
48 51 #include <sys/smp_impldefs.h>
49 52 #include <sys/cram.h>
50 53 #include <sys/acpi/acpi.h>
51 54 #include <sys/acpica.h>
52 55 #include <sys/psm_common.h>
53 56 #include <sys/apic.h>
54 57 #include <sys/pit.h>
55 58 #include <sys/ddi.h>
56 59 #include <sys/sunddi.h>
57 60 #include <sys/ddi_impldefs.h>
58 61 #include <sys/pci.h>
59 62 #include <sys/promif.h>
60 63 #include <sys/x86_archext.h>
61 64 #include <sys/cpc_impl.h>
62 65 #include <sys/uadmin.h>
63 66 #include <sys/panic.h>
64 67 #include <sys/debug.h>
65 68 #include <sys/archsystm.h>
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66 69 #include <sys/trap.h>
67 70 #include <sys/machsystm.h>
68 71 #include <sys/sysmacros.h>
69 72 #include <sys/cpuvar.h>
70 73 #include <sys/rm_platter.h>
71 74 #include <sys/privregs.h>
72 75 #include <sys/note.h>
73 76 #include <sys/pci_intr_lib.h>
74 77 #include <sys/spl.h>
75 78 #include <sys/clock.h>
79 +#include <sys/cyclic.h>
76 80 #include <sys/dditypes.h>
77 81 #include <sys/sunddi.h>
78 82 #include <sys/x_call.h>
79 83 #include <sys/reboot.h>
80 84 #include <sys/hpet.h>
81 85 #include <sys/apic_common.h>
82 86 #include <sys/apic_timer.h>
83 87
84 88 /*
85 89 * Local Function Prototypes
86 90 */
87 91 static void apic_init_intr(void);
88 92
89 93 /*
90 94 * standard MP entries
91 95 */
92 96 static int apic_probe(void);
93 97 static int apic_getclkirq(int ipl);
94 98 static void apic_init(void);
95 99 static void apic_picinit(void);
96 100 static int apic_post_cpu_start(void);
97 101 static int apic_intr_enter(int ipl, int *vect);
98 102 static void apic_setspl(int ipl);
99 103 static void x2apic_setspl(int ipl);
100 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
101 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
102 106 static int apic_disable_intr(processorid_t cpun);
103 107 static void apic_enable_intr(processorid_t cpun);
104 108 static int apic_get_ipivect(int ipl, int type);
105 109 static void apic_post_cyclic_setup(void *arg);
106 110
107 111 /*
108 112 * The following vector assignments influence the value of ipltopri and
109 113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
110 114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
111 115 * we care to do so in future. Note some IPLs which are rarely used
112 116 * will share the vector ranges and heavily used IPLs (5 and 6) have
113 117 * a wide range.
114 118 *
115 119 * This array is used to initialize apic_ipls[] (in apic_init()).
116 120 *
117 121 * IPL Vector range. as passed to intr_enter
118 122 * 0 none.
119 123 * 1,2,3 0x20-0x2f 0x0-0xf
120 124 * 4 0x30-0x3f 0x10-0x1f
121 125 * 5 0x40-0x5f 0x20-0x3f
122 126 * 6 0x60-0x7f 0x40-0x5f
123 127 * 7,8,9 0x80-0x8f 0x60-0x6f
124 128 * 10 0x90-0x9f 0x70-0x7f
125 129 * 11 0xa0-0xaf 0x80-0x8f
126 130 * ... ...
127 131 * 15 0xe0-0xef 0xc0-0xcf
128 132 * 15 0xf0-0xff 0xd0-0xdf
129 133 */
130 134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
131 135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
132 136 };
133 137 /*
134 138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
135 139 * NOTE that this is vector as passed into intr_enter which is
136 140 * programmed vector - 0x20 (APIC_BASE_VECT)
137 141 */
138 142
139 143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
140 144 /* The taskpri to be programmed into apic to mask given ipl */
141 145
142 146 #if defined(__amd64)
143 147 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */
144 148 #endif
145 149
146 150 /*
147 151 * Correlation of the hardware vector to the IPL in use, initialized
148 152 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
149 153 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
150 154 * connected to errata-stricken IOAPICs
151 155 */
152 156 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
153 157
154 158 /*
155 159 * Patchable global variables.
156 160 */
157 161 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
158 162 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
159 163
160 164 /*
161 165 * Local static data
162 166 */
163 167 static struct psm_ops apic_ops = {
164 168 apic_probe,
165 169
166 170 apic_init,
167 171 apic_picinit,
168 172 apic_intr_enter,
169 173 apic_intr_exit,
170 174 apic_setspl,
171 175 apic_addspl,
172 176 apic_delspl,
173 177 apic_disable_intr,
174 178 apic_enable_intr,
175 179 (int (*)(int))NULL, /* psm_softlvl_to_irq */
176 180 (void (*)(int))NULL, /* psm_set_softintr */
177 181
178 182 apic_set_idlecpu,
179 183 apic_unset_idlecpu,
180 184
181 185 apic_clkinit,
182 186 apic_getclkirq,
183 187 (void (*)(void))NULL, /* psm_hrtimeinit */
184 188 apic_gethrtime,
185 189
186 190 apic_get_next_processorid,
187 191 apic_cpu_start,
188 192 apic_post_cpu_start,
189 193 apic_shutdown,
190 194 apic_get_ipivect,
191 195 apic_send_ipi,
192 196
193 197 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
194 198 (void (*)(int, char *))NULL, /* psm_notify_error */
195 199 (void (*)(int))NULL, /* psm_notify_func */
196 200 apic_timer_reprogram,
197 201 apic_timer_enable,
198 202 apic_timer_disable,
199 203 apic_post_cyclic_setup,
200 204 apic_preshutdown,
201 205 apic_intr_ops, /* Advanced DDI Interrupt framework */
202 206 apic_state, /* save, restore apic state for S3 */
203 207 apic_cpu_ops, /* CPU control interface. */
204 208 };
205 209
206 210 struct psm_ops *psmops = &apic_ops;
207 211
208 212 static struct psm_info apic_psm_info = {
209 213 PSM_INFO_VER01_7, /* version */
210 214 PSM_OWN_EXCLUSIVE, /* ownership */
211 215 (struct psm_ops *)&apic_ops, /* operation */
212 216 APIC_PCPLUSMP_NAME, /* machine name */
213 217 "pcplusmp v1.4 compatible",
214 218 };
215 219
216 220 static void *apic_hdlp;
217 221
218 222 /*
219 223 * apic_let_idle_redistribute can have the following values:
220 224 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
221 225 * apic_redistribute_lock prevents multiple idle cpus from redistributing
222 226 */
223 227 int apic_num_idle_redistributions = 0;
224 228 static int apic_let_idle_redistribute = 0;
225 229
226 230 /* to gather intr data and redistribute */
227 231 static void apic_redistribute_compute(void);
228 232
229 233 /*
230 234 * This is the loadable module wrapper
231 235 */
232 236
233 237 int
234 238 _init(void)
235 239 {
236 240 if (apic_coarse_hrtime)
237 241 apic_ops.psm_gethrtime = &apic_gettime;
238 242 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
239 243 }
240 244
241 245 int
242 246 _fini(void)
243 247 {
244 248 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
245 249 }
246 250
247 251 int
248 252 _info(struct modinfo *modinfop)
249 253 {
250 254 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
251 255 }
252 256
253 257 static int
254 258 apic_probe(void)
255 259 {
256 260 /* check if apix is initialized */
257 261 if (apix_enable && apix_loaded())
258 262 return (PSM_FAILURE);
259 263 else
260 264 apix_enable = 0; /* continue using pcplusmp PSM */
261 265
262 266 return (apic_probe_common(apic_psm_info.p_mach_idstring));
263 267 }
264 268
265 269 static uchar_t
266 270 apic_xlate_vector_by_irq(uchar_t irq)
267 271 {
268 272 if (apic_irq_table[irq] == NULL)
269 273 return (0);
270 274
271 275 return (apic_irq_table[irq]->airq_vector);
272 276 }
273 277
274 278 void
275 279 apic_init(void)
276 280 {
277 281 int i;
278 282 int j = 1;
279 283
280 284 psm_get_ioapicid = apic_get_ioapicid;
281 285 psm_get_localapicid = apic_get_localapicid;
282 286 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
283 287
284 288 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
285 289 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
286 290 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
287 291 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
288 292 /* get to highest vector at the same ipl */
289 293 continue;
290 294 for (; j <= apic_vectortoipl[i]; j++) {
291 295 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
292 296 APIC_BASE_VECT;
293 297 }
294 298 }
295 299 for (; j < MAXIPL + 1; j++)
296 300 /* fill up any empty ipltopri slots */
297 301 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
298 302 apic_init_common();
299 303 #if defined(__amd64)
300 304 /*
301 305 * Make cpu-specific interrupt info point to cr8pri vector
302 306 */
303 307 for (i = 0; i <= MAXIPL; i++)
304 308 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT;
305 309 CPU->cpu_pri_data = apic_cr8pri;
306 310 #else
307 311 if (cpuid_have_cr8access(CPU))
308 312 apic_have_32bit_cr8 = 1;
309 313 #endif /* __amd64 */
310 314 }
311 315
312 316 static void
313 317 apic_init_intr(void)
314 318 {
315 319 processorid_t cpun = psm_get_cpu_id();
316 320 uint_t nlvt;
317 321 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
318 322
319 323 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
320 324
321 325 if (apic_mode == LOCAL_APIC) {
322 326 /*
323 327 * We are running APIC in MMIO mode.
324 328 */
325 329 if (apic_flat_model) {
326 330 apic_reg_ops->apic_write(APIC_FORMAT_REG,
327 331 APIC_FLAT_MODEL);
328 332 } else {
329 333 apic_reg_ops->apic_write(APIC_FORMAT_REG,
330 334 APIC_CLUSTER_MODEL);
331 335 }
332 336
333 337 apic_reg_ops->apic_write(APIC_DEST_REG,
334 338 AV_HIGH_ORDER >> cpun);
335 339 }
336 340
337 341 if (apic_directed_EOI_supported()) {
338 342 /*
339 343 * Setting the 12th bit in the Spurious Interrupt Vector
340 344 * Register suppresses broadcast EOIs generated by the local
341 345 * APIC. The suppression of broadcast EOIs happens only when
342 346 * interrupts are level-triggered.
343 347 */
344 348 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
345 349 }
346 350
347 351 /* need to enable APIC before unmasking NMI */
348 352 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
349 353
350 354 /*
351 355 * Presence of an invalid vector with delivery mode AV_FIXED can
352 356 * cause an error interrupt, even if the entry is masked...so
353 357 * write a valid vector to LVT entries along with the mask bit
354 358 */
355 359
356 360 /* All APICs have timer and LINT0/1 */
357 361 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
358 362 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
359 363 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
360 364
361 365 /*
362 366 * On integrated APICs, the number of LVT entries is
363 367 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
364 368 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
365 369 */
366 370
367 371 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
368 372 nlvt = 3;
369 373 } else {
370 374 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
371 375 0xFF) + 1;
372 376 }
373 377
374 378 if (nlvt >= 5) {
375 379 /* Enable performance counter overflow interrupt */
376 380
377 381 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
378 382 apic_enable_cpcovf_intr = 0;
379 383 if (apic_enable_cpcovf_intr) {
380 384 if (apic_cpcovf_vect == 0) {
381 385 int ipl = APIC_PCINT_IPL;
382 386 int irq = apic_get_ipivect(ipl, -1);
383 387
384 388 ASSERT(irq != -1);
385 389 apic_cpcovf_vect =
386 390 apic_irq_table[irq]->airq_vector;
387 391 ASSERT(apic_cpcovf_vect);
388 392 (void) add_avintr(NULL, ipl,
389 393 (avfunc)kcpc_hw_overflow_intr,
390 394 "apic pcint", irq, NULL, NULL, NULL, NULL);
391 395 kcpc_hw_overflow_intr_installed = 1;
392 396 kcpc_hw_enable_cpc_intr =
393 397 apic_cpcovf_mask_clear;
394 398 }
395 399 apic_reg_ops->apic_write(APIC_PCINT_VECT,
396 400 apic_cpcovf_vect);
397 401 }
398 402 }
399 403
400 404 if (nlvt >= 6) {
401 405 /* Only mask TM intr if the BIOS apparently doesn't use it */
402 406
403 407 uint32_t lvtval;
404 408
405 409 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
406 410 if (((lvtval & AV_MASK) == AV_MASK) ||
407 411 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
408 412 apic_reg_ops->apic_write(APIC_THERM_VECT,
409 413 AV_MASK|APIC_RESV_IRQ);
410 414 }
411 415 }
412 416
413 417 /* Enable error interrupt */
414 418
415 419 if (nlvt >= 4 && apic_enable_error_intr) {
416 420 if (apic_errvect == 0) {
417 421 int ipl = 0xf; /* get highest priority intr */
418 422 int irq = apic_get_ipivect(ipl, -1);
419 423
420 424 ASSERT(irq != -1);
421 425 apic_errvect = apic_irq_table[irq]->airq_vector;
422 426 ASSERT(apic_errvect);
423 427 /*
424 428 * Not PSMI compliant, but we are going to merge
425 429 * with ON anyway
426 430 */
427 431 (void) add_avintr((void *)NULL, ipl,
428 432 (avfunc)apic_error_intr, "apic error intr",
429 433 irq, NULL, NULL, NULL, NULL);
430 434 }
431 435 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
432 436 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
433 437 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
434 438 }
435 439
436 440 /* Enable CMCI interrupt */
437 441 if (cmi_enable_cmci) {
438 442
439 443 mutex_enter(&cmci_cpu_setup_lock);
440 444 if (cmci_cpu_setup_registered == 0) {
441 445 mutex_enter(&cpu_lock);
442 446 register_cpu_setup_func(cmci_cpu_setup, NULL);
443 447 mutex_exit(&cpu_lock);
444 448 cmci_cpu_setup_registered = 1;
445 449 }
446 450 mutex_exit(&cmci_cpu_setup_lock);
447 451
448 452 if (apic_cmci_vect == 0) {
449 453 int ipl = 0x2;
450 454 int irq = apic_get_ipivect(ipl, -1);
451 455
452 456 ASSERT(irq != -1);
453 457 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
454 458 ASSERT(apic_cmci_vect);
455 459
456 460 (void) add_avintr(NULL, ipl,
457 461 (avfunc)cmi_cmci_trap,
458 462 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
459 463 }
460 464 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
461 465 }
462 466 }
463 467
464 468 static void
465 469 apic_picinit(void)
466 470 {
467 471 int i, j;
468 472 uint_t isr;
469 473
470 474 /*
471 475 * Initialize and enable interrupt remapping before apic
472 476 * hardware initialization
473 477 */
474 478 apic_intrmap_init(apic_mode);
475 479
476 480 /*
477 481 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
478 482 * bit on without clearing it with EOI. Since softint
479 483 * uses vector 0x20 to interrupt itself, so softint will
480 484 * not work on this machine. In order to fix this problem
481 485 * a check is made to verify all the isr bits are clear.
482 486 * If not, EOIs are issued to clear the bits.
483 487 */
484 488 for (i = 7; i >= 1; i--) {
485 489 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
486 490 if (isr != 0)
487 491 for (j = 0; ((j < 32) && (isr != 0)); j++)
488 492 if (isr & (1 << j)) {
489 493 apic_reg_ops->apic_write(
490 494 APIC_EOI_REG, 0);
491 495 isr &= ~(1 << j);
492 496 apic_error |= APIC_ERR_BOOT_EOI;
493 497 }
494 498 }
495 499
496 500 /* set a flag so we know we have run apic_picinit() */
497 501 apic_picinit_called = 1;
498 502 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
499 503 LOCK_INIT_CLEAR(&apic_ioapic_lock);
500 504 LOCK_INIT_CLEAR(&apic_error_lock);
501 505 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
502 506
503 507 picsetup(); /* initialise the 8259 */
504 508
505 509 /* add nmi handler - least priority nmi handler */
506 510 LOCK_INIT_CLEAR(&apic_nmi_lock);
507 511
508 512 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
509 513 "pcplusmp NMI handler", (caddr_t)NULL))
510 514 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
511 515
512 516 /*
513 517 * Check for directed-EOI capability in the local APIC.
514 518 */
515 519 if (apic_directed_EOI_supported() == 1) {
516 520 apic_set_directed_EOI_handler();
517 521 }
518 522
519 523 apic_init_intr();
520 524
521 525 /* enable apic mode if imcr present */
522 526 if (apic_imcrp) {
523 527 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
524 528 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
525 529 }
526 530
527 531 ioapic_init_intr(IOAPIC_MASK);
528 532 }
529 533
530 534 #ifdef DEBUG
531 535 void
532 536 apic_break(void)
533 537 {
534 538 }
535 539 #endif /* DEBUG */
536 540
537 541 /*
538 542 * platform_intr_enter
539 543 *
540 544 * Called at the beginning of the interrupt service routine to
541 545 * mask all level equal to and below the interrupt priority
542 546 * of the interrupting vector. An EOI should be given to
543 547 * the interrupt controller to enable other HW interrupts.
544 548 *
545 549 * Return -1 for spurious interrupts
546 550 *
547 551 */
548 552 /*ARGSUSED*/
549 553 static int
550 554 apic_intr_enter(int ipl, int *vectorp)
551 555 {
552 556 uchar_t vector;
553 557 int nipl;
554 558 int irq;
555 559 ulong_t iflag;
556 560 apic_cpus_info_t *cpu_infop;
557 561
558 562 /*
559 563 * The real vector delivered is (*vectorp + 0x20), but our caller
560 564 * subtracts 0x20 from the vector before passing it to us.
561 565 * (That's why APIC_BASE_VECT is 0x20.)
562 566 */
563 567 vector = (uchar_t)*vectorp;
564 568
565 569 /* if interrupted by the clock, increment apic_nsec_since_boot */
566 570 if (vector == apic_clkvect) {
567 571 if (!apic_oneshot) {
568 572 /* NOTE: this is not MT aware */
569 573 apic_hrtime_stamp++;
570 574 apic_nsec_since_boot += apic_nsec_per_intr;
571 575 apic_hrtime_stamp++;
572 576 last_count_read = apic_hertz_count;
573 577 apic_redistribute_compute();
574 578 }
575 579
576 580 /* We will avoid all the book keeping overhead for clock */
577 581 nipl = apic_ipls[vector];
578 582
579 583 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
580 584 if (apic_mode == LOCAL_APIC) {
581 585 #if defined(__amd64)
582 586 setcr8((ulong_t)(apic_ipltopri[nipl] >>
583 587 APIC_IPL_SHIFT));
584 588 #else
585 589 if (apic_have_32bit_cr8)
586 590 setcr8((ulong_t)(apic_ipltopri[nipl] >>
587 591 APIC_IPL_SHIFT));
588 592 else
589 593 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
590 594 (uint32_t)apic_ipltopri[nipl]);
591 595 #endif
592 596 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
593 597 } else {
594 598 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
595 599 X2APIC_WRITE(APIC_EOI_REG, 0);
596 600 }
597 601
598 602 return (nipl);
599 603 }
600 604
601 605 cpu_infop = &apic_cpus[psm_get_cpu_id()];
602 606
603 607 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
604 608 cpu_infop->aci_spur_cnt++;
605 609 return (APIC_INT_SPURIOUS);
606 610 }
607 611
608 612 /* Check if the vector we got is really what we need */
609 613 if (apic_revector_pending) {
610 614 /*
611 615 * Disable interrupts for the duration of
612 616 * the vector translation to prevent a self-race for
613 617 * the apic_revector_lock. This cannot be done
614 618 * in apic_xlate_vector because it is recursive and
615 619 * we want the vector translation to be atomic with
616 620 * respect to other (higher-priority) interrupts.
617 621 */
618 622 iflag = intr_clear();
619 623 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
620 624 APIC_BASE_VECT;
621 625 intr_restore(iflag);
622 626 }
623 627
624 628 nipl = apic_ipls[vector];
625 629 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
626 630
627 631 if (apic_mode == LOCAL_APIC) {
628 632 #if defined(__amd64)
629 633 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT));
630 634 #else
631 635 if (apic_have_32bit_cr8)
632 636 setcr8((ulong_t)(apic_ipltopri[nipl] >>
633 637 APIC_IPL_SHIFT));
634 638 else
635 639 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
636 640 (uint32_t)apic_ipltopri[nipl]);
637 641 #endif
638 642 } else {
639 643 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
640 644 }
641 645
642 646 cpu_infop->aci_current[nipl] = (uchar_t)irq;
643 647 cpu_infop->aci_curipl = (uchar_t)nipl;
644 648 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
645 649
646 650 /*
647 651 * apic_level_intr could have been assimilated into the irq struct.
648 652 * but, having it as a character array is more efficient in terms of
649 653 * cache usage. So, we leave it as is.
650 654 */
651 655 if (!apic_level_intr[irq]) {
652 656 if (apic_mode == LOCAL_APIC) {
653 657 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
654 658 } else {
655 659 X2APIC_WRITE(APIC_EOI_REG, 0);
656 660 }
657 661 }
658 662
659 663 #ifdef DEBUG
660 664 APIC_DEBUG_BUF_PUT(vector);
661 665 APIC_DEBUG_BUF_PUT(irq);
662 666 APIC_DEBUG_BUF_PUT(nipl);
663 667 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
664 668 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
665 669 drv_usecwait(apic_stretch_interrupts);
666 670
667 671 if (apic_break_on_cpu == psm_get_cpu_id())
668 672 apic_break();
669 673 #endif /* DEBUG */
670 674 return (nipl);
671 675 }
672 676
673 677 /*
674 678 * This macro is a common code used by MMIO local apic and X2APIC
675 679 * local apic.
676 680 */
677 681 #define APIC_INTR_EXIT() \
678 682 { \
679 683 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
680 684 if (apic_level_intr[irq]) \
681 685 apic_reg_ops->apic_send_eoi(irq); \
682 686 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
683 687 /* ISR above current pri could not be in progress */ \
684 688 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
685 689 }
686 690
687 691 /*
688 692 * Any changes made to this function must also change X2APIC
689 693 * version of intr_exit.
690 694 */
691 695 void
692 696 apic_intr_exit(int prev_ipl, int irq)
693 697 {
694 698 apic_cpus_info_t *cpu_infop;
695 699
696 700 #if defined(__amd64)
697 701 setcr8((ulong_t)apic_cr8pri[prev_ipl]);
698 702 #else
699 703 if (apic_have_32bit_cr8)
700 704 setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
701 705 else
702 706 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl];
703 707 #endif
704 708
705 709 APIC_INTR_EXIT();
706 710 }
707 711
708 712 /*
709 713 * Same as apic_intr_exit() except it uses MSR rather than MMIO
710 714 * to access local apic registers.
711 715 */
712 716 void
713 717 x2apic_intr_exit(int prev_ipl, int irq)
714 718 {
715 719 apic_cpus_info_t *cpu_infop;
716 720
717 721 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
718 722 APIC_INTR_EXIT();
719 723 }
720 724
721 725 intr_exit_fn_t
722 726 psm_intr_exit_fn(void)
723 727 {
724 728 if (apic_mode == LOCAL_X2APIC)
725 729 return (x2apic_intr_exit);
726 730
727 731 return (apic_intr_exit);
728 732 }
729 733
730 734 /*
731 735 * Mask all interrupts below or equal to the given IPL.
732 736 * Any changes made to this function must also change X2APIC
733 737 * version of setspl.
734 738 */
735 739 static void
736 740 apic_setspl(int ipl)
737 741 {
738 742 #if defined(__amd64)
739 743 setcr8((ulong_t)apic_cr8pri[ipl]);
740 744 #else
741 745 if (apic_have_32bit_cr8)
742 746 setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
743 747 else
744 748 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl];
745 749 #endif
746 750
747 751 /* interrupts at ipl above this cannot be in progress */
748 752 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
749 753 /*
750 754 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
751 755 * have enough time to come in before the priority is raised again
752 756 * during the idle() loop.
753 757 */
754 758 if (apic_setspl_delay)
755 759 (void) apic_reg_ops->apic_get_pri();
756 760 }
757 761
758 762 /*
759 763 * X2APIC version of setspl.
760 764 * Mask all interrupts below or equal to the given IPL
761 765 */
762 766 static void
763 767 x2apic_setspl(int ipl)
764 768 {
765 769 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
766 770
767 771 /* interrupts at ipl above this cannot be in progress */
768 772 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
769 773 }
770 774
771 775 /*ARGSUSED*/
772 776 static int
773 777 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
774 778 {
775 779 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
776 780 }
777 781
778 782 static int
779 783 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
780 784 {
781 785 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
782 786 }
783 787
784 788 static int
785 789 apic_post_cpu_start(void)
786 790 {
787 791 int cpun;
788 792 static int cpus_started = 1;
789 793
790 794 /* We know this CPU + BSP started successfully. */
791 795 cpus_started++;
792 796
793 797 /*
794 798 * On BSP we would have enabled X2APIC, if supported by processor,
795 799 * in acpi_probe(), but on AP we do it here.
796 800 *
797 801 * We enable X2APIC mode only if BSP is running in X2APIC & the
798 802 * local APIC mode of the current CPU is MMIO (xAPIC).
799 803 */
800 804 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
801 805 apic_local_mode() == LOCAL_APIC) {
802 806 apic_enable_x2apic();
803 807 }
804 808
805 809 /*
806 810 * Switch back to x2apic IPI sending method for performance when target
807 811 * CPU has entered x2apic mode.
808 812 */
809 813 if (apic_mode == LOCAL_X2APIC) {
810 814 apic_switch_ipi_callback(B_FALSE);
811 815 }
812 816
813 817 splx(ipltospl(LOCK_LEVEL));
814 818 apic_init_intr();
815 819
816 820 /*
817 821 * since some systems don't enable the internal cache on the non-boot
818 822 * cpus, so we have to enable them here
819 823 */
820 824 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
821 825
822 826 #ifdef DEBUG
823 827 APIC_AV_PENDING_SET();
824 828 #else
825 829 if (apic_mode == LOCAL_APIC)
826 830 APIC_AV_PENDING_SET();
827 831 #endif /* DEBUG */
828 832
829 833 /*
830 834 * We may be booting, or resuming from suspend; aci_status will
831 835 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
832 836 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
833 837 */
834 838 cpun = psm_get_cpu_id();
835 839 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
836 840
837 841 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
838 842 return (PSM_SUCCESS);
839 843 }
840 844
841 845 /*
842 846 * type == -1 indicates it is an internal request. Do not change
843 847 * resv_vector for these requests
844 848 */
845 849 static int
846 850 apic_get_ipivect(int ipl, int type)
847 851 {
848 852 uchar_t vector;
849 853 int irq;
850 854
851 855 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
852 856 if (vector = apic_allocate_vector(ipl, irq, 1)) {
853 857 apic_irq_table[irq]->airq_mps_intr_index =
854 858 RESERVE_INDEX;
855 859 apic_irq_table[irq]->airq_vector = vector;
856 860 if (type != -1) {
857 861 apic_resv_vector[ipl] = vector;
858 862 }
859 863 return (irq);
860 864 }
861 865 }
862 866 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
863 867 return (-1); /* shouldn't happen */
864 868 }
865 869
866 870 static int
867 871 apic_getclkirq(int ipl)
868 872 {
869 873 int irq;
870 874
871 875 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
872 876 return (-1);
873 877 /*
874 878 * Note the vector in apic_clkvect for per clock handling.
875 879 */
876 880 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
877 881 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
878 882 apic_clkvect));
879 883 return (irq);
880 884 }
881 885
882 886 /*
883 887 * Try and disable all interrupts. We just assign interrupts to other
884 888 * processors based on policy. If any were bound by user request, we
885 889 * let them continue and return failure. We do not bother to check
886 890 * for cache affinity while rebinding.
887 891 */
888 892
889 893 static int
890 894 apic_disable_intr(processorid_t cpun)
891 895 {
892 896 int bind_cpu = 0, i, hardbound = 0;
893 897 apic_irq_t *irq_ptr;
894 898 ulong_t iflag;
895 899
896 900 iflag = intr_clear();
897 901 lock_set(&apic_ioapic_lock);
898 902
899 903 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
900 904 if (apic_reprogram_info[i].done == B_FALSE) {
901 905 if (apic_reprogram_info[i].bindcpu == cpun) {
902 906 /*
903 907 * CPU is busy -- it's the target of
904 908 * a pending reprogramming attempt
905 909 */
906 910 lock_clear(&apic_ioapic_lock);
907 911 intr_restore(iflag);
908 912 return (PSM_FAILURE);
909 913 }
910 914 }
911 915 }
912 916
913 917 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
914 918
915 919 apic_cpus[cpun].aci_curipl = 0;
916 920
917 921 i = apic_min_device_irq;
918 922 for (; i <= apic_max_device_irq; i++) {
919 923 /*
920 924 * If there are bound interrupts on this cpu, then
921 925 * rebind them to other processors.
922 926 */
923 927 if ((irq_ptr = apic_irq_table[i]) != NULL) {
924 928 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
925 929 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
926 930 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
927 931
928 932 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
929 933 hardbound = 1;
930 934 continue;
931 935 }
932 936
933 937 if (irq_ptr->airq_temp_cpu == cpun) {
934 938 do {
935 939 bind_cpu =
936 940 apic_find_cpu(APIC_CPU_INTR_ENABLE);
937 941 } while (apic_rebind_all(irq_ptr, bind_cpu));
938 942 }
939 943 }
940 944 }
941 945
942 946 lock_clear(&apic_ioapic_lock);
943 947 intr_restore(iflag);
944 948
945 949 if (hardbound) {
946 950 cmn_err(CE_WARN, "Could not disable interrupts on %d"
947 951 "due to user bound interrupts", cpun);
948 952 return (PSM_FAILURE);
949 953 }
950 954 else
951 955 return (PSM_SUCCESS);
952 956 }
953 957
954 958 /*
955 959 * Bind interrupts to the CPU's local APIC.
956 960 * Interrupts should not be bound to a CPU's local APIC until the CPU
957 961 * is ready to receive interrupts.
958 962 */
959 963 static void
960 964 apic_enable_intr(processorid_t cpun)
961 965 {
962 966 int i;
963 967 apic_irq_t *irq_ptr;
964 968 ulong_t iflag;
965 969
966 970 iflag = intr_clear();
967 971 lock_set(&apic_ioapic_lock);
968 972
969 973 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
970 974
971 975 i = apic_min_device_irq;
972 976 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
973 977 if ((irq_ptr = apic_irq_table[i]) != NULL) {
974 978 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
975 979 (void) apic_rebind_all(irq_ptr,
976 980 irq_ptr->airq_cpu);
977 981 }
978 982 }
979 983 }
980 984
981 985 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
982 986 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
983 987
984 988 lock_clear(&apic_ioapic_lock);
985 989 intr_restore(iflag);
986 990 }
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987 991
988 992 /*
989 993 * If this module needs a periodic handler for the interrupt distribution, it
990 994 * can be added here. The argument to the periodic handler is not currently
991 995 * used, but is reserved for future.
992 996 */
993 997 static void
994 998 apic_post_cyclic_setup(void *arg)
995 999 {
996 1000 _NOTE(ARGUNUSED(arg))
1001 +
1002 + cyc_handler_t cyh;
1003 + cyc_time_t cyt;
1004 +
997 1005 /* cpu_lock is held */
998 1006 /* set up a periodic handler for intr redistribution */
999 1007
1000 1008 /*
1001 1009 * In peridoc mode intr redistribution processing is done in
1002 1010 * apic_intr_enter during clk intr processing
1003 1011 */
1004 1012 if (!apic_oneshot)
1005 1013 return;
1014 +
1006 1015 /*
1007 1016 * Register a periodical handler for the redistribution processing.
1008 - * On X86, CY_LOW_LEVEL is mapped to the level 2 interrupt, so
1009 - * DDI_IPL_2 should be passed to ddi_periodic_add() here.
1017 + * Though we would generally prefer to use the DDI interface for
1018 + * periodic handler invocation, ddi_periodic_add(9F), we are
1019 + * unfortunately already holding cpu_lock, which ddi_periodic_add will
1020 + * attempt to take for us. Thus, we add our own cyclic directly:
1010 1021 */
1011 - apic_periodic_id = ddi_periodic_add(
1012 - (void (*)(void *))apic_redistribute_compute, NULL,
1013 - apic_redistribute_sample_interval, DDI_IPL_2);
1022 + cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
1023 + cyh.cyh_arg = NULL;
1024 + cyh.cyh_level = CY_LOW_LEVEL;
1025 +
1026 + cyt.cyt_when = 0;
1027 + cyt.cyt_interval = apic_redistribute_sample_interval;
1028 +
1029 + apic_cyclic_id = cyclic_add(&cyh, &cyt);
1014 1030 }
1015 1031
1016 1032 static void
1017 1033 apic_redistribute_compute(void)
1018 1034 {
1019 1035 int i, j, max_busy;
1020 1036
1021 1037 if (apic_enable_dynamic_migration) {
1022 1038 if (++apic_nticks == apic_sample_factor_redistribution) {
1023 1039 /*
1024 1040 * Time to call apic_intr_redistribute().
1025 1041 * reset apic_nticks. This will cause max_busy
1026 1042 * to be calculated below and if it is more than
1027 1043 * apic_int_busy, we will do the whole thing
1028 1044 */
1029 1045 apic_nticks = 0;
1030 1046 }
1031 1047 max_busy = 0;
1032 1048 for (i = 0; i < apic_nproc; i++) {
1033 1049 if (!apic_cpu_in_range(i))
1034 1050 continue;
1035 1051
1036 1052 /*
1037 1053 * Check if curipl is non zero & if ISR is in
1038 1054 * progress
1039 1055 */
1040 1056 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1041 1057 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1042 1058
1043 1059 int irq;
1044 1060 apic_cpus[i].aci_busy++;
1045 1061 irq = apic_cpus[i].aci_current[j];
1046 1062 apic_irq_table[irq]->airq_busy++;
1047 1063 }
1048 1064
1049 1065 if (!apic_nticks &&
1050 1066 (apic_cpus[i].aci_busy > max_busy))
1051 1067 max_busy = apic_cpus[i].aci_busy;
1052 1068 }
1053 1069 if (!apic_nticks) {
1054 1070 if (max_busy > apic_int_busy_mark) {
1055 1071 /*
1056 1072 * We could make the following check be
1057 1073 * skipped > 1 in which case, we get a
1058 1074 * redistribution at half the busy mark (due to
1059 1075 * double interval). Need to be able to collect
1060 1076 * more empirical data to decide if that is a
1061 1077 * good strategy. Punt for now.
1062 1078 */
1063 1079 if (apic_skipped_redistribute) {
1064 1080 apic_cleanup_busy();
1065 1081 apic_skipped_redistribute = 0;
1066 1082 } else {
1067 1083 apic_intr_redistribute();
1068 1084 }
1069 1085 } else
1070 1086 apic_skipped_redistribute++;
1071 1087 }
1072 1088 }
1073 1089 }
1074 1090
1075 1091
1076 1092 /*
1077 1093 * The following functions are in the platform specific file so that they
1078 1094 * can be different functions depending on whether we are running on
1079 1095 * bare metal or a hypervisor.
1080 1096 */
1081 1097
1082 1098 /*
1083 1099 * Check to make sure there are enough irq slots
1084 1100 */
1085 1101 int
1086 1102 apic_check_free_irqs(int count)
1087 1103 {
1088 1104 int i, avail;
1089 1105
1090 1106 avail = 0;
1091 1107 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1092 1108 if ((apic_irq_table[i] == NULL) ||
1093 1109 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1094 1110 if (++avail >= count)
1095 1111 return (PSM_SUCCESS);
1096 1112 }
1097 1113 }
1098 1114 return (PSM_FAILURE);
1099 1115 }
1100 1116
1101 1117 /*
1102 1118 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1103 1119 */
1104 1120 int
1105 1121 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1106 1122 int behavior)
1107 1123 {
1108 1124 int rcount, i;
1109 1125 uchar_t start, irqno;
1110 1126 uint32_t cpu;
1111 1127 major_t major;
1112 1128 apic_irq_t *irqptr;
1113 1129
1114 1130 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1115 1131 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1116 1132 (void *)dip, inum, pri, count, behavior));
1117 1133
1118 1134 if (count > 1) {
1119 1135 if (behavior == DDI_INTR_ALLOC_STRICT &&
1120 1136 apic_multi_msi_enable == 0)
1121 1137 return (0);
1122 1138 if (apic_multi_msi_enable == 0)
1123 1139 count = 1;
1124 1140 }
1125 1141
1126 1142 if ((rcount = apic_navail_vector(dip, pri)) > count)
1127 1143 rcount = count;
1128 1144 else if (rcount == 0 || (rcount < count &&
1129 1145 behavior == DDI_INTR_ALLOC_STRICT))
1130 1146 return (0);
1131 1147
1132 1148 /* if not ISP2, then round it down */
1133 1149 if (!ISP2(rcount))
1134 1150 rcount = 1 << (highbit(rcount) - 1);
1135 1151
1136 1152 mutex_enter(&airq_mutex);
1137 1153
1138 1154 for (start = 0; rcount > 0; rcount >>= 1) {
1139 1155 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1140 1156 behavior == DDI_INTR_ALLOC_STRICT)
1141 1157 break;
1142 1158 }
1143 1159
1144 1160 if (start == 0) {
1145 1161 /* no vector available */
1146 1162 mutex_exit(&airq_mutex);
1147 1163 return (0);
1148 1164 }
1149 1165
1150 1166 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1151 1167 /* not enough free irq slots available */
1152 1168 mutex_exit(&airq_mutex);
1153 1169 return (0);
1154 1170 }
1155 1171
1156 1172 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1157 1173 for (i = 0; i < rcount; i++) {
1158 1174 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1159 1175 (uchar_t)-1) {
1160 1176 /*
1161 1177 * shouldn't happen because of the
1162 1178 * apic_check_free_irqs() check earlier
1163 1179 */
1164 1180 mutex_exit(&airq_mutex);
1165 1181 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1166 1182 "apic_allocate_irq failed\n"));
1167 1183 return (i);
1168 1184 }
1169 1185 apic_max_device_irq = max(irqno, apic_max_device_irq);
1170 1186 apic_min_device_irq = min(irqno, apic_min_device_irq);
1171 1187 irqptr = apic_irq_table[irqno];
1172 1188 #ifdef DEBUG
1173 1189 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1174 1190 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1175 1191 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1176 1192 #endif
1177 1193 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1178 1194
1179 1195 irqptr->airq_vector = (uchar_t)(start + i);
1180 1196 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1181 1197 irqptr->airq_intin_no = (uchar_t)rcount;
1182 1198 irqptr->airq_ipl = pri;
1183 1199 irqptr->airq_vector = start + i;
1184 1200 irqptr->airq_origirq = (uchar_t)(inum + i);
1185 1201 irqptr->airq_share_id = 0;
1186 1202 irqptr->airq_mps_intr_index = MSI_INDEX;
1187 1203 irqptr->airq_dip = dip;
1188 1204 irqptr->airq_major = major;
1189 1205 if (i == 0) /* they all bound to the same cpu */
1190 1206 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1191 1207 0xff, 0xff);
1192 1208 else
1193 1209 irqptr->airq_cpu = cpu;
1194 1210 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1195 1211 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1196 1212 (void *)irqptr->airq_dip, irqptr->airq_vector,
1197 1213 irqptr->airq_origirq, pri));
1198 1214 }
1199 1215 mutex_exit(&airq_mutex);
1200 1216 return (rcount);
1201 1217 }
1202 1218
1203 1219 /*
1204 1220 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1205 1221 */
1206 1222 int
1207 1223 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1208 1224 int behavior)
1209 1225 {
1210 1226 int rcount, i;
1211 1227 major_t major;
1212 1228
1213 1229 mutex_enter(&airq_mutex);
1214 1230
1215 1231 if ((rcount = apic_navail_vector(dip, pri)) > count)
1216 1232 rcount = count;
1217 1233 else if (rcount == 0 || (rcount < count &&
1218 1234 behavior == DDI_INTR_ALLOC_STRICT)) {
1219 1235 rcount = 0;
1220 1236 goto out;
1221 1237 }
1222 1238
1223 1239 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1224 1240 /* not enough free irq slots available */
1225 1241 rcount = 0;
1226 1242 goto out;
1227 1243 }
1228 1244
1229 1245 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1230 1246 for (i = 0; i < rcount; i++) {
1231 1247 uchar_t vector, irqno;
1232 1248 apic_irq_t *irqptr;
1233 1249
1234 1250 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1235 1251 (uchar_t)-1) {
1236 1252 /*
1237 1253 * shouldn't happen because of the
1238 1254 * apic_check_free_irqs() check earlier
1239 1255 */
1240 1256 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1241 1257 "apic_allocate_irq failed\n"));
1242 1258 rcount = i;
1243 1259 goto out;
1244 1260 }
1245 1261 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1246 1262 /*
1247 1263 * shouldn't happen because of the
1248 1264 * apic_navail_vector() call earlier
1249 1265 */
1250 1266 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1251 1267 "apic_allocate_vector failed\n"));
1252 1268 rcount = i;
1253 1269 goto out;
1254 1270 }
1255 1271 apic_max_device_irq = max(irqno, apic_max_device_irq);
1256 1272 apic_min_device_irq = min(irqno, apic_min_device_irq);
1257 1273 irqptr = apic_irq_table[irqno];
1258 1274 irqptr->airq_vector = (uchar_t)vector;
1259 1275 irqptr->airq_ipl = pri;
1260 1276 irqptr->airq_origirq = (uchar_t)(inum + i);
1261 1277 irqptr->airq_share_id = 0;
1262 1278 irqptr->airq_mps_intr_index = MSIX_INDEX;
1263 1279 irqptr->airq_dip = dip;
1264 1280 irqptr->airq_major = major;
1265 1281 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1266 1282 }
1267 1283 out:
1268 1284 mutex_exit(&airq_mutex);
1269 1285 return (rcount);
1270 1286 }
1271 1287
1272 1288 /*
1273 1289 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1274 1290 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1275 1291 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1276 1292 * requests and allocated only when pri is set.
1277 1293 */
1278 1294 uchar_t
1279 1295 apic_allocate_vector(int ipl, int irq, int pri)
1280 1296 {
1281 1297 int lowest, highest, i;
1282 1298
1283 1299 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1284 1300 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1285 1301
1286 1302 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1287 1303 lowest -= APIC_VECTOR_PER_IPL;
1288 1304
1289 1305 #ifdef DEBUG
1290 1306 if (apic_restrict_vector) /* for testing shared interrupt logic */
1291 1307 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1292 1308 #endif /* DEBUG */
1293 1309 if (pri == 0)
1294 1310 highest -= APIC_HI_PRI_VECTS;
1295 1311
1296 1312 for (i = lowest; i <= highest; i++) {
1297 1313 if (APIC_CHECK_RESERVE_VECTORS(i))
1298 1314 continue;
1299 1315 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1300 1316 apic_vector_to_irq[i] = (uchar_t)irq;
1301 1317 return (i);
1302 1318 }
1303 1319 }
1304 1320
1305 1321 return (0);
1306 1322 }
1307 1323
1308 1324 /* Mark vector as not being used by any irq */
1309 1325 void
1310 1326 apic_free_vector(uchar_t vector)
1311 1327 {
1312 1328 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1313 1329 }
1314 1330
1315 1331 /*
1316 1332 * Call rebind to do the actual programming.
1317 1333 * Must be called with interrupts disabled and apic_ioapic_lock held
1318 1334 * 'p' is polymorphic -- if this function is called to process a deferred
1319 1335 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1320 1336 * the irq pointer is retrieved. If not doing deferred reprogramming,
1321 1337 * p is of the type 'apic_irq_t *'.
1322 1338 *
1323 1339 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1324 1340 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1325 1341 * taken offline after a cpu is selected, but before apic_rebind is called to
1326 1342 * bind interrupts to it.
1327 1343 */
1328 1344 int
1329 1345 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1330 1346 {
1331 1347 apic_irq_t *irqptr;
1332 1348 struct ioapic_reprogram_data *drep = NULL;
1333 1349 int rv;
1334 1350
1335 1351 if (deferred) {
1336 1352 drep = (struct ioapic_reprogram_data *)p;
1337 1353 ASSERT(drep != NULL);
1338 1354 irqptr = drep->irqp;
1339 1355 } else
1340 1356 irqptr = (apic_irq_t *)p;
1341 1357
1342 1358 ASSERT(irqptr != NULL);
1343 1359
1344 1360 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1345 1361 if (rv) {
1346 1362 /*
1347 1363 * CPU is not up or interrupts are disabled. Fall back to
1348 1364 * the first available CPU
1349 1365 */
1350 1366 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1351 1367 drep);
1352 1368 }
1353 1369
1354 1370 return (rv);
1355 1371 }
1356 1372
1357 1373
1358 1374 uchar_t
1359 1375 apic_modify_vector(uchar_t vector, int irq)
1360 1376 {
1361 1377 apic_vector_to_irq[vector] = (uchar_t)irq;
1362 1378 return (vector);
1363 1379 }
1364 1380
1365 1381 char *
1366 1382 apic_get_apic_type(void)
1367 1383 {
1368 1384 return (apic_psm_info.p_mach_idstring);
1369 1385 }
1370 1386
1371 1387 void
1372 1388 x2apic_update_psm(void)
1373 1389 {
1374 1390 struct psm_ops *pops = &apic_ops;
1375 1391
1376 1392 ASSERT(pops != NULL);
1377 1393
1378 1394 pops->psm_intr_exit = x2apic_intr_exit;
1379 1395 pops->psm_setspl = x2apic_setspl;
1380 1396
1381 1397 pops->psm_send_ipi = x2apic_send_ipi;
1382 1398 send_dirintf = pops->psm_send_ipi;
1383 1399
1384 1400 apic_mode = LOCAL_X2APIC;
1385 1401 apic_change_ops();
1386 1402 }
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