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  18 .Dd October 29, 2017
  19 .Dt TERMIOX 7I
  20 .Os
  21 .Sh NAME
  22 .Nm termiox
  23 .Nd extended general terminal interface
  24 .Sh DESCRIPTION
  25 The extended general terminal interface supplements the
  26 .Xr termio 7I
  27 general terminal interface by adding support for asynchronous hardware flow
  28 control, isochronous flow control and clock modes, and local implementations of
  29 additional asynchronous features.
  30 Some systems may not support all of these
  31 capabilities because of either hardware or software limitations.
  32 Other systems may not permit certain functions to be disabled.
  33 In these cases the appropriate bits will be ignored.
  34 See
  35 .In sys/termiox.h
  36 for your system to find out which capabilities are supported.
  37 .Ss "Hardware Flow Control Modes"
  38 Hardware flow control supplements the
  39 .Xr termio 7I
  40 .Dv IXON ,
  41 .Dv IXOFF ,
  42 and
  43 .Dv IXANY
  44 character flow control.
  45 Character flow control occurs when one
  46 device controls the data transfer of another device by the insertion of control
  47 characters in the data stream between devices.
  48 Hardware flow control occurs
  49 when one device controls the data transfer of another device using electrical
  50 control signals on wires (circuits) of the asynchronous interface.
  51 Isochronous
  52 hardware flow control occurs when one device controls the data transfer of
  53 another device by asserting or removing the transmit clock signals of that
  54 device.
  55 Character flow control and hardware flow control may be simultaneously
  56 set.
  57 .Pp
  58 In asynchronous, full duplex applications, the use of the Electronic Industries
  59 Association's EIA-232-D Request To Send (RTS) and Clear To Send (CTS) circuits
  60 is the preferred method of hardware flow control.
  61 An interface to other
  62 hardware flow control methods is included to provide a standard interface to
  63 these existing methods.
  64 .Pp
  65 The EIA-232-D standard specified only unidirectional hardware flow control \(em
  66 the Data Circuit-terminating Equipment or Data Communications Equipment (DCE)
  67 indicates to the Data Terminal Equipment (DTE) to stop transmitting data.
  68 The
  69 .Nm
  70 interface allows both unidirectional and bidirectional hardware
  71 flow control; when bidirectional flow control is enabled, either the DCE or DTE
  72 can indicate to each other to stop transmitting data across the interface.
  73 Note: It is assumed that the asynchronous port is configured as a DTE.
  74 If the
  75 connected device is also a DTE and not a DCE, then DTE to DTE (for example,
  76 terminal or printer connected to computer) hardware flow control is possible by
  77 using a null modem to interconnect the appropriate data and control circuits.
  78 .Ss "Clock Modes"
  79 Isochronous communication is a variation of asynchronous communication whereby
  80 two communicating devices may provide transmit and/or receive clock signals to
  81 one another.
  82 Incoming clock signals can be taken from the baud rate generator
  83 on the local isochronous port controller, from CCITT V\.24 circuit 114,
  84 Transmitter Signal Element Timing - DCE source (EIA-232-D pin 15), or from
  85 CITT V\.24 circuit 115, Receiver Signal Element Timing - DCE source (EIA-232-D
  86 pin 17).
  87 Outgoing clock signals can be sent on CCITT V\.24 circuit 113,
  88 Transmitter Signal Element Timing - DTE source (EIA-232-D pin 24), on CCITT
  89 V\.24 circuit 128, Receiver Signal Element Timing - DTE source (no EIA-232-D
  90 pin), or not sent at all.
  91 .Pp
  92 In terms of clock modes, traditional asynchronous communication is implemented
  93 simply by using the local baud rate generator as the incoming transmit and
  94 receive clock source and not outputting any clock signals.
  95 .Ss "Terminal Parameters"
  96 The parameters that control the behavior of devices providing the
  97 .Nm
  98 interface are specified by the
  99 .Vt termiox
 100 structure defined in the
 101 .In sys/termiox.h
 102 header.
 103 Several
 104 .Xr ioctl 2
 105 system calls that fetch
 106 or change these parameters use this structure:
 107 .Bd -literal -offset 2n
 108 #define NFF     5
 109 struct termiox  {
 110         unsigned short  x_hflag;       /* hardware flow control modes */
 111         unsigned short  x_cflag;       /* clock modes */
 112         unsigned short  x_rflag[NFF];  /* reserved modes */
 113         unsigned short  x_sflag;       /* spare local modes */
 114 };
 115 .Ed
 116 .Pp
 117 The
 118 .Fa x_hflag
 119 field describes hardware flow control modes:
 120 .Bl -column xxxxxxx xxxxxxx x
 121 .It Dv RTSXOFF Ta 0000001 Ta "Enable RTS hardware flow control on input."
 122 .It Dv CTSXON Ta 0000002 Ta "Enable CTS hardware flow control on output."
 123 .It Dv DTRXOFF Ta 0000004 Ta "Enable DTR hardware flow control on input."
 124 .It Dv CDXON Ta 0000010 Ta "Enable CD hardware flow control on output."
 125 .It Dv ISXOFF Ta 0000020 Ta "Enable isochronous hardware flow control on input."
 126 .El
 127 .Pp
 128 The EIA-232-D DTR and CD circuits are used to establish a connection between
 129 two systems.
 130 The RTS circuit is also used to establish a connection with a modem.
 131 Thus, both DTR and RTS are activated when an asynchronous port is opened.
 132 If DTR is used for hardware flow control, then RTS must be used for
 133 connectivity.
 134 If CD is used for hardware flow control, then CTS must be used
 135 for connectivity.
 136 Thus, RTS and DTR (or CTS and CD) cannot both be used for
 137 hardware flow control at the same time.
 138 Other mutual exclusions may apply, such as the simultaneous setting of the
 139 .Xr termio 7I
 140 .Dv HUPCL
 141 and the
 142 .Vt termiox
 143 .Dv DTRXOFF
 144 bits, which use the DTE ready line for different functions.
 145 .Pp
 146 Variations of different hardware flow control methods may be selected by
 147 setting the appropriate bits.
 148 For example, bidirectional RTS/CTS flow control is selected by setting both the
 149 .Dv RTSXOFF
 150 and
 151 .Dv CTSXON
 152 bits and bidirectional DTR/CTS flow control is selected by setting both the
 153 .Dv DTRXOFF
 154 and
 155 .Dv CTSXON .
 156 Modem control or unidirectional CTS hardware
 157 flow control is selected by setting only the
 158 .Dv CTSXON
 159 bit.
 160 .Pp
 161 As previously mentioned, it is assumed that the local asynchronous port (for
 162 example, computer) is configured as a DTE.
 163 If the connected device (for example, printer) is also a DTE, it is assumed
 164 that the device is connected to the computer's asynchronous port using a null
 165 modem that swaps control circuits (typically RTS and CTS).
 166 The connected DTE drives RTS and the null modem swaps
 167 RTS and CTS so that the remote RTS is received as CTS by the local DTE.
 168 In the case that
 169 .Dv CTSXON
 170 is set for hardware flow control, printer's lowering
 171 of its RTS would cause CTS seen by the computer to be lowered.
 172 Output to the printer is suspended until the printer's raising of its RTS,
 173 which would cause CTS seen by the computer to be raised.
 174 .Pp
 175 If
 176 .Dv RTSXOFF
 177 is set, the Request To Send (RTS) circuit (line) will be
 178 raised, and if the asynchronous port needs to have its input stopped, it will
 179 lower the Request To Send (RTS) line.
 180 If the RTS line is lowered, it is assumed
 181 that the connected device will stop its output until RTS is raised.
 182 .Pp
 183 If
 184 .Dv CTSXON
 185 is set, output will occur only if the Clear To Send (CTS)
 186 circuit (line) is raised by the connected device.
 187 If the CTS line is lowered by
 188 the connected device, output is suspended until CTS is raised.
 189 .Pp
 190 If
 191 .Dv DTRXOFF
 192 is set, the DTE Ready (DTR) circuit (line) will be raised, and
 193 if the asynchronous port needs to have its input stopped, it will lower the DTE
 194 Ready (DTR) line.
 195 If the DTR line is lowered, it is assumed that the connected
 196 device will stop its output until DTR is raised.
 197 .Pp
 198 If
 199 .Dv CDXON
 200 is set, output will occur only if the Received Line Signal
 201 Detector (CD) circuit (line) is raised by the connected device.
 202 If the CD line
 203 is lowered by the connected device, output is suspended until CD is raised.
 204 .Pp
 205 If
 206 .Dv ISXOFF
 207 is set, and if the isochronous port needs to have its input
 208 stopped, it will stop the outgoing clock signal.
 209 It is assumed that the
 210 connected device is using this clock signal to create its output.
 211 Transit and receive clock sources are programmed using the
 212 .Fa x_cflag
 213 fields.
 214 If the port is not programmed for external clock generation,
 215 .Dv ISXOFF
 216 is ignored.
 217 Output isochronous flow control is supported by appropriate clock source
 218 programming using the
 219 .Fa x_cflag
 220 field and enabled at the remote connected device.
 221 .Pp
 222 The
 223 .Fa x_cflag
 224 field specifies the system treatment of clock modes.
 225 .Bl -column xxxxxxxxx xxxxxxxx l
 226 .It Dv XMTCLK Ta 0000007 Ta "Transmit clock source:"
 227 .It Dv XCIBRG Ta 0000000 Ta "Get transmit clock from internal baud rate generator."
 228 .It Dv XCTSET Ta 0000001 Ta "Get transmit clock from transmitter signal element timing (DCE source) lead, CCITT V\.24 circuit 114, EIA-232-D pin 15."
 229 .It Dv XCRSET Ta 0000002 Ta  Get transmit clock from receiver signal element timing (DCE source) lead, CCITT V\.4 circuit 115, EIA-232-D pin 17."
 230 .It Dv RCVCLK Ta 0000070 Ta "Receive clock source:"
 231 .It Dv RCIBRG Ta 0000000 Ta "Get receive clock from internal baud rate generator."
 232 .It Dv RCTSET Ta 0000010 Ta "Get receive clock from transmitter signal element timing (DCE source) lead, CCITT V\.24 circuit 114, EIA-232-D pin 15."
 233 .It Dv RCRSET Ta 0000020 Ta "Get receive clock from receiver signal element timing (DCE source) lead, CCITT V\.24 circuit 115, EIA-232-D pin 17."
 234 .It Dv TSETCLK Ta 0000700 Ta "Transmitter signal element timing (DTE source) lead, CCITT V\.24 circuit 113, EIA-232-D pin 24, clock source:"
 235 .It Dv TSETCOFF Ta 0000000 Ta "TSET clock not provided."
 236 .It Dv TSETCRBRG Ta 0000100 Ta "Output receive baud rate generator on circuit 113."
 237 .It Dv TSETCTBRG Ta 0000200 Ta "Output transmit baud rate generator on circuit 113"
 238 .It Dv TSETCTSET Ta 0000300 Ta "Output transmitter signal element timing (DCE source) on circuit 113."
 239 .It Dv TSETCRSET Ta 0000400 Ta "Output receiver signal element timing (DCE source) on circuit 113."
 240 .It Dv RSETCLK Ta 0007000 Ta "Receiver signal element timing (DTE source) lead, CCITT V\.24 circuit 128, no EIA-232-D pin, clock source:"
 241 .It Dv RSETCOFF Ta 0000000 Ta "RSET clock not provided."
 242 .It Dv RSETCRBRG Ta 0001000 Ta "Output receive baud rate generator on circuit 128."
 243 .It Dv RSETCTBRG Ta 0002000 Ta "Output transmit baud rate generator on circuit 128."
 244 .It Dv RSETCTSET Ta 0003000 Ta "Output transmitter signal element timing (DCE source) on circuit 128."
 245 .It Dv RSETCRSET Ta 0004000 Ta "Output receiver signal element timing (DCE) on circuit 128."
 246 .El
 247 .Pp
 248 If the
 249 .Fa XMTCLK
 250 field has a value of
 251 .Dv XCIBRG
 252 the transmit clock is taken from the hardware internal baud rate generator, as
 253 in normal asynchronous transmission.
 254 If
 255 .Fa XMTCLK
 256 =
 257 .Dv XCTSET
 258 the transmit clock is taken from
 259 the Transmitter Signal Element Timing (DCE source) circuit.
 260 If
 261 .Fa XMTCLK
 262 =
 263 .Dv XCRSET
 264 the transmit clock is taken from the Receiver Signal Element
 265 Timing (DCE source) circuit.
 266 .Pp
 267 If the
 268 .Fa RCVCLK
 269 field has a value of
 270 .Dv RCIBRG ,
 271 the receive clock is
 272 taken from the hardware Internal Baud Rate Generator, as in normal asynchronous
 273 transmission.
 274 If
 275 .Fa RCVCLK
 276 =
 277 .Dv RCTSET
 278 the receive clock is taken from
 279 the Transmitter Signal Element Timing (DCE source) circuit.
 280 If
 281 .Fa RCVCLK
 282 =
 283 .Dv RCRSET
 284 the receive clock is taken from the Receiver Signal Element Timing
 285 (DCE source) circuit.
 286 .Pp
 287 If the
 288 .Fa TSETCLK
 289 field has a value of
 290 .Dv TSETCOFF
 291 the Transmitter Signal Element Timing (DTE source) circuit is not driven.
 292 If
 293 .Fa TSETCLK
 294 =
 295 .Dv TSETCRBRG
 296 the Transmitter Signal Element Timing (DTE source) circuit is
 297 driven by the Receive Baud Rate Generator.
 298 If
 299 .Fa TSETCLK
 300 =
 301 .Dv TSETCTBRG
 302 the Transmitter Signal Element Timing (DTE source) circuit is driven by the
 303 Transmit Baud Rate Generator.
 304 If
 305 .Fa TSETCLK
 306 =
 307 .Dv TSETCTSET
 308 the Transmitter Signal Element Timing (DTE source) circuit is driven by the
 309 Transmitter Signal Element Timing (DCE source).
 310 If
 311 .Fa TSETCLK
 312 =
 313 .Dv TSETCRBRG
 314 the Transmitter Signal Element Timing (DTE source) circuit is
 315 driven by the Receiver Signal Element Timing (DCE source).
 316 .Pp
 317 If the
 318 .Fa RSETCLK
 319 field has a value of
 320 .Dv RSETCOFF
 321 the Receiver Signal Element Timing (DTE source) circuit is not driven.
 322 If
 323 .Fa RSETCLK
 324 =
 325 .Dv RSETCRBRG
 326 the Receiver Signal Element Timing (DTE source) circuit is
 327 driven by the Receive Baud Rate Generator.
 328 If
 329 .Fa RSETCLK
 330 =
 331 .Dv RSETCTBRG
 332 the Receiver Signal Element Timing (DTE source) circuit is driven by the
 333 Transmit Baud Rate Generator.
 334 If
 335 .Fa RSETCLK
 336 =
 337 .Dv RSETCTSET
 338 the Receiver
 339 Signal Element Timing (DTE source) circuit is driven by the Transmitter Signal
 340 Element Timing (DCE source).
 341 If
 342 .Fa RSETCLK
 343 =
 344 .Dv RSETCRBRG
 345 the Receiver
 346 Signal Element Timing (DTE source) circuit is driven by the Receiver Signal
 347 Element Timing (DCE source).
 348 .Pp
 349 The
 350 .Fa x_rflag
 351 is reserved for future interface definitions and should not
 352 be used by any implementations.
 353 The
 354 .Fa x_sflag
 355 may be used by local
 356 implementations wishing to customize their terminal interface using the
 357 .Nm
 358 ioctl system calls.
 359 .Sh IOCTLS
 360 The
 361 .Xr ioctl 2
 362 system calls have the form:
 363 .Bd -literal -offset 2n
 364 struct termiox *arg;
 365 ioctl(fildes, command, arg);
 366 .Ed
 367 .Pp
 368 The commands using this form are:
 369 .Bl -tag -width TCSETXW
 370 .It Dv TCGETX
 371 The argument is a pointer to a
 372 .Vt termiox
 373 structure.
 374 The current terminal parameters are fetched and stored into that structure.
 375 .It Dv TCSETX
 376 The argument is a pointer to a
 377 .Vt termiox
 378 structure.
 379 The current terminal parameters are set from the values stored in that structure.
 380 The change is immediate.
 381 .It Dv TCSETXW
 382 The argument is a pointer to a
 383 .Vt termiox
 384 structure.
 385 The current terminal parameters are set from the values stored in that structure.
 386 The change occurs after all characters queued for output have been transmitted.
 387 This form should be used when changing parameters that will affect output.
 388 .It Dv TCSETXF
 389 The argument is a pointer to a
 390 .Vt termiox
 391 structure.
 392 The current terminal parameters are set from the values stored in that structure.
 393 The change occurs
 394 after all characters queued for output have been transmitted; all characters
 395 queued for input are discarded and then the change occurs.
 396 .El
 397 .Sh FILES
 398 .Pa /dev/*
 399 .Sh SEE ALSO
 400 .Xr stty 1 ,
 401 .Xr ioctl 2 ,
 402 .Xr termio 7I
 403 .Sh NOTES
 404 The
 405 .Nm termiox Ns Pq 7I
 406 system call is provided for compatibility with previous
 407 releases and its use is discouraged.
 408 Instead, the
 409 .Xr termio 7I
 410 system call is recommended.
 411 See
 412 .Xr termio 7I
 413 for usage information.