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XXXX Nexenta fixes for mpt_sas(7d)
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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 25 */
26 26
27 27 /*
28 28 * Copyright (c) 2000 to 2010, LSI Corporation.
29 29 * All rights reserved.
30 30 *
31 31 * Redistribution and use in source and binary forms of all code within
32 32 * this file that is exclusively owned by LSI, with or without
33 33 * modification, is permitted provided that, in addition to the CDDL 1.0
34 34 * License requirements, the following conditions are met:
35 35 *
36 36 * Neither the name of the author nor the names of its contributors may be
37 37 * used to endorse or promote products derived from this software without
38 38 * specific prior written permission.
39 39 *
40 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
43 43 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
44 44 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
45 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
46 46 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
47 47 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
48 48 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
49 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51 51 * DAMAGE.
52 52 */
53 53
54 54 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
55 55 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
56 56
57 57 #include <sys/byteorder.h>
58 58 #include <sys/isa_defs.h>
59 59 #include <sys/sunmdi.h>
60 60 #include <sys/mdi_impldefs.h>
61 61 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
62 62 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
63 63 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
64 64
65 65 #ifdef __cplusplus
66 66 extern "C" {
67 67 #endif
68 68
69 69 /*
70 70 * Compile options
71 71 */
72 72 #ifdef DEBUG
73 73 #define MPTSAS_DEBUG /* turn on debugging code */
74 74 #endif /* DEBUG */
75 75
76 76 #define MPTSAS_INITIAL_SOFT_SPACE 4
77 77
78 78 #define MAX_MPI_PORTS 16
79 79
80 80 /*
81 81 * Note below macro definition and data type definition
82 82 * are used for phy mask handling, it should be changed
83 83 * simultaneously.
84 84 */
85 85 #define MPTSAS_MAX_PHYS 16
86 86 typedef uint16_t mptsas_phymask_t;
87 87
88 88 #define MPTSAS_INVALID_DEVHDL 0xffff
89 89 #define MPTSAS_SATA_GUID "sata-guid"
90 90
91 91 /*
92 92 * MPT HW defines
93 93 */
94 94 #define MPTSAS_MAX_DISKS_IN_CONFIG 14
95 95 #define MPTSAS_MAX_DISKS_IN_VOL 10
96 96 #define MPTSAS_MAX_HOTSPARES 2
97 97 #define MPTSAS_MAX_RAIDVOLS 2
98 98 #define MPTSAS_MAX_RAIDCONFIGS 5
99 99
100 100 /*
101 101 * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
102 102 * plus two means the prefix 'w' and end of the string '\0'.
103 103 */
104 104 #define MPTSAS_WWN_STRLEN (16 + 2)
105 105 #define MPTSAS_MAX_GUID_LEN 64
106 106
107 107 /*
108 108 * DMA routine flags
109 109 */
110 110 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2
111 111 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4
112 112 #define MPTSAS_DMA_HANDLE_BOUND 0x8
113 113
114 114 /*
115 115 * If the HBA supports DMA or bus-mastering, you may have your own
116 116 * scatter-gather list for physically non-contiguous memory in one
117 117 * I/O operation; if so, there's probably a size for that list.
118 118 * It must be placed in the ddi_dma_lim_t structure, so that the system
119 119 * DMA-support routines can use it to break up the I/O request, so we
120 120 * define it here.
121 121 */
122 122 #if defined(__sparc)
123 123 #define MPTSAS_MAX_DMA_SEGS 1
124 124 #define MPTSAS_MAX_CMD_SEGS 1
125 125 #else
126 126 #define MPTSAS_MAX_DMA_SEGS 256
127 127 #define MPTSAS_MAX_CMD_SEGS 257
128 128 #endif
129 129 #define MPTSAS_MAX_FRAME_SGES(mpt) \
130 130 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
131 131
132 132 /*
133 133 * Caculating how many 64-bit DMA simple elements can be stored in the first
134 134 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
135 135 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in
136 136 * size.
137 137 */
138 138 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
139 139 ((mpt->m_req_frame_size - \
140 140 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12)
141 141
142 142 /*
143 143 * Scatter-gather list structure defined by HBA hardware
144 144 */
145 145 typedef struct NcrTableIndirect { /* Table Indirect entries */
146 146 uint32_t count; /* 24 bit count */
147 147 union {
148 148 uint32_t address32; /* 32 bit address */
149 149 struct {
150 150 uint32_t Low;
151 151 uint32_t High;
152 152 } address64; /* 64 bit address */
153 153 } addr;
154 154 } mptti_t;
155 155
156 156 /*
157 157 * preferred pkt_private length in 64-bit quantities
158 158 */
159 159 #ifdef _LP64
160 160 #define PKT_PRIV_SIZE 2
161 161 #define PKT_PRIV_LEN 16 /* in bytes */
162 162 #else /* _ILP32 */
163 163 #define PKT_PRIV_SIZE 1
164 164 #define PKT_PRIV_LEN 8 /* in bytes */
165 165 #endif
166 166
167 167 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
168 168 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
169 169 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
170 170
171 171 /*
172 172 * get offset of item in structure
173 173 */
174 174 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
175 175
176 176 /*
177 177 * WWID provided by LSI firmware is generated by firmware but the WWID is not
178 178 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
179 179 * address. According LSI's confirmation, the top nibble of RAID WWID is
180 180 * meanless, so the consensus between Solaris and OBP is to replace top nibble
181 181 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
182 182 * format unit address.
183 183 */
184 184 #define MPTSAS_RAID_WWID(wwid) \
185 185 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
186 186
187 187 typedef struct mptsas_target {
188 188 uint64_t m_sas_wwn; /* hash key1 */
189 189 mptsas_phymask_t m_phymask; /* hash key2 */
190 190 /*
191 191 * m_dr_flag is a flag for DR, make sure the member
192 192 * take the place of dr_flag of mptsas_hash_data.
193 193 */
194 194 uint8_t m_dr_flag; /* dr_flag */
195 195 uint16_t m_devhdl;
196 196 uint32_t m_deviceinfo;
197 197 uint8_t m_phynum;
198 198 uint32_t m_dups;
199 199 int32_t m_timeout;
200 200 int32_t m_timebase;
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201 201 int32_t m_t_throttle;
202 202 int32_t m_t_ncmds;
203 203 int32_t m_reset_delay;
204 204 int32_t m_t_nwait;
205 205
206 206 uint16_t m_qfull_retry_interval;
207 207 uint8_t m_qfull_retries;
208 208 uint16_t m_enclosure;
209 209 uint16_t m_slot_num;
210 210 uint32_t m_tgt_unconfigured;
211 + uint32_t m_timeout_interval;
212 + uint8_t m_timeout_count;
211 213
212 - /*
213 - * For the common case, the elements in this structure are
214 - * protected by the per hba instance mutex. In order to make
215 - * the key code path in ISR lockless, a separate mutex is
216 - * introdeced to protect those shown in ISR.
217 - */
218 - kmutex_t m_tgt_intr_mutex;
219 -
220 214 } mptsas_target_t;
221 215
222 216 typedef struct mptsas_smp {
223 217 uint64_t m_sasaddr; /* hash key1 */
224 218 mptsas_phymask_t m_phymask; /* hash key2 */
225 219 uint8_t reserved1;
226 220 uint16_t m_devhdl;
227 221 uint32_t m_deviceinfo;
228 222 uint16_t m_pdevhdl;
229 223 uint32_t m_pdevinfo;
230 224 } mptsas_smp_t;
231 225
232 226 typedef struct mptsas_hash_data {
233 227 uint64_t key1;
234 228 mptsas_phymask_t key2;
235 229 uint8_t dr_flag;
236 230 uint16_t devhdl;
237 231 uint32_t device_info;
238 232 } mptsas_hash_data_t;
239 233
240 234 typedef struct mptsas_cache_frames {
241 235 ddi_dma_handle_t m_dma_hdl;
242 236 ddi_acc_handle_t m_acc_hdl;
243 237 caddr_t m_frames_addr;
244 238 uint32_t m_phys_addr;
245 239 } mptsas_cache_frames_t;
246 240
247 241 typedef struct mptsas_cmd {
248 242 uint_t cmd_flags; /* flags from scsi_init_pkt */
249 243 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
250 244 ddi_dma_cookie_t cmd_cookie;
251 245 uint_t cmd_cookiec;
252 246 uint_t cmd_winindex;
253 247 uint_t cmd_nwin;
254 248 uint_t cmd_cur_cookie;
255 249 off_t cmd_dma_offset;
256 250 size_t cmd_dma_len;
257 251 uint32_t cmd_totaldmacount;
258 252
259 253 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */
260 254 ddi_dma_cookie_t cmd_arqcookie;
261 255 struct buf *cmd_arq_buf;
262 256 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */
263 257 ddi_dma_cookie_t cmd_ext_arqcookie;
264 258 struct buf *cmd_ext_arq_buf;
265 259
266 260 int cmd_pkt_flags;
267 261
268 262 /* timer for command in active slot */
269 263 int cmd_active_timeout;
270 264
271 265 struct scsi_pkt *cmd_pkt;
272 266 struct scsi_arq_status cmd_scb;
273 267 uchar_t cmd_cdblen; /* length of cdb */
274 268 uchar_t cmd_rqslen; /* len of requested rqsense */
275 269 uchar_t cmd_privlen;
276 270 uint_t cmd_scblen;
277 271 uint32_t cmd_dmacount;
278 272 uint64_t cmd_dma_addr;
279 273 uchar_t cmd_age;
280 274 ushort_t cmd_qfull_retries;
281 275 uchar_t cmd_queued; /* true if queued */
282 276 struct mptsas_cmd *cmd_linkp;
283 277 mptti_t *cmd_sg; /* Scatter/Gather structure */
284 278 uchar_t cmd_cdb[SCSI_CDB_SIZE];
285 279 uint64_t cmd_pkt_private[PKT_PRIV_LEN];
286 280 uint32_t cmd_slot;
287 281 uint32_t ioc_cmd_slot;
288 282
289 283 mptsas_cache_frames_t *cmd_extra_frames;
290 284
291 285 uint32_t cmd_rfm;
292 286 mptsas_target_t *cmd_tgt_addr;
293 287 } mptsas_cmd_t;
294 288
295 289 /*
296 290 * These are the defined cmd_flags for this structure.
297 291 */
298 292 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */
299 293 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */
300 294 #define CFLAG_FINISHED 0x000004 /* command completed */
301 295 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */
302 296 #define CFLAG_COMPLETED 0x000010 /* completion routine called */
303 297 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */
304 298 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */
305 299 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */
306 300 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */
307 301 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */
308 302 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */
309 303 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */
310 304 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */
311 305 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */
312 306 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */
313 307 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */
314 308 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */
315 309 #define CFLAG_FREE 0x010000 /* packet is on free list */
316 310 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */
317 311 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */
318 312 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
319 313 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
320 314 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
321 315 #define CFLAG_RETRY 0x400000 /* cmd has been retried */
322 316 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
323 317 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */
324 318 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
325 319 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
326 320 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
327 321 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
328 322 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
329 323 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
330 324 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
331 325
332 326 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
333 327 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
334 328 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
335 329 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
336 330 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
337 331 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0
338 332 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00
339 333 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01
340 334 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10
341 335 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20
342 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30
343 337
344 338 #define MPTSAS_HASH_ARRAY_SIZE 16
345 339 /*
346 340 * hash table definition
347 341 */
348 342
349 343 #define MPTSAS_HASH_FIRST 0xffff
350 344 #define MPTSAS_HASH_NEXT 0x0000
351 345
352 346 typedef struct mptsas_dma_alloc_state
353 347 {
354 348 ddi_dma_handle_t handle;
355 349 caddr_t memp;
356 350 size_t size;
357 351 ddi_acc_handle_t accessp;
358 352 ddi_dma_cookie_t cookie;
359 353 } mptsas_dma_alloc_state_t;
360 354
361 355 /*
362 356 * passthrough request structure
363 357 */
364 358 typedef struct mptsas_pt_request {
365 359 uint8_t *request;
366 360 uint32_t request_size;
367 361 uint32_t data_size;
368 362 uint32_t dataout_size;
369 363 uint32_t direction;
370 364 ddi_dma_cookie_t data_cookie;
371 365 ddi_dma_cookie_t dataout_cookie;
372 366 } mptsas_pt_request_t;
373 367
374 368 /*
375 369 * config page request structure
376 370 */
377 371 typedef struct mptsas_config_request {
378 372 uint32_t page_address;
379 373 uint8_t action;
380 374 uint8_t page_type;
381 375 uint8_t page_number;
382 376 uint8_t page_length;
383 377 uint8_t page_version;
384 378 uint8_t ext_page_type;
385 379 uint16_t ext_page_length;
386 380 } mptsas_config_request_t;
387 381
388 382 typedef struct mptsas_fw_diagnostic_buffer {
389 383 mptsas_dma_alloc_state_t buffer_data;
390 384 uint8_t extended_type;
391 385 uint8_t buffer_type;
392 386 uint8_t force_release;
393 387 uint32_t product_specific[23];
394 388 uint8_t immediate;
395 389 uint8_t enabled;
396 390 uint8_t valid_data;
397 391 uint8_t owned_by_firmware;
398 392 uint32_t unique_id;
399 393 } mptsas_fw_diagnostic_buffer_t;
400 394
401 395 /*
402 396 * FW diag request structure
403 397 */
404 398 typedef struct mptsas_diag_request {
405 399 mptsas_fw_diagnostic_buffer_t *pBuffer;
406 400 uint8_t function;
407 401 } mptsas_diag_request_t;
408 402
409 403 typedef struct mptsas_hash_node {
410 404 void *data;
411 405 struct mptsas_hash_node *next;
412 406 } mptsas_hash_node_t;
413 407
414 408 typedef struct mptsas_hash_table {
415 409 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
416 410 /*
417 411 * last position in traverse
418 412 */
419 413 struct mptsas_hash_node *cur;
420 414 uint16_t line;
421 415
422 416 } mptsas_hash_table_t;
423 417
424 418 /*
425 419 * RAID volume information
426 420 */
427 421 typedef struct mptsas_raidvol {
428 422 ushort_t m_israid;
429 423 uint16_t m_raidhandle;
430 424 uint64_t m_raidwwid;
431 425 uint8_t m_state;
432 426 uint32_t m_statusflags;
433 427 uint32_t m_settings;
434 428 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
435 429 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
436 430 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
437 431 uint64_t m_raidsize;
438 432 int m_raidlevel;
439 433 int m_ndisks;
440 434 mptsas_target_t *m_raidtgt;
441 435 } mptsas_raidvol_t;
442 436
443 437 /*
444 438 * RAID configurations
445 439 */
446 440 typedef struct mptsas_raidconfig {
447 441 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS];
448 442 uint16_t m_physdisk_devhdl[
449 443 MPTSAS_MAX_DISKS_IN_CONFIG];
450 444 uint8_t m_native;
451 445 } m_raidconfig_t;
452 446
453 447 /*
454 448 * Structure to hold active outstanding cmds. Also, keep
455 449 * timeout on a per target basis.
456 450 */
457 451 typedef struct mptsas_slots {
458 452 mptsas_hash_table_t m_tgttbl;
459 453 mptsas_hash_table_t m_smptbl;
460 454 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
461 455 uint8_t m_num_raid_configs;
462 456 uint16_t m_tags;
463 457 size_t m_size;
464 458 uint16_t m_n_slots;
465 459 mptsas_cmd_t *m_slot[1];
466 460 } mptsas_slots_t;
467 461
468 462 /*
469 463 * Structure to hold command and packets for event ack
470 464 * and task management commands.
471 465 */
472 466 typedef struct m_event_struct {
473 467 struct mptsas_cmd m_event_cmd;
474 468 struct m_event_struct *m_event_linkp;
475 469 /*
476 470 * event member record the failure event and eventcntx
477 471 * event member would be used in send ack pending process
478 472 */
479 473 uint32_t m_event;
480 474 uint32_t m_eventcntx;
481 475 uint_t in_use;
482 476 struct scsi_pkt m_event_pkt; /* must be last */
483 477 /* ... scsi_pkt_size() */
484 478 } m_event_struct_t;
485 479 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \
486 480 sizeof (struct scsi_pkt) + scsi_pkt_size())
487 481
488 482 #define MAX_IOC_COMMANDS 8
489 483
490 484 /*
491 485 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
492 486 * A new event ack command requests mptsas_cmd and scsi_pkt structures
493 487 * from this pool, and returns it back when done.
494 488 */
495 489
496 490 typedef struct m_replyh_arg {
497 491 void *mpt;
498 492 uint32_t rfm;
499 493 } m_replyh_arg_t;
500 494 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
501 495 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
502 496
503 497 /*
504 498 * Flags for DR handler topology change
505 499 */
506 500 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0
507 501 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1
508 502 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2
509 503 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4
510 504 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8
511 505 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10
512 506
513 507 typedef struct mptsas_topo_change_list {
514 508 void *mpt;
515 509 uint_t event;
516 510 union {
517 511 uint8_t physport;
518 512 mptsas_phymask_t phymask;
519 513 } un;
520 514 uint16_t devhdl;
521 515 void *object;
522 516 uint8_t flags;
523 517 struct mptsas_topo_change_list *next;
524 518 } mptsas_topo_change_list_t;
525 519
526 520
527 521 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
528 522 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
529 523 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
530 524 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
531 525 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
532 526 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
533 527
534 528 /*
535 529 * Status types when calling mptsas_get_target_device_info
536 530 */
537 531 #define DEV_INFO_SUCCESS 0x0
538 532 #define DEV_INFO_FAIL_PAGE0 0x1
539 533 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2
540 534 #define DEV_INFO_PHYS_DISK 0x3
541 535 #define DEV_INFO_FAIL_ALLOC 0x4
542 536
543 537 /*
544 538 * mpt hotplug event defines
545 539 */
546 540 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
547 541 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
548 542 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
549 543
550 544 /*
551 545 * SMP target hotplug events
552 546 */
553 547 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
554 548 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20
555 549 #define MPTSAS_DR_EVENT_MASK 0x3F
556 550
557 551 /*
558 552 * mpt hotplug status definition for m_dr_flag
559 553 */
560 554
561 555 /*
562 556 * MPTSAS_DR_INACTIVE
563 557 *
564 558 * The target is in a normal operating state.
565 559 * No dynamic reconfiguration operation is in progress.
566 560 */
567 561 #define MPTSAS_DR_INACTIVE 0x0
568 562 /*
569 563 * MPTSAS_DR_INTRANSITION
570 564 *
571 565 * The target is in a transition mode since
572 566 * hotplug event happens and offline procedure has not
573 567 * been finished
574 568 */
575 569 #define MPTSAS_DR_INTRANSITION 0x1
576 570
577 571 typedef struct mptsas_tgt_private {
578 572 int t_lun;
579 573 struct mptsas_target *t_private;
580 574 } mptsas_tgt_private_t;
581 575
582 576 /*
583 577 * The following defines are used in mptsas_set_init_mode to track the current
584 578 * state as we progress through reprogramming the HBA from target mode into
585 579 * initiator mode.
586 580 */
587 581
588 582 #define IOUC_READ_PAGE0 0x00000100
589 583 #define IOUC_READ_PAGE1 0x00000200
590 584 #define IOUC_WRITE_PAGE1 0x00000400
591 585 #define IOUC_DONE 0x00000800
592 586 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
593 587 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
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594 588
595 589 /*
596 590 * Last allocated slot is used for TM requests. Since only m_max_requests
597 591 * frames are allocated, the last SMID will be m_max_requests - 1.
598 592 */
599 593 #define MPTSAS_SLOTS_SIZE(mpt) \
600 594 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
601 595 mpt->m_max_requests))
602 596 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
603 597
604 -typedef struct mptsas_slot_free_e {
605 - processorid_t cpuid;
606 - int slot;
607 - list_node_t node;
608 -} mptsas_slot_free_e_t;
609 -
610 598 /*
611 - * each of the allocq and releaseq in all CPU groups resides in separate
612 - * cacheline(64 bytes). Multiple mutex in the same cacheline is not good
613 - * for performance.
614 - */
615 -typedef union mptsas_slot_freeq {
616 - struct {
617 - kmutex_t m_fq_mutex;
618 - list_t m_fq_list;
619 - int m_fq_n;
620 - int m_fq_n_init;
621 - } s;
622 - char pad[64];
623 -} mptsas_slot_freeq_t;
624 -
625 -typedef struct mptsas_slot_freeq_pair {
626 - mptsas_slot_freeq_t m_slot_allocq;
627 - mptsas_slot_freeq_t m_slot_releq;
628 -} mptsas_slot_freeq_pair_t;
629 -
630 -/*
631 599 * Macro for phy_flags
632 600 */
633 601
634 602 typedef struct smhba_info {
635 603 kmutex_t phy_mutex;
636 604 uint8_t phy_id;
637 605 uint64_t sas_addr;
638 606 char path[8];
639 607 uint16_t owner_devhdl;
640 608 uint16_t attached_devhdl;
641 609 uint8_t attached_phy_identify;
642 610 uint32_t attached_phy_info;
643 611 uint8_t programmed_link_rate;
644 612 uint8_t hw_link_rate;
645 613 uint8_t change_count;
646 614 uint32_t phy_info;
647 615 uint8_t negotiated_link_rate;
648 616 uint8_t port_num;
649 617 kstat_t *phy_stats;
650 618 uint32_t invalid_dword_count;
651 619 uint32_t running_disparity_error_count;
652 620 uint32_t loss_of_dword_sync_count;
653 621 uint32_t phy_reset_problem_count;
654 622 void *mpt;
655 623 } smhba_info_t;
656 624
657 625 typedef struct mptsas_phy_info {
658 626 uint8_t port_num;
659 627 uint8_t port_flags;
660 628 uint16_t ctrl_devhdl;
661 629 uint32_t phy_device_type;
662 630 uint16_t attached_devhdl;
663 631 mptsas_phymask_t phy_mask;
664 632 smhba_info_t smhba_info;
665 633 } mptsas_phy_info_t;
666 634
667 635
668 636 typedef struct mptsas_doneq_thread_arg {
669 637 void *mpt;
670 638 uint64_t t;
671 639 } mptsas_doneq_thread_arg_t;
672 640
673 641 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
674 642 typedef struct mptsas_doneq_thread_list {
675 643 mptsas_cmd_t *doneq;
676 644 mptsas_cmd_t **donetail;
677 645 kthread_t *threadp;
678 646 kcondvar_t cv;
679 647 ushort_t reserv1;
680 648 uint32_t reserv2;
681 649 kmutex_t mutex;
682 650 uint32_t flag;
683 651 uint32_t len;
684 652 mptsas_doneq_thread_arg_t arg;
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685 653 } mptsas_doneq_thread_list_t;
686 654
687 655 typedef struct mptsas {
688 656 int m_instance;
689 657
690 658 struct mptsas *m_next;
691 659
692 660 scsi_hba_tran_t *m_tran;
693 661 smp_hba_tran_t *m_smptran;
694 662 kmutex_t m_mutex;
663 + kmutex_t m_passthru_mutex;
695 664 kcondvar_t m_cv;
665 + kcondvar_t m_passthru_cv;
696 666 kcondvar_t m_fw_cv;
697 667 kcondvar_t m_config_cv;
698 668 kcondvar_t m_fw_diag_cv;
699 669 dev_info_t *m_dip;
700 670
701 671 /*
702 672 * soft state flags
703 673 */
704 674 uint_t m_softstate;
705 675
706 676 struct mptsas_slots *m_active; /* outstanding cmds */
707 677
708 678 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
709 679 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
710 680
681 + kmutex_t m_tx_waitq_mutex;
682 + mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
683 + mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
684 + int m_tx_draining; /* TX queue draining flag */
685 +
711 686 mptsas_cmd_t *m_doneq; /* queue of completed commands */
712 687 mptsas_cmd_t **m_donetail; /* queue tail ptr */
713 688
714 - kmutex_t m_passthru_mutex;
715 - kcondvar_t m_passthru_cv;
716 689 /*
717 690 * variables for helper threads (fan-out interrupts)
718 691 */
719 692 mptsas_doneq_thread_list_t *m_doneq_thread_id;
720 693 uint32_t m_doneq_thread_n;
721 694 uint32_t m_doneq_thread_threshold;
722 695 uint32_t m_doneq_length_threshold;
723 696 uint32_t m_doneq_len;
724 697 kcondvar_t m_doneq_thread_cv;
725 698 kmutex_t m_doneq_mutex;
726 699
727 700 int m_ncmds; /* number of outstanding commands */
728 701 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
729 702 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
730 703
731 704 ddi_acc_handle_t m_datap; /* operating regs data access handle */
732 705
733 706 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
734 707
735 708 ushort_t m_devid; /* device id of chip. */
736 709 uchar_t m_revid; /* revision of chip. */
737 710 uint16_t m_svid; /* subsystem Vendor ID of chip */
738 711 uint16_t m_ssid; /* subsystem Device ID of chip */
739 712
740 713 uchar_t m_sync_offset; /* default offset for this chip. */
741 714
742 715 timeout_id_t m_quiesce_timeid;
743 716
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744 717 ddi_dma_handle_t m_dma_req_frame_hdl;
745 718 ddi_acc_handle_t m_acc_req_frame_hdl;
746 719 ddi_dma_handle_t m_dma_reply_frame_hdl;
747 720 ddi_acc_handle_t m_acc_reply_frame_hdl;
748 721 ddi_dma_handle_t m_dma_free_queue_hdl;
749 722 ddi_acc_handle_t m_acc_free_queue_hdl;
750 723 ddi_dma_handle_t m_dma_post_queue_hdl;
751 724 ddi_acc_handle_t m_acc_post_queue_hdl;
752 725
753 726 /*
754 - * Try the best to make the key code path in the ISR lockless.
755 - * so avoid to use the per instance mutex m_mutex in the ISR. Introduce
756 - * a separate mutex to protect the elements shown in ISR.
757 - */
758 - kmutex_t m_intr_mutex;
759 -
760 - /*
761 727 * list of reset notification requests
762 728 */
763 729 struct scsi_reset_notify_entry *m_reset_notify_listf;
764 730
765 731 /*
766 732 * qfull handling
767 733 */
768 734 timeout_id_t m_restart_cmd_timeid;
769 735
770 736 /*
771 737 * scsi reset delay per bus
772 738 */
773 739 uint_t m_scsi_reset_delay;
774 740
775 741 int m_pm_idle_delay;
776 742
777 743 uchar_t m_polled_intr; /* intr was polled. */
778 744 uchar_t m_suspended; /* true if driver is suspended */
779 745
780 746 struct kmem_cache *m_kmem_cache;
781 747 struct kmem_cache *m_cache_frames;
782 748
783 749 /*
784 750 * hba options.
785 751 */
786 752 uint_t m_options;
787 753
788 754 int m_in_callback;
789 755
790 756 int m_power_level; /* current power level */
791 757
792 758 int m_busy; /* power management busy state */
793 759
794 760 off_t m_pmcsr_offset; /* PMCSR offset */
795 761
796 762 ddi_acc_handle_t m_config_handle;
797 763
798 764 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
799 765 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
800 766 ddi_device_acc_attr_t m_dev_acc_attr;
801 767 ddi_device_acc_attr_t m_reg_acc_attr;
802 768
803 769 /*
804 770 * request/reply variables
805 771 */
806 772 caddr_t m_req_frame;
807 773 uint64_t m_req_frame_dma_addr;
808 774 caddr_t m_reply_frame;
809 775 uint64_t m_reply_frame_dma_addr;
810 776 caddr_t m_free_queue;
811 777 uint64_t m_free_queue_dma_addr;
812 778 caddr_t m_post_queue;
813 779 uint64_t m_post_queue_dma_addr;
814 780
815 781 m_replyh_arg_t *m_replyh_args;
816 782
817 783 uint16_t m_max_requests;
818 784 uint16_t m_req_frame_size;
819 785
820 786 /*
821 787 * Max frames per request reprted in IOC Facts
822 788 */
823 789 uint8_t m_max_chain_depth;
824 790 /*
825 791 * Max frames per request which is used in reality. It's adjusted
826 792 * according DMA SG length attribute, and shall not exceed the
827 793 * m_max_chain_depth.
828 794 */
829 795 uint8_t m_max_request_frames;
830 796
831 797 uint16_t m_free_queue_depth;
832 798 uint16_t m_post_queue_depth;
833 799 uint16_t m_max_replies;
834 800 uint32_t m_free_index;
835 801 uint32_t m_post_index;
836 802 uint8_t m_reply_frame_size;
837 803 uint32_t m_ioc_capabilities;
838 804
839 805 /*
840 806 * indicates if the firmware was upload by the driver
841 807 * at boot time
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842 808 */
843 809 ushort_t m_fwupload;
844 810
845 811 uint16_t m_productid;
846 812
847 813 /*
848 814 * per instance data structures for dma memory resources for
849 815 * MPI handshake protocol. only one handshake cmd can run at a time.
850 816 */
851 817 ddi_dma_handle_t m_hshk_dma_hdl;
852 -
853 818 ddi_acc_handle_t m_hshk_acc_hdl;
854 -
855 819 caddr_t m_hshk_memp;
856 -
857 820 size_t m_hshk_dma_size;
858 821
859 822 /* Firmware version on the card at boot time */
860 823 uint32_t m_fwversion;
861 824
862 825 /* MSI specific fields */
863 826 ddi_intr_handle_t *m_htable; /* For array of interrupts */
864 827 int m_intr_type; /* What type of interrupt */
865 828 int m_intr_cnt; /* # of intrs count returned */
866 829 size_t m_intr_size; /* Size of intr array */
867 830 uint_t m_intr_pri; /* Interrupt priority */
868 831 int m_intr_cap; /* Interrupt capabilities */
869 832 ddi_taskq_t *m_event_taskq;
870 833
871 834 /* SAS specific information */
872 835
873 836 union {
874 837 uint64_t m_base_wwid; /* Base WWID */
875 838 struct {
876 839 #ifdef _BIG_ENDIAN
877 840 uint32_t m_base_wwid_hi;
878 841 uint32_t m_base_wwid_lo;
879 842 #else
880 843 uint32_t m_base_wwid_lo;
881 844 uint32_t m_base_wwid_hi;
882 845 #endif
883 846 } sasaddr;
884 847 } un;
885 848
886 849 uint8_t m_num_phys; /* # of PHYs */
887 850 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS];
888 851 uint8_t m_port_chng; /* initiator port changes */
889 852 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */
890 853 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */
891 854
892 855 /* FMA Capabilities */
893 856 int m_fm_capabilities;
894 857 ddi_taskq_t *m_dr_taskq;
895 858 int m_mpxio_enable;
896 859 uint8_t m_done_traverse_dev;
897 860 uint8_t m_done_traverse_smp;
898 861 int m_diag_action_in_progress;
899 862 uint16_t m_dev_handle;
900 863 uint16_t m_smp_devhdl;
901 864
902 865 /*
903 866 * Event recording
904 867 */
905 868 uint8_t m_event_index;
906 869 uint32_t m_event_number;
907 870 uint32_t m_event_mask[4];
908 871 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
909 872
910 873 /*
911 874 * FW diag Buffer List
912 875 */
913 876 mptsas_fw_diagnostic_buffer_t
914 877 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
915 878
916 879 /*
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917 880 * Event Replay flag (MUR support)
918 881 */
919 882 uint8_t m_event_replay;
920 883
921 884 /*
922 885 * IR Capable flag
923 886 */
924 887 uint8_t m_ir_capable;
925 888
926 889 /*
927 - * release and alloc queue for slot
928 - */
929 - int m_slot_freeq_pair_n;
930 - mptsas_slot_freeq_pair_t *m_slot_freeq_pairp;
931 - mptsas_slot_free_e_t *m_slot_free_ae;
932 -#define MPI_ADDRESS_COALSCE_MAX 128
933 - pMpi2ReplyDescriptorsUnion_t m_reply;
934 -
935 - /*
936 890 * Is HBA processing a diag reset?
937 891 */
938 892 uint8_t m_in_reset;
939 893
940 894 /*
941 895 * per instance cmd data structures for task management cmds
942 896 */
943 897 m_event_struct_t m_event_task_mgmt; /* must be last */
944 898 /* ... scsi_pkt_size */
945 899 } mptsas_t;
946 900 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
947 901 sizeof (struct scsi_pkt) + scsi_pkt_size())
948 902 /*
949 903 * Only one of below two conditions is satisfied, we
950 904 * think the target is associated to the iport and
951 905 * allow call into mptsas_probe_lun().
952 906 * 1. physicalsport == physport
953 907 * 2. (phymask & (1 << physport)) == 0
954 908 * The condition #2 is because LSI uses lowest PHY
955 909 * number as the value of physical port when auto port
956 910 * configuration.
957 911 */
958 912 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
959 913 ((physicalport == physport) || (dynamicport && (phymask & \
960 914 (1 << physport))))
961 915
962 916 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
963 917 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
964 918 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
965 919 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
966 920 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
967 921 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
968 922 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
969 923 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type))
970 924 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
971 925 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets))
972 926 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
973 927
974 928 /*
975 929 * These should eventually migrate into the mpt header files
976 930 * that may become the /kernel/misc/mpt module...
977 931 */
978 932 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
979 933 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
980 934 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
981 935 mptsas_put_msg_Function(hdl, mp, Function); \
982 936 mptsas_put_msg_Lun(hdl, mp, Lun)
983 937
984 938 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
985 939 ddi_put16(hdl, &(mp)->DevHandle, (val))
986 940 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
987 941 ddi_put8(hdl, &(mp)->ChainOffset, (val))
988 942 #define mptsas_put_msg_Function(hdl, mp, val) \
989 943 ddi_put8(hdl, &(mp)->Function, (val))
990 944 #define mptsas_put_msg_Lun(hdl, mp, val) \
991 945 ddi_put8(hdl, &(mp)->LUN[1], (val))
992 946
993 947 #define mptsas_get_msg_Function(hdl, mp) \
994 948 ddi_get8(hdl, &(mp)->Function)
995 949
996 950 #define mptsas_get_msg_MsgFlags(hdl, mp) \
997 951 ddi_get8(hdl, &(mp)->MsgFlags)
998 952
999 953 #define MPTSAS_ENABLE_DRWE(hdl) \
1000 954 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1001 955 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
1002 956 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1003 957 MPI2_WRSEQ_1ST_KEY_VALUE); \
1004 958 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1005 959 MPI2_WRSEQ_2ND_KEY_VALUE); \
1006 960 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1007 961 MPI2_WRSEQ_3RD_KEY_VALUE); \
1008 962 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1009 963 MPI2_WRSEQ_4TH_KEY_VALUE); \
1010 964 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1011 965 MPI2_WRSEQ_5TH_KEY_VALUE); \
1012 966 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1013 967 MPI2_WRSEQ_6TH_KEY_VALUE);
1014 968
1015 969 /*
1016 970 * m_options flags
1017 971 */
1018 972 #define MPTSAS_OPT_PM 0x01 /* Power Management */
1019 973
1020 974 /*
1021 975 * m_softstate flags
1022 976 */
1023 977 #define MPTSAS_SS_DRAINING 0x02
1024 978 #define MPTSAS_SS_QUIESCED 0x04
1025 979 #define MPTSAS_SS_MSG_UNIT_RESET 0x08
1026 980 #define MPTSAS_DID_MSG_UNIT_RESET 0x10
1027 981
1028 982 /*
1029 983 * regspec defines.
1030 984 */
1031 985 #define CONFIG_SPACE 0 /* regset[0] - configuration space */
1032 986 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
1033 987 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
1034 988 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */
1035 989
1036 990 /*
1037 991 * Handy constants
1038 992 */
1039 993 #define FALSE 0
1040 994 #define TRUE 1
1041 995 #define UNDEFINED -1
1042 996 #define FAILED -2
1043 997
1044 998 /*
1045 999 * power management.
1046 1000 */
1047 1001 #define MPTSAS_POWER_ON(mpt) { \
1048 1002 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1049 1003 PCI_PMCSR_D0); \
1050 1004 delay(drv_usectohz(10000)); \
1051 1005 (void) pci_restore_config_regs(mpt->m_dip); \
1052 1006 mptsas_setup_cmd_reg(mpt); \
1053 1007 }
1054 1008
1055 1009 #define MPTSAS_POWER_OFF(mpt) { \
1056 1010 (void) pci_save_config_regs(mpt->m_dip); \
1057 1011 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1058 1012 PCI_PMCSR_D3HOT); \
1059 1013 mpt->m_power_level = PM_LEVEL_D3; \
1060 1014 }
1061 1015
1062 1016 /*
1063 1017 * inq_dtype:
1064 1018 * Bits 5 through 7 are the Peripheral Device Qualifier
1065 1019 * 001b: device not connected to the LUN
1066 1020 * Bits 0 through 4 are the Peripheral Device Type
1067 1021 * 1fh: Unknown or no device type
1068 1022 *
1069 1023 * Although the inquiry may return success, the following value
1070 1024 * means no valid LUN connected.
1071 1025 */
1072 1026 #define MPTSAS_VALID_LUN(sd_inq) \
1073 1027 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1074 1028 ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1075 1029
1076 1030 /*
1077 1031 * Default is to have 10 retries on receiving QFULL status and
1078 1032 * each retry to be after 100 ms.
1079 1033 */
1080 1034 #define QFULL_RETRIES 10
1081 1035 #define QFULL_RETRY_INTERVAL 100
1082 1036
1083 1037 /*
1084 1038 * Handy macros
1085 1039 */
1086 1040 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1087 1041 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1088 1042
1089 1043 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1090 1044 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1091 1045
1092 1046 /*
1093 1047 * poll time for mptsas_pollret() and mptsas_wait_intr()
1094 1048 */
1095 1049 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */
1096 1050
1097 1051 /*
1098 1052 * default time for mptsas_do_passthru
1099 1053 */
1100 1054 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */
1101 1055
1102 1056 /*
1103 1057 * macro to return the effective address of a given per-target field
1104 1058 */
1105 1059 #define EFF_ADDR(start, offset) ((start) + (offset))
1106 1060
1107 1061 #define SDEV2ADDR(devp) (&((devp)->sd_address))
1108 1062 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran)
1109 1063 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran)
1110 1064 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
1111 1065 #define DIP2TRAN(dip) (ddi_get_driver_private(dip))
1112 1066
1113 1067
1114 1068 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private)
1115 1069 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1116 1070 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd)))
1117 1071 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt)))
1118 1072
1119 1073 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap)))
1120 1074
1121 1075 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000)
1122 1076 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */
1123 1077 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */
1124 1078 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */
1125 1079
1126 1080 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \
1127 1081 &(mpt)->m_reg->HostInterruptStatus))
1128 1082
1129 1083 #define MPTSAS_SET_SIGP(P) \
1130 1084 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1131 1085
1132 1086 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1133 1087 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1134 1088
1135 1089 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1136 1090 (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1137 1091
1138 1092
1139 1093 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \
1140 1094 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\
1141 1095 req_desc_lo);\
1142 1096 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\
1143 1097 req_desc_hi);
1144 1098
1145 1099 #define INTPENDING(mpt) \
1146 1100 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1147 1101
1148 1102 /*
1149 1103 * Mask all interrupts to disable
1150 1104 */
1151 1105 #define MPTSAS_DISABLE_INTR(mpt) \
1152 1106 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1153 1107 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1154 1108
1155 1109 /*
1156 1110 * Mask Doorbell and Reset interrupts to enable reply desc int.
1157 1111 */
1158 1112 #define MPTSAS_ENABLE_INTR(mpt) \
1159 1113 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1160 1114 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1161 1115
1162 1116 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \
1163 1117 &((uint64_t *)(void *)mpt->m_post_queue)[index]
1164 1118
1165 1119 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1166 1120 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1167 1121
1168 1122 #define ClrSetBits32(hdl, reg, clr, set) \
1169 1123 ddi_put32(hdl, (reg), \
1170 1124 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1171 1125
1172 1126 #define ClrSetBits(reg, clr, set) \
1173 1127 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1174 1128 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1175 1129
1176 1130 #define MPTSAS_WAITQ_RM(mpt, cmdp) \
1177 1131 if ((cmdp = mpt->m_waitq) != NULL) { \
1178 1132 /* If the queue is now empty fix the tail pointer */ \
1179 1133 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1180 1134 mpt->m_waitqtail = &mpt->m_waitq; \
1181 1135 cmdp->cmd_linkp = NULL; \
1182 1136 cmdp->cmd_queued = FALSE; \
1183 1137 }
1184 1138
1185 1139 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \
1186 1140 if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1187 1141 /* If the queue is now empty fix the tail pointer */ \
1188 1142 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1189 1143 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1190 1144 cmdp->cmd_linkp = NULL; \
1191 1145 cmdp->cmd_queued = FALSE; \
1192 1146 }
1193 1147
1194 1148 /*
1195 1149 * defaults for the global properties
1196 1150 */
1197 1151 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
1198 1152 #define DEFAULT_TAG_AGE_LIMIT 2
1199 1153 #define DEFAULT_WD_TICK 10
1200 1154
1201 1155 /*
1202 1156 * invalid hostid.
1203 1157 */
1204 1158 #define MPTSAS_INVALID_HOSTID -1
1205 1159
1206 1160 /*
1207 1161 * Get/Set hostid from SCSI port configuration page
1208 1162 */
1209 1163 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1210 1164 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1211 1165
1212 1166 /*
1213 1167 * Config space.
1214 1168 */
1215 1169 #define MPTSAS_LATENCY_TIMER 0x40
1216 1170
1217 1171 /*
1218 1172 * Offset to firmware version
1219 1173 */
1220 1174 #define MPTSAS_FW_VERSION_OFFSET 9
1221 1175
1222 1176 /*
1223 1177 * Offset and masks to get at the ProductId field
1224 1178 */
1225 1179 #define MPTSAS_FW_PRODUCTID_OFFSET 8
1226 1180 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000
1227 1181 #define MPTSAS_FW_PRODUCTID_SHIFT 16
1228 1182
1229 1183 /*
1230 1184 * Subsystem ID for HBAs.
1231 1185 */
1232 1186 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1233 1187 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1234 1188
1235 1189 /*
1236 1190 * reset delay tick
1237 1191 */
1238 1192 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1239 1193
1240 1194 /*
1241 1195 * Ioc reset return values
1242 1196 */
1243 1197 #define MPTSAS_RESET_FAIL -1
1244 1198 #define MPTSAS_NO_RESET 0
1245 1199 #define MPTSAS_SUCCESS_HARDRESET 1
1246 1200 #define MPTSAS_SUCCESS_MUR 2
1247 1201
1248 1202 /*
1249 1203 * throttle support.
1250 1204 */
1251 1205 #define MAX_THROTTLE 32
1252 1206 #define HOLD_THROTTLE 0
1253 1207 #define DRAIN_THROTTLE -1
1254 1208 #define QFULL_THROTTLE -2
1255 1209
1256 1210 /*
1257 1211 * Passthrough/config request flags
1258 1212 */
1259 1213 #define MPTSAS_DATA_ALLOCATED 0x0001
1260 1214 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1261 1215 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1262 1216 #define MPTSAS_ADDRESS_REPLY 0x0008
1263 1217 #define MPTSAS_CMD_TIMEOUT 0x0010
1264 1218
1265 1219 /*
1266 1220 * response code tlr flag
1267 1221 */
1268 1222 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1269 1223
1270 1224 /*
1271 1225 * System Events
1272 1226 */
1273 1227 #ifndef DDI_VENDOR_LSI
1274 1228 #define DDI_VENDOR_LSI "LSI"
1275 1229 #endif /* DDI_VENDOR_LSI */
1276 1230
1277 1231 /*
1278 1232 * Shared functions
1279 1233 */
1280 1234 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1281 1235 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1282 1236 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1283 1237 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1284 1238 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1285 1239 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1286 1240 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1287 1241 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1288 1242 uint8_t pageversion, uint8_t pagelength, uint32_t
1289 1243 SGEflagslength, uint32_t SGEaddress32);
1290 1244 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1291 1245 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1292 1246 uint8_t pageversion, uint16_t extpagelength,
1293 1247 uint32_t SGEflagslength, uint32_t SGEaddress32);
1294 1248 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1295 1249 uint8_t type, int mode);
1296 1250 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1297 1251 uint8_t type, int mode);
1298 1252 int mptsas_download_firmware();
1299 1253 int mptsas_can_download_firmware();
1300 1254 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1301 1255 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1302 1256 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1303 1257 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1304 1258 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1305 1259 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1306 1260 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1307 1261 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1308 1262 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1309 1263 uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1310 1264 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1311 1265
1312 1266 /*
1313 1267 * impl functions
1314 1268 */
1315 1269 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1316 1270 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1317 1271 int mptsas_ioc_reset(mptsas_t *mpt, int);
1318 1272 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1319 1273 ddi_acc_handle_t accessp);
1320 1274 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1321 1275 ddi_acc_handle_t accessp);
1322 1276 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1323 1277 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1324 1278 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1325 1279 uint32_t SGEaddress32);
1326 1280 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1327 1281 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1328 1282 uint8_t pageversion, uint16_t extpagelength,
1329 1283 uint32_t SGEflagslength, uint32_t SGEaddress32);
1330 1284
1331 1285 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1332 1286 struct scsi_pkt **pkt);
1333 1287 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1334 1288 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1335 1289 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1336 1290 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1337 1291 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1338 1292 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1339 1293
1340 1294 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1341 1295 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1342 1296 int mode);
1343 1297 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1344 1298 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1345 1299 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1346 1300 int mptsas_restart_ioc(mptsas_t *mpt);
1347 1301 void mptsas_update_driver_data(struct mptsas *mpt);
1348 1302 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1349 1303
1350 1304 /*
1351 1305 * init functions
1352 1306 */
1353 1307 int mptsas_ioc_get_facts(mptsas_t *mpt);
1354 1308 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1355 1309 int mptsas_ioc_enable_port(mptsas_t *mpt);
1356 1310 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1357 1311 int mptsas_ioc_init(mptsas_t *mpt);
1358 1312
1359 1313 /*
1360 1314 * configuration pages operation
1361 1315 */
1362 1316 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1363 1317 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1364 1318 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1365 1319 uint16_t *slot_num, uint16_t *enclosure);
1366 1320 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1367 1321 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1368 1322 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1369 1323 mptsas_smp_t *info);
1370 1324 int mptsas_set_ioc_params(mptsas_t *mpt);
1371 1325 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1372 1326 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1373 1327 uint64_t *sas_wwn, uint8_t *portwidth);
1374 1328 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version);
1375 1329 int
1376 1330 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1377 1331 smhba_info_t *info);
1378 1332 int
1379 1333 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1380 1334 smhba_info_t *info);
1381 1335 int
1382 1336 mptsas_get_manufacture_page0(mptsas_t *mpt);
1383 1337 void
1384 1338 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1385 1339 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1386 1340 int mptsas_smhba_phy_init(mptsas_t *mpt);
1387 1341 /*
1388 1342 * RAID functions
1389 1343 */
1390 1344 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1391 1345 int mptsas_get_raid_info(mptsas_t *mpt);
1392 1346 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1393 1347 uint8_t physdisknum);
1394 1348 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1395 1349 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1396 1350
1397 1351 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1398 1352 /*
1399 1353 * debugging.
1400 1354 */
1401 1355 #if defined(MPTSAS_DEBUG)
1402 1356
1403 1357 void mptsas_printf(char *fmt, ...);
1404 1358
1405 1359 #define MPTSAS_DBGPR(m, args) \
1406 1360 if (mptsas_debug_flags & (m)) \
1407 1361 mptsas_printf args
1408 1362 #else /* ! defined(MPTSAS_DEBUG) */
1409 1363 #define MPTSAS_DBGPR(m, args)
1410 1364 #endif /* defined(MPTSAS_DEBUG) */
1411 1365
1412 1366 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
1413 1367 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */
1414 1368 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
1415 1369 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
1416 1370
1417 1371 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
1418 1372 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
1419 1373 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
1420 1374 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
1421 1375
1422 1376 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
1423 1377 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
1424 1378 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
1425 1379 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
1426 1380
1427 1381 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
1428 1382 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
1429 1383 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
1430 1384 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args)
1431 1385
1432 1386 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args)
1433 1387 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
1434 1388 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
1435 1389 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
1436 1390
1437 1391 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
1438 1392 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
1439 1393 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
1440 1394 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */
1441 1395
1442 1396 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */
1443 1397 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */
1444 1398 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args)
1445 1399 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args)
1446 1400
1447 1401 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */
1448 1402 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */
1449 1403 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */
1450 1404 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */
1451 1405
1452 1406 /*
1453 1407 * auto request sense
1454 1408 */
1455 1409 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1456 1410 (pkt)->pkt_flags = (flag), \
1457 1411 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1458 1412 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1459 1413 (pkt)->pkt_address.a_lun
1460 1414
1461 1415 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1462 1416 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1463 1417 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1464 1418 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1465 1419
1466 1420
1467 1421 #ifdef __cplusplus
1468 1422 }
1469 1423 #endif
1470 1424
1471 1425 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */
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