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4431 igb support for I354
4616 igb has uninitialized kstats
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--- old/usr/src/uts/common/io/e1000api/e1000_regs.h
+++ new/usr/src/uts/common/io/e1000api/e1000_regs.h
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2013, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD$*/
34 34
35 35 #ifndef _E1000_REGS_H_
36 36 #define _E1000_REGS_H_
37 37
38 38 #ifdef __cplusplus
39 39 extern "C" {
40 40 #endif
41 41
42 42 #define E1000_CTRL 0x00000 /* Device Control - RW */
43 43 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
44 44 #define E1000_STATUS 0x00008 /* Device Status - RO */
45 45 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
46 46 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
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47 47 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
48 48 #define E1000_FLA 0x0001C /* Flash Access - RW */
49 49 #define E1000_MDIC 0x00020 /* MDI Control - RW */
50 50 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
51 51 #define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */
52 52 #define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */
53 53 #define E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */
54 54 #define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */
55 55 #define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */
56 56 #define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */
57 +#define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */
58 +#define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */
59 +#define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */
60 +#define E1000_PPHY_CTRL 0x5b48 /* PCIe PHY Control */
57 61 #define E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */
58 62 #define E1000_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/
59 63 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
60 64 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
61 65 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
62 66 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
63 67 #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
64 68 #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
65 69 #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
66 70 #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
67 71 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
68 72 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
69 73 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
70 74 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
71 75 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
72 76 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
73 77 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
74 78 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
75 79 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
76 80 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
77 81 #define E1000_SVCR 0x000F0
78 82 #define E1000_SVT 0x000F4
79 83 #define E1000_LPIC 0x000FC /* Low Power IDLE control */
80 84 #define E1000_RCTL 0x00100 /* Rx Control - RW */
81 85 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
82 86 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
83 87 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
84 88 #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */
85 89 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
86 90 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
87 91 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
88 92 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
89 93 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
90 94 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
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91 95 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
92 96 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
93 97 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
94 98 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
95 99 #define E1000_TCTL 0x00400 /* Tx Control - RW */
96 100 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
97 101 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
98 102 #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
99 103 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
100 104 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
105 +#define E1000_LEDMUX 0x08130 /* LED MUX Control */
101 106 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
102 107 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
103 108 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
104 109 #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
105 110 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
106 111 #define E1000_PBS 0x01008 /* Packet Buffer Size */
107 112 #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
108 113 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
109 114 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
110 115 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
111 116 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
112 117 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
113 118 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
114 119 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
115 120 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
116 121 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
117 122 #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
118 123 #define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */
119 124 #define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */
120 125 #define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */
121 126 #define E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */
122 127 #define E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */
123 128 #define E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */
124 129 #define E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */
125 130 #define E1000_I2C_CLK_STRETCH_DIS 0x00008000 /* I2C- Dis Clk Stretching */
126 131 #define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */
127 132 #define E1000_SWDSTS 0x01044 /* SW Device Status - RW */
128 133 #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
129 134 #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
130 135 #define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */
131 136 #define E1000_ICR_V2 0x01500 /* Intr Cause - new location - RC */
132 137 #define E1000_ICS_V2 0x01504 /* Intr Cause Set - new location - WO */
133 138 #define E1000_IMS_V2 0x01508 /* Intr Mask Set/Read - new location - RW */
134 139 #define E1000_IMC_V2 0x0150C /* Intr Mask Clear - new location - WO */
135 140 #define E1000_IAM_V2 0x01510 /* Intr Ack Auto Mask - new location - RW */
136 141 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
137 142 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
138 143 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
139 144 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
140 145 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
141 146 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
142 147 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
143 148 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
144 149 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
145 150 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
146 151 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
147 152 /* Split and Replication Rx Control - RW */
148 153 #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
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149 154 #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
150 155 #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
151 156 #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
152 157 #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
153 158 #define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */
154 159 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
155 160 #define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */
156 161 #define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */
157 162 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
158 163 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
164 +#define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */
165 +#define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */
159 166 #define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */
160 167 #define E1000_I210_FLMNGCTL 0x12038
161 168 #define E1000_I210_FLMNGDATA 0x1203C
162 169 #define E1000_I210_FLMNGCNT 0x12040
163 170
164 171 #define E1000_I210_FLSWCTL 0x12048
165 172 #define E1000_I210_FLSWDATA 0x1204C
166 173 #define E1000_I210_FLSWCNT 0x12050
167 174
168 175 #define E1000_I210_FLA 0x1201C
169 176
170 177 #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))
171 178 #define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */
172 179
173 180 /* QAV Tx mode control register */
174 181 #define E1000_I210_TQAVCTRL 0x3570
175 182
176 183 /* QAV Tx mode control register bitfields masks */
177 184 /* QAV enable */
178 185 #define E1000_TQAVCTRL_MODE (1 << 0)
179 186 /* Fetching arbitration type */
180 187 #define E1000_TQAVCTRL_FETCH_ARB (1 << 4)
181 188 /* Fetching timer enable */
182 189 #define E1000_TQAVCTRL_FETCH_TIMER_ENABLE (1 << 5)
183 190 /* Launch arbitration type */
184 191 #define E1000_TQAVCTRL_LAUNCH_ARB (1 << 8)
185 192 /* Launch timer enable */
186 193 #define E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE (1 << 9)
187 194 /* SP waits for SR enable */
188 195 #define E1000_TQAVCTRL_SP_WAIT_SR (1 << 10)
189 196 /* Fetching timer correction */
190 197 #define E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET 16
191 198 #define E1000_TQAVCTRL_FETCH_TIMER_DELTA \
192 199 (0xFFFF << E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET)
193 200
194 201 /* High credit registers where _n can be 0 or 1. */
195 202 #define E1000_I210_TQAVHC(_n) (0x300C + 0x40 * (_n))
196 203
197 204 /* Queues fetch arbitration priority control register */
198 205 #define E1000_I210_TQAVARBCTRL 0x3574
199 206 /* Queues priority masks where _n and _p can be 0-3. */
200 207 #define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * _n))
201 208 /* QAV Tx mode control registers where _n can be 0 or 1. */
202 209 #define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n))
203 210
204 211 /* QAV Tx mode control register bitfields masks */
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205 212 #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */
206 213 #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */
207 214 #define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */
208 215
209 216 /* Good transmitted packets counter registers */
210 217 #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))
211 218
212 219 /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
213 220 #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n))
214 221
222 +#define E1000_MMDAC 13 /* MMD Access Control */
223 +#define E1000_MMDAAD 14 /* MMD Access Address/Data */
224 +
215 225 /* Convenience macros
216 226 *
217 227 * Note: "_n" is the queue number of the register to be written to.
218 228 *
219 229 * Example usage:
220 230 * E1000_RDBAL_REG(current_rx_queue)
221 231 */
222 232 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
223 233 (0x0C000 + ((_n) * 0x40)))
224 234 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
225 235 (0x0C004 + ((_n) * 0x40)))
226 236 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
227 237 (0x0C008 + ((_n) * 0x40)))
228 238 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
229 239 (0x0C00C + ((_n) * 0x40)))
230 240 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
231 241 (0x0C010 + ((_n) * 0x40)))
232 242 #define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
233 243 (0x0C014 + ((_n) * 0x40)))
234 244 #define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
235 245 #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
236 246 (0x0C018 + ((_n) * 0x40)))
237 247 #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
238 248 (0x0C028 + ((_n) * 0x40)))
239 249 #define E1000_RQDPC(_n) ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
240 250 (0x0C030 + ((_n) * 0x40)))
241 251 #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
242 252 (0x0E000 + ((_n) * 0x40)))
243 253 #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
244 254 (0x0E004 + ((_n) * 0x40)))
245 255 #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
246 256 (0x0E008 + ((_n) * 0x40)))
247 257 #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
248 258 (0x0E010 + ((_n) * 0x40)))
249 259 #define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
250 260 (0x0E014 + ((_n) * 0x40)))
251 261 #define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
252 262 #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
253 263 (0x0E018 + ((_n) * 0x40)))
254 264 #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
255 265 (0x0E028 + ((_n) * 0x40)))
256 266 #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
257 267 (0x0E038 + ((_n) * 0x40)))
258 268 #define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
259 269 (0x0E03C + ((_n) * 0x40)))
260 270 #define E1000_TARC(_n) (0x03840 + ((_n) * 0x100))
261 271 #define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
262 272 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
263 273 #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
264 274 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
265 275 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
266 276 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
267 277 (0x054E0 + ((_i - 16) * 8)))
268 278 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
269 279 (0x054E4 + ((_i - 16) * 8)))
270 280 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
271 281 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
272 282 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
273 283 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
274 284 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
275 285 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
276 286 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
277 287 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
278 288 #define E1000_PBSLAC 0x03100 /* Pkt Buffer Slave Access Control */
279 289 #define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */
280 290 #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
281 291 /* Same as TXPBS, renamed for newer Si - RW */
282 292 #define E1000_ITPBS 0x03404
283 293 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
284 294 #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
285 295 #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
286 296 #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
287 297 #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
288 298 #define E1000_TDPUMB 0x0357C /* DMA Tx Desc uC Mail Box - RW */
289 299 #define E1000_TDPUAD 0x03580 /* DMA Tx Desc uC Addr Command - RW */
290 300 #define E1000_TDPUWD 0x03584 /* DMA Tx Desc uC Data Write - RW */
291 301 #define E1000_TDPURD 0x03588 /* DMA Tx Desc uC Data Read - RW */
292 302 #define E1000_TDPUCTL 0x0358C /* DMA Tx Desc uC Control - RW */
293 303 #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
294 304 #define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
295 305 #define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
296 306 /* DMA Tx Max Total Allow Size Reqs - RW */
297 307 #define E1000_DTXMXSZRQ 0x03540
298 308 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
299 309 #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
300 310 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
301 311 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
302 312 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
303 313 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
304 314 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
305 315 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
306 316 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
307 317 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
308 318 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
309 319 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
310 320 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
311 321 #define E1000_DC 0x04030 /* Defer Count - R/clr */
312 322 #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
313 323 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
314 324 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
315 325 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
316 326 #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
317 327 #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
318 328 #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
319 329 #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
320 330 #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
321 331 #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
322 332 #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
323 333 #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
324 334 #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
325 335 #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
326 336 #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
327 337 #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
328 338 #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
329 339 #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
330 340 #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
331 341 #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
332 342 #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
333 343 #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
334 344 #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
335 345 #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
336 346 #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
337 347 #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
338 348 #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
339 349 #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
340 350 #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
341 351 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
342 352 #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
343 353 #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
344 354 #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
345 355 #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
346 356 #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
347 357 #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
348 358 #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
349 359 #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
350 360 #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
351 361 #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
352 362 #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
353 363 #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
354 364 #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
355 365 #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
356 366 #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
357 367 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
358 368 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
359 369 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */
360 370 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
361 371 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
362 372 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */
363 373 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */
364 374 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
365 375 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */
366 376 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */
367 377 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
368 378 #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */
369 379
370 380 #define E1000_VFGPRC 0x00F10
371 381 #define E1000_VFGORC 0x00F18
372 382 #define E1000_VFMPRC 0x00F3C
373 383 #define E1000_VFGPTC 0x00F14
374 384 #define E1000_VFGOTC 0x00F34
375 385 #define E1000_VFGOTLBC 0x00F50
376 386 #define E1000_VFGPTLBC 0x00F44
377 387 #define E1000_VFGORLBC 0x00F48
378 388 #define E1000_VFGPRLBC 0x00F40
379 389 /* Virtualization statistical counters */
380 390 #define E1000_PFVFGPRC(_n) (0x010010 + (0x100 * (_n)))
381 391 #define E1000_PFVFGPTC(_n) (0x010014 + (0x100 * (_n)))
382 392 #define E1000_PFVFGORC(_n) (0x010018 + (0x100 * (_n)))
383 393 #define E1000_PFVFGOTC(_n) (0x010034 + (0x100 * (_n)))
384 394 #define E1000_PFVFMPRC(_n) (0x010038 + (0x100 * (_n)))
385 395 #define E1000_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n)))
386 396 #define E1000_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n)))
387 397 #define E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n)))
388 398 #define E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n)))
389 399
390 400 /* LinkSec */
391 401 #define E1000_LSECTXUT 0x04300 /* Tx Untagged Pkt Cnt */
392 402 #define E1000_LSECTXPKTE 0x04304 /* Encrypted Tx Pkts Cnt */
393 403 #define E1000_LSECTXPKTP 0x04308 /* Protected Tx Pkt Cnt */
394 404 #define E1000_LSECTXOCTE 0x0430C /* Encrypted Tx Octets Cnt */
395 405 #define E1000_LSECTXOCTP 0x04310 /* Protected Tx Octets Cnt */
396 406 #define E1000_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */
397 407 #define E1000_LSECRXOCTD 0x0431C /* Rx Octets Decrypted Count */
398 408 #define E1000_LSECRXOCTV 0x04320 /* Rx Octets Validated */
399 409 #define E1000_LSECRXBAD 0x04324 /* Rx Bad Tag */
400 410 #define E1000_LSECRXNOSCI 0x04328 /* Rx Packet No SCI Count */
401 411 #define E1000_LSECRXUNSCI 0x0432C /* Rx Packet Unknown SCI Count */
402 412 #define E1000_LSECRXUNCH 0x04330 /* Rx Unchecked Packets Count */
403 413 #define E1000_LSECRXDELAY 0x04340 /* Rx Delayed Packet Count */
404 414 #define E1000_LSECRXLATE 0x04350 /* Rx Late Packets Count */
405 415 #define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */
406 416 #define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */
407 417 #define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */
408 418 #define E1000_LSECRXUNSA 0x043C0 /* Rx Unused SA Count */
409 419 #define E1000_LSECRXNUSA 0x043D0 /* Rx Not Using SA Count */
410 420 #define E1000_LSECTXCAP 0x0B000 /* Tx Capabilities Register - RO */
411 421 #define E1000_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */
412 422 #define E1000_LSECTXCTRL 0x0B004 /* Tx Control - RW */
413 423 #define E1000_LSECRXCTRL 0x0B304 /* Rx Control - RW */
414 424 #define E1000_LSECTXSCL 0x0B008 /* Tx SCI Low - RW */
415 425 #define E1000_LSECTXSCH 0x0B00C /* Tx SCI High - RW */
416 426 #define E1000_LSECTXSA 0x0B010 /* Tx SA0 - RW */
417 427 #define E1000_LSECTXPN0 0x0B018 /* Tx SA PN 0 - RW */
418 428 #define E1000_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */
419 429 #define E1000_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */
420 430 #define E1000_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */
421 431 /* LinkSec Tx 128-bit Key 0 - WO */
422 432 #define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n)))
423 433 /* LinkSec Tx 128-bit Key 1 - WO */
424 434 #define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n)))
425 435 #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
426 436 #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
427 437 /* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
428 438 * key - RW.
429 439 */
430 440 #define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
431 441
432 442 #define E1000_SSVPC 0x041A0 /* Switch Security Violation Pkt Cnt */
433 443 #define E1000_IPSCTRL 0xB430 /* IpSec Control Register */
434 444 #define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */
435 445 #define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */
436 446 /* IPSec Rx IPv4/v6 Address - RW */
437 447 #define E1000_IPSRXIPADDR(_n) (0x0B420 + (0x04 * (_n)))
438 448 /* IPSec Rx 128-bit Key - RW */
439 449 #define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n)))
440 450 #define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */
441 451 #define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */
442 452 /* IPSec Tx 128-bit Key - RW */
443 453 #define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n)))
444 454 #define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */
445 455 #define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */
446 456 #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
447 457 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
448 458 #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
449 459 #define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */
450 460 #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
451 461 #define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */
452 462 #define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */
453 463 #define E1000_RPTHC 0x04104 /* Rx Packets To Host */
454 464 #define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */
455 465 #define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */
456 466 #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
457 467 #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
458 468 #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
459 469 #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
460 470 #define E1000_LENERRS 0x04138 /* Length Errors Count */
461 471 #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
462 472 #define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */
463 473 #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
464 474 #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
465 475 #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
466 476 #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */
467 477 #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
468 478 #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */
469 479 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/
470 480 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
471 481 #define E1000_RA 0x05400 /* Receive Address - RW Array */
472 482 #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */
473 483 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
474 484 #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
475 485 #define E1000_CIAA 0x05B88 /* Config Indirect Access Address - RW */
476 486 #define E1000_CIAD 0x05B8C /* Config Indirect Access Data - RW */
477 487 #define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */
478 488 #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */
479 489 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
480 490 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
481 491 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
482 492 #define E1000_MANC 0x05820 /* Management Control - RW */
483 493 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
484 494 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
485 495 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
486 496 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
487 497 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
488 498 #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
489 499 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
490 500 #define E1000_HOST_IF 0x08800 /* Host Interface */
491 501 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
492 502 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
493 503 #define E1000_HIBBA 0x8F40 /* Host Interface Buffer Base Address */
494 504 /* Flexible Host Filter Table */
495 505 #define E1000_FHFT(_n) (0x09000 + ((_n) * 0x100))
496 506 /* Ext Flexible Host Filter Table */
497 507 #define E1000_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100))
498 508
499 509
500 510 #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
501 511 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
502 512 /* Management Decision Filters */
503 513 #define E1000_MDEF(_n) (0x05890 + (4 * (_n)))
504 514 #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
505 515 #define E1000_CCMCTL 0x05B48 /* CCM Control Register */
506 516 #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
507 517 #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
508 518 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
509 519 #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */
510 520 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
511 521 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
512 522 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
513 523 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
514 524 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
515 525 #define E1000_SWSM 0x05B50 /* SW Semaphore */
516 526 #define E1000_FWSM 0x05B54 /* FW Semaphore */
517 527 /* Driver-only SW semaphore (not used by BOOT agents) */
518 528 #define E1000_SWSM2 0x05B58
519 529 #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
520 530 #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
521 531 #define E1000_UFUSE 0x05B78 /* UFUSE - RO */
522 532 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
523 533 #define E1000_HICR 0x08F00 /* Host Interface Control */
524 534 #define E1000_FWSTS 0x08F0C /* FW Status */
525 535
526 536 /* RSS registers */
527 537 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
528 538 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
529 539 #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
530 540 #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/
531 541 #define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
532 542 #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
533 543 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
534 544 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
535 545 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
536 546 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
537 547 /* VT Registers */
538 548 #define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */
539 549 #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */
540 550 #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */
541 551 #define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */
542 552 #define E1000_VFRE 0x00C8C /* VF Receive Enables */
543 553 #define E1000_VFTE 0x00C90 /* VF Transmit Enables */
544 554 #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */
545 555 #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */
546 556 #define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */
547 557 #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */
548 558 #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */
549 559 #define E1000_IOVTCL 0x05BBC /* IOV Control Register */
550 560 #define E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */
551 561 #define E1000_VMRVLAN 0x05D90 /* Virtual Mirror Rule VLAN */
552 562 #define E1000_VMRVM 0x05DA0 /* Virtual Mirror Rule VM */
553 563 #define E1000_MDFB 0x03558 /* Malicious Driver free block */
554 564 #define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */
555 565 #define E1000_TXSWC 0x05ACC /* Tx Switch Control */
556 566 #define E1000_SCCRL 0x05DB0 /* Storm Control Control */
557 567 #define E1000_BSCTRH 0x05DB8 /* Broadcast Storm Control Threshold */
558 568 #define E1000_MSCTRH 0x05DBC /* Multicast Storm Control Threshold */
559 569 /* These act per VF so an array friendly macro is used */
560 570 #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
561 571 #define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n)))
562 572 #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
563 573 #define E1000_VFVMBMEM(_n) (0x00800 + (_n))
564 574 #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n)))
565 575 /* VLAN Virtual Machine Filter - RW */
566 576 #define E1000_VLVF(_n) (0x05D00 + (4 * (_n)))
567 577 #define E1000_VMVIR(_n) (0x03700 + (4 * (_n)))
568 578 #define E1000_DVMOLR(_n) (0x0C038 + (0x40 * (_n))) /* DMA VM offload */
569 579 #define E1000_VTCTRL(_n) (0x10000 + (0x100 * (_n))) /* VT Control */
570 580 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
571 581 #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
572 582 #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
573 583 #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
574 584 #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
575 585 #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */
576 586 #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */
577 587 #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
578 588 #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
579 589 #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */
580 590 #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */
581 591 #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
582 592 #define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */
583 593 #define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */
584 594 #define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */
585 595 #define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */
586 596 #define E1000_TSICR 0x0B66C /* Interrupt Cause Register */
587 597 #define E1000_TSIM 0x0B674 /* Interrupt Mask Register */
588 598 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
589 599 #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
590 600
591 601 /* Filtering Registers */
592 602 #define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
593 603 #define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
594 604 #define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
595 605 #define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
596 606 #define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
597 607 #define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
598 608 #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
599 609
600 610 #define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */
601 611 #define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */
602 612 #define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */
603 613 #define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */
604 614 #define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */
605 615 /* Tx Desc plane TC Rate-scheduler config */
606 616 #define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4))
607 617 /* Tx Packet plane TC Rate-Scheduler Config */
608 618 #define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4))
609 619 /* Rx Packet plane TC Rate-Scheduler Config */
610 620 #define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4))
611 621 /* Tx Desc Plane TC Rate-Scheduler Status */
612 622 #define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4))
613 623 /* Tx Desc Plane TC Rate-Scheduler MMW */
614 624 #define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4))
615 625 /* Tx Packet plane TC Rate-Scheduler Status */
616 626 #define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4))
617 627 /* Tx Packet plane TC Rate-scheduler MMW */
618 628 #define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4))
619 629 /* Rx Packet plane TC Rate-Scheduler Status */
620 630 #define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4))
621 631 /* Rx Packet plane TC Rate-Scheduler MMW */
622 632 #define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4))
623 633 /* Tx Desc plane VM Rate-Scheduler MMW*/
624 634 #define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4))
625 635 /* Tx BCN Rate-Scheduler MMW */
626 636 #define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4))
627 637 #define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */
628 638 #define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */
629 639 #define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */
630 640 #define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */
631 641 #define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */
632 642 #define E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */
633 643 #define E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */
634 644 #define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */
635 645 #define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */
636 646 #define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */
637 647 #define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */
638 648 #define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */
639 649 #define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */
640 650 #define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */
641 651
642 652 /* DMA Coalescing registers */
643 653 #define E1000_DMACR 0x02508 /* Control Register */
644 654 #define E1000_DMCTXTH 0x03550 /* Transmit Threshold */
645 655 #define E1000_DMCTLX 0x02514 /* Time to Lx Request */
646 656 #define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */
647 657 #define E1000_DMCCNT 0x05DD4 /* Current Rx Count */
648 658 #define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */
649 659 #define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */
650 660
651 661 /* PCIe Parity Status Register */
652 662 #define E1000_PCIEERRSTS 0x05BA8
653 663
654 664 #define E1000_PROXYS 0x5F64 /* Proxying Status */
655 665 #define E1000_PROXYFC 0x5F60 /* Proxying Filter Control */
656 666 /* Thermal sensor configuration and status registers */
657 667 #define E1000_THMJT 0x08100 /* Junction Temperature */
658 668 #define E1000_THLOWTC 0x08104 /* Low Threshold Control */
659 669 #define E1000_THMIDTC 0x08108 /* Mid Threshold Control */
660 670 #define E1000_THHIGHTC 0x0810C /* High Threshold Control */
661 671 #define E1000_THSTAT 0x08110 /* Thermal Sensor Status */
662 672
663 673 /* Energy Efficient Ethernet "EEE" registers */
664 674 #define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */
665 675 #define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */
666 676 #define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/
667 677 #define E1000_EEE_SU 0x0E34 /* EEE Setup */
668 678 #define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */
669 679 #define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */
670 680
671 681 /* OS2BMC Registers */
672 682 #define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */
673 683 #define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */
674 684 #define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */
675 685 #define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */
676 686
677 687 #define E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */
678 688
679 689
680 690 #ifdef __cplusplus
681 691 }
682 692 #endif
683 693
684 694 #endif /* _E1000_REGS_H_ */
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