--- old/usr/src/pkg/manifests/driver-network-igb.mf	Wed Feb 26 09:49:36 2014
+++ new/usr/src/pkg/manifests/driver-network-igb.mf	Wed Feb 26 09:49:36 2014
@@ -22,6 +22,7 @@
 #
 # Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
 # Copyright 2012, Nexenta Systems, Inc. All rights reserved.
+# Copyright 2014 Pluribus Networks Inc.
 #
 
 #
@@ -70,6 +71,9 @@
     alias=pciex8086,1538 \
     alias=pciex8086,1539 \
     alias=pciex8086,1546 \
+    alias=pciex8086,1f40 \
+    alias=pciex8086,1f41 \
+    alias=pciex8086,1f45 \
     alias=pciex8086,438
 file path=kernel/drv/$(ARCH64)/igb group=sys
 $(i386_ONLY)file path=kernel/drv/igb group=sys
--- old/usr/src/uts/common/io/e1000api/e1000_82575.c	Wed Feb 26 09:49:36 2014
+++ new/usr/src/uts/common/io/e1000api/e1000_82575.c	Wed Feb 26 09:49:36 2014
@@ -144,6 +144,7 @@
 		break;
 	case e1000_82580:
 	case e1000_i350:
+	case e1000_i354:
 	case e1000_i210:
 	case e1000_i211:
 		reg = E1000_READ_REG(hw, E1000_MDICNFG);
@@ -207,6 +208,7 @@
 		switch (hw->mac.type) {
 		case e1000_82580:
 		case e1000_i350:
+		case e1000_i354:
 			phy->ops.read_reg = e1000_read_phy_reg_82580;
 			phy->ops.write_reg = e1000_write_phy_reg_82580;
 			break;
@@ -226,6 +228,8 @@
 
 	/* Verify phy id and set remaining function pointers */
 	switch (phy->id) {
+	case M88E1543_E_PHY_ID:
+	case M88E1512_E_PHY_ID:
 	case I347AT4_E_PHY_ID:
 	case M88E1112_E_PHY_ID:
 	case M88E1340M_E_PHY_ID:
@@ -233,13 +237,17 @@
 		phy->type		= e1000_phy_m88;
 		phy->ops.check_polarity	= e1000_check_polarity_m88;
 		phy->ops.get_info	= e1000_get_phy_info_m88;
-		if (phy->id == I347AT4_E_PHY_ID ||
-		    phy->id == M88E1112_E_PHY_ID ||
-		    phy->id == M88E1340M_E_PHY_ID)
+		switch (phy->id) {
+		case I347AT4_E_PHY_ID:
+		case M88E1112_E_PHY_ID:
+		case M88E1340M_E_PHY_ID:
+		case M88E1543_E_PHY_ID:
+		case M88E1512_E_PHY_ID:
 			phy->ops.get_cable_length =
 					 e1000_get_cable_length_m88_gen2;
-		else
+		default:
 			phy->ops.get_cable_length = e1000_get_cable_length_m88;
+		}
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 		break;
 	case IGP03E1000_E_PHY_ID:
@@ -355,6 +363,7 @@
 		nvm->ops.update = e1000_update_nvm_checksum_82580;
 		break;
 	case e1000_i350:
+	case e1000_i354:
 		nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 		nvm->ops.update = e1000_update_nvm_checksum_i350;
 		break;
@@ -388,10 +397,10 @@
 		mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 	if (mac->type == e1000_82580)
 		mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
-	if (mac->type == e1000_i350)
+	if (mac->type == e1000_i350 || mac->type == e1000_i354)
 		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 
-	/* Enable EEE default settings for EEE supported devices */
+	/* Disable EEE default settings for EEE supported devices */
 	if (mac->type >= e1000_i350)
 		dev_spec->eee_disable = TRUE;
 
@@ -436,7 +445,7 @@
 	mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 	/* multicast address update */
 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
-	if (mac->type == e1000_i350) {
+	if (mac->type == e1000_i350 || mac->type == e1000_i354) {
 		/* writing VFTA */
 		mac->ops.write_vfta = e1000_write_vfta_i350;
 		/* clearing VFTA */
@@ -622,6 +631,10 @@
 
 	DEBUGFUNC("e1000_get_phy_id_82575");
 
+	/* some i354 devices need an extra read for phy id */
+	if (hw->mac.type == e1000_i354)
+		e1000_get_phy_id(hw);
+
 	/*
 	 * For SGMII PHYs, we try the list of possible addresses until
 	 * we find one that works.  For non-SGMII PHYs
@@ -645,6 +658,7 @@
 			break;
 		case e1000_82580:
 		case e1000_i350:
+		case e1000_i354:
 		case e1000_i210:
 		case e1000_i211:
 			mdic = E1000_READ_REG(hw, E1000_MDICNFG);
@@ -1215,6 +1229,7 @@
 {
 	struct e1000_mac_info *mac = &hw->mac;
 	u32 pcs;
+	u32 status;
 
 	DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
 
@@ -1245,6 +1260,18 @@
 		else
 			*duplex = HALF_DUPLEX;
 
+		/* Check if it is an I354 2.5Gb backplane connection. */
+		if (mac->type == e1000_i354) {
+			status = E1000_READ_REG(hw, E1000_STATUS);
+			if ((status & E1000_STATUS_2P5_SKU) &&
+			    !(status & E1000_STATUS_2P5_SKU_OVER)) {
+				*speed = SPEED_2500;
+				*duplex = FULL_DUPLEX;
+				DEBUGOUT("2500 Mbs, ");
+				DEBUGOUT("Full Duplex\n");
+			}
+		}
+
 	} else {
 		mac->serdes_has_link = FALSE;
 		*speed = 0;
@@ -1430,11 +1457,18 @@
 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 
-	/* Clear Go Link Disconnect bit */
-	if (hw->mac.type >= e1000_82580) {
+	/* Clear Go Link Disconnect bit on supported devices */
+	switch (hw->mac.type) {
+	case e1000_82580:
+	case e1000_i350:
+	case e1000_i210:
+	case e1000_i211:
 		phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 		phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 		E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
+		break;
+	default:
+		break;
 	}
 
 	ret_val = e1000_setup_serdes_link_82575(hw);
@@ -2132,42 +2166,32 @@
  **/
 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
 {
-	u32 dtxswc;
+	u32 reg_val, reg_offset;
 
 	switch (hw->mac.type) {
 	case e1000_82576:
-		dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
-		if (enable) {
-			dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
-				   E1000_DTXSWC_VLAN_SPOOF_MASK);
-			/* The PF can spoof - it has to in order to
-			 * support emulation mode NICs */
-			dtxswc ^= (1 << pf | 1 << (pf +
-				   E1000_DTXSWC_VLAN_SPOOF_SHIFT));
-		} else {
-			dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
-				    E1000_DTXSWC_VLAN_SPOOF_MASK);
-		}
-		E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
+		reg_offset = E1000_DTXSWC;
 		break;
 	case e1000_i350:
-		dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
-		if (enable) {
-			dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
-				   E1000_DTXSWC_VLAN_SPOOF_MASK);
-			/* The PF can spoof - it has to in order to
-			 * support emulation mode NICs
-			 */
-			dtxswc ^= (1 << pf | 1 << (pf +
-				   E1000_DTXSWC_VLAN_SPOOF_SHIFT));
-		} else {
-			dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
-				    E1000_DTXSWC_VLAN_SPOOF_MASK);
-		}
-		E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
-	default:
+	case e1000_i354:
+		reg_offset = E1000_TXSWC;
 		break;
+	default:
+		return;
 	}
+	reg_val = E1000_READ_REG(hw, reg_offset);
+	if (enable) {
+		reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
+			   E1000_DTXSWC_VLAN_SPOOF_MASK);
+		/* The PF can spoof - it has to in order to
+		 * support emulation mode NICs
+		 */
+		reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
+	} else {
+		reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
+			    E1000_DTXSWC_VLAN_SPOOF_MASK);
+	}
+	E1000_WRITE_REG(hw, reg_offset, reg_val);
 }
 
 /**
@@ -2191,6 +2215,7 @@
 		E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
 		break;
 	case e1000_i350:
+	case e1000_i354:
 		dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
 		if (enable)
 			dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
@@ -2688,6 +2713,114 @@
 
 	return ret_val;
 }
+
+/**
+ *  e1000_set_eee_i354 - Enable/disable EEE support
+ *  @hw: pointer to the HW structure
+ *
+ *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
+ *
+ **/
+s32 e1000_set_eee_i354(struct e1000_hw *hw)
+{
+	struct e1000_phy_info *phy = &hw->phy;
+	s32 ret_val = E1000_SUCCESS;
+	u16 phy_data;
+
+	DEBUGFUNC("e1000_set_eee_i354");
+
+	if ((hw->phy.media_type != e1000_media_type_copper) ||
+	    ((phy->id != M88E1543_E_PHY_ID) &&
+	    (phy->id != M88E1512_E_PHY_ID)))
+		goto out;
+
+	if (!hw->dev_spec._82575.eee_disable) {
+		/* Switch to PHY page 18. */
+		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
+		if (ret_val)
+			goto out;
+
+		ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
+					    &phy_data);
+		if (ret_val)
+			goto out;
+
+		phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
+		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
+					     phy_data);
+		if (ret_val)
+			goto out;
+
+		/* Return the PHY to page 0. */
+		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
+		if (ret_val)
+			goto out;
+
+		/* Turn on EEE advertisement. */
+		ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
+					       E1000_EEE_ADV_DEV_I354,
+					       &phy_data);
+		if (ret_val)
+       			goto out;
+
+		phy_data |= E1000_EEE_ADV_100_SUPPORTED |
+			    E1000_EEE_ADV_1000_SUPPORTED;
+		ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
+						E1000_EEE_ADV_DEV_I354,
+						phy_data);
+	} else {
+		/* Turn off EEE advertisement. */
+		ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
+					       E1000_EEE_ADV_DEV_I354,
+					       &phy_data);
+		if (ret_val)
+			goto out;
+
+		phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
+			      E1000_EEE_ADV_1000_SUPPORTED);
+		ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
+						E1000_EEE_ADV_DEV_I354,
+						phy_data);
+	}
+
+out:
+	return ret_val;
+}
+
+/**
+ *  e1000_get_eee_status_i354 - Get EEE status
+ *  @hw: pointer to the HW structure
+ *  @status: EEE status
+ *
+ *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
+ *  been received.
+ **/
+s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
+{
+	struct e1000_phy_info *phy = &hw->phy;
+	s32 ret_val = E1000_SUCCESS;
+	u16 phy_data;
+
+	DEBUGFUNC("e1000_get_eee_status_i354");
+
+	/* Check if EEE is supported on this device. */
+	if ((hw->phy.media_type != e1000_media_type_copper) ||
+	    ((phy->id != M88E1543_E_PHY_ID) &&
+	     (phy->id != M88E1512_E_PHY_ID)))
+		goto out;
+
+	ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
+				       E1000_PCS_STATUS_DEV_I354,
+				       &phy_data);
+	if (ret_val)
+		goto out;
+
+	*status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
+			      E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE;
+
+out:
+	return ret_val;
+}
 
 /* Due to a hw errata, if the host tries to  configure the VFTA register
  * while performing queries from the BMC or DMA, then the VFTA in some
--- old/usr/src/uts/common/io/e1000api/e1000_82575.h	Wed Feb 26 09:49:36 2014
+++ new/usr/src/uts/common/io/e1000api/e1000_82575.h	Wed Feb 26 09:49:36 2014
@@ -496,6 +496,8 @@
 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);
 u16 e1000_rxpbs_adjust_82580(u32 data);
 s32 e1000_set_eee_i350(struct e1000_hw *);
+s32 e1000_set_eee_i354(struct e1000_hw *);
+s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *);
 
 /* I2C SDA and SCL timing parameters for standard mode */
 #define E1000_I2C_T_HD_STA	4
--- old/usr/src/uts/common/io/e1000api/e1000_api.c	Wed Feb 26 09:49:36 2014
+++ new/usr/src/uts/common/io/e1000api/e1000_api.c	Wed Feb 26 09:49:36 2014
@@ -351,6 +351,11 @@
 	case E1000_DEV_ID_I350_VF_HV:
 		mac->type = e1000_vfadapt_i350;
 		break;
+	case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
+	case E1000_DEV_ID_I354_SGMII:
+	case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
+		mac->type = e1000_i354;
+		break;
 
 	default:
 		/* Should never have loaded on this device */
@@ -447,6 +452,7 @@
 	case e1000_82576:
 	case e1000_82580:
 	case e1000_i350:
+	case e1000_i354:
 		e1000_init_function_pointers_82575(hw);
 		break;
 	case e1000_i210:
--- old/usr/src/uts/common/io/e1000api/e1000_defines.h	Wed Feb 26 09:49:37 2014
+++ new/usr/src/uts/common/io/e1000api/e1000_defines.h	Wed Feb 26 09:49:37 2014
@@ -287,7 +287,10 @@
 
 #define E1000_CONNSW_ENRGSRC		0x4
 #define E1000_CONNSW_PHYSD		0x400
+#define	E1000_CONNSW_PHY_PDN		0x800
 #define E1000_CONNSW_SERDESD		0x200
+#define	E1000_CONNSW_AUTOSENSE_CONF	0x2
+#define	E1000_CONNSW_AUTOSENSE_EN	0x1
 #define E1000_PCS_CFG_PCS_EN		8
 #define E1000_PCS_LCTL_FLV_LINK_UP	1
 #define E1000_PCS_LCTL_FSV_10		0
@@ -325,6 +328,8 @@
 #define E1000_STATUS_GIO_MASTER_ENABLE	0x00080000 /* Master request status */
 #define E1000_STATUS_PCI66		0x00000800 /* In 66Mhz slot */
 #define E1000_STATUS_BUS64		0x00001000 /* In 64 bit slot */
+#define	E1000_STATUS_2P5_SKU		0x00001000 /* Val of 2.5GBE SKU strap */
+#define	E1000_STATUS_2P5_SKU_OVER	0x00002000 /* Val of 2.5GBE SKU Over */
 #define E1000_STATUS_PCIX_MODE		0x00002000 /* PCI-X mode */
 #define E1000_STATUS_PCIX_SPEED		0x0000C000 /* PCI-X bus speed */
 
@@ -336,6 +341,7 @@
 #define SPEED_10	10
 #define SPEED_100	100
 #define SPEED_1000	1000
+#define	SPEED_2500	2500
 #define HALF_DUPLEX	1
 #define FULL_DUPLEX	2
 
@@ -650,6 +656,7 @@
 #define E1000_EITR_ITR_INT_MASK	0x0000FFFF
 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
 #define E1000_EITR_CNT_IGNR	0x80000000 /* Don't reset counters on write */
+#define	E1000_EITR_INTERVAL	0x00007FFC
 
 /* Transmit Descriptor Control */
 #define E1000_TXDCTL_PTHRESH	0x0000003F /* TXDCTL Prefetch Threshold */
@@ -821,6 +828,19 @@
 #define E1000_EEER_EEE_NEG		0x20000000 /* EEE capability nego */
 #define E1000_EEER_RX_LPI_STATUS	0x40000000 /* Rx in LPI state */
 #define E1000_EEER_TX_LPI_STATUS	0x80000000 /* Tx in LPI state */
+#define	E1000_EEE_LP_ADV_ADDR_I350	0x040F     /* EEE LP Advertisement */
+#define	E1000_M88E1543_PAGE_ADDR	0x16       /* Page Offset Register */
+#define	E1000_M88E1543_EEE_CTRL_1	0x0
+#define	E1000_M88E1543_EEE_CTRL_1_MS	0x0001     /* EEE Master/Slave */
+#define	E1000_EEE_ADV_DEV_I354		7
+#define	E1000_EEE_ADV_ADDR_I354		60
+#define	E1000_EEE_ADV_100_SUPPORTED	(1 << 1)   /* 100BaseTx EEE Supported */
+#define	E1000_EEE_ADV_1000_SUPPORTED	(1 << 2)   /* 1000BaseT EEE Supported */
+#define	E1000_PCS_STATUS_DEV_I354	3
+#define	E1000_PCS_STATUS_ADDR_I354	1
+#define	E1000_PCS_STATUS_RX_LPI_RCVD	0x0400
+#define	E1000_PCS_STATUS_TX_LPI_RCVD	0x0800
+
 #define E1000_EEE_SU_LPI_CLK_STP	0x00800000 /* EEE LPI Clock Stop */
 /* PCI Express Control */
 #define E1000_GCR_RXD_NO_SNOOP		0x00000001
@@ -834,6 +854,7 @@
 #define E1000_GCR_CMPL_TMOUT_RESEND	0x00010000
 #define E1000_GCR_CAP_VER2		0x00040000
 
+
 #define PCIE_NO_SNOOP_ALL	(E1000_GCR_RXD_NO_SNOOP | \
 				 E1000_GCR_RXDSCW_NO_SNOOP | \
 				 E1000_GCR_RXDSCR_NO_SNOOP | \
@@ -841,6 +862,8 @@
 				 E1000_GCR_TXDSCW_NO_SNOOP | \
 				 E1000_GCR_TXDSCR_NO_SNOOP)
 
+#define	E1000_MMDAC_FUNC_DATA	0x4000 /* Data, no post increment */
+
 /* mPHY address control and data registers */
 #define E1000_MPHY_ADDR_CTL		0x0024 /* Address Control Reg */
 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK	0xFFFF0000
@@ -1174,6 +1197,8 @@
 #define M88E1011_I_PHY_ID	0x01410C20
 #define IGP01E1000_I_PHY_ID	0x02A80380
 #define M88E1111_I_PHY_ID	0x01410CC0
+#define	M88E1543_E_PHY_ID	0x01410EA0
+#define	M88E1512_E_PHY_ID	0x01410DD0
 #define M88E1112_E_PHY_ID	0x01410C90
 #define I347AT4_E_PHY_ID	0x01410DC0
 #define M88E1340M_E_PHY_ID	0x01410DF0
--- old/usr/src/uts/common/io/e1000api/e1000_hw.h	Wed Feb 26 09:49:37 2014
+++ new/usr/src/uts/common/io/e1000api/e1000_hw.h	Wed Feb 26 09:49:37 2014
@@ -170,6 +170,9 @@
 #define E1000_DEV_ID_I210_SERDES		0x1537
 #define E1000_DEV_ID_I210_SGMII			0x1538
 #define E1000_DEV_ID_I211_COPPER		0x1539
+#define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40
+#define E1000_DEV_ID_I354_SGMII			0x1F41
+#define	E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45
 #define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
 #define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
 #define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
@@ -221,6 +224,7 @@
 	e1000_82576,
 	e1000_82580,
 	e1000_i350,
+	e1000_i354,
 	e1000_i210,
 	e1000_i211,
 	e1000_vfadapt,
--- old/usr/src/uts/common/io/e1000api/e1000_i210.c	Wed Feb 26 09:49:37 2014
+++ new/usr/src/uts/common/io/e1000api/e1000_i210.c	Wed Feb 26 09:49:37 2014
@@ -752,3 +752,76 @@
 out:
 	return ret_val;
 }
+
+/**
+ *  __e1000_access_xmdio_reg - Read/write XMDIO register
+ *  @hw: pointer to the HW structure
+ *  @address: XMDIO address to program
+ *  @dev_addr: device address to program
+ *  @data: pointer to value to read/write from/to the XMDIO address
+ *  @read: boolean flag to indicate read or write
+ **/
+static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
+				    u8 dev_addr, u16 *data, bool read)
+{
+	s32 ret_val = E1000_SUCCESS;
+
+	DEBUGFUNC("__e1000_access_xmdio_reg");
+
+	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
+	if (ret_val)
+		return ret_val;
+
+	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
+	if (ret_val)
+		return ret_val;
+
+	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
+							 dev_addr);
+	if (ret_val)
+		return ret_val;
+
+	if (read)
+		ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
+	else
+		ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
+	if (ret_val)
+		return ret_val;
+
+	/* Recalibrate the device back to 0 */
+	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
+	if (ret_val)
+		return ret_val;
+
+	return ret_val;
+}
+
+/**
+ *  e1000_read_xmdio_reg - Read XMDIO register
+ *  @hw: pointer to the HW structure
+ *  @addr: XMDIO address to program
+ *  @dev_addr: device address to program
+ *  @data: value to be read from the EMI address
+ **/
+s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
+{
+	DEBUGFUNC("e1000_read_xmdio_reg");
+
+	return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, TRUE);
+}
+
+/**
+ *  e1000_write_xmdio_reg - Write XMDIO register
+ *  @hw: pointer to the HW structure
+ *  @addr: XMDIO address to program
+ *  @dev_addr: device address to program
+ *  @data: value to be written to the XMDIO address
+ **/
+s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
+{
+	DEBUGFUNC("e1000_read_xmdio_reg");
+
+	return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data, FALSE);
+}
+
+
--- old/usr/src/uts/common/io/e1000api/e1000_i210.h	Wed Feb 26 09:49:37 2014
+++ new/usr/src/uts/common/io/e1000api/e1000_i210.h	Wed Feb 26 09:49:37 2014
@@ -49,6 +49,10 @@
 s32 e1000_read_invm_i211(struct e1000_hw *hw, u8 address, u16 *data);
 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
+s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
+			 u16 *data);
+s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
+			  u16 data);
 
 #define E1000_STM_OPCODE		0xDB00
 #define E1000_EEPROM_FLASH_SIZE_WORD	0x11
--- old/usr/src/uts/common/io/e1000api/e1000_regs.h	Wed Feb 26 09:49:37 2014
+++ new/usr/src/uts/common/io/e1000api/e1000_regs.h	Wed Feb 26 09:49:37 2014
@@ -54,6 +54,10 @@
 #define E1000_BARCTRL			0x5BBC /* BAR ctrl reg */
 #define E1000_BARCTRL_FLSIZE		0x0700 /* BAR ctrl Flsize */
 #define E1000_BARCTRL_CSRSIZE		0x2000 /* BAR ctrl CSR size */
+#define	E1000_MPHY_ADDR_CTRL		0x0024 /* GbE MPHY Address Control */
+#define	E1000_MPHY_DATA			0x0E10 /* GBE MPHY Data */
+#define	E1000_MPHY_STAT			0x0E0C /* GBE MPHY Statistics */
+#define	E1000_PPHY_CTRL			0x5b48 /* PCIe PHY Control */
 #define E1000_I350_BARCTRL		0x5BFC /* BAR ctrl reg */
 #define E1000_I350_DTXMXPKTSZ		0x355C /* Maximum sent packet size reg*/
 #define E1000_SCTL	0x00024  /* SerDes Control - RW */
@@ -98,6 +102,7 @@
 #define E1000_TBT	0x00448  /* Tx Burst Timer - RW */
 #define E1000_AIT	0x00458  /* Adaptive Interframe Spacing Throttle - RW */
 #define E1000_LEDCTL	0x00E00  /* LED Control - RW */
+#define E1000_LEDMUX	0x08130	/* LED MUX Control */
 #define E1000_EXTCNF_CTRL	0x00F00  /* Extended Configuration Control */
 #define E1000_EXTCNF_SIZE	0x00F08  /* Extended Configuration Size */
 #define E1000_PHY_CTRL	0x00F10  /* PHY Control Register in CSR */
@@ -156,6 +161,8 @@
 #define E1000_PBRWAC	0x024E8 /* Rx packet buffer wrap around counter - RO */
 #define E1000_RDTR	0x02820  /* Rx Delay Timer - RW */
 #define E1000_RADV	0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
+#define	E1000_EMIADD	0x10	/* Extended Memory Indirect Address */
+#define	E1000_EMIDATA	0x11	/* Extended Memory Indirect Data */
 #define E1000_SRWR		0x12018  /* Shadow Ram Write Register - RW */
 #define E1000_I210_FLMNGCTL	0x12038
 #define E1000_I210_FLMNGDATA	0x1203C
@@ -212,6 +219,9 @@
 /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
 #define E1000_I210_TXPBS_SIZE(_n, _s)	((_s) << (6 * _n))
 
+#define	E1000_MMDAC			13 /* MMD Access Control */
+#define	E1000_MMDAAD			14 /* MMD Access Address/Data */
+
 /* Convenience macros
  *
  * Note: "_n" is the queue number of the register to be written to.
--- old/usr/src/uts/common/io/igb/igb_gld.c	Wed Feb 26 09:49:37 2014
+++ new/usr/src/uts/common/io/igb/igb_gld.c	Wed Feb 26 09:49:37 2014
@@ -26,6 +26,7 @@
 /*
  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
  * Copyright 2013, Nexenta Systems, Inc. All rights reserved.
+ * Copyright 2014 Pluribus Networks Inc.
  */
 
 #include "igb_sw.h"
@@ -53,51 +54,42 @@
 		break;
 
 	case MAC_STAT_MULTIRCV:
-		igb_ks->mprc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_MPRC);
-		*val = igb_ks->mprc.value.ui64;
+		igb->stat_mprc += E1000_READ_REG(hw, E1000_MPRC);
+		*val = igb->stat_mprc;
 		break;
 
 	case MAC_STAT_BRDCSTRCV:
-		igb_ks->bprc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_BPRC);
-		*val = igb_ks->bprc.value.ui64;
+		igb->stat_bprc += E1000_READ_REG(hw, E1000_BPRC);
+		*val = igb->stat_bprc;
 		break;
 
 	case MAC_STAT_MULTIXMT:
-		igb_ks->mptc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_MPTC);
-		*val = igb_ks->mptc.value.ui64;
+		igb->stat_mptc += E1000_READ_REG(hw, E1000_MPTC);
+		*val = igb->stat_mptc;
 		break;
 
 	case MAC_STAT_BRDCSTXMT:
-		igb_ks->bptc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_BPTC);
-		*val = igb_ks->bptc.value.ui64;
+		igb->stat_bptc += E1000_READ_REG(hw, E1000_BPTC);
+		*val = igb->stat_bptc;
 		break;
 
 	case MAC_STAT_NORCVBUF:
-		igb_ks->rnbc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_RNBC);
-		*val = igb_ks->rnbc.value.ui64;
+		igb->stat_rnbc += E1000_READ_REG(hw, E1000_RNBC);
+		*val = igb->stat_rnbc;
 		break;
 
 	case MAC_STAT_IERRORS:
-		igb_ks->rxerrc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_RXERRC);
-		igb_ks->algnerrc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_ALGNERRC);
+		igb->stat_rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
+		igb->stat_algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 		igb_ks->rlec.value.ui64 +=
 		    E1000_READ_REG(hw, E1000_RLEC);
-		igb_ks->crcerrs.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_CRCERRS);
-		igb_ks->cexterr.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_CEXTERR);
-		*val = igb_ks->rxerrc.value.ui64 +
-		    igb_ks->algnerrc.value.ui64 +
+		igb->stat_crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
+		igb->stat_cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
+		*val = igb->stat_rxerrc +
+		    igb->stat_algnerrc +
 		    igb_ks->rlec.value.ui64 +
-		    igb_ks->crcerrs.value.ui64 +
-		    igb_ks->cexterr.value.ui64;
+		    igb->stat_crcerrs +
+		    igb->stat_cexterr;
 		break;
 
 	case MAC_STAT_NOXMTBUF:
@@ -105,15 +97,13 @@
 		break;
 
 	case MAC_STAT_OERRORS:
-		igb_ks->ecol.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_ECOL);
-		*val = igb_ks->ecol.value.ui64;
+		igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
+		*val = igb->stat_ecol;
 		break;
 
 	case MAC_STAT_COLLISIONS:
-		igb_ks->colc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_COLC);
-		*val = igb_ks->colc.value.ui64;
+		igb->stat_colc += E1000_READ_REG(hw, E1000_COLC);
+		*val = igb->stat_colc;
 		break;
 
 	case MAC_STAT_RBYTES:
@@ -124,15 +114,13 @@
 		 */
 		low_val = E1000_READ_REG(hw, E1000_TORL);
 		high_val = E1000_READ_REG(hw, E1000_TORH);
-		igb_ks->tor.value.ui64 +=
-		    (uint64_t)high_val << 32 | (uint64_t)low_val;
-		*val = igb_ks->tor.value.ui64;
+		igb->stat_tor += (uint64_t)high_val << 32 | (uint64_t)low_val;
+		*val = igb->stat_tor;
 		break;
 
 	case MAC_STAT_IPACKETS:
-		igb_ks->tpr.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_TPR);
-		*val = igb_ks->tpr.value.ui64;
+		igb->stat_tpr += E1000_READ_REG(hw, E1000_TPR);
+		*val = igb->stat_tpr;
 		break;
 
 	case MAC_STAT_OBYTES:
@@ -143,88 +131,74 @@
 		 */
 		low_val = E1000_READ_REG(hw, E1000_TOTL);
 		high_val = E1000_READ_REG(hw, E1000_TOTH);
-		igb_ks->tot.value.ui64 +=
-		    (uint64_t)high_val << 32 | (uint64_t)low_val;
-		*val = igb_ks->tot.value.ui64;
+		igb->stat_tot += (uint64_t)high_val << 32 | (uint64_t)low_val;
+		*val = igb->stat_tot;
 		break;
 
 	case MAC_STAT_OPACKETS:
-		igb_ks->tpt.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_TPT);
-		*val = igb_ks->tpt.value.ui64;
+		igb->stat_tpt += E1000_READ_REG(hw, E1000_TPT);
+		*val = igb->stat_tpt;
 		break;
 
 	/* RFC 1643 stats */
 	case ETHER_STAT_ALIGN_ERRORS:
-		igb_ks->algnerrc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_ALGNERRC);
-		*val = igb_ks->algnerrc.value.ui64;
+		igb->stat_algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
+		*val = igb->stat_algnerrc;
 		break;
 
 	case ETHER_STAT_FCS_ERRORS:
-		igb_ks->crcerrs.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_CRCERRS);
-		*val = igb_ks->crcerrs.value.ui64;
+		igb->stat_crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
+		*val = igb->stat_crcerrs;
 		break;
 
 	case ETHER_STAT_FIRST_COLLISIONS:
-		igb_ks->scc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_SCC);
-		*val = igb_ks->scc.value.ui64;
+		igb->stat_scc += E1000_READ_REG(hw, E1000_SCC);
+		*val = igb->stat_scc;
 		break;
 
 	case ETHER_STAT_MULTI_COLLISIONS:
-		igb_ks->mcc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_MCC);
-		*val = igb_ks->mcc.value.ui64;
+		igb->stat_mcc += E1000_READ_REG(hw, E1000_MCC);
+		*val = igb->stat_mcc;
 		break;
 
 	case ETHER_STAT_SQE_ERRORS:
-		igb_ks->sec.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_SEC);
-		*val = igb_ks->sec.value.ui64;
+		igb->stat_sec += E1000_READ_REG(hw, E1000_SEC);
+		*val = igb->stat_sec;
 		break;
 
 	case ETHER_STAT_DEFER_XMTS:
-		igb_ks->dc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_DC);
-		*val = igb_ks->dc.value.ui64;
+		igb->stat_dc += E1000_READ_REG(hw, E1000_DC);
+		*val = igb->stat_dc;
 		break;
 
 	case ETHER_STAT_TX_LATE_COLLISIONS:
-		igb_ks->latecol.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_LATECOL);
-		*val = igb_ks->latecol.value.ui64;
+		igb->stat_latecol += E1000_READ_REG(hw, E1000_LATECOL);
+		*val = igb->stat_latecol;
 		break;
 
 	case ETHER_STAT_EX_COLLISIONS:
-		igb_ks->ecol.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_ECOL);
-		*val = igb_ks->ecol.value.ui64;
+		igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
+		*val = igb->stat_ecol;
 		break;
 
 	case ETHER_STAT_MACXMT_ERRORS:
-		igb_ks->ecol.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_ECOL);
-		*val = igb_ks->ecol.value.ui64;
+		igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
+		*val = igb->stat_ecol;
 		break;
 
 	case ETHER_STAT_CARRIER_ERRORS:
-		igb_ks->cexterr.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_CEXTERR);
-		*val = igb_ks->cexterr.value.ui64;
+		igb->stat_cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
+		*val = igb->stat_cexterr;
 		break;
 
 	case ETHER_STAT_TOOLONG_ERRORS:
-		igb_ks->roc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_ROC);
-		*val = igb_ks->roc.value.ui64;
+		igb->stat_roc += E1000_READ_REG(hw, E1000_ROC);
+		*val = igb->stat_roc;
 		break;
 
 	case ETHER_STAT_MACRCV_ERRORS:
-		igb_ks->rxerrc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_RXERRC);
-		*val = igb_ks->rxerrc.value.ui64;
+		igb->stat_rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
+		*val = igb->stat_rxerrc;
 		break;
 
 	/* MII/GMII stats */
@@ -385,9 +359,8 @@
 		break;
 
 	case ETHER_STAT_TOOSHORT_ERRORS:
-		igb_ks->ruc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_RUC);
-		*val = igb_ks->ruc.value.ui64;
+		igb->stat_ruc += E1000_READ_REG(hw, E1000_RUC);
+		*val = igb->stat_ruc;
 		break;
 
 	case ETHER_STAT_CAP_REMFAULT:
@@ -403,9 +376,8 @@
 		break;
 
 	case ETHER_STAT_JABBER_ERRORS:
-		igb_ks->rjc.value.ui64 +=
-		    E1000_READ_REG(hw, E1000_RJC);
-		*val = igb_ks->rjc.value.ui64;
+		igb->stat_rjc += E1000_READ_REG(hw, E1000_RJC);
+		*val = igb->stat_rjc;
 		break;
 
 	case ETHER_STAT_CAP_100T4:
@@ -1393,18 +1365,27 @@
 		switch (result) {
 		case 0:
 		case 1:
-			if (hw->mac.type != e1000_i350) {
-				/*
-				 * For now, only supported on I350.
-				 * Add new mac.type values (or use < instead)
-				 * as new cards offer up EEE.
-				 */
+			/*
+			 * For now, only supported on I350/I354.
+			 * Add new mac.type values (or use < instead)
+			 * as new cards offer up EEE.
+			 */
+			switch (hw->mac.type) {
+			case e1000_i350:
+				/* Must set this prior to the set call. */
+				hw->dev_spec._82575.eee_disable = !result;
+				if (e1000_set_eee_i350(hw) != E1000_SUCCESS)
+					err = EIO;
+				break;
+			case e1000_i354:
+				/* Must set this prior to the set call. */
+				hw->dev_spec._82575.eee_disable = !result;
+				if (e1000_set_eee_i354(hw) != E1000_SUCCESS)
+					err = EIO;
+				break;
+			default:
 				return (ENXIO);
 			}
-			/* Must set this prior to the set call. */
-			hw->dev_spec._82575.eee_disable = !result;
-			if (e1000_set_eee_i350(hw) != E1000_SUCCESS)
-				err = EIO;
 			break;
 		default:
 			err = EINVAL;
@@ -1539,8 +1520,14 @@
 		 * For now, only supported on I350.  Add new mac.type values
 		 * (or use < instead) as new cards offer up EEE.
 		 */
-		value = (igb->hw.mac.type != e1000_i350) ? 0 :
-		    !(igb->hw.dev_spec._82575.eee_disable);
+		switch (igb->hw.mac.type) {
+		case e1000_i350:
+		case e1000_i354:
+			value = !(igb->hw.dev_spec._82575.eee_disable);
+			break;
+		default:
+			value = 0;
+		}
 	} else if (strcmp(pr_name, "_tx_copy_thresh") == 0) {
 		value = igb->tx_copy_thresh;
 	} else if (strcmp(pr_name, "_tx_recycle_thresh") == 0) {
--- old/usr/src/uts/common/io/igb/igb_main.c	Wed Feb 26 09:49:37 2014
+++ new/usr/src/uts/common/io/igb/igb_main.c	Wed Feb 26 09:49:37 2014
@@ -335,6 +335,30 @@
 	0xfff00000		/* mask for RXDCTL register */
 };
 
+static adapter_info_t igb_i354_cap = {
+	/* limits */
+	8,		/* maximum number of rx queues */
+	1,		/* minimum number of rx queues */
+	4,		/* default number of rx queues */
+	8,		/* maximum number of tx queues */
+	1,		/* minimum number of tx queues */
+	4,		/* default number of tx queues */
+	65535,		/* maximum interrupt throttle rate */
+	0,		/* minimum interrupt throttle rate */
+	200,		/* default interrupt throttle rate */
+
+	/* function pointers */
+	igb_enable_adapter_interrupts_82580,
+	igb_setup_msix_82580,
+
+	/* capabilities */
+	(IGB_FLAG_HAS_DCA |	/* capability flags */
+	IGB_FLAG_VMDQ_POOL |
+	IGB_FLAG_NEED_CTX_IDX),
+
+	0xfff00000		/* mask for RXDCTL register */
+};
+
 /*
  * Module Initialization Functions
  */
@@ -573,6 +597,8 @@
 	 */
 	if (igb->hw.mac.type == e1000_i350)
 		(void) e1000_set_eee_i350(&igb->hw);
+	else if (igb->hw.mac.type == e1000_i354)
+		(void) e1000_set_eee_i354(&igb->hw);
 
 	return (DDI_SUCCESS);
 
@@ -900,6 +926,9 @@
 	case e1000_i211:
 		igb->capab = &igb_i210_cap;
 		break;
+	case e1000_i354:
+		igb->capab = &igb_i354_cap;
+		break;
 	default:
 		return (IGB_FAILURE);
 	}
@@ -1318,6 +1347,7 @@
 		break;
 	case e1000_82580:
 	case e1000_i350:
+	case e1000_i354:
 		pba = E1000_READ_REG(hw, E1000_RXPBS);
 		pba = e1000_rxpbs_adjust_82580(pba);
 		break;
@@ -1835,6 +1865,8 @@
 
 	if (igb->hw.mac.type == e1000_i350)
 		(void) e1000_set_eee_i350(&igb->hw);
+	else if (igb->hw.mac.type == e1000_i354)
+		(void) e1000_set_eee_i354(&igb->hw);
 
 	for (i = igb->num_tx_rings - 1; i >= 0; i--)
 		mutex_exit(&igb->tx_rings[i].tx_lock);
--- old/usr/src/uts/common/io/igb/igb_stat.c	Wed Feb 26 09:49:38 2014
+++ new/usr/src/uts/common/io/igb/igb_stat.c	Wed Feb 26 09:49:38 2014
@@ -24,6 +24,9 @@
  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
+/*
+ * Copyright 2014 Pluribus Networks Inc.
+ */
 
 #include "igb_sw.h"
 
@@ -53,7 +56,6 @@
 	/*
 	 * Basic information.
 	 */
-	igb_ks->link_speed.value.ui64 = igb->link_speed;
 	igb_ks->reset_count.value.ui64 = igb->reset_count;
 	igb_ks->dout_sync.value.ui64 = igb->dout_sync;
 
@@ -119,7 +121,6 @@
 	val_high = E1000_READ_REG(hw, E1000_GOTCH);
 	igb_ks->got.value.ui64 += (uint64_t)val_high << 32 | (uint64_t)val_low;
 #endif
-
 	igb_ks->symerrs.value.ui64 += E1000_READ_REG(hw, E1000_SYMERRS);
 	igb_ks->mpc.value.ui64 += E1000_READ_REG(hw, E1000_MPC);
 	igb_ks->rlec.value.ui64 += E1000_READ_REG(hw, E1000_RLEC);
@@ -172,8 +173,6 @@
 	/*
 	 * Initialize all the statistics.
 	 */
-	kstat_named_init(&igb_ks->link_speed, "link_speed",
-	    KSTAT_DATA_UINT64);
 	kstat_named_init(&igb_ks->reset_count, "reset_count",
 	    KSTAT_DATA_UINT64);
 	kstat_named_init(&igb_ks->dout_sync, "DMA_out_sync",
--- old/usr/src/uts/common/io/igb/igb_sw.h	Wed Feb 26 09:49:38 2014
+++ new/usr/src/uts/common/io/igb/igb_sw.h	Wed Feb 26 09:49:38 2014
@@ -25,6 +25,7 @@
 
 /*
  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2014 Pluribus Networks Inc. 
  */
 
 #ifndef	_IGB_SW_H
@@ -648,6 +649,34 @@
 	 */
 	kstat_t			*igb_ks;
 
+	/*
+	 * Backing store for MAC stats.  These are reported via GLDv3, instead of
+	 * via our private kstat structure.
+	 */
+	uint64_t		stat_tor;	/* rbytes */
+	uint64_t		stat_tpr;	/* rpackets */
+	uint64_t		stat_tot;	/* obytes */
+	uint64_t		stat_tpt;	/* opackets */
+	uint64_t		stat_colc;	/* collisions */
+	uint64_t		stat_mcc;	/* multi colls */
+	uint64_t		stat_scc;	/* single colls */
+	uint64_t		stat_ecol;	/* excessive colls */
+	uint64_t		stat_latecol;	/* late colls */
+	uint64_t		stat_bptc;	/* xmit bcast */
+	uint64_t		stat_mptc;	/* xmit bcast */
+	uint64_t		stat_bprc;	/* recv bcast */
+	uint64_t		stat_mprc;	/* recv mcast */
+	uint64_t		stat_rnbc;	/* recv nobuf */
+	uint64_t		stat_roc;	/* recv toolong */
+	uint64_t		stat_sec;	/* sqe errors */
+	uint64_t		stat_dc;	/* defer */
+	uint64_t		stat_algnerrc;	/* align errors */
+	uint64_t		stat_crcerrs;	/* crc errors */
+	uint64_t		stat_cexterr;	/* carrier extension errors */
+	uint64_t		stat_ruc;	/* recv tooshort */
+	uint64_t		stat_rjc;	/* recv jabber */
+	uint64_t		stat_rxerrc;	/* recv errors */
+
 	uint32_t		param_en_1000fdx_cap:1,
 				param_en_1000hdx_cap:1,
 				param_en_100t4_cap:1,
@@ -701,7 +730,6 @@
 
 typedef struct igb_stat {
 
-	kstat_named_t link_speed;	/* Link Speed */
 	kstat_named_t reset_count;	/* Reset Count */
 	kstat_named_t dout_sync;	/* DMA out of sync */
 #ifdef IGB_DEBUG
@@ -732,16 +760,8 @@
 	kstat_named_t ptc1023;	/* Packets Xmitted (512-1023b) */
 	kstat_named_t ptc1522;	/* Packets Xmitted (1024-1522b */
 #endif
-	kstat_named_t crcerrs;	/* CRC Error Count */
 	kstat_named_t symerrs;	/* Symbol Error Count */
 	kstat_named_t mpc;	/* Missed Packet Count */
-	kstat_named_t scc;	/* Single Collision Count */
-	kstat_named_t ecol;	/* Excessive Collision Count */
-	kstat_named_t mcc;	/* Multiple Collision Count */
-	kstat_named_t latecol;	/* Late Collision Count */
-	kstat_named_t colc;	/* Collision Count */
-	kstat_named_t dc;	/* Defer Count */
-	kstat_named_t sec;	/* Sequence Error Count */
 	kstat_named_t rlec;	/* Receive Length Error Count */
 	kstat_named_t xonrxc;	/* XON Received Count */
 	kstat_named_t xontxc;	/* XON Xmitted Count */
@@ -748,23 +768,8 @@
 	kstat_named_t xoffrxc;	/* XOFF Received Count */
 	kstat_named_t xofftxc;	/* Xoff Xmitted Count */
 	kstat_named_t fcruc;	/* Unknown Flow Conrol Packet Rcvd Count */
-	kstat_named_t bprc;	/* Broadcasts Pkts Received Count */
-	kstat_named_t mprc;	/* Multicast Pkts Received Count */
-	kstat_named_t rnbc;	/* Receive No Buffers Count */
-	kstat_named_t ruc;	/* Receive Undersize Count */
 	kstat_named_t rfc;	/* Receive Frag Count */
-	kstat_named_t roc;	/* Receive Oversize Count */
-	kstat_named_t rjc;	/* Receive Jabber Count */
-	kstat_named_t tor;	/* Total Octets Recvd Count */
-	kstat_named_t tot;	/* Total Octets Xmted Count */
-	kstat_named_t tpr;	/* Total Packets Received */
-	kstat_named_t tpt;	/* Total Packets Xmitted */
-	kstat_named_t mptc;	/* Multicast Packets Xmited Count */
-	kstat_named_t bptc;	/* Broadcast Packets Xmited Count */
-	kstat_named_t algnerrc;	/* Alignment Error count */
-	kstat_named_t rxerrc;	/* Rx Error Count */
 	kstat_named_t tncrs;	/* Transmit with no CRS */
-	kstat_named_t cexterr;	/* Carrier Extension Error count */
 	kstat_named_t tsctc;	/* TCP seg contexts xmit count */
 	kstat_named_t tsctfc;	/* TCP seg contexts xmit fail count */
 } igb_stat_t;
