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          --- old/usr/src/lib/libm/common/m9x/__fex_sse.c
          +++ new/usr/src/lib/libm/common/m9x/__fex_sse.c
↓ open down ↓ 362 lines elided ↑ open up ↑
 363  363  
 364  364          case cvtss2si:
 365  365          case cvtsd2si:
 366  366          case cvttss2si:
 367  367          case cvttsd2si:
 368  368          case cvtss2siq:
 369  369          case cvtsd2siq:
 370  370          case cvttss2siq:
 371  371          case cvttsd2siq:
 372  372                  return fex_inv_int;
      373 +        default:
      374 +                break;
 373  375          }
 374  376  
 375  377          /* check op1 for signaling nan */
 376  378          t1 = ((int)inst->op & DOUBLE)? my_fp_class(&inst->op1->d[0]) :
 377  379              my_fp_classf(&inst->op1->f[0]);
 378  380          if (t1 == fp_signaling)
 379  381                  return fex_inv_snan;
 380  382  
 381  383          /* check two-operand instructions for other cases */
 382  384          switch (inst->op) {
↓ open down ↓ 21 lines elided ↑ open up ↑
 404  406                      (t2 == fp_zero && t1 == fp_infinity))
 405  407                          return fex_inv_zmi;
 406  408                  break;
 407  409  
 408  410          case divss:
 409  411          case divsd:
 410  412                  if (t1 == fp_zero && t2 == fp_zero)
 411  413                          return fex_inv_zdz;
 412  414                  if (t1 == fp_infinity && t2 == fp_infinity)
 413  415                          return fex_inv_idi;
      416 +        default:
      417 +                break;
 414  418          }
 415  419  
 416  420          return (enum fex_exception)-1;
 417  421  }
 418  422  
 419  423  /* inline templates */
 420  424  extern void sse_cmpeqss(float *, float *, int *);
 421  425  extern void sse_cmpltss(float *, float *, int *);
 422  426  extern void sse_cmpless(float *, float *, int *);
 423  427  extern void sse_cmpunordss(float *, float *, int *);
↓ open down ↓ 207 lines elided ↑ open up ↑
 631  635                          info->op = fex_cmp;
 632  636                          info->res.type = fex_nodata;
 633  637                          sse_ucomisd(&info->op1.val.d, &info->op2.val.d);
 634  638                          break;
 635  639  
 636  640                  case comisd:
 637  641                          info->op = fex_cmp;
 638  642                          info->res.type = fex_nodata;
 639  643                          sse_comisd(&info->op1.val.d, &info->op2.val.d);
 640  644                          break;
      645 +                default:
      646 +                        break;
 641  647                  }
 642  648          } else {
 643  649                  if (inst->op == cvtsi2ss) {
 644  650                          info->op1.type = fex_int;
 645  651                          info->op1.val.i = inst->op2->i[0];
 646  652                          info->op2.type = fex_nodata;
 647  653                  } else if (inst->op == cvtsi2ssq) {
 648  654                          info->op1.type = fex_llong;
 649  655                          info->op1.val.l = inst->op2->l[0];
 650  656                          info->op2.type = fex_nodata;
↓ open down ↓ 133 lines elided ↑ open up ↑
 784  790                          info->op = fex_cmp;
 785  791                          info->res.type = fex_nodata;
 786  792                          sse_ucomiss(&info->op1.val.f, &info->op2.val.f);
 787  793                          break;
 788  794  
 789  795                  case comiss:
 790  796                          info->op = fex_cmp;
 791  797                          info->res.type = fex_nodata;
 792  798                          sse_comiss(&info->op1.val.f, &info->op2.val.f);
 793  799                          break;
      800 +                default:
      801 +                        break;
 794  802                  }
 795  803          }
 796  804          __fenv_getmxcsr(&mxcsr);
 797  805          info->flags = mxcsr & 0x3d;
 798  806          __fenv_setmxcsr(&oldmxcsr);
 799  807  
 800  808          /* determine which exception would have been trapped */
 801  809          te = ~(uap->uc_mcontext.fpregs.fp_reg_set.fpchip_state.mxcsr
 802  810              >> 7) & 0x3d;
 803  811          e = mxcsr & te;
↓ open down ↓ 272 lines elided ↑ open up ↑
1076 1084                  }
1077 1085                  break;
1078 1086  
1079 1087          case cvtpd2ps:
1080 1088                  dummy.op = cvtsd2ss;
1081 1089                  for (i = 0; i < 2; i++) {
1082 1090                          dummy.op1 = (sseoperand_t *)&inst->op1->f[i];
1083 1091                          dummy.op2 = (sseoperand_t *)&inst->op2->d[i];
1084 1092                          e[i] = __fex_get_sse_op(uap, &dummy, &info[i]);
1085 1093                  }
     1094 +        default:
     1095 +                break;
1086 1096          }
1087 1097  }
1088 1098  
1089 1099  /*
1090 1100   * Store the result value from *info in the destination of the scalar
1091 1101   * SSE instruction specified by *inst.  If no result is given but the
1092 1102   * exception is underflow or overflow, supply the default trapped result.
1093 1103   *
1094 1104   * This routine does not work if the instruction specified by *inst
1095 1105   * is not a scalar instruction.
1096 1106   */
1097 1107  void
1098 1108  __fex_st_sse_result(ucontext_t *uap, sseinst_t *inst, enum fex_exception e,
1099 1109      fex_info_t *info)
1100 1110  {
1101      -        int             i;
1102      -        long long       l;
1103      -        float           f, fscl;
1104      -        double          d, dscl;
     1111 +        int             i = 0;
     1112 +        long long       l = 0L;;
     1113 +        float           f = 0.0, fscl;
     1114 +        double          d = 0.0L, dscl;
1105 1115  
1106 1116          /* for compares that write eflags, just set the flags
1107 1117             to indicate "unordered" */
1108 1118          if (inst->op == ucomiss || inst->op == comiss ||
1109 1119              inst->op == ucomisd || inst->op == comisd) {
1110 1120                  uap->uc_mcontext.gregs[REG_PS] |= 0x45;
1111 1121                  return;
1112 1122          }
1113 1123  
1114 1124          /* if info doesn't specify a result value, try to generate
↓ open down ↓ 106 lines elided ↑ open up ↑
1221 1231                          i = info->res.val.f;
1222 1232                          break;
1223 1233  
1224 1234                  case fex_double:
1225 1235                          i = info->res.val.d;
1226 1236                          break;
1227 1237  
1228 1238                  case fex_ldouble:
1229 1239                          i = info->res.val.q;
1230 1240                          break;
     1241 +
     1242 +                default:
     1243 +                        break;
1231 1244                  }
1232 1245                  inst->op1->i[0] = i;
1233 1246          } else if (inst->op == cmpsd || inst->op == cvttss2siq ||
1234 1247              inst->op == cvtss2siq || inst->op == cvttsd2siq ||
1235 1248              inst->op == cvtsd2siq) {
1236 1249                  switch (info->res.type) {
1237 1250                  case fex_int:
1238 1251                          l = info->res.val.i;
1239 1252                          break;
1240 1253  
↓ open down ↓ 5 lines elided ↑ open up ↑
1246 1259                          l = info->res.val.f;
1247 1260                          break;
1248 1261  
1249 1262                  case fex_double:
1250 1263                          l = info->res.val.d;
1251 1264                          break;
1252 1265  
1253 1266                  case fex_ldouble:
1254 1267                          l = info->res.val.q;
1255 1268                          break;
     1269 +
     1270 +                default:
     1271 +                        break;
1256 1272                  }
1257 1273                  inst->op1->l[0] = l;
1258 1274          } else if ((((int)inst->op & DOUBLE) && inst->op != cvtsd2ss) ||
1259 1275              inst->op == cvtss2sd) {
1260 1276                  switch (info->res.type) {
1261 1277                  case fex_int:
1262 1278                          d = info->res.val.i;
1263 1279                          break;
1264 1280  
1265 1281                  case fex_llong:
↓ open down ↓ 4 lines elided ↑ open up ↑
1270 1286                          d = info->res.val.f;
1271 1287                          break;
1272 1288  
1273 1289                  case fex_double:
1274 1290                          d = info->res.val.d;
1275 1291                          break;
1276 1292  
1277 1293                  case fex_ldouble:
1278 1294                          d = info->res.val.q;
1279 1295                          break;
     1296 +
     1297 +                default:
     1298 +                        break;
1280 1299                  }
1281 1300                  inst->op1->d[0] = d;
1282 1301          } else {
1283 1302                  switch (info->res.type) {
1284 1303                  case fex_int:
1285 1304                          f = info->res.val.i;
1286 1305                          break;
1287 1306  
1288 1307                  case fex_llong:
1289 1308                          f = info->res.val.l;
↓ open down ↓ 3 lines elided ↑ open up ↑
1293 1312                          f = info->res.val.f;
1294 1313                          break;
1295 1314  
1296 1315                  case fex_double:
1297 1316                          f = info->res.val.d;
1298 1317                          break;
1299 1318  
1300 1319                  case fex_ldouble:
1301 1320                          f = info->res.val.q;
1302 1321                          break;
     1322 +
     1323 +                default:
     1324 +                        break;
1303 1325                  }
1304 1326                  inst->op1->f[0] = f;
1305 1327          }
1306 1328  }
1307 1329  
1308 1330  /*
1309 1331   * Store the results from a SIMD instruction.  For each i, store
1310 1332   * the result value from info[i] in the i-th part of the destination
1311 1333   * of the SIMD SSE instruction specified by *inst.  If no result
1312 1334   * is given but the exception indicated by e[i] is underflow or
↓ open down ↓ 258 lines elided ↑ open up ↑
1571 1593  
1572 1594          case cvtpd2ps:
1573 1595                  dummy.op = cvtsd2ss;
1574 1596                  for (i = 0; i < 2; i++) {
1575 1597                          dummy.op1 = (sseoperand_t *)&inst->op1->f[i];
1576 1598                          dummy.op2 = (sseoperand_t *)&inst->op2->d[i];
1577 1599                          __fex_st_sse_result(uap, &dummy, e[i], &info[i]);
1578 1600                  }
1579 1601                  /* zero the high 64 bits of the destination */
1580 1602                  inst->op1->l[1] = 0ll;
     1603 +
     1604 +        default:
     1605 +                break;
1581 1606          }
1582 1607  }
     1608 +
    
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