Print this page
6064 ixgbe needs X550 support
   1 /******************************************************************************
   2 
   3   Copyright (c) 2001-2012, Intel Corporation 
   4   All rights reserved.
   5   
   6   Redistribution and use in source and binary forms, with or without 
   7   modification, are permitted provided that the following conditions are met:
   8   
   9    1. Redistributions of source code must retain the above copyright notice, 
  10       this list of conditions and the following disclaimer.
  11   
  12    2. Redistributions in binary form must reproduce the above copyright 
  13       notice, this list of conditions and the following disclaimer in the 
  14       documentation and/or other materials provided with the distribution.
  15   
  16    3. Neither the name of the Intel Corporation nor the names of its 
  17       contributors may be used to endorse or promote products derived from 
  18       this software without specific prior written permission.
  19   
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31 
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34 
  35 #ifndef _IXGBE_PHY_H_
  36 #define _IXGBE_PHY_H_
  37 
  38 #include "ixgbe_type.h"
  39 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0


  40 
  41 /* EEPROM byte offsets */
  42 #define IXGBE_SFF_IDENTIFIER            0x0
  43 #define IXGBE_SFF_IDENTIFIER_SFP        0x3
  44 #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
  45 #define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
  46 #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
  47 #define IXGBE_SFF_1GBE_COMP_CODES       0x6
  48 #define IXGBE_SFF_10GBE_COMP_CODES      0x3
  49 #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
  50 #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C













  51 
  52 /* Bitmasks */
  53 #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
  54 #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
  55 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING       0x4
  56 #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
  57 #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
  58 #define IXGBE_SFF_1GBASET_CAPABLE       0x8
  59 #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
  60 #define IXGBE_SFF_10GBASELR_CAPABLE     0x20








  61 #define IXGBE_I2C_EEPROM_READ_MASK      0x100
  62 #define IXGBE_I2C_EEPROM_STATUS_MASK    0x3
  63 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
  64 #define IXGBE_I2C_EEPROM_STATUS_PASS    0x1
  65 #define IXGBE_I2C_EEPROM_STATUS_FAIL    0x2
  66 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS     0x3
  67 



























  68 /* Flow control defines */
  69 #define IXGBE_TAF_SYM_PAUSE             0x400
  70 #define IXGBE_TAF_ASM_PAUSE             0x800
  71 
  72 /* Bit-shift macros */
  73 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT        24
  74 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT        16
  75 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT        8
  76 
  77 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
  78 #define IXGBE_SFF_VENDOR_OUI_TYCO       0x00407600
  79 #define IXGBE_SFF_VENDOR_OUI_FTL        0x00906500
  80 #define IXGBE_SFF_VENDOR_OUI_AVAGO      0x00176A00
  81 #define IXGBE_SFF_VENDOR_OUI_INTEL      0x001B2100
  82 
  83 /* I2C SDA and SCL timing parameters for standard mode */
  84 #define IXGBE_I2C_T_HD_STA      4
  85 #define IXGBE_I2C_T_LOW         5
  86 #define IXGBE_I2C_T_HIGH        4
  87 #define IXGBE_I2C_T_SU_STA      5
  88 #define IXGBE_I2C_T_HD_DATA     5
  89 #define IXGBE_I2C_T_SU_DATA     1
  90 #define IXGBE_I2C_T_RISE        1
  91 #define IXGBE_I2C_T_FALL        1
  92 #define IXGBE_I2C_T_SU_STO      4
  93 #define IXGBE_I2C_T_BUF         5
  94 




  95 #define IXGBE_TN_LASI_STATUS_REG        0x9005
  96 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
  97 



  98 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
  99 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
 100 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
 101 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
 102 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 103 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);




 104 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 105                                u32 device_type, u16 *phy_data);
 106 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 107                                 u32 device_type, u16 phy_data);
 108 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 109 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 110                                        ixgbe_link_speed speed,
 111                                        bool autoneg,
 112                                        bool autoneg_wait_to_complete);
 113 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 114                                                ixgbe_link_speed *speed,
 115                                                bool *autoneg);

 116 
 117 /* PHY specific */
 118 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
 119                              ixgbe_link_speed *speed,
 120                              bool *link_up);
 121 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 122 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 123                                        u16 *firmware_version);
 124 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 125                                            u16 *firmware_version);
 126 
 127 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);

 128 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
 129 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);


 130 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 131                                         u16 *list_offset,
 132                                         u16 *data_offset);
 133 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 134 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 135                                 u8 dev_addr, u8 *data);


 136 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 137                                  u8 dev_addr, u8 data);


 138 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 139                                   u8 *eeprom_data);
 140 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 141                                    u8 eeprom_data);
 142 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
 143 #endif /* _IXGBE_PHY_H_ */
   1 /******************************************************************************
   2 
   3   Copyright (c) 2001-2015, Intel Corporation 
   4   All rights reserved.
   5   
   6   Redistribution and use in source and binary forms, with or without 
   7   modification, are permitted provided that the following conditions are met:
   8   
   9    1. Redistributions of source code must retain the above copyright notice, 
  10       this list of conditions and the following disclaimer.
  11   
  12    2. Redistributions in binary form must reproduce the above copyright 
  13       notice, this list of conditions and the following disclaimer in the 
  14       documentation and/or other materials provided with the distribution.
  15   
  16    3. Neither the name of the Intel Corporation nor the names of its 
  17       contributors may be used to endorse or promote products derived from 
  18       this software without specific prior written permission.
  19   
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31 
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34 
  35 #ifndef _IXGBE_PHY_H_
  36 #define _IXGBE_PHY_H_
  37 
  38 #include "ixgbe_type.h"
  39 #define IXGBE_I2C_EEPROM_DEV_ADDR       0xA0
  40 #define IXGBE_I2C_EEPROM_DEV_ADDR2      0xA2
  41 #define IXGBE_I2C_EEPROM_BANK_LEN       0xFF
  42 
  43 /* EEPROM byte offsets */
  44 #define IXGBE_SFF_IDENTIFIER            0x0
  45 #define IXGBE_SFF_IDENTIFIER_SFP        0x3
  46 #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
  47 #define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
  48 #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
  49 #define IXGBE_SFF_1GBE_COMP_CODES       0x6
  50 #define IXGBE_SFF_10GBE_COMP_CODES      0x3
  51 #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
  52 #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
  53 #define IXGBE_SFF_SFF_8472_SWAP         0x5C
  54 #define IXGBE_SFF_SFF_8472_COMP         0x5E
  55 #define IXGBE_SFF_SFF_8472_OSCB         0x6E
  56 #define IXGBE_SFF_SFF_8472_ESCB         0x76
  57 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS  0xD
  58 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
  59 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
  60 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
  61 #define IXGBE_SFF_QSFP_CONNECTOR        0x82
  62 #define IXGBE_SFF_QSFP_10GBE_COMP       0x83
  63 #define IXGBE_SFF_QSFP_1GBE_COMP        0x86
  64 #define IXGBE_SFF_QSFP_CABLE_LENGTH     0x92
  65 #define IXGBE_SFF_QSFP_DEVICE_TECH      0x93
  66 
  67 /* Bitmasks */
  68 #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
  69 #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
  70 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING       0x4
  71 #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
  72 #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
  73 #define IXGBE_SFF_1GBASET_CAPABLE       0x8
  74 #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
  75 #define IXGBE_SFF_10GBASELR_CAPABLE     0x20
  76 #define IXGBE_SFF_SOFT_RS_SELECT_MASK   0x8
  77 #define IXGBE_SFF_SOFT_RS_SELECT_10G    0x8
  78 #define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
  79 #define IXGBE_SFF_ADDRESSING_MODE       0x4
  80 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE  0x1
  81 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
  82 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE  0x23
  83 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL   0x0
  84 #define IXGBE_I2C_EEPROM_READ_MASK      0x100
  85 #define IXGBE_I2C_EEPROM_STATUS_MASK    0x3
  86 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
  87 #define IXGBE_I2C_EEPROM_STATUS_PASS    0x1
  88 #define IXGBE_I2C_EEPROM_STATUS_FAIL    0x2
  89 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS     0x3
  90 
  91 #define IXGBE_CS4227                    0xBE    /* CS4227 address */
  92 #define IXGBE_CS4227_GLOBAL_ID_LSB      0
  93 #define IXGBE_CS4227_SCRATCH            2
  94 #define IXGBE_CS4227_GLOBAL_ID_VALUE    0x03E5
  95 #define IXGBE_CS4227_RESET_PENDING      0x1357
  96 #define IXGBE_CS4227_RESET_COMPLETE     0x5AA5
  97 #define IXGBE_CS4227_RETRIES            15
  98 #define IXGBE_CS4227_EFUSE_STATUS       0x0181
  99 #define IXGBE_CS4227_LINE_SPARE22_MSB   0x12AD  /* Reg to program speed */
 100 #define IXGBE_CS4227_LINE_SPARE24_LSB   0x12B0  /* Reg to program EDC */
 101 #define IXGBE_CS4227_HOST_SPARE22_MSB   0x1AAD  /* Reg to program speed */
 102 #define IXGBE_CS4227_HOST_SPARE24_LSB   0x1AB0  /* Reg to program EDC */
 103 #define IXGBE_CS4227_EEPROM_STATUS      0x5001
 104 #define IXGBE_CS4227_EEPROM_LOAD_OK     0x0001
 105 #define IXGBE_CS4227_SPEED_1G           0x8000
 106 #define IXGBE_CS4227_SPEED_10G          0
 107 #define IXGBE_CS4227_EDC_MODE_CX1       0x0002
 108 #define IXGBE_CS4227_EDC_MODE_SR        0x0004
 109 #define IXGBE_CS4227_EDC_MODE_DIAG      0x0008
 110 #define IXGBE_CS4227_RESET_HOLD         500     /* microseconds */
 111 #define IXGBE_CS4227_RESET_DELAY        450     /* milliseconds */
 112 #define IXGBE_CS4227_CHECK_DELAY        30      /* milliseconds */
 113 #define IXGBE_PE                        0xE0    /* Port expander address */
 114 #define IXGBE_PE_OUTPUT                 1       /* Output register offset */
 115 #define IXGBE_PE_CONFIG                 3       /* Config register offset */
 116 #define IXGBE_PE_BIT1                   (1 << 1)
 117 
 118 /* Flow control defines */
 119 #define IXGBE_TAF_SYM_PAUSE             0x400
 120 #define IXGBE_TAF_ASM_PAUSE             0x800
 121 
 122 /* Bit-shift macros */
 123 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT        24
 124 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT        16
 125 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT        8
 126 
 127 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
 128 #define IXGBE_SFF_VENDOR_OUI_TYCO       0x00407600
 129 #define IXGBE_SFF_VENDOR_OUI_FTL        0x00906500
 130 #define IXGBE_SFF_VENDOR_OUI_AVAGO      0x00176A00
 131 #define IXGBE_SFF_VENDOR_OUI_INTEL      0x001B2100
 132 
 133 /* I2C SDA and SCL timing parameters for standard mode */
 134 #define IXGBE_I2C_T_HD_STA      4
 135 #define IXGBE_I2C_T_LOW         5
 136 #define IXGBE_I2C_T_HIGH        4
 137 #define IXGBE_I2C_T_SU_STA      5
 138 #define IXGBE_I2C_T_HD_DATA     5
 139 #define IXGBE_I2C_T_SU_DATA     1
 140 #define IXGBE_I2C_T_RISE        1
 141 #define IXGBE_I2C_T_FALL        1
 142 #define IXGBE_I2C_T_SU_STO      4
 143 #define IXGBE_I2C_T_BUF         5
 144 
 145 #ifndef IXGBE_SFP_DETECT_RETRIES
 146 #define IXGBE_SFP_DETECT_RETRIES        10
 147 
 148 #endif /* IXGBE_SFP_DETECT_RETRIES */
 149 #define IXGBE_TN_LASI_STATUS_REG        0x9005
 150 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
 151 
 152 /* SFP+ SFF-8472 Compliance */
 153 #define IXGBE_SFF_SFF_8472_UNSUP        0x00
 154 
 155 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
 156 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
 157 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
 158 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
 159 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 160 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
 161 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 162                            u16 *phy_data);
 163 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 164                             u16 phy_data);
 165 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 166                                u32 device_type, u16 *phy_data);
 167 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 168                                 u32 device_type, u16 phy_data);
 169 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 170 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 171                                        ixgbe_link_speed speed,

 172                                        bool autoneg_wait_to_complete);
 173 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 174                                                ixgbe_link_speed *speed,
 175                                                bool *autoneg);
 176 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
 177 
 178 /* PHY specific */
 179 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
 180                              ixgbe_link_speed *speed,
 181                              bool *link_up);
 182 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 183 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 184                                        u16 *firmware_version);
 185 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 186                                            u16 *firmware_version);
 187 
 188 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 189 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
 190 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
 191 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
 192 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
 193 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
 194 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 195                                         u16 *list_offset,
 196                                         u16 *data_offset);
 197 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 198 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 199                                 u8 dev_addr, u8 *data);
 200 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
 201                                          u8 dev_addr, u8 *data);
 202 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 203                                  u8 dev_addr, u8 data);
 204 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
 205                                           u8 dev_addr, u8 data);
 206 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 207                                   u8 *eeprom_data);
 208 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 209                                    u8 eeprom_data);
 210 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
 211 #endif /* _IXGBE_PHY_H_ */