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  32 ******************************************************************************/
  33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
  34 
  35 #include "ixgbe_api.h"
  36 #include "ixgbe_common.h"
  37 #include "ixgbe_phy.h"
  38 
  39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  50 
  51 /**
  52  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  53  *  @hw: pointer to the hardware structure
  54  *
  55  *  Initialize the function pointers.
  56  **/
  57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  58 {
  59         struct ixgbe_phy_info *phy = &hw->phy;
  60 
  61         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  62 
  63         /* PHY */
  64         phy->ops.identify = &ixgbe_identify_phy_generic;
  65         phy->ops.reset = &ixgbe_reset_phy_generic;
  66         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  67         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  68         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  69         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  70         phy->ops.check_link = NULL;
  71         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  72         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  73         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  74         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  75         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  76         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  77         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  78         phy->sfp_type = ixgbe_sfp_type_unknown;
  79         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  80         return IXGBE_SUCCESS;
  81 }
  82 
  83 /**
  84  *  ixgbe_identify_phy_generic - Get physical layer module
  85  *  @hw: pointer to hardware structure
  86  *
  87  *  Determines the physical layer module found on the current adapter.
  88  **/
  89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  90 {
  91         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  92         u32 phy_addr;
  93         u16 ext_ability = 0;
  94 
  95         DEBUGFUNC("ixgbe_identify_phy_generic");
  96 
  97         if (hw->phy.type == ixgbe_phy_unknown) {
  98                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  99                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 100                                 hw->phy.addr = phy_addr;
 101                                 (void) ixgbe_get_phy_id(hw);
 102                                 hw->phy.type =
 103                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 104 
 105                                 if (hw->phy.type == ixgbe_phy_unknown) {
 106                                         hw->phy.ops.read_reg(hw,
 107                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 108                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 109                                                   &ext_ability);
 110                                         if (ext_ability &
 111                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 112                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 113                                                 hw->phy.type =
 114                                                          ixgbe_phy_cu_unknown;
 115                                         else
 116                                                 hw->phy.type =
 117                                                          ixgbe_phy_generic;
 118                                 }
 119 
 120                                 status = IXGBE_SUCCESS;
 121                                 break;
 122                         }
 123                 }
 124                 /* clear value if nothing found */
 125                 if (status != IXGBE_SUCCESS)
 126                         hw->phy.addr = 0;
 127         } else {
 128                 status = IXGBE_SUCCESS;
 129         }
 130 
 131         return status;
 132 }
 133 
 134 /**
 135  *  ixgbe_validate_phy_addr - Determines phy address is valid
 136  *  @hw: pointer to hardware structure
 137  *
 138  **/
 139 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 140 {
 141         u16 phy_id = 0;
 142         bool valid = FALSE;
 143 
 144         DEBUGFUNC("ixgbe_validate_phy_addr");
 145 
 146         hw->phy.addr = phy_addr;
 147         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 148                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 149 
 150         if (phy_id != 0xFFFF && phy_id != 0x0)
 151                 valid = TRUE;
 152 
 153         return valid;
 154 }
 155 
 156 /**
 157  *  ixgbe_get_phy_id - Get the phy type
 158  *  @hw: pointer to hardware structure
 159  *
 160  **/
 161 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 162 {
 163         u32 status;
 164         u16 phy_id_high = 0;
 165         u16 phy_id_low = 0;
 166 
 167         DEBUGFUNC("ixgbe_get_phy_id");
 168 
 169         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 170                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 171                                       &phy_id_high);
 172 
 173         if (status == IXGBE_SUCCESS) {
 174                 hw->phy.id = (u32)(phy_id_high << 16);
 175                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 176                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 177                                               &phy_id_low);
 178                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 179                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 180         }
 181         return status;
 182 }
 183 
 184 /**
 185  *  ixgbe_get_phy_type_from_id - Get the phy type
 186  *  @hw: pointer to hardware structure
 187  *
 188  **/
 189 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 190 {
 191         enum ixgbe_phy_type phy_type;
 192 
 193         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 194 
 195         switch (phy_id) {
 196         case TN1010_PHY_ID:
 197                 phy_type = ixgbe_phy_tn;
 198                 break;
 199         case X540_PHY_ID:
 200                 phy_type = ixgbe_phy_aq;
 201                 break;
 202         case QT2022_PHY_ID:
 203                 phy_type = ixgbe_phy_qt;
 204                 break;
 205         case ATH_PHY_ID:
 206                 phy_type = ixgbe_phy_nl;
 207                 break;
 208         default:
 209                 phy_type = ixgbe_phy_unknown;
 210                 break;
 211         }
 212 
 213         DEBUGOUT1("phy type found is %d\n", phy_type);
 214         return phy_type;
 215 }
 216 
 217 /**
 218  *  ixgbe_reset_phy_generic - Performs a PHY reset
 219  *  @hw: pointer to hardware structure
 220  **/
 221 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 222 {
 223         u32 i;
 224         u16 ctrl = 0;
 225         s32 status = IXGBE_SUCCESS;
 226 
 227         DEBUGFUNC("ixgbe_reset_phy_generic");
 228 
 229         if (hw->phy.type == ixgbe_phy_unknown)
 230                 status = ixgbe_identify_phy_generic(hw);
 231 
 232         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 233                 goto out;
 234 
 235         /* Don't reset PHY if it's shut down due to overtemp. */
 236         if (!hw->phy.reset_if_overtemp &&
 237             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 238                 goto out;
 239 
 240         /*
 241          * Perform soft PHY reset to the PHY_XS.
 242          * This will cause a soft reset to the PHY
 243          */
 244         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 245                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 246                               IXGBE_MDIO_PHY_XS_RESET);
 247 
 248         /*
 249          * Poll for reset bit to self-clear indicating reset is complete.
 250          * Some PHYs could take up to 3 seconds to complete and need about
 251          * 1.7 usec delay after the reset is complete.
 252          */
 253         for (i = 0; i < 30; i++) {
 254                 msec_delay(100);
 255                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 256                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 257                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 258                         usec_delay(2);
 259                         break;
 260                 }
 261         }
 262 
 263         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 264                 status = IXGBE_ERR_RESET_FAILED;
 265                 DEBUGOUT("PHY reset polling failed to complete.\n");
 266         }
 267 
 268 out:
 269         return status;
 270 }
 271 
 272 /**
 273  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 274  *  @hw: pointer to hardware structure
 275  *  @reg_addr: 32 bit address of PHY register to read
 276  *  @phy_data: Pointer to read data from PHY register
 277  **/
 278 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 279                                u32 device_type, u16 *phy_data)
 280 {
 281         u32 command;
 282         u32 i;
 283         u32 data;
 284         s32 status = IXGBE_SUCCESS;
 285         u16 gssr;
 286 
 287         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 288 
 289         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 290                 gssr = IXGBE_GSSR_PHY1_SM;
 291         else
 292                 gssr = IXGBE_GSSR_PHY0_SM;
 293 
 294         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 295                 status = IXGBE_ERR_SWFW_SYNC;
 296 
 297         if (status == IXGBE_SUCCESS) {
 298                 /* Setup and write the address cycle command */
 299                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 300                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 301                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 302                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 303 
 304                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 305 
 306                 /*
 307                  * Check every 10 usec to see if the address cycle completed.
 308                  * The MDI Command bit will clear when the operation is
 309                  * complete
 310                  */
 311                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 312                         usec_delay(10);
 313 
 314                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 315 
 316                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 317                                 break;
 318                 }
 319 
 320                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 321                         DEBUGOUT("PHY address command did not complete.\n");
 322                         status = IXGBE_ERR_PHY;
 323                 }
 324 
 325                 if (status == IXGBE_SUCCESS) {
 326                         /*
 327                          * Address cycle complete, setup and write the read
 328                          * command
 329                          */
 330                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 331                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 332                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 333                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 334 
 335                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 336 
 337                         /*
 338                          * Check every 10 usec to see if the address cycle
 339                          * completed. The MDI Command bit will clear when the
 340                          * operation is complete
 341                          */
 342                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 343                                 usec_delay(10);
 344 
 345                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 346 
 347                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 348                                         break;
 349                         }
 350 
 351                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 352                                 DEBUGOUT("PHY read command didn't complete\n");
 353                                 status = IXGBE_ERR_PHY;
 354                         } else {
 355                                 /*
 356                                  * Read operation is complete.  Get the data
 357                                  * from MSRWD
 358                                  */
 359                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 360                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 361                                 *phy_data = (u16)(data);
 362                         }
 363                 }
 364 
 365                 hw->mac.ops.release_swfw_sync(hw, gssr);
 366         }
 367 
 368         return status;
 369 }
 370 
 371 /**
 372  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 373  *  @hw: pointer to hardware structure
 374  *  @reg_addr: 32 bit PHY register to write
 375  *  @device_type: 5 bit device type
 376  *  @phy_data: Data to write to the PHY register
 377  **/
 378 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 379                                 u32 device_type, u16 phy_data)
 380 {
 381         u32 command;
 382         u32 i;
 383         s32 status = IXGBE_SUCCESS;
 384         u16 gssr;
 385 
 386         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 387 
 388         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 389                 gssr = IXGBE_GSSR_PHY1_SM;
 390         else
 391                 gssr = IXGBE_GSSR_PHY0_SM;
 392 
 393         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 394                 status = IXGBE_ERR_SWFW_SYNC;
 395 
 396         if (status == IXGBE_SUCCESS) {
 397                 /* Put the data in the MDI single read and write data register*/
 398                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 399 
 400                 /* Setup and write the address cycle command */
 401                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 402                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 403                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 404                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 405 
 406                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 407 
 408                 /*
 409                  * Check every 10 usec to see if the address cycle completed.
 410                  * The MDI Command bit will clear when the operation is
 411                  * complete
 412                  */
 413                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 414                         usec_delay(10);
 415 
 416                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 417 
 418                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 419                                 break;
 420                 }
 421 
 422                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 423                         DEBUGOUT("PHY address cmd didn't complete\n");
 424                         status = IXGBE_ERR_PHY;
 425                 }
 426 
 427                 if (status == IXGBE_SUCCESS) {
 428                         /*
 429                          * Address cycle complete, setup and write the write
 430                          * command
 431                          */
 432                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 433                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 434                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 435                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 436 
 437                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 438 
 439                         /*
 440                          * Check every 10 usec to see if the address cycle
 441                          * completed. The MDI Command bit will clear when the
 442                          * operation is complete
 443                          */
 444                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 445                                 usec_delay(10);
 446 
 447                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 448 
 449                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 450                                         break;
 451                         }
 452 
 453                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 454                                 DEBUGOUT("PHY address cmd didn't complete\n");
 455                                 status = IXGBE_ERR_PHY;
 456                         }
 457                 }
 458 
 459                 hw->mac.ops.release_swfw_sync(hw, gssr);
 460         }
 461 
 462         return status;
 463 }
 464 
 465 /**
 466  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 467  *  @hw: pointer to hardware structure
 468  *
 469  *  Restart autonegotiation and PHY and waits for completion.
 470  **/
 471 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 472 {
 473         s32 status;
 474         u32 time_out;
 475         u32 max_time_out = 10;
 476         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 477         bool autoneg = FALSE;
 478         ixgbe_link_speed speed;
 479 
 480         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 481 
 482         status =
 483             ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 484         if (status != IXGBE_SUCCESS)
 485                 return status;
 486 
 487         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 488                 /* Set or unset auto-negotiation 10G advertisement */
 489                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 490                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 491                                      &autoneg_reg);
 492 
 493                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 494                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 495                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 496 
 497                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 498                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 499                                       autoneg_reg);
 500         }
 501 
 502         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 503                 /* Set or unset auto-negotiation 1G advertisement */
 504                 hw->phy.ops.read_reg(hw,
 505                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 506                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 507                                      &autoneg_reg);
 508 
 509                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 510                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 511                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 512 
 513                 hw->phy.ops.write_reg(hw,
 514                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 515                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 516                                       autoneg_reg);
 517         }
 518 
 519         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 520                 /* Set or unset auto-negotiation 100M advertisement */
 521                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 522                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 523                                      &autoneg_reg);
 524 
 525                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 526                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 527                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 528                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 529 
 530                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 531                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 532                                       autoneg_reg);
 533         }
 534 
 535         /* Restart PHY autonegotiation and wait for completion */
 536         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 537                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 538 
 539         autoneg_reg |= IXGBE_MII_RESTART;
 540 
 541         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 542                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 543 
 544         /* Wait for autonegotiation to finish */
 545         for (time_out = 0; time_out < max_time_out; time_out++) {
 546                 usec_delay(10);
 547                 /* Restart PHY autonegotiation and wait for completion */
 548                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 549                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 550                                               &autoneg_reg);
 551 
 552                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 553                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 554                         break;
 555         }
 556 
 557         if (time_out == max_time_out) {
 558                 status = IXGBE_ERR_LINK_SETUP;
 559                 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
 560         }
 561 
 562         return status;
 563 }
 564 
 565 /**
 566  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 567  *  @hw: pointer to hardware structure
 568  *  @speed: new link speed
 569  *  @autoneg: TRUE if autonegotiation enabled
 570  **/
 571 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 572                                        ixgbe_link_speed speed,
 573                                        bool autoneg,
 574                                        bool autoneg_wait_to_complete)
 575 {
 576         UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
 577 
 578         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 579 
 580         /*
 581          * Clear autoneg_advertised and set new values based on input link
 582          * speed.
 583          */
 584         hw->phy.autoneg_advertised = 0;
 585 
 586         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 587                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 588 
 589         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 590                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 591 
 592         if (speed & IXGBE_LINK_SPEED_100_FULL)
 593                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 594 
 595         /* Setup link based on the new speed settings */
 596         hw->phy.ops.setup_link(hw);
 597 
 598         return IXGBE_SUCCESS;
 599 }
 600 
 601 /**
 602  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 603  *  @hw: pointer to hardware structure
 604  *  @speed: pointer to link speed
 605  *  @autoneg: boolean auto-negotiation value
 606  *
 607  *  Determines the link capabilities by reading the AUTOC register.
 608  **/
 609 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 610                                                ixgbe_link_speed *speed,
 611                                                bool *autoneg)
 612 {
 613         s32 status = IXGBE_ERR_LINK_SETUP;
 614         u16 speed_ability;
 615 
 616         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 617 
 618         *speed = 0;
 619         *autoneg = TRUE;
 620 
 621         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 622                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 623                                       &speed_ability);
 624 
 625         if (status == IXGBE_SUCCESS) {
 626                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 627                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 628                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 629                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 630                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 631                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 632         }
 633 
 634         return status;
 635 }
 636 
 637 /**
 638  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 639  *  @hw: pointer to hardware structure
 640  *
 641  *  Reads the VS1 register to determine if link is up and the current speed for
 642  *  the PHY.
 643  **/
 644 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 645                              bool *link_up)
 646 {
 647         s32 status = IXGBE_SUCCESS;
 648         u32 time_out;
 649         u32 max_time_out = 10;
 650         u16 phy_link = 0;
 651         u16 phy_speed = 0;
 652         u16 phy_data = 0;
 653 
 654         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 655 
 656         /* Initialize speed and link to default case */
 657         *link_up = FALSE;
 658         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 659 
 660         /*
 661          * Check current speed and link status of the PHY register.
 662          * This is a vendor specific register and may have to
 663          * be changed for other copper PHYs.
 664          */
 665         for (time_out = 0; time_out < max_time_out; time_out++) {
 666                 usec_delay(10);
 667                 status = hw->phy.ops.read_reg(hw,
 668                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 669                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 670                                         &phy_data);
 671                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 672                 phy_speed = phy_data &
 673                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 674                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 675                         *link_up = TRUE;
 676                         if (phy_speed ==
 677                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 678                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 679                         break;
 680                 }
 681         }
 682 
 683         return status;
 684 }
 685 
 686 /**
 687  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 688  *      @hw: pointer to hardware structure
 689  *
 690  *      Restart autonegotiation and PHY and waits for completion.
 691  **/
 692 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 693 {
 694         s32 status;
 695         u32 time_out;
 696         u32 max_time_out = 10;
 697         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 698         bool autoneg = FALSE;
 699         ixgbe_link_speed speed;
 700 
 701         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 702 
 703         status =
 704             ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 705         if (status != IXGBE_SUCCESS)
 706                 return status;
 707 
 708         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 709                 /* Set or unset auto-negotiation 10G advertisement */
 710                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 711                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 712                                      &autoneg_reg);
 713 
 714                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 715                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 716                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 717 
 718                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 719                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 720                                       autoneg_reg);
 721         }
 722 
 723         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 724                 /* Set or unset auto-negotiation 1G advertisement */
 725                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 726                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 727                                      &autoneg_reg);
 728 
 729                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 730                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 731                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 732 
 733                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 734                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 735                                       autoneg_reg);
 736         }
 737 
 738         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 739                 /* Set or unset auto-negotiation 100M advertisement */
 740                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 741                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 742                                      &autoneg_reg);
 743 
 744                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 745                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 746                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 747 
 748                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 749                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 750                                       autoneg_reg);
 751         }
 752 
 753         /* Restart PHY autonegotiation and wait for completion */
 754         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 755                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 756 
 757         autoneg_reg |= IXGBE_MII_RESTART;
 758 
 759         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 760                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 761 
 762         /* Wait for autonegotiation to finish */
 763         for (time_out = 0; time_out < max_time_out; time_out++) {
 764                 usec_delay(10);
 765                 /* Restart PHY autonegotiation and wait for completion */
 766                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 767                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 768                                               &autoneg_reg);
 769 
 770                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 771                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 772                         break;
 773         }
 774 
 775         if (time_out == max_time_out) {
 776                 status = IXGBE_ERR_LINK_SETUP;
 777                 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
 778         }
 779 
 780         return status;
 781 }
 782 
 783 /**
 784  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 785  *  @hw: pointer to hardware structure
 786  *  @firmware_version: pointer to the PHY Firmware Version
 787  **/
 788 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 789                                        u16 *firmware_version)
 790 {
 791         s32 status = IXGBE_SUCCESS;
 792 
 793         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 794 
 795         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 796                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 797                                       firmware_version);
 798 
 799         return status;
 800 }
 801 
 802 /**
 803  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 804  *  @hw: pointer to hardware structure
 805  *  @firmware_version: pointer to the PHY Firmware Version
 806  **/
 807 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 808                                            u16 *firmware_version)
 809 {
 810         s32 status = IXGBE_SUCCESS;
 811 
 812         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 813 
 814         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 815                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 816                                       firmware_version);
 817 
 818         return status;
 819 }
 820 
 821 /**
 822  *  ixgbe_reset_phy_nl - Performs a PHY reset
 823  *  @hw: pointer to hardware structure
 824  **/
 825 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 826 {
 827         u16 phy_offset, control, eword, edata, block_crc;
 828         bool end_data = FALSE;
 829         u16 list_offset, data_offset;
 830         u16 phy_data = 0;
 831         s32 ret_val = IXGBE_SUCCESS;
 832         u32 i;
 833 
 834         DEBUGFUNC("ixgbe_reset_phy_nl");
 835 
 836         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 837                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 838 
 839         /* reset the PHY and poll for completion */
 840         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 841                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 842                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 843 
 844         for (i = 0; i < 100; i++) {
 845                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 846                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 847                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 848                         break;
 849                 msec_delay(10);
 850         }
 851 
 852         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 853                 DEBUGOUT("PHY reset did not complete.\n");
 854                 ret_val = IXGBE_ERR_PHY;
 855                 goto out;
 856         }
 857 
 858         /* Get init offsets */
 859         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 860                                                       &data_offset);
 861         if (ret_val != IXGBE_SUCCESS)
 862                 goto out;
 863 
 864         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 865         data_offset++;
 866         while (!end_data) {
 867                 /*
 868                  * Read control word from PHY init contents offset
 869                  */
 870                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 871                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 872                            IXGBE_CONTROL_SHIFT_NL;
 873                 edata = eword & IXGBE_DATA_MASK_NL;
 874                 switch (control) {
 875                 case IXGBE_DELAY_NL:
 876                         data_offset++;
 877                         DEBUGOUT1("DELAY: %d MS\n", edata);
 878                         msec_delay(edata);
 879                         break;
 880                 case IXGBE_DATA_NL:
 881                         DEBUGOUT("DATA:\n");
 882                         data_offset++;
 883                         hw->eeprom.ops.read(hw, data_offset++,
 884                                             &phy_offset);
 885                         for (i = 0; i < edata; i++) {
 886                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 887                                 hw->phy.ops.write_reg(hw, phy_offset,
 888                                                       IXGBE_TWINAX_DEV, eword);
 889                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 890                                           phy_offset);
 891                                 data_offset++;
 892                                 phy_offset++;
 893                         }
 894                         break;
 895                 case IXGBE_CONTROL_NL:
 896                         data_offset++;
 897                         DEBUGOUT("CONTROL:\n");
 898                         if (edata == IXGBE_CONTROL_EOL_NL) {
 899                                 DEBUGOUT("EOL\n");
 900                                 end_data = TRUE;
 901                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 902                                 DEBUGOUT("SOL\n");
 903                         } else {
 904                                 DEBUGOUT("Bad control value\n");
 905                                 ret_val = IXGBE_ERR_PHY;
 906                                 goto out;
 907                         }
 908                         break;
 909                 default:
 910                         DEBUGOUT("Bad control type\n");
 911                         ret_val = IXGBE_ERR_PHY;
 912                         goto out;
 913                 }
 914         }
 915 
 916 out:
 917         return ret_val;
 918 }
 919 
 920 /**
 921  *  ixgbe_identify_module_generic - Identifies module type
 922  *  @hw: pointer to hardware structure
 923  *
 924  *  Determines HW type and calls appropriate function.
 925  **/
 926 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 927 {
 928         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 929 
 930         DEBUGFUNC("ixgbe_identify_module_generic");
 931 
 932         switch (hw->mac.ops.get_media_type(hw)) {
 933         case ixgbe_media_type_fiber:
 934                 status = ixgbe_identify_sfp_module_generic(hw);
 935                 break;
 936 
 937 
 938         default:
 939                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 940                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 941                 break;
 942         }
 943 
 944         return status;
 945 }
 946 
 947 /**
 948  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 949  *  @hw: pointer to hardware structure
 950  *
 951  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 952  **/
 953 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 954 {
 955         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 956         u32 vendor_oui = 0;
 957         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 958         u8 identifier = 0;
 959         u8 comp_codes_1g = 0;
 960         u8 comp_codes_10g = 0;
 961         u8 oui_bytes[3] = {0, 0, 0};
 962         u8 cable_tech = 0;
 963         u8 cable_spec = 0;
 964         u16 enforce_sfp = 0;
 965 
 966         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
 967 
 968         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 969                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 970                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 971                 goto out;
 972         }
 973 
 974         status = hw->phy.ops.read_i2c_eeprom(hw,
 975                                              IXGBE_SFF_IDENTIFIER,
 976                                              &identifier);
 977 
 978         if (status == IXGBE_ERR_SWFW_SYNC ||
 979             status == IXGBE_ERR_I2C ||
 980             status == IXGBE_ERR_SFP_NOT_PRESENT)
 981                 goto err_read_i2c_eeprom;
 982 
 983         /* LAN ID is needed for sfp_type determination */
 984         hw->mac.ops.set_lan_id(hw);
 985 
 986         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 987                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 988                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 989         } else {
 990                 status = hw->phy.ops.read_i2c_eeprom(hw,
 991                                                      IXGBE_SFF_1GBE_COMP_CODES,
 992                                                      &comp_codes_1g);
 993 
 994                 if (status == IXGBE_ERR_SWFW_SYNC ||
 995                     status == IXGBE_ERR_I2C ||
 996                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 997                         goto err_read_i2c_eeprom;
 998 
 999                 status = hw->phy.ops.read_i2c_eeprom(hw,
1000                                                      IXGBE_SFF_10GBE_COMP_CODES,
1001                                                      &comp_codes_10g);
1002 
1003                 if (status == IXGBE_ERR_SWFW_SYNC ||
1004                     status == IXGBE_ERR_I2C ||
1005                     status == IXGBE_ERR_SFP_NOT_PRESENT)
1006                         goto err_read_i2c_eeprom;
1007                 status = hw->phy.ops.read_i2c_eeprom(hw,
1008                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1009                                                      &cable_tech);
1010 
1011                 if (status == IXGBE_ERR_SWFW_SYNC ||
1012                     status == IXGBE_ERR_I2C ||
1013                     status == IXGBE_ERR_SFP_NOT_PRESENT)
1014                         goto err_read_i2c_eeprom;
1015 
1016                  /* ID Module
1017                   * =========
1018                   * 0   SFP_DA_CU
1019                   * 1   SFP_SR
1020                   * 2   SFP_LR
1021                   * 3   SFP_DA_CORE0 - 82599-specific
1022                   * 4   SFP_DA_CORE1 - 82599-specific
1023                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1024                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1025                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1026                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1027                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1028                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1029                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1030                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1031                   */
1032                 if (hw->mac.type == ixgbe_mac_82598EB) {
1033                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1034                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1035                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1036                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1037                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1038                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1039                         else
1040                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1041                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1042                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1043                                 if (hw->bus.lan_id == 0)
1044                                         hw->phy.sfp_type =
1045                                                      ixgbe_sfp_type_da_cu_core0;
1046                                 else
1047                                         hw->phy.sfp_type =
1048                                                      ixgbe_sfp_type_da_cu_core1;
1049                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1050                                 hw->phy.ops.read_i2c_eeprom(
1051                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1052                                                 &cable_spec);
1053                                 if (cable_spec &
1054                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1055                                         if (hw->bus.lan_id == 0)
1056                                                 hw->phy.sfp_type =
1057                                                 ixgbe_sfp_type_da_act_lmt_core0;
1058                                         else
1059                                                 hw->phy.sfp_type =
1060                                                 ixgbe_sfp_type_da_act_lmt_core1;
1061                                 } else {
1062                                         hw->phy.sfp_type =
1063                                                         ixgbe_sfp_type_unknown;
1064                                 }
1065                         } else if (comp_codes_10g &
1066                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1067                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1068                                 if (hw->bus.lan_id == 0)
1069                                         hw->phy.sfp_type =
1070                                                       ixgbe_sfp_type_srlr_core0;
1071                                 else
1072                                         hw->phy.sfp_type =
1073                                                       ixgbe_sfp_type_srlr_core1;
1074                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1075                                 if (hw->bus.lan_id == 0)
1076                                         hw->phy.sfp_type =
1077                                                 ixgbe_sfp_type_1g_cu_core0;
1078                                 else
1079                                         hw->phy.sfp_type =
1080                                                 ixgbe_sfp_type_1g_cu_core1;
1081                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1082                                 if (hw->bus.lan_id == 0)
1083                                         hw->phy.sfp_type =
1084                                                 ixgbe_sfp_type_1g_sx_core0;
1085                                 else
1086                                         hw->phy.sfp_type =
1087                                                 ixgbe_sfp_type_1g_sx_core1;
1088                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1089                                 if (hw->bus.lan_id == 0)
1090                                         hw->phy.sfp_type =
1091                                                 ixgbe_sfp_type_1g_lx_core0;
1092                                 else
1093                                         hw->phy.sfp_type =
1094                                                 ixgbe_sfp_type_1g_lx_core1;
1095                         } else {
1096                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1097                         }
1098                 }
1099 
1100                 if (hw->phy.sfp_type != stored_sfp_type)
1101                         hw->phy.sfp_setup_needed = TRUE;
1102 
1103                 /* Determine if the SFP+ PHY is dual speed or not. */
1104                 hw->phy.multispeed_fiber = FALSE;
1105                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1106                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1107                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1108                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1109                         hw->phy.multispeed_fiber = TRUE;
1110 
1111                 /* Determine PHY vendor */
1112                 if (hw->phy.type != ixgbe_phy_nl) {
1113                         hw->phy.id = identifier;
1114                         status = hw->phy.ops.read_i2c_eeprom(hw,
1115                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1116                                                     &oui_bytes[0]);
1117 
1118                         if (status == IXGBE_ERR_SWFW_SYNC ||
1119                             status == IXGBE_ERR_I2C ||
1120                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1121                                 goto err_read_i2c_eeprom;
1122 
1123                         status = hw->phy.ops.read_i2c_eeprom(hw,
1124                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1125                                                     &oui_bytes[1]);
1126 
1127                         if (status == IXGBE_ERR_SWFW_SYNC ||
1128                             status == IXGBE_ERR_I2C ||
1129                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1130                                 goto err_read_i2c_eeprom;
1131 
1132                         status = hw->phy.ops.read_i2c_eeprom(hw,
1133                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1134                                                     &oui_bytes[2]);
1135 
1136                         if (status == IXGBE_ERR_SWFW_SYNC ||
1137                             status == IXGBE_ERR_I2C ||
1138                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1139                                 goto err_read_i2c_eeprom;
1140 
1141                         vendor_oui =
1142                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1143                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1144                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1145 
1146                         switch (vendor_oui) {
1147                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1148                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1149                                         hw->phy.type =
1150                                                     ixgbe_phy_sfp_passive_tyco;
1151                                 break;
1152                         case IXGBE_SFF_VENDOR_OUI_FTL:
1153                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1154                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1155                                 else
1156                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1157                                 break;
1158                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1159                                 hw->phy.type = ixgbe_phy_sfp_avago;
1160                                 break;
1161                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1162                                 hw->phy.type = ixgbe_phy_sfp_intel;
1163                                 break;
1164                         default:
1165                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1166                                         hw->phy.type =
1167                                                  ixgbe_phy_sfp_passive_unknown;
1168                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1169                                         hw->phy.type =
1170                                                 ixgbe_phy_sfp_active_unknown;
1171                                 else
1172                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1173                                 break;
1174                         }
1175                 }
1176 
1177                 /* Allow any DA cable vendor */
1178                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1179                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1180                         status = IXGBE_SUCCESS;
1181                         goto out;
1182                 }
1183 
1184                 /* Verify supported 1G SFP modules */
1185                 if (comp_codes_10g == 0 &&
1186                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1187                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1188                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1189                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1190                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0  ||
1191                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1192                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1193                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1194                         goto out;
1195                 }
1196 
1197                 /* Anything else 82598-based is supported */
1198                 if (hw->mac.type == ixgbe_mac_82598EB) {
1199                         status = IXGBE_SUCCESS;
1200                         goto out;
1201                 }
1202 
1203                 (void) ixgbe_get_device_caps(hw, &enforce_sfp);
1204                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1205                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1206                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1207                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1208                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1209                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1210                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1211                         /* Make sure we're a supported PHY type */
1212                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1213                                 status = IXGBE_SUCCESS;
1214                         } else {
1215                                 if (hw->allow_unsupported_sfp == TRUE) {
1216                                         EWARN(hw, "WARNING: Intel (R) Network "
1217                                               "Connections are quality tested "
1218                                               "using Intel (R) Ethernet Optics."
1219                                               " Using untested modules is not "
1220                                               "supported and may cause unstable"
1221                                               " operation or damage to the "
1222                                               "module or the adapter. Intel "
1223                                               "Corporation is not responsible "
1224                                               "for any harm caused by using "
1225                                               "untested modules.\n", status);
1226                                         status = IXGBE_SUCCESS;
1227                                 } else {
1228                                         EWARN(hw, "SFP+ module not supported\n",
1229                                               status);
1230                                         hw->phy.type =
1231                                                 ixgbe_phy_sfp_unsupported;
1232                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1233                                 }
1234                         }
1235                 } else {
1236                         status = IXGBE_SUCCESS;
1237                 }
1238         }
1239 
1240 out:
1241         return status;
1242 
1243 err_read_i2c_eeprom:
1244         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1245         if (hw->phy.type != ixgbe_phy_nl) {
1246                 hw->phy.id = 0;
1247                 hw->phy.type = ixgbe_phy_unknown;
1248         }
1249         return IXGBE_ERR_SFP_NOT_PRESENT;
1250 }
1251 
1252 
1253 
1254 /**
1255  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1256  *  @hw: pointer to hardware structure
1257  *  @list_offset: offset to the SFP ID list
1258  *  @data_offset: offset to the SFP data block
1259  *
1260  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1261  *  so it returns the offsets to the phy init sequence block.
1262  **/
1263 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1264                                         u16 *list_offset,
1265                                         u16 *data_offset)
1266 {
1267         u16 sfp_id;
1268         u16 sfp_type = hw->phy.sfp_type;
1269 
1270         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1271 
1272         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1273                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1274 
1275         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1276                 return IXGBE_ERR_SFP_NOT_PRESENT;
1277 
1278         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1279             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1280                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1281 
1282         /*
1283          * Limiting active cables and 1G Phys must be initialized as
1284          * SR modules
1285          */
1286         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1287             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1288             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1289             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1290                 sfp_type = ixgbe_sfp_type_srlr_core0;
1291         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1292                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1293                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1294                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1295                 sfp_type = ixgbe_sfp_type_srlr_core1;
1296 
1297         /* Read offset to PHY init contents */
1298         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1299 
1300         if ((!*list_offset) || (*list_offset == 0xFFFF))
1301                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1302 
1303         /* Shift offset to first ID word */
1304         (*list_offset)++;
1305 
1306         /*
1307          * Find the matching SFP ID in the EEPROM
1308          * and program the init sequence
1309          */
1310         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1311 
1312         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1313                 if (sfp_id == sfp_type) {
1314                         (*list_offset)++;
1315                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
1316                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1317                                 DEBUGOUT("SFP+ module not supported\n");
1318                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1319                         } else {
1320                                 break;
1321                         }
1322                 } else {
1323                         (*list_offset) += 2;
1324                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1325                                 return IXGBE_ERR_PHY;
1326                 }
1327         }
1328 
1329         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1330                 DEBUGOUT("No matching SFP+ module found\n");
1331                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1332         }
1333 
1334         return IXGBE_SUCCESS;
1335 }
1336 
1337 /**
1338  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1339  *  @hw: pointer to hardware structure
1340  *  @byte_offset: EEPROM byte offset to read
1341  *  @eeprom_data: value read
1342  *
1343  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1344  **/
1345 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1346                                   u8 *eeprom_data)
1347 {
1348         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1349 
1350         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1351                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1352                                          eeprom_data);
1353 }
1354 
1355 /**
1356  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1357  *  @hw: pointer to hardware structure
1358  *  @byte_offset: EEPROM byte offset to write
1359  *  @eeprom_data: value to write
1360  *
1361  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1362  **/
1363 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1364                                    u8 eeprom_data)
1365 {
1366         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1367 
1368         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1369                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1370                                           eeprom_data);
1371 }
1372 
1373 /**
1374  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1375  *  @hw: pointer to hardware structure
1376  *  @byte_offset: byte offset to read
1377  *  @data: value read
1378  *
1379  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1380  *  a specified device address.
1381  **/
1382 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1383                                 u8 dev_addr, u8 *data)
1384 {
1385         s32 status = IXGBE_SUCCESS;
1386         u32 max_retry = 10;
1387         u32 retry = 0;
1388         u16 swfw_mask = 0;
1389         bool nack = 1;
1390         *data = 0;
1391 
1392         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1393 
1394         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1395                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1396         else
1397                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1398 
1399         do {
1400                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1401                     != IXGBE_SUCCESS) {
1402                         status = IXGBE_ERR_SWFW_SYNC;
1403                         goto read_byte_out;
1404                 }
1405 
1406                 ixgbe_i2c_start(hw);
1407 
1408                 /* Device Address and write indication */
1409                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1410                 if (status != IXGBE_SUCCESS)
1411                         goto fail;
1412 
1413                 status = ixgbe_get_i2c_ack(hw);
1414                 if (status != IXGBE_SUCCESS)
1415                         goto fail;
1416 
1417                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1418                 if (status != IXGBE_SUCCESS)
1419                         goto fail;
1420 
1421                 status = ixgbe_get_i2c_ack(hw);
1422                 if (status != IXGBE_SUCCESS)
1423                         goto fail;
1424 
1425                 ixgbe_i2c_start(hw);
1426 
1427                 /* Device Address and read indication */
1428                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1429                 if (status != IXGBE_SUCCESS)
1430                         goto fail;
1431 
1432                 status = ixgbe_get_i2c_ack(hw);
1433                 if (status != IXGBE_SUCCESS)
1434                         goto fail;
1435 
1436                 status = ixgbe_clock_in_i2c_byte(hw, data);
1437                 if (status != IXGBE_SUCCESS)
1438                         goto fail;
1439 
1440                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1441                 if (status != IXGBE_SUCCESS)
1442                         goto fail;
1443 
1444                 ixgbe_i2c_stop(hw);
1445                 break;
1446 
1447 fail:
1448                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1449                 msec_delay(100);
1450                 ixgbe_i2c_bus_clear(hw);
1451                 retry++;
1452                 if (retry < max_retry)
1453                         DEBUGOUT("I2C byte read error - Retrying.\n");
1454                 else
1455                         DEBUGOUT("I2C byte read error.\n");
1456 
1457         } while (retry < max_retry);
1458 
1459         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1460 
1461 read_byte_out:
1462         return status;
1463 }
1464 
1465 /**
1466  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1467  *  @hw: pointer to hardware structure
1468  *  @byte_offset: byte offset to write
1469  *  @data: value to write
1470  *
1471  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1472  *  a specified device address.
1473  **/
1474 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1475                                  u8 dev_addr, u8 data)
1476 {
1477         s32 status = IXGBE_SUCCESS;
1478         u32 max_retry = 1;
1479         u32 retry = 0;
1480         u16 swfw_mask = 0;
1481 
1482         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1483 
1484         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1485                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1486         else
1487                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1488 
1489         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1490                 status = IXGBE_ERR_SWFW_SYNC;
1491                 goto write_byte_out;
1492         }
1493 
1494         do {
1495                 ixgbe_i2c_start(hw);
1496 
1497                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1498                 if (status != IXGBE_SUCCESS)
1499                         goto fail;
1500 
1501                 status = ixgbe_get_i2c_ack(hw);
1502                 if (status != IXGBE_SUCCESS)
1503                         goto fail;
1504 
1505                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1506                 if (status != IXGBE_SUCCESS)
1507                         goto fail;
1508 
1509                 status = ixgbe_get_i2c_ack(hw);
1510                 if (status != IXGBE_SUCCESS)
1511                         goto fail;
1512 
1513                 status = ixgbe_clock_out_i2c_byte(hw, data);
1514                 if (status != IXGBE_SUCCESS)
1515                         goto fail;
1516 
1517                 status = ixgbe_get_i2c_ack(hw);
1518                 if (status != IXGBE_SUCCESS)
1519                         goto fail;
1520 
1521                 ixgbe_i2c_stop(hw);
1522                 break;
1523 
1524 fail:
1525                 ixgbe_i2c_bus_clear(hw);
1526                 retry++;
1527                 if (retry < max_retry)
1528                         DEBUGOUT("I2C byte write error - Retrying.\n");
1529                 else
1530                         DEBUGOUT("I2C byte write error.\n");
1531         } while (retry < max_retry);
1532 
1533         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1534 
1535 write_byte_out:
1536         return status;
1537 }
1538 
1539 /**
1540  *  ixgbe_i2c_start - Sets I2C start condition
1541  *  @hw: pointer to hardware structure
1542  *
1543  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1544  **/
1545 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1546 {
1547         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1548 
1549         DEBUGFUNC("ixgbe_i2c_start");
1550 
1551         /* Start condition must begin with data and clock high */
1552         (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1553         ixgbe_raise_i2c_clk(hw, &i2cctl);
1554 
1555         /* Setup time for start condition (4.7us) */
1556         usec_delay(IXGBE_I2C_T_SU_STA);
1557 
1558         (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1559 
1560         /* Hold time for start condition (4us) */
1561         usec_delay(IXGBE_I2C_T_HD_STA);
1562 
1563         ixgbe_lower_i2c_clk(hw, &i2cctl);
1564 
1565         /* Minimum low period of clock is 4.7 us */
1566         usec_delay(IXGBE_I2C_T_LOW);
1567 
1568 }
1569 
1570 /**
1571  *  ixgbe_i2c_stop - Sets I2C stop condition
1572  *  @hw: pointer to hardware structure
1573  *
1574  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1575  **/
1576 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1577 {
1578         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1579 
1580         DEBUGFUNC("ixgbe_i2c_stop");
1581 
1582         /* Stop condition must begin with data low and clock high */
1583         (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1584         ixgbe_raise_i2c_clk(hw, &i2cctl);
1585 
1586         /* Setup time for stop condition (4us) */
1587         usec_delay(IXGBE_I2C_T_SU_STO);
1588 
1589         (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1590 
1591         /* bus free time between stop and start (4.7us)*/
1592         usec_delay(IXGBE_I2C_T_BUF);
1593 }
1594 
1595 /**
1596  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1597  *  @hw: pointer to hardware structure
1598  *  @data: data byte to clock in
1599  *
1600  *  Clocks in one byte data via I2C data/clock
1601  **/
1602 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1603 {
1604         s32 i, status = IXGBE_SUCCESS;
1605         bool bit = 0;
1606 
1607         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1608 
1609         for (i = 7; i >= 0; i--) {
1610                 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1611                 if (status != IXGBE_SUCCESS)
1612                         break;
1613                 *data |= bit << i;
1614         }
1615 
1616         return status;
1617 }
1618 
1619 /**
1620  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1621  *  @hw: pointer to hardware structure
1622  *  @data: data byte clocked out
1623  *
1624  *  Clocks out one byte data via I2C data/clock
1625  **/
1626 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1627 {
1628         s32 status = IXGBE_SUCCESS;
1629         s32 i;
1630         u32 i2cctl;
1631         bool bit = 0;
1632 
1633         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1634 
1635         for (i = 7; i >= 0; i--) {
1636                 bit = (data >> i) & 0x1;
1637                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1638 
1639                 if (status != IXGBE_SUCCESS)
1640                         break;
1641         }
1642 
1643         /* Release SDA line (set high) */
1644         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1645         i2cctl |= IXGBE_I2C_DATA_OUT;
1646         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1647         IXGBE_WRITE_FLUSH(hw);
1648 
1649         return status;
1650 }
1651 
1652 /**
1653  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1654  *  @hw: pointer to hardware structure
1655  *
1656  *  Clocks in/out one bit via I2C data/clock
1657  **/
1658 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1659 {
1660         s32 status = IXGBE_SUCCESS;
1661         u32 i = 0;
1662         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1663         u32 timeout = 10;
1664         bool ack = 1;
1665 
1666         DEBUGFUNC("ixgbe_get_i2c_ack");
1667 
1668         ixgbe_raise_i2c_clk(hw, &i2cctl);
1669 
1670 
1671         /* Minimum high period of clock is 4us */
1672         usec_delay(IXGBE_I2C_T_HIGH);
1673 
1674         /* Poll for ACK.  Note that ACK in I2C spec is
1675          * transition from 1 to 0 */
1676         for (i = 0; i < timeout; i++) {
1677                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1678                 ack = ixgbe_get_i2c_data(&i2cctl);
1679 
1680                 usec_delay(1);
1681                 if (ack == 0)
1682                         break;
1683         }
1684 
1685         if (ack == 1) {
1686                 DEBUGOUT("I2C ack was not received.\n");
1687                 status = IXGBE_ERR_I2C;
1688         }
1689 
1690         ixgbe_lower_i2c_clk(hw, &i2cctl);
1691 
1692         /* Minimum low period of clock is 4.7 us */
1693         usec_delay(IXGBE_I2C_T_LOW);
1694 
1695         return status;
1696 }
1697 
1698 /**
1699  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1700  *  @hw: pointer to hardware structure
1701  *  @data: read data value
1702  *
1703  *  Clocks in one bit via I2C data/clock
1704  **/
1705 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1706 {
1707         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1708 
1709         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1710 
1711         ixgbe_raise_i2c_clk(hw, &i2cctl);
1712 
1713         /* Minimum high period of clock is 4us */
1714         usec_delay(IXGBE_I2C_T_HIGH);
1715 
1716         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1717         *data = ixgbe_get_i2c_data(&i2cctl);
1718 
1719         ixgbe_lower_i2c_clk(hw, &i2cctl);
1720 
1721         /* Minimum low period of clock is 4.7 us */
1722         usec_delay(IXGBE_I2C_T_LOW);
1723 
1724         return IXGBE_SUCCESS;
1725 }
1726 
1727 /**
1728  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1729  *  @hw: pointer to hardware structure
1730  *  @data: data value to write
1731  *
1732  *  Clocks out one bit via I2C data/clock
1733  **/
1734 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1735 {
1736         s32 status;
1737         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1738 
1739         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1740 
1741         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1742         if (status == IXGBE_SUCCESS) {
1743                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1744 
1745                 /* Minimum high period of clock is 4us */
1746                 usec_delay(IXGBE_I2C_T_HIGH);
1747 
1748                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1749 
1750                 /* Minimum low period of clock is 4.7 us.
1751                  * This also takes care of the data hold time.
1752                  */
1753                 usec_delay(IXGBE_I2C_T_LOW);
1754         } else {
1755                 status = IXGBE_ERR_I2C;
1756                 DEBUGOUT1("I2C data was not set to %X\n", data);
1757         }
1758 
1759         return status;
1760 }
1761 /**
1762  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1763  *  @hw: pointer to hardware structure
1764  *  @i2cctl: Current value of I2CCTL register
1765  *
1766  *  Raises the I2C clock line '0'->'1'
1767  **/
1768 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1769 {
1770         u32 i = 0;
1771         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1772         u32 i2cctl_r = 0;
1773 
1774         DEBUGFUNC("ixgbe_raise_i2c_clk");
1775 
1776         for (i = 0; i < timeout; i++) {
1777                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1778 
1779                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1780                 IXGBE_WRITE_FLUSH(hw);
1781                 /* SCL rise time (1000ns) */
1782                 usec_delay(IXGBE_I2C_T_RISE);
1783 
1784                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1785                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1786                         break;
1787         }
1788 }
1789 
1790 /**
1791  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1792  *  @hw: pointer to hardware structure
1793  *  @i2cctl: Current value of I2CCTL register
1794  *
1795  *  Lowers the I2C clock line '1'->'0'
1796  **/
1797 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1798 {
1799 
1800         DEBUGFUNC("ixgbe_lower_i2c_clk");
1801 
1802         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1803 
1804         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1805         IXGBE_WRITE_FLUSH(hw);
1806 
1807         /* SCL fall time (300ns) */
1808         usec_delay(IXGBE_I2C_T_FALL);
1809 }
1810 
1811 /**
1812  *  ixgbe_set_i2c_data - Sets the I2C data bit
1813  *  @hw: pointer to hardware structure
1814  *  @i2cctl: Current value of I2CCTL register
1815  *  @data: I2C data value (0 or 1) to set
1816  *
1817  *  Sets the I2C data bit
1818  **/
1819 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1820 {
1821         s32 status = IXGBE_SUCCESS;
1822 
1823         DEBUGFUNC("ixgbe_set_i2c_data");
1824 
1825         if (data)
1826                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1827         else
1828                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1829 
1830         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1831         IXGBE_WRITE_FLUSH(hw);
1832 
1833         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1834         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1835 
1836         /* Verify data was set correctly */
1837         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1838         if (data != ixgbe_get_i2c_data(i2cctl)) {
1839                 status = IXGBE_ERR_I2C;
1840                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1841         }
1842 
1843         return status;
1844 }
1845 
1846 /**
1847  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1848  *  @hw: pointer to hardware structure
1849  *  @i2cctl: Current value of I2CCTL register
1850  *
1851  *  Returns the I2C data bit value
1852  **/
1853 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1854 {
1855         bool data;
1856 
1857         DEBUGFUNC("ixgbe_get_i2c_data");
1858 
1859         if (*i2cctl & IXGBE_I2C_DATA_IN)
1860                 data = 1;
1861         else
1862                 data = 0;
1863 
1864         return data;
1865 }
1866 
1867 /**
1868  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1869  *  @hw: pointer to hardware structure
1870  *
1871  *  Clears the I2C bus by sending nine clock pulses.
1872  *  Used when data line is stuck low.
1873  **/
1874 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1875 {
1876         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1877         u32 i;
1878 
1879         DEBUGFUNC("ixgbe_i2c_bus_clear");
1880 
1881         ixgbe_i2c_start(hw);
1882 
1883         (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1884 
1885         for (i = 0; i < 9; i++) {
1886                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1887 
1888                 /* Min high period of clock is 4us */
1889                 usec_delay(IXGBE_I2C_T_HIGH);
1890 
1891                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1892 
1893                 /* Min low period of clock is 4.7us*/
1894                 usec_delay(IXGBE_I2C_T_LOW);
1895         }
1896 
1897         ixgbe_i2c_start(hw);
1898 
1899         /* Put the i2c bus back to default state */
1900         ixgbe_i2c_stop(hw);
1901 }
1902 
1903 /**
1904  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1905  *  @hw: pointer to hardware structure
1906  *
1907  *  Checks if the LASI temp alarm status was triggered due to overtemp
1908  **/
1909 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1910 {
1911         s32 status = IXGBE_SUCCESS;
1912         u16 phy_data = 0;
1913 
1914         DEBUGFUNC("ixgbe_tn_check_overtemp");
1915 
1916         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1917                 goto out;
1918 
1919         /* Check that the LASI temp alarm status was triggered */
1920         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1921                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1922 
1923         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1924                 goto out;
1925 
1926         status = IXGBE_ERR_OVERTEMP;
1927 out:
1928         return status;
1929 }