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6064 ixgbe needs X550 support
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_api.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_api.c
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2012, Intel Corporation
3 + Copyright (c) 2001-2015, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 -/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
33 +/*$FreeBSD$*/
34 34
35 35 #include "ixgbe_api.h"
36 36 #include "ixgbe_common.h"
37 37
38 +#define IXGBE_EMPTY_PARAM
39 +
40 +static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {
41 + IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM)
42 +};
43 +
44 +static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
45 + IXGBE_MVALS_INIT(_X540)
46 +};
47 +
48 +static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
49 + IXGBE_MVALS_INIT(_X550)
50 +};
51 +
52 +static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
53 + IXGBE_MVALS_INIT(_X550EM_x)
54 +};
55 +
38 56 /**
57 + * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
58 + * @hw: pointer to hardware structure
59 + * @map: pointer to u8 arr for returning map
60 + *
61 + * Read the rtrup2tc HW register and resolve its content into map
62 + **/
63 +void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
64 +{
65 + if (hw->mac.ops.get_rtrup2tc)
66 + hw->mac.ops.get_rtrup2tc(hw, map);
67 +}
68 +
69 +/**
39 70 * ixgbe_init_shared_code - Initialize the shared code
40 71 * @hw: pointer to hardware structure
41 72 *
42 73 * This will assign function pointers and assign the MAC type and PHY code.
43 74 * Does not touch the hardware. This function must be called prior to any
44 75 * other function in the shared code. The ixgbe_hw structure should be
45 76 * memset to 0 prior to calling this function. The following fields in
46 77 * hw structure should be filled in prior to calling this function:
47 78 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
48 79 * subsystem_vendor_id, and revision_id
49 80 **/
50 81 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
51 82 {
52 83 s32 status;
53 84
54 85 DEBUGFUNC("ixgbe_init_shared_code");
55 86
56 87 /*
57 88 * Set the mac type
58 89 */
59 - status = ixgbe_set_mac_type(hw);
60 - if (status != IXGBE_SUCCESS)
61 - return (status);
90 + ixgbe_set_mac_type(hw);
62 91
63 92 switch (hw->mac.type) {
64 93 case ixgbe_mac_82598EB:
65 94 status = ixgbe_init_ops_82598(hw);
66 95 break;
67 96 case ixgbe_mac_82599EB:
68 97 status = ixgbe_init_ops_82599(hw);
69 98 break;
70 99 case ixgbe_mac_X540:
71 100 status = ixgbe_init_ops_X540(hw);
72 101 break;
102 + case ixgbe_mac_X550:
103 + status = ixgbe_init_ops_X550(hw);
104 + break;
105 + case ixgbe_mac_X550EM_x:
106 + status = ixgbe_init_ops_X550EM(hw);
107 + break;
108 + case ixgbe_mac_82599_vf:
109 + case ixgbe_mac_X540_vf:
110 + case ixgbe_mac_X550_vf:
111 + case ixgbe_mac_X550EM_x_vf:
112 + status = ixgbe_init_ops_vf(hw);
113 + break;
73 114 default:
74 115 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
75 116 break;
76 117 }
118 + hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;
77 119
78 120 return status;
79 121 }
80 122
81 123 /**
82 124 * ixgbe_set_mac_type - Sets MAC type
83 125 * @hw: pointer to the HW structure
84 126 *
85 127 * This function sets the mac type of the adapter based on the
86 128 * vendor ID and device ID stored in the hw structure.
87 129 **/
88 130 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
89 131 {
90 132 s32 ret_val = IXGBE_SUCCESS;
91 133
92 134 DEBUGFUNC("ixgbe_set_mac_type\n");
93 135
94 - if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
95 - switch (hw->device_id) {
96 - case IXGBE_DEV_ID_82598:
97 - case IXGBE_DEV_ID_82598_BX:
98 - case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
99 - case IXGBE_DEV_ID_82598AF_DUAL_PORT:
100 - case IXGBE_DEV_ID_82598AT:
101 - case IXGBE_DEV_ID_82598AT2:
102 - case IXGBE_DEV_ID_82598EB_CX4:
103 - case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
104 - case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
105 - case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
106 - case IXGBE_DEV_ID_82598EB_XF_LR:
107 - case IXGBE_DEV_ID_82598EB_SFP_LOM:
108 - hw->mac.type = ixgbe_mac_82598EB;
109 - break;
110 - case IXGBE_DEV_ID_82599_KX4:
111 - case IXGBE_DEV_ID_82599_KX4_MEZZ:
112 - case IXGBE_DEV_ID_82599_XAUI_LOM:
113 - case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
114 - case IXGBE_DEV_ID_82599_KR:
115 - case IXGBE_DEV_ID_82599_SFP:
116 - case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
117 - case IXGBE_DEV_ID_82599_SFP_FCOE:
118 - case IXGBE_DEV_ID_82599_SFP_EM:
119 - case IXGBE_DEV_ID_82599_SFP_SF2:
120 - case IXGBE_DEV_ID_82599EN_SFP:
121 - case IXGBE_DEV_ID_82599_CX4:
122 - case IXGBE_DEV_ID_82599_T3_LOM:
123 - hw->mac.type = ixgbe_mac_82599EB;
124 - break;
125 - case IXGBE_DEV_ID_82599_VF:
126 - hw->mac.type = ixgbe_mac_82599_vf;
127 - break;
128 - case IXGBE_DEV_ID_X540_VF:
129 - hw->mac.type = ixgbe_mac_X540_vf;
130 - break;
131 - case IXGBE_DEV_ID_X540T:
132 - case IXGBE_DEV_ID_X540T1:
133 - hw->mac.type = ixgbe_mac_X540;
134 - break;
135 - default:
136 - ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
137 - break;
138 - }
139 - } else {
136 + if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) {
137 + ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
138 + "Unsupported vendor id: %x", hw->vendor_id);
139 + return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
140 + }
141 +
142 + hw->mvals = ixgbe_mvals_base;
143 +
144 + switch (hw->device_id) {
145 + case IXGBE_DEV_ID_82598:
146 + case IXGBE_DEV_ID_82598_BX:
147 + case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
148 + case IXGBE_DEV_ID_82598AF_DUAL_PORT:
149 + case IXGBE_DEV_ID_82598AT:
150 + case IXGBE_DEV_ID_82598AT2:
151 + case IXGBE_DEV_ID_82598EB_CX4:
152 + case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
153 + case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
154 + case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
155 + case IXGBE_DEV_ID_82598EB_XF_LR:
156 + case IXGBE_DEV_ID_82598EB_SFP_LOM:
157 + hw->mac.type = ixgbe_mac_82598EB;
158 + break;
159 + case IXGBE_DEV_ID_82599_KX4:
160 + case IXGBE_DEV_ID_82599_KX4_MEZZ:
161 + case IXGBE_DEV_ID_82599_XAUI_LOM:
162 + case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
163 + case IXGBE_DEV_ID_82599_KR:
164 + case IXGBE_DEV_ID_82599_SFP:
165 + case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
166 + case IXGBE_DEV_ID_82599_SFP_FCOE:
167 + case IXGBE_DEV_ID_82599_SFP_EM:
168 + case IXGBE_DEV_ID_82599_SFP_SF2:
169 + case IXGBE_DEV_ID_82599_SFP_SF_QP:
170 + case IXGBE_DEV_ID_82599_QSFP_SF_QP:
171 + case IXGBE_DEV_ID_82599EN_SFP:
172 + case IXGBE_DEV_ID_82599_CX4:
173 + case IXGBE_DEV_ID_82599_BYPASS:
174 + case IXGBE_DEV_ID_82599_T3_LOM:
175 + hw->mac.type = ixgbe_mac_82599EB;
176 + break;
177 + case IXGBE_DEV_ID_82599_VF:
178 + case IXGBE_DEV_ID_82599_VF_HV:
179 + hw->mac.type = ixgbe_mac_82599_vf;
180 + break;
181 + case IXGBE_DEV_ID_X540_VF:
182 + case IXGBE_DEV_ID_X540_VF_HV:
183 + hw->mac.type = ixgbe_mac_X540_vf;
184 + hw->mvals = ixgbe_mvals_X540;
185 + break;
186 + case IXGBE_DEV_ID_X540T:
187 + case IXGBE_DEV_ID_X540T1:
188 + case IXGBE_DEV_ID_X540_BYPASS:
189 + hw->mac.type = ixgbe_mac_X540;
190 + hw->mvals = ixgbe_mvals_X540;
191 + break;
192 + case IXGBE_DEV_ID_X550T:
193 + case IXGBE_DEV_ID_X550T1:
194 + hw->mac.type = ixgbe_mac_X550;
195 + hw->mvals = ixgbe_mvals_X550;
196 + break;
197 + case IXGBE_DEV_ID_X550EM_X_KX4:
198 + case IXGBE_DEV_ID_X550EM_X_KR:
199 + case IXGBE_DEV_ID_X550EM_X_10G_T:
200 + case IXGBE_DEV_ID_X550EM_X_1G_T:
201 + case IXGBE_DEV_ID_X550EM_X_SFP:
202 + hw->mac.type = ixgbe_mac_X550EM_x;
203 + hw->mvals = ixgbe_mvals_X550EM_x;
204 + break;
205 + case IXGBE_DEV_ID_X550_VF:
206 + case IXGBE_DEV_ID_X550_VF_HV:
207 + hw->mac.type = ixgbe_mac_X550_vf;
208 + hw->mvals = ixgbe_mvals_X550;
209 + break;
210 + case IXGBE_DEV_ID_X550EM_X_VF:
211 + case IXGBE_DEV_ID_X550EM_X_VF_HV:
212 + hw->mac.type = ixgbe_mac_X550EM_x_vf;
213 + hw->mvals = ixgbe_mvals_X550EM_x;
214 + break;
215 + default:
140 216 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
217 + ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
218 + "Unsupported device id: %x",
219 + hw->device_id);
220 + break;
141 221 }
142 222
143 223 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
144 224 hw->mac.type, ret_val);
145 225 return ret_val;
146 226 }
147 227
148 228 /**
149 229 * ixgbe_init_hw - Initialize the hardware
150 230 * @hw: pointer to hardware structure
151 231 *
152 232 * Initialize the hardware by resetting and then starting the hardware
153 233 **/
154 234 s32 ixgbe_init_hw(struct ixgbe_hw *hw)
155 235 {
156 236 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
157 237 IXGBE_NOT_IMPLEMENTED);
158 238 }
159 239
160 240 /**
161 241 * ixgbe_reset_hw - Performs a hardware reset
162 242 * @hw: pointer to hardware structure
163 243 *
164 244 * Resets the hardware by resetting the transmit and receive units, masks and
165 245 * clears all interrupts, performs a PHY reset, and performs a MAC reset
166 246 **/
167 247 s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
168 248 {
169 249 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
170 250 IXGBE_NOT_IMPLEMENTED);
171 251 }
172 252
173 253 /**
174 254 * ixgbe_start_hw - Prepares hardware for Rx/Tx
175 255 * @hw: pointer to hardware structure
176 256 *
177 257 * Starts the hardware by filling the bus info structure and media type,
178 258 * clears all on chip counters, initializes receive address registers,
179 259 * multicast table, VLAN filter table, calls routine to setup link and
180 260 * flow control settings, and leaves transmit and receive units disabled
181 261 * and uninitialized.
182 262 **/
183 263 s32 ixgbe_start_hw(struct ixgbe_hw *hw)
184 264 {
185 265 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
186 266 IXGBE_NOT_IMPLEMENTED);
187 267 }
188 268
189 269 /**
190 270 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
191 271 * which is disabled by default in ixgbe_start_hw();
192 272 *
193 273 * @hw: pointer to hardware structure
194 274 *
195 275 * Enable relaxed ordering;
196 276 **/
197 277 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
198 278 {
199 279 if (hw->mac.ops.enable_relaxed_ordering)
200 280 hw->mac.ops.enable_relaxed_ordering(hw);
201 281 }
202 282
203 283 /**
204 284 * ixgbe_clear_hw_cntrs - Clear hardware counters
205 285 * @hw: pointer to hardware structure
206 286 *
207 287 * Clears all hardware statistics counters by reading them from the hardware
208 288 * Statistics counters are clear on read.
209 289 **/
210 290 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
211 291 {
212 292 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
213 293 IXGBE_NOT_IMPLEMENTED);
214 294 }
215 295
216 296 /**
217 297 * ixgbe_get_media_type - Get media type
218 298 * @hw: pointer to hardware structure
219 299 *
220 300 * Returns the media type (fiber, copper, backplane)
221 301 **/
222 302 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
223 303 {
224 304 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
225 305 ixgbe_media_type_unknown);
226 306 }
227 307
228 308 /**
229 309 * ixgbe_get_mac_addr - Get MAC address
230 310 * @hw: pointer to hardware structure
231 311 * @mac_addr: Adapter MAC address
232 312 *
233 313 * Reads the adapter's MAC address from the first Receive Address Register
234 314 * (RAR0) A reset of the adapter must have been performed prior to calling
235 315 * this function in order for the MAC address to have been loaded from the
236 316 * EEPROM into RAR0
237 317 **/
238 318 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
239 319 {
240 320 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
241 321 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
242 322 }
243 323
244 324 /**
245 325 * ixgbe_get_san_mac_addr - Get SAN MAC address
246 326 * @hw: pointer to hardware structure
247 327 * @san_mac_addr: SAN MAC address
248 328 *
249 329 * Reads the SAN MAC address from the EEPROM, if it's available. This is
250 330 * per-port, so set_lan_id() must be called before reading the addresses.
251 331 **/
252 332 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
253 333 {
254 334 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
255 335 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
256 336 }
257 337
258 338 /**
259 339 * ixgbe_set_san_mac_addr - Write a SAN MAC address
260 340 * @hw: pointer to hardware structure
261 341 * @san_mac_addr: SAN MAC address
262 342 *
263 343 * Writes A SAN MAC address to the EEPROM.
264 344 **/
265 345 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
266 346 {
267 347 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
268 348 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
269 349 }
270 350
271 351 /**
272 352 * ixgbe_get_device_caps - Get additional device capabilities
273 353 * @hw: pointer to hardware structure
274 354 * @device_caps: the EEPROM word for device capabilities
275 355 *
276 356 * Reads the extra device capabilities from the EEPROM
277 357 **/
278 358 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
279 359 {
280 360 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
281 361 (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
282 362 }
283 363
284 364 /**
285 365 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
286 366 * @hw: pointer to hardware structure
287 367 * @wwnn_prefix: the alternative WWNN prefix
288 368 * @wwpn_prefix: the alternative WWPN prefix
289 369 *
290 370 * This function will read the EEPROM from the alternative SAN MAC address
291 371 * block to check the support for the alternative WWNN/WWPN prefix support.
292 372 **/
293 373 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
294 374 u16 *wwpn_prefix)
295 375 {
296 376 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
297 377 (hw, wwnn_prefix, wwpn_prefix),
298 378 IXGBE_NOT_IMPLEMENTED);
299 379 }
300 380
301 381 /**
302 382 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM
303 383 * @hw: pointer to hardware structure
304 384 * @bs: the fcoe boot status
305 385 *
306 386 * This function will read the FCOE boot status from the iSCSI FCOE block
307 387 **/
308 388 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
309 389 {
310 390 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
311 391 (hw, bs),
312 392 IXGBE_NOT_IMPLEMENTED);
313 393 }
314 394
315 395 /**
316 396 * ixgbe_get_bus_info - Set PCI bus info
317 397 * @hw: pointer to hardware structure
318 398 *
319 399 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
320 400 **/
321 401 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
322 402 {
323 403 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
324 404 IXGBE_NOT_IMPLEMENTED);
325 405 }
326 406
327 407 /**
328 408 * ixgbe_get_num_of_tx_queues - Get Tx queues
329 409 * @hw: pointer to hardware structure
330 410 *
331 411 * Returns the number of transmit queues for the given adapter.
332 412 **/
333 413 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
334 414 {
335 415 return hw->mac.max_tx_queues;
336 416 }
337 417
338 418 /**
339 419 * ixgbe_get_num_of_rx_queues - Get Rx queues
340 420 * @hw: pointer to hardware structure
341 421 *
342 422 * Returns the number of receive queues for the given adapter.
343 423 **/
344 424 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
345 425 {
346 426 return hw->mac.max_rx_queues;
347 427 }
348 428
349 429 /**
350 430 * ixgbe_stop_adapter - Disable Rx/Tx units
351 431 * @hw: pointer to hardware structure
352 432 *
353 433 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
354 434 * disables transmit and receive units. The adapter_stopped flag is used by
355 435 * the shared code and drivers to determine if the adapter is in a stopped
356 436 * state and should not touch the hardware.
357 437 **/
358 438 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
359 439 {
360 440 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
361 441 IXGBE_NOT_IMPLEMENTED);
362 442 }
363 443
364 444 /**
365 445 * ixgbe_read_pba_string - Reads part number string from EEPROM
366 446 * @hw: pointer to hardware structure
367 447 * @pba_num: stores the part number string from the EEPROM
368 448 * @pba_num_size: part number string buffer length
369 449 *
370 450 * Reads the part number string from the EEPROM.
371 451 **/
372 452 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
373 453 {
374 454 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
375 455 }
376 456
377 457 /**
378 458 * ixgbe_read_pba_num - Reads part number from EEPROM
379 459 * @hw: pointer to hardware structure
380 460 * @pba_num: stores the part number from the EEPROM
381 461 *
382 462 * Reads the part number from the EEPROM.
383 463 **/
384 464 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
385 465 {
386 466 return ixgbe_read_pba_num_generic(hw, pba_num);
387 467 }
388 468
389 469 /**
390 470 * ixgbe_identify_phy - Get PHY type
391 471 * @hw: pointer to hardware structure
392 472 *
393 473 * Determines the physical layer module found on the current adapter.
394 474 **/
395 475 s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
396 476 {
397 477 s32 status = IXGBE_SUCCESS;
398 478
399 479 if (hw->phy.type == ixgbe_phy_unknown) {
400 480 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
401 481 IXGBE_NOT_IMPLEMENTED);
402 482 }
403 483
404 484 return status;
405 485 }
406 486
407 487 /**
408 488 * ixgbe_reset_phy - Perform a PHY reset
409 489 * @hw: pointer to hardware structure
410 490 **/
411 491 s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
412 492 {
413 493 s32 status = IXGBE_SUCCESS;
414 494
415 495 if (hw->phy.type == ixgbe_phy_unknown) {
416 496 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
417 497 status = IXGBE_ERR_PHY;
418 498 }
419 499
420 500 if (status == IXGBE_SUCCESS) {
421 501 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
422 502 IXGBE_NOT_IMPLEMENTED);
423 503 }
424 504 return status;
425 505 }
426 506
427 507 /**
428 508 * ixgbe_get_phy_firmware_version -
429 509 * @hw: pointer to hardware structure
430 510 * @firmware_version: pointer to firmware version
431 511 **/
432 512 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
433 513 {
434 514 s32 status = IXGBE_SUCCESS;
435 515
436 516 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
437 517 (hw, firmware_version),
438 518 IXGBE_NOT_IMPLEMENTED);
439 519 return status;
440 520 }
441 521
442 522 /**
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443 523 * ixgbe_read_phy_reg - Read PHY register
444 524 * @hw: pointer to hardware structure
445 525 * @reg_addr: 32 bit address of PHY register to read
446 526 * @phy_data: Pointer to read data from PHY register
447 527 *
448 528 * Reads a value from a specified PHY register
449 529 **/
450 530 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
451 531 u16 *phy_data)
452 532 {
453 - s32 status;
454 -
455 533 if (hw->phy.id == 0)
456 - status = ixgbe_identify_phy(hw);
457 - else
458 - status = IXGBE_SUCCESS;
534 + ixgbe_identify_phy(hw);
459 535
460 - if (status == IXGBE_SUCCESS) {
461 - status = ixgbe_call_func(hw, hw->phy.ops.read_reg,
462 - (hw, reg_addr, device_type, phy_data),
463 - IXGBE_NOT_IMPLEMENTED);
464 - }
465 - return (status);
536 + return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
537 + device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
466 538 }
467 539
468 540 /**
469 541 * ixgbe_write_phy_reg - Write PHY register
470 542 * @hw: pointer to hardware structure
471 543 * @reg_addr: 32 bit PHY register to write
472 544 * @phy_data: Data to write to the PHY register
473 545 *
474 546 * Writes a value to specified PHY register
475 547 **/
476 548 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
477 549 u16 phy_data)
478 550 {
479 - s32 status;
480 -
481 551 if (hw->phy.id == 0)
482 - status = ixgbe_identify_phy(hw);
483 - else
484 - status = IXGBE_SUCCESS;
552 + ixgbe_identify_phy(hw);
485 553
486 - if (status == IXGBE_SUCCESS) {
487 - status = ixgbe_call_func(hw, hw->phy.ops.write_reg,
488 - (hw, reg_addr, device_type, phy_data),
489 - IXGBE_NOT_IMPLEMENTED);
490 - }
491 -
492 - return status;
554 + return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
555 + device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
493 556 }
494 557
495 558 /**
496 559 * ixgbe_setup_phy_link - Restart PHY autoneg
497 560 * @hw: pointer to hardware structure
498 561 *
499 562 * Restart autonegotiation and PHY and waits for completion.
500 563 **/
501 564 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
502 565 {
503 566 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
504 567 IXGBE_NOT_IMPLEMENTED);
505 568 }
506 569
507 570 /**
571 + * ixgbe_setup_internal_phy - Configure integrated PHY
572 + * @hw: pointer to hardware structure
573 + *
574 + * Reconfigure the integrated PHY in order to enable talk to the external PHY.
575 + * Returns success if not implemented, since nothing needs to be done in this
576 + * case.
577 + */
578 +s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
579 +{
580 + return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),
581 + IXGBE_SUCCESS);
582 +}
583 +
584 +/**
508 585 * ixgbe_check_phy_link - Determine link and speed status
509 586 * @hw: pointer to hardware structure
510 587 *
511 588 * Reads a PHY register to determine if link is up and the current speed for
512 589 * the PHY.
513 590 **/
514 591 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
515 592 bool *link_up)
516 593 {
517 594 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
518 595 link_up), IXGBE_NOT_IMPLEMENTED);
519 596 }
520 597
521 598 /**
522 599 * ixgbe_setup_phy_link_speed - Set auto advertise
523 600 * @hw: pointer to hardware structure
524 601 * @speed: new link speed
525 - * @autoneg: TRUE if autonegotiation enabled
526 602 *
527 603 * Sets the auto advertised capabilities
528 604 **/
529 605 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
530 - bool autoneg,
531 606 bool autoneg_wait_to_complete)
532 607 {
533 608 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
534 - autoneg, autoneg_wait_to_complete),
609 + autoneg_wait_to_complete),
535 610 IXGBE_NOT_IMPLEMENTED);
536 611 }
537 612
538 613 /**
614 + * ixgbe_set_phy_power - Control the phy power state
615 + * @hw: pointer to hardware structure
616 + * @on: TRUE for on, FALSE for off
617 + */
618 +s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on)
619 +{
620 + return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on),
621 + IXGBE_NOT_IMPLEMENTED);
622 +}
623 +
624 +/**
539 625 * ixgbe_check_link - Get link and speed status
540 626 * @hw: pointer to hardware structure
541 627 *
542 628 * Reads the links register to determine if link is up and the current speed
543 629 **/
544 630 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
545 631 bool *link_up, bool link_up_wait_to_complete)
546 632 {
547 633 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
548 634 link_up, link_up_wait_to_complete),
549 635 IXGBE_NOT_IMPLEMENTED);
550 636 }
551 637
552 638 /**
553 639 * ixgbe_disable_tx_laser - Disable Tx laser
554 640 * @hw: pointer to hardware structure
555 641 *
556 642 * If the driver needs to disable the laser on SFI optics.
557 643 **/
558 644 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
559 645 {
560 646 if (hw->mac.ops.disable_tx_laser)
561 647 hw->mac.ops.disable_tx_laser(hw);
562 648 }
563 649
564 650 /**
565 651 * ixgbe_enable_tx_laser - Enable Tx laser
566 652 * @hw: pointer to hardware structure
567 653 *
568 654 * If the driver needs to enable the laser on SFI optics.
569 655 **/
570 656 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
571 657 {
572 658 if (hw->mac.ops.enable_tx_laser)
573 659 hw->mac.ops.enable_tx_laser(hw);
574 660 }
575 661
576 662 /**
577 663 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
578 664 * @hw: pointer to hardware structure
579 665 *
580 666 * When the driver changes the link speeds that it can support then
581 667 * flap the tx laser to alert the link partner to start autotry
582 668 * process on its end.
583 669 **/
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584 670 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
585 671 {
586 672 if (hw->mac.ops.flap_tx_laser)
587 673 hw->mac.ops.flap_tx_laser(hw);
588 674 }
589 675
590 676 /**
591 677 * ixgbe_setup_link - Set link speed
592 678 * @hw: pointer to hardware structure
593 679 * @speed: new link speed
594 - * @autoneg: TRUE if autonegotiation enabled
595 680 *
596 681 * Configures link settings. Restarts the link.
597 682 * Performs autonegotiation if needed.
598 683 **/
599 684 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
600 - bool autoneg,
601 685 bool autoneg_wait_to_complete)
602 686 {
603 687 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
604 - autoneg, autoneg_wait_to_complete),
688 + autoneg_wait_to_complete),
605 689 IXGBE_NOT_IMPLEMENTED);
606 690 }
607 691
608 692 /**
693 + * ixgbe_setup_mac_link - Set link speed
694 + * @hw: pointer to hardware structure
695 + * @speed: new link speed
696 + *
697 + * Configures link settings. Restarts the link.
698 + * Performs autonegotiation if needed.
699 + **/
700 +s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
701 + bool autoneg_wait_to_complete)
702 +{
703 + return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed,
704 + autoneg_wait_to_complete),
705 + IXGBE_NOT_IMPLEMENTED);
706 +}
707 +
708 +/**
609 709 * ixgbe_get_link_capabilities - Returns link capabilities
610 710 * @hw: pointer to hardware structure
611 711 *
612 712 * Determines the link capabilities of the current configuration.
613 713 **/
614 714 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
615 715 bool *autoneg)
616 716 {
617 717 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
618 718 speed, autoneg), IXGBE_NOT_IMPLEMENTED);
619 719 }
620 720
621 721 /**
622 722 * ixgbe_led_on - Turn on LEDs
623 723 * @hw: pointer to hardware structure
624 724 * @index: led number to turn on
625 725 *
626 726 * Turns on the software controllable LEDs.
627 727 **/
628 728 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
629 729 {
630 730 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
631 731 IXGBE_NOT_IMPLEMENTED);
632 732 }
633 733
634 734 /**
635 735 * ixgbe_led_off - Turn off LEDs
636 736 * @hw: pointer to hardware structure
637 737 * @index: led number to turn off
638 738 *
639 739 * Turns off the software controllable LEDs.
640 740 **/
641 741 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
642 742 {
643 743 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
644 744 IXGBE_NOT_IMPLEMENTED);
645 745 }
646 746
647 747 /**
648 748 * ixgbe_blink_led_start - Blink LEDs
649 749 * @hw: pointer to hardware structure
650 750 * @index: led number to blink
651 751 *
652 752 * Blink LED based on index.
653 753 **/
654 754 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
655 755 {
656 756 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
657 757 IXGBE_NOT_IMPLEMENTED);
658 758 }
659 759
660 760 /**
661 761 * ixgbe_blink_led_stop - Stop blinking LEDs
662 762 * @hw: pointer to hardware structure
663 763 *
664 764 * Stop blinking LED based on index.
665 765 **/
666 766 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
667 767 {
668 768 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
669 769 IXGBE_NOT_IMPLEMENTED);
670 770 }
671 771
672 772 /**
673 773 * ixgbe_init_eeprom_params - Initialize EEPROM parameters
674 774 * @hw: pointer to hardware structure
675 775 *
676 776 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
677 777 * ixgbe_hw struct in order to set up EEPROM access.
678 778 **/
679 779 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
680 780 {
681 781 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
682 782 IXGBE_NOT_IMPLEMENTED);
683 783 }
684 784
685 785
686 786 /**
687 787 * ixgbe_write_eeprom - Write word to EEPROM
688 788 * @hw: pointer to hardware structure
689 789 * @offset: offset within the EEPROM to be written to
690 790 * @data: 16 bit word to be written to the EEPROM
691 791 *
692 792 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
693 793 * called after this function, the EEPROM will most likely contain an
694 794 * invalid checksum.
695 795 **/
696 796 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
697 797 {
698 798 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
699 799 IXGBE_NOT_IMPLEMENTED);
700 800 }
701 801
702 802 /**
703 803 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
704 804 * @hw: pointer to hardware structure
705 805 * @offset: offset within the EEPROM to be written to
706 806 * @data: 16 bit word(s) to be written to the EEPROM
707 807 * @words: number of words
708 808 *
709 809 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
710 810 * called after this function, the EEPROM will most likely contain an
711 811 * invalid checksum.
712 812 **/
713 813 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
714 814 u16 *data)
715 815 {
716 816 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
717 817 (hw, offset, words, data),
718 818 IXGBE_NOT_IMPLEMENTED);
719 819 }
720 820
721 821 /**
722 822 * ixgbe_read_eeprom - Read word from EEPROM
723 823 * @hw: pointer to hardware structure
724 824 * @offset: offset within the EEPROM to be read
725 825 * @data: read 16 bit value from EEPROM
726 826 *
727 827 * Reads 16 bit value from EEPROM
728 828 **/
729 829 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
730 830 {
731 831 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
732 832 IXGBE_NOT_IMPLEMENTED);
733 833 }
734 834
735 835 /**
736 836 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
737 837 * @hw: pointer to hardware structure
738 838 * @offset: offset within the EEPROM to be read
739 839 * @data: read 16 bit word(s) from EEPROM
740 840 * @words: number of words
741 841 *
742 842 * Reads 16 bit word(s) from EEPROM
743 843 **/
744 844 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
745 845 u16 words, u16 *data)
746 846 {
747 847 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
748 848 (hw, offset, words, data),
749 849 IXGBE_NOT_IMPLEMENTED);
750 850 }
751 851
752 852 /**
753 853 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
754 854 * @hw: pointer to hardware structure
755 855 * @checksum_val: calculated checksum
756 856 *
757 857 * Performs checksum calculation and validates the EEPROM checksum
758 858 **/
759 859 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
760 860 {
761 861 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
762 862 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
763 863 }
764 864
765 865 /**
766 866 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
767 867 * @hw: pointer to hardware structure
768 868 **/
769 869 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
770 870 {
771 871 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
772 872 IXGBE_NOT_IMPLEMENTED);
773 873 }
774 874
775 875 /**
776 876 * ixgbe_insert_mac_addr - Find a RAR for this mac address
777 877 * @hw: pointer to hardware structure
778 878 * @addr: Address to put into receive address register
779 879 * @vmdq: VMDq pool to assign
780 880 *
781 881 * Puts an ethernet address into a receive address register, or
782 882 * finds the rar that it is aleady in; adds to the pool list
783 883 **/
784 884 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
785 885 {
786 886 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
787 887 (hw, addr, vmdq),
788 888 IXGBE_NOT_IMPLEMENTED);
789 889 }
790 890
791 891 /**
792 892 * ixgbe_set_rar - Set Rx address register
793 893 * @hw: pointer to hardware structure
794 894 * @index: Receive address register to write
795 895 * @addr: Address to put into receive address register
796 896 * @vmdq: VMDq "set"
797 897 * @enable_addr: set flag that address is active
798 898 *
799 899 * Puts an ethernet address into a receive address register.
800 900 **/
801 901 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
802 902 u32 enable_addr)
803 903 {
804 904 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
805 905 enable_addr), IXGBE_NOT_IMPLEMENTED);
806 906 }
807 907
808 908 /**
809 909 * ixgbe_clear_rar - Clear Rx address register
810 910 * @hw: pointer to hardware structure
811 911 * @index: Receive address register to write
812 912 *
813 913 * Puts an ethernet address into a receive address register.
814 914 **/
815 915 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
816 916 {
817 917 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
818 918 IXGBE_NOT_IMPLEMENTED);
819 919 }
820 920
821 921 /**
822 922 * ixgbe_set_vmdq - Associate a VMDq index with a receive address
823 923 * @hw: pointer to hardware structure
824 924 * @rar: receive address register index to associate with VMDq index
825 925 * @vmdq: VMDq set or pool index
826 926 **/
827 927 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
828 928 {
829 929 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
830 930 IXGBE_NOT_IMPLEMENTED);
831 931
832 932 }
833 933
834 934 /**
835 935 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
836 936 * @hw: pointer to hardware structure
837 937 * @vmdq: VMDq default pool index
838 938 **/
839 939 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
840 940 {
841 941 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
842 942 (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
843 943 }
844 944
845 945 /**
846 946 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
847 947 * @hw: pointer to hardware structure
848 948 * @rar: receive address register index to disassociate with VMDq index
849 949 * @vmdq: VMDq set or pool index
850 950 **/
851 951 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
852 952 {
853 953 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
854 954 IXGBE_NOT_IMPLEMENTED);
855 955 }
856 956
857 957 /**
858 958 * ixgbe_init_rx_addrs - Initializes receive address filters.
859 959 * @hw: pointer to hardware structure
860 960 *
861 961 * Places the MAC address in receive address register 0 and clears the rest
862 962 * of the receive address registers. Clears the multicast table. Assumes
863 963 * the receiver is in reset when the routine is called.
864 964 **/
865 965 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
866 966 {
867 967 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
868 968 IXGBE_NOT_IMPLEMENTED);
869 969 }
870 970
871 971 /**
872 972 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
873 973 * @hw: pointer to hardware structure
874 974 **/
875 975 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
876 976 {
877 977 return hw->mac.num_rar_entries;
878 978 }
879 979
880 980 /**
881 981 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
882 982 * @hw: pointer to hardware structure
883 983 * @addr_list: the list of new multicast addresses
884 984 * @addr_count: number of addresses
885 985 * @func: iterator function to walk the multicast address list
886 986 *
887 987 * The given list replaces any existing list. Clears the secondary addrs from
888 988 * receive address registers. Uses unused receive address registers for the
889 989 * first secondary addresses, and falls back to promiscuous mode as needed.
890 990 **/
891 991 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
892 992 u32 addr_count, ixgbe_mc_addr_itr func)
893 993 {
894 994 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
895 995 addr_list, addr_count, func),
896 996 IXGBE_NOT_IMPLEMENTED);
897 997 }
898 998
899 999 /**
900 1000 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
901 1001 * @hw: pointer to hardware structure
902 1002 * @mc_addr_list: the list of new multicast addresses
903 1003 * @mc_addr_count: number of addresses
904 1004 * @func: iterator function to walk the multicast address list
905 1005 *
906 1006 * The given list replaces any existing list. Clears the MC addrs from receive
907 1007 * address registers and the multicast table. Uses unused receive address
908 1008 * registers for the first multicast addresses, and hashes the rest into the
909 1009 * multicast table.
910 1010 **/
911 1011 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
912 1012 u32 mc_addr_count, ixgbe_mc_addr_itr func,
913 1013 bool clear)
914 1014 {
915 1015 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
916 1016 mc_addr_list, mc_addr_count, func, clear),
917 1017 IXGBE_NOT_IMPLEMENTED);
918 1018 }
919 1019
920 1020 /**
921 1021 * ixgbe_enable_mc - Enable multicast address in RAR
922 1022 * @hw: pointer to hardware structure
923 1023 *
924 1024 * Enables multicast address in RAR and the use of the multicast hash table.
925 1025 **/
926 1026 s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
927 1027 {
928 1028 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
929 1029 IXGBE_NOT_IMPLEMENTED);
930 1030 }
931 1031
932 1032 /**
933 1033 * ixgbe_disable_mc - Disable multicast address in RAR
934 1034 * @hw: pointer to hardware structure
935 1035 *
936 1036 * Disables multicast address in RAR and the use of the multicast hash table.
937 1037 **/
938 1038 s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
939 1039 {
940 1040 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
941 1041 IXGBE_NOT_IMPLEMENTED);
942 1042 }
943 1043
944 1044 /**
945 1045 * ixgbe_clear_vfta - Clear VLAN filter table
946 1046 * @hw: pointer to hardware structure
947 1047 *
948 1048 * Clears the VLAN filer table, and the VMDq index associated with the filter
949 1049 **/
950 1050 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
951 1051 {
952 1052 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
953 1053 IXGBE_NOT_IMPLEMENTED);
954 1054 }
955 1055
956 1056 /**
957 1057 * ixgbe_set_vfta - Set VLAN filter table
958 1058 * @hw: pointer to hardware structure
959 1059 * @vlan: VLAN id to write to VLAN filter
960 1060 * @vind: VMDq output index that maps queue to VLAN id in VFTA
961 1061 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
962 1062 *
963 1063 * Turn on/off specified VLAN in the VLAN filter table.
964 1064 **/
965 1065 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
966 1066 {
967 1067 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
968 1068 vlan_on), IXGBE_NOT_IMPLEMENTED);
969 1069 }
970 1070
971 1071 /**
972 1072 * ixgbe_set_vlvf - Set VLAN Pool Filter
973 1073 * @hw: pointer to hardware structure
974 1074 * @vlan: VLAN id to write to VLAN filter
975 1075 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
976 1076 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
977 1077 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
978 1078 * should be changed
979 1079 *
980 1080 * Turn on/off specified bit in VLVF table.
981 1081 **/
982 1082 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
983 1083 bool *vfta_changed)
984 1084 {
985 1085 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
986 1086 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
987 1087 }
988 1088
989 1089 /**
990 1090 * ixgbe_fc_enable - Enable flow control
991 1091 * @hw: pointer to hardware structure
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992 1092 *
993 1093 * Configures the flow control settings based on SW configuration.
994 1094 **/
995 1095 s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
996 1096 {
997 1097 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
998 1098 IXGBE_NOT_IMPLEMENTED);
999 1099 }
1000 1100
1001 1101 /**
1102 + * ixgbe_setup_fc - Set up flow control
1103 + * @hw: pointer to hardware structure
1104 + *
1105 + * Called at init time to set up flow control.
1106 + **/
1107 +s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
1108 +{
1109 + return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw),
1110 + IXGBE_NOT_IMPLEMENTED);
1111 +}
1112 +
1113 +/**
1002 1114 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1003 1115 * @hw: pointer to hardware structure
1004 1116 * @maj: driver major number to be sent to firmware
1005 1117 * @min: driver minor number to be sent to firmware
1006 1118 * @build: driver build number to be sent to firmware
1007 1119 * @ver: driver version number to be sent to firmware
1008 1120 **/
1009 1121 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1010 1122 u8 ver)
1011 1123 {
1012 1124 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1013 1125 build, ver), IXGBE_NOT_IMPLEMENTED);
1014 1126 }
1015 1127
1016 1128
1129 +
1017 1130 /**
1131 + * ixgbe_dmac_config - Configure DMA Coalescing registers.
1132 + * @hw: pointer to hardware structure
1133 + *
1134 + * Configure DMA coalescing. If enabling dmac, dmac is activated.
1135 + * When disabling dmac, dmac enable dmac bit is cleared.
1136 + **/
1137 +s32 ixgbe_dmac_config(struct ixgbe_hw *hw)
1138 +{
1139 + return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw),
1140 + IXGBE_NOT_IMPLEMENTED);
1141 +}
1142 +
1143 +/**
1144 + * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.
1145 + * @hw: pointer to hardware structure
1146 + *
1147 + * Disables dmac, updates per TC settings, and then enable dmac.
1148 + **/
1149 +s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)
1150 +{
1151 + return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw),
1152 + IXGBE_NOT_IMPLEMENTED);
1153 +}
1154 +
1155 +/**
1156 + * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.
1157 + * @hw: pointer to hardware structure
1158 + *
1159 + * Configure DMA coalescing threshold per TC and set high priority bit for
1160 + * FCOE TC. The dmac enable bit must be cleared before configuring.
1161 + **/
1162 +s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)
1163 +{
1164 + return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw),
1165 + IXGBE_NOT_IMPLEMENTED);
1166 +}
1167 +
1168 +/**
1169 + * ixgbe_setup_eee - Enable/disable EEE support
1170 + * @hw: pointer to the HW structure
1171 + * @enable_eee: boolean flag to enable EEE
1172 + *
1173 + * Enable/disable EEE based on enable_ee flag.
1174 + * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1175 + * are modified.
1176 + *
1177 + **/
1178 +s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee)
1179 +{
1180 + return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee),
1181 + IXGBE_NOT_IMPLEMENTED);
1182 +}
1183 +
1184 +/**
1185 + * ixgbe_set_source_address_pruning - Enable/Disable source address pruning
1186 + * @hw: pointer to hardware structure
1187 + * @enbale: enable or disable source address pruning
1188 + * @pool: Rx pool - Rx pool to toggle source address pruning
1189 + **/
1190 +void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
1191 + unsigned int pool)
1192 +{
1193 + if (hw->mac.ops.set_source_address_pruning)
1194 + hw->mac.ops.set_source_address_pruning(hw, enable, pool);
1195 +}
1196 +
1197 +/**
1198 + * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing
1199 + * @hw: pointer to hardware structure
1200 + * @enable: enable or disable switch for Ethertype anti-spoofing
1201 + * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1202 + *
1203 + **/
1204 +void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
1205 +{
1206 + if (hw->mac.ops.set_ethertype_anti_spoofing)
1207 + hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);
1208 +}
1209 +
1210 +/**
1211 + * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register
1212 + * @hw: pointer to hardware structure
1213 + * @reg_addr: 32 bit address of PHY register to read
1214 + * @device_type: type of device you want to communicate with
1215 + * @phy_data: Pointer to read data from PHY register
1216 + *
1217 + * Reads a value from a specified PHY register
1218 + **/
1219 +s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
1220 + u32 device_type, u32 *phy_data)
1221 +{
1222 + return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,
1223 + device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
1224 +}
1225 +
1226 +/**
1227 + * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband
1228 + * @hw: pointer to hardware structure
1229 + * @reg_addr: 32 bit PHY register to write
1230 + * @device_type: type of device you want to communicate with
1231 + * @phy_data: Data to write to the PHY register
1232 + *
1233 + * Writes a value to specified PHY register
1234 + **/
1235 +s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
1236 + u32 device_type, u32 phy_data)
1237 +{
1238 + return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,
1239 + device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
1240 +}
1241 +
1242 +/**
1243 + * ixgbe_disable_mdd - Disable malicious driver detection
1244 + * @hw: pointer to hardware structure
1245 + *
1246 + **/
1247 +void ixgbe_disable_mdd(struct ixgbe_hw *hw)
1248 +{
1249 + if (hw->mac.ops.disable_mdd)
1250 + hw->mac.ops.disable_mdd(hw);
1251 +}
1252 +
1253 +/**
1254 + * ixgbe_enable_mdd - Enable malicious driver detection
1255 + * @hw: pointer to hardware structure
1256 + *
1257 + **/
1258 +void ixgbe_enable_mdd(struct ixgbe_hw *hw)
1259 +{
1260 + if (hw->mac.ops.enable_mdd)
1261 + hw->mac.ops.enable_mdd(hw);
1262 +}
1263 +
1264 +/**
1265 + * ixgbe_mdd_event - Handle malicious driver detection event
1266 + * @hw: pointer to hardware structure
1267 + * @vf_bitmap: vf bitmap of malicious vfs
1268 + *
1269 + **/
1270 +void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)
1271 +{
1272 + if (hw->mac.ops.mdd_event)
1273 + hw->mac.ops.mdd_event(hw, vf_bitmap);
1274 +}
1275 +
1276 +/**
1277 + * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver
1278 + * detection event
1279 + * @hw: pointer to hardware structure
1280 + * @vf: vf index
1281 + *
1282 + **/
1283 +void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)
1284 +{
1285 + if (hw->mac.ops.restore_mdd_vf)
1286 + hw->mac.ops.restore_mdd_vf(hw, vf);
1287 +}
1288 +
1289 +/**
1290 + * ixgbe_enter_lplu - Transition to low power states
1291 + * @hw: pointer to hardware structure
1292 + *
1293 + * Configures Low Power Link Up on transition to low power states
1294 + * (from D0 to non-D0).
1295 + **/
1296 +s32 ixgbe_enter_lplu(struct ixgbe_hw *hw)
1297 +{
1298 + return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw),
1299 + IXGBE_NOT_IMPLEMENTED);
1300 +}
1301 +
1302 +/**
1303 + * ixgbe_handle_lasi - Handle external Base T PHY interrupt
1304 + * @hw: pointer to hardware structure
1305 + *
1306 + * Handle external Base T PHY interrupt. If high temperature
1307 + * failure alarm then return error, else if link status change
1308 + * then setup internal/external PHY link
1309 + *
1310 + * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1311 + * failure alarm, else return PHY access status.
1312 + */
1313 +s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)
1314 +{
1315 + return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),
1316 + IXGBE_NOT_IMPLEMENTED);
1317 +}
1318 +
1319 +/**
1018 1320 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1019 1321 * @hw: pointer to hardware structure
1020 1322 * @reg: analog register to read
1021 1323 * @val: read value
1022 1324 *
1023 1325 * Performs write operation to analog register specified.
1024 1326 **/
1025 1327 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1026 1328 {
1027 1329 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
1028 1330 val), IXGBE_NOT_IMPLEMENTED);
1029 1331 }
1030 1332
1031 1333 /**
1032 1334 * ixgbe_write_analog_reg8 - Writes 8 bit analog register
1033 1335 * @hw: pointer to hardware structure
1034 1336 * @reg: analog register to write
1035 1337 * @val: value to write
1036 1338 *
1037 1339 * Performs write operation to Atlas analog register specified.
1038 1340 **/
1039 1341 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
1040 1342 {
1041 1343 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
1042 1344 val), IXGBE_NOT_IMPLEMENTED);
1043 1345 }
1044 1346
1045 1347 /**
1046 1348 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
1047 1349 * @hw: pointer to hardware structure
1048 1350 *
1049 1351 * Initializes the Unicast Table Arrays to zero on device load. This
1050 1352 * is part of the Rx init addr execution path.
1051 1353 **/
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1052 1354 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
1053 1355 {
1054 1356 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
1055 1357 IXGBE_NOT_IMPLEMENTED);
1056 1358 }
1057 1359
1058 1360 /**
1059 1361 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
1060 1362 * @hw: pointer to hardware structure
1061 1363 * @byte_offset: byte offset to read
1364 + * @dev_addr: I2C bus address to read from
1062 1365 * @data: value read
1063 1366 *
1064 1367 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1065 1368 **/
1066 1369 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1067 1370 u8 *data)
1068 1371 {
1069 1372 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
1070 1373 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1071 1374 }
1072 1375
1073 1376 /**
1377 + * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address
1378 + * @hw: pointer to hardware structure
1379 + * @byte_offset: byte offset to read
1380 + * @dev_addr: I2C bus address to read from
1381 + * @data: value read
1382 + *
1383 + * Performs byte read operation to SFP module's EEPROM over I2C interface.
1384 + **/
1385 +s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1386 + u8 dev_addr, u8 *data)
1387 +{
1388 + return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,
1389 + (hw, byte_offset, dev_addr, data),
1390 + IXGBE_NOT_IMPLEMENTED);
1391 +}
1392 +
1393 +/**
1394 + * ixgbe_read_i2c_combined - Perform I2C read combined operation
1395 + * @hw: pointer to the hardware structure
1396 + * @addr: I2C bus address to read from
1397 + * @reg: I2C device register to read from
1398 + * @val: pointer to location to receive read value
1399 + *
1400 + * Returns an error code on error.
1401 + */
1402 +s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
1403 +{
1404 + return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr,
1405 + reg, val), IXGBE_NOT_IMPLEMENTED);
1406 +}
1407 +
1408 +/**
1409 + * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation
1410 + * @hw: pointer to the hardware structure
1411 + * @addr: I2C bus address to read from
1412 + * @reg: I2C device register to read from
1413 + * @val: pointer to location to receive read value
1414 + *
1415 + * Returns an error code on error.
1416 + **/
1417 +s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,
1418 + u16 *val)
1419 +{
1420 + return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked,
1421 + (hw, addr, reg, val),
1422 + IXGBE_NOT_IMPLEMENTED);
1423 +}
1424 +
1425 +/**
1074 1426 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1075 1427 * @hw: pointer to hardware structure
1076 1428 * @byte_offset: byte offset to write
1429 + * @dev_addr: I2C bus address to write to
1077 1430 * @data: value to write
1078 1431 *
1079 1432 * Performs byte write operation to SFP module's EEPROM over I2C interface
1080 1433 * at a specified device address.
1081 1434 **/
1082 1435 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1083 1436 u8 data)
1084 1437 {
1085 1438 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
1086 1439 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1087 1440 }
1088 1441
1089 1442 /**
1443 + * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1444 + * @hw: pointer to hardware structure
1445 + * @byte_offset: byte offset to write
1446 + * @dev_addr: I2C bus address to write to
1447 + * @data: value to write
1448 + *
1449 + * Performs byte write operation to SFP module's EEPROM over I2C interface
1450 + * at a specified device address.
1451 + **/
1452 +s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1453 + u8 dev_addr, u8 data)
1454 +{
1455 + return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,
1456 + (hw, byte_offset, dev_addr, data),
1457 + IXGBE_NOT_IMPLEMENTED);
1458 +}
1459 +
1460 +/**
1461 + * ixgbe_write_i2c_combined - Perform I2C write combined operation
1462 + * @hw: pointer to the hardware structure
1463 + * @addr: I2C bus address to write to
1464 + * @reg: I2C device register to write to
1465 + * @val: value to write
1466 + *
1467 + * Returns an error code on error.
1468 + */
1469 +s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
1470 +{
1471 + return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr,
1472 + reg, val), IXGBE_NOT_IMPLEMENTED);
1473 +}
1474 +
1475 +/**
1476 + * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation
1477 + * @hw: pointer to the hardware structure
1478 + * @addr: I2C bus address to write to
1479 + * @reg: I2C device register to write to
1480 + * @val: value to write
1481 + *
1482 + * Returns an error code on error.
1483 + **/
1484 +s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,
1485 + u16 val)
1486 +{
1487 + return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked,
1488 + (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1489 +}
1490 +
1491 +/**
1090 1492 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1091 1493 * @hw: pointer to hardware structure
1092 1494 * @byte_offset: EEPROM byte offset to write
1093 1495 * @eeprom_data: value to write
1094 1496 *
1095 1497 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1096 1498 **/
1097 1499 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1098 1500 u8 byte_offset, u8 eeprom_data)
1099 1501 {
1100 1502 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1101 1503 (hw, byte_offset, eeprom_data),
1102 1504 IXGBE_NOT_IMPLEMENTED);
1103 1505 }
1104 1506
1105 1507 /**
1106 1508 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1107 1509 * @hw: pointer to hardware structure
1108 1510 * @byte_offset: EEPROM byte offset to read
1109 1511 * @eeprom_data: value read
1110 1512 *
1111 1513 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1112 1514 **/
1113 1515 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
1114 1516 {
1115 1517 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
1116 1518 (hw, byte_offset, eeprom_data),
1117 1519 IXGBE_NOT_IMPLEMENTED);
1118 1520 }
1119 1521
1120 1522 /**
1121 1523 * ixgbe_get_supported_physical_layer - Returns physical layer type
1122 1524 * @hw: pointer to hardware structure
1123 1525 *
1124 1526 * Determines physical layer capabilities of the current configuration.
1125 1527 **/
1126 1528 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1127 1529 {
1128 1530 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1129 1531 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1130 1532 }
1131 1533
1132 1534 /**
1133 1535 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1134 1536 * @hw: pointer to hardware structure
1135 1537 * @regval: bitfield to write to the Rx DMA register
1136 1538 *
1137 1539 * Enables the Rx DMA unit of the device.
1138 1540 **/
1139 1541 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
1140 1542 {
1141 1543 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
1142 1544 (hw, regval), IXGBE_NOT_IMPLEMENTED);
1143 1545 }
1144 1546
1145 1547 /**
1146 1548 * ixgbe_disable_sec_rx_path - Stops the receive data path
1147 1549 * @hw: pointer to hardware structure
1148 1550 *
1149 1551 * Stops the receive data path.
1150 1552 **/
1151 1553 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
1152 1554 {
1153 1555 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
1154 1556 (hw), IXGBE_NOT_IMPLEMENTED);
1155 1557 }
1156 1558
1157 1559 /**
1158 1560 * ixgbe_enable_sec_rx_path - Enables the receive data path
1159 1561 * @hw: pointer to hardware structure
1160 1562 *
1161 1563 * Enables the receive data path.
1162 1564 **/
1163 1565 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1164 1566 {
1165 1567 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1166 1568 (hw), IXGBE_NOT_IMPLEMENTED);
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1167 1569 }
1168 1570
1169 1571 /**
1170 1572 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1171 1573 * @hw: pointer to hardware structure
1172 1574 * @mask: Mask to specify which semaphore to acquire
1173 1575 *
1174 1576 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1175 1577 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1176 1578 **/
1177 -s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1579 +s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1178 1580 {
1179 1581 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1180 1582 (hw, mask), IXGBE_NOT_IMPLEMENTED);
1181 1583 }
1182 1584
1183 1585 /**
1184 1586 * ixgbe_release_swfw_semaphore - Release SWFW semaphore
1185 1587 * @hw: pointer to hardware structure
1186 1588 * @mask: Mask to specify which semaphore to release
1187 1589 *
1188 1590 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1189 1591 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1190 1592 **/
1191 -void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1593 +void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1192 1594 {
1193 1595 if (hw->mac.ops.release_swfw_sync)
1194 1596 hw->mac.ops.release_swfw_sync(hw, mask);
1195 1597 }
1196 1598
1599 +
1600 +void ixgbe_disable_rx(struct ixgbe_hw *hw)
1601 +{
1602 + if (hw->mac.ops.disable_rx)
1603 + hw->mac.ops.disable_rx(hw);
1604 +}
1605 +
1606 +void ixgbe_enable_rx(struct ixgbe_hw *hw)
1607 +{
1608 + if (hw->mac.ops.enable_rx)
1609 + hw->mac.ops.enable_rx(hw);
1610 +}
1611 +
1612 +/**
1613 + * ixgbe_set_rate_select_speed - Set module link speed
1614 + * @hw: pointer to hardware structure
1615 + * @speed: link speed to set
1616 + *
1617 + * Set module link speed via the rate select.
1618 + */
1619 +void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
1620 +{
1621 + if (hw->mac.ops.set_rate_select_speed)
1622 + hw->mac.ops.set_rate_select_speed(hw, speed);
1623 +}
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