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6064 ixgbe needs X550 support

*** 1,8 **** /****************************************************************************** ! Copyright (c) 2001-2012, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: --- 1,8 ---- /****************************************************************************** ! Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
*** 28,43 **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ ! /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/ #include "ixgbe_api.h" #include "ixgbe_common.h" /** * ixgbe_init_shared_code - Initialize the shared code * @hw: pointer to hardware structure * * This will assign function pointers and assign the MAC type and PHY code. * Does not touch the hardware. This function must be called prior to any --- 28,74 ---- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ ! /*$FreeBSD$*/ #include "ixgbe_api.h" #include "ixgbe_common.h" + #define IXGBE_EMPTY_PARAM + + static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { + IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) + }; + + static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { + IXGBE_MVALS_INIT(_X540) + }; + + static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { + IXGBE_MVALS_INIT(_X550) + }; + + static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { + IXGBE_MVALS_INIT(_X550EM_x) + }; + /** + * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg + * @hw: pointer to hardware structure + * @map: pointer to u8 arr for returning map + * + * Read the rtrup2tc HW register and resolve its content into map + **/ + void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) + { + if (hw->mac.ops.get_rtrup2tc) + hw->mac.ops.get_rtrup2tc(hw, map); + } + + /** * ixgbe_init_shared_code - Initialize the shared code * @hw: pointer to hardware structure * * This will assign function pointers and assign the MAC type and PHY code. * Does not touch the hardware. This function must be called prior to any
*** 54,66 **** DEBUGFUNC("ixgbe_init_shared_code"); /* * Set the mac type */ ! status = ixgbe_set_mac_type(hw); ! if (status != IXGBE_SUCCESS) ! return (status); switch (hw->mac.type) { case ixgbe_mac_82598EB: status = ixgbe_init_ops_82598(hw); break; --- 85,95 ---- DEBUGFUNC("ixgbe_init_shared_code"); /* * Set the mac type */ ! ixgbe_set_mac_type(hw); switch (hw->mac.type) { case ixgbe_mac_82598EB: status = ixgbe_init_ops_82598(hw); break;
*** 68,81 **** --- 97,123 ---- status = ixgbe_init_ops_82599(hw); break; case ixgbe_mac_X540: status = ixgbe_init_ops_X540(hw); break; + case ixgbe_mac_X550: + status = ixgbe_init_ops_X550(hw); + break; + case ixgbe_mac_X550EM_x: + status = ixgbe_init_ops_X550EM(hw); + break; + case ixgbe_mac_82599_vf: + case ixgbe_mac_X540_vf: + case ixgbe_mac_X550_vf: + case ixgbe_mac_X550EM_x_vf: + status = ixgbe_init_ops_vf(hw); + break; default: status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; break; } + hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; return status; } /**
*** 89,99 **** { s32 ret_val = IXGBE_SUCCESS; DEBUGFUNC("ixgbe_set_mac_type\n"); ! if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { switch (hw->device_id) { case IXGBE_DEV_ID_82598: case IXGBE_DEV_ID_82598_BX: case IXGBE_DEV_ID_82598AF_SINGLE_PORT: case IXGBE_DEV_ID_82598AF_DUAL_PORT: --- 131,148 ---- { s32 ret_val = IXGBE_SUCCESS; DEBUGFUNC("ixgbe_set_mac_type\n"); ! if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { ! ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, ! "Unsupported vendor id: %x", hw->vendor_id); ! return IXGBE_ERR_DEVICE_NOT_SUPPORTED; ! } ! ! hw->mvals = ixgbe_mvals_base; ! switch (hw->device_id) { case IXGBE_DEV_ID_82598: case IXGBE_DEV_ID_82598_BX: case IXGBE_DEV_ID_82598AF_SINGLE_PORT: case IXGBE_DEV_ID_82598AF_DUAL_PORT:
*** 115,146 **** case IXGBE_DEV_ID_82599_SFP: case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: case IXGBE_DEV_ID_82599_SFP_FCOE: case IXGBE_DEV_ID_82599_SFP_EM: case IXGBE_DEV_ID_82599_SFP_SF2: case IXGBE_DEV_ID_82599EN_SFP: case IXGBE_DEV_ID_82599_CX4: case IXGBE_DEV_ID_82599_T3_LOM: hw->mac.type = ixgbe_mac_82599EB; break; case IXGBE_DEV_ID_82599_VF: hw->mac.type = ixgbe_mac_82599_vf; break; case IXGBE_DEV_ID_X540_VF: hw->mac.type = ixgbe_mac_X540_vf; break; case IXGBE_DEV_ID_X540T: case IXGBE_DEV_ID_X540T1: hw->mac.type = ixgbe_mac_X540; break; default: ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; break; } - } else { - ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; - } DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", hw->mac.type, ret_val); return ret_val; } --- 164,226 ---- case IXGBE_DEV_ID_82599_SFP: case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: case IXGBE_DEV_ID_82599_SFP_FCOE: case IXGBE_DEV_ID_82599_SFP_EM: case IXGBE_DEV_ID_82599_SFP_SF2: + case IXGBE_DEV_ID_82599_SFP_SF_QP: + case IXGBE_DEV_ID_82599_QSFP_SF_QP: case IXGBE_DEV_ID_82599EN_SFP: case IXGBE_DEV_ID_82599_CX4: + case IXGBE_DEV_ID_82599_BYPASS: case IXGBE_DEV_ID_82599_T3_LOM: hw->mac.type = ixgbe_mac_82599EB; break; case IXGBE_DEV_ID_82599_VF: + case IXGBE_DEV_ID_82599_VF_HV: hw->mac.type = ixgbe_mac_82599_vf; break; case IXGBE_DEV_ID_X540_VF: + case IXGBE_DEV_ID_X540_VF_HV: hw->mac.type = ixgbe_mac_X540_vf; + hw->mvals = ixgbe_mvals_X540; break; case IXGBE_DEV_ID_X540T: case IXGBE_DEV_ID_X540T1: + case IXGBE_DEV_ID_X540_BYPASS: hw->mac.type = ixgbe_mac_X540; + hw->mvals = ixgbe_mvals_X540; break; + case IXGBE_DEV_ID_X550T: + case IXGBE_DEV_ID_X550T1: + hw->mac.type = ixgbe_mac_X550; + hw->mvals = ixgbe_mvals_X550; + break; + case IXGBE_DEV_ID_X550EM_X_KX4: + case IXGBE_DEV_ID_X550EM_X_KR: + case IXGBE_DEV_ID_X550EM_X_10G_T: + case IXGBE_DEV_ID_X550EM_X_1G_T: + case IXGBE_DEV_ID_X550EM_X_SFP: + hw->mac.type = ixgbe_mac_X550EM_x; + hw->mvals = ixgbe_mvals_X550EM_x; + break; + case IXGBE_DEV_ID_X550_VF: + case IXGBE_DEV_ID_X550_VF_HV: + hw->mac.type = ixgbe_mac_X550_vf; + hw->mvals = ixgbe_mvals_X550; + break; + case IXGBE_DEV_ID_X550EM_X_VF: + case IXGBE_DEV_ID_X550EM_X_VF_HV: + hw->mac.type = ixgbe_mac_X550EM_x_vf; + hw->mvals = ixgbe_mvals_X550EM_x; + break; default: ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; + ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, + "Unsupported device id: %x", + hw->device_id); break; } DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", hw->mac.type, ret_val); return ret_val; }
*** 448,470 **** * Reads a value from a specified PHY register **/ s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) { - s32 status; - if (hw->phy.id == 0) ! status = ixgbe_identify_phy(hw); ! else ! status = IXGBE_SUCCESS; ! if (status == IXGBE_SUCCESS) { ! status = ixgbe_call_func(hw, hw->phy.ops.read_reg, ! (hw, reg_addr, device_type, phy_data), ! IXGBE_NOT_IMPLEMENTED); ! } ! return (status); } /** * ixgbe_write_phy_reg - Write PHY register * @hw: pointer to hardware structure --- 528,542 ---- * Reads a value from a specified PHY register **/ s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) { if (hw->phy.id == 0) ! ixgbe_identify_phy(hw); ! return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, ! device_type, phy_data), IXGBE_NOT_IMPLEMENTED); } /** * ixgbe_write_phy_reg - Write PHY register * @hw: pointer to hardware structure
*** 474,497 **** * Writes a value to specified PHY register **/ s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data) { - s32 status; - if (hw->phy.id == 0) ! status = ixgbe_identify_phy(hw); ! else ! status = IXGBE_SUCCESS; ! if (status == IXGBE_SUCCESS) { ! status = ixgbe_call_func(hw, hw->phy.ops.write_reg, ! (hw, reg_addr, device_type, phy_data), ! IXGBE_NOT_IMPLEMENTED); ! } ! ! return status; } /** * ixgbe_setup_phy_link - Restart PHY autoneg * @hw: pointer to hardware structure --- 546,560 ---- * Writes a value to specified PHY register **/ s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data) { if (hw->phy.id == 0) ! ixgbe_identify_phy(hw); ! return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, ! device_type, phy_data), IXGBE_NOT_IMPLEMENTED); } /** * ixgbe_setup_phy_link - Restart PHY autoneg * @hw: pointer to hardware structure
*** 503,512 **** --- 566,589 ---- return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), IXGBE_NOT_IMPLEMENTED); } /** + * ixgbe_setup_internal_phy - Configure integrated PHY + * @hw: pointer to hardware structure + * + * Reconfigure the integrated PHY in order to enable talk to the external PHY. + * Returns success if not implemented, since nothing needs to be done in this + * case. + */ + s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) + { + return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), + IXGBE_SUCCESS); + } + + /** * ixgbe_check_phy_link - Determine link and speed status * @hw: pointer to hardware structure * * Reads a PHY register to determine if link is up and the current speed for * the PHY.
*** 520,543 **** /** * ixgbe_setup_phy_link_speed - Set auto advertise * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled * * Sets the auto advertised capabilities **/ s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, - bool autoneg, bool autoneg_wait_to_complete) { return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, ! autoneg, autoneg_wait_to_complete), IXGBE_NOT_IMPLEMENTED); } /** * ixgbe_check_link - Get link and speed status * @hw: pointer to hardware structure * * Reads the links register to determine if link is up and the current speed **/ --- 597,629 ---- /** * ixgbe_setup_phy_link_speed - Set auto advertise * @hw: pointer to hardware structure * @speed: new link speed * * Sets the auto advertised capabilities **/ s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, ! autoneg_wait_to_complete), IXGBE_NOT_IMPLEMENTED); } /** + * ixgbe_set_phy_power - Control the phy power state + * @hw: pointer to hardware structure + * @on: TRUE for on, FALSE for off + */ + s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) + { + return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), + IXGBE_NOT_IMPLEMENTED); + } + + /** * ixgbe_check_link - Get link and speed status * @hw: pointer to hardware structure * * Reads the links register to determine if link is up and the current speed **/
*** 589,613 **** /** * ixgbe_setup_link - Set link speed * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled * * Configures link settings. Restarts the link. * Performs autonegotiation if needed. **/ s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, - bool autoneg, bool autoneg_wait_to_complete) { return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, ! autoneg, autoneg_wait_to_complete), IXGBE_NOT_IMPLEMENTED); } /** * ixgbe_get_link_capabilities - Returns link capabilities * @hw: pointer to hardware structure * * Determines the link capabilities of the current configuration. **/ --- 675,713 ---- /** * ixgbe_setup_link - Set link speed * @hw: pointer to hardware structure * @speed: new link speed * * Configures link settings. Restarts the link. * Performs autonegotiation if needed. **/ s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, ! autoneg_wait_to_complete), IXGBE_NOT_IMPLEMENTED); } /** + * ixgbe_setup_mac_link - Set link speed + * @hw: pointer to hardware structure + * @speed: new link speed + * + * Configures link settings. Restarts the link. + * Performs autonegotiation if needed. + **/ + s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, + bool autoneg_wait_to_complete) + { + return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, + autoneg_wait_to_complete), + IXGBE_NOT_IMPLEMENTED); + } + + /** * ixgbe_get_link_capabilities - Returns link capabilities * @hw: pointer to hardware structure * * Determines the link capabilities of the current configuration. **/
*** 997,1006 **** --- 1097,1118 ---- return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), IXGBE_NOT_IMPLEMENTED); } /** + * ixgbe_setup_fc - Set up flow control + * @hw: pointer to hardware structure + * + * Called at init time to set up flow control. + **/ + s32 ixgbe_setup_fc(struct ixgbe_hw *hw) + { + return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), + IXGBE_NOT_IMPLEMENTED); + } + + /** * ixgbe_set_fw_drv_ver - Try to send the driver version number FW * @hw: pointer to hardware structure * @maj: driver major number to be sent to firmware * @min: driver minor number to be sent to firmware * @build: driver build number to be sent to firmware
*** 1012,1022 **** --- 1124,1324 ---- return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, build, ver), IXGBE_NOT_IMPLEMENTED); } + /** + * ixgbe_dmac_config - Configure DMA Coalescing registers. + * @hw: pointer to hardware structure + * + * Configure DMA coalescing. If enabling dmac, dmac is activated. + * When disabling dmac, dmac enable dmac bit is cleared. + **/ + s32 ixgbe_dmac_config(struct ixgbe_hw *hw) + { + return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), + IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. + * @hw: pointer to hardware structure + * + * Disables dmac, updates per TC settings, and then enable dmac. + **/ + s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) + { + return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), + IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. + * @hw: pointer to hardware structure + * + * Configure DMA coalescing threshold per TC and set high priority bit for + * FCOE TC. The dmac enable bit must be cleared before configuring. + **/ + s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) + { + return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), + IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_setup_eee - Enable/disable EEE support + * @hw: pointer to the HW structure + * @enable_eee: boolean flag to enable EEE + * + * Enable/disable EEE based on enable_ee flag. + * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C + * are modified. + * + **/ + s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) + { + return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), + IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_set_source_address_pruning - Enable/Disable source address pruning + * @hw: pointer to hardware structure + * @enbale: enable or disable source address pruning + * @pool: Rx pool - Rx pool to toggle source address pruning + **/ + void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, + unsigned int pool) + { + if (hw->mac.ops.set_source_address_pruning) + hw->mac.ops.set_source_address_pruning(hw, enable, pool); + } + + /** + * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing + * @hw: pointer to hardware structure + * @enable: enable or disable switch for Ethertype anti-spoofing + * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing + * + **/ + void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) + { + if (hw->mac.ops.set_ethertype_anti_spoofing) + hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); + } + + /** + * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register + * @hw: pointer to hardware structure + * @reg_addr: 32 bit address of PHY register to read + * @device_type: type of device you want to communicate with + * @phy_data: Pointer to read data from PHY register + * + * Reads a value from a specified PHY register + **/ + s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, + u32 device_type, u32 *phy_data) + { + return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, + device_type, phy_data), IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband + * @hw: pointer to hardware structure + * @reg_addr: 32 bit PHY register to write + * @device_type: type of device you want to communicate with + * @phy_data: Data to write to the PHY register + * + * Writes a value to specified PHY register + **/ + s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, + u32 device_type, u32 phy_data) + { + return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, + device_type, phy_data), IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_disable_mdd - Disable malicious driver detection + * @hw: pointer to hardware structure + * + **/ + void ixgbe_disable_mdd(struct ixgbe_hw *hw) + { + if (hw->mac.ops.disable_mdd) + hw->mac.ops.disable_mdd(hw); + } + + /** + * ixgbe_enable_mdd - Enable malicious driver detection + * @hw: pointer to hardware structure + * + **/ + void ixgbe_enable_mdd(struct ixgbe_hw *hw) + { + if (hw->mac.ops.enable_mdd) + hw->mac.ops.enable_mdd(hw); + } + + /** + * ixgbe_mdd_event - Handle malicious driver detection event + * @hw: pointer to hardware structure + * @vf_bitmap: vf bitmap of malicious vfs + * + **/ + void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) + { + if (hw->mac.ops.mdd_event) + hw->mac.ops.mdd_event(hw, vf_bitmap); + } + + /** + * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver + * detection event + * @hw: pointer to hardware structure + * @vf: vf index + * + **/ + void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) + { + if (hw->mac.ops.restore_mdd_vf) + hw->mac.ops.restore_mdd_vf(hw, vf); + } + + /** + * ixgbe_enter_lplu - Transition to low power states + * @hw: pointer to hardware structure + * + * Configures Low Power Link Up on transition to low power states + * (from D0 to non-D0). + **/ + s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) + { + return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), + IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_handle_lasi - Handle external Base T PHY interrupt + * @hw: pointer to hardware structure + * + * Handle external Base T PHY interrupt. If high temperature + * failure alarm then return error, else if link status change + * then setup internal/external PHY link + * + * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature + * failure alarm, else return PHY access status. + */ + s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) + { + return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), + IXGBE_NOT_IMPLEMENTED); + } + + /** * ixgbe_read_analog_reg8 - Reads 8 bit analog register * @hw: pointer to hardware structure * @reg: analog register to read * @val: read value *
*** 1057,1066 **** --- 1359,1369 ---- /** * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address * @hw: pointer to hardware structure * @byte_offset: byte offset to read + * @dev_addr: I2C bus address to read from * @data: value read * * Performs byte read operation to SFP module's EEPROM over I2C interface. **/ s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
*** 1069,1081 **** --- 1372,1434 ---- return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, dev_addr, data), IXGBE_NOT_IMPLEMENTED); } /** + * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address + * @hw: pointer to hardware structure + * @byte_offset: byte offset to read + * @dev_addr: I2C bus address to read from + * @data: value read + * + * Performs byte read operation to SFP module's EEPROM over I2C interface. + **/ + s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, + u8 dev_addr, u8 *data) + { + return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, + (hw, byte_offset, dev_addr, data), + IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_read_i2c_combined - Perform I2C read combined operation + * @hw: pointer to the hardware structure + * @addr: I2C bus address to read from + * @reg: I2C device register to read from + * @val: pointer to location to receive read value + * + * Returns an error code on error. + */ + s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) + { + return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr, + reg, val), IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation + * @hw: pointer to the hardware structure + * @addr: I2C bus address to read from + * @reg: I2C device register to read from + * @val: pointer to location to receive read value + * + * Returns an error code on error. + **/ + s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, + u16 *val) + { + return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked, + (hw, addr, reg, val), + IXGBE_NOT_IMPLEMENTED); + } + + /** * ixgbe_write_i2c_byte - Writes 8 bit word over I2C * @hw: pointer to hardware structure * @byte_offset: byte offset to write + * @dev_addr: I2C bus address to write to * @data: value to write * * Performs byte write operation to SFP module's EEPROM over I2C interface * at a specified device address. **/
*** 1085,1094 **** --- 1438,1496 ---- return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, dev_addr, data), IXGBE_NOT_IMPLEMENTED); } /** + * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C + * @hw: pointer to hardware structure + * @byte_offset: byte offset to write + * @dev_addr: I2C bus address to write to + * @data: value to write + * + * Performs byte write operation to SFP module's EEPROM over I2C interface + * at a specified device address. + **/ + s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, + u8 dev_addr, u8 data) + { + return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, + (hw, byte_offset, dev_addr, data), + IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_write_i2c_combined - Perform I2C write combined operation + * @hw: pointer to the hardware structure + * @addr: I2C bus address to write to + * @reg: I2C device register to write to + * @val: value to write + * + * Returns an error code on error. + */ + s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) + { + return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr, + reg, val), IXGBE_NOT_IMPLEMENTED); + } + + /** + * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation + * @hw: pointer to the hardware structure + * @addr: I2C bus address to write to + * @reg: I2C device register to write to + * @val: value to write + * + * Returns an error code on error. + **/ + s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, + u16 val) + { + return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked, + (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); + } + + /** * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface * @hw: pointer to hardware structure * @byte_offset: EEPROM byte offset to write * @eeprom_data: value to write *
*** 1172,1182 **** * @mask: Mask to specify which semaphore to acquire * * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified * function (CSR, PHY0, PHY1, EEPROM, Flash) **/ ! s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) { return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, (hw, mask), IXGBE_NOT_IMPLEMENTED); } --- 1574,1584 ---- * @mask: Mask to specify which semaphore to acquire * * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified * function (CSR, PHY0, PHY1, EEPROM, Flash) **/ ! s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) { return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, (hw, mask), IXGBE_NOT_IMPLEMENTED); }
*** 1186,1196 **** * @mask: Mask to specify which semaphore to release * * Releases the SWFW semaphore through SW_FW_SYNC register for the specified * function (CSR, PHY0, PHY1, EEPROM, Flash) **/ ! void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) { if (hw->mac.ops.release_swfw_sync) hw->mac.ops.release_swfw_sync(hw, mask); } --- 1588,1623 ---- * @mask: Mask to specify which semaphore to release * * Releases the SWFW semaphore through SW_FW_SYNC register for the specified * function (CSR, PHY0, PHY1, EEPROM, Flash) **/ ! void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) { if (hw->mac.ops.release_swfw_sync) hw->mac.ops.release_swfw_sync(hw, mask); } + + void ixgbe_disable_rx(struct ixgbe_hw *hw) + { + if (hw->mac.ops.disable_rx) + hw->mac.ops.disable_rx(hw); + } + + void ixgbe_enable_rx(struct ixgbe_hw *hw) + { + if (hw->mac.ops.enable_rx) + hw->mac.ops.enable_rx(hw); + } + + /** + * ixgbe_set_rate_select_speed - Set module link speed + * @hw: pointer to hardware structure + * @speed: link speed to set + * + * Set module link speed via the rate select. + */ + void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) + { + if (hw->mac.ops.set_rate_select_speed) + hw->mac.ops.set_rate_select_speed(hw, speed); + }