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6064 ixgbe needs X550 support

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          --- old/usr/src/uts/common/io/ixgbe/ixgbe_82598.c
          +++ new/usr/src/uts/common/io/ixgbe/ixgbe_82598.c
   1    1  /******************************************************************************
   2    2  
   3      -  Copyright (c) 2001-2012, Intel Corporation 
        3 +  Copyright (c) 2001-2015, Intel Corporation 
   4    4    All rights reserved.
   5    5    
   6    6    Redistribution and use in source and binary forms, with or without 
   7    7    modification, are permitted provided that the following conditions are met:
   8    8    
   9    9     1. Redistributions of source code must retain the above copyright notice, 
  10   10        this list of conditions and the following disclaimer.
  11   11    
  12   12     2. Redistributions in binary form must reproduce the above copyright 
  13   13        notice, this list of conditions and the following disclaimer in the 
↓ open down ↓ 9 lines elided ↑ open up ↑
  23   23    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
  24   24    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
  25   25    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
  26   26    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
  27   27    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
  28   28    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
  29   29    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   30    POSSIBILITY OF SUCH DAMAGE.
  31   31  
  32   32  ******************************************************************************/
  33      -/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
       33 +/*$FreeBSD$*/
  34   34  
  35   35  #include "ixgbe_type.h"
  36   36  #include "ixgbe_82598.h"
  37   37  #include "ixgbe_api.h"
  38   38  #include "ixgbe_common.h"
  39   39  #include "ixgbe_phy.h"
  40   40  
       41 +#define IXGBE_82598_MAX_TX_QUEUES 32
       42 +#define IXGBE_82598_MAX_RX_QUEUES 64
       43 +#define IXGBE_82598_RAR_ENTRIES   16
       44 +#define IXGBE_82598_MC_TBL_SIZE  128
       45 +#define IXGBE_82598_VFT_TBL_SIZE 128
       46 +#define IXGBE_82598_RX_PB_SIZE   512
       47 +
  41   48  static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
  42   49                                               ixgbe_link_speed *speed,
  43   50                                               bool *autoneg);
  44   51  static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
  45   52  static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
  46   53                                        bool autoneg_wait_to_complete);
  47   54  static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
  48   55                                        ixgbe_link_speed *speed, bool *link_up,
  49   56                                        bool link_up_wait_to_complete);
  50   57  static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
  51   58                                        ixgbe_link_speed speed,
  52      -                                      bool autoneg,
  53   59                                        bool autoneg_wait_to_complete);
  54   60  static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
  55   61                                           ixgbe_link_speed speed,
  56      -                                         bool autoneg,
  57   62                                           bool autoneg_wait_to_complete);
  58   63  static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
  59   64  static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  60   65  static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
  61   66  static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
  62   67                                    u32 headroom, int strategy);
  63      -
       68 +static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
       69 +                                        u8 *sff8472_data);
  64   70  /**
  65   71   *  ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
  66   72   *  @hw: pointer to the HW structure
  67   73   *
  68   74   *  The defaults for 82598 should be in the range of 50us to 50ms,
  69   75   *  however the hardware default for these parts is 500us to 1ms which is less
  70   76   *  than the 10ms recommended by the pci-e spec.  To address this we need to
  71   77   *  increase the value to either 10ms to 250ms for capability version 1 config,
  72   78   *  or 16ms to 55ms for version 2.
  73   79   **/
↓ open down ↓ 41 lines elided ↑ open up ↑
 115  121          struct ixgbe_mac_info *mac = &hw->mac;
 116  122          struct ixgbe_phy_info *phy = &hw->phy;
 117  123          s32 ret_val;
 118  124  
 119  125          DEBUGFUNC("ixgbe_init_ops_82598");
 120  126  
 121  127          ret_val = ixgbe_init_phy_ops_generic(hw);
 122  128          ret_val = ixgbe_init_ops_generic(hw);
 123  129  
 124  130          /* PHY */
 125      -        phy->ops.init = &ixgbe_init_phy_ops_82598;
      131 +        phy->ops.init = ixgbe_init_phy_ops_82598;
 126  132  
 127  133          /* MAC */
 128      -        mac->ops.start_hw = &ixgbe_start_hw_82598;
 129      -        mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
 130      -        mac->ops.reset_hw = &ixgbe_reset_hw_82598;
 131      -        mac->ops.get_media_type = &ixgbe_get_media_type_82598;
      134 +        mac->ops.start_hw = ixgbe_start_hw_82598;
      135 +        mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598;
      136 +        mac->ops.reset_hw = ixgbe_reset_hw_82598;
      137 +        mac->ops.get_media_type = ixgbe_get_media_type_82598;
 132  138          mac->ops.get_supported_physical_layer =
 133      -                                &ixgbe_get_supported_physical_layer_82598;
 134      -        mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
 135      -        mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
 136      -        mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
      139 +                                ixgbe_get_supported_physical_layer_82598;
      140 +        mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598;
      141 +        mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598;
      142 +        mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598;
      143 +        mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598;
 137  144  
 138  145          /* RAR, Multicast, VLAN */
 139      -        mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
 140      -        mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
 141      -        mac->ops.set_vfta = &ixgbe_set_vfta_82598;
      146 +        mac->ops.set_vmdq = ixgbe_set_vmdq_82598;
      147 +        mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598;
      148 +        mac->ops.set_vfta = ixgbe_set_vfta_82598;
 142  149          mac->ops.set_vlvf = NULL;
 143      -        mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
      150 +        mac->ops.clear_vfta = ixgbe_clear_vfta_82598;
 144  151  
 145  152          /* Flow Control */
 146      -        mac->ops.fc_enable = &ixgbe_fc_enable_82598;
      153 +        mac->ops.fc_enable = ixgbe_fc_enable_82598;
 147  154  
 148      -        mac->mcft_size          = 128;
 149      -        mac->vft_size           = 128;
 150      -        mac->num_rar_entries    = 16;
 151      -        mac->rx_pb_size         = 512;
 152      -        mac->max_tx_queues      = 32;
 153      -        mac->max_rx_queues      = 64;
      155 +        mac->mcft_size          = IXGBE_82598_MC_TBL_SIZE;
      156 +        mac->vft_size           = IXGBE_82598_VFT_TBL_SIZE;
      157 +        mac->num_rar_entries    = IXGBE_82598_RAR_ENTRIES;
      158 +        mac->rx_pb_size         = IXGBE_82598_RX_PB_SIZE;
      159 +        mac->max_rx_queues      = IXGBE_82598_MAX_RX_QUEUES;
      160 +        mac->max_tx_queues      = IXGBE_82598_MAX_TX_QUEUES;
 154  161          mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 155  162  
 156  163          /* SFP+ Module */
 157      -        phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
      164 +        phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;
      165 +        phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598;
 158  166  
 159  167          /* Link */
 160      -        mac->ops.check_link = &ixgbe_check_mac_link_82598;
 161      -        mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
      168 +        mac->ops.check_link = ixgbe_check_mac_link_82598;
      169 +        mac->ops.setup_link = ixgbe_setup_mac_link_82598;
 162  170          mac->ops.flap_tx_laser = NULL;
 163      -        mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
 164      -        mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
      171 +        mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598;
      172 +        mac->ops.setup_rxpba = ixgbe_set_rxpba_82598;
 165  173  
 166  174          /* Manageability interface */
 167  175          mac->ops.set_fw_drv_ver = NULL;
 168  176  
      177 +        mac->ops.get_rtrup2tc = NULL;
      178 +
 169  179          return ret_val;
 170  180  }
 171  181  
 172  182  /**
 173  183   *  ixgbe_init_phy_ops_82598 - PHY/SFP specific init
 174  184   *  @hw: pointer to hardware structure
 175  185   *
 176  186   *  Initialize any function pointers that were not able to be
 177  187   *  set during init_shared_code because the PHY/SFP type was
 178  188   *  not known.  Perform the SFP init if necessary.
↓ open down ↓ 6 lines elided ↑ open up ↑
 185  195          s32 ret_val = IXGBE_SUCCESS;
 186  196          u16 list_offset, data_offset;
 187  197  
 188  198          DEBUGFUNC("ixgbe_init_phy_ops_82598");
 189  199  
 190  200          /* Identify the PHY */
 191  201          phy->ops.identify(hw);
 192  202  
 193  203          /* Overwrite the link function pointers if copper PHY */
 194  204          if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 195      -                mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
      205 +                mac->ops.setup_link = ixgbe_setup_copper_link_82598;
 196  206                  mac->ops.get_link_capabilities =
 197      -                                &ixgbe_get_copper_link_capabilities_generic;
      207 +                                ixgbe_get_copper_link_capabilities_generic;
 198  208          }
 199  209  
 200  210          switch (hw->phy.type) {
 201  211          case ixgbe_phy_tn:
 202      -                phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
 203      -                phy->ops.check_link = &ixgbe_check_phy_link_tnx;
      212 +                phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
      213 +                phy->ops.check_link = ixgbe_check_phy_link_tnx;
 204  214                  phy->ops.get_firmware_version =
 205      -                                        &ixgbe_get_phy_firmware_version_tnx;
      215 +                                        ixgbe_get_phy_firmware_version_tnx;
 206  216                  break;
 207  217          case ixgbe_phy_nl:
 208      -                phy->ops.reset = &ixgbe_reset_phy_nl;
      218 +                phy->ops.reset = ixgbe_reset_phy_nl;
 209  219  
 210  220                  /* Call SFP+ identify routine to get the SFP+ module type */
 211  221                  ret_val = phy->ops.identify_sfp(hw);
 212  222                  if (ret_val != IXGBE_SUCCESS)
 213  223                          goto out;
 214  224                  else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 215  225                          ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 216  226                          goto out;
 217  227                  }
 218  228  
↓ open down ↓ 24 lines elided ↑ open up ↑
 243  253   **/
 244  254  s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
 245  255  {
 246  256          u32 regval;
 247  257          u32 i;
 248  258          s32 ret_val = IXGBE_SUCCESS;
 249  259  
 250  260          DEBUGFUNC("ixgbe_start_hw_82598");
 251  261  
 252  262          ret_val = ixgbe_start_hw_generic(hw);
      263 +        if (ret_val)
      264 +                return ret_val;
 253  265  
 254  266          /* Disable relaxed ordering */
 255  267          for (i = 0; ((i < hw->mac.max_tx_queues) &&
 256  268               (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
 257  269                  regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 258  270                  regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
 259  271                  IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
 260  272          }
 261  273  
 262  274          for (i = 0; ((i < hw->mac.max_rx_queues) &&
 263  275               (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
 264  276                  regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 265  277                  regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
 266  278                              IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
 267  279                  IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
 268  280          }
 269  281  
 270  282          /* set the completion timeout for interface */
 271      -        if (ret_val == IXGBE_SUCCESS)
 272      -                ixgbe_set_pcie_completion_timeout(hw);
      283 +        ixgbe_set_pcie_completion_timeout(hw);
 273  284  
 274  285          return ret_val;
 275  286  }
 276  287  
 277  288  /**
 278  289   *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 279  290   *  @hw: pointer to hardware structure
 280  291   *  @speed: pointer to link speed
 281  292   *  @autoneg: boolean auto-negotiation value
 282  293   *
↓ open down ↓ 210 lines elided ↑ open up ↑
 493  504                  break;
 494  505          case ixgbe_fc_full:
 495  506                  /* Flow control (both Rx and Tx) is enabled by SW override. */
 496  507                  fctrl_reg |= IXGBE_FCTRL_RFCE;
 497  508                  rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 498  509                  break;
 499  510          default:
 500  511                  DEBUGOUT("Flow control param set incorrectly\n");
 501  512                  ret_val = IXGBE_ERR_CONFIG;
 502  513                  goto out;
      514 +                break;
 503  515          }
 504  516  
 505  517          /* Set 802.3x based flow control settings. */
 506  518          fctrl_reg |= IXGBE_FCTRL_DPF;
 507  519          IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
 508  520          IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 509  521  
 510  522          /* Set up and enable Rx high/low water mark thresholds, enable XON. */
 511  523          for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 512  524                  if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
↓ open down ↓ 128 lines elided ↑ open up ↑
 641  653           * register 0xC79F.  Bit 0 set indicates link is up/ready; clear
 642  654           * indicates link down.  OxC00C is read to check that the XAUI lanes
 643  655           * are active.  Bit 0 clear indicates active; set indicates inactive.
 644  656           */
 645  657          if (hw->phy.type == ixgbe_phy_nl) {
 646  658                  hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 647  659                  hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 648  660                  hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
 649  661                                       &adapt_comp_reg);
 650  662                  if (link_up_wait_to_complete) {
 651      -                        for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
      663 +                        for (i = 0; i < hw->mac.max_link_up_time; i++) {
 652  664                                  if ((link_reg & 1) &&
 653  665                                      ((adapt_comp_reg & 1) == 0)) {
 654  666                                          *link_up = TRUE;
 655  667                                          break;
 656  668                                  } else {
 657  669                                          *link_up = FALSE;
 658  670                                  }
 659  671                                  msec_delay(100);
 660  672                                  hw->phy.ops.read_reg(hw, 0xC79F,
 661  673                                                       IXGBE_TWINAX_DEV,
↓ open down ↓ 8 lines elided ↑ open up ↑
 670  682                          else
 671  683                                  *link_up = FALSE;
 672  684                  }
 673  685  
 674  686                  if (*link_up == FALSE)
 675  687                          goto out;
 676  688          }
 677  689  
 678  690          links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 679  691          if (link_up_wait_to_complete) {
 680      -                for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
      692 +                for (i = 0; i < hw->mac.max_link_up_time; i++) {
 681  693                          if (links_reg & IXGBE_LINKS_UP) {
 682  694                                  *link_up = TRUE;
 683  695                                  break;
 684  696                          } else {
 685  697                                  *link_up = FALSE;
 686  698                          }
 687  699                          msec_delay(100);
 688  700                          links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 689  701                  }
 690  702          } else {
↓ open down ↓ 13 lines elided ↑ open up ↑
 704  716                  *link_up = FALSE;
 705  717  
 706  718  out:
 707  719          return IXGBE_SUCCESS;
 708  720  }
 709  721  
 710  722  /**
 711  723   *  ixgbe_setup_mac_link_82598 - Set MAC link speed
 712  724   *  @hw: pointer to hardware structure
 713  725   *  @speed: new link speed
 714      - *  @autoneg: TRUE if autonegotiation enabled
 715  726   *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
 716  727   *
 717  728   *  Set the link speed in the AUTOC register and restarts link.
 718  729   **/
 719  730  static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
 720      -                                      ixgbe_link_speed speed, bool autoneg,
      731 +                                      ixgbe_link_speed speed,
 721  732                                        bool autoneg_wait_to_complete)
 722  733  {
 723      -        s32 status;
      734 +        bool autoneg = FALSE;
      735 +        s32 status = IXGBE_SUCCESS;
 724  736          ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 725  737          u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 726  738          u32 autoc = curr_autoc;
 727  739          u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
 728  740  
 729  741          DEBUGFUNC("ixgbe_setup_mac_link_82598");
 730  742  
 731  743          /* Check to see if speed passed in is supported. */
 732      -        status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
 733      -        if (status != IXGBE_SUCCESS)
 734      -                return (status);
      744 +        ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
 735  745          speed &= link_capabilities;
 736  746  
 737  747          if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 738  748                  status = IXGBE_ERR_LINK_SETUP;
 739  749  
 740  750          /* Set KX4/KX support according to speed requested */
 741  751          else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 742  752                   link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 743  753                  autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 744  754                  if (speed & IXGBE_LINK_SPEED_10GB_FULL)
↓ open down ↓ 15 lines elided ↑ open up ↑
 760  770          }
 761  771  
 762  772          return status;
 763  773  }
 764  774  
 765  775  
 766  776  /**
 767  777   *  ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
 768  778   *  @hw: pointer to hardware structure
 769  779   *  @speed: new link speed
 770      - *  @autoneg: TRUE if autonegotiation enabled
 771  780   *  @autoneg_wait_to_complete: TRUE if waiting is needed to complete
 772  781   *
 773  782   *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 774  783   **/
 775  784  static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
 776  785                                           ixgbe_link_speed speed,
 777      -                                         bool autoneg,
 778  786                                           bool autoneg_wait_to_complete)
 779  787  {
 780  788          s32 status;
 781  789  
 782  790          DEBUGFUNC("ixgbe_setup_copper_link_82598");
 783  791  
 784  792          /* Setup the PHY according to input speed */
 785      -        status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
      793 +        status = hw->phy.ops.setup_link_speed(hw, speed,
 786  794                                                autoneg_wait_to_complete);
 787      -        if (status == IXGBE_SUCCESS) {
 788      -                /* Set up MAC */
 789      -                status =
 790      -                    ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
 791      -        }
      795 +        /* Set up MAC */
      796 +        ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
 792  797  
 793  798          return status;
 794  799  }
 795  800  
 796  801  /**
 797  802   *  ixgbe_reset_hw_82598 - Performs hardware reset
 798  803   *  @hw: pointer to hardware structure
 799  804   *
 800  805   *  Resets the hardware by resetting the transmit and receive units, masks and
 801  806   *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
↓ open down ↓ 297 lines elided ↑ open up ↑
1099 1104  
1100 1105          atlas_ctl = (reg << 8) | val;
1101 1106          IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1102 1107          IXGBE_WRITE_FLUSH(hw);
1103 1108          usec_delay(10);
1104 1109  
1105 1110          return IXGBE_SUCCESS;
1106 1111  }
1107 1112  
1108 1113  /**
1109      - *  ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
     1114 + *  ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
1110 1115   *  @hw: pointer to hardware structure
1111      - *  @byte_offset: EEPROM byte offset to read
     1116 + *  @dev_addr: address to read from
     1117 + *  @byte_offset: byte offset to read from dev_addr
1112 1118   *  @eeprom_data: value read
1113 1119   *
1114 1120   *  Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1115 1121   **/
1116      -s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1117      -                                u8 *eeprom_data)
     1122 +static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
     1123 +                                    u8 byte_offset, u8 *eeprom_data)
1118 1124  {
1119 1125          s32 status = IXGBE_SUCCESS;
1120 1126          u16 sfp_addr = 0;
1121 1127          u16 sfp_data = 0;
1122 1128          u16 sfp_stat = 0;
     1129 +        u16 gssr;
1123 1130          u32 i;
1124 1131  
1125      -        DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
     1132 +        DEBUGFUNC("ixgbe_read_i2c_phy_82598");
1126 1133  
     1134 +        if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
     1135 +                gssr = IXGBE_GSSR_PHY1_SM;
     1136 +        else
     1137 +                gssr = IXGBE_GSSR_PHY0_SM;
     1138 +
     1139 +        if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
     1140 +                return IXGBE_ERR_SWFW_SYNC;
     1141 +
1127 1142          if (hw->phy.type == ixgbe_phy_nl) {
1128 1143                  /*
1129 1144                   * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1130 1145                   * 0xC30D. These registers are used to talk to the SFP+
1131 1146                   * module's EEPROM through the SDA/SCL (I2C) interface.
1132 1147                   */
1133      -                sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
     1148 +                sfp_addr = (dev_addr << 8) + byte_offset;
1134 1149                  sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1135      -                hw->phy.ops.write_reg(hw,
1136      -                                      IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1137      -                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1138      -                                      sfp_addr);
     1150 +                hw->phy.ops.write_reg_mdi(hw,
     1151 +                                          IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
     1152 +                                          IXGBE_MDIO_PMA_PMD_DEV_TYPE,
     1153 +                                          sfp_addr);
1139 1154  
1140 1155                  /* Poll status */
1141 1156                  for (i = 0; i < 100; i++) {
1142      -                        hw->phy.ops.read_reg(hw,
1143      -                                             IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1144      -                                             IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1145      -                                             &sfp_stat);
     1157 +                        hw->phy.ops.read_reg_mdi(hw,
     1158 +                                                IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
     1159 +                                                IXGBE_MDIO_PMA_PMD_DEV_TYPE,
     1160 +                                                &sfp_stat);
1146 1161                          sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1147 1162                          if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1148 1163                                  break;
1149 1164                          msec_delay(10);
1150 1165                  }
1151 1166  
1152 1167                  if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1153 1168                          DEBUGOUT("EEPROM read did not pass.\n");
1154 1169                          status = IXGBE_ERR_SFP_NOT_PRESENT;
1155 1170                          goto out;
1156 1171                  }
1157 1172  
1158 1173                  /* Read data */
1159      -                hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1160      -                                     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
     1174 +                hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
     1175 +                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1161 1176  
1162 1177                  *eeprom_data = (u8)(sfp_data >> 8);
1163 1178          } else {
1164 1179                  status = IXGBE_ERR_PHY;
1165      -                goto out;
1166 1180          }
1167 1181  
1168 1182  out:
     1183 +        hw->mac.ops.release_swfw_sync(hw, gssr);
1169 1184          return status;
1170 1185  }
1171 1186  
1172 1187  /**
     1188 + *  ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
     1189 + *  @hw: pointer to hardware structure
     1190 + *  @byte_offset: EEPROM byte offset to read
     1191 + *  @eeprom_data: value read
     1192 + *
     1193 + *  Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
     1194 + **/
     1195 +s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
     1196 +                                u8 *eeprom_data)
     1197 +{
     1198 +        return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
     1199 +                                        byte_offset, eeprom_data);
     1200 +}
     1201 +
     1202 +/**
     1203 + *  ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
     1204 + *  @hw: pointer to hardware structure
     1205 + *  @byte_offset: byte offset at address 0xA2
     1206 + *  @eeprom_data: value read
     1207 + *
     1208 + *  Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
     1209 + **/
     1210 +static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
     1211 +                                        u8 *sff8472_data)
     1212 +{
     1213 +        return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
     1214 +                                        byte_offset, sff8472_data);
     1215 +}
     1216 +
     1217 +/**
1173 1218   *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1174 1219   *  @hw: pointer to hardware structure
1175 1220   *
1176 1221   *  Determines physical layer capabilities of the current configuration.
1177 1222   **/
1178 1223  u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1179 1224  {
1180 1225          u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1181 1226          u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1182 1227          u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
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1355 1400          /* Setup Rx packet buffer sizes */
1356 1401          switch (strategy) {
1357 1402          case PBA_STRATEGY_WEIGHTED:
1358 1403                  /* Setup the first four at 80KB */
1359 1404                  rxpktsize = IXGBE_RXPBSIZE_80KB;
1360 1405                  for (; i < 4; i++)
1361 1406                          IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1362 1407                  /* Setup the last four at 48KB...don't re-init i */
1363 1408                  rxpktsize = IXGBE_RXPBSIZE_48KB;
1364 1409                  /* Fall Through */
1365      -                /* FALLTHRU */
1366 1410          case PBA_STRATEGY_EQUAL:
1367 1411          default:
1368 1412                  /* Divide the remaining Rx packet buffer evenly among the TCs */
1369 1413                  for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1370 1414                          IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1371 1415                  break;
1372 1416          }
1373 1417  
1374 1418          /* Setup Tx packet buffer sizes */
1375 1419          for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1376 1420                  IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
     1421 +}
     1422 +
     1423 +/**
     1424 + *  ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit
     1425 + *  @hw: pointer to hardware structure
     1426 + *  @regval: register value to write to RXCTRL
     1427 + *
     1428 + *  Enables the Rx DMA unit
     1429 + **/
     1430 +s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)
     1431 +{
     1432 +        DEBUGFUNC("ixgbe_enable_rx_dma_82598");
     1433 +
     1434 +        IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
     1435 +
     1436 +        return IXGBE_SUCCESS;
1377 1437  }
    
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