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8659 ata: unused but set warnings with GCC 5.X
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--- old/usr/src/uts/intel/io/dktp/controller/ata/sil3xxx.c
+++ new/usr/src/uts/intel/io/dktp/controller/ata/sil3xxx.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 + *
26 + * Copyright 2017 RackTop Systems.
25 27 */
26 28 /*
27 29 * Silicon Image 3XXX controller specific processing
28 30 *
29 31 * This file may be expanded to take advantage of Silicon Image
30 32 * additional features (if applicable to specific controller model):
31 33 * 1. Virtual DMA operation
32 34 * 2. Concurrent all-channel DMA
33 35 * 3. Large Block Transfers
34 36 * 4. Watchdog Timer
35 37 * 5. Power Management
36 38 * 6. Hot Plug Support
37 39 */
38 40
39 -#pragma ident "%Z%%M% %I% %E% SMI"
40 -
41 41 #include "ata_common.h"
42 42 #include "sil3xxx.h"
43 43 #include <sys/pci.h>
44 44
45 45 int fifocntctl[] = {FIFO_CNTCTL_0, FIFO_CNTCTL_1, FIFO_CNTCTL_2, FIFO_CNTCTL_3};
46 46 int sfiscfg[] = {SFISCFG_0, SFISCFG_1, SFISCFG_2, SFISCFG_3};
47 47
48 48 /*
49 49 * Controller specific initialization
50 50 */
51 51 uint_t
52 52 sil3xxx_init_controller(dev_info_t *dip,
53 53 /* LINTED */
54 54 ushort_t vendor_id, ushort_t device_id)
55 55 {
56 56 ddi_acc_handle_t pci_conf_handle; /* pci config space handle */
57 57 uint8_t cache_lnsz, frrc = 0;
58 58 uint32_t fifo_cnt_ctl;
59 59 int ports, i;
60 60
61 -#ifdef DEBUG
62 - /* LINTED */
61 +#ifdef ATA_DEBUG
63 62 ushort_t sfiscfg_val;
64 63 #endif
65 64
66 65 /*
67 66 * Sil3114, Sil3512, Sil3112
68 67 * We want to perform this initialization only once per entire
69 68 * pciide controller (all channels)
70 69 */
71 70 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_get_parent(dip),
72 71 DDI_PROP_DONTPASS, "sil3xxx-initialized")) {
73 72 return (TRUE);
74 73 }
75 74
76 75 if (pci_config_setup(ddi_get_parent(dip), &pci_conf_handle) !=
77 76 DDI_SUCCESS) {
78 77 cmn_err(CE_WARN,
79 78 "sil3xxx_init_controller: Can't do pci_config_setup\n");
80 79 return (FALSE);
81 80 }
82 81
83 82 /*
84 83 * Sil3114/3512/3112 incorrectly change between MR and back to
85 84 * MRM for same transaction, which violates the PCI spec and can
86 85 * lead to incorrect data reads. The workaround
87 86 * is to set bits 2:0 in the FIFO count and control register so
88 87 * that its value, a multiple of 32 bytes starting at 32, not 0,
89 88 * is greater or equal to the cacheline size, a multiple of 4
90 89 * bytes. This will prevent any reads until the FIFO free space
91 90 * is greater than a cacheline size, ensuring only MRM is issued.
92 91 */
93 92
94 93 cache_lnsz = pci_config_get8(pci_conf_handle, PCI_CONF_CACHE_LINESZ);
95 94
96 95 /*
97 96 * The cache line is specified in 32-bit words, so multiply by 4
98 97 * to get bytes. Then divide by 32 bytes, the granularity of the
99 98 * FIFO control bits 2:0. Add 1 if there is any remainder to
100 99 * account for a partial 32-byte block, then subtract 1 since for
101 100 * FIFO controls bits 2:0, 0 corresponds to 32, 1 corresponds to
102 101 * 64, and so on. The calculation is expanded for clarity.
103 102 */
104 103 if (cache_lnsz != 0) {
105 104 frrc = (cache_lnsz * 4 / 32) +
106 105 (((cache_lnsz * 4) % 32) ? 1 : 0) - 1;
107 106 }
108 107
109 108 if (device_id == SIL3114_DEVICE_ID) {
110 109 ports = 4;
111 110 } else {
112 111 ports = 2;
113 112 }
114 113
115 114 /*
116 115 * The following BAR5 registers are accessed via an indirect register
117 116 * in the PCI configuration space rather than mapping BAR5.
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118 117 */
119 118 for (i = 0; i < ports; i++) {
120 119 GET_BAR5_INDIRECT(pci_conf_handle, fifocntctl[i],
121 120 fifo_cnt_ctl);
122 121 fifo_cnt_ctl = (fifo_cnt_ctl & ~0x7) | (frrc & 0x7);
123 122 PUT_BAR5_INDIRECT(pci_conf_handle, fifocntctl[i],
124 123 fifo_cnt_ctl);
125 124 /*
126 125 * Correct default setting for FIS0cfg
127 126 */
128 -#ifdef DEBUG
127 +#ifdef ATA_DEBUG
129 128 GET_BAR5_INDIRECT(pci_conf_handle, sfiscfg[i],
130 129 sfiscfg_val);
131 130 ADBG_WARN(("sil3xxx_init_controller: old val SFISCfg "
132 131 "ch%d: %x\n", i, sfiscfg_val));
133 132 #endif
134 133 PUT_BAR5_INDIRECT(pci_conf_handle, sfiscfg[i],
135 134 SFISCFG_ERRATA);
136 -#ifdef DEBUG
135 +#ifdef ATA_DEBUG
137 136 GET_BAR5_INDIRECT(pci_conf_handle, sfiscfg[i],
138 137 sfiscfg_val);
139 138 ADBG_WARN(("sil3xxx_init_controller: new val SFISCfg "
140 139 "ch%d: %x\n", i, sfiscfg_val));
141 140 #endif
142 141 }
143 142
144 143 /* Now tear down the pci config setup */
145 144 pci_config_teardown(&pci_conf_handle);
146 145
147 146 /* Create property indicating that initialization was done */
148 147 (void) ddi_prop_update_int(DDI_DEV_T_NONE, ddi_get_parent(dip),
149 148 "sil3xxx-initialized", 1);
150 149
151 150 return (TRUE);
152 151 }
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