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8659 ata: unused but set warnings with GCC 5.X
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--- old/usr/src/uts/intel/io/dktp/controller/ata/ata_common.c
+++ new/usr/src/uts/intel/io/dktp/controller/ata/ata_common.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
|
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 + *
26 + * Copyright 2017 RackTop Systems.
25 27 */
26 28
27 29 #include <sys/types.h>
28 30 #include <sys/modctl.h>
29 31 #include <sys/debug.h>
30 32 #include <sys/promif.h>
31 33 #include <sys/pci.h>
32 34 #include <sys/errno.h>
33 35 #include <sys/open.h>
34 36 #include <sys/uio.h>
35 37 #include <sys/cred.h>
36 38 #include <sys/cpu.h>
37 39 #include "ata_common.h"
38 40 #include "ata_disk.h"
39 41 #include "atapi.h"
40 42 #include "ata_blacklist.h"
41 43 #include "sil3xxx.h"
42 44
43 45 /*
44 46 * Solaris Entry Points.
45 47 */
46 48
47 49 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
48 50 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
49 51 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o,
50 52 void *a, void *v);
51 53 static uint_t ata_intr(caddr_t arg);
52 54
53 55 /*
54 56 * GHD Entry points
55 57 */
56 58
57 59 static int ata_get_status(void *hba_handle, void *intr_status);
58 60 static void ata_process_intr(void *hba_handle, void *intr_status);
59 61 static int ata_hba_start(void *handle, gcmd_t *gcmdp);
60 62 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback);
61 63 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp,
62 64 gtgt_t *gtgtp, gact_t action, int calltype);
63 65
64 66 /*
65 67 * Local Function Prototypes
66 68 */
67 69 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip,
68 70 uint_t flags, char *name, int defvalue);
69 71 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp,
70 72 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp,
71 73 int *DoneFlgp);
72 74 static void ata_destroy_controller(dev_info_t *dip);
73 75 static int ata_drive_type(uchar_t drvhd,
74 76 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1,
75 77 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2,
76 78 struct ata_id *ata_id_bufp);
77 79 static ata_ctl_t *ata_init_controller(dev_info_t *dip);
78 80 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp,
79 81 uchar_t targ, uchar_t lun);
80 82 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp,
81 83 dev_info_t *tdip);
82 84 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp);
83 85 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp);
84 86 static int ata_reset_bus(ata_ctl_t *ata_ctlp);
85 87 static int ata_setup_ioaddr(dev_info_t *dip,
86 88 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p,
87 89 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p,
88 90 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp);
89 91 static int ata_software_reset(ata_ctl_t *ata_ctlp);
90 92 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp,
91 93 ata_pkt_t *ata_pktp);
92 94 static int ata_strncmp(char *p1, char *p2, int cnt);
93 95 static void ata_uninit_drive(ata_drv_t *ata_drvp);
94 96
95 97 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags);
96 98 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp);
97 99 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *);
98 100 static int ata_spec_init_controller(dev_info_t *dip);
99 101
100 102 static void ata_init_pm(dev_info_t *);
101 103 static int ata_suspend(dev_info_t *);
102 104 static int ata_resume(dev_info_t *);
103 105 static int ata_power(dev_info_t *, int, int);
104 106 static int ata_change_power(dev_info_t *, uint8_t);
105 107 static int ata_is_pci(dev_info_t *);
106 108 static void ata_disable_DMA(ata_drv_t *ata_drvp);
107 109 static int ata_check_dma_mode(ata_drv_t *ata_drvp);
108 110
109 111 /*
110 112 * Local static data
111 113 */
112 114 static void *ata_state;
113 115
114 116 static tmr_t ata_timer_conf; /* single timeout list for all instances */
115 117 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */
116 118
117 119 int ata_hba_start_watchdog = 1000;
118 120 int ata_process_intr_watchdog = 1000;
119 121 int ata_reset_bus_watchdog = 1000;
120 122
121 123
122 124 /*
123 125 * Use local or framework power management
124 126 */
125 127
126 128 #ifdef ATA_USE_AUTOPM
127 129 #define ATA_BUSY_COMPONENT(d, c) ((void)pm_busy_component(d, c))
128 130 #define ATA_IDLE_COMPONENT(d, c) ((void)pm_idle_component(d, c))
129 131 #define ATA_RAISE_POWER(d, c, l) pm_raise_power(d, c, l)
130 132 #define ATA_LOWER_POWER(d, c, l) pm_lower_power(d, c, l)
131 133 #else
132 134 #define ATA_BUSY_COMPONENT(d, c)
133 135 #define ATA_IDLE_COMPONENT(d, c)
134 136 #define ATA_RAISE_POWER(d, c, l) ata_power(d, c, l)
135 137 #define ATA_LOWER_POWER(d, c, l) ata_power(d, c, l)
136 138 #endif
137 139 /*
138 140 * number of seconds to wait during various operations
139 141 */
140 142 int ata_flush_delay = 5 * 1000000;
141 143 uint_t ata_set_feature_wait = 4 * 1000000;
142 144 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */
143 145
144 146 /*
145 147 * Change this for SFF-8070i support. Currently SFF-8070i is
146 148 * using a field in the IDENTIFY PACKET DEVICE response which
147 149 * already seems to be in use by some vendor's drives. I suspect
148 150 * SFF will either move their laslun field or provide a reliable
149 151 * way to validate it.
150 152 */
151 153 int ata_enable_atapi_luns = FALSE;
152 154
153 155 /*
154 156 * set this to disable all DMA requests
155 157 */
156 158 int ata_dma_disabled = FALSE;
157 159
158 160 /*
159 161 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the
160 162 * "ata" or "atapi" property.
161 163 */
162 164 int ata_id_debug = FALSE;
163 165
164 166 /*
165 167 * set this to TRUE to enable logging device-capability data
166 168 */
167 169 int ata_capability_data = FALSE;
168 170
169 171 /*
170 172 * DMA selection message pointers
171 173 */
172 174 char *ata_cntrl_DMA_sel_msg;
173 175 char *ata_dev_DMA_sel_msg;
174 176
175 177 /*
176 178 * bus nexus operations
177 179 */
178 180 static struct bus_ops ata_bus_ops;
179 181 static struct bus_ops *scsa_bus_ops_p;
180 182
181 183 /* ARGSUSED */
182 184 static int
183 185 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p)
184 186 {
185 187 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL)
186 188 return (ENXIO);
187 189
188 190 return (0);
189 191 }
190 192
191 193 /*
192 194 * The purpose of this function is to pass the ioaddress of the controller
193 195 * to the caller, specifically used for upgrade from pre-pciide
194 196 * to pciide nodes
195 197 */
196 198 /* ARGSUSED */
197 199 static int
198 200 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p)
199 201 {
200 202 ata_ctl_t *ata_ctlp;
201 203 char buf[18];
202 204 long len;
203 205
204 206 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev));
205 207
206 208 if (ata_ctlp == NULL)
207 209 return (ENXIO);
208 210
209 211 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1);
210 212
211 213 len = strlen(buf) - uio_p->uio_offset;
212 214 len = min(uio_p->uio_resid, len);
213 215 if (len <= 0)
214 216 return (0);
215 217
216 218 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len,
217 219 UIO_READ, uio_p));
218 220 }
219 221
220 222 int
221 223 ata_devo_reset(
222 224 dev_info_t *dip,
223 225 ddi_reset_cmd_t cmd)
224 226 {
225 227 ata_ctl_t *ata_ctlp;
226 228 ata_drv_t *ata_drvp;
227 229 int instance;
228 230 int i;
229 231 int rc;
230 232 int flush_okay;
231 233
232 234 if (cmd != DDI_RESET_FORCE)
233 235 return (0);
234 236
235 237 instance = ddi_get_instance(dip);
236 238 ata_ctlp = ddi_get_soft_state(ata_state, instance);
237 239
238 240 if (!ata_ctlp)
239 241 return (0);
240 242
241 243 /*
242 244 * reset ATA drives and flush the write cache of any drives
243 245 */
244 246 flush_okay = TRUE;
245 247 for (i = 0; i < ATA_MAXTARG; i++) {
246 248 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0)
247 249 continue;
248 250 /* Don't revert to defaults for certain IBM drives */
249 251 if ((ata_drvp->ad_flags & AD_DISK) != 0 &&
250 252 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) {
251 253 /* Enable revert to defaults when reset */
252 254 (void) ata_set_feature(ata_ctlp, ata_drvp,
253 255 ATSF_ENA_REVPOD, 0);
254 256 }
255 257
256 258 /*
257 259 * skip flush cache if device type is cdrom
258 260 *
259 261 * notes: the structure definitions for ata_drvp->ad_id are
260 262 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set
261 263 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE
262 264 */
263 265 if (!IS_CDROM(ata_drvp)) {
264 266
265 267 /*
266 268 * Try the ATA/ATAPI flush write cache command
267 269 */
268 270 rc = ata_flush_cache(ata_ctlp, ata_drvp);
269 271 ADBG_WARN(("ata_flush_cache %s\n",
270 272 rc ? "okay" : "failed"));
271 273
272 274 if (!rc)
273 275 flush_okay = FALSE;
274 276 }
275 277
276 278
277 279 /*
278 280 * do something else if flush cache not supported
279 281 */
280 282 }
281 283
282 284 /*
283 285 * just busy wait if any drive doesn't support FLUSH CACHE
284 286 */
285 287 if (!flush_okay)
286 288 drv_usecwait(ata_flush_delay);
287 289 return (0);
288 290 }
289 291
290 292 /*
291 293 * quiesce(9E) entry point.
292 294 *
293 295 * This function is called when the system is single-threaded at high
294 296 * PIL with preemption disabled. Therefore, this function must not be
295 297 * blocked.
296 298 *
297 299 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
298 300 * DDI_FAILURE indicates an error condition and should almost never happen.
299 301 */
300 302 int
301 303 ata_quiesce(dev_info_t *dip)
302 304 {
303 305 #ifdef ATA_DEBUG
304 306 /*
305 307 * Turn off debugging
306 308 */
307 309 ata_debug = 0;
308 310 #endif
309 311
310 312 return (ata_devo_reset(dip, DDI_RESET_FORCE));
311 313 }
312 314
313 315
314 316 static struct cb_ops ata_cb_ops = {
315 317 ata_open, /* open */
316 318 nulldev, /* close */
317 319 nodev, /* strategy */
318 320 nodev, /* print */
319 321 nodev, /* dump */
320 322 ata_read, /* read */
321 323 nodev, /* write */
322 324 nodev, /* ioctl */
323 325 nodev, /* devmap */
324 326 nodev, /* mmap */
325 327 nodev, /* segmap */
326 328 nochpoll, /* chpoll */
327 329 ddi_prop_op, /* prop_op */
328 330 NULL, /* stream info */
329 331 D_MP, /* driver compatibility flag */
330 332 CB_REV, /* cb_ops revision */
331 333 nodev, /* aread */
332 334 nodev /* awrite */
333 335 };
334 336
335 337 static struct dev_ops ata_ops = {
336 338 DEVO_REV, /* devo_rev, */
337 339 0, /* refcnt */
338 340 ddi_getinfo_1to1, /* info */
339 341 nulldev, /* identify */
340 342 NULL, /* probe */
341 343 ata_attach, /* attach */
342 344 ata_detach, /* detach */
343 345 ata_devo_reset, /* reset */
344 346 &ata_cb_ops, /* driver operations */
345 347 NULL, /* bus operations */
346 348 ata_power, /* power */
347 349 ata_quiesce /* quiesce */
348 350 };
349 351
350 352 /* driver loadable module wrapper */
351 353 static struct modldrv modldrv = {
352 354 &mod_driverops, /* Type of module. This one is a driver */
353 355 "ATA AT-bus attachment disk controller Driver", /* module name */
354 356 &ata_ops, /* driver ops */
355 357 };
356 358
357 359 static struct modlinkage modlinkage = {
358 360 MODREV_1, (void *)&modldrv, NULL
359 361 };
360 362
361 363 #ifdef ATA_DEBUG
362 364 int ata_debug_init = FALSE;
363 365 int ata_debug_attach = FALSE;
364 366
365 367 int ata_debug = ADBG_FLAG_ERROR
366 368 /* | ADBG_FLAG_ARQ */
367 369 /* | ADBG_FLAG_INIT */
368 370 /* | ADBG_FLAG_TRACE */
369 371 /* | ADBG_FLAG_TRANSPORT */
370 372 /* | ADBG_FLAG_WARN */
371 373 ;
372 374 #endif
373 375
374 376 int
375 377 _init(void)
376 378 {
377 379 int err;
378 380
379 381 #ifdef ATA_DEBUG
380 382 if (ata_debug_init)
381 383 debug_enter("\nATA _INIT\n");
382 384 #endif
383 385
384 386 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0)
385 387 return (err);
386 388
387 389 if ((err = scsi_hba_init(&modlinkage)) != 0) {
388 390 ddi_soft_state_fini(&ata_state);
389 391 return (err);
390 392 }
391 393
392 394 /* save pointer to SCSA provided bus_ops struct */
393 395 scsa_bus_ops_p = ata_ops.devo_bus_ops;
394 396
395 397 /* make a copy of SCSA bus_ops */
396 398 ata_bus_ops = *(ata_ops.devo_bus_ops);
397 399
398 400 /*
399 401 * Modify our bus_ops to call our routines. Our implementation
400 402 * will determine if the device is ATA or ATAPI/SCSA and react
401 403 * accordingly.
402 404 */
403 405 ata_bus_ops.bus_ctl = ata_bus_ctl;
404 406
405 407 /* patch our bus_ops into the dev_ops struct */
406 408 ata_ops.devo_bus_ops = &ata_bus_ops;
407 409
408 410 if ((err = mod_install(&modlinkage)) != 0) {
409 411 scsi_hba_fini(&modlinkage);
410 412 ddi_soft_state_fini(&ata_state);
411 413 }
412 414
413 415 /*
414 416 * Initialize the per driver timer info.
415 417 */
416 418
417 419 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec));
418 420
419 421 return (err);
420 422 }
421 423
422 424 int
423 425 _fini(void)
424 426 {
425 427 int err;
426 428
427 429 if ((err = mod_remove(&modlinkage)) == 0) {
428 430 ghd_timer_fini(&ata_timer_conf);
429 431 scsi_hba_fini(&modlinkage);
430 432 ddi_soft_state_fini(&ata_state);
431 433 }
432 434
433 435 return (err);
434 436 }
435 437
436 438 int
437 439 _info(struct modinfo *modinfop)
438 440 {
439 441 return (mod_info(&modlinkage, modinfop));
440 442 }
441 443
442 444
443 445 /*
444 446 *
445 447 * driver attach entry point
446 448 *
447 449 */
448 450
449 451 static int
450 452 ata_attach(
451 453 dev_info_t *dip,
452 454 ddi_attach_cmd_t cmd)
453 455 {
454 456 ata_ctl_t *ata_ctlp;
455 457 ata_drv_t *ata_drvp;
456 458 ata_drv_t *first_drvp = NULL;
457 459 uchar_t targ;
458 460 uchar_t lun;
459 461 uchar_t lastlun;
460 462 int atapi_count = 0;
461 463 int disk_count = 0;
462 464
463 465 ADBG_TRACE(("ata_attach entered\n"));
464 466 #ifdef ATA_DEBUG
465 467 if (ata_debug_attach)
466 468 debug_enter("\nATA_ATTACH\n\n");
467 469 #endif
468 470
469 471 switch (cmd) {
470 472 case DDI_ATTACH:
471 473 break;
472 474 case DDI_RESUME:
473 475 return (ata_resume(dip));
474 476 default:
475 477 return (DDI_FAILURE);
476 478 }
477 479
478 480 /* initialize controller */
479 481 ata_ctlp = ata_init_controller(dip);
480 482
481 483 if (ata_ctlp == NULL)
482 484 goto errout;
483 485
484 486 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex);
485 487
486 488 /* initialize drives */
487 489
488 490 for (targ = 0; targ < ATA_MAXTARG; targ++) {
489 491
490 492 ata_drvp = ata_init_drive(ata_ctlp, targ, 0);
491 493 if (ata_drvp == NULL)
492 494 continue;
493 495
494 496 if (first_drvp == NULL)
495 497 first_drvp = ata_drvp;
496 498
497 499 if (ATAPIDRV(ata_drvp)) {
498 500 atapi_count++;
499 501 lastlun = ata_drvp->ad_id.ai_lastlun;
500 502 } else {
501 503 disk_count++;
502 504 lastlun = 0;
503 505 }
504 506
505 507 /*
506 508 * LUN support is currently disabled. Check with SFF-8070i
507 509 * before enabling.
508 510 */
509 511 if (!ata_enable_atapi_luns)
510 512 lastlun = 0;
511 513
512 514 /* Initialize higher LUNs, if there are any */
513 515 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) {
514 516 if ((ata_drvp =
515 517 ata_init_drive(ata_ctlp, targ, lun)) != NULL) {
516 518 ata_show_transfer_mode(ata_ctlp, ata_drvp);
517 519 }
518 520 }
519 521 }
520 522
521 523 if ((atapi_count == 0) && (disk_count == 0)) {
522 524 ADBG_WARN(("ata_attach: no drives detected\n"));
523 525 goto errout1;
524 526 }
525 527
526 528 /*
527 529 * Always make certain that a valid drive is selected so
528 530 * that routines which poll the status register don't get
529 531 * confused by non-existent drives.
530 532 */
531 533 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd,
532 534 first_drvp->ad_drive_bits);
533 535 ata_nsecwait(400);
534 536
535 537 /*
536 538 * make certain the drive selected
537 539 */
538 540 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2,
539 541 0, ATS_BSY, 5000000)) {
540 542 ADBG_ERROR(("ata_attach: select failed\n"));
541 543 }
542 544
543 545 /*
544 546 * initialize atapi/ata_dsk modules if we have at least
545 547 * one drive of that type.
546 548 */
547 549
548 550 if (atapi_count) {
549 551 if (!atapi_attach(ata_ctlp))
550 552 goto errout1;
551 553 ata_ctlp->ac_flags |= AC_ATAPI_INIT;
552 554 }
553 555
554 556 if (disk_count) {
555 557 if (!ata_disk_attach(ata_ctlp))
556 558 goto errout1;
557 559 ata_ctlp->ac_flags |= AC_DISK_INIT;
558 560 }
559 561
560 562 /*
561 563 * make certain the interrupt and error latches are clear
562 564 */
563 565 if (ata_ctlp->ac_pciide) {
564 566
565 567 int instance = ddi_get_instance(dip);
566 568 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance,
567 569 DDI_PSEUDO, 0) != DDI_SUCCESS) {
568 570 goto errout1;
569 571 }
570 572
571 573 (void) ata_pciide_status_clear(ata_ctlp);
572 574
573 575 }
574 576
575 577 /*
576 578 * enable the interrupt handler and drop the mutex
577 579 */
578 580 ata_ctlp->ac_flags |= AC_ATTACHED;
579 581 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex);
580 582
581 583 ata_init_pm(dip);
582 584
583 585 ddi_report_dev(dip);
584 586 return (DDI_SUCCESS);
585 587
586 588 errout1:
587 589 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex);
588 590 errout:
589 591 (void) ata_detach(dip, DDI_DETACH);
590 592 return (DDI_FAILURE);
591 593 }
592 594
593 595 /* driver detach entry point */
594 596
595 597 static int
596 598 ata_detach(
597 599 dev_info_t *dip,
598 600 ddi_detach_cmd_t cmd)
599 601 {
600 602 ata_ctl_t *ata_ctlp;
601 603 ata_drv_t *ata_drvp;
602 604 int instance;
603 605 int i;
604 606 int j;
605 607
606 608 ADBG_TRACE(("ata_detach entered\n"));
607 609
608 610 switch (cmd) {
609 611 case DDI_DETACH:
610 612 break;
611 613 case DDI_SUSPEND:
612 614 return (ata_suspend(dip));
613 615 default:
614 616 return (DDI_FAILURE);
615 617 }
616 618
617 619 instance = ddi_get_instance(dip);
618 620 ata_ctlp = ddi_get_soft_state(ata_state, instance);
619 621
620 622 if (!ata_ctlp)
621 623 return (DDI_SUCCESS);
622 624
623 625 if (ata_ctlp->ac_pm_support) {
624 626 ATA_BUSY_COMPONENT(dip, 0);
625 627 if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) {
626 628 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) !=
627 629 DDI_SUCCESS) {
628 630 ATA_IDLE_COMPONENT(dip, 0);
629 631 return (DDI_FAILURE);
630 632 }
631 633 }
632 634 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components");
633 635 }
634 636 ata_ctlp->ac_flags &= ~AC_ATTACHED;
635 637
636 638 /* destroy ata module */
637 639 if (ata_ctlp->ac_flags & AC_DISK_INIT)
638 640 ata_disk_detach(ata_ctlp);
639 641
640 642 /* destroy atapi module */
641 643 if (ata_ctlp->ac_flags & AC_ATAPI_INIT)
642 644 atapi_detach(ata_ctlp);
643 645
644 646 ddi_remove_minor_node(dip, NULL);
645 647
646 648 /* destroy drives */
647 649 for (i = 0; i < ATA_MAXTARG; i++) {
648 650 for (j = 0; j < ATA_MAXLUN; j++) {
649 651 ata_drvp = CTL2DRV(ata_ctlp, i, j);
650 652 if (ata_drvp != NULL)
651 653 ata_uninit_drive(ata_drvp);
652 654 }
653 655 }
654 656
655 657 if (ata_ctlp->ac_iohandle1)
656 658 ddi_regs_map_free(&ata_ctlp->ac_iohandle1);
657 659 if (ata_ctlp->ac_iohandle2)
658 660 ddi_regs_map_free(&ata_ctlp->ac_iohandle2);
659 661 if (ata_ctlp->ac_bmhandle)
660 662 ddi_regs_map_free(&ata_ctlp->ac_bmhandle);
661 663
662 664 /* destroy controller */
663 665 ata_destroy_controller(dip);
664 666
665 667 ddi_prop_remove_all(dip);
666 668
667 669 return (DDI_SUCCESS);
668 670 }
669 671
670 672 /*
671 673 * Nexus driver bus_ctl entry point
672 674 */
673 675 /*ARGSUSED*/
674 676 static int
675 677 ata_bus_ctl(
676 678 dev_info_t *d,
677 679 dev_info_t *r,
678 680 ddi_ctl_enum_t o,
679 681 void *a,
680 682 void *v)
681 683 {
682 684 dev_info_t *tdip;
683 685 int target_type;
684 686 int rc;
685 687 char *bufp;
686 688
687 689 ADBG_TRACE(("ata_bus_ctl entered\n"));
688 690
689 691 switch (o) {
690 692
691 693 case DDI_CTLOPS_SIDDEV:
692 694 return (DDI_FAILURE);
693 695
694 696 case DDI_CTLOPS_IOMIN:
695 697
696 698 /*
697 699 * Since we use PIO, we return a minimum I/O size of
698 700 * one byte. This will need to be updated when we
699 701 * implement DMA support
700 702 */
701 703
702 704 *((int *)v) = 1;
703 705 return (DDI_SUCCESS);
704 706
705 707 case DDI_CTLOPS_DMAPMAPC:
706 708 case DDI_CTLOPS_REPORTINT:
707 709 case DDI_CTLOPS_REGSIZE:
708 710 case DDI_CTLOPS_NREGS:
709 711 case DDI_CTLOPS_SLAVEONLY:
710 712 case DDI_CTLOPS_AFFINITY:
711 713 case DDI_CTLOPS_POKE:
712 714 case DDI_CTLOPS_PEEK:
713 715
714 716 /* These ops shouldn't be called by a target driver */
715 717 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n",
716 718 ddi_driver_name(d), ddi_get_instance(d), o,
717 719 ddi_driver_name(r), ddi_get_instance(r)));
718 720
719 721 return (DDI_FAILURE);
720 722
721 723 case DDI_CTLOPS_REPORTDEV:
722 724 case DDI_CTLOPS_INITCHILD:
723 725 case DDI_CTLOPS_UNINITCHILD:
724 726
725 727 /* these require special handling below */
726 728 break;
727 729
728 730 default:
729 731 return (ddi_ctlops(d, r, o, a, v));
730 732 }
731 733
732 734 /* get targets dip */
733 735
734 736 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD)
735 737 tdip = (dev_info_t *)a;
736 738 else
737 739 tdip = r;
738 740
739 741 /*
740 742 * XXX - Get class of target
741 743 * Before the "class" entry in a conf file becomes
742 744 * a real property, we use an additional property
743 745 * tentatively called "class_prop". We will require that
744 746 * new classes (ie. direct) export "class_prop".
745 747 * SCSA target drivers will not have this property, so
746 748 * no property implies SCSA.
747 749 */
748 750 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS,
749 751 "class", &bufp) == DDI_PROP_SUCCESS) ||
750 752 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS,
751 753 "class_prop", &bufp) == DDI_PROP_SUCCESS)) {
752 754 if (strcmp(bufp, "dada") == 0)
753 755 target_type = ATA_DEV_DISK;
754 756 else if (strcmp(bufp, "scsi") == 0)
755 757 target_type = ATA_DEV_ATAPI;
756 758 else {
757 759 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n",
758 760 bufp));
759 761 ddi_prop_free(bufp);
760 762 return (DDI_FAILURE);
761 763 }
762 764 ddi_prop_free(bufp);
763 765 } else {
764 766 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */
765 767 }
766 768
767 769 if (o == DDI_CTLOPS_INITCHILD) {
768 770 int instance = ddi_get_instance(d);
769 771 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance);
770 772 ata_drv_t *ata_drvp;
771 773 int targ;
772 774 int lun;
773 775 int drive_type;
774 776 char *disk_prop;
775 777 char *class_prop;
776 778
777 779 if (ata_ctlp == NULL) {
778 780 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n"));
779 781 return (DDI_FAILURE);
780 782 }
781 783
782 784 /* get (target,lun) of child device */
783 785
784 786 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS,
785 787 "target", -1);
786 788 if (targ == -1) {
787 789 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n"));
788 790 return (DDI_FAILURE);
789 791 }
790 792
791 793 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS,
792 794 "lun", 0);
793 795
794 796 if ((targ < 0) || (targ >= ATA_MAXTARG) ||
795 797 (lun < 0) || (lun >= ATA_MAXLUN)) {
796 798 return (DDI_FAILURE);
797 799 }
798 800
799 801 ata_drvp = CTL2DRV(ata_ctlp, targ, lun);
800 802
801 803 if (ata_drvp == NULL)
802 804 return (DDI_FAILURE); /* no drive */
803 805
804 806 /* get type of device */
805 807
806 808 if (ATAPIDRV(ata_drvp))
807 809 drive_type = ATA_DEV_ATAPI;
808 810 else
809 811 drive_type = ATA_DEV_DISK;
810 812
811 813 /*
812 814 * Check for special handling when child driver is
813 815 * cmdk (which morphs to the correct interface)
814 816 */
815 817 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) {
816 818
817 819 if ((target_type == ATA_DEV_DISK) &&
818 820 (target_type != drive_type))
819 821 return (DDI_FAILURE);
820 822
821 823 target_type = drive_type;
822 824
823 825 if (drive_type == ATA_DEV_ATAPI) {
824 826 class_prop = "scsi";
825 827 } else {
826 828 disk_prop = "dadk";
827 829 class_prop = "dada";
828 830
829 831 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip,
830 832 "disk", disk_prop) != DDI_PROP_SUCCESS) {
831 833 ADBG_WARN(("ata_bus_ctl: failed to "
832 834 "create disk prop\n"));
833 835 return (DDI_FAILURE);
834 836 }
835 837 }
836 838
837 839 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip,
838 840 "class_prop", class_prop) != DDI_PROP_SUCCESS) {
839 841 ADBG_WARN(("ata_bus_ctl: failed to "
840 842 "create class prop\n"));
841 843 return (DDI_FAILURE);
842 844 }
843 845 }
844 846
845 847 /* Check that target class matches the device */
846 848
847 849 if (target_type != drive_type)
848 850 return (DDI_FAILURE);
849 851
850 852 /* save pointer to drive struct for ata_disk_bus_ctl */
851 853 ddi_set_driver_private(tdip, ata_drvp);
852 854
853 855 /*
854 856 * Determine whether to enable DMA support for this drive. This
855 857 * check is deferred to this point so that the various dma
856 858 * properties could reside on the devinfo node should finer
857 859 * grained dma control be required.
858 860 */
859 861 if (ata_drvp->ad_pciide_dma == ATA_DMA_UNINITIALIZED) {
860 862 ata_drvp->ad_pciide_dma =
861 863 ata_init_drive_pcidma(ata_ctlp, ata_drvp, tdip);
862 864 ata_show_transfer_mode(ata_ctlp, ata_drvp);
863 865 }
864 866 }
865 867
866 868 if (target_type == ATA_DEV_ATAPI) {
867 869 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v);
868 870 } else {
869 871 rc = ata_disk_bus_ctl(d, r, o, a, v);
870 872 }
871 873
872 874 return (rc);
873 875 }
874 876
875 877 /*
876 878 *
877 879 * GHD ccc_hba_complete callback
878 880 *
879 881 */
880 882
881 883 /* ARGSUSED */
882 884 static void
883 885 ata_hba_complete(
884 886 void *hba_handle,
885 887 gcmd_t *gcmdp,
886 888 int do_callback)
887 889 {
888 890 ata_drv_t *ata_drvp;
889 891 ata_pkt_t *ata_pktp;
890 892
891 893 ADBG_TRACE(("ata_hba_complete entered\n"));
892 894
893 895 ata_drvp = GCMD2DRV(gcmdp);
894 896 ata_pktp = GCMD2APKT(gcmdp);
895 897 if (ata_pktp->ap_complete)
896 898 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp,
897 899 do_callback);
898 900 }
899 901
900 902 /* GHD ccc_timeout_func callback */
901 903
902 904 /* ARGSUSED */
903 905 static int
904 906 ata_timeout_func(
905 907 void *hba_handle,
906 908 gcmd_t *gcmdp,
907 909 gtgt_t *gtgtp,
908 910 gact_t action,
909 911 int calltype)
910 912 {
911 913 ata_ctl_t *ata_ctlp;
912 914 ata_pkt_t *ata_pktp;
913 915 ata_drv_t *ata_drvp;
914 916
915 917 ADBG_TRACE(("ata_timeout_func entered\n"));
916 918
917 919 ata_ctlp = (ata_ctl_t *)hba_handle;
918 920
919 921 if (gcmdp != NULL)
920 922 ata_pktp = GCMD2APKT(gcmdp);
921 923 else
922 924 ata_pktp = NULL;
923 925
924 926 switch (action) {
925 927 case GACTION_EARLY_ABORT:
926 928 /* abort before request was started */
927 929 if (ata_pktp != NULL) {
928 930 ata_pktp->ap_flags |= AP_ABORT;
929 931 }
930 932 ghd_complete(&ata_ctlp->ac_ccc, gcmdp);
931 933 return (TRUE);
932 934
933 935 case GACTION_EARLY_TIMEOUT:
934 936 /* timeout before request was started */
935 937 if (ata_pktp != NULL) {
936 938 ata_pktp->ap_flags |= AP_TIMEOUT;
937 939 }
938 940 ghd_complete(&ata_ctlp->ac_ccc, gcmdp);
939 941 return (TRUE);
940 942
941 943 case GACTION_RESET_TARGET:
942 944 /*
943 945 * Reset a device is not supported. Resetting a specific
944 946 * device can't be done at all to an ATA device and if
945 947 * you send a RESET to an ATAPI device you have to
946 948 * reset the whole bus to make certain both devices
947 949 * on the bus stay in sync regarding which device is
948 950 * the currently selected one.
949 951 */
950 952 return (FALSE);
951 953
952 954 case GACTION_RESET_BUS:
953 955 /*
954 956 * Issue bus reset and reinitialize both drives.
955 957 * But only if this is a timed-out request. Target
956 958 * driver reset requests are ignored because ATA
957 959 * and ATAPI devices shouldn't be gratuitously reset.
958 960 * Also disable DMA if it is a CF device.
959 961 */
960 962 if (gcmdp == NULL)
961 963 break;
962 964 ata_drvp = GCMD2DRV(gcmdp);
963 965 if (ata_drvp != NULL)
964 966 if (ata_drvp->ad_id.ai_config == ATA_ID_CF_TO_ATA)
965 967 ata_disable_DMA(ata_drvp);
966 968 return (ata_reset_bus(ata_ctlp));
967 969 default:
968 970 break;
969 971 }
970 972 return (FALSE);
971 973 }
972 974
973 975 /*
974 976 *
975 977 * Initialize controller's soft-state structure
976 978 *
977 979 */
978 980
979 981 static ata_ctl_t *
980 982 ata_init_controller(
981 983 dev_info_t *dip)
982 984 {
983 985 ata_ctl_t *ata_ctlp;
984 986 int instance;
985 987 caddr_t ioaddr1;
986 988 caddr_t ioaddr2;
987 989
988 990 ADBG_TRACE(("ata_init_controller entered\n"));
989 991
990 992 instance = ddi_get_instance(dip);
991 993
992 994 /* allocate controller structure */
993 995 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) {
994 996 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n"));
995 997 return (NULL);
996 998 }
997 999
998 1000 ata_ctlp = ddi_get_soft_state(ata_state, instance);
999 1001
1000 1002 if (ata_ctlp == NULL) {
1001 1003 ADBG_WARN(("ata_init_controller: failed to find "
1002 1004 "controller struct\n"));
1003 1005 return (NULL);
1004 1006 }
1005 1007
1006 1008 /*
1007 1009 * initialize per-controller data
1008 1010 */
1009 1011 ata_ctlp->ac_dip = dip;
1010 1012 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP);
1011 1013
1012 1014 /*
1013 1015 * map the device registers
1014 1016 */
1015 1017 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1,
1016 1018 &ata_ctlp->ac_iohandle2, &ioaddr2,
1017 1019 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) {
1018 1020 (void) ata_detach(dip, DDI_DETACH);
1019 1021 return (NULL);
1020 1022 }
1021 1023
1022 1024 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n",
1023 1025 ioaddr1, ioaddr2));
1024 1026
1025 1027 /*
1026 1028 * Do ARQ setup
1027 1029 */
1028 1030 atapi_init_arq(ata_ctlp);
1029 1031
1030 1032 /*
1031 1033 * Do PCI-IDE setup
1032 1034 */
1033 1035 ata_init_pciide(dip, ata_ctlp);
1034 1036
1035 1037 /*
1036 1038 * port addresses associated with ioaddr1
1037 1039 */
1038 1040 ata_ctlp->ac_ioaddr1 = ioaddr1;
1039 1041 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA;
1040 1042 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR;
1041 1043 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE;
1042 1044 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT;
1043 1045 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT;
1044 1046 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL;
1045 1047 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL;
1046 1048 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD;
1047 1049 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS;
1048 1050 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD;
1049 1051
1050 1052 /*
1051 1053 * port addresses associated with ioaddr2
1052 1054 */
1053 1055 ata_ctlp->ac_ioaddr2 = ioaddr2;
1054 1056 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS;
1055 1057 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL;
1056 1058
1057 1059 /*
1058 1060 * If AC_BSY_WAIT needs to be set for laptops that do
1059 1061 * suspend/resume but do not correctly wait for the busy bit to
1060 1062 * drop after a resume.
1061 1063 */
1062 1064 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY,
1063 1065 dip, DDI_PROP_DONTPASS, "timing_flags", 0);
1064 1066 /*
1065 1067 * get max transfer size, default to 256 sectors
1066 1068 */
1067 1069 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY,
1068 1070 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100);
1069 1071 if (ata_ctlp->ac_max_transfer < 1)
1070 1072 ata_ctlp->ac_max_transfer = 1;
1071 1073 if (ata_ctlp->ac_max_transfer > 0x100)
1072 1074 ata_ctlp->ac_max_transfer = 0x100;
1073 1075
1074 1076 /*
1075 1077 * Get the standby timer value
1076 1078 */
1077 1079 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY,
1078 1080 dip, DDI_PROP_DONTPASS, "standby", -1);
1079 1081
1080 1082 /*
1081 1083 * If this is a /pci/pci-ide instance check to see if
1082 1084 * it's supposed to be attached as an /isa/ata
1083 1085 */
1084 1086 if (ata_ctlp->ac_pciide) {
1085 1087 static char prop_buf[] = "SUNW-ata-ffff-isa";
1086 1088 int addr1 = (intptr_t)ioaddr1;
1087 1089
1088 1090
1089 1091 if (addr1 < 0 || addr1 > 0xffff) {
1090 1092 (void) ata_detach(dip, DDI_DETACH);
1091 1093 return (NULL);
1092 1094 }
1093 1095 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa",
1094 1096 addr1);
1095 1097 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(),
1096 1098 DDI_PROP_DONTPASS, prop_buf)) {
1097 1099 (void) ata_detach(dip, DDI_DETACH);
1098 1100 return (NULL);
1099 1101 }
1100 1102 }
1101 1103
1102 1104 /* Init controller specific stuff */
1103 1105 (void) ata_spec_init_controller(dip);
1104 1106
1105 1107 /*
1106 1108 * initialize GHD
1107 1109 */
1108 1110
1109 1111 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1);
1110 1112
1111 1113 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp,
1112 1114 atapi_ccballoc, atapi_ccbfree,
1113 1115 ata_pciide_dma_sg_func, ata_hba_start,
1114 1116 ata_hba_complete, ata_intr,
1115 1117 ata_get_status, ata_process_intr, ata_timeout_func,
1116 1118 &ata_timer_conf, NULL)) {
1117 1119 (void) ata_detach(dip, DDI_DETACH);
1118 1120 return (NULL);
1119 1121 }
1120 1122
1121 1123 ata_ctlp->ac_flags |= AC_GHD_INIT;
1122 1124 return (ata_ctlp);
1123 1125 }
1124 1126
1125 1127 /* destroy a controller */
1126 1128
1127 1129 static void
1128 1130 ata_destroy_controller(
1129 1131 dev_info_t *dip)
1130 1132 {
1131 1133 ata_ctl_t *ata_ctlp;
1132 1134 int instance;
1133 1135
1134 1136 ADBG_TRACE(("ata_destroy_controller entered\n"));
1135 1137
1136 1138 instance = ddi_get_instance(dip);
1137 1139 ata_ctlp = ddi_get_soft_state(ata_state, instance);
1138 1140
1139 1141 if (ata_ctlp == NULL)
1140 1142 return;
1141 1143
1142 1144 /* destroy ghd */
1143 1145 if (ata_ctlp->ac_flags & AC_GHD_INIT)
1144 1146 ghd_unregister(&ata_ctlp->ac_ccc);
1145 1147
1146 1148 /* free the pciide buffer (if any) */
1147 1149 ata_pciide_free(ata_ctlp);
1148 1150
1149 1151 /* destroy controller struct */
1150 1152 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t));
1151 1153 ddi_soft_state_free(ata_state, instance);
1152 1154
1153 1155 }
1154 1156
1155 1157
1156 1158 /*
1157 1159 *
1158 1160 * initialize a drive
1159 1161 *
1160 1162 */
1161 1163
1162 1164 static ata_drv_t *
1163 1165 ata_init_drive(
1164 1166 ata_ctl_t *ata_ctlp,
1165 1167 uchar_t targ,
1166 1168 uchar_t lun)
1167 1169 {
1168 1170 static char nec_260[] = "NEC CD-ROM DRIVE";
1169 1171 ata_drv_t *ata_drvp;
1170 1172 struct ata_id *aidp;
1171 1173 char buf[80];
1172 1174 int drive_type;
1173 1175 int i;
1174 1176 int valid_version = 0;
1175 1177
1176 1178 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n",
1177 1179 targ, lun));
1178 1180
1179 1181 /* check if device already exists */
1180 1182
1181 1183 ata_drvp = CTL2DRV(ata_ctlp, targ, lun);
1182 1184
1183 1185 if (ata_drvp != NULL)
1184 1186 return (ata_drvp);
1185 1187
1186 1188 /* allocate new device structure */
1187 1189
1188 1190 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP);
1189 1191 aidp = &ata_drvp->ad_id;
1190 1192
1191 1193 /*
1192 1194 * set up drive struct
1193 1195 */
1194 1196 ata_drvp->ad_ctlp = ata_ctlp;
1195 1197 ata_drvp->ad_pciide_dma = ATA_DMA_UNINITIALIZED;
1196 1198 ata_drvp->ad_targ = targ;
1197 1199 ata_drvp->ad_drive_bits =
1198 1200 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1);
1199 1201 /*
1200 1202 * Add the LUN for SFF-8070i support
1201 1203 */
1202 1204 ata_drvp->ad_lun = lun;
1203 1205 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun;
1204 1206
1205 1207 /*
1206 1208 * get drive type, side effect is to collect
1207 1209 * IDENTIFY DRIVE data
1208 1210 */
1209 1211
1210 1212 drive_type = ata_drive_type(ata_drvp->ad_drive_bits,
1211 1213 ata_ctlp->ac_iohandle1,
1212 1214 ata_ctlp->ac_ioaddr1,
1213 1215 ata_ctlp->ac_iohandle2,
1214 1216 ata_ctlp->ac_ioaddr2,
1215 1217 aidp);
1216 1218
1217 1219 switch (drive_type) {
1218 1220 case ATA_DEV_NONE:
1219 1221 /* no drive found */
1220 1222 goto errout;
1221 1223 case ATA_DEV_ATAPI:
1222 1224 ata_drvp->ad_flags |= AD_ATAPI;
1223 1225 break;
1224 1226 case ATA_DEV_DISK:
1225 1227 ata_drvp->ad_flags |= AD_DISK;
1226 1228 break;
1227 1229 }
1228 1230
1229 1231 /*
1230 1232 * swap bytes of all text fields
1231 1233 */
1232 1234 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) {
1233 1235 swab(aidp->ai_drvser, aidp->ai_drvser,
1234 1236 sizeof (aidp->ai_drvser));
1235 1237 swab(aidp->ai_fw, aidp->ai_fw,
1236 1238 sizeof (aidp->ai_fw));
1237 1239 swab(aidp->ai_model, aidp->ai_model,
1238 1240 sizeof (aidp->ai_model));
1239 1241 }
1240 1242
1241 1243 /*
1242 1244 * Check if this drive has the Single Sector bug
1243 1245 */
1244 1246
1245 1247 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR))
1246 1248 ata_drvp->ad_flags |= AD_1SECTOR;
1247 1249 else
1248 1250 ata_drvp->ad_flags &= ~AD_1SECTOR;
1249 1251
1250 1252 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_LBA48))
1251 1253 ata_drvp->ad_flags |= AD_BLLBA48;
1252 1254 else
1253 1255 ata_drvp->ad_flags &= ~AD_BLLBA48;
1254 1256
1255 1257 /* Check if this drive has the "revert to defaults" bug */
1256 1258 if (!ata_check_revert_to_defaults(ata_drvp))
1257 1259 ata_drvp->ad_flags |= AD_NORVRT;
1258 1260
1259 1261 /* Dump the drive info */
1260 1262 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model));
1261 1263 buf[sizeof (aidp->ai_model)-1] = '\0';
1262 1264 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--)
1263 1265 buf[i] = '\0';
1264 1266
1265 1267 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n",
1266 1268 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"),
1267 1269 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun));
1268 1270
1269 1271 ATAPRT(("?\tmodel %s\n", buf));
1270 1272
1271 1273 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) {
1272 1274 for (i = 14; i >= 2; i--) {
1273 1275 if (aidp->ai_majorversion & (1 << i)) {
1274 1276 valid_version = i;
1275 1277 break;
1276 1278 }
1277 1279 }
1278 1280 ATAPRT((
1279 1281 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n",
1280 1282 valid_version,
1281 1283 aidp->ai_majorversion,
1282 1284 aidp->ai_minorversion));
1283 1285 }
1284 1286
1285 1287 if (ata_capability_data) {
1286 1288
1287 1289 ATAPRT(("?\t\tstat %x, err %x\n",
1288 1290 ddi_get8(ata_ctlp->ac_iohandle2,
1289 1291 ata_ctlp->ac_altstatus),
1290 1292 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error)));
1291 1293
1292 1294 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n",
1293 1295 aidp->ai_config,
1294 1296 aidp->ai_cap));
1295 1297
1296 1298 /*
1297 1299 * Be aware that ATA-6 and later drives may not provide valid
1298 1300 * geometry information and other obsoleted info.
1299 1301 * Select what is printed based on supported ATA model (skip
1300 1302 * anything below ATA/ATAPI-3)
1301 1303 */
1302 1304
1303 1305 if (valid_version == 0 || aidp->ai_majorversion <
1304 1306 ATAC_MAJVER_6) {
1305 1307 /*
1306 1308 * Supported version less then ATA-6
1307 1309 */
1308 1310 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n",
1309 1311 aidp->ai_fixcyls,
1310 1312 aidp->ai_heads,
1311 1313 aidp->ai_sectors));
1312 1314 }
1313 1315 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n",
1314 1316 aidp->ai_mult1,
1315 1317 aidp->ai_mult2));
1316 1318 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) {
1317 1319 ATAPRT((
1318 1320 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n",
1319 1321 aidp->ai_piomode,
1320 1322 aidp->ai_dmamode,
1321 1323 aidp->ai_advpiomode));
1322 1324 } else {
1323 1325 ATAPRT(("?\t\tadvpiomode 0x%x\n",
1324 1326 aidp->ai_advpiomode));
1325 1327 }
1326 1328 ATAPRT(("?\t\tminpio %d, minpioflow %d\n",
1327 1329 aidp->ai_minpio,
1328 1330 aidp->ai_minpioflow));
1329 1331 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 &&
1330 1332 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) {
1331 1333 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n",
1332 1334 aidp->ai_dworddma,
1333 1335 aidp->ai_ultradma));
1334 1336 } else {
1335 1337 ATAPRT(("?\t\tdwdma 0x%x\n",
1336 1338 aidp->ai_dworddma));
1337 1339 }
1338 1340 }
1339 1341
1340 1342 if (ATAPIDRV(ata_drvp)) {
1341 1343 if (!atapi_init_drive(ata_drvp))
1342 1344 goto errout;
1343 1345 } else {
1344 1346 if (!ata_disk_init_drive(ata_drvp))
1345 1347 goto errout;
1346 1348 }
1347 1349
1348 1350 /*
1349 1351 * store pointer in controller struct
1350 1352 */
1351 1353 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp;
1352 1354
1353 1355 /*
1354 1356 * lock the drive's current settings in case I have to
1355 1357 * reset the drive due to some sort of error
1356 1358 */
1357 1359 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0);
1358 1360
1359 1361 return (ata_drvp);
1360 1362
1361 1363 errout:
1362 1364 ata_uninit_drive(ata_drvp);
1363 1365 return (NULL);
1364 1366 }
1365 1367
1366 1368 /* destroy a drive */
1367 1369
1368 1370 static void
1369 1371 ata_uninit_drive(
1370 1372 ata_drv_t *ata_drvp)
1371 1373 {
1372 1374 #if 0
1373 1375 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp;
1374 1376 #endif
1375 1377
1376 1378 ADBG_TRACE(("ata_uninit_drive entered\n"));
1377 1379
1378 1380 #if 0
1379 1381 /*
1380 1382 * DON'T DO THIS. disabling interrupts floats the IRQ line
1381 1383 * which generates spurious interrupts
1382 1384 */
1383 1385
1384 1386 /*
1385 1387 * Select the correct drive
1386 1388 */
1387 1389 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd,
1388 1390 ata_drvp->ad_drive_bits);
1389 1391 ata_nsecwait(400);
1390 1392
1391 1393 /*
1392 1394 * Disable interrupts from the drive
1393 1395 */
1394 1396 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl,
1395 1397 (ATDC_D3 | ATDC_NIEN));
1396 1398 #endif
1397 1399
1398 1400 /* interface specific clean-ups */
1399 1401
1400 1402 if (ata_drvp->ad_flags & AD_ATAPI)
1401 1403 atapi_uninit_drive(ata_drvp);
1402 1404 else if (ata_drvp->ad_flags & AD_DISK)
1403 1405 ata_disk_uninit_drive(ata_drvp);
1404 1406
1405 1407 /* free drive struct */
1406 1408
1407 1409 kmem_free(ata_drvp, sizeof (ata_drv_t));
1408 1410 }
1409 1411
1410 1412
1411 1413 /*
1412 1414 * ata_drive_type()
1413 1415 *
1414 1416 * The timeout values and exact sequence of checking is critical
1415 1417 * especially for atapi device detection, and should not be changed lightly.
1416 1418 *
1417 1419 */
1418 1420 static int
1419 1421 ata_drive_type(
1420 1422 uchar_t drvhd,
1421 1423 ddi_acc_handle_t io_hdl1,
1422 1424 caddr_t ioaddr1,
1423 1425 ddi_acc_handle_t io_hdl2,
1424 1426 caddr_t ioaddr2,
1425 1427 struct ata_id *ata_id_bufp)
1426 1428 {
1427 1429 uchar_t status;
1428 1430
1429 1431 ADBG_TRACE(("ata_drive_type entered\n"));
1430 1432
1431 1433 /*
1432 1434 * select the appropriate drive and LUN
1433 1435 */
1434 1436 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd);
1435 1437 ata_nsecwait(400);
1436 1438
1437 1439 /*
1438 1440 * make certain the drive is selected, and wait for not busy
1439 1441 */
1440 1442 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0,
1441 1443 5 * 1000000);
1442 1444
1443 1445 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS);
1444 1446
1445 1447 if (status & ATS_BSY) {
1446 1448 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status));
1447 1449 return (ATA_DEV_NONE);
1448 1450 }
1449 1451
1450 1452 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp))
1451 1453 return (ATA_DEV_DISK);
1452 1454
1453 1455 /*
1454 1456 * No disk, check for atapi unit.
1455 1457 */
1456 1458 if (!atapi_signature(io_hdl1, ioaddr1)) {
1457 1459 #ifndef ATA_DISABLE_ATAPI_1_7
1458 1460 /*
1459 1461 * Check for old (but prevalent) atapi 1.7B
1460 1462 * spec device, the only known example is the
1461 1463 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2
1462 1464 * compliant). This device has no signature
1463 1465 * and requires conversion from hex to BCD
1464 1466 * for some scsi audio commands.
1465 1467 */
1466 1468 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) {
1467 1469 return (ATA_DEV_ATAPI);
1468 1470 }
1469 1471 #endif
1470 1472 return (ATA_DEV_NONE);
1471 1473 }
1472 1474
1473 1475 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) {
1474 1476 return (ATA_DEV_ATAPI);
1475 1477 }
1476 1478
1477 1479 return (ATA_DEV_NONE);
1478 1480
1479 1481 }
1480 1482
1481 1483 /*
1482 1484 * nsec-granularity time delay function
1483 1485 */
1484 1486 void
1485 1487 ata_nsecwait(clock_t count)
1486 1488 {
1487 1489 extern int tsc_gethrtime_initted;
1488 1490
1489 1491 if (tsc_gethrtime_initted) {
1490 1492 hrtime_t end = gethrtime() + count;
1491 1493
1492 1494 while (gethrtime() < end) {
1493 1495 SMT_PAUSE();
1494 1496 }
1495 1497 } else {
1496 1498 drv_usecwait(1 + (count / 1000));
1497 1499 }
1498 1500 }
1499 1501
1500 1502
1501 1503 /*
1502 1504 * Wait for a register of a controller to achieve a specific state.
1503 1505 * To return normally, all the bits in the first sub-mask must be ON,
1504 1506 * all the bits in the second sub-mask must be OFF.
1505 1507 * If timeout_usec microseconds pass without the controller achieving
1506 1508 * the desired bit configuration, we return TRUE, else FALSE.
1507 1509 */
1508 1510
1509 1511 int ata_usec_delay = 10;
1510 1512
1511 1513 int
1512 1514 ata_wait(
1513 1515 ddi_acc_handle_t io_hdl,
1514 1516 caddr_t ioaddr,
1515 1517 uchar_t onbits,
1516 1518 uchar_t offbits,
1517 1519 uint_t timeout_usec)
1518 1520 {
1519 1521 ushort_t val;
1520 1522 hrtime_t deadline = gethrtime() +
1521 1523 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC);
1522 1524
1523 1525
1524 1526 do {
1525 1527 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS);
1526 1528 if ((val & onbits) == onbits && (val & offbits) == 0)
1527 1529 return (TRUE);
1528 1530 drv_usecwait(ata_usec_delay);
1529 1531 } while (gethrtime() < deadline);
1530 1532
1531 1533 return (FALSE);
1532 1534 }
1533 1535
1534 1536
1535 1537 /*
1536 1538 *
1537 1539 * This is a slightly more complicated version that checks
1538 1540 * for error conditions and bails-out rather than looping
1539 1541 * until the timeout expires
1540 1542 */
1541 1543 int
1542 1544 ata_wait3(
1543 1545 ddi_acc_handle_t io_hdl,
1544 1546 caddr_t ioaddr,
1545 1547 uchar_t onbits1,
1546 1548 uchar_t offbits1,
1547 1549 uchar_t failure_onbits2,
1548 1550 uchar_t failure_offbits2,
1549 1551 uchar_t failure_onbits3,
1550 1552 uchar_t failure_offbits3,
1551 1553 uint_t timeout_usec)
1552 1554 {
1553 1555 ushort_t val;
1554 1556 hrtime_t deadline = gethrtime() +
1555 1557 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC);
1556 1558
1557 1559 do {
1558 1560 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS);
1559 1561
1560 1562 /*
1561 1563 * check for expected condition
1562 1564 */
1563 1565 if ((val & onbits1) == onbits1 && (val & offbits1) == 0)
1564 1566 return (TRUE);
1565 1567
1566 1568 /*
1567 1569 * check for error conditions
1568 1570 */
1569 1571 if ((val & failure_onbits2) == failure_onbits2 &&
1570 1572 (val & failure_offbits2) == 0) {
1571 1573 return (FALSE);
1572 1574 }
1573 1575
1574 1576 if ((val & failure_onbits3) == failure_onbits3 &&
1575 1577 (val & failure_offbits3) == 0) {
1576 1578 return (FALSE);
1577 1579 }
1578 1580
1579 1581 drv_usecwait(ata_usec_delay);
1580 1582 } while (gethrtime() < deadline);
1581 1583
1582 1584 return (FALSE);
1583 1585 }
1584 1586
1585 1587
1586 1588 /*
1587 1589 *
1588 1590 * low level routine for ata_disk_id() and atapi_id()
1589 1591 *
1590 1592 */
1591 1593
1592 1594 int
1593 1595 ata_id_common(
1594 1596 uchar_t id_cmd,
1595 1597 int expect_drdy,
1596 1598 ddi_acc_handle_t io_hdl1,
1597 1599 caddr_t ioaddr1,
1598 1600 ddi_acc_handle_t io_hdl2,
1599 1601 caddr_t ioaddr2,
1600 1602 struct ata_id *aidp)
1601 1603 {
1602 1604 uchar_t status;
1603 1605
1604 1606 ADBG_TRACE(("ata_id_common entered\n"));
1605 1607
1606 1608 bzero(aidp, sizeof (struct ata_id));
1607 1609
1608 1610 /*
1609 1611 * clear the features register
1610 1612 */
1611 1613 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0);
1612 1614
1613 1615 /*
1614 1616 * Disable interrupts from the device. When the ata
1615 1617 * hardware is sharing its interrupt with another
1616 1618 * device, the shared interrupt might have already been
1617 1619 * unmasked in the interrupt controller and
1618 1620 * triggering ata device interrupts will result in an
1619 1621 * interrupt storm and a hung system.
1620 1622 */
1621 1623 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN);
1622 1624
1623 1625 /*
1624 1626 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command
1625 1627 */
1626 1628 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd);
1627 1629
1628 1630 /* wait for the busy bit to settle */
1629 1631 ata_nsecwait(400);
1630 1632
1631 1633 /*
1632 1634 * read alternate status and check for conditions which
1633 1635 * may indicate the drive is not present, to prevent getting
1634 1636 * stuck in ata_wait3() below.
1635 1637 */
1636 1638 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS);
1637 1639
1638 1640 /*
1639 1641 * 0x0, 0x7f, or ATS_DF can happen when no drive is present
1640 1642 */
1641 1643 if ((status == 0x0) || (status == 0x7f) ||
1642 1644 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) {
1643 1645 /* invalid status, can't be an ATA or ATAPI device */
1644 1646 return (FALSE);
1645 1647 }
1646 1648
1647 1649 /*
1648 1650 * According to the ATA specification, some drives may have
1649 1651 * to read the media to complete this command. We need to
1650 1652 * make sure we give them enough time to respond.
1651 1653 */
1652 1654 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY,
1653 1655 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000);
1654 1656
1655 1657 /*
1656 1658 * read the status byte and clear the pending interrupt
1657 1659 */
1658 1660 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS);
1659 1661
1660 1662 /*
1661 1663 * this happens if there's no drive present
1662 1664 */
1663 1665 if (status == 0xff || status == 0x7f) {
1664 1666 /* invalid status, can't be an ATA or ATAPI device */
1665 1667 return (FALSE);
1666 1668 }
1667 1669
1668 1670 if (status & ATS_BSY) {
1669 1671 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n",
1670 1672 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS),
1671 1673 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR)));
1672 1674 return (FALSE);
1673 1675 }
1674 1676
1675 1677 if (!(status & ATS_DRQ)) {
1676 1678 if (status & (ATS_ERR | ATS_DF)) {
1677 1679 return (FALSE);
1678 1680 }
1679 1681 /*
1680 1682 * Give the drive another second to assert DRQ. Some older
1681 1683 * drives de-assert BSY before asserting DRQ. Bail out
1682 1684 * immediately if the status becomes 0x7f, which is invalid
1683 1685 * value. It can happen when no drive is present.
1684 1686 */
1685 1687 if (!ata_wait3(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 0x7f,
1686 1688 ATS_BSY, 0x7f, ATS_BSY, 1000000)) {
1687 1689 ADBG_WARN(("ata_id_common: "
1688 1690 "!DRQ status 0x%x error 0x%x\n",
1689 1691 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS),
1690 1692 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR)));
1691 1693 return (FALSE);
1692 1694 }
1693 1695 }
1694 1696
1695 1697 /*
1696 1698 * transfer the data
1697 1699 */
1698 1700 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA,
1699 1701 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR);
1700 1702
1701 1703 /* wait for the busy bit to settle */
1702 1704 ata_nsecwait(400);
1703 1705
1704 1706
1705 1707 /*
1706 1708 * Wait for the drive to recognize I've read all the data.
1707 1709 * Some drives have been observed to take as much as 3msec to
1708 1710 * deassert DRQ after reading the data; allow 1 sec just in case.
1709 1711 *
1710 1712 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V,
1711 1713 * CDR-1350A) don't assert DRDY. If we've made it this far we can
1712 1714 * safely ignore the DRDY bit since the ATAPI Packet command
1713 1715 * actually doesn't require it to ever be asserted.
1714 1716 *
1715 1717 * Bail out immediately if the status becomes 0x7f, which is invalid
1716 1718 * value. It can happen when no drive is present.
1717 1719 *
1718 1720 */
1719 1721 if (!ata_wait3(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0),
1720 1722 (ATS_BSY | ATS_DRQ), 0x7f, ATS_BSY, 0x7f, ATS_BSY, 1000000)) {
1721 1723 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n",
1722 1724 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS),
1723 1725 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR)));
1724 1726 return (FALSE);
1725 1727 }
1726 1728
1727 1729 /*
1728 1730 * Check to see if the command aborted. This happens if
1729 1731 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device,
1730 1732 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA
1731 1733 * (non-PACKET) device.
1732 1734 */
1733 1735 if (status & (ATS_DF | ATS_ERR)) {
1734 1736 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n",
1735 1737 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS),
1736 1738 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR)));
1737 1739 return (FALSE);
1738 1740 }
1739 1741 return (TRUE);
1740 1742 }
1741 1743
1742 1744
1743 1745 /*
1744 1746 * Low level routine to issue a non-data command and busy wait for
1745 1747 * the completion status.
1746 1748 */
1747 1749
1748 1750 int
1749 1751 ata_command(
1750 1752 ata_ctl_t *ata_ctlp,
1751 1753 ata_drv_t *ata_drvp,
1752 1754 int expect_drdy,
1753 1755 int silent,
1754 1756 uint_t busy_wait,
1755 1757 uchar_t cmd,
1756 1758 uchar_t feature,
1757 1759 uchar_t count,
1758 1760 uchar_t sector,
1759 1761 uchar_t head,
1760 1762 uchar_t cyl_low,
1761 1763 uchar_t cyl_hi)
1762 1764 {
1763 1765 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1;
1764 1766 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2;
1765 1767 uchar_t status;
1766 1768
1767 1769 /* select the drive */
1768 1770 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits);
1769 1771 ata_nsecwait(400);
1770 1772
1771 1773 /* make certain the drive selected */
1772 1774 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2,
1773 1775 (uchar_t)(expect_drdy ? ATS_DRDY : 0),
1774 1776 ATS_BSY, busy_wait)) {
1775 1777 ADBG_ERROR(("ata_command: select failed "
1776 1778 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x "
1777 1779 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n",
1778 1780 expect_drdy, cmd, feature, count,
1779 1781 sector, head, cyl_low, cyl_hi));
1780 1782 return (FALSE);
1781 1783 }
1782 1784
1783 1785 /*
1784 1786 * set all the regs
1785 1787 */
1786 1788 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits));
1787 1789 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector);
1788 1790 ddi_put8(io_hdl1, ata_ctlp->ac_count, count);
1789 1791 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low);
1790 1792 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi);
1791 1793 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature);
1792 1794
1793 1795 /* send the command */
1794 1796 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd);
1795 1797
1796 1798 /* wait for the busy bit to settle */
1797 1799 ata_nsecwait(400);
1798 1800
1799 1801 /* wait for not busy */
1800 1802 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) {
1801 1803 ADBG_ERROR(("ata_command: BSY too long!"
1802 1804 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x "
1803 1805 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n",
1804 1806 expect_drdy, cmd, feature, count,
1805 1807 sector, head, cyl_low, cyl_hi));
1806 1808 return (FALSE);
1807 1809 }
1808 1810
1809 1811 /*
1810 1812 * wait for DRDY before continuing
1811 1813 */
1812 1814 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2,
1813 1815 ATS_DRDY, ATS_BSY, /* okay */
1814 1816 ATS_ERR, ATS_BSY, /* cmd failed */
1815 1817 ATS_DF, ATS_BSY, /* drive failed */
1816 1818 busy_wait);
1817 1819
1818 1820 /* read status to clear IRQ, and check for error */
1819 1821 status = ddi_get8(io_hdl1, ata_ctlp->ac_status);
1820 1822
1821 1823 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0)
1822 1824 return (TRUE);
1823 1825
1824 1826 if (!silent) {
1825 1827 ADBG_ERROR(("ata_command status 0x%x error 0x%x "
1826 1828 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x "
1827 1829 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n",
1828 1830 ddi_get8(io_hdl1, ata_ctlp->ac_status),
1829 1831 ddi_get8(io_hdl1, ata_ctlp->ac_error),
1830 1832 expect_drdy, cmd, feature, count,
1831 1833 sector, head, cyl_low, cyl_hi));
1832 1834 }
1833 1835 return (FALSE);
1834 1836 }
1835 1837
1836 1838
1837 1839
1838 1840 /*
1839 1841 *
1840 1842 * Issue a SET FEATURES command
1841 1843 *
1842 1844 */
1843 1845
1844 1846 int
1845 1847 ata_set_feature(
1846 1848 ata_ctl_t *ata_ctlp,
1847 1849 ata_drv_t *ata_drvp,
1848 1850 uchar_t feature,
1849 1851 uchar_t value)
1850 1852 {
1851 1853 int rc;
1852 1854
1853 1855 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait,
1854 1856 ATC_SET_FEAT, feature, value, 0, 0, 0, 0);
1855 1857 /* feature, count, sector, head, cyl_low, cyl_hi */
1856 1858
1857 1859 if (rc) {
1858 1860 return (TRUE);
1859 1861 }
1860 1862
1861 1863 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value));
1862 1864 return (FALSE);
1863 1865 }
1864 1866
1865 1867
1866 1868
1867 1869 /*
1868 1870 *
1869 1871 * Issue a FLUSH CACHE command
1870 1872 *
1871 1873 */
1872 1874
1873 1875 static int
1874 1876 ata_flush_cache(
1875 1877 ata_ctl_t *ata_ctlp,
1876 1878 ata_drv_t *ata_drvp)
1877 1879 {
1878 1880 /* this command is optional so fail silently */
1879 1881 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE,
1880 1882 ata_flush_cache_wait,
1881 1883 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0));
1882 1884 }
1883 1885
1884 1886 /*
1885 1887 * ata_setup_ioaddr()
1886 1888 *
1887 1889 * Map the device registers and return the handles.
1888 1890 *
1889 1891 * If this is a ISA-ATA controller then only two handles are
1890 1892 * initialized and returned.
1891 1893 *
1892 1894 * If this is a PCI-IDE controller than a third handle (for the
1893 1895 * PCI-IDE Bus Mastering registers) is initialized and returned.
1894 1896 *
1895 1897 */
1896 1898
1897 1899 static int
1898 1900 ata_setup_ioaddr(
1899 1901 dev_info_t *dip,
1900 1902 ddi_acc_handle_t *handle1p,
1901 1903 caddr_t *addr1p,
1902 1904 ddi_acc_handle_t *handle2p,
1903 1905 caddr_t *addr2p,
1904 1906 ddi_acc_handle_t *bm_hdlp,
1905 1907 caddr_t *bm_addrp)
1906 1908 {
1907 1909 ddi_device_acc_attr_t dev_attr;
1908 1910 int rnumber;
1909 1911 int rc;
1910 1912 off_t regsize;
1911 1913
1912 1914 /*
1913 1915 * Make certain the controller is enabled and its regs are map-able
1914 1916 *
1915 1917 */
1916 1918 rc = ddi_dev_regsize(dip, 0, ®size);
1917 1919 if (rc != DDI_SUCCESS || regsize <= AT_CMD) {
1918 1920 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n",
1919 1921 rc, (long long)regsize));
1920 1922 return (FALSE);
1921 1923 }
1922 1924
1923 1925 rc = ddi_dev_regsize(dip, 1, ®size);
1924 1926 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) {
1925 1927 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n",
1926 1928 rc, (long long)regsize));
1927 1929 return (FALSE);
1928 1930 }
1929 1931
1930 1932 /*
1931 1933 * setup the device attribute structure for little-endian,
1932 1934 * strict ordering access.
1933 1935 */
1934 1936 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1935 1937 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
1936 1938 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1937 1939
1938 1940 *handle1p = NULL;
1939 1941 *handle2p = NULL;
1940 1942 *bm_hdlp = NULL;
1941 1943
1942 1944 /*
1943 1945 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device
1944 1946 */
1945 1947 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) {
1946 1948 /* it's PNP-ISA, skip over the extra reg tuple */
1947 1949 rnumber = 1;
1948 1950 goto not_pciide;
1949 1951 }
1950 1952
1951 1953 /* else, it's ISA or PCI-IDE, check further */
1952 1954 rnumber = 0;
1953 1955
1954 1956 if (!ata_is_pci(dip)) {
1955 1957 /*
1956 1958 * If it's not a PCI-IDE, there are only two reg tuples
1957 1959 * and the first one contains the I/O base (170 or 1f0)
1958 1960 * rather than the controller instance number.
1959 1961 */
1960 1962 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n"));
1961 1963 goto not_pciide;
1962 1964 }
1963 1965
1964 1966
1965 1967 /*
1966 1968 * Map the correct half of the PCI-IDE Bus Master registers.
1967 1969 * There's a single BAR that maps these registers for both
1968 1970 * controller's in a dual-controller chip and it's upto my
1969 1971 * parent nexus, pciide, to adjust which (based on my instance
1970 1972 * number) half this call maps.
1971 1973 */
1972 1974 rc = ddi_dev_regsize(dip, 2, ®size);
1973 1975 if (rc != DDI_SUCCESS || regsize < 8) {
1974 1976 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n",
1975 1977 rc, (long long)regsize));
1976 1978 goto not_pciide;
1977 1979 }
1978 1980
1979 1981 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp);
1980 1982
1981 1983 if (rc != DDI_SUCCESS) {
1982 1984 /* map failed, try to use in non-pci-ide mode */
1983 1985 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n",
1984 1986 rc));
1985 1987 *bm_hdlp = NULL;
1986 1988 }
1987 1989
1988 1990 not_pciide:
1989 1991 /*
1990 1992 * map the lower command block registers
1991 1993 */
1992 1994
1993 1995 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr,
1994 1996 handle1p);
1995 1997
1996 1998 if (rc != DDI_SUCCESS) {
1997 1999 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc);
1998 2000 goto out1;
1999 2001 }
2000 2002
2001 2003 /*
2002 2004 * If the controller is being used in compatibility mode
2003 2005 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property
2004 2006 * will specify zeros for the I/O ports for the PCI
2005 2007 * instance.
2006 2008 */
2007 2009 if (*addr1p == 0) {
2008 2010 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n"));
2009 2011 goto out2;
2010 2012 }
2011 2013
2012 2014 /*
2013 2015 * map the upper control block registers
2014 2016 */
2015 2017 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr,
2016 2018 handle2p);
2017 2019 if (rc == DDI_SUCCESS)
2018 2020 return (TRUE);
2019 2021
2020 2022 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc);
2021 2023
2022 2024 out2:
2023 2025 if (*handle1p != NULL) {
2024 2026 ddi_regs_map_free(handle1p);
2025 2027 *handle1p = NULL;
2026 2028 }
2027 2029
2028 2030 out1:
2029 2031 if (*bm_hdlp != NULL) {
2030 2032 ddi_regs_map_free(bm_hdlp);
2031 2033 *bm_hdlp = NULL;
2032 2034 }
2033 2035 return (FALSE);
2034 2036
2035 2037 }
2036 2038
2037 2039 /*
2038 2040 *
2039 2041 * Currently, the only supported controllers are ones which
2040 2042 * support the SFF-8038 Bus Mastering spec.
2041 2043 *
2042 2044 * Check the parent node's IEEE 1275 class-code property to
2043 2045 * determine if it's an PCI-IDE instance which supports SFF-8038
2044 2046 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller
2045 2047 * that doesn't do Bus Mastering. In that case, my interrupt handler
2046 2048 * only uses the interrupt latch bit in PCI-IDE status register.
2047 2049 * The assumption is that the programming interface byte of the
2048 2050 * class-code property reflects the bus master DMA capability of
2049 2051 * the controller.
2050 2052 *
2051 2053 * Whether the drive support supports the DMA option still needs
2052 2054 * to be checked later. Each individual request also has to be
2053 2055 * checked for alignment and size to decide whether to use the
2054 2056 * DMA transfer mode.
2055 2057 */
2056 2058
2057 2059 static void
2058 2060 ata_init_pciide(
2059 2061 dev_info_t *dip,
2060 2062 ata_ctl_t *ata_ctlp)
2061 2063 {
2062 2064 uint_t class_code;
2063 2065 uchar_t status;
2064 2066
2065 2067 ata_cntrl_DMA_sel_msg = NULL;
2066 2068
2067 2069 if (ata_ctlp->ac_bmhandle == NULL) {
2068 2070 ata_ctlp->ac_pciide = FALSE;
2069 2071 ata_ctlp->ac_pciide_bm = FALSE;
2070 2072 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable";
2071 2073 return;
2072 2074 }
2073 2075
2074 2076 /*
2075 2077 * check if it's a known bogus PCI-IDE chip
2076 2078 */
2077 2079 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) {
2078 2080 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n"));
2079 2081 ata_ctlp->ac_pciide = FALSE;
2080 2082 ata_ctlp->ac_pciide_bm = FALSE;
2081 2083 ata_cntrl_DMA_sel_msg = "cntrl blacklisted";
2082 2084 return;
2083 2085 }
2084 2086 ata_ctlp->ac_pciide = TRUE;
2085 2087
2086 2088 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) {
2087 2089 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN;
2088 2090 }
2089 2091
2090 2092 /*
2091 2093 * check for a PCI-IDE chip with a broken DMA engine
2092 2094 */
2093 2095 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) {
2094 2096 ata_ctlp->ac_pciide_bm = FALSE;
2095 2097 ata_cntrl_DMA_sel_msg =
2096 2098 "cntrl blacklisted/DMA engine broken";
2097 2099 return;
2098 2100 }
2099 2101
2100 2102 /*
2101 2103 * Check the Programming Interface register to determine
2102 2104 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE
2103 2105 * devices don't support Bus Mastering or DMA.
2104 2106 * Since we are dealing with pre-qualified pci-ide controller,
2105 2107 * check programming interface byte only.
2106 2108 */
2107 2109
2108 2110 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
2109 2111 DDI_PROP_DONTPASS, "class-code", 0);
2110 2112 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) {
2111 2113 ata_ctlp->ac_pciide_bm = FALSE;
2112 2114 ata_cntrl_DMA_sel_msg =
2113 2115 "cntrl not Bus Master DMA capable";
2114 2116 return;
2115 2117 }
2116 2118
2117 2119 /*
2118 2120 * Avoid doing DMA on "simplex" chips which share hardware
2119 2121 * between channels
2120 2122 */
2121 2123 status = ddi_get8(ata_ctlp->ac_bmhandle,
2122 2124 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG);
2123 2125 /*
2124 2126 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode".
2125 2127 * In such a mode, the simplex bit is asserted, but in fact testing
2126 2128 * on such a motherboard has shown that the devices are not simplex
2127 2129 * -- DMA can be used on both channels concurrently with no special
2128 2130 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX
2129 2131 * flag set to indicate that the value of the simplex bit can be
2130 2132 * ignored.
2131 2133 */
2132 2134
2133 2135 if (status & PCIIDE_BMISX_SIMPLEX) {
2134 2136 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) {
2135 2137 cmn_err(CE_WARN, "Ignoring false simplex bit \n");
2136 2138
2137 2139 } else {
2138 2140
2139 2141 int simplex_dma_channel, *rp, proplen, channel;
2140 2142 int dma_on = FALSE;
2141 2143
2142 2144 /*
2143 2145 * By default,use DMA on channel 0 and PIO on channel
2144 2146 * 1. This can be switched by setting
2145 2147 * ata-simplex-dma-channel to:
2146 2148 * 0 DMA on channel 0 (default without this
2147 2149 * property)
2148 2150 * 1 DMA on channel 1
2149 2151 * any other value: DMA off on both channels.
2150 2152 */
2151 2153 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY,
2152 2154 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0);
2153 2155
2154 2156 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
2155 2157 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp,
2156 2158 (uint_t *)&proplen) == DDI_PROP_SUCCESS) {
2157 2159
2158 2160 channel = *rp;
2159 2161 ddi_prop_free(rp);
2160 2162
2161 2163 if (simplex_dma_channel == channel) {
2162 2164 cmn_err(CE_CONT, "?ata: simplex "
2163 2165 "controller. DMA on channel"
2164 2166 " %d PIO on channel %d",
2165 2167 channel, channel ? 0:1);
2166 2168 dma_on = TRUE;
2167 2169 } else {
2168 2170 ata_cntrl_DMA_sel_msg =
2169 2171 "simplex controller";
2170 2172 }
2171 2173 }
2172 2174
2173 2175 if (dma_on == FALSE) {
2174 2176 ata_ctlp->ac_pciide_bm = FALSE;
2175 2177
2176 2178 return;
2177 2179 }
2178 2180 }
2179 2181 }
2180 2182
2181 2183 /*
2182 2184 * It's a compatible PCI-IDE Bus Mastering controller,
2183 2185 * allocate and map the DMA Scatter/Gather list (PRDE table).
2184 2186 */
2185 2187 if (ata_pciide_alloc(dip, ata_ctlp))
2186 2188 ata_ctlp->ac_pciide_bm = TRUE;
2187 2189 else {
2188 2190 ata_ctlp->ac_pciide_bm = FALSE;
2189 2191 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list";
2190 2192 }
2191 2193 }
2192 2194
2193 2195 /*
2194 2196 *
2195 2197 * Determine whether to enable DMA support for this drive.
2196 2198 * The controller and the drive both have to support DMA.
2197 2199 * The controller's capabilities were already checked in
2198 2200 * ata_init_pciide(), now just check the drive's capabilities.
2199 2201 *
2200 2202 */
2201 2203
2202 2204 static int
2203 2205 ata_init_drive_pcidma(
2204 2206 ata_ctl_t *ata_ctlp,
2205 2207 ata_drv_t *ata_drvp,
2206 2208 dev_info_t *tdip)
2207 2209 {
2208 2210 boolean_t dma;
2209 2211 boolean_t cd_dma;
2210 2212 boolean_t disk_dma;
2211 2213 boolean_t atapi_dma;
2212 2214 int ata_options;
2213 2215
2214 2216 ata_dev_DMA_sel_msg = NULL;
2215 2217
2216 2218 if (ata_ctlp->ac_pciide_bm != TRUE) {
2217 2219 ata_dev_DMA_sel_msg =
2218 2220 "controller is not Bus Master capable";
2219 2221
2220 2222 return (ATA_DMA_OFF);
2221 2223 }
2222 2224
2223 2225 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip,
2224 2226 0, "ata-options", 0);
2225 2227
2226 2228 if (!(ata_options & ATA_OPTIONS_DMA)) {
2227 2229 /*
2228 2230 * Either the ata-options property was not found or
2229 2231 * DMA is not enabled by this property
2230 2232 */
2231 2233 ata_dev_DMA_sel_msg =
2232 2234 "disabled by \"ata-options\" property";
2233 2235
2234 2236 return (ATA_DMA_OFF);
2235 2237 }
2236 2238
2237 2239 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) {
2238 2240 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted";
2239 2241
2240 2242 return (ATA_DMA_OFF);
2241 2243 }
2242 2244
2243 2245 /*
2244 2246 * DMA mode is mandatory on ATA-3 (or newer) drives but is
2245 2247 * optional on ATA-2 (or older) drives.
2246 2248 *
2247 2249 * On ATA-2 drives the ai_majorversion word will probably
2248 2250 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in
2249 2251 * the capabilities word instead. The order of these tests
2250 2252 * is important since an ATA-3 drive doesn't have to set
2251 2253 * the DMA bit in the capabilities word.
2252 2254 *
2253 2255 */
2254 2256
2255 2257 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 &&
2256 2258 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) &&
2257 2259 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) {
2258 2260 ata_dev_DMA_sel_msg = "device not DMA capable";
2259 2261
2260 2262 return (ATA_DMA_OFF);
2261 2263 }
2262 2264
2263 2265 /*
2264 2266 * Disable DMA for ATAPI devices on controllers known to
2265 2267 * have trouble with ATAPI DMA
2266 2268 */
2267 2269
2268 2270 if (ATAPIDRV(ata_drvp)) {
2269 2271 if (ata_check_pciide_blacklist(ata_ctlp->ac_dip,
2270 2272 ATA_BL_ATAPI_NODMA)) {
2271 2273 ata_dev_DMA_sel_msg =
2272 2274 "controller incapable of DMA for ATAPI device";
2273 2275
2274 2276 return (ATA_DMA_OFF);
2275 2277 }
2276 2278 }
2277 2279 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip,
2278 2280 0, "ata-dma-enabled", TRUE);
2279 2281 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip,
2280 2282 0, "ata-disk-dma-enabled", TRUE);
2281 2283 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip,
2282 2284 0, "atapi-cd-dma-enabled", FALSE);
2283 2285 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip,
2284 2286 0, "atapi-other-dma-enabled", TRUE);
2285 2287
2286 2288 if (dma == FALSE) {
2287 2289 cmn_err(CE_CONT, "?ata_init_drive_pcidma: "
2288 2290 "DMA disabled by \"ata-dma-enabled\" property");
2289 2291 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled";
2290 2292
2291 2293 return (ATA_DMA_OFF);
2292 2294 }
2293 2295
2294 2296 if (IS_CDROM(ata_drvp) == TRUE) {
2295 2297 if (cd_dma == FALSE) {
2296 2298 ata_dev_DMA_sel_msg =
2297 2299 "disabled. Control with \"atapi-cd-dma-enabled\""
2298 2300 " property";
2299 2301
2300 2302 return (ATA_DMA_OFF);
2301 2303 }
2302 2304
2303 2305 } else if (ATAPIDRV(ata_drvp) == FALSE) {
2304 2306 if (disk_dma == FALSE) {
2305 2307 ata_dev_DMA_sel_msg =
2306 2308 "disabled by \"ata-disk-dma-enabled\" property";
2307 2309
2308 2310 return (ATA_DMA_OFF);
2309 2311 }
2310 2312
2311 2313 } else if (atapi_dma == FALSE) {
2312 2314 ata_dev_DMA_sel_msg =
2313 2315 "disabled by \"atapi-other-dma-enabled\" property";
2314 2316
2315 2317 return (ATA_DMA_OFF);
2316 2318 }
2317 2319
2318 2320 return (ATA_DMA_ON);
2319 2321 }
2320 2322
2321 2323
2322 2324
2323 2325 /*
2324 2326 * this compare routine squeezes out extra blanks and
2325 2327 * returns TRUE if p1 matches the leftmost substring of p2
2326 2328 */
2327 2329
2328 2330 static int
2329 2331 ata_strncmp(
2330 2332 char *p1,
2331 2333 char *p2,
2332 2334 int cnt)
2333 2335 {
2334 2336
2335 2337 for (;;) {
2336 2338 /*
2337 2339 * skip over any extra blanks in both strings
2338 2340 */
2339 2341 while (*p1 != '\0' && *p1 == ' ')
2340 2342 p1++;
2341 2343
2342 2344 while (cnt != 0 && *p2 == ' ') {
2343 2345 p2++;
2344 2346 cnt--;
2345 2347 }
2346 2348
2347 2349 /*
2348 2350 * compare the two strings
2349 2351 */
2350 2352
2351 2353 if (cnt == 0 || *p1 != *p2)
2352 2354 break;
2353 2355
2354 2356 while (cnt > 0 && *p1 == *p2) {
2355 2357 p1++;
2356 2358 p2++;
2357 2359 cnt--;
2358 2360 }
2359 2361
2360 2362 }
2361 2363
2362 2364 /* return TRUE if both strings ended at same point */
2363 2365 return ((*p1 == '\0') ? TRUE : FALSE);
2364 2366 }
2365 2367
2366 2368 /*
2367 2369 * Per PSARC/1997/281 create variant="atapi" property (if necessary)
2368 2370 * on the target's dev_info node. Currently, the sd target driver
2369 2371 * is the only driver which refers to this property.
2370 2372 *
2371 2373 * If the flag ata_id_debug is set also create the
2372 2374 * the "ata" or "atapi" property on the target's dev_info node
2373 2375 *
2374 2376 */
2375 2377
2376 2378 int
2377 2379 ata_prop_create(
2378 2380 dev_info_t *tgt_dip,
2379 2381 ata_drv_t *ata_drvp,
2380 2382 char *name)
2381 2383 {
2382 2384 int rc;
2383 2385
2384 2386 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name));
2385 2387
2386 2388 if (strcmp("atapi", name) == 0) {
2387 2389 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip,
2388 2390 "variant", name);
2389 2391 if (rc != DDI_PROP_SUCCESS)
2390 2392 return (FALSE);
2391 2393 }
2392 2394
2393 2395 if (!ata_id_debug)
2394 2396 return (TRUE);
2395 2397
2396 2398 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name,
2397 2399 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id));
2398 2400 if (rc != DDI_PROP_SUCCESS) {
2399 2401 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc));
2400 2402 }
2401 2403 return (TRUE);
2402 2404 }
2403 2405
2404 2406
2405 2407 /* *********************************************************************** */
2406 2408 /* *********************************************************************** */
2407 2409 /* *********************************************************************** */
2408 2410
2409 2411 /*
2410 2412 * This state machine doesn't implement the ATAPI Optional Overlap
2411 2413 * feature. You need that feature to efficiently support ATAPI
2412 2414 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24,
2413 2415 * for an example of how to add the necessary additional NextActions
2414 2416 * and NextStates to this FSM and the atapi_fsm, in order to support
2415 2417 * the Overlap Feature.
2416 2418 */
2417 2419
2418 2420
2419 2421 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = {
2420 2422 /* --------------------- next action --------------------- | - current - */
2421 2423 /* start0 --- start1 ---- intr ------ fini --- reset --- */
2422 2424 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */
2423 2425 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */
2424 2426 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */
2425 2427 };
2426 2428
2427 2429 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = {
2428 2430
2429 2431 /* --------------------- next state --------------------- | - current - */
2430 2432 /* start0 --- start1 ---- intr ------ fini --- reset --- */
2431 2433 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */
2432 2434 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */
2433 2435 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */
2434 2436 };
2435 2437
2436 2438
2437 2439 static int
2438 2440 ata_ctlr_fsm(
2439 2441 uchar_t fsm_func,
2440 2442 ata_ctl_t *ata_ctlp,
2441 2443 ata_drv_t *ata_drvp,
2442 2444 ata_pkt_t *ata_pktp,
2443 2445 int *DoneFlgp)
2444 2446 {
2445 2447 uchar_t action;
2446 2448 uchar_t current_state;
2447 2449 uchar_t next_state;
2448 2450 int rc;
2449 2451
2450 2452 current_state = ata_ctlp->ac_state;
2451 2453 action = ata_ctlr_fsm_NextAction[current_state][fsm_func];
2452 2454 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func];
2453 2455
2454 2456 /*
2455 2457 * Set the controller's new state
2456 2458 */
2457 2459 ata_ctlp->ac_state = next_state;
2458 2460 switch (action) {
2459 2461
2460 2462 case AC_BUSY:
2461 2463 return (ATA_FSM_RC_BUSY);
2462 2464
2463 2465 case AC_NADA:
2464 2466 return (ATA_FSM_RC_OKAY);
2465 2467
2466 2468 case AC_START:
2467 2469 ASSERT(ata_ctlp->ac_active_pktp == NULL);
2468 2470 ASSERT(ata_ctlp->ac_active_drvp == NULL);
2469 2471
2470 2472 ata_ctlp->ac_active_pktp = ata_pktp;
2471 2473 ata_ctlp->ac_active_drvp = ata_drvp;
2472 2474
2473 2475 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp);
2474 2476
2475 2477 if (rc == ATA_FSM_RC_BUSY) {
2476 2478 /* the request didn't start, GHD will requeue it */
2477 2479 ata_ctlp->ac_state = AS_IDLE;
2478 2480 ata_ctlp->ac_active_pktp = NULL;
2479 2481 ata_ctlp->ac_active_drvp = NULL;
2480 2482 }
2481 2483 return (rc);
2482 2484
2483 2485 case AC_INTR:
2484 2486 ASSERT(ata_ctlp->ac_active_pktp != NULL);
2485 2487 ASSERT(ata_ctlp->ac_active_drvp != NULL);
2486 2488
2487 2489 ata_drvp = ata_ctlp->ac_active_drvp;
2488 2490 ata_pktp = ata_ctlp->ac_active_pktp;
2489 2491 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp));
2490 2492
2491 2493 case AC_RESET_A: /* Reset, controller active */
2492 2494 ASSERT(ata_ctlp->ac_active_pktp != NULL);
2493 2495 ASSERT(ata_ctlp->ac_active_drvp != NULL);
2494 2496
2495 2497 /* clean up the active request */
2496 2498 ata_pktp = ata_ctlp->ac_active_pktp;
2497 2499 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET;
2498 2500
2499 2501 /* halt the DMA engine */
2500 2502 if (ata_pktp->ap_pciide_dma) {
2501 2503 ata_pciide_dma_stop(ata_ctlp);
2502 2504 (void) ata_pciide_status_clear(ata_ctlp);
2503 2505 }
2504 2506
2505 2507 /* Do a Software Reset to unwedge the bus */
2506 2508 if (!ata_software_reset(ata_ctlp)) {
2507 2509 return (ATA_FSM_RC_BUSY);
2508 2510 }
2509 2511
2510 2512 /* Then send a DEVICE RESET cmd to each ATAPI device */
2511 2513 atapi_fsm_reset(ata_ctlp);
2512 2514 return (ATA_FSM_RC_FINI);
2513 2515
2514 2516 case AC_RESET_I: /* Reset, controller idle */
2515 2517 /* Do a Software Reset to unwedge the bus */
2516 2518 if (!ata_software_reset(ata_ctlp)) {
2517 2519 return (ATA_FSM_RC_BUSY);
2518 2520 }
2519 2521
2520 2522 /* Then send a DEVICE RESET cmd to each ATAPI device */
2521 2523 atapi_fsm_reset(ata_ctlp);
2522 2524 return (ATA_FSM_RC_OKAY);
2523 2525
2524 2526 case AC_FINI:
2525 2527 break;
2526 2528 }
2527 2529
2528 2530 /*
2529 2531 * AC_FINI, check ARQ needs to be started or finished
2530 2532 */
2531 2533
2532 2534 ASSERT(action == AC_FINI);
2533 2535 ASSERT(ata_ctlp->ac_active_pktp != NULL);
2534 2536 ASSERT(ata_ctlp->ac_active_drvp != NULL);
2535 2537
2536 2538 /*
2537 2539 * The active request is done now.
2538 2540 * Disconnect the request from the controller and
2539 2541 * add it to the done queue.
2540 2542 */
2541 2543 ata_drvp = ata_ctlp->ac_active_drvp;
2542 2544 ata_pktp = ata_ctlp->ac_active_pktp;
2543 2545
2544 2546 /*
2545 2547 * If ARQ pkt is done, get ptr to original pkt and wrap it up.
2546 2548 */
2547 2549 if (ata_pktp == ata_ctlp->ac_arq_pktp) {
2548 2550 ata_pkt_t *arq_pktp;
2549 2551
2550 2552 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp));
2551 2553
2552 2554 arq_pktp = ata_pktp;
2553 2555 ata_pktp = ata_ctlp->ac_fault_pktp;
2554 2556 ata_ctlp->ac_fault_pktp = NULL;
2555 2557 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET))
2556 2558 ata_pktp->ap_flags |= AP_ARQ_ERROR;
2557 2559 else
2558 2560 ata_pktp->ap_flags |= AP_ARQ_OKAY;
2559 2561 goto all_done;
2560 2562 }
2561 2563
2562 2564
2563 2565 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR)
2564 2566
2565 2567 /*
2566 2568 * Start ARQ pkt if necessary
2567 2569 */
2568 2570 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED &&
2569 2571 (ata_pktp->ap_status & ATS_ERR)) {
2570 2572
2571 2573 /* set controller state back to active */
2572 2574 ata_ctlp->ac_state = current_state;
2573 2575
2574 2576 /* try to start the ARQ pkt */
2575 2577 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp);
2576 2578
2577 2579 if (rc == ATA_FSM_RC_BUSY) {
2578 2580 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp));
2579 2581 /* let the target driver handle the problem */
2580 2582 ata_ctlp->ac_state = AS_IDLE;
2581 2583 ata_ctlp->ac_active_pktp = NULL;
2582 2584 ata_ctlp->ac_active_drvp = NULL;
2583 2585 ata_ctlp->ac_fault_pktp = NULL;
2584 2586 goto all_done;
2585 2587 }
2586 2588
2587 2589 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp));
2588 2590 return (rc);
2589 2591 }
2590 2592
2591 2593 /*
2592 2594 * Normal completion, no error status, and not an ARQ pkt,
2593 2595 * just fall through.
2594 2596 */
2595 2597
2596 2598 all_done:
2597 2599
2598 2600 /*
2599 2601 * wrap everything up and tie a ribbon around it
2600 2602 */
2601 2603 ata_ctlp->ac_active_pktp = NULL;
2602 2604 ata_ctlp->ac_active_drvp = NULL;
2603 2605 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) {
2604 2606 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp));
2605 2607 if (DoneFlgp)
2606 2608 *DoneFlgp = TRUE;
2607 2609 }
2608 2610
2609 2611 return (ATA_FSM_RC_OKAY);
2610 2612 }
2611 2613
2612 2614
2613 2615 static int
2614 2616 ata_start_arq(
2615 2617 ata_ctl_t *ata_ctlp,
2616 2618 ata_drv_t *ata_drvp,
2617 2619 ata_pkt_t *ata_pktp)
2618 2620 {
2619 2621 ata_pkt_t *arq_pktp;
2620 2622 int bytes;
2621 2623 uint_t senselen;
2622 2624
2623 2625 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp));
2624 2626
2625 2627 /*
2626 2628 * Determine just the size of the Request Sense Data buffer within
2627 2629 * the scsi_arq_status structure.
2628 2630 */
2629 2631 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \
2630 2632 - sizeof (struct scsi_extended_sense))
2631 2633 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER;
2632 2634 ASSERT(senselen > 0);
2633 2635
2634 2636
2635 2637 /* save ptr to original pkt */
2636 2638 ata_ctlp->ac_fault_pktp = ata_pktp;
2637 2639
2638 2640 /* switch the controller's active pkt to the ARQ pkt */
2639 2641 arq_pktp = ata_ctlp->ac_arq_pktp;
2640 2642 ata_ctlp->ac_active_pktp = arq_pktp;
2641 2643
2642 2644 /* finish initializing the ARQ CDB */
2643 2645 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4;
2644 2646 ata_ctlp->ac_arq_cdb[4] = (uchar_t)senselen;
2645 2647
2646 2648 /* finish initializing the ARQ pkt */
2647 2649 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata;
2648 2650
2649 2651 arq_pktp->ap_resid = senselen;
2650 2652 arq_pktp->ap_flags = AP_ATAPI | AP_READ;
2651 2653 arq_pktp->ap_cdb_pad =
2652 2654 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1;
2653 2655
2654 2656 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ);
2655 2657 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8);
2656 2658 arq_pktp->ap_lwcyl = (uchar_t)bytes;
2657 2659
2658 2660 /*
2659 2661 * This packet is shared by all drives on this controller
2660 2662 * therefore we need to init the drive number on every ARQ.
2661 2663 */
2662 2664 arq_pktp->ap_hd = ata_drvp->ad_drive_bits;
2663 2665
2664 2666 /* start it up */
2665 2667 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp));
2666 2668 }
2667 2669
2668 2670 /*
2669 2671 *
2670 2672 * reset the bus
2671 2673 *
2672 2674 */
2673 2675
2674 2676 static int
2675 2677 ata_reset_bus(
2676 2678 ata_ctl_t *ata_ctlp)
2677 2679 {
2678 2680 int watchdog;
2679 2681 uchar_t drive;
2680 2682 int rc = FALSE;
2681 2683 uchar_t fsm_func;
2682 2684 int DoneFlg = FALSE;
2683 2685
2684 2686 /*
2685 2687 * Do a Software Reset to unwedge the bus, and send
2686 2688 * ATAPI DEVICE RESET to each ATAPI drive.
2687 2689 */
2688 2690 fsm_func = ATA_FSM_RESET;
2689 2691 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) {
2690 2692 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL,
2691 2693 &DoneFlg)) {
2692 2694 case ATA_FSM_RC_OKAY:
2693 2695 rc = TRUE;
2694 2696 goto fsm_done;
2695 2697
2696 2698 case ATA_FSM_RC_BUSY:
2697 2699 return (FALSE);
2698 2700
2699 2701 case ATA_FSM_RC_INTR:
2700 2702 fsm_func = ATA_FSM_INTR;
2701 2703 rc = TRUE;
2702 2704 continue;
2703 2705
2704 2706 case ATA_FSM_RC_FINI:
2705 2707 fsm_func = ATA_FSM_FINI;
2706 2708 rc = TRUE;
2707 2709 continue;
2708 2710 }
2709 2711 }
2710 2712 ADBG_WARN(("ata_reset_bus: watchdog\n"));
2711 2713
2712 2714 fsm_done:
2713 2715
2714 2716 /*
2715 2717 * Reinitialize the ATA drives
2716 2718 */
2717 2719 for (drive = 0; drive < ATA_MAXTARG; drive++) {
2718 2720 ata_drv_t *ata_drvp;
2719 2721
2720 2722 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL)
2721 2723 continue;
2722 2724
2723 2725 if (ATAPIDRV(ata_drvp))
2724 2726 continue;
2725 2727
2726 2728 /*
2727 2729 * Reprogram the Read/Write Multiple block factor
2728 2730 * and current geometry into the drive.
2729 2731 */
2730 2732 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp))
2731 2733 rc = FALSE;
2732 2734 }
2733 2735
2734 2736 /* If DoneFlg is TRUE, it means that ghd_complete() function */
2735 2737 /* has been already called. In this case ignore any errors and */
2736 2738 /* return TRUE to the caller, otherwise return the value of rc */
2737 2739 /* to the caller */
2738 2740 if (DoneFlg)
2739 2741 return (TRUE);
2740 2742 else
2741 2743 return (rc);
2742 2744 }
2743 2745
2744 2746
2745 2747 /*
2746 2748 *
2747 2749 * Low level routine to toggle the Software Reset bit
2748 2750 *
2749 2751 */
2750 2752
2751 2753 static int
2752 2754 ata_software_reset(
2753 2755 ata_ctl_t *ata_ctlp)
2754 2756 {
2755 2757 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1;
2756 2758 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2;
2757 2759 hrtime_t deadline;
2758 2760 uint_t usecs_left;
2759 2761
2760 2762 ADBG_TRACE(("ata_reset_bus entered\n"));
2761 2763
2762 2764 /* disable interrupts and turn the software reset bit on */
2763 2765 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST));
2764 2766
2765 2767 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */
2766 2768 drv_usecwait(30000);
2767 2769
2768 2770 /* turn the software reset bit back off */
2769 2771 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3);
2770 2772
2771 2773 /*
2772 2774 * Wait for the controller to assert BUSY status.
2773 2775 * I don't think 300 msecs is correct. The ATA/ATAPI-4
2774 2776 * spec says 400 nsecs, (and 2 msecs if device
2775 2777 * was in sleep mode; but we don't put drives to sleep
2776 2778 * so it probably doesn't matter).
2777 2779 */
2778 2780 drv_usecwait(300000);
2779 2781
2780 2782 /*
2781 2783 * If drive 0 exists the test for completion is simple
2782 2784 */
2783 2785 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC);
2784 2786
2785 2787 if (CTL2DRV(ata_ctlp, 0, 0)) {
2786 2788 goto wait_for_not_busy;
2787 2789 }
2788 2790
2789 2791 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL);
2790 2792
2791 2793 /*
2792 2794 * This must be a single device configuration, with drive 1
2793 2795 * only. This complicates the test for completion because
2794 2796 * issuing the software reset just caused drive 1 to
2795 2797 * deselect. With drive 1 deselected, if I just read the
2796 2798 * status register to test the BSY bit I get garbage, but
2797 2799 * I can't re-select drive 1 until I'm certain the BSY bit
2798 2800 * is de-asserted. Catch-22.
2799 2801 *
2800 2802 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle
2801 2803 * this situation like this:
2802 2804 */
2803 2805
2804 2806 /* give up if the drive doesn't settle within 31 seconds */
2805 2807 while (gethrtime() < deadline) {
2806 2808 /*
2807 2809 * delay 10msec each time around the loop
2808 2810 */
2809 2811 drv_usecwait(10000);
2810 2812
2811 2813 /*
2812 2814 * try to select drive 1
2813 2815 */
2814 2816 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1);
2815 2817
2816 2818 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55);
2817 2819 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa);
2818 2820 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa)
2819 2821 continue;
2820 2822
2821 2823 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55);
2822 2824 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa);
2823 2825 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa)
2824 2826 continue;
2825 2827
2826 2828 goto wait_for_not_busy;
2827 2829 }
2828 2830 return (FALSE);
2829 2831
2830 2832 wait_for_not_busy:
2831 2833
2832 2834 /*
2833 2835 * Now wait up to 31 seconds for BUSY to clear.
2834 2836 */
2835 2837 usecs_left = (deadline - gethrtime()) / 1000;
2836 2838 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY,
2837 2839 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left);
2838 2840
2839 2841 return (TRUE);
2840 2842 }
2841 2843
2842 2844 /*
2843 2845 *
2844 2846 * DDI interrupt handler
2845 2847 *
2846 2848 */
2847 2849
2848 2850 static uint_t
2849 2851 ata_intr(
2850 2852 caddr_t arg)
2851 2853 {
2852 2854 ata_ctl_t *ata_ctlp;
2853 2855 int one_shot = 1;
2854 2856
2855 2857 ata_ctlp = (ata_ctl_t *)arg;
2856 2858
2857 2859 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot));
2858 2860 }
2859 2861
2860 2862
2861 2863 /*
2862 2864 *
2863 2865 * GHD ccc_get_status callback
2864 2866 *
2865 2867 */
2866 2868
2867 2869 static int
2868 2870 ata_get_status(
2869 2871 void *hba_handle,
2870 2872 void *intr_status)
2871 2873 {
2872 2874 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle;
2873 2875 uchar_t status;
2874 2876
2875 2877 ADBG_TRACE(("ata_get_status entered\n"));
2876 2878
2877 2879 /*
2878 2880 * ignore interrupts before ata_attach completes
2879 2881 */
2880 2882 if (!(ata_ctlp->ac_flags & AC_ATTACHED))
2881 2883 return (FALSE);
2882 2884
2883 2885 /*
2884 2886 * can't be interrupt pending if nothing active
2885 2887 */
2886 2888 switch (ata_ctlp->ac_state) {
2887 2889 case AS_IDLE:
2888 2890 return (FALSE);
2889 2891 case AS_ACTIVE0:
2890 2892 case AS_ACTIVE1:
2891 2893 ASSERT(ata_ctlp->ac_active_drvp != NULL);
2892 2894 ASSERT(ata_ctlp->ac_active_pktp != NULL);
2893 2895 break;
2894 2896 }
2895 2897
2896 2898 /*
2897 2899 * If this is a PCI-IDE controller, check the PCI-IDE controller's
2898 2900 * interrupt status latch. But don't clear it yet.
2899 2901 *
2900 2902 * AC_BMSTATREG_PIO_BROKEN flag is used currently for
2901 2903 * CMD chips with device id 0x646. Since the interrupt bit on
2902 2904 * Bus master IDE register is not usable when in PIO mode,
2903 2905 * this chip is treated as a legacy device for interrupt
2904 2906 * indication. The following code for CMD
2905 2907 * chips may need to be revisited when we enable support for dma.
2906 2908 *
2907 2909 * CHANGE: DMA is not disabled for these devices. BM intr bit is
2908 2910 * checked only if there was DMA used or BM intr is useable on PIO,
2909 2911 * else treat it as before - as legacy device.
2910 2912 */
2911 2913
2912 2914 if ((ata_ctlp->ac_pciide) &&
2913 2915 ((ata_ctlp->ac_pciide_bm != FALSE) &&
2914 2916 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) ||
2915 2917 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) {
2916 2918
2917 2919 if (!ata_pciide_status_pending(ata_ctlp))
2918 2920 return (FALSE);
2919 2921 } else {
2920 2922 /*
2921 2923 * Interrupts from legacy ATA/IDE controllers are
2922 2924 * edge-triggered but the dumb legacy ATA/IDE controllers
2923 2925 * and drives don't have an interrupt status bit.
2924 2926 *
2925 2927 * Use a one_shot variable to make sure we only return
2926 2928 * one status per interrupt.
2927 2929 */
2928 2930 if (intr_status != NULL) {
2929 2931 int *one_shot = (int *)intr_status;
2930 2932
2931 2933 if (*one_shot == 1)
2932 2934 *one_shot = 0;
2933 2935 else
2934 2936 return (FALSE);
2935 2937 }
2936 2938 }
2937 2939
2938 2940 /* check if device is still busy */
2939 2941
2940 2942 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus);
2941 2943 if (status & ATS_BSY)
2942 2944 return (FALSE);
2943 2945 return (TRUE);
2944 2946 }
2945 2947
2946 2948
2947 2949 /*
2948 2950 *
2949 2951 * get the current status and clear the IRQ
2950 2952 *
2951 2953 */
2952 2954
2953 2955 int
2954 2956 ata_get_status_clear_intr(
2955 2957 ata_ctl_t *ata_ctlp,
2956 2958 ata_pkt_t *ata_pktp)
2957 2959 {
2958 2960 uchar_t status;
2959 2961
2960 2962 /*
2961 2963 * Here's where we clear the PCI-IDE interrupt latch. If this
2962 2964 * request used DMA mode then we also have to check and clear
2963 2965 * the DMA error latch at the same time.
2964 2966 */
2965 2967
2966 2968 if (ata_pktp->ap_pciide_dma) {
2967 2969 if (ata_pciide_status_dmacheck_clear(ata_ctlp))
2968 2970 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR;
2969 2971 } else if ((ata_ctlp->ac_pciide) &&
2970 2972 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) {
2971 2973 /*
2972 2974 * Some requests don't use DMA mode and therefore won't
2973 2975 * set the DMA error latch, but we still have to clear
2974 2976 * the interrupt latch.
2975 2977 * Controllers with broken BM intr in PIO mode do not go
2976 2978 * through this path.
2977 2979 */
2978 2980 (void) ata_pciide_status_clear(ata_ctlp);
2979 2981 }
2980 2982
2981 2983 /*
2982 2984 * this clears the drive's interrupt
2983 2985 */
2984 2986 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status);
2985 2987 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status));
2986 2988 return (status);
2987 2989 }
2988 2990
2989 2991
2990 2992
2991 2993 /*
2992 2994 *
2993 2995 * GHD interrupt handler
2994 2996 *
2995 2997 */
2996 2998
2997 2999 /* ARGSUSED */
2998 3000 static void
2999 3001 ata_process_intr(
3000 3002 void *hba_handle,
3001 3003 void *intr_status)
3002 3004 {
3003 3005 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle;
3004 3006 int watchdog;
3005 3007 uchar_t fsm_func;
3006 3008 int rc;
3007 3009
3008 3010 ADBG_TRACE(("ata_process_intr entered\n"));
3009 3011
3010 3012 /*
3011 3013 * process the ATA or ATAPI interrupt
3012 3014 */
3013 3015
3014 3016 fsm_func = ATA_FSM_INTR;
3015 3017 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) {
3016 3018 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL);
3017 3019
3018 3020 switch (rc) {
3019 3021 case ATA_FSM_RC_OKAY:
3020 3022 return;
3021 3023
3022 3024 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */
3023 3025 return;
3024 3026
3025 3027 case ATA_FSM_RC_INTR: /* re-invoke the FSM */
3026 3028 fsm_func = ATA_FSM_INTR;
3027 3029 break;
3028 3030
3029 3031 case ATA_FSM_RC_FINI: /* move a request to done Q */
3030 3032 fsm_func = ATA_FSM_FINI;
3031 3033 break;
3032 3034 }
3033 3035 }
3034 3036 ADBG_WARN(("ata_process_intr: watchdog\n"));
3035 3037 }
3036 3038
3037 3039
3038 3040
3039 3041 /*
3040 3042 *
3041 3043 * GHD ccc_hba_start callback
3042 3044 *
3043 3045 */
3044 3046
3045 3047 static int
3046 3048 ata_hba_start(
3047 3049 void *hba_handle,
3048 3050 gcmd_t *gcmdp)
3049 3051 {
3050 3052 ata_ctl_t *ata_ctlp;
3051 3053 ata_drv_t *ata_drvp;
3052 3054 ata_pkt_t *ata_pktp;
3053 3055 uchar_t fsm_func;
3054 3056 int request_started;
3055 3057 int watchdog;
3056 3058
3057 3059 ADBG_TRACE(("ata_hba_start entered\n"));
3058 3060
3059 3061 ata_ctlp = (ata_ctl_t *)hba_handle;
3060 3062
3061 3063 if (ata_ctlp->ac_active_drvp != NULL) {
3062 3064 ADBG_WARN(("ata_hba_start drvp not null\n"));
3063 3065 return (FALSE);
3064 3066 }
3065 3067 if (ata_ctlp->ac_active_pktp != NULL) {
3066 3068 ADBG_WARN(("ata_hba_start pktp not null\n"));
3067 3069 return (FALSE);
3068 3070 }
3069 3071
3070 3072 ata_pktp = GCMD2APKT(gcmdp);
3071 3073 ata_drvp = GCMD2DRV(gcmdp);
3072 3074
3073 3075 /*
3074 3076 * which drive?
3075 3077 */
3076 3078 if (ata_drvp->ad_targ == 0)
3077 3079 fsm_func = ATA_FSM_START0;
3078 3080 else
3079 3081 fsm_func = ATA_FSM_START1;
3080 3082
3081 3083 /*
3082 3084 * start the request
3083 3085 */
3084 3086 request_started = FALSE;
3085 3087 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) {
3086 3088 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp,
3087 3089 NULL)) {
3088 3090 case ATA_FSM_RC_OKAY:
3089 3091 request_started = TRUE;
3090 3092 goto fsm_done;
3091 3093
3092 3094 case ATA_FSM_RC_BUSY:
3093 3095 /* if first time, tell GHD to requeue the request */
3094 3096 goto fsm_done;
3095 3097
3096 3098 case ATA_FSM_RC_INTR:
3097 3099 /*
3098 3100 * The start function polled for the next
3099 3101 * bus phase, now fake an interrupt to process
3100 3102 * the next action.
3101 3103 */
3102 3104 request_started = TRUE;
3103 3105 fsm_func = ATA_FSM_INTR;
3104 3106 ata_drvp = NULL;
3105 3107 ata_pktp = NULL;
3106 3108 break;
3107 3109
3108 3110 case ATA_FSM_RC_FINI: /* move request to the done queue */
3109 3111 request_started = TRUE;
3110 3112 fsm_func = ATA_FSM_FINI;
3111 3113 ata_drvp = NULL;
3112 3114 ata_pktp = NULL;
3113 3115 break;
3114 3116 }
3115 3117 }
3116 3118 ADBG_WARN(("ata_hba_start: watchdog\n"));
3117 3119
3118 3120 fsm_done:
3119 3121 return (request_started);
3120 3122
3121 3123 }
3122 3124
3123 3125 static int
3124 3126 ata_check_pciide_blacklist(
3125 3127 dev_info_t *dip,
3126 3128 uint_t flags)
3127 3129 {
3128 3130 ushort_t vendorid;
3129 3131 ushort_t deviceid;
3130 3132 pcibl_t *blp;
3131 3133 int *propp;
3132 3134 uint_t count;
3133 3135 int rc;
3134 3136
3135 3137
3136 3138 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
3137 3139 DDI_PROP_DONTPASS, "vendor-id", 0);
3138 3140 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
3139 3141 DDI_PROP_DONTPASS, "device-id", 0);
3140 3142
3141 3143 /*
3142 3144 * first check for a match in the "pci-ide-blacklist" property
3143 3145 */
3144 3146 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0,
3145 3147 "pci-ide-blacklist", &propp, &count);
3146 3148
3147 3149 if (rc == DDI_PROP_SUCCESS) {
3148 3150 count = (count * sizeof (uint_t)) / sizeof (pcibl_t);
3149 3151 blp = (pcibl_t *)propp;
3150 3152 while (count--) {
3151 3153 /* check for matching ID */
3152 3154 if ((vendorid & blp->b_vmask)
3153 3155 != (blp->b_vendorid & blp->b_vmask)) {
3154 3156 blp++;
3155 3157 continue;
3156 3158 }
3157 3159 if ((deviceid & blp->b_dmask)
3158 3160 != (blp->b_deviceid & blp->b_dmask)) {
3159 3161 blp++;
3160 3162 continue;
3161 3163 }
3162 3164
3163 3165 /* got a match */
3164 3166 if (blp->b_flags & flags) {
3165 3167 ddi_prop_free(propp);
3166 3168 return (TRUE);
3167 3169 } else {
3168 3170 ddi_prop_free(propp);
3169 3171 return (FALSE);
3170 3172 }
3171 3173 }
3172 3174 ddi_prop_free(propp);
3173 3175 }
3174 3176
3175 3177 /*
3176 3178 * then check the built-in blacklist
3177 3179 */
3178 3180 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) {
3179 3181 if ((vendorid & blp->b_vmask) != blp->b_vendorid)
3180 3182 continue;
3181 3183 if ((deviceid & blp->b_dmask) != blp->b_deviceid)
3182 3184 continue;
3183 3185 if (!(blp->b_flags & flags))
3184 3186 continue;
3185 3187 return (TRUE);
3186 3188 }
3187 3189 return (FALSE);
3188 3190 }
3189 3191
3190 3192 int
3191 3193 ata_check_drive_blacklist(
3192 3194 struct ata_id *aidp,
3193 3195 uint_t flags)
3194 3196 {
3195 3197 atabl_t *blp;
3196 3198
3197 3199 for (blp = ata_drive_blacklist; blp->b_model != NULL; blp++) {
3198 3200 if (!ata_strncmp(blp->b_model, aidp->ai_model,
3199 3201 sizeof (aidp->ai_model)))
3200 3202 continue;
3201 3203 if (blp->b_fw != NULL) {
3202 3204 if (!ata_strncmp(blp->b_fw, aidp->ai_fw,
3203 3205 sizeof (aidp->ai_fw)))
3204 3206 continue;
3205 3207 }
3206 3208 if (blp->b_flags & flags)
3207 3209 return (TRUE);
3208 3210 return (FALSE);
3209 3211 }
3210 3212 return (FALSE);
3211 3213 }
3212 3214
3213 3215 /*
3214 3216 * Queue a request to perform some sort of internally
3215 3217 * generated command. When this request packet reaches
3216 3218 * the front of the queue (*func)() is invoked.
3217 3219 *
3218 3220 */
3219 3221
3220 3222 int
3221 3223 ata_queue_cmd(
3222 3224 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *),
3223 3225 void *arg,
3224 3226 ata_ctl_t *ata_ctlp,
3225 3227 ata_drv_t *ata_drvp,
3226 3228 gtgt_t *gtgtp)
3227 3229 {
3228 3230 ata_pkt_t *ata_pktp;
3229 3231 gcmd_t *gcmdp;
3230 3232 int rc;
3231 3233
3232 3234 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) {
3233 3235 ADBG_ERROR(("atapi_id_update alloc failed\n"));
3234 3236 return (FALSE);
3235 3237 }
3236 3238
3237 3239
3238 3240 /* set the back ptr from the ata_pkt to the gcmd_t */
3239 3241 ata_pktp = GCMD2APKT(gcmdp);
3240 3242 ata_pktp->ap_gcmdp = gcmdp;
3241 3243 ata_pktp->ap_hd = ata_drvp->ad_drive_bits;
3242 3244 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block;
3243 3245
3244 3246 /*
3245 3247 * over-ride the default start function
3246 3248 */
3247 3249 ata_pktp = GCMD2APKT(gcmdp);
3248 3250 ata_pktp->ap_start = func;
3249 3251 ata_pktp->ap_complete = NULL;
3250 3252 ata_pktp->ap_v_addr = (caddr_t)arg;
3251 3253
3252 3254 /*
3253 3255 * add it to the queue, when it gets to the front the
3254 3256 * ap_start function is called.
3255 3257 */
3256 3258 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp,
3257 3259 0, TRUE, NULL);
3258 3260
3259 3261 if (rc != TRAN_ACCEPT) {
3260 3262 /* this should never, ever happen */
3261 3263 return (FALSE);
3262 3264 }
3263 3265
3264 3266 if (ata_pktp->ap_flags & AP_ERROR)
3265 3267 return (FALSE);
3266 3268 return (TRUE);
3267 3269 }
3268 3270
3269 3271 /*
3270 3272 * Check if this drive has the "revert to defaults" bug
3271 3273 * PSARC 2001/500 and 2001/xxx - check for the properties
3272 3274 * ata-revert-to-defaults and atarvrt-<diskmodel> before
3273 3275 * examining the blacklist.
3274 3276 * <diskmodel> is made from the model number reported by Identify Drive
3275 3277 * with uppercase letters converted to lowercase and all characters
3276 3278 * except letters, digits, ".", "_", and "-" deleted.
3277 3279 * Return value:
3278 3280 * TRUE: enable revert to defaults
3279 3281 * FALSE: disable revert to defaults
3280 3282 *
3281 3283 * NOTE: revert to power on defaults that includes reverting to MDMA
3282 3284 * mode is allowed by ATA-6 & ATA-7 specs.
3283 3285 * Therefore drives exhibiting this behaviour are not violating the spec.
3284 3286 * Furthermore, the spec explicitly says that after the soft reset
3285 3287 * host should check the current setting of the device features.
3286 3288 * Correctly working BIOS would therefore reprogram either the drive
3287 3289 * and/or the host controller to match transfer modes.
3288 3290 * Devices with ATA_BL_NORVRT flag will be removed from
3289 3291 * the ata_blacklist.
3290 3292 * The default behaviour will be - no revert to power-on defaults
3291 3293 * for all devices. The property is retained in case the user
3292 3294 * explicitly requests revert-to-defaults before reboot.
3293 3295 */
3294 3296
3295 3297 #define ATA_REVERT_PROP_PREFIX "revert-"
3296 3298 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults"
3297 3299 /* room for prefix + model number + terminating NUL character */
3298 3300 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \
3299 3301 sizeof (aidp->ai_model) + 1)
3300 3302 #define PROP_LEN_MAX (31)
3301 3303
3302 3304 static int
3303 3305 ata_check_revert_to_defaults(
3304 3306 ata_drv_t *ata_drvp)
3305 3307 {
3306 3308 struct ata_id *aidp = &ata_drvp->ad_id;
3307 3309 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp;
3308 3310 char prop_buf[PROP_BUF_SIZE];
3309 3311 int i, j;
3310 3312 int propval;
3311 3313
3312 3314 /* put prefix into the buffer */
3313 3315 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX);
3314 3316 j = strlen(prop_buf);
3315 3317
3316 3318 /* append the model number, leaving out invalid characters */
3317 3319 for (i = 0; i < sizeof (aidp->ai_model); ++i) {
3318 3320 char c = aidp->ai_model[i];
3319 3321 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */
3320 3322 c = c - 'A' + 'a';
3321 3323 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' ||
3322 3324 c == '.' || c == '_' || c == '-')
3323 3325 prop_buf[j++] = c;
3324 3326 if (c == '\0')
3325 3327 break;
3326 3328 }
3327 3329
3328 3330 /* make sure there's a terminating NUL character */
3329 3331 if (j >= PROP_LEN_MAX)
3330 3332 j = PROP_LEN_MAX;
3331 3333 prop_buf[j] = '\0';
3332 3334
3333 3335 /* look for a disk-specific "revert" property" */
3334 3336 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip,
3335 3337 DDI_PROP_DONTPASS, prop_buf, -1);
3336 3338 if (propval == 0)
3337 3339 return (FALSE);
3338 3340 else if (propval != -1)
3339 3341 return (TRUE);
3340 3342
3341 3343 /* look for a global "revert" property" */
3342 3344 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip,
3343 3345 0, ATA_REVERT_PROP_GLOBAL, -1);
3344 3346 if (propval == 0)
3345 3347 return (FALSE);
3346 3348 else if (propval != -1)
3347 3349 return (TRUE);
3348 3350
3349 3351 return (FALSE);
3350 3352 }
3351 3353
3352 3354 void
3353 3355 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp)
3354 3356 {
3355 3357 int i;
3356 3358
3357 3359 if (ata_ctlp->ac_pciide_bm == FALSE ||
3358 3360 ata_drvp->ad_pciide_dma != ATA_DMA_ON) {
3359 3361 if (ata_cntrl_DMA_sel_msg) {
3360 3362 ATAPRT((
3361 3363 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg));
3362 3364 } else if (ata_dev_DMA_sel_msg) {
3363 3365 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg));
3364 3366 }
3365 3367 ATAPRT(("?\tPIO mode %d selected\n",
3366 3368 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) ==
3367 3369 ATAC_ADVPIO_4_SUP ? 4 : 3));
3368 3370 } else {
3369 3371 /* Using DMA */
3370 3372 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) {
3371 3373 /*
3372 3374 * Rely on the fact that either dwdma or udma is
3373 3375 * selected, not both.
3374 3376 */
3375 3377 ATAPRT(("?\tMultiwordDMA mode %d selected\n",
3376 3378 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) ==
3377 3379 ATAC_MDMA_2_SEL ? 2 :
3378 3380 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) ==
3379 3381 ATAC_MDMA_1_SEL ? 1 : 0));
3380 3382 } else {
3381 3383 for (i = 0; i <= 6; i++) {
3382 3384 if (ata_drvp->ad_id.ai_ultradma &
3383 3385 (1 << (i + 8))) {
3384 3386 ATAPRT((
3385 3387 "?\tUltraDMA mode %d selected\n",
3386 3388 i));
3387 3389 break;
3388 3390 }
3389 3391 }
3390 3392 }
3391 3393 }
3392 3394 }
3393 3395
3394 3396 /*
3395 3397 * Controller-specific operation pointers.
3396 3398 * Should be extended as needed - init only for now
3397 3399 */
3398 3400 struct ata_ctl_spec_ops {
3399 3401 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */
3400 3402 };
3401 3403
3402 3404
3403 3405 struct ata_ctl_spec {
3404 3406 ushort_t cs_vendor_id;
3405 3407 ushort_t cs_device_id;
3406 3408 struct ata_ctl_spec_ops *cs_ops;
3407 3409 };
3408 3410
3409 3411 /* Sil3XXX-specific functions (init only for now) */
3410 3412 struct ata_ctl_spec_ops sil3xxx_ops = {
3411 3413 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */
3412 3414 };
3413 3415
3414 3416
3415 3417 struct ata_ctl_spec ata_cntrls_spec[] = {
3416 3418 {0x1095, 0x3114, &sil3xxx_ops},
3417 3419 {0x1095, 0x3512, &sil3xxx_ops},
3418 3420 {0x1095, 0x3112, &sil3xxx_ops},
3419 3421 {0, 0, NULL} /* List must end with cs_ops set to NULL */
3420 3422 };
3421 3423
3422 3424 /*
3423 3425 * Do controller specific initialization if necessary.
3424 3426 * Pick-up controller specific functions.
3425 3427 */
3426 3428
3427 3429 int
3428 3430 ata_spec_init_controller(dev_info_t *dip)
3429 3431 {
3430 3432 ushort_t vendor_id;
3431 3433 ushort_t device_id;
3432 3434 struct ata_ctl_spec *ctlsp;
3433 3435
3434 3436 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
3435 3437 DDI_PROP_DONTPASS, "vendor-id", 0);
3436 3438 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
3437 3439 DDI_PROP_DONTPASS, "device-id", 0);
3438 3440
3439 3441 /* Locate controller specific ops, if they exist */
3440 3442 ctlsp = ata_cntrls_spec;
3441 3443 while (ctlsp->cs_ops != NULL) {
3442 3444 if (ctlsp->cs_vendor_id == vendor_id &&
3443 3445 ctlsp->cs_device_id == device_id)
3444 3446 break;
3445 3447 ctlsp++;
3446 3448 }
3447 3449
3448 3450 if (ctlsp->cs_ops != NULL) {
3449 3451 if (ctlsp->cs_ops->cs_init != NULL) {
3450 3452 /* Initialize controller */
3451 3453 if ((*(ctlsp->cs_ops->cs_init))
3452 3454 (dip, vendor_id, device_id) != TRUE) {
3453 3455 cmn_err(CE_WARN,
3454 3456 "pci%4x,%4x cntrl specific "
3455 3457 "initialization failed",
3456 3458 vendor_id, device_id);
3457 3459 return (FALSE);
3458 3460 }
3459 3461 }
3460 3462 }
3461 3463 return (TRUE);
3462 3464 }
3463 3465
3464 3466 /*
3465 3467 * this routine works like ddi_prop_get_int, except that it works on
3466 3468 * a string property that contains ascii representations
3467 3469 * of an integer.
3468 3470 * If the property is not found, the default value is returned.
3469 3471 */
3470 3472 static int
3471 3473 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip,
3472 3474 uint_t flags, char *name, int defvalue)
3473 3475 {
3474 3476
3475 3477 char *bufp, *cp;
3476 3478 int rc = defvalue;
3477 3479 int proprc;
3478 3480
3479 3481 proprc = ddi_prop_lookup_string(match_dev, dip,
3480 3482 flags, name, &bufp);
3481 3483
3482 3484 if (proprc == DDI_PROP_SUCCESS) {
3483 3485 cp = bufp;
3484 3486 rc = stoi(&cp);
3485 3487 ddi_prop_free(bufp);
3486 3488 } else {
3487 3489 /*
3488 3490 * see if property is encoded as an int instead of string.
3489 3491 */
3490 3492 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue);
3491 3493 }
|
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3457 lines elided |
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3492 3494
3493 3495 return (rc);
3494 3496 }
3495 3497
3496 3498 /*
3497 3499 * Initialize the power management components
3498 3500 */
3499 3501 static void
3500 3502 ata_init_pm(dev_info_t *dip)
3501 3503 {
3504 + int instance;
3505 + ata_ctl_t *ata_ctlp;
3506 +#ifdef ATA_USE_AUTOPM
3502 3507 char pmc_name[16];
3503 3508 char *pmc[] = {
3504 3509 NULL,
3505 3510 "0=Sleep (PCI D3 State)",
3506 3511 "3=PowerOn (PCI D0 State)",
3507 3512 NULL
3508 3513 };
3509 - int instance;
3510 - ata_ctl_t *ata_ctlp;
3514 +#endif
3511 3515
3512 3516
3513 3517 instance = ddi_get_instance(dip);
3514 3518 ata_ctlp = ddi_get_soft_state(ata_state, instance);
3515 3519 ata_ctlp->ac_pm_support = 0;
3516 3520
3517 3521 /* check PCI capabilities */
3518 3522 if (!ata_is_pci(dip))
3519 3523 return;
3520 3524
3525 +#ifdef ATA_USE_AUTOPM
3521 3526 (void) sprintf(pmc_name, "NAME=ata%d", instance);
3522 3527 pmc[0] = pmc_name;
3523 3528
3524 -#ifdef ATA_USE_AUTOPM
3525 3529 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip,
3526 3530 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
3527 3531 return;
3528 3532 }
3529 3533 #endif
3530 3534
3531 3535 ata_ctlp->ac_pm_support = 1;
3532 3536 ata_ctlp->ac_pm_level = PM_LEVEL_D0;
3533 3537
3534 3538 ATA_BUSY_COMPONENT(dip, 0);
3535 3539 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
3536 3540 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components");
3537 3541 }
3538 3542 ATA_IDLE_COMPONENT(dip, 0);
3539 3543 }
3540 3544
3541 3545 /*
3542 3546 * resume the hard drive
3543 3547 */
3544 3548 static void
3545 3549 ata_resume_drive(ata_drv_t *ata_drvp)
3546 3550 {
3547 3551 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp;
3548 3552 int drive_type;
3549 3553 struct ata_id id;
3550 3554
3551 3555 ADBG_TRACE(("ata_resume_drive entered\n"));
3552 3556
3553 3557 drive_type = ata_drive_type(ata_drvp->ad_drive_bits,
3554 3558 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1,
3555 3559 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2,
3556 3560 &id);
3557 3561 if (drive_type == ATA_DEV_NONE)
3558 3562 return;
3559 3563
3560 3564 if (!ATAPIDRV(ata_drvp)) {
3561 3565 /* Reset Ultra DMA mode */
3562 3566 ata_reset_dma_mode(ata_drvp);
3563 3567 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp))
3564 3568 return;
3565 3569 } else {
3566 3570 (void) atapi_init_drive(ata_drvp);
3567 3571 if (ata_drvp->ad_dma_mode != 0) {
3568 3572 (void) atapi_reset_dma_mode(ata_drvp, FALSE);
3569 3573 if (!ata_check_dma_mode(ata_drvp))
3570 3574 atapi_reset_dma_mode(ata_drvp, TRUE);
3571 3575 if (ata_drvp->ad_id.ai_ultradma !=
3572 3576 ata_drvp->ad_dma_mode) {
3573 3577 ata_drvp->ad_pciide_dma = ATA_DMA_OFF;
3574 3578 } else {
3575 3579 ata_drvp->ad_pciide_dma = ATA_DMA_ON;
3576 3580 }
3577 3581 }
3578 3582 }
3579 3583 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0);
3580 3584
3581 3585 }
3582 3586
3583 3587 /*
3584 3588 * resume routine, it will be run when get the command
3585 3589 * DDI_RESUME at attach(9E) from system power management
3586 3590 */
3587 3591 static int
3588 3592 ata_resume(dev_info_t *dip)
3589 3593 {
3590 3594 int instance;
3591 3595 ata_ctl_t *ata_ctlp;
3592 3596 ddi_acc_handle_t io_hdl2;
3593 3597 caddr_t ioaddr2;
3594 3598
3595 3599 instance = ddi_get_instance(dip);
3596 3600 ata_ctlp = ddi_get_soft_state(ata_state, instance);
3597 3601
3598 3602 if (!ata_ctlp->ac_pm_support)
3599 3603 return (DDI_FAILURE);
3600 3604 if (ata_ctlp->ac_pm_level == PM_LEVEL_D0)
3601 3605 return (DDI_SUCCESS);
3602 3606
3603 3607 ATA_BUSY_COMPONENT(dip, 0);
3604 3608 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE)
3605 3609 return (DDI_FAILURE);
3606 3610 ATA_IDLE_COMPONENT(dip, 0);
3607 3611
3608 3612 /* enable interrupts from the device */
3609 3613 io_hdl2 = ata_ctlp->ac_iohandle2;
3610 3614 ioaddr2 = ata_ctlp->ac_ioaddr2;
3611 3615 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3);
3612 3616 ata_ctlp->ac_pm_level = PM_LEVEL_D0;
3613 3617
3614 3618 return (DDI_SUCCESS);
3615 3619 }
3616 3620
3617 3621 /*
3618 3622 * suspend routine, it will be run when get the command
3619 3623 * DDI_SUSPEND at detach(9E) from system power management
3620 3624 */
3621 3625 static int
3622 3626 ata_suspend(dev_info_t *dip)
3623 3627 {
3624 3628 int instance;
3625 3629 ata_ctl_t *ata_ctlp;
3626 3630 ddi_acc_handle_t io_hdl2;
3627 3631
3628 3632 instance = ddi_get_instance(dip);
3629 3633 ata_ctlp = ddi_get_soft_state(ata_state, instance);
3630 3634
3631 3635 if (!ata_ctlp->ac_pm_support)
3632 3636 return (DDI_FAILURE);
3633 3637 if (ata_ctlp->ac_pm_level == PM_LEVEL_D3)
3634 3638 return (DDI_SUCCESS);
3635 3639
3636 3640 /* disable interrupts and turn the software reset bit on */
3637 3641 io_hdl2 = ata_ctlp->ac_iohandle2;
3638 3642 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST));
3639 3643
3640 3644 (void) ata_reset_bus(ata_ctlp);
3641 3645 (void) ata_change_power(dip, ATC_SLEEP);
3642 3646 ata_ctlp->ac_pm_level = PM_LEVEL_D3;
3643 3647 return (DDI_SUCCESS);
3644 3648 }
3645 3649
3646 3650 int ata_save_pci_config = 0;
3647 3651 /*
3648 3652 * ata specific power management entry point, it was
3649 3653 * used to change the power management component
3650 3654 */
3651 3655 static int
3652 3656 ata_power(dev_info_t *dip, int component, int level)
3653 3657 {
3654 3658 int instance;
3655 3659 ata_ctl_t *ata_ctlp;
3656 3660 uint8_t cmd;
3657 3661
3658 3662 ADBG_TRACE(("ata_power entered, component = %d, level = %d\n",
3659 3663 component, level));
3660 3664
3661 3665 instance = ddi_get_instance(dip);
3662 3666 ata_ctlp = ddi_get_soft_state(ata_state, instance);
3663 3667 if (ata_ctlp == NULL || component != 0)
3664 3668 return (DDI_FAILURE);
3665 3669
3666 3670 if (!ata_ctlp->ac_pm_support)
3667 3671 return (DDI_FAILURE);
3668 3672
3669 3673 if (ata_ctlp->ac_pm_level == level)
3670 3674 return (DDI_SUCCESS);
3671 3675
3672 3676 switch (level) {
3673 3677 case PM_LEVEL_D0:
3674 3678 if (ata_save_pci_config)
3675 3679 (void) pci_restore_config_regs(dip);
3676 3680 ata_ctlp->ac_pm_level = PM_LEVEL_D0;
3677 3681 cmd = ATC_IDLE_IMMED;
3678 3682 break;
3679 3683 case PM_LEVEL_D3:
3680 3684 if (ata_save_pci_config)
3681 3685 (void) pci_save_config_regs(dip);
3682 3686 ata_ctlp->ac_pm_level = PM_LEVEL_D3;
3683 3687 cmd = ATC_SLEEP;
3684 3688 break;
3685 3689 default:
3686 3690 return (DDI_FAILURE);
3687 3691 }
3688 3692 return (ata_change_power(dip, cmd));
3689 3693 }
3690 3694
3691 3695 /*
3692 3696 * sent commands to ata controller to change the power level
3693 3697 */
3694 3698 static int
3695 3699 ata_change_power(dev_info_t *dip, uint8_t cmd)
3696 3700 {
3697 3701 int instance;
3698 3702 ata_ctl_t *ata_ctlp;
3699 3703 ata_drv_t *ata_drvp;
3700 3704 uchar_t targ;
3701 3705 struct ata_id id;
3702 3706 uchar_t lun;
3703 3707 uchar_t lastlun;
3704 3708 struct ata_id *aidp;
3705 3709
3706 3710 ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd));
3707 3711
3708 3712 instance = ddi_get_instance(dip);
3709 3713 ata_ctlp = ddi_get_soft_state(ata_state, instance);
3710 3714
3711 3715 /*
3712 3716 * Issue command on each disk device on the bus.
3713 3717 */
3714 3718 if (cmd == ATC_SLEEP) {
3715 3719 for (targ = 0; targ < ATA_MAXTARG; targ++) {
3716 3720 ata_drvp = CTL2DRV(ata_ctlp, targ, 0);
3717 3721 if (ata_drvp == NULL)
3718 3722 continue;
3719 3723 if (ata_drvp->ad_dma_cap == 0 &&
3720 3724 ata_drvp->ad_pciide_dma == ATA_DMA_ON) {
3721 3725 aidp = &ata_drvp->ad_id;
3722 3726 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) &&
3723 3727 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) {
3724 3728 ata_drvp->ad_dma_cap =
3725 3729 ATA_DMA_ULTRAMODE;
3726 3730 ata_drvp->ad_dma_mode =
3727 3731 aidp->ai_ultradma;
3728 3732 } else if (aidp->ai_dworddma &
3729 3733 ATAC_MDMA_SEL_MASK) {
3730 3734 ata_drvp->ad_dma_cap =
3731 3735 ATA_DMA_MWORDMODE;
3732 3736 ata_drvp->ad_dma_mode =
3733 3737 aidp->ai_dworddma;
3734 3738 }
3735 3739 }
3736 3740 if (ata_drive_type(ata_drvp->ad_drive_bits,
3737 3741 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1,
3738 3742 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2,
3739 3743 &id) != ATA_DEV_DISK)
3740 3744 continue;
3741 3745 (void) ata_flush_cache(ata_ctlp, ata_drvp);
3742 3746 if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE,
3743 3747 5 * 1000000, cmd, 0, 0, 0, 0, 0, 0)) {
3744 3748 cmn_err(CE_WARN, "!ata_controller - Can not "
3745 3749 "put drive %d in to power mode %u",
3746 3750 targ, cmd);
3747 3751 (void) ata_devo_reset(dip, DDI_RESET_FORCE);
3748 3752 return (DDI_FAILURE);
3749 3753 }
3750 3754 }
3751 3755 return (DDI_SUCCESS);
3752 3756 }
3753 3757
3754 3758 (void) ata_software_reset(ata_ctlp);
3755 3759 for (targ = 0; targ < ATA_MAXTARG; targ++) {
3756 3760 ata_drvp = CTL2DRV(ata_ctlp, targ, 0);
3757 3761 if (ata_drvp == NULL)
3758 3762 continue;
3759 3763 ata_resume_drive(ata_drvp);
3760 3764
3761 3765 if (ATAPIDRV(ata_drvp))
3762 3766 lastlun = ata_drvp->ad_id.ai_lastlun;
3763 3767 else
3764 3768 lastlun = 0;
3765 3769 if (!ata_enable_atapi_luns)
3766 3770 lastlun = 0;
3767 3771 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) {
3768 3772 ata_drvp = CTL2DRV(ata_ctlp, targ, lun);
3769 3773 if (ata_drvp != NULL)
3770 3774 ata_resume_drive(ata_drvp);
3771 3775 }
3772 3776 }
3773 3777
3774 3778 return (DDI_SUCCESS);
3775 3779 }
3776 3780
3777 3781 /*
3778 3782 * return 1 when ata controller is a pci device,
3779 3783 * otherwise return 0
3780 3784 */
3781 3785 static int
3782 3786 ata_is_pci(dev_info_t *dip)
3783 3787 {
3784 3788 int rc;
3785 3789 char *bufp;
3786 3790 int ispci;
3787 3791
3788 3792 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip),
3789 3793 DDI_PROP_DONTPASS, "device_type", &bufp);
3790 3794
3791 3795 if (rc != DDI_PROP_SUCCESS) {
3792 3796 ADBG_ERROR(("ata_is_pci !device_type\n"));
3793 3797 return (0);
3794 3798 }
3795 3799
3796 3800 ispci = (strcmp(bufp, "pci-ide") == 0);
3797 3801
3798 3802 ddi_prop_free(bufp);
3799 3803
3800 3804 return (ispci);
3801 3805 }
3802 3806
3803 3807 /*
3804 3808 * Disable DMA for this drive
3805 3809 */
3806 3810 static void
3807 3811 ata_disable_DMA(ata_drv_t *ata_drvp)
3808 3812 {
3809 3813 struct ata_id *aidp;
3810 3814 char buf[sizeof (aidp->ai_model) +2];
3811 3815 int i;
3812 3816
3813 3817 if (ata_drvp == NULL)
3814 3818 return;
3815 3819
3816 3820 if (ata_drvp->ad_pciide_dma == ATA_DMA_OFF)
3817 3821 return;
3818 3822
3819 3823 ata_drvp->ad_pciide_dma = ATA_DMA_OFF;
3820 3824
3821 3825 /* Print the message */
3822 3826 buf[0] = '\0';
3823 3827 aidp = &ata_drvp->ad_id;
3824 3828 if (aidp != NULL) {
3825 3829 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model));
3826 3830 buf[sizeof (aidp->ai_model) -1] = '\0';
3827 3831 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--)
3828 3832 buf[i] = '\0';
3829 3833 }
3830 3834 cmn_err(CE_CONT,
3831 3835 "?DMA disabled on %s target=%d, lun=%d due to DMA errors,",
3832 3836 buf, ata_drvp->ad_targ, ata_drvp->ad_lun);
3833 3837 cmn_err(CE_CONT, "?most likely due to the CF-to-IDE adapter.");
3834 3838 }
3835 3839
3836 3840 /*
3837 3841 * Check and select DMA mode
3838 3842 *
3839 3843 * TRUE is returned when set feature is called successfully,
3840 3844 * otherwise return FALSE
3841 3845 */
3842 3846 int
3843 3847 ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp)
3844 3848 {
3845 3849 struct ata_id *aidp;
3846 3850 int mode, rval = FALSE;
3847 3851 uint8_t subcmd;
3848 3852
3849 3853 aidp = &ata_drvp->ad_id;
3850 3854
3851 3855 /* Return directly if DMA is not supported */
3852 3856 if (!(aidp->ai_cap & ATAC_DMA_SUPPORT))
3853 3857 return (rval);
3854 3858
3855 3859 /* Return if DMA mode is already selected */
3856 3860 if (((aidp->ai_validinfo & ATAC_VALIDINFO_83) &&
3857 3861 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) ||
3858 3862 (aidp->ai_dworddma & ATAC_MDMA_SEL_MASK))
3859 3863 return (rval);
3860 3864
3861 3865 /* First check Ultra DMA mode if no DMA is selected */
3862 3866 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) &&
3863 3867 (aidp->ai_ultradma & ATAC_UDMA_SUP_MASK)) {
3864 3868 for (mode = 6; mode >= 0; --mode) {
3865 3869 if (aidp->ai_ultradma & (1 << mode))
3866 3870 break;
3867 3871 }
3868 3872 subcmd = ATF_XFRMOD_UDMA;
3869 3873
3870 3874 } else if (aidp->ai_dworddma & ATAC_MDMA_SUP_MASK) {
3871 3875 /* Then check multi-word DMA mode */
3872 3876 for (mode = 2; mode >= 0; --mode) {
3873 3877 if (aidp->ai_dworddma & (1 << mode))
3874 3878 break;
3875 3879 }
3876 3880 subcmd = ATF_XFRMOD_MDMA;
3877 3881
3878 3882 } else {
3879 3883 return (rval);
3880 3884 }
3881 3885
3882 3886 rval = ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD,
3883 3887 subcmd|mode);
3884 3888
3885 3889 return (rval);
3886 3890 }
3887 3891
3888 3892 /*
3889 3893 * Reset Ultra DMA mode / MWDMA mode
3890 3894 */
3891 3895 void
3892 3896 ata_reset_dma_mode(ata_drv_t *ata_drvp)
3893 3897 {
3894 3898 uint8_t subcmd;
3895 3899 int mode;
3896 3900 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp;
3897 3901
3898 3902 switch (ata_drvp->ad_dma_cap) {
3899 3903 case ATA_DMA_ULTRAMODE:
3900 3904 subcmd = ATF_XFRMOD_UDMA;
3901 3905 for (mode = 0; mode <= 6; mode++) {
3902 3906 if (ata_drvp->ad_dma_mode & (1 << (mode + 8)))
3903 3907 break;
3904 3908 }
3905 3909 break;
3906 3910 case ATA_DMA_MWORDMODE:
3907 3911 subcmd = ATF_XFRMOD_MDMA;
3908 3912 mode = ((ata_drvp->ad_dma_mode & ATAC_MDMA_2_SEL) ==
3909 3913 ATAC_MDMA_2_SEL ? 2 :
3910 3914 (ata_drvp->ad_dma_mode & ATAC_MDMA_1_SEL) ==
3911 3915 ATAC_MDMA_1_SEL ? 1 : 0);
3912 3916 break;
3913 3917 default:
3914 3918 return;
3915 3919 }
3916 3920
3917 3921 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD,
3918 3922 (subcmd | mode));
3919 3923 }
3920 3924
3921 3925 /*
3922 3926 * Check DMA mode is the same with saved info
3923 3927 * return value: 0 - not same
3924 3928 * 1 - same
3925 3929 */
3926 3930 static int
3927 3931 ata_check_dma_mode(ata_drv_t *ata_drvp)
3928 3932 {
3929 3933 struct ata_id *aidp;
3930 3934
3931 3935 aidp = &ata_drvp->ad_id;
3932 3936 switch (ata_drvp->ad_dma_cap) {
3933 3937 case ATA_DMA_ULTRAMODE:
3934 3938 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) &&
3935 3939 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK) &&
3936 3940 (aidp->ai_ultradma == ata_drvp->ad_dma_mode))
3937 3941 break;
3938 3942 else
3939 3943 return (0);
3940 3944 case ATA_DMA_MWORDMODE:
3941 3945 if ((aidp->ai_dworddma & ATAC_MDMA_SEL_MASK) &&
3942 3946 (aidp->ai_dworddma == ata_drvp->ad_dma_mode))
3943 3947 break;
3944 3948 else
3945 3949 return (0);
3946 3950 default:
3947 3951 return (0);
3948 3952 }
3949 3953 return (1);
3950 3954 }
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